FUJITSU SEMICONDUCTOR DATA SHEET DS04-31102-1E ASSP for Graphics Control Graphics Display Controller MB86291A ■ DESCRIPTION The MB86291A is an evolved version of the Fujitsu MB86290A graphics controller designed for use in a car navigation system or amusement equipment. The MB86291A is a graphics display controller with a geometry processor, digital video capture facility, and on-chip SDRAM. Embedding SDRAM implements data transfer at a higher bandwidth, resulting in faster drawing. Integrating the geometry processor reduces the CPU load, thereby improving the performance of the entire system. ■ FEATUERS • Operating frequency : 100 MHz (External clock of 14.32 MHz Max) • Geometry processor: Capable of executing operations for geometric transformation and surface front/rear evaluation. • Memory block: Embedded 16-Mbit SDRAM • Video capture block: Embedded facility to capture digital video images, for example, from TV, capable of easily implementing “Picture in Picture” and video graphics superimposing. • Host interface: Enables direct connection to various CPUs (Fujitsu SparcLite, Hitachi SH3/4 or NEC V83x) . (Continued) ■ PACKAGE 208-pin plastic QFP (FPT-208P-M04) MB86291A (Continued) • Drawing features: • Drawing at a peak rate of 800 Mpixels per second (at an internal operating frequency of 100 MHz) • 2D drawing functions: Point, line, triangle, polygon, BLT, and pattern drawing • 3D drawing functions: Point, line, and triangle drawing, and hidden surface removal by Z-buffering • Special effects: Anti-aliasing, bold/dashed-line processing, alpha blending, Gouraud shading, texture mapping (bilinear filtering, perspective correct) , and tiling • Display features : • Maximum display resolution supported : 1024×768 pixels • Color display either with a color palette of 8 bits per pixel or directly using 5-bit RGB colors of 16 bits per pixel • Overlaying four layers of screen, of which two lower layers can be divided into the left and right parts • Supporting two 64×64-pixel hardware cursors • Output of analog RGB and digital RGB signals • Capable of superimposing using an external synchronization mode • Power-supply voltage : Two power supplies at 2.5 V±0.2 V for internal circuits and SDRAM, and 3.3 V±0.2 V for I/O parts • Package: Plastic QFP with 208 pins (with a lead pitch of 0.5 mm) • Process technology : 0.25 µm CMOS 2 MB86291A ■ PIN ASSIGNMENT 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 VSS GV HSYNC VSYNC CSYNC VSS DCLKO VDDE VI7 VI6 VI5 VI4 VI3 VI2 VI1 VI0 VDDI VSS DCLKI EO RESERVE RESERVE RESERVE RESERVE RESERVE TESTH5 CCLK VDDE VSS A24 A23 A22 A21 A20 A19 A18 A17 A16 VDDI VSS A15 A14 A13 A12 A11 A10 A9 A8 TESTL1 VDDE VDDI VSS (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 ACOMPR VREF VRO AVD3 AOUTR AVS3 AVS2 AVD2 AVS1 AOUTG AVD1 ACOMPG AVS0 AOUTB AVD0 ACOMPB VSS VDDI A7 A6 A5 A4 A3 A2 VDDI VSS PLLVSS S OSCOUT PLLVDD VDDE VSS CLK OSCCNT VSS VDDI WE3 WE2 WE1 WE0 RD BS CS BCLKI VDDI VSS VDDE OPEN DTACK/TC DRACK/DMAAK CKM TESTH4 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 TESTH0 VSS VDDI D0 D1 D2 D3 D4 D5 D6 D7 VDDE VSS D8 D9 D10 D11 D12 D13 D14 VDDI VSS D15 D16 D17 D18 VDDE D19 D20 D21 D22 D23 D24 VSS VDDI D25 D26 D27 D28 D29 VSS VDDE D30 D31 RDY DREQ INT VSS VDDI TESTH1 TESTH2 TESTH3 VSS VCC0 R0 R1 VCC1 VSS R2 R3 R4 R5 R6 R7 VCC2 VDDE VSS VCC3 VDDI G0 G1 G2 G3 VSS G4 G5 G6 G7 VDDE B0 B1 B2 B3 VSS B4 B5 B6 B7 VCC4 VDDI VSS VCC5 VDDE CLKSEL0 CLKSEL1 RESET MODE0 MODE1 VSS VCC6 MODE2 TESTL0 VCC7 VSS : Ground VSS/AVS/PLLVSS : 3.3 V power supply VDDH/VDDE VDDL/AVD/PLLVDD/VCC/VDDI : 2.5 V power supply : Analog power supply AVD : PLL power supply PLLVDD : Internal DRAM power supply VCC : Do not connect anything. OPEN : Input the low level. TESTL0/TESTL1 : Input the high level. TESTH0 ~ TESTH5 : Input the high level. RESERVE Notes : • The AVD and PLLVDD should be separated on the board. • Insert a bypass capacitor with a superior high-frequency characteristic between the power supply and ground. Place the capacitor as near the pins as possible. 3 MB86291A ■ PIN DESCRIPTION D0-D31 DCLKO A2-A24 DCLKI AOUTR, AOUTG, AOUTB HSYNC BCLKI RESET Host CPU interface CS VSYNC RD CSYNC WE0-WE3 EO RDY GV BS DREQ MB86291A Graphics Controller DRACK DTACK INT MODE0MODE2 TESTL, TESTH HQFP208 VREF VRO ACOMPR, ACOMPG, ACOMPB R0-R7 G0-G7 B0-B7 CCLK CLK S Clock CKM CLKSEL0CLKSEL1 OSCOUT OSCCNT 4 Vide output interface VI0-VI7 Vide capture interface MB86291A • Host Interface Pins Pin Name Input/output Function MODE0 to MODE2 Input Host CPU mode/Ready mode select RESET Input Hardware reset D0 to D31 Input/output A2 to A24 Input Host CPU bus address (Connect A[24] to MWR in V832 mode.) BCLKI Input Host CPU bus clock BS Input Bus cycle start signal CS Input Chip select signal RD Input Read strobe signal WE0 Input D0 to D7 write strobe signal WE1 Input D8 to D15 write strobe signal WE2 Input D16 to D23 write strobe signal WE3 Input D24 to D31 write strobe signal RDY Output Tristate Wait request signal (“0” for wait state with SH3; “1” for wait state with SH4, V832, or SPARClite) DREQ Output DMA request signal (active low with both SH and V832) DRACK/DMAAK Input DMA request acknowledge signal (Connect this to DMAAK in V832 mode. Active high with both SH and V832.) DTACK/TC Input DMA transfer strobe signal (Connect this to TC in V832 mode. SH = active high, V832 = active low) INT Output TEST0, TEST1, TESTH0 to TESTH5 Input Host CPU bus data Host CPU interrupt signal (SH = active low, V832 = active high) Test signal Note : The host interface can connect the MB86291A to the SH4 (SH7750) or SH3 (SH7709) from Hitachi Ltd. the V832 from NEC, or to the SPARClite (MB86833) from Fujitsu without any external circuit in between. (Using the SRAM interface allows the MB86291A to use another CPU.) The host CPU is set by the MODE0 and MODE1 pins as shown below. MODE1 pin MODE0 pin CPU Type L L SH3 L H SH4 H L V832 H H SPARClite Note : The MODE2 pin can be used to set the Ready signal level to be used upon completion of the bus cycle. To use the MODE2 signal at "H" level, set the software setting to two cycles. MODE2 pin Ready signal mode L Set RDY signal to "Not Ready" level upon completion of bus cycle. H Set RDY signal to "Ready" level upon completion of bus cycle. 5 MB86291A Notes : • The host interface transfers data signals at a fixed width of 32 bits. • There are 23 lines for address signals handled in double words ( = 32 bits) and 32 Mbytes of address space. • The external bus can be used at an operating frequency of 100 MHz maximum. • The RDY signal at the low level sets the ready state in the SH4 or V832 mode; the signal at the low level sets the wait state in the SH3 mode. Note that the RDY signal is a tristate output. • The host interface supports DMA transfer using an external DMA controller. • The host interface generates a host processor interrupt signal. • The RESET pin requires low level input of at least 300 µs after setting “S” (PLL reset signal) to high level. • Fix the TEST signal at high level. • In the V832 mode, connect the following pins as specified : SCARLET Pin Name V832 Signal Name A24 MWR DTACK TC DRACK DMAAK • Vide Output Interface Pin Name Input/output Function DCLKO Output Display dot clock signal output DCLKI Input HSYNC Input/output Horizontal sync signal output Horizontal sync signal input in external synchronization mode VSYNC Input/output Vertical sync signal output Vertical sync signal input in external synchronization mode CSYNC Output EO Input GV Output Graphics/video select signal R0-R7 Output Digital video (R) signal output G0-G7 Output Digital video (G) signal output B0-B7 Output Digital video (B) signal output Dot clock signal input Composite sync signal output Even/odd-number field identification input AOUTR Analog output Analog video (R) signal output AOUTG Analog output Analog video (G) signal output AOUTB Analog output Analog video (B) signal output VREF Analog Reference voltage input pin ACOMPR Analog R-signal compensation pin ACOMPG Analog G-signal compensation pin ACOMPB Analog B-signal compensation pin VRO Analog Reference current setting pin Notes : • The video output interface contains an 8-bit D/A converter to output analog RGB signals. Also, the eight-bit RGB digital output pins can connect an external digital video encoder. • Using an additional external circuit, the video output interface can generate composite video signals. • The video output interface can provide display synchronized with external video. The mode for synchronization with the DCLKI signal can be selected as well as the mode for synchronization with a set dot clock as for normal display. 6 MB86291A • The HSYNC and VSYNC signals must be pulled up outside the LSI as they enter the input state upon reset. • Terminate the AOUTR, AOUTG, and AOUTB pins with a resistance of 75 Ω. • Input 1.1 V to the VREF pin. Between this pin and analog ground, insert a bypass capacitor (one with a superior high-frequency characteristic such as a laminated ceramic capacitor). • Connect the ACOMPR, ACOMPG, and ACOMPB pins to the 0.1 µF ceramic capacitor ahead of the analog power supply. • Connect the VRO pin to the analog ground with a 2.7 kΩ resistor. • For noninterlaced display in external synchronization mode, input "0" to the EO pin, for example, using a pull-down resistor. • The GV signal serves to switch between graphics and video for chroma keying. The pin outputs a low level signal to select video. 7 MB86291A • Video Capture Interface Pin Name Input/output Function CCLK Input Digital video input clock signal input VI0-VI7 Input Digital video data input Note : The video capture interface inputs digital video signals in the ITU-RBT-656 format. • Clock Input Pin Name Input/output Function CLK Input Clock input signal S Input PLL reset signal CKM Input Clock mode signal Input Clock rate select signal CLKSEL1, CLKSEL0 1 Input/output 2 Input OSCOUT* OSCCNT* For connection of crystal oscillator (Reserved) For selection of crystal oscillator (Reserved) *1 : Do not connect anything. *2 : Input the “H” level. Notes : • The clock input block inputs the clock signal that serves as the basis for the reference clock for the internal operating clock and display dot clock. Usually input 4 Fsc ( = 14.31818 MHz) . The internal PLL generates the internal operating clock signal of 100 MHz and the display reference clock signal of 200 MHz. • The internal operating clock signal to be used can be selected between the clock signal (100 MHz) generated by the internal PLL and the bus clock BCLKI input to the host CPU interface. Select the BCLKI input to use the host CPU bus at 100 MHz. CKM Clock Mode L Select internal PLL output. H Select host CPU bus clock (BCLKI) Note : Use the CLKSEL pin to select the input clock frequency for using the internal PLL with CKM = L. CLKSEL1 CLKSEL0 Clock Frequency L L Input 13.5 MHz. L H Input 14.32 MHz. H L Input 17.73 MHz. H H Reserved Note : Immediately after turning the power supply on, input a pulse whose low level period is 500 ns or more to the S pin before setting it to high level. After the S signal goes high, input the RESET signal at low level for 300 µs or more 8 MB86291A ■ BLOCK DIAGRAM D0-D31 External Video Interface Controller Host Interface RBT656 A2-A24 Display Controller DAC Memory Interface Controller Geometry Engine DRGB ARGB 2D/3D Rendering Engine Embedded SDRAM 9 MB86291A ■ FUNCTION BLOCKS • Host Interfacee This block allows the MB86291A to be connected to the SH3 or SH4 microprocessor from Hitachi Ltd., the V83x microprocessor from NEC, or to the SPARCLite from Fujitsu without any external circuit in between. The block provides an interface to transfer display list and texture pattern data directly from main memory to this device’s graphics memory or internal register using the external DMA controller. • Memory Interface Controller and Embedded SDRAM The embedded 16-megabit SDRAM eliminates the need for external memory. The SDRAM operates at 100 MHz. • Display Controller This block contains a three-channel, eight-bit D-A converter to output analog RGB signals. The block has eightbit RGB digital video outputs, allowing an external digital video encoder to be connected. The block supports resolutions of up to XGA (1024×768 pixels), enabling flexible setting. • External Video Interface Controller This block can input digital video in the ITU RBT-656 format by connecting an external digital video decoder using the eight-bit video input pin. Input video data is stored temporarily in graphics memory and then displayed on the screen in synchronization with the display scan. The block supports video in the NTSC and PAL formats. • Set-up Engine The on-chip geometry engine executes mathematical operations required for graphics processing precisely using the fronting-point format. The geometry engine executes the required geometry processes selected depending on the drawing mode and primitive type settings up to the final drawing process. • 2D/3D Rendering Engine This block draws images in two or three dimensions. • 2D drawing The block provides the anti-aliasing and alpha blending functions to display high-quality images even on a lowresolution LCD. • 3D drawing The block provides true 3D drawing functions such as perspective texture mapping and Gouraud shading. 10 MB86291A ■ ABSOLUTE MAXIMUM RATINGS Parameter Rating Symbol Unit Min Max VDDL*1 − 0.5 + 3.0 VDDH − 0.5 + 4.0 Input voltage VI − 0.5 VDDH + 0.5 (< 4.0) V Output current IO − 13 + 13 mA IPOW 60 mA Power supply voltage Power pin current Ambient operating temperature Ambient storage temperature + 70 0 TA − 30* °C + 85*2 2 − 55 Tstg V + 125 °C *1 : The analog and PLL power supplies are included. *2 : Model supporting a wider range of temperatures WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. ■ RECOMMENDED OPERATING CONDITION Parameter Symbol Value Unit Min Typ Max VDDL*1 2.3 2.5 2.7 V VDDH 3.0 3.3 3.6 V Input voltage (High level) VIH 2.0 VDDH + 0.3 V Input voltage (Low level) VIL − 0.3 + 0.8 V VREF pin input voltage VREF 1.05 1.10 1.15 V VRO pin external resistor RVRO 2.7 kΩ RAOUT 75 Ω CACOMP 0.1 µF TA − 40 + 85 °C Power supply voltage AOUT pin external resistor*2 ACOMP pin external capacitor* 3 Ambient operating temperature *1 : The analog and PLL power supplies are included. *2 : AOUTR, AOUTG and AOUTB pins *3 : ACOMPR, ACOMPG, and ACOMPB pins 11 MB86291A Notes : • The VDDL and VDDH power supplies can be turned on or off in either order. Note, however, that the VDDH voltage must not be applied alone continuously for several seconds. • After turning the power on, input a pulse remaining at low level for at least 500 ns to the S pin. Then, set the S pin to high level and input the RESET signal held at low level for at least 300 µs. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 12 MB86291A ■ ELECTRICAL CHARACTERISTICS 1. DC Characteristics Parameter VDDL = 2.5 V ± 0.2 V, VDDH = 3.3 V ± 0.3, VSS = 0.0 V, TA = 0 °C to + 70 °C Value Symbol Unit Min Typ Max Output voltage (High level) *1 VOH VDDH − 0.2 VDDH V Output voltage (Low level) *2 VOL 0.0 0.2 V OHM 4 − 4.0 OHH 3 − 8.0 mA IOLM*4 4.0 IOLH*3 8.0 mA 9.90 10.42 10.94 mA 0 2 20 µA VAOUT − 0.1 + 1.1 V Input leakage current IL ±5 µA Pin capacitance C 16 pF Output current (High level) Output current (Low level) AOUT output current*5 Full scale Zero scale AOUT voltage*6 I * I * IAOUT *1 : Value when −100 µA current flows into output pins. *2 : Value when 100 µA current flows into output pins. *3 : Output characteristics of INT, DREQ, and RDY *4 : Output characteristics of the signals (excluding analog signals) other than those in *3 *5 : AOUTR, AOUTG, and AOUTB pin output current. Condition VREF = 1.10 V, RVRO = 2.7 kΩ (The full-scale output current calculation expression is (VREF / RVRO) × 25.575) *6 : AOUTR, AOUTG, and AOUTB pins 13 MB86291A 2. AC Characteristics (VIH = 2.0 V, VIL = 0.8 V) • Input measurement conditions tf tr VIH 80% Input 80% (VIH + VIL) / 2 20% 20% VIL •tr, tf ≤ 5 ns •Input measurement standard : (VIH + VIL) / 2 • Output measurement conditions VIH Input (VIH + VIL) /2 VIL tpHL, tpZL tpLH, tpZH VOH Output 1 VDD/2 VDD/2 VOL tpLZ Output 2 0.5 V VOL tpHZ VOH Output 3 •Output measurement standard : tpLZ : VOL + 0.5 V tpHZ : VOH − 0.5 V Else : VDD/2 14 0.5 V MB86291A (1) Host Interface • Clock signals Value Symbol Condition Min Typ Max BCLKI frequency fBCLKI 100 MHz BCLKI H period tHBCLKI 1 ns BCLKI L period tLBCLKI 1 ns Parameter Unit • Host interface signals (External load of 20 pF) Value Symbol Condition Min Typ Max Address setup time tADS 4 ns Address hold time tADH 0 ns BS setup time tBSS 3 ns BS hold time tBSH 0 ns CS setup time tCSS 3 ns CS hold time tCSH 0 ns RD setup time tRDS 3 ns RD hold time tRDH 0 ns WE setup time tWES 5 ns WE hold time tWEH 1 ns Write data setup time tWDS 3 ns Write data hold time tWDH 0 ns DTACK setup time tDAKS 3 ns DTACK hold time tDAKH 0 ns DRACK setup time tDRKS 3 ns DRACK hold time tDRKH 0 ns Read data delay time (to RD) tRDDZ 3.0 11.0 ns Read data delay time tRDD *2 4.5 10.5 ns RDY delay time (to CS) tRDYDZ 2.5 5.0 ns RDY delay time tRDYD 2.5 6.0 ns INT delay time tINTD 3.0 6.5 ns DREQ delay time tDRQD 2.5 6.0 ns MODE hold time tMODH *1 20.0 ns Parameter Unit *1 : Hold time for reset cancellation *2 : Read data is output one cycle before the CPU samples it. 15 MB86291A • Clock 1/fBCLKI tHBCLKI tLBCLKI BCLKI • Input setup and hold times BCLKI A2~A24, BS, CS, DTACK, DRACK tADS, tBSS, tCSS, tDAKS, tDRKS tADH, tBSH, tCSH, tDAKH, tDRKH • Read/write enable (RD, WE) and input data (D) setup times BCLKI BS RD, WE D0~D31 16 tRDS, tWES tWDS tRDH, tWEH tWDH MB86291A • DREQ output delay time BCLKI DREQ (output) tDRQD • INT output delay time BCLKI INT (output) tINTD • RDY delay value (with respect to CS) BCLKI CS High-Z High-Z RDY (output) tRDYDZ tRDYDZ 17 MB86291A • RDY/D output delay values BCLKI RD tRDD tRDDZ High-Z Output data D0~D31 (output) RDY tRDYD tRDYD • MODE signal hold time RESET MODE0~ MODE2 tMODH 18 MB86291A (2) Video Interface • Clock Value Symbol Condition Min Typ Max CLK frequency fCLK 14.32 MHz CLK H period tHCLK 25 ns CLK L period tLCLK 25 ns DCLKI frequency fDCLKI 67 MHz DCLKI H period tHDCLKI 5 ns DCLKI L period tLDCLKI 5 ns DCLKO frequency fDCLKO 67 MHz Symbol Condition Min Typ Max tWHSYNC0 *1 3 clock tWHSYNC1 *2 3 clock HSYNC input setup time tSHSYNC *2 10 ns HSYNC input hold time tHHSYNC *2 10 ns VSYNC input pulse width tWHSYNC1 1 HSYNC 1 cycle EO input setup time tSEO *3 10 ns EO input hold time tHEO *3 10 ns Parameter unit • Input signals Parameter HSYNC input pulse width Value unit *1 : Applied only in PLL synchronization mode (CKS = 0) . The reference clock is the internal PLL’s output with Cycle = 1/ (14 fCLK) . *2 : Applied only in DCLKI synchronization mode (CKS = 1) . The reference clock is DCLKI. *3 : Based on the edge with VSYNC negated. • Output signals Value Symbol Condition Min Typ Max tDEO * 1.5 11 ns HSYNC output delay time tDHSYNC 1.5 11 ns VSYNC output delay time tDVSYNC 1.5 11 ns CSYNC output delay time tDCSYNC 1.5 11 ns tDGV 1.5 11 ns Parameter EO output delay time GV output delay time unit * : The EO output varies at the same time as VSYNC is asserted. 19 MB86291A • Clock 1/fCLK tHCLK tLCLK CLK VIH VIL • HSYNC signal setup and hold 1/fDCLKI tHDCLKI tLDCLKI DCLKI HSYNC (input) tSHSYNC tHHSYNC • EO signal setup and hold VSYNC EO (input) tSEO tHEO • Output signal delay DCLKO EO (output) HSYNC (output) VSYNC (output) CSYNC GV tDEO, tDHSYNC, tDVSYNC, tDCSYNC, tDGV 20 MB86291A (3) Video Capture Interface • Clock Value Symbol Condition Min Typ Max CCLKI frequency fCCLKI 27 MHz CCLKI H period tHCCLKI 1 ns CCLKI L period tLCCLKI 1 ns Parameter unit • Input signals Value Symbol Condition Min Typ Max VI setup time (External load of 25 pF) tVIS 11 ns VI hold time (External load of 15 pF) tVIH 2 ns Parameter unit • Clock 1/fCLK tHCLK CLK tLCLK VIH VIL • Video input CCLKI VI0~VI7 tVIS tVIH 21 MB86291A (4) PLL Standards Parameter 22 Value Unit Remarks Min Typ Max Input frequency 14.31818 MHz Output frequency 200.45452 MHz Duty ratio 93.1 101.3 % PLL output clock H/L pulse width ratio Jitter − 150 + 180 ps Cycle difference between two consecutive cycles Multiplied by 14 MB86291A ■ ORDERING INFORMATION Part Number MB86291APFVS Package Remarks 208-pin plastic QFP (FPT-208P-M04) 23 MB86291A ■ PACKAGE DIMENSION 208-pin plastic QFP (FPT-208P-M04) Note : Pins width and pins thickness include plating thickness. 30.60±0.20(1.205±.008)SQ 28.00±0.10(1.102±.004)SQ +0.03 0.17 –0.08 156 +.001 .007 –.003 105 157 104 0.08(.003) Details of "A" part +0.20 3.75 –0.30 +.008 .148 –.012 (Mounting height) +0.10 0.40 –0.15 +.004 INDEX 0°~8° 208 LEAD No. 53 1 52 0.50(.020) C 0.22±0.05 (.009±.002) 0.08(.003) "A" 0.50±0.20 (.020±.008) 0.60±0.15 (.024±.006) .016 –.006 (Stand off) 0.25(.010) M 2000 FUJITSU LIMITED F208020S-c-2-3 Dimension in mm (inches) 24 MB86291A FUJITSU LIMITED For further information please contact: Japan FUJITSU LIMITED Marketing Division Electronic Devices Shinjuku Dai-Ichi Seimei Bldg. 7-1, Nishishinjuku 2-chome, Shinjuku-ku, Tokyo 163-0721, Japan Tel: +81-3-5322-3353 Fax: +81-3-5322-3386 http://edevice.fujitsu.com/ North and South America FUJITSU MICROELECTRONICS AMERICA, INC. 3545 North First Street, San Jose, CA 95134-1804, U.S.A. Tel: +1-408-922-9000 Fax: +1-408-922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: +1-800-866-8608 Fax: +1-408-922-9179 http://www.fma.fujitsu.com/ Europe FUJITSU MICROELECTRONICS EUROPE GmbH Am Siebenstein 6-10, D-63303 Dreieich-Buchschlag, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://www.fme.fujitsu.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LTD. #05-08, 151 Lorong Chuan, New Tech Park, Singapore 556741 Tel: +65-281-0770 Fax: +65-281-0220 http://www.fmal.fujitsu.com/ Korea FUJITSU MICROELECTRONICS KOREA LTD. 1702 KOSMO TOWER, 1002 Daechi-Dong, Kangnam-Gu,Seoul 135-280 Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111 F0203 FUJITSU LIMITED Printed in Japan All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. 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