FUJITSU SEMICONDUCTOR DATA SHEET DS04-29115-2E Spread Spectrum Clock Generator MB88154 ■ DESCRIPTION MB88154 is a clock generator for EMI (Electro Magnetic Interference) reduction. The peak of unnecessary radiation noise (EMI) can be attenuated by making the oscillation frequency slightly modulate periodically with the internal modulator. It corresponds to both of the center spread which modulates input frequency as Middle Centered and down spread which modulates so as not to exceed input frequency. ■ FEATURE • Input frequency : 16.6 MHz to 67 MHz • Output frequency: 16.6 MHz to 67 MHz (One time input frequency) • Modulation rate can select from ± 0.5%, ± 1.0%, ± 1.5% or − 1.0%, − 2.0%, − 3.0%. (For center spread / down spread.) • Equipped with crystal oscillation circuit: Range of oscillation 16.6 M MHz to 48 MHz • The external clock can be input: 16.6 MHz to 67 MHz • Modulation clock output Duty : 40% to 60% • Modulation clock Cycle-Cycle Jitter : Less than 100 ps • Low current consumption by CMOS process : 5.0 mA (24 MHz : Typ-sample, no load) • Power supply voltage : 3.3 V ± 0.3 V • Operating temperature : − 40 °C to +85 °C • Package : SOP 8-pin ■ PACKAGE 8-pin plastic SOP (FPT-8P-M02) MB88154 ■ PRODUCT LINEUP MB88154 has two kinds of input frequency, and two kinds of modulation type (center/down spread), total four lineups. Product Input/Output frequency Modulation type MB88154-102 33 MHz to 67 MHz MB88154-103 16.6 MHz to 40 MHz MB88154-112 33 MHz to 67 MHz MB88154-113 16.6 MHz to 40 MHz Down Center ■ PIN ASSIGNMENT TOP VIEW CKOUT 1 8 SEL1 VDD 2 7 REFOUT MB88154 VSS 3 6 SEL0 XIN 4 5 XOUT FPT-8P-M02 ■ PIN DESCRIPTION 2 Pin name I/O Pin no. Description CKOUT O 1 Modulated clock output pin VDD ⎯ 2 Power supply voltage pin VSS ⎯ 3 GND pin XIN I 4 Crystal resonator connection pin/clock input pin XOUT O 5 Crystal resonator connection pin SEL0 I 6 Modulation rate setting pin REFOUT O 7 Non-modulated clock output pin SEL1 I 8 Modulation rate setting pin MB88154 ■ I/O CIRCUIT TYPE Pin Circuit type Remarks • CMOS hysteresis input SEL0 SEL1 • CMOS output • IOL = 3 mA CKOUT REFOUT Note : For XIN and XOUT pins, see “■OSCILLATION CIRCUIT” 3 MB88154 ■ HANDLING DEVICES Preventing Latchup A latchup can occur if, on this device, (a) a voltage higher than VDD or a voltage lower than VSS is applied to an input or output pin or (b) a voltage higher than the rating is applied between VDD and VSS. The latchup, if it occurs, significantly increases the power supply current and may cause thermal destruction of an element. When you use this device, be very careful not to exceed the maximum rating. Handling unused pins Do not leave an unused input pin open, since it may cause a malfunction. Handle by, using a pull-up or pull-down resistor. Unused output pin should be opened. The attention when the external clock is used Input the clock to XIN pin, and XOUT pin should be opened when you use the external clock. Please pay attention so that an overshoot and an undershoot do not occur to an input clock of XIN pin. Power supply pins Please design connecting the power supply pin of this device by as low impedance as possible from the current supply source. We recommend connecting electrolytic capacitor (about 10 µF) and the ceramic capacitor (about 0.01 µF) in parallel between VSS and VDD near the device, as a bypass capacitor. Oscillation circuit Noise near the XIN and XOUT pins may cause the device to malfunction. Design printed circuit boards so that electric wiring of XIN or XOUT pin and the resonator do not intersect other wiring. Design the printed circuit board that surrounds the XIN and XOUT pins with ground. 4 MB88154 ■ BLOCK DIAGRAM VDD SEL1 CKOUT Modulation rate setting Clock output SEL0 PLL block Reference clock XOUT Reference clock output REFOUT XIN Rf = 1 MΩ VSS 1 − M Phase compare Reference clock 1 − N Charge pump V/I conversion IDAC Modulation Clock output Loop filter 1 − L ICO Modulation logic Modulation rate setting Modulation enable setting MB88154 PLL block A glitchless IDAC (current output D/A converter) provides precise modulation, thereby dramatically reducing EMI. 5 MB88154 ■ PIN SETTING SEL 0, SEL 1 Modulation rate setting modulation rate SEL1 Notes : SEL0 MB88154-102, MB88154-103 MB88154-112, MB88154-113 Down spread Center spread L L − 1.0% ± 0.5% L H − 2.0% ± 1.0% H L − 3.0% ± 1.5% H H No spread No spread • The modulation rate can be changed at the level of the pin. Spectrum does not spread when “H” level is set to SEL0 and SEL1 pin. The clock with low jitter can be obtained. • When changing the modulation rate setting, the stabilization wait time for the modulation clock is required. The stabilization wait time for the modulation clock take the maximum value of “■ ELECTRICAL CHARACTERISTICS • AC Characteristics Lock-Up time”. • Center spread Spectrum is spread (modulated) by centering on the input frequency. Modulation width 3.0% Radiation level −1.5% +1.5% Frequency Input frequency Modulation rate center spread example of ± 1.5% • Down spread Spectrum is spread (modulated) below the input frequency. Modulation width 3.0% Radiation level −3.0% Frequency Frequency in modulation off Modulation width down spread example of − 3.0% 6 MB88154 ■ ABSOLUTE MAXIMUM RATINGS Parameter Rating Symbol Unit Min Max VDD − 0.5 + 4.0 V Input voltage* VI VSS − 0.5 VDD + 0.5 V Output voltage* VO VSS − 0.5 VDD + 0.5 V Storage temperature TST − 55 + 125 °C Operation junction temperature TJ − 40 + 125 °C Output current IO − 14 + 14 mA Overshoot VIOVER ⎯ VDD + 1.0 (tOVER ≤ 50 ns) V Undershoot VIUNDER VSS − 1.0 (tUNDER ≤ 50 ns) ⎯ V Power supply voltage* * : The parameter is based on VSS = 0.0 V. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. Overshoot/Undershoot tUNDER ≤ 50 ns VIOVER ≤ VDD + 1.0 V VDD Input pin VSS tOVER ≤ 50 ns VIUNDER ≤ VSS − 1.0 V 7 MB88154 ■ RECOMMENDED OPERATING CONDITIONS (VSS = 0.0 V) Parameter Symbol Pin Conditions Power supply voltage VDD VDD “H” level input voltage VIH “L” level input voltage VIL XIN, SEL0, SEL1 Input clock duty cycle tDCI Operating temperature Ta Value Unit Min Typ Max ⎯ 3.0 3.3 3.6 V ⎯ VDD × 0.80 ⎯ VDD + 0.3 V ⎯ VSS ⎯ VDD × 0.20 V XIN 16.6 MHz to 67 MHz 40 50 60 % ⎯ ⎯ − 40 ⎯ + 85 °C WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. Input clock duty cycle (tDCI = tb/ta) ta tb XIN 8 1.5 V MB88154 ■ ELECTRICAL CHARACTERISTICS • DC Characteristics (Ta = −40 °C to + 85 °C, VDD = 3.3 V ± 0.3 V, VSS = 0.0 V) Parameter Power supply current Symbol Pin Conditions ICC VDD VOH Output voltage VOL CKOUT, REFOUT Value Unit Min Typ Max no load capacitance at 24 MHz output ⎯ 5.0 7.0 mA “H” level output IOH = − 3 mA VDD − 0.5 ⎯ VDD V “L” level output IOL = 3 mA VSS ⎯ 0.4 V Output impedance ZO CKOUT, REFOUT 16.6 MHz to 67 MHz ⎯ 70 ⎯ Ω Input capacitance CIN XIN, SEL0, SEL1 Ta = + 25 °C, VDD = VI = 0.0 V, f = 1 MHz ⎯ ⎯ 16 pF • AC Characteristics (Ta = −40 °C to + 85 °C, VDD = 3.3 V ± 0.3 V, VSS = 0.0 V) Parameter Symbol Pin Conditions Oscillation frequency fx XIN, XOUT Input frequency fin XIN Output frequency fOUT CKOUT, REFOUT Output slew rate SR CKOUT, 0.4 V to 2.4 V REFOUT load capacitance 15 pF Output clock duty cycle Modulation frequency Lock-Up time Cycle-cycle jitter Value Unit Min Typ Max Fundamental oscillation 16.6 ⎯ 40 3rd over-tone oscillation 40 ⎯ 48 MB88154-103/113 16.6 ⎯ 40 MB88154-102/112 33 ⎯ 67 MB88154-103/113 16.6 ⎯ 40 MB88154-102/112 33 ⎯ 67 0.3 ⎯ 2.0 V/ns MHz MHz MHz tDCC CKOUT 1.5 V 40 ⎯ 60 % tDCR REFOUT 1.5 V tDCI − 10* ⎯ tDCI + 10* % fMOD CKOUT ⎯ ⎯ 12.5 ⎯ kHz tLK CKOUT ⎯ ⎯ 2 5 ms CKOUT No load capacitance, Ta = +25 °C, VDD = 3.3 V, Standard deviation σ ⎯ ⎯ 100 ps tJC * : Duty of the REFOUT output is guaranteed only for the following A and B because it depends on tDCI of input clock duty. A. Resonator : When resonator is connected with XIN and XOUT and oscillates normally. B. External clock input : The input level is Full - swing (VSS − VDD). 9 MB88154 ■ OUTPUT CLOCK DUTY CYCLE (tDCC, tDCR = tb/ta) ta tb 1.5 V CKOUT, REFOUT ■ INPUT FREQUENCY (fin = 1/tin) tin 0.8 VDD XIN ■ OUTPUT SLEW RATE (SR) 2.4 V CKOUT, REFOUT 0.4 V tr tf Note : SR = (2.4−0.4) /tr, SR = (2.4−0.4) /tf ■ CYCLE-CYCLE JITTER (tJC = | tn − tn + 1 |) CKOUT tn tn+1 Note : Cycle-cycle jitter is defined the difference between a certain cycle and immediately after (or, immediately before) . 10 MB88154 ■ MODULATION WAVEFORM • ±1.5% modulation rate, Example of center spread CKOUT output frequency + 1.5 % Frequency at modulation OFF Time − 1.5 % fMOD = 12.5 kHz (Typ) • −1.0% modulation rate, Example of down spread CKOUT output frequency Frequency at modulation OFF Time − 0.5 % − 1.0 % fMOD = 12.5 kHz (Typ) 11 MB88154 ■ LOCK-UP TIME VDD 3.0 V Internal clock stabilization wait time XIN Setting pin SEL0, SEL1 VIH tLK (lock-up time ) CKOUT If the setting pin is fixed at the “H” or “L” level, the maximum time after the power is turned on until the set clock signal is output from CKOUT pin is (the stabilization wait time of input clock to XIN pin) + (the lock-up time “tLK”). For the input clock stabilization time, check the characteristics of the resonator or oscillator used. Note : When the pin setting is changed, the CKOUT pin output clock stabilization time is required. Until the output clock signal becomes stable, the output frequency, output clock duty cycle, modulation period, and cyclecycle jitter cannot be guaranteed. It is therefore advisable to perform processing such as cancelling a reset of the device at the succeeding stage after the lock-up time. 12 MB88154 ■ OSCILLATION CIRCUIT The left side of figures below shows the connection example about general resonator. The oscillation circuit has the built-in feedback resistance (1 MΩ) . The value of capacity (C1 and C2) is required adjusting to the most suitable value of an individual resonator. The right side of figures below shows the example of connecting for the 3rd over-tone resonator. The value of capacity (C1, C2 and C3) and inductance (L1) is needed adjusting to the most suitable value of an individual resonator. The most suitable value is different by individual resonator. Please refer to the resonator manufacturer which use for the most suitable value. When an external clock is used (the resonator is not used) , input the clock to XIN pin and do not connect anything with XOUT. • When using a resonator Internal LSI Rf (1 MΩ) Rf (1 MΩ) XIN Pin XOUT Pin XIN Pin XOUT Pin External LSI L1 C1 C2 C2 C1 Normal resonator C3 3rd over-tone resonator • When using an external clock LSI Internal Rf (1 MΩ) XIN Pin XOUT Pin LSI External External clock OPEN Note : Note that a jitter characteristic of an input clock may cause an affect a cycle-cycle jitter characteristic. 13 MB88154 ■ INTERCONNECTION CIRCUIT EXAMPLE SEL1 R2 1 8 7 2 MB88154 + R1 3 6 4 5 SEL0 C3 C4 ENS Xtal C1 14 C2 C1, C2 : Oscillation stabilization capacitance (see “■OSCILLATION CIRCUIT”.) C3 : Capacitor of 10 µF or higher C4 : Capacitor about 0.01 µF (connect a capacitor of good high frequency property (ex. laminated ceramic capacitor) to close to this device.) R1, R2 : Impedance matching resistor for board pattern MB88154 ■ EXAMPLE CHARACTERISTICS The condition of the examples of the characteristic is shown as follows: Input frequency = 20 MHz (Output frequency = 20 MHz : Using MB88154-113), Power - supply voltage = 3.3 V, None load capacity. Modulation rate = ± 1.5% (center spread) Spectrum analyzer HP4396B is connected with CKOUT. The result of the measurement with RBW = 1 kHz (ATT use for − 6dB). CH B Spectrum 10 dB /REF 0 dBm No modulation −6.18 dBm Avg 4 modulation ± 1.5 % −26.03 dBm RBW# 1 kHZ VBW 1 kHZ CENTER 20 MHZ ATT 6 dB SWP 2.505 s SPAN 4 MHZ 15 MB88154 ■ ORDERING INFORMATION Part number 16 Input/Output frequency Modulation type Package Remarks MB88154PNF-G-102-JNE1 MB88154PNF-G-103-JNE1 MB88154PNF-G-112-JNE1 MB88154PNF-G-113-JNE1 33 MHz to 67 MHz 16.6 MHz to 40 MHz 33 MHz to 67 MHz 16.6 MHz to 40 MHz Down Down Center Center 8-pin plastic SOP (FPT-8P-M02) MB88154PNF-G-102-JN-EFE1 MB88154PNF-G-103-JN-EFE1 MB88154PNF-G-112-JN-EFE1 MB88154PNF-G-113-JN-EFE1 33 MHz to 67 MHz 16.6 MHz to 40 MHz 33 MHz to 67 MHz 16.6 MHz to 40 MHz Down Down Center Center 8-pin plastic SOP Emboss taping (FPT-8P-M02) (EF type) MB88154PNF-G-102-JN-ERE1 MB88154PNF-G-103-JN-ERE1 MB88154PNF-G-112-JN-ERE1 MB88154PNF-G-113-JN-ERE1 33 MHz to 67 MHz 16.6 MHz to 40 MHz 33 MHz to 67 MHz 16.6 MHz to 40 MHz Down Down Center Center 8-pin plastic SOP Emboss taping (FPT-8P-M02) (ER type) MB88154 ■ PACKAGE DIMENSION Note 1) *1 : These dimensions include resin protrusion. Note 2) *2 : These dimensions do not include resin protrusion. Note 3) Pins width and pins thickness include plating thickness. Note 4) Pins width do not include tie bar cutting remainder. 8-pin plastic SOP (FPT-8P-M02) +0.25 +.010 +0.03 *1 5.05 –0.20 .199 –.008 0.22 –0.07 +.001 .009 –.003 8 5 *2 3.90±0.30 6.00±0.40 (.154±.012) (.236±.016) Details of "A" part 45˚ 1.55±0.20 (Mounting height) (.061±.008) 0.25(.010) 0.40(.016) 1 "A" 4 1.27(.050) 0.44±0.08 (.017±.003) 0.13(.005) 0~8˚ M 0.50±0.20 (.020±.008) 0.60±0.15 (.024±.006) 0.15±0.10 (.006±.004) (Stand off) 0.10(.004) C 2002 FUJITSU LIMITED F08004S-c-4-7 Dimensions in mm (inches) Note : The values in parentheses are reference values. 17 MB88154 FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party’s intellectual property right or other right by using such information. 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