FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-13729-1E
16-bit Proprietary Microcontroller
CMOS
F2MC-16LX MB90370/375 Series
MB90372/F372/F377/V370
■ DESCRIPTION
The MB90370/375 series is a line of general-purpose, 16-bit microcontrollers designed for those applications
which require high-speed real-time processing. The instruction set is designed to be optimized for controller
applications which inheriting the AT architecture of F2MC-16LX series and allow a wide range of control tasks to
be processed efficiently at high speed.
A built-in LPC interface, serial IRQ and PS/2 interface simplifies communication with host CPU and PS/2 devices
in computer system. Moreover, SMbus compliant I2C*2, comparator for battery control and A/D converter implements the smart battery control. With these features, the MB90370/375 series matches itself as keyboard controller with smart battery control.
(Continued)
■ PACKAGE
144-pin plastic LQFP
(FPT-144P-M12)
MB90370/375 Series
(Continued)
While inheriting the AT architecture of the F2MC*1 family, the instruction set for the F2MC-16LX CPU core of the
MB90370/375 series incorporates additional instructions for high-level languages, supports extended addressing
modes, and contains enhanced multiplication and division instructions as well as a substantial collection of
improved bit manipulation instructions. In addition, the MB90370 has an on-chip 32-bit accumulator which
enables processing of long-word data.
*1 : F2MC stands for FUJITSU Flexible Microcontroller and a registered trademark of FUJITSU LIMITED.
*2 : Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use, these
components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined
by Philips.
■ FEATURES
• Clock
• Embedded PLL clock multiplication circuit
• Operating clock (PLL clock) can be selected from divided-by-2 of oscillation or one to four times the oscillation
(at oscillation of 4 MHz to 16 MHz) .
• Minimum instruction execution time of 62.5 ns (at oscillation of 4 MHz, four times the PLL clock, operation at
VCC of 3.3 V)
• CPU addressing space of 16M bytes
• Internal 24-bit addressing
• Instruction set optimized for controller applications
• Rich data types (bit, byte, word, long word)
• Rich addressing mode (23 types)
• High code efficiency
• Enhanced precision calculation realized by the 32-bit accumulator
• Instruction set designed for high level language (C) and multi-task operations
• Adoption of system stack pointer
• Enhanced pointer indirect instructions
• Barrel shift instructions
• Program patch function (2 address pointer)
• Improved execution speed
• 4-byte instruction queue
• Powerful interrupt function
• Priority level programmable : 8 levels
• 32 factors of stronger interrupt function
• Automatic data transmission function independent of CPU operation
• Extended intelligent I/O service function (EI2OS)
• Maximum 16 channels
• Low-power consumption (standby) mode
• Sleep mode (mode in which CPU operating clock is stopped)
• Timebase timer mode (mode in which operations other than timebase timer and watch timer are stopped)
• Stop mode (mode in which all oscillations are stopped)
• CPU intermittent operation mode
• Watch mode
• Package
• LQFP-144 (FPT-144P-M12 : 0.4 mm pitch)
• Process
• CMOS technology
2
MB90370/375 Series
■ PRODUCT LINEUP
Part number
Parameter
MB90V370
MB90F372
MB90F377
Classification
—
ROM size
—
64K Bytes
RAM size
15.7K Bytes
6K Bytes
CPU function
I/O port
16-bit reload timer
16-bit PPG timer
Bit decoder
Flash type ROM
I/O port (N-channel) : 16
I/O port (CMOS) : 72
I/O port (CMOS with pull-up control) : 32
Total : 120
Reload timer : 4 channels
Reload mode, single-shot mode or event count mode selectable
PPG timer : 3 channels
PWM mode or single-shot mode selectable
Bit decoder : 1 channel
Parity generator : 1 channel
Selectable odd/even parity
PS/2 interface
PS/2 interface : 3 channels
4 selectable sampling clocks
LPC interface
LPC bus interface : 1 channel
Universal peripheral Interface : 4 channels
GA20 output control : for UPI channel 0 only
Data buffer array : 48 bytes
Serial IRQ controller
UART
I2C
PC Arbitration under
a paticular condition*2
Mask ROM
Number of instruction : 351
Minimum execution time : 62.5 ns / 4 MHz (PLL × 4)
Addressing mode : 23
Data bit length : 1, 8, 16 bits
Maximum memory space : 16M Bytes
Parity generator
LPC Standby (able to work
in Stop/TBT/Watch mode)
MB90372
Yes
No
Yes
No
Serial IRQ request : 6 channels
LPC clock monitor / control
With full-duplex double buffer (variable data length)
Clock asynchronized or clock synchronized transmission (with start and stop bits)
can be selectively used
I2C (SMbus compliant) : 1 channel
Support I2C bus of Philips and the SMbus proposed by Intel
Selectable packet error check
Timeout detection function
No
No
Yes
No
(Continued)
3
MB90370/375 Series
(Continued)
Part number
Parameter
Multi-address I2C
MB90V370
MB90F372
MB90F377
MB90372
Multi-address I2C (SMbus compliant) : 1 channel
Support I2C bus of Philips and the SMbus proposed by Intel
Selectable packet error check
Timeout detection function
6 addresses support
ALERT function
Bridge circuit
Three bus connection routes can be switched by I2C / multi-address I2C
Comparator
A comparator that can change the hysteresis width is contained
Battery voltage, mounting/dismounting and instantaneous interruption can be detected
Parallel and serial charging/discharging
External
interrupt
Key-on wake-up
interrupt
8/10-bit A/D
converter
8-bit D/A
converter
LCD controller/driver*3
Low-power
consumption
6 independent channels
Selectable causes : Rise/fall edge, fall edge, “L” level or “H” level
8 independent channels
Causes : “L” level
8/10-bit resolution : 12 channels
Conversion time : Less than 6.13 µs (16 MHz internal clock)
8-bit resolution : 2 channels
Up to 9 SEG × 4 COM
Without LCD
Selectable LCD output or CMOS I/O port controller/driver
Stop mode / Sleep mode / CPU intermittent operation mode / Watch mode
Process
Package
Operating voltage
Same as
MB90F372
CMOS
PGA256
LQFP-144 (FPT-144P-M12 : 0.4 mm pitch)
3.0 V to 3.6 V @ 16 MHz *1
*1 : Varies with conditions such as the operating frequency (see Section “■ ELECTRICAL CHARACTERISTICS”) ,
Assurance for the MB90V370 is given only for operation with a tool at power supply voltage of 3.0 V to 3.6 V,
an operating temperature of 0 °C to +25 °C, and an operating frequency of 1 MHz to 16 MHz.
*2 : I2C can detect the arbitration lost when another I2C starts another communication at the same time.
*3 : After reset, PF5 to PF7 serve as general purpose I/O pins in MB90F377; however, these pins serve as V1, V2
and V3 function in other products.
4
MB90370/375 Series
■ PACKAGE AND CORRESPONDING PRODUCTS
Package
MB90V370
PGA256
FPT-144P-M12
MB90F372
MB90F377
MB90372
X
X
X
X
: Available
X : Not available
Note : For more information about each package, see Section “■ PACKAGE DIMENSIONS”.
■ DIFFERENCES AMONG PRODUCTS
Memory size
In evaluation with an evaluation product, note the difference between the evaluation product and the product
actually used. The following items must be taken into consideration.
• The MB90V370 does not have an internal ROM, however, operations equivalent to chips with an internal ROM
can be evaluated by using a dedicated development tool, enabling selection of ROM size by settings of the
development tool.
• In the MB90V370, images from FF4000H to FFFFFFH are mapped to bank 00, and FF0000H to FF3FFFH are
mapped to bank FF only. (This setting can be changed by the development tool configuration.)
• In the MB90372/F372, images from FF4000H to FFFFFFH are mapped to bank 00, and FF0000H to FF3FFFH
are mapped to bank FF only.
5
MB90370/375 Series
■ PIN ASSIGNMENT
• MB90372/F372
144
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
LQFP-144
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
PB3/VSI1
PB4/VOL2
PB5/VSI2
PB6/VOL3
PB7/VSI3
AVcc
AVR
AVss
PC0/AN0/SW1
PC1/AN1/SW2
PC2/AN2/SW3
PC3/AN3
PC4/AN4
PC5/AN5
PC6/AN6
PC7/AN7
PD0/AN8
Vcc
Vss
MD2
MD1
MD0
PD1/AN9
PD2/AN10
PD3/AN11
PD4/DA1
PD5/DA2
PD6/PPG2
P90/SCL2
P91/SDA2
P92/SCL3
P93/SDA3
P94/SCL4
P95/SDA4
P80/SCL1
P81/SDA1
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
P40/PSCK0
P41/PSDA0
P42/PSCK1
P43/PSDA1
P44/PSCK2
P45/PSDA2
P46/CLKRUN
P47/SERIRQ
P50/GA20
P51/LFRAME
P52/LRESET
P53/LCK
P54/LAD0
P55/LAD1
P56/LAD2
P57/LAD3
RST
Vcc
Vss
X0A
X1A
PA0/ALR1
PA1/ALR2
PA2/ALR3
PA3/ACO
PA4/OFB1
PA5/OFB2
PA6/OFB3
CVcc
CVRH1
CVRH2
CVRL
CVss
PB0/DCIN
PB1/DCIN2
PB2/VOL1
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
P37/ADTG
P36
P35
P34
P33
P32
P31
P30
P27
P26
P25
P24
P23
P22
P21
X1
X0
Vss
Vcc
P20
P17
P16
P15
P14
P13
P12
P11
P10
P07/KSI7
P06/KSI6
P05/KSI5
P04/KSI4
P03/KSI3
P02/KSI2
P01/KSI1
P00/KSI0
(TOP VIEW)
(FPT-144P-M12)
* : High current pins
6
P77/PPG1
P76/UI3
P75/UO3
P74/UCK3
P73/UI2
P72/UO2
P71/UCK2
P70/UI1
P67/UO1
P66/UCK1
P65/INT5
P64/INT4
P63/INT3
P62/INT2
P61/INT1
P60/INT0
PD7/PPG3
Vss
Vcc
PF7/V3*
PF6/V2*
PF5/V1*
PF4/COM3*
PF3/COM2*
PF2/COM1*
PF1/COM0*
PF0/SEG8*
PE7/TO4/SEG7
PE6/TIN4/SEG6
PE5/TO3/SEG5
PE4/TIN3/SEG4
PE3/TO2/SEG3
PE2/TIN2/SEG2
PE1/TO1/SEG1
PE0/TIN1/SEG0
P82/ALERT
MB90370/375 Series
• MB90F377
144
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
LQFP-144
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
P77/PPG1
P76/UI3
P75/UO3
P74/UCK3
P73/UI2
P72/UO2
P71/UCK2
P70/UI1
P67/UO1
P66/UCK1
P65/INT5
P64/INT4
P63/INT3
P62/INT2
P61/INT1
P60/INT0
PD7/PPG3
Vss
Vcc
PF7*
PF6*
PF5*
PF4*
PF3*
PF2*
PF1*
PF0*
PE7/TO4
PE6/TIN4
PE5/TO3
PE4/TIN3
PE3/TO2
PE2/TIN2
PE1/TO1
PE0/TIN1
P82/ALERT
PB3/VSI1
PB4/VOL2
PB5/VSI2
PB6/VOL3
PB7/VSI3
AVcc
AVR
AVss
PC0/AN0/SW1
PC1/AN1/SW2
PC2/AN2/SW3
PC3/AN3
PC4/AN4
PC5/AN5
PC6/AN6
PC7/AN7
PD0/AN8
Vcc
Vss
MD2
MD1
MD0
PD1/AN9
PD2/AN10
PD3/AN11
PD4/DA1
PD5/DA2
PD6/PPG2
P90/SCL2
P91/SDA2
P92/SCL3
P93/SDA3
P94/SCL4
P95/SDA4
P80/SCL1
P81/SDA1
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
P40/PSCK0
P41/PSDA0
P42/PSCK1
P43/PSDA1
P44/PSCK2
P45/PSDA2
P46/CLKRUN
P47/SERIRQ
P50/GA20
P51/LFRAME
P52/LRESET
P53/LCK
P54/LAD0
P55/LAD1
P56/LAD2
P57/LAD3
RST
Vcc
Vss
X0A
X1A
PA0/ALR1
PA1/ALR2
PA2/ALR3
PA3/ACO
PA4/OFB1
PA5/OFB2
PA6/OFB3
CVcc
CVRH1
CVRH2
CVRL
CVss
PB0/DCIN
PB1/DCIN2
PB2/VOL1
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
P37/ADTG
P36
P35
P34
P33
P32
P31
P30
P27
P26
P25
P24
P23
P22
P21
X1
X0
Vss
Vcc
P20
P17
P16
P15
P14
P13
P12
P11
P10
P07/KSI7
P06/KSI6
P05/KSI5
P04/KSI4
P03/KSI3
P02/KSI2
P01/KSI1
P00/KSI0
(TOP VIEW)
(FPT-144P-M12)
* : High current pins
7
MB90370/375 Series
■ PIN DESCRIPTION
Pin no.
LQFP-144
Pin name
I/O
Pin status
circuit during reset
Function
128, 129
X0, X1
A
Oscillating
Main oscillation pins.
20, 21
X0A, X1A
A
Oscillating
Sub-clock oscillation pins.
17
RST
B
Reset input External reset input pin.
58, 57, 56
MD0 to
MD2
C
Mode input
P00 to P07
Input pin for operation mode specification. Connect this pin
directly to Vcc or Vss.
General-purpose I/O ports.
D
Can be used as key-on wake-up interrupt input channel 0 to
channel 7. Input is enabled when 1 is set in EICR : EN0 to EN7
in standby mode.
117 to 124 P10 to P17
E
General-purpose I/O ports.
125,
P20 to P27
130 to 136
E
General-purpose I/O ports.
137 to 143 P30 to P36
E
General-purpose I/O ports.
109 to 116
144
KSI0 to
KSI7
P37
ADTG
General-purpose I/O ports.
E
External trigger input pin (ADTG) for the A/D converter.
P40
1
PSCK0
General-purpose N-ch open-drain I/O port.
F
Serial clock I/O pin for PS/2 interface channel 0. This function
is selected when PS/2 interface channel 0 is enabled.
P41
2
PSDA0
General-purpose N-ch open-drain I/O port.
F
Port input
P42
3
PSCK1
General-purpose N-ch open-drain I/O port.
F
P43
4
PSDA1
PSCK2
PSDA2
F
CLKRUN
Serial clock I/O pin for PS/2 interface channel 2. This function
is selected when PS/2 interface channel 2 is enabled.
General-purpose N-ch open-drain I/O port.
F
P46
7
Serial data I/O pin for PS/2 interface channel 1. This function
is selected when PS/2 interface channel 1 is enabled.
General-purpose N-ch open-drain I/O port.
P45
6
Serial clock I/O pin for PS/2 interface channel 1. This function
is selected when PS/2 interface channel 1 is enabled.
General-purpose N-ch open-drain I/O port.
F
P44
5
Serial data I/O pin for PS/2 interface channel 0. This function
is selected when PS/2 interface channel 0 is enabled.
Serial data I/O pin for PS/2 interface channel 2. This function
is selected when PS/2 interface channel 2 is enabled.
General-purpose N-ch open-drain I/O port.
G
LPC clock status / restart request I/O pin for serial IRQ controller. This function is selected when serial IRQ and LPC clock
restart request is enabled.
(Continued)
8
MB90370/375 Series
Pin no.
LQFP-144
Pin name
I/O
Pin status
circuit during reset
P47
8
SERIRQ
General-purpose I/O port.
H
Serial IRQ data I/O pin for serial IRQ controller. This function
is selected when serial IRQ is enabled.
P50
9
GA20
General-purpose I/O port.
H
GA20 output for LPC interface. This function is selected when
GA20 function is enabled.
P51
10
LFRAME
General-purpose I/O port.
H
LFRAME input for LPC interface. This function is selected
when LPC interface is enabled.
P52
11
LRESET
General-purpose I/O port.
H
Reset input for LPC interface. This function is selected when
LPC interface is enabled.
P53
12
LCK
General-purpose I/O port.
H
Clock input for LPC interface. This function is selected when
LPC interface is enabled.
P54 to P57
13 to 16
LAD0 to
LAD3
General-purpose I/O ports.
H
Port input
P60 to P65
93 to 98
INT0 to
INT5
UCK1
I
UO1
I
UI1
I
UCK2
Serial data output pin for UART channel 1. This function is
enabled when UART channel 1 enables data output.
General-purpose I/O port.
I
P71
102
Serial clock I/O pin for UART channel 1. This function is
enabled when UART channel 1 enables clock output.
General-purpose I/O port.
P70
101
Can be used as DTP/external interrupt request input channel
0 to 5. Input is enabled when 1 is set in ENIR : EN0 to EN5 in
standby mode.
General-purpose I/O port.
P67
100
Address/Data I/O for LPC interface. This function is selected
when LPC interface is enabled.
General-purpose I/O ports.
P66
99
Function
Serial data input pin for UART channel 1. While UART
channel 1 is operating for input, the input of this pin is used as
required and must not be used for any other input.
General-purpose I/O port.
I
Serial clock I/O pin for UART channel 2. This function is
enabled when UART channel 2 enables clock output.
(Continued)
9
MB90370/375 Series
Pin no.
LQFP-144
Pin name
I/O
Pin status
circuit during reset
P72
103
UO2
General-purpose I/O port.
I
Serial data output pin for UART channel 2. This function is
enabled when UART channel 2 enables data output.
P73
104
UI2
General-purpose I/O port.
Serial data input pin for UART channel 2. While UART
channel 2 is operating for input, the input of this pin is used as
required and must not be used for any other input.
I
P74
105
UCK3
General-purpose I/O port.
I
Serial clock I/O pin for UART channel 3. This function is
enabled when UART channel 3 enables clock output.
P75
106
UO3
General-purpose I/O port.
I
Serial data output pin for UART channel 3. This function is
enabled when UART channel 3 enables data output.
P76
107
UI3
General-purpose I/O port.
71
72
73
65
66
67
68
PPG1
P80
SCL1
P81
SDA1
P82
ALERT
P90
SCL2
P91
SDA2
P92
SCL3
P93
SDA3
Serial data input pin for UART channel 3. While UART
channel 3 is operating for input, the input of this pin is used as
required and must not be used for any other input.
I
P77
108
Function
I
T
T
J
T
T
T
T
Port input
General-purpose I/O port.
Output pin for PPG channel 1. This function is enabled when
PPG channel 1 output is enabled.
General-purpose N-ch open-drain I/O port.
Serial clock I/O pin for multi-address I2C.
General-purpose N-ch open-drain I/O port.
Serial data I/O pin for multi-address I2C.
General-purpose N-ch open-drain I/O port.
ALERT output pin for multi-address I2C.
General-purpose N-ch open-drain I/O port.
Serial clock I/O pin for bridge circuit.
General-purpose N-ch open-drain I/O port.
Serial data I/O pin for bridge circuit.
General-purpose N-ch open-drain I/O port.
Serial clock I/O pin for bridge circuit.
General-purpose N-ch open-drain I/O port.
Serial data I/O pin for bridge circuit.
(Continued)
10
MB90370/375 Series
Pin no.
LQFP-144
69
70
Pin name
P94
SCL4
P95
SDA4
I/O
Pin status
circuit during reset
General-purpose N-ch open-drain I/O port.
T
Serial clock I/O pin for bridge circuit.
General-purpose N-ch open-drain I/O port.
T
Serial data I/O pin for bridge circuit.
PA0 to PA2
22 to 24
25
ALR1 to
ALR3
PA3
ACO
General-purpose I/O ports.
H
H
PA4 to PA6
26 to 28
OFB1 to
OFB3
DCIN to
DCIN2
H
37
VOL1
PB3
VSI1
K
39
VOL2
PB5
VSI2
K
K
K
K
PB6
40
41
VOL3
PB7
VSI3
SW1 to
SW3
AN0 to
AN2
AC power set signal output in comparator circuit.
Battery 1 to 3 discharge control signal output in comparator
circuit.
AC power monitoring input in comparator circuit.
Battery 1 power instantaneous interruption monitoring input in
comparator circuit.
General-purpose I/O ports.
Battery 1 indicator monitoring input in comparator circuit.
Comparator General-purpose I/O ports.
input
Battery 2 power instantaneous interruption monitoring input in
comparator circuit.
General-purpose I/O ports.
Battery 2 indicator monitoring input in comparator circuit.
General-purpose I/O ports.
K
K
PC0 to
PC2
45 to 47
General-purpose I/O port.
General-purpose I/O ports.
PB4
38
Alarm signal output when battery 1 to 3 run down in
comparator circuit.
General-purpose I/O ports.
PB2
36
Port input
General-purpose I/O ports.
PB0 to PB1
34, 35
Function
L
Battery 3 power instantaneous interruption monitoring input in
comparator circuit.
General-purpose I/O ports.
Battery 3 indicator monitoring input in comparator circuit.
General-purpose I/O ports.
Comparator
input
Battery 1 to 3 mount / dismount detection input in comparator
or
circuit.
A/D input A/D converter analog input pin 0 to 2. This function is enabled
when the analog input specification is enabled (ADER1) .
(Continued)
11
MB90370/375 Series
Pin no.
LQFP-144
Pin name
I/O
circuit
Pin status
during reset
PC3 to PC7
48 to 52
AN3 to AN7
General-purpose I/O ports.
M
A/D input
PD0 to PD3
53,
59 to 61
AN8 to
AN11
DA1 to DA2
PPG2 to
PPG3
D/A converter analog output 1 to 2. This function is
selected when D/A converter is enabled.
General-purpose I/O port.
H
Output pin for PPG channel 2 to 3. This function is
selected when PPG channel 2 to 3 output is enabled.
PE0
74
SEG0*1
General-purpose I/O port.
O1
(O2 for
MB90F377)
Segment output pin for LCD controller/driver. This function
is selected when LCD segment output is enabled.
TIN1
External clock input pin for reload timer 1.
PE1
75
SEG1*1
General-purpose I/O port.
O1
(O2 for
MB90F377)
Segment output pin for LCD controller/driver. This function
is selected when LCD segment output is enabled.
TO1
Event output pin for reload timer 1.
PE2
76
SEG2*1
O1
(O2 for
MB90F377)
TIN2
SEG3*1
TO3
Segment output pin for LCD controller/driver. This function
is selected when LCD segment output is enabled.
External clock input pin for reload timer 3.
PE5
SEG5*1
Segment output pin for LCD controller/driver. This function
is selected when LCD segment output is enabled.
General-purpose I/O port.
O1
(O2 for
MB90F377)
TIN3
79
Segment output pin for LCD controller/driver. This function
is selected when LCD segment output is enabled.
Event output pin for reload timer 2.
PE4
SEG4*1
General-purpose I/O port.
General-purpose I/O port.
O1
(O2 for
MB90F377)
TO2
78
Port input
External clock input pin for reload timer 2.
PE3
77
General-purpose I/O ports.
General-purpose I/O ports.
N
PD6 to PD7
64, 92
A/D converter analog input pin 3 to 7. This function is
enabled when the analog input specification is enabled
(ADER1) .
A/D converter analog input pin 8 to 11. This function is
enabled when the analog input specification is enabled
(ADER2) .
M
PD4 to PD5
62 to 63
Function
General-purpose I/O port.
O1
(O2 for
MB90F377)
Segment output pin for LCD controller/driver. This function
is selected when LCD segment output is enabled.
Event output pin for reload timer 3.
(Continued)
12
MB90370/375 Series
(Continued)
Pin no.
LQFP-144
Pin name
I/O
circuit
Pin status
during reset
PE6
80
SEG6*1
General-purpose I/O port.
O1
(O2 for
MB90F377)
Segment output pin for LCD controller/driver. This function
is selected when LCD segment output is enabled.
TIN4
External clock input pin for reload timer 4.
PE7
81
SEG7*1
General-purpose I/O port.
O1
(O2 for
MB90F377)
TO4
PF0
82
SEG8*1
PF1 to PF4
83 to 86
COM0 to
COM3*2
PF5 to PF7
87 to 89
V1 to V3*2
Function
Port input
Segment output pin for LCD controller/driver. This function
is selected when LCD segment output is enabled.
Event output pin for reload timer 4.
P1
(P2 for
MB90F377)
General-purpose I/O port.
P1
(P2 for
MB90F377)
General-purpose I/O port.
Segment output pin for LCD controller/driver. This function
is selected when LCD segment output is enabled.
COM output pin for LCD controller/driver. This function is
selected when LCD COM output is enabled.
General-purpose I/O port.
Q1
(Q2 for
Power input Power input pin for LCD controller/driver. This function is
MB90F377)
selected when external voltage divider is enabled.
42
AVCC
R
43
AVR
S
44
AVSS
R
Vss power input pin for analog circuits.
29
CVCC
R
Vcc power input pin for analog circuits.
30
CVRH1
R
31
CVRH2
R
32
CVRL
R
33
CVSS
R
Vss power input pin for analog circuits.
19, 55, 91,
127
Vss
–
Power (0 V) input pin.
18, 54, 90,
126
Vcc
–
Vcc power input pin for analog circuits.
Power input Vref+ input pin for the A/D converter. This voltage must not
exceed Vcc. Vref- is fixed to AVSS.
Power input
Standard power input pin of the comparator.
Power input
Power (3.3 V) input pin.
*1 : It doesn’t exist in MB90F377.
*2 : They don’t exist in MB90F377.
13
MB90370/375 Series
■ I/O CIRCUIT TYPE
Type
Circuit
Remarks
X1/X1A
Xout
N-ch P-ch
A
P-ch
X0/X0A
N-ch
Main/Sub clock (main/sub clock crystal
oscillator)
• High-rate oscillation feedback
resistor of approximately 1 MΩ
• Low-rate oscillation feedback
resistor of approximately 10 MΩ
Standby mode control
B
• Hysteresis input
• Pull-up resistor approximately
50 kΩ
R
• Hysteresis input
C
R
P-ch
Pull-up control
P-ch
Pout
D
• CMOS output
• Hysteresis input
• Selectable pull-up resistor
approximately 50 kΩ
• IOL = 4 mA
Nout
N-ch
Hysteresis input
Standby mode control
R
P-ch
Pull-up control
P-ch
Pout
E
N-ch
• CMOS output
• CMOS input
• Selectable pull-up resistor
approximately 50 kΩ
• IOL = 4 mA
Nout
CMOS input
Standby mode control
N-ch
F
N-ch
Nout
•
•
•
•
N-ch open-drain output
Hysteresis input
IOL = 4 mA
5 V tolerant
Hysteresis input
Standby mode control
(Continued)
14
MB90370/375 Series
Type
Circuit
Remarks
• N-ch open-drain output
• CMOS input
• IOL = 4 mA
P-ch
G
N-ch
Nout
CMOS input
Standby mode control
P-ch
H
N-ch
Pout
• CMOS output
• CMOS input
• IOL = 4 mA
Nout
CMOS input
Standby mode control
P-ch
I
N-ch
Pout
• CMOS output
• Hysteresis input
• IOL = 4 mA
Nout
Hysteresis input
Standby mode control
N-ch
J
N-ch
Nout
•
•
•
•
N-ch open-drain output
CMOS input
IOL = 4 mA
5 V tolerant
•
•
•
•
CMOS output
CMOS input
Comparator input
IOL = 4 mA
CMOS input
Standby mode control
P-ch
Pout
N-ch
Nout
K
CMOS input
Standby mode control
+
−
Comparator input
(Continued)
15
MB90370/375 Series
Type
Circuit
Remarks
P-ch
Pout
N-ch
Nout
L
•
•
•
•
•
CMOS output
CMOS input
Comparator input
A/D analog input
IOL = 4 mA
•
•
•
•
CMOS output
CMOS input
A/D analog input
IOL = 4 mA
•
•
•
•
CMOS output
CMOS input
D/A analog output
IOL = 4 mA
•
•
•
•
CMOS output
CMOS input
Segment output
IOL = 4 mA
CMOS input
Standby mode control
+
−
Comparator input
Analog input
M
P-ch
Pout
N-ch
Nout
CMOS input
Standby mode control
Analog input
P-ch
Pout
N-ch
Nout
N
CMOS input
Standby mode control
Analog input
P-ch
Pout
N-ch
Nout
O1
CMOS input
Standby mode control
Segment output
(Continued)
16
MB90370/375 Series
Type
O2
Circuit
Remarks
P-ch
Pout
N-ch
Nout
• CMOS output
• CMOS input
• IOL = 4 mA
CMOS input
Standby mode control
P-ch
Pout
N-ch
Nout
•
•
•
•
CMOS output
CMOS input
Segment output
IOL = 12 mA
P1
CMOS input
Standby mode control
Segment output
P2
P-ch
Pout
N-ch
Nout
• CMOS output
• CMOS input
• IOL = 12 mA
CMOS input
Standby mode control
P-ch
Pout
N-ch
Nout
•
•
•
•
CMOS output
CMOS input
LCD driving power supply
IOL = 12 mA
Q1
CMOS input
Standby mode control
LCD driving power supply
Q2
P-ch
Pout
N-ch
Nout
• CMOS output
• CMOS input
• IOL = 12 mA
CMOS input
Standby mode control
(Continued)
17
MB90370/375 Series
(Continued)
Type
Circuit
Remarks
• Power supply input protection circuit
P-ch
R
IN
N-ch
P-ch
Analog input enable
IN
S
N-ch
Analog input enable
N-ch
T
N-ch
Nout
CMOS input
Standby mode control
18
• A/D converter reference voltage
(AVR) input pin with protection circuit
•
•
•
•
N-ch open-drain output
CMOS input
IOL = 4 mA
5 V tolerant
MB90370/375 Series
■ HANDLING DEVICES
• Be sure that the maximum rated voltage is not exceeded (latch-up prevention) .
A latch-up may occur on a CMOS IC if a voltage higher than VCC or lower than VSS is applied to an input or
output pin other than medium-to-high voltage pins. A latch-up may also occur if a voltage higher than the
rating is applied between VCC and VSS. A latch-up causes a rapid increase in the power supply current, which
can result in thermal damage to an element. Take utmost care that the maximum rated voltage is not exceeded.
When turning the power on or off to analog circuits, be sure that the analog supply voltages (AVCC, CVCC, AVR,
CVRH1, CVRH2 and CVRL) and analog input voltage do not exceed the digital supply voltage (VCC) .
• Stabilize the supply voltages
Even within the operation guarantee range of the VCC supply voltage, a malfunction can be caused if the supply
voltage undergoes a rapid change. For voltage stabilization guidelines, the VCC ripple fluctuations (P-P value)
at commercial frequencies (50 Hz to 60 Hz) should be suppressed to 10% or less of the reference VCC value.
During a momentary change such as when switching a supply voltage, voltage fluctuations should also be
suppressed so that the transient fluctuation rate is 0.1 V/ms or less.
• Power-on
To prevent a malfunction in the built-in voltage drop circuit, secure 50 µs (between 0.2 V and 1.8 V) or more
for the voltage rise time during power-on.
• Treatment of unused input pins
An unused input pin may cause a malfunction if it is left open. Every unused input pin should be pulled up or
down.
• Treatment of A/D converter, D/A converter and comparator power pin
When the A/D converter, D/A converter and comparator is not used, connect the pins as follows : AVCC = CVCC
= VCC, AVSS = AVR = CVSS = CVRL = CVRH1 = CVRH2 = VSS.
• Notes on external clock
When an external clock is used, the oscillation stabilization wait time is required at power-on reset or at
cancellation of sub-clock mode or stop mode. As shown in diagram below, when an external clock is used,
connect only the X0 pin and leave the X1 pin open.
X0
MB90370/375 series
Open
X1
• Power supply pins
When a device has two or more VCC or VSS pins, the pins that should have equal potential are connected within
the device in order to prevent a latch-up or other malfunction. To reduce extraneous emission, to prevent a
malfunction of the strobe signal due to an increase in the group level, and to maintain the local output current
rating, connect all these power supply pins to an external power supply and ground them.
The current source should be connected to the VCC and VSS pins of the device with minimum impedance. It
is recommended that a bypass capacitor of about 0.1 µF be connected near the terminals between VCC and VSS.
19
MB90370/375 Series
• Analog power-on sequence of A/D converter, D/A converter and comparator
The power to the A/D converter, D/A converter and comparator (AVCC, CVCC, AVR, CVRH1, CVRH2 and CVRL)
and analog inputs (AN0 to AN11, VOL1 to VOL3, VSI1 to VSI3, SW1 to SW3, DCIN and DCIN2) must be
turned on after the power to the digital circuits (VCC) is turned on. When turning off the power, turn off the
power to the digital circuits (VCC) after turning off the power to the A/D converter, D/A converter, comparator
and analog inputs. When the power is turned on or off, AVR should not exceed AVCC. And CVRH1, CVRH2
and CVRL should not exceed CVCC. Also, when a pin that is used for A/D analog input is used as an input port,
the input voltage should not exceed AVCC. And when comparator analog input is also used as an input port,
the input voltage should not exceed CVCC. (The power to the analog circuits and the power to the digital circuits
can be simultaneously turned on or off.)
• Caution on Operations during PLL Clock Mode
If the PLL clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit even
when there is no external oscillator or external clock input is stopped. Performance of this operation, however,
cannot be guaranteed.
20
MB90370/375 Series
■ BLOCK DIAGRAM
• MB90372/F372/V370
X0, X0A
X1, X1A
CPU
series core
Clock control
circuit
F2MC-16LX
Delayed interrupt generator
Reset circuit
(Watchdog timer)
RST
Other pins
Vss x 4, Vcc x 4, MD0-2, AVcc, AVss, CVcc, CVss
N-ch open-drain I/O port 8, 9
Interrupt controller
P10 to P17
P20 to P27
CMOS I/O port 0, 1, 2, 3*
I2C bus
P80/SCL1
P81/SDA1
P82/ALERT
P90/SCL2
P91/SDA2
P92/SCL3
P93/SDA3
P94/SCL4
P95/SDA4
8
8
8
8
Key-on wake-up
interrupt
P30 to P36 8
P37/ADTG
P40/PSCK0
P41/PSDA0
P42/PSCK1
P43/PSDA1
P44/PSCK2
P45/PSDA2
P46/CLKRUN
P47/SERIRQ
Bridge circuit
N-ch open-drain I/O port 4
(P47 is CMOS I/O port)
6
3CH PS/2 interface
Comparator
2
Serial IRQ (6 channels)
LPC Interface
GateA20 control
7
Bus interface
P50/GA20
P51/LFRAME
P52/LRESET
P53/LCK
P54/LAD0
P55/LAD1
P56/LAD2
P57/LAD3
6
Battery select circuit
7
8
Voltage comparator
3
UPI
(Ch0, 1, 2, 3)
PA0/ALR1 to
PA2/ALR3
PA3/ACO
PA4/OFB1 to
PA6/OFB3
PB0/DCIN
PB1/DCIN2
PB2/VOL1
PB3/VSI1
PB4/VOL2
PB5/VSI2
PB6/VOL3
PB7/VSI3
CVRH1, CVRH2, CVRL
AVR
CMOS I/O port 5
P60/INT0 to 6
P65/INT5
P66/UCK1
P67/UO1
P70/UI1
P71/UCK2
P72/UO2
P73/UI2
P74/UCK3
P75/UO3
P76/UI3
P77/PPG1
6
CMOS I/O port A, B
F2MC-16LX bus
P00/KSI0 to
P07/KSI7
Timebase timer
I2C bus
(Multi-address)
DTP/External interrupt
UART
(Ch1, 2, 3)
A/D converter
(8/10 bit)
2
D/A converter
16-bit PPG
(Ch2, 3)
16-bit PPG (Ch1)
CMOS I/O port C, D
CMOS I/O port 6, 7
CMOS I/O port E, F
RAM
ROM
ROM correction
ROM mirroring
12
16-bit reload timer
(Ch1, 2, 3, 4)
PC0/AN0/SW1
PC1/AN1/SW2
PC2/AN2/SW3
PC3/AN3 to
PC7/AN7
PD0/AN8 to
PD3/AN11
PD4/DA1
PD5/DA2
PD6/PPG2
PD7/PPG3
PE0/TIN1
PE1/TO1
PE2/TIN2
PE3/TO2
PE4/TIN3
PE5/TO3
PE6/TIN4
PE7/TO4
PF0
PF1 to
PF4
PF5 to
PF7
* : P00 to P07, P10 to P17, P20 to P27, P30 to P37 : With registers that can be used as input pull-up resistors
Note: PF0 to PF7 : High current pins
21
MB90370/375 Series
• MB90F377
X0, X0A
X1, X1A
CPU
F2MC-16LX series core
Clock control
circuit
Delayed interrupt generator
Reset circuit
(Watchdog timer)
RST
Other pins
Vss x 4, Vcc x 4, MD0-2, AVcc, AVss, CVcc, CVss
N-ch open-drain I/O port 8, 9
Interrupt controller
P10 to P17
P20 to P27
CMOS I/O port 0, 1, 2, 3*
I2C bus
P80/SCL1
P81/SDA1
P82/ALERT
P90/SCL2
P91/SDA2
P92/SCL3
P93/SDA3
P94/SCL4
P95/SDA4
8
8
8
8
Key-on wake-up
interrupt
P30 to P36 8
P37/ADTG
P40/PSCK0
P41/PSDA0
P42/PSCK1
P43/PSDA1
P44/PSCK2
P45/PSDA2
P46/CLKRUN
P47/SERIRQ
Bridge circuit
N-ch open-drain I/O port 4
(P47 is CMOS I/O port)
6
3CH PS/2 interface
Comparator
2
Serial IRQ (6 channels)
LPC Interface
GateA20 control
7
Bus interface
P50/GA20
P51/LFRAME
P52/LRESET
P53/LCK
P54/LAD0
P55/LAD1
P56/LAD2
P57/LAD3
6
Battery select circuit
7
8
Voltage comparator
3
UPI
(Ch0, 1, 2, 3)
PA0/ALR1 to
PA2/ALR3
PA3/ACO
PA4/OFB1 to
PA6/OFB3
PB0/DCIN
PB1/DCIN2
PB2/VOL1
PB3/VSI1
PB4/VOL2
PB5/VSI2
PB6/VOL3
PB7/VSI3
CVRH1, CVRH2, CVRL
AVR
CMOS I/O port 5
P60/INT0 to 6
P65/INT5
P66/UCK1
P67/UO1
P70/UI1
P71/UCK2
P72/UO2
P73/UI2
P74/UCK3
P75/UO3
P76/UI3
P77/PPG1
6
CMOS I/O port A, B
F2MC-16LX bus
P00/KSI0 to
P07/KSI7
Timebase timer
I2C bus
(Multi-address)
DTP/External interrupt
UART
(Ch1, 2, 3)
A/D converter
(8/10 bit)
2
D/A converter
16-bit PPG
(Ch2, 3)
16-bit PPG (Ch1)
CMOS I/O port C, D
CMOS I/O port 6, 7
CMOS I/O port E, F
RAM
ROM
ROM correction
ROM mirroring
12
16-bit reload timer
(Ch1, 2, 3, 4)
PC0/AN0/SW1
PC1/AN1/SW2
PC2/AN2/SW3
PC3/AN3 to
PC7/AN7
PD0/AN8 to
PD3/AN11
PD4/DA1
PD5/DA2
PD6/PPG2
PD7/PPG3
PE0/TIN1
PE1/TO1
PE2/TIN2
PE3/TO2
PE4/TIN3
PE5/TO3
PE6/TIN4
PE7/TO4
PF0
PF1 to
PF4
PF5 to
PF7
* : P00 to P07, P10 to P17, P20 to P27, P30 to P37 : With registers that can be used as input pull-up resistors
Note: PF0 to PF7 : High current pins
22
MB90370/375 Series
■ MEMORY MAP
Single-chip mode
(with ROM mirroring function)
FFFFFFH
ROM area
Address #1
FC0000H
010000H
ROM area
(FF bank image)
Address #2
004000H
003FC0H
Address #3
Peripheral area
RAM
area
Register
000100H
0000F8H
000000H
: Internal access memory
Peripheral area
: Access not allowed
Model
Address #1
Address #2
Address #3
MB90372
FF0000H
004000H
001900H
MB90F372/F377
FF0000H
004000H
001900H
MB90V370
FF0000H*
004000H*
003FC0H
* : The MB90V370 does not contain ROM. Assume that the development tool uses these area for its ROM decode
areas.
Note : ROM data in the FF bank can be seen as an image in the higher 00 bank to validate the small model C
compiler. Because addresses of the 16 low-order bits in the FF bank are the same, the table in ROM can
be referenced without the “far” specification. For example, when 00C000H is accessed, the contents of
ROM at FFC000H are actually accessed. The ROM area in the FF bank exceeds 48 kilobytes, and all
areas cannot be seen as images in the 00 bank. Because ROM data from FF4000H to FFFFFFH is seen
as an image at 004000H to 00FFFFH, the ROM data table should be stored in the area from FF4000H to
FFFFFFH.
23
MB90370/375 Series
■ F2MC-16LX CPU PROGRAMMING MODEL
• Dedicated registers
AH
AL
Accumulator (A)
USP
User Stack Pointer (USP)
SSP
System Stack Pointer (SSP)
PS
Processor Status (PS)
PC
Program Counter (PC)
DPR
Direct Page Register (DPR)
PCB
Program Bank Register (PCB)
DTB
Data Bank Register (DTB)
USB
User Stack Bank Register (USB)
SSB
System Stack Bank Register (SSB)
ADB
Additional Data Bank Register (ADB)
8 bits
16 bits
32 bits
24
MB90370/375 Series
• General-purpose registers
CPU
Dedicated register
RAM
RAM
General-purpose
register
Accumulator
User stack pointer
System stack pointer
Internal bus
Processor status
Program counter
Direct page register
Program bank register
Data bank register
User stack bank register
System stack bank register
Additional data bank register
• Processor status (PS)
15
1312
PS
Default value
Default value
Default value
0
RP
CCR
000
00000
-01XXXXX
7
6
5
4
3
2
1
0
I
S
T
N
Z
V
C
0
1
X
X
X
X
X
B4 B3 B2 B1
Default value
8 7
ILM
0
0
0
0
B0
: CCR
: RP
0
ILM2
ILM1
ILM0
0
0
0
: ILM
- : Not used
X : Undefined
25
MB90370/375 Series
■ I/O MAP
Address
Abbreviation
Resource
name
Initial value
000000H
PDR0
Port 0 data register
R/W
R/W
Port 0
XXXXXXXXB
000001H
PDR1
Port 1 data register
R/W
R/W
Port 1
XXXXXXXXB
000002H
PDR2
Port 2 data register
R/W
R/W
Port 2
XXXXXXXXB
000003H
PDR3
Port 3 data register
R/W
R/W
Port 3
XXXXXXXXB
000004H
PDR4
Port 4 data register
R/W
R/W
Port 4
X1111111B
000005H
PDR5
Port 5 data register
R/W
R/W
Port 5
XXXXXXXXB
000006H
PDR6
Port 6 data register
R/W
R/W
Port 6
XXXXXXXXB
000007H
PDR7
Port 7 data register
R/W
R/W
Port 7
XXXXXXXXB
000008H
PDR8
Port 8 data register
R/W
R/W
Port 8
-----111B
000009H
PDR9
Port 9 data register
R/W
R/W
Port 9
--111111B
00000AH
PDRA
Port A data register
R/W
R/W
Port A
-XXXXXXXB
00000BH
PDRB
Port B data register
R/W
R/W
Port B
XXXXXXXXB
00000CH
PDRC
Port C data register
R/W
R/W
Port C
XXXXXXXXB
00000DH
PDRD
Port D data register
R/W
R/W
Port D
XXXXXXXXB
00000EH
PDRE
Port E data register
R/W
R/W
Port E
XXXXXXXXB
00000FH
PDRF
Port F data register
R/W
R/W
Port F
XXXXXXXXB
000010H
DDR0
Port 0 direction register
R/W
R/W
Port 0
00000000B
000011H
DDR1
Port 1 direction register
R/W
R/W
Port 1
00000000B
000012H
DDR2
Port 2 direction register
R/W
R/W
Port 2
00000000B
000013H
DDR3
Port 3 direction register
R/W
R/W
Port 3
00000000B
000014H
DDR4
Port 4 direction register
R/W
R/W
Port 4
0-------B
000015H
DDR5
Port 5 direction register
R/W
R/W
Port 5
00000000B
000016H
DDR6
Port 6 direction register
R/W
R/W
Port 6
00000000B
000017H
DDR7
Port 7 direction register
R/W
R/W
Port 7
00000000B
000018H
PGDR
Parity generator data register
R/W
R/W
000019H
PGCSR
Parity generator control status
register
R/W
R/W
00001AH
DDRA
Port A direction register
R/W
R/W
Port A
-0000000B
00001BH
DDRB
Port B direction register
R/W
R/W
Port B
00000000B
00001CH
DDRC
Port C direction register
R/W
R/W
Port C
00000000B
00001DH
DDRD
Port D direction register
R/W
R/W
Port D
00000000B
00001EH
DDRE
Port E direction register
R/W
R/W
Port E
00000000B
00001FH
DDRF
Port F direction register
R/W
R/W
Port F
00000000B
Register
Byte
Word
access access
XXXXXXXXB
Parity generator
X------0B
(Continued)
26
MB90370/375 Series
Address
Abbreviation
000020H
SMR1
Serial mode register 1
R/W
R/W
00000-00B
000021H
SCR1
Serial control register 1
R/W
R/W
00000100B
000022H
SIDR1/
SODR1
Input data register 1 /
Output data register 1
R/W
R/W
000023H
SSR1
Serial status register 1
R/W
R/W
00001000B
000024H
M2CR1
Mode 2 control register 1
R/W
R/W
----1000B
000025H
CDCR1
Clock division control register 1
R/W
R/W
000026H
ENIR
Interrupt / DTP enable register
R/W
R/W
000027H
EIRR
Interrupt / DTP cause register
R/W
R/W
ELVR
Request level setting register
R/W
R/W
R/W
R/W
00002AH
ADER1
Analog input enable register 1
R/W
R/W
Port C, A/D
11111111B
00002BH
ADER2
Analog input enable register 2
R/W
R/W
Port D, A/D
----1111B
00002CH
BRSR
Bridge circuit selection register
R/W
R/W
Bridge circuit
--000000B
00002DH
ADC0
A/D control register
R/W
R/W
00002EH
ADCR0
R
R
000028H
000029H
00002FH
ADCR1
000030H
ADCS0
000031H
ADCS1
000032H
SICRL
000033H
Register
A/D data register
Byte
Word
access access
Resource
name
UART1
Communication
prescaler 1
Initial value
XXXXXXXXB
0---0000B
--000000B
DTP/external
interrupt
--XXXXXXB
00000000B
----0000B
00000000B
XXXXXXXXB
8/10-bit A/D
converter
R/W
R/W
R/W
R/W
00--------B
R/W
R/W
00000000B
Serial interrupt request register
R/W
R/W
00000000B
SICRH
Serial interrupt control register
R/W
R/W
00000000B
000034H
SIFR1
Serial interrupt frame number
register 1
R/W
R/W
--000000B
000035H
SIFR2
Serial interrupt frame number
register 2
R/W
R/W
000036H
SIFR3
Serial interrupt frame number
register 3
R/W
R/W
--000000B
000037H
SIFR4
Serial interrupt frame number
register 4
R/W
R/W
--000000B
A/D control status register
Serial IRQ
00000-XXB
--000000B
(Continued)
27
MB90370/375 Series
Address
Abbreviation
000038H
PDCRL1
000039H
PDCRH1
00003AH
PCSRL1
00003BH
PCSRH1
00003CH
PDUTL1
00003DH
PDUTH1
00003EH
PCNTL1
00003FH
PCNTH1
000040H
PDCRL2
000041H
PDCRH2
000042H
PCSRL2
000043H
PCSRH2
000044H
PDUTL2
000045H
PDUTH2
000046H
PCNTL2
000047H
PCNTH2
000048H
PDCRL3
000049H
PDCRH3
00004AH
PCSRL3
00004BH
PCSRH3
00004CH
PDUTL3
00004DH
PDUTH3
00004EH
PCNTL3
00004FH
PCNTH3
000050H
PSCR0
000051H
Register
Byte
Word
access access
Resource
name
Initial value
R
11111111B
R
11111111B
W
XXXXXXXXB
W
W
W
XXXXXXXXB
R/W
R/W
--000000B
R/W
R/W
00000000B
R
11111111B
R
11111111B
W
XXXXXXXXB
W
W
W
XXXXXXXXB
R/W
R/W
--000000B
R/W
R/W
00000000B
R
11111111B
R
11111111B
W
XXXXXXXXB
W
W
W
XXXXXXXXB
R/W
R/W
--000000B
R/W
R/W
00000000B
PS/2 interface control register 0
R/W
R/W
0--00000B
PSSR0
PS/2 interface status register 0
R/W
R/W
00000000B
000052H
PSCR1
PS/2 interface control register 1
R/W
R/W
0--00000B
000053H
PSSR1
PS/2 interface status register 1
R/W
R/W
00000000B
000054H
PSCR2
PS/2 interface control register 2
R/W
R/W
000055H
PSSR2
PS/2 interface status register 2
R/W
R/W
000056H
PSDR0
PS/2 interface data register 0
R/W
R/W
00000000B
000057H
PSDR1
PS/2 interface data register 1
R/W
R/W
00000000B
000058H
PSDR2
PS/2 interface data register 2
R/W
R/W
00000000B
000059H
PSMR
PS/2 interface mode register
R/W
R/W
----0000B
PPG1 down counter register
PPG1 period setting register
PPG1 duty setting register
PPG1 control status register
PPG2 down counter register
PPG2 period setting register
PPG2 duty setting register
PPG2 control status register
PPG3 down counter register
PPG3 period setting register
PPG3 duty setting register
PPG3 control status register
16-bit
PPG timer
(CH1)
16-bit
PPG timer
(CH2)
16-bit
PPG timer
(CH3)
3-channel PS/2
interface
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
0--00000B
00000000B
(Continued)
28
MB90370/375 Series
Address
Abbreviation
00005AH
DAT0
D/A converter data register 0
R/W
R/W
00005BH
DAT1
D/A converter data register 1
R/W
R/W
00005CH
DACR0
D/A control register 0
R/W
R/W
00005DH
DACR1
D/A control register 1
R/W
R/W
-------0B
00005EH
UPAL1
UPI1 address register (lower)
R/W
R/W
XXXXXXXXB
00005FH
UPAH1
UPI1 address register (upper)
R/W
R/W
XXXXXXXXB
000060H
UPAL2
UPI2 address register (lower)
R/W
R/W
XXXXXXXXB
000061H
UPAH2
UPI2 address register (upper)
R/W
R/W
XXXXXXXXB
000062H
UPAL3
UPI3 address register (lower)
R/W
R/W
XXXXXXXXB
000063H
UPAH3
UPI3 address register (upper)
R/W
R/W
XXXXXXXXB
000064H
UPCL
UPI control register (lower)
R/W
R/W
00000000B
000065H
UPCH
UPI control register (upper)
R/W
R/W
-000-000B
000066H
UPDI0/
UPDO0
UPI0 data input register / data
output register
R/W
R/W
XXXXXXXXB
000067H
UPS0
UPI0 status register
R/W
R/W
000068H
UPDI1/
UPDO1
UPI1 data input register / data
output register
R/W
R/W
XXXXXXXXB
000069H
UPS1
UPI1 status register
R/W
R/W
00000000B
00006AH
UPDI2/
UPDO2
UPI2 data input register / data
output register
R/W
R/W
XXXXXXXXB
00006BH
UPS2
UPI2 status register
R/W
R/W
00000000B
00006CH
UPDI3/
UPDO3
UPI3 data input register / data
output register
R/W
R/W
XXXXXXXXB
00006DH
UPS3
UPI3 status register
R/W
R/W
00000000B
00006EH
LCR
LPC control register
R/W
R/W
-----000B
00006FH
ROMM
ROM mirroring function selection
register
W
W
000070H
TMCSRL1
Timer control status register CH1
(lower)
R/W
R/W
000071H
TMCSRH1
Timer control status register CH1
(upper)
R/W
R/W
000072H
TMR1/
TMRD1
R/W
XXXXXXXXB
R/W
XXXXXXXXB
000073H
Register
16-bit timer/reload register CH1
Byte
Word
access access
Resource
name
Initial value
XXXXXXXXB
D/A converter
LPC interface
ROM mirroring
function
XXXXXXXXB
-------0B
00000000B
------01B
00000000B
16-bit reload
timer (CH1)
----0000B
(Continued)
29
MB90370/375 Series
Address
Abbreviation
Register
000074H
TMCSRL2
Timer control status register CH2
(lower)
R/W
R/W
000075H
TMCSRH2
Timer control status register CH2
(upper)
R/W
R/W
000076H
R/W
XXXXXXXXB
000077H
TMR2/
TMRD2
R/W
XXXXXXXXB
000078H
TMCSRL3
Timer control status register CH3
(lower)
R/W
R/W
00000000B
000079H
TMCSRH3
Timer control status register CH3
(upper)
R/W
R/W
00007AH
R/W
XXXXXXXXB
00007BH
TMR3/
TMRD3
R/W
XXXXXXXXB
00007CH
TMCSRL4
Timer control status register CH4
(lower)
R/W
R/W
00000000B
00007DH
TMCSRH4
Timer control status register CH4
(upper)
R/W
R/W
00007EH
TMR4/
TMRD4
R/W
XXXXXXXXB
00007FH
000080H
IBCRL
16-bit timer/reload register CH2
16-bit timer/reload register CH3
16-bit timer/reload register CH4
Byte
Word
access access
Resource
name
Initial value
00000000B
16-bit reload
timer (CH2)
16-bit reload
timer (CH3)
16-bit reload
timer (CH4)
----0000B
----0000B
----0000B
R/W
XXXXXXXXB
2
R/W
R/W
----0000B
2
I C bus control register (lower)
000081H
IBCRH
I C bus control register (upper)
R/W
R/W
00000000B
000082H
IBSRL
I2C bus status register (lower)
R
R
00000000B
000083H
IBSRH
I2C bus status register (upper)
000084H
IDAR
R/W
R/W
--000000B
2
R/W
R/W
XXXXXXXXB
2
I C data register
000085H
IADR
I C address register
R/W
R/W
000086H
ICCR
I2C clock control register
R/W
R/W
000087H
ITCR
I2C timeout control register
000088H
ITOC
I2C
-XXXXXXXB
0-000000B
R/W
R/W
-0-00000B
2
R/W
R/W
00000000B
2
I C timeout clock register
000089H
ITOD
I C timeout data register
R/W
R/W
00000000B
00008AH
ISTO
I2C slave timeout register
R/W
R/W
00000000B
00008BH
IMTO
I2C master timeout register
R/W
R/W
00000000B
00008CH
RDR0
Port 0 pull-up resistor setting
register
R/W
R/W
Port 0
00000000B
00008DH
RDR1
Port 1 pull-up resistor setting
register
R/W
R/W
Port 1
00000000B
00008EH
RDR2
Port 2 pull-up resistor setting
register
R/W
R/W
Port 2
00000000B
00008FH
RDR3
Port 3 pull-up resistor setting
register
R/W
R/W
Port 3
00000000B
(Continued)
30
MB90370/375 Series
Address
Abbreviation
Byte
Word
access access
Register
000090H
to 9DH
Resource
name
Initial value
Prohibited area
00009EH
PACSR
Program address detect control
status register
R/W
R/W
ROM correction
----0000B
00009FH
DIRR
Delayed interrupt cause / clear
register
R/W
R/W
Delayed
interrupt
-------0B
0000A0H
LPMCR
Low-power consumption mode
register
R/W
R/W
0000A1H
CKSCR
Clock selection register
R/W
0000A2H
to A7H
00011000B
R/W
Low-power
consumption
control register
11111100B
Prohibited area
0000A8H
WDTC
Watchdog control register
R/W
R/W
Watchdog timer
X-XXX111B
0000A9H
TBTC
Timebase timer control register
R/W
R/W
Timebase timer
1--00100B
0000AAH
WTC
Watch timer control register
R/W
R/W
Watch timer
10001000B
Wake-up
interrupt
00000000B
0000ABH
Prohibited area
0000ACH
EICR
Wake-up interrupt control register
R/W
R/W
0000ADH
EIFR
Wake-up interrupt flag register
R/W
R/W
0000AEH
FMCS
Flash memory control status
register
R/W
R/W
0000AFH
Flash memory
interface circuit
-------0B
00010000B
Prohibited area
0000B0H
ICR00
Interrupt control register 00
R/W
R/W
00000111B
0000B1H
ICR01
Interrupt control register 01
R/W
R/W
00000111B
0000B2H
ICR02
Interrupt control register 02
R/W
R/W
00000111B
0000B3H
ICR03
Interrupt control register 03
R/W
R/W
00000111B
0000B4H
ICR04
Interrupt control register 04
R/W
R/W
00000111B
Interrupt
controller
0000B5H
ICR05
Interrupt control register 05
R/W
R/W
00000111B
0000B6H
ICR06
Interrupt control register 06
R/W
R/W
00000111B
0000B7H
ICR07
Interrupt control register 07
R/W
R/W
00000111B
0000B8H
ICR08
Interrupt control register 08
R/W
R/W
00000111B
0000B9H
ICR09
Interrupt control register 09
R/W
R/W
00000111B
0000BAH
ICR10
Interrupt control register 10
R/W
R/W
00000111B
(Continued)
31
MB90370/375 Series
Address
Abbreviation
0000BBH
ICR11
Interrupt control register 11
R/W
R/W
0000BCH
ICR12
Interrupt control register 12
R/W
R/W
Register
Byte
Word
access access
Resource
name
Initial value
00000111B
00000111B
Interrupt
controller
0000BDH
ICR13
Interrupt control register 13
R/W
R/W
0000BEH
ICR14
Interrupt control register 14
R/W
R/W
00000111B
0000BFH
ICR15
Interrupt control register 15
R/W
R/W
00000111B
2
00000111B
0000C0H
MBCRL
MI C bus control register (lower)
R/W
R/W
----0000B
0000C1H
MBCRH
MI2C bus control register (upper)
R/W
R/W
00000000B
0000C2H
MBSRL
MI2C bus status register (lower)
0000C3H
MBSRH
R
R
00000000B
2
R/W
R/W
--000000B
2
MI C bus status register (upper)
0000C4H
MDAR
MI C data register
R/W
R/W
XXXXXXXXB
0000C5H
MALR
MI2C alert register
R/W
R/W
----0000B
0000C6H
MADR1
MI2C address register 1
0000C7H
MADR2
R/W
R/W
-XXXXXXXB
2
R/W
R/W
-XXXXXXXB
2
MI C address register 2
0000C8H
MADR3
MI C address register 3
R/W
R/W
0000C9H
MADR4
MI2C address register 4
R/W
R/W
0000CAH
MADR5
MI2C address register 5
0000CBH
MADR6
MI2C
-XXXXXXXB
-XXXXXXXB
R/W
R/W
-XXXXXXXB
2
R/W
R/W
-XXXXXXXB
2
MI C address register 6
0000CCH
MCCR
MI C clock control register
R/W
R/W
0-000000B
0000CDH
MTCR
MI2C timeout control register
R/W
R/W
-0-00000B
0000CEH
MTOC
MI2C timeout clock register
0000CFH
MTOD
R/W
R/W
00000000B
2
R/W
R/W
00000000B
2
MI C timeout data register
0000D0H
MSTO
MI C slave timeout register
R/W
R/W
00000000B
0000D1H
MMTO
MI2C master timeout register
R/W
R/W
00000000B
0000D2H
SMR2
Serial mode register 2
R/W
R/W
00000-00B
0000D3H
SCR2
Serial control register 2
R/W
R/W
00000100B
0000D4H
SIDR2/
SODR2
Input data register 2 /
output data register 2
R/W
R/W
0000D5H
SSR2
Status register 2
R/W
R/W
00001000B
0000D6H
M2CR2
Mode 2 control register 2
R/W
R/W
----1000B
0000D7H
CDCR2
Clock division control register 2
R/W
R/W
UART2
Communication
prescaler 2
XXXXXXXXB
0---0000B
(Continued)
32
MB90370/375 Series
Address
Abbreviation
Byte
Word
access access
0000D8H
COCRL
Comparator control register
(lower)
R/W
R/W
--000000B
0000D9H
COCRH
Comparator control register
(upper)
R/W
R/W
00011111B
0000DAH
COSRL1
Comparator status register 1
(lower)
R/W
R/W
00000000B
0000DBH
COSRH1
Comparator status register 1
(upper)
R/W
R/W
--000000B
0000DCH
CICRL
Comparator interrupt control
register (lower)
R/W
R/W
0000DDH
CICRH
Comparator interrupt control
register (upper)
R/W
R/W
--000000B
0000DEH
COSRL2
Comparator status register 2
(lower)
R
R
XXXXXXXXB
0000DFH
COSRH2
Comparator status register 2
(upper)
R
R
--XXXXXXB
0000E0H
CIER
Comparator input enable register
R/W
R/W
---11111B
0000E1H
BDR
Bit data register
R/W
R/W
----XXXXB
0000E2H
BRRL
Bit result register (lower)
R
R
0000E3H
BRRH
Bit result register (upper)
R
R
XXXXXXXXB
0000E4H
SMR3
Serial mode register 3
R/W
R/W
00000-00B
0000E5H
SCR3
Serial control register 3
R/W
R/W
00000100B
0000E6H
SIDR3/
SODR3
Input data register 3 /
output data register 3
R/W
R/W
0000E7H
SSR3
Status register 3
R/W
R/W
00001000B
0000E8H
M2CR3
Mode 2 control register 3
R/W
R/W
----1000B
0000E9H
CDCR3
Clock division control register 3
R/W
R/W
Communication
prescaler 3
0---0000B
0000EAH
PDL3
Port 3 data latch register
R/W
R/W
Port 3 data latch
00000000B
Register
0000EBH
to EDH
Resource
name
Voltage
comparator
Bit decoder
UART3
Initial value
00000000B
XXXXXXXXB
XXXXXXXXB
Prohibited area
0000EEH
LCRL*1
LCD control register 0*2
R/W
R/W
0000EFH
LCRH*
1
2
LCD control register 1*
R/W
R/W
0000F0H
to F4H
VRAM*1
LCD display RAM*2
R/W
0000F5H
to F7H
Prohibited area
0000F8H
to FFH
External area
00010000B
LCD controller /
driver
00000000B
XXXXXXXXB
(Continued)
33
MB90370/375 Series
Address
Abbreviation
Register
Byte
Word
access access
Resource
name
Initial value
Program address detection
register 0
R/W
R/W
XXXXXXXXB
Program address detection
register 1
R/W
R/W
XXXXXXXXB
001FF2H
Program address detection
register 2
R/W
R/W
XXXXXXXXB
001FF3H
Program address detection
register 3
R/W
R/W
XXXXXXXXB
Program address detection
register 4
R/W
R/W
XXXXXXXXB
Program address detection
register 5
R/W
R/W
XXXXXXXXB
001FF0H
001FF1H
001FF4H
PADR0
PADR1
001FF5H
ROM correction
003FC0H
UDRL0
UP data register 0 (lower)
R/W
R/W
XXXXXXXXB
003FC1H
UDRH0
UP data register 0 (upper)
R/W
R/W
XXXXXXXXB
003FC2H
UDRL1
UP data register 1 (lower)
R/W
R/W
XXXXXXXXB
003FC3H
UDRH1
UP data register 1 (upper)
R/W
R/W
XXXXXXXXB
003FC4H
UDRL2
UP data register 2 (lower)
R/W
R/W
XXXXXXXXB
003FC5H
UDRH2
UP data register 2 (upper)
R/W
R/W
XXXXXXXXB
003FC6H
UDRL3
UP data register 3 (lower)
R/W
R/W
XXXXXXXXB
003FC7H
UDRH3
UP data register 3 (upper)
R/W
R/W
XXXXXXXXB
003FC8H
UDRL4
UP data register 4 (lower)
R/W
R/W
XXXXXXXXB
003FC9H
UDRH4
UP data register 4 (upper)
R/W
R/W
003FCAH
UDRL5
UP data register 5 (lower)
R/W
R/W
LPC data buffer XXXXXXXXB
array
XXXXXXXXB
003FCBH
UDRH5
UP data register 5 (upper)
R/W
R/W
XXXXXXXXB
003FCCH
UDRL6
UP data register 6 (lower)
R/W
R/W
XXXXXXXXB
003FCDH
UDRH6
UP data register 6 (upper)
R/W
R/W
XXXXXXXXB
003FCEH
UDRL7
UP data register 7 (lower)
R/W
R/W
XXXXXXXXB
003FCFH
UDRH7
UP data register 7 (upper)
R/W
R/W
XXXXXXXXB
003FD0H
UDRL8
UP data register 8 (lower)
R/W
R/W
XXXXXXXXB
003FD1H
UDRH8
UP data register 8 (upper)
R/W
R/W
XXXXXXXXB
003FD2H
UDRL9
UP data register 9 (lower)
R/W
R/W
XXXXXXXXB
003FD3H
UDRH9
UP data register 9 (upper)
R/W
R/W
XXXXXXXXB
(Continued)
34
MB90370/375 Series
(Continued)
Address
Abbreviation
003FD4H
UDRLA
UP data register A (lower)
R/W
R/W
XXXXXXXXB
003FD5H
UDRHA
UP data register A (upper)
R/W
R/W
XXXXXXXXB
003FD6H
UDRLB
UP data register B (lower)
R/W
R/W
XXXXXXXXB
003FD7H
UDRHB
UP data register B (upper)
R/W
R/W
XXXXXXXXB
003FD8H
UDRLC
UP data register C (lower)
R/W
R/W
XXXXXXXXB
003FD9H
UDRHC
UP data register C (upper)
R/W
R/W
XXXXXXXXB
003FDAH
UDRLD
UP data register D (lower)
R/W
R/W
XXXXXXXXB
003FDBH
UDRHD
UP data register D (upper)
R/W
R/W
XXXXXXXXB
003FDCH
UDRLE
UP data register E (lower)
R/W
R/W
XXXXXXXXB
003FDDH
UDRHE
UP data register E (upper)
R/W
R/W
XXXXXXXXB
003FDEH
UDRLF
UP data register F (lower)
R/W
R/W
XXXXXXXXB
003FDFH
UDRHF
UP data register F (upper)
R/W
R/W
XXXXXXXXB
003FE0H
DNDL0
DOWN data register 0 (lower)
R
R
XXXXXXXXB
003FE1H
DNDH0
DOWN data register 0 (upper)
R
R
XXXXXXXXB
003FE2H
DNDL1
DOWN data register 1 (lower)
R
R
003FE3H
DNDH1
DOWN data register 1 (upper)
R
R
003FE4H
DNDL2
DOWN data register 2 (lower)
R
R
XXXXXXXXB
LPC data buffer XXXXXXXXB
array
XXXXXXXXB
003FE5H
DNDH2
DOWN data register 2 (upper)
R
R
XXXXXXXXB
003FE6H
DNDL3
DOWN data register 3 (lower)
R
R
XXXXXXXXB
003FE7H
DNDH3
DOWN data register 3 (upper)
R
R
XXXXXXXXB
003FE8H
DNDL4
DOWN data register 4 (lower)
R
R
XXXXXXXXB
003FE9H
DNDH4
DOWN data register 4 (upper)
R
R
XXXXXXXXB
003FEAH
DNDL5
DOWN data register 5 (lower)
R
R
XXXXXXXXB
003FEBH
DNDH5
DOWN data register 5 (upper)
R
R
XXXXXXXXB
003FECH
DNDL6
DOWN data register 6 (lower)
R
R
XXXXXXXXB
003FEDH
DNDH6
DOWN data register 6 (upper)
R
R
XXXXXXXXB
003FEEH
DNDL7
DOWN data register 7 (lower)
R
R
XXXXXXXXB
003FEFH
DNDH7
DOWN data register 7 (upper)
R
R
XXXXXXXXB
003FF0H
DBAAL
Data buffer array address register
(lower)
R/W
R/W
XXXXXXXXB
003FF1H
DBAAH
Data buffer array address register
(upper)
R/W
R/W
XXXXXXXXB
003FF2H
to
003FFFH
Byte
Word
access access
Register
Resource
name
Initial value
Prohibited area
35
MB90370/375 Series
• Meaning of abbreviations used for reading and writing
R/W : Read and write enabled
R:
Read-only
W:
Write-only
• Explanation of initial values
0:
The bit is initialized to 0.
1:
The bit is initialized to 1.
X:
The initial value of the bit is undefined.
-:
The bit is not used. Its initial value is undefined.
• Instruction using IO addressing e.g. MOV A, io, is not supported for registers area 003FC0H to 003FFFH.
*1 : It doesn’t exist in MB90F377.
*2 : Prohibited area in MB90F377.
36
MB90370/375 Series
■ INTERRUPT FACTORS, INTERRUPT VECTORS, INTERRUPT CONTROL REGISTER
Interrupt cause
EI2OS
support
Interrupt vector
Number
Address
Interrupt control
register
ICR
Address
Reset
X
#08
08H FFFFDCH
INT9 instruction
X
#09
09H
FFFFD8H
Exception processing
X
#10
0AH FFFFD4H
A/D converter conversion termination
#11
0BH FFFFD0H
Timebase timer
#12
0CH FFFFCCH
UPI0 IBF / LPC reset
#13
0DH FFFFC8H
UPI1 IBF
#14
0EH FFFFC4H
UPI2 IBF
#15
0FH
UPI3 IBF
#16
10H FFFFBCH
DTP/ext. interrupt channels 0/1 detection
#17
11H
FFFFB8H
DTP/ext. interrupt channels 2/3 detection
#18
12H
FFFFB4H
DTP/ext. interrupt channels 4/5 detection
#19
13H
FFFFB0H
Wake-up interrupt detection
#20
14H FFFFACH
UPI0/1/2/3 OBE
#21
15H
FFFFA8H
16-bit PPG timer 1
#22
16H
FFFFA4H
PS/2 interface 0/1
#23
17H
FFFFA0H
PS/2 interface 2
#24
18H
FFFF9CH
Watch timer
#25
19H
FFFF98H
I2C transfer complete / bus error
#26
1AH
FFFF94H
16-bit PPG timer 2/3
#27
1BH
FFFF90H
Voltage comparator 1
#28
1CH FFFF8CH
MI2C transfer complete / bus error
#29
1DH
FFFF88H
Voltage comparator 2
#30
1EH
FFFF84H
I2C timeout / standby wake-up
#31
1FH
FFFF80H
16-bit reload timer 1/2 underflow
#32
20H
FFFF7CH
MI2C timeout / standby wake-up
#33
21H
FFFF78H
16-bit reload timer 3/4 underflow
#34
22H
FFFF74H
UART1 receive
#35
23H
FFFF70H
UART1 send
#36
24H
FFFF6CH
UART2 receive
#37
25H
FFFF68H
UART2 send
#38
26H
FFFF64H
UART3 receive
#39
27H
FFFF60H
UART3 send
#40
28H
FFFF5CH
Flash memory status
#41
29H
FFFF58H
Delayed interrupt generator module
#42
2AH
FFFF54H
FFFFC0H
Priority*2
High
ICR00 0000B0H*1
ICR01 0000B1H*1
ICR02 0000B2H*1
ICR03 0000B3H*1
ICR04 0000B4H*1
ICR05 0000B5H*2
ICR06 0000B6H*1
ICR07 0000B7H*1
ICR08 0000B8H*1
ICR09 0000B9H*1
ICR10 0000BAH*1
ICR11 0000BBH*1
ICR12 0000BCH*1
ICR13 0000BDH*1
ICR14 0000BEH*1
ICR15 0000BFH*1
Low
37
MB90370/375 Series
: Can be used and interrupt request flag is cleared by EI2OS interrupt clear signal.
× : Cannot be used.
: Can be used and support the EI2OS stop request.
: Can be used.
*1 : • For peripheral functions that share the ICR register, the interrupt level will be the same.
• If the extended intelligent I/O service is to be used with a peripheral function that shares the ICR register with
another peripheral function, the service can be started by either of the function. And if EI2OS clear is supported,
both interrupt request flags for the two interrupt causes are cleared by EI2OS interrupt clear signal. It is
recommended to mask either of the interrupt request during the use of EI2OS.
• EI2OS service cannot be started multiple times simultaneously. Interrupt other than the operating interrupt is
masked during EI2OS operation. It is recommended to mask either of the interrupt requests during the use
of EI2OS.
*2 : This priority is applied when interrupts of the same level occur simultaneously.
38
MB90370/375 Series
■ PERIPHERAL RESOURCES
1. Low-power Consumption Control Circuit
The MB90370/375 series has the following CPU operating mode selected by the configuration of an operating
clock and clock operation control.
• Clock Mode
• PLL clock mode
In this mode, a PLL clock that is a multiple of the oscillation clock (HCLK) is used to operate the CPU and
peripheral functions.
• Main clock mode
In this mode, the main clock, with the oscillation clock (HCLK) frequency divided by 2 is used to operate
the CPU and peripheral functions. In the main clock mode, the PLL multiplier circuit is inactive.
• Sub-clock mode
In this mode, the sub-clock, with the sub-clock (SCLK) frequency divided by 4 is used to operate the CPU
and peripheral functions. In the sub-clock mode, the main clock and PLL multiplier circuit are inactive.
• CPU Intermittent Operating Mode
In this mode, the CPU is operated intermittently while high-speed clock pluses are supplied to peripheral functions, thereby reducing power consumption. In this mode, intermittent clock pulses are supplied only to the CPU
while it is accessing a register, internal memory, or peripheral function.
• Standby Mode
In this mode, the low-power consumption control circuit stops supplying the clock to the CPU (sleep mode) or
the CPU and peripheral functions (timebase timer mode) or stops the oscillation clock itself (stop mode) , thereby
reducing power consumption.
• PLL sleep mode
The PLL sleep mode is activated to stop the CPU operating clock in the PLL clock mode. Components
excluding the CPU operate on the PLL clock.
• Main sleep mode
The main sleep mode is activated to stop the CPU operating clock in the main clock mode. Components
excluding the CPU operate on the main clock.
• Sub-sleep mode
The sub-sleep mode is activated to stop the CPU operating clock in the sub-clock mode. Components
excluding the CPU operate on the divided-by-four sub-clock.
• Timebase timer mode
The timebase timer mode causes the operation of functions, excluding the oscillation clock, timebase timer,
and watch timer, to stop. All functions other than the timebase timer and watch timer are inactivated.
• Watch mode and main watch mode
The watch mode and main watch mode operates the watch timer only. The sub-clock operates but the
main clock and PLL multiplier circuit stop.
• Stop mode
The stop mode causes the oscillation to stop. All functions are inactivated.
Note : Because the stop mode turns the oscillation clock off, data can be retained by the lowest power consumption.
39
MB90370/375 Series
(1) Register configuration
Clock Selection Register
Address : 0000A1H
Read/write
Initial value
15
14
13
12
11
10
9
8
SCM
MCM
WS1
WS0
SCS
MCS
CS1
CS0
R
1
R
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
0
R/W
0
Bit number
CKSCR
Lower Power Consumption Mode Control Register
Address : 0000A0H
Read/write
Initial value
7
6
5
4
3
2
1
0
STP
SLP
SPL
RST
TMD
CG1
CG0
Reserved
W
0
W
0
R/W
0
W
1
W
1
R/W
0
R/W
0
R/W
0
Bit number
LPMCR
(2) Block diagram
Low power consumption mode control register (LPMCR)
STP SLP SPL RST TMD CG1 CG0 RESV
Pin highimpedance
control circuit
RST
Internal reset
Internal reset
generation
circuit
Intermittent cycle
selection
Pin
CPU intermittent
operation selector
CPU clock
control circuit
2
Standby
control circuit
Interrupt clearing
Pin Hi-Z control
CPU clock pulse
Stop and sleep signals
Stop signal
Machine clock
Oscillation stabilization wait clearing
Clock generation part
Peripheral
clock control
circuit
Oscillation
stabilization
wait time
selector
Clock selector
2
Divideby-4
Subclock
2
PLL multiplier
circuit
Subclock
generation
circuit
X0A Pin
X1A Pin
System clock
generation
circuit
X0 Pin
SCM MCM WS1 WS0 SCS MCS CS1 CS0
Clock selection register (CKSCR)
Divideby-2
Main clock
X1 Pin
40
Peripheral clock
Divideby-8
Divideby-16
Divideby-128
Divideby-4
Divideby-4
Timebase timer
MB90370/375 Series
2. I/O Ports
(1) Outline of I/O ports
Each I/O port outputs data from the CPU to the I/O pins or inputs signals from the I/O pins to the CPU as directed
by the port data register (PDR) . Each CMOS I/O port can also designate the direction of a data flow (input or
output) at the I/O pins in bit units using the port data direction register (DDR) . Or N-channel open-drain port
can designate the direction of a data flow (input or output) at the I/O pins in bit units using the port data register
(PDR) . The function of each port and the resources using it are described below :
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
Port 8
Port 9
Port A
Port B
Port C
Port D
Port E
Port F
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
General-purpose I/O port/resource (Key-on wake-up interrupt)
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port/resource (A/D converter external trigger)
General-purpose I/O port/resource (PS/2 interface / serial IRQ controller)
General-purpose I/O port/resource (LPC interface)
General-purpose I/O port/resource (DTP / UART1)
General-purpose I/O port/resource (UART1 / UART2 / UART3 / PPG1)
General-purpose I/O port/resource (Multi-address I2C)
General-purpose I/O port/resource (I2C / Multi-address I2C)
General-purpose I/O port/resource (Comparator)
General-purpose I/O port/resource (Comparator)
General-purpose I/O port/resource (Comparator / A/D converter)
General-purpose I/O port/resource (A/D converter / D/A converter / PPG2 / PPG3)
General-purpose I/O port/resource (Reload timer1 to 4 / LCD controller*)
General-purpose I/O port/resource (LCD controller*)
* : LCD controller doesn’t exist in MB90F377, and so Port E and F of MB90F377 are not used for this purpose.
(2) Register configuration
Register
Read/Write
Address
Initial value
Port 0 data register (PDR0)
R/W
000000H
XXXXXXXXB
Port 1 data register (PDR1)
R/W
000001H
XXXXXXXXB
Port 2 data register (PDR2)
R/W
000002H
XXXXXXXXB
Port 3 data register (PDR3)
R/W
000003H
XXXXXXXXB
Port 4 data register (PDR4)
R/W
000004H
X1111111B
Port 5 data register (PDR5)
R/W
000005H
XXXXXXXXB
Port 6 data register (PDR6)
R/W
000006H
XXXXXXXXB
Port 7 data register (PDR7)
R/W
000007H
XXXXXXXXB
Port 8 data register (PDR8)
R/W
000008H
-----111B
Port 9 data register (PDR9)
R/W
000009H
--111111B
Port A data register (PDRA)
R/W
00000AH
-XXXXXXXB
Port B data register (PDRB)
R/W
00000BH
XXXXXXXXB
Port C data register (PDRC)
R/W
00000CH
XXXXXXXXB
Port D data register (PDRD)
R/W
00000DH
XXXXXXXXB
Port E data register (PDRE)
R/W
00000EH
XXXXXXXXB
(Continued)
41
MB90370/375 Series
(Continued)
Register
Read/Write
Address
Initial value
Port F data register (PDRF)
R/W
00000FH
XXXXXXXXB
Port 0 data direction register (DDR0)
R/W
000010H
00000000B
Port 1 data direction register (DDR1)
R/W
000011H
00000000B
Port 2 data direction register (DDR2)
R/W
000012H
00000000B
Port 3 data direction register (DDR3)
R/W
000013H
00000000B
Port 4 data direction register (DDR4)
R/W
000014H
0-------B
Port 5 data direction register (DDR5)
R/W
000015H
00000000B
Port 6 data direction register (DDR6)
R/W
000016H
00000000B
Port 7 data direction register (DDR7)
R/W
000017H
00000000B
Port A data direction register (DDRA)
R/W
00001AH
-0000000B
Port B data direction register (DDRB)
R/W
00001BH
00000000B
Port C data direction register (DDRC)
R/W
00001CH
00000000B
Port D data direction register (DDRD)
R/W
00001DH
00000000B
Port E data direction register (DDRE)
R/W
00001EH
00000000B
Port F data direction register (DDRF)
R/W
00001FH
00000000B
Analog data input enable register (ADER1)
R/W
00002AH
11111111B
Analog data input enable register (ADER2)
R/W
00002BH
----1111B
Comparator input enable register (CIER)
R/W
0000E0H
---11111B
LCD control register 1 (LCRH)
R/W
0000EFH
00000000B
Port 0 pull-up resistor setting register (RDR0)
R/W
00008CH
00000000B
Port 1 pull-up resistor setting register (RDR1)
R/W
00008DH
00000000B
Port 2 pull-up resistor setting register (RDR2)
R/W
00008EH
00000000B
Port 3 pull-up resistor setting register (RDR3)
R/W
00008FH
00000000B
Port 3 data latch register (PDL3)
R/W
0000EAH
00000000B
R/W
X
-
42
: Read/write enabled
: Undefined
: Not used
MB90370/375 Series
(3) Block diagram of I/O ports
• Block diagram of port 0 pins
RDR
Resource input
Port data register (PDR)
Pull-up resistor
About 50 kΩ
Internal data bus
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL = 1)
• Block diagram of port 1 pins
RDR
Port data register (PDR)
Pull-up resistor
About 50 kΩ
Internal data bus
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL = 1)
43
MB90370/375 Series
• Block diagram of port 2 pins
RDR
Port data register (PDR)
Pull-up resistor
About 50 kΩ
Internal data bus
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL = 1)
• Block diagram of port 3 pins
RDR
Port data register (PDR)
Resource input
Pull-up resistor
About 50 kΩ
Internal data bus
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL = 1)
Port data latch register (PDL)
Input latch
44
R
MB90370/375 Series
• Block diagram of port 47 pin
Resource output
Resource input
Resource output enable
Port data register (PDR)
Internal data bus
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL = 1)
• Block diagram of port 46 pin
Resource output
Resource input
Resource output enable
Port data register (PDR)
Internal data bus
PDR read
Output latch
PDR write
Pin
Read-Modify-Write instruction
Standby control (SPL = 1)
45
MB90370/375 Series
• Block diagram of port 45 to 40 pins
Resource output
Resource input
Resource output enable
Port data register (PDR)
Internal data bus
PDR read
Output latch
PDR write
Pin
Read-Modify-Write instruction
Standby control (SPL = 1)
• Block diagram of port 5 pins
Resource output
Resource input
Resource output enable
Port data register (PDR)
Internal data bus
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
46
Standby control (SPL = 1)
MB90370/375 Series
• Block diagram of port 6 pins
Resource output
Resource input
Resource output enable
Port data register (PDR)
Internal data bus
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL = 1)
• Block diagram of port 7 pins
Resource output
Resource input
Resource output enable
Port data register (PDR)
Internal data bus
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL = 1)
47
MB90370/375 Series
• Block diagram of port 8 pins
Resource output
Resource input
Resource output enable
Port data register (PDR)
Internal data bus
PDR read
Output latch
PDR write
Pin
Read-Modify-Write instruction
Standby control (SPL = 1)
• Block diagram of port 9 pins
Resource output
Resource input
Resource output enable
Port data register (PDR)
Internal data bus
PDR read
Output latch
PDR write
Pin
Read-Modify-Write instruction
Standby control (SPL = 1)
48
MB90370/375 Series
• Block diagram of port A pins
Resource output
Resource output enable
Port data register (PDR)
Internal data bus
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL = 1)
• Block diagram of port B pins
CIER
Port data register (PDR)
Internal data bus
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
Standby control (SPL = 1)
DDR read
Comparator
operation
enable
Comparator input
49
MB90370/375 Series
• Block diagram of port C7 to C3 pins
ADER
Port data register (PDR)
Internal data bus
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
Standby control (SPL = 1)
A/D converter
channel
selection bit
DDR read
to A/D converter analog input
• Block diagram of port C2 to C0 pins
CIER
Comparator
ADER
Comparator operation
enable bit
(COCRH)
Port data register (PDR)
Internal data bus
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
A/D converter
channel
selection bit
DDR write
Standby control (SPL = 1)
DDR read
to A/D converter analog input
50
MB90370/375 Series
• Block diagram of port D7 and D6 pins
Resource output
Resource output enable
Port data register (PDR)
Internal data bus
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL = 1)
• Block diagram of port D5 and D4 pins
Port data register (PDR)
Internal data bus
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL = 1)
Analog output
D/A output enable
51
MB90370/375 Series
• Block diagram of port D3 to D0 pins
ADER
A/D input
Port data register (PDR)
Internal data bus
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
Standby control (SPL = 1)
DDR read
• Block diagram of port E pins (not for MB90F377)
Resource output
Resource input
Resource output enable
Port data register (PDR)
Internal data bus
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL = 1)
LCD output
LCD output enable
52
MB90370/375 Series
• Block diagram of port F7 to F5 pins (not for MB90F377)
LCRH
VS
LCD input (V1 to V3)
Port data register (PDR)
Internal data bus
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
Standby control (SPL = 1)
DDR read
• Block diagram of port F4 to F0 pins (not for MB90F377)
Port data register (PDR)
Internal data bus
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL = 1)
LCD output
LCD output enable
53
MB90370/375 Series
3. Timebase timer
The timebase timer is an 18-bit free-running counter (timebase counter) that counts up in synchronization with
the internal count clock (one-half of the source oscillation) .
Features of timebase timer :
• Interrupt generated when counter overflow
• EI2OS supported
• Interval timer function :
An interrupt generated at four different time intervals
• Clock supply function :
Four different clocks can be selected as watchdog timer’s count clock.
Supply clock for oscillation stabilization
(1) Register configuration
Timebase Timer Control Register
Address : 0000A9H
Read/write
Initial value
15
14
13
12
11
10
9
8
Reserved
TBIE
TBOF
TBR
TBC1
TBC0
R/W
1
R/W
0
R/W
0
R/W
1
R/W
0
R/W
0
Bit number
TBTC
(2) Block diagram of timebase timer
To watchdog timer
Timebase
timer counter
Divide-by
-two HCLK
×21 ×22 ×23
×27 × 28 ×29 ×210 ×211 ×212 ×213 ×214 ×215 ×216 ×217 ×218
OF
OF
OF
OF
To the oscillation
stabilization wait
time selector in the
clock control
section
Power-on reset
Stop mode start
CKSCR : MCS = 1 → 0 (*1)
SCS = 1 → 0 (*2)
Counter
clear circuit
Interval
timer selector
TBOF set
Timebase timer
interrupt signal
#12 (0CH)
RESV
TBIE TBOF TBR TBC1 TBC0
Timebase timer interrupt register (TBTC)
: Unused
OF : Overflow
HCLK : Oscillation clock
*1 : Switching of the machine clock from the oscillation clock to the PLL clock
*2 : Switching from main clock to sub-clock
54
MB90370/375 Series
4. Watchdog timer
The watchdog timer is a 2-bit counter that uses the timebase timer’s supply clock as the count clock. After
activation, if the watchdog timer is not cleared within a given period, the CPU will be reset.
• Features of watchdog timer :
Reset CPU at four different time intervals
Status bits to indicate the reset causes
(1) Register configuration of watchdog timer
Watchdog Timer Control Register
Address : 0000A8H
Read/write
Initial value
7
6
5
4
3
2
1
0
PONR
WRST
ERST
SRST
WTE
WT1
WT0
R
X
R
X
R
X
R
X
W
1
W
1
W
1
Bit number
WDTC
(2) Block diagram of watchdog timer
Watchdog timer control register (WDTC)
PONR
Watchdog timer
WRST ERST SRST WTE
WT1
WDCS (from watch timer
control register, WTC)
WT0
2
Activation with CLR
Start of watch mode
Start of sleep mode
Start of stop mode
reset generation
Counter
clear control
circuit
Count
clock
selector
2-bit
counter
CLR
Overflow Watchdog
reset
generator
CLK
To the
internal
reset
generator
4
4
(Timebase timer counter)
One-half of HCLK
×21 ×22
Sub-clock divide by 4
×21 ×22
×28 ×29 ×210 ×211 ×212 ×213 ×214 ×215 ×216 ×217 ×218
×210 ×211 ×212 ×213 ×214 ×215
Watch timer counter
HCLK : Oscillation clock
55
MB90370/375 Series
5. Watch timer
The watch timer is a 15-bit timer that uses sub-clocks and can generate an interval interrupt. It can also be used
as the watchdog timer clock source and sub-clock oscillation wait time.
Features of the watch timer :
• Provides the watchdog timer clock source
• Sub-clock oscillation stabilization wait timer function
• Interval timer function that generates interrupts in a given cycle
(1) Register configuration of watch timer
Watch Timer Control Register
Address : 0000AAH
Read/write
Initial value
7
6
5
4
3
2
1
0
WDCS
SCE
WTIE
WTOF
WTR
WTC2
WTC1
WTC0
R/W
1
R
0
R/W
0
R/W
0
W
1
R/W
0
R/W
0
R/W
0
Bit number
WTC
(2) Block diagram of watch timer
Watch timer control register (WTC)
WDCS
SCE
WTIE
WTOF
WTR
Clear
The subclock
divided by 4
WTC1
WTC0
28
29
210
211
212
Watch counter
WTC2
213
214
Interval selector
Interrupt
generator
Watch
timer
interrupt
215
210
213
214
215
To the
watchdog
timer
56
MB90370/375 Series
6. 16-bit PPG timer (×
× 3)
The 16-bit PPG (Programmable Pulse Generator) timer consists of a 16-bit down counter, prescaler, 16-bit
period setting register, 16-bit duty setting register, 16-bit control register and a PPG output pin.
Features of 16-bit PPG timer :
• 8 types of counter operation clock (φ, φ/2, φ/4, φ/8, φ/16, φ/32, φ/64, φ/128) can be selected (φ is the machine clock)
• An interrupt is generated when there is a trigger or a counter borrow or when PPG rising (normal polarity) /
PPG falling (inverted polarity) .
• PPG output operation
The 16-bit PPG timer can output pulse waveforms with variable period and duty ratio. Also, it can be used as
D/A converter in conjunction with an external circuit.
(1) Register configuration of PPG timer
PPG Down Counter Register (Upper)
Address : ch1 000039H
15
14
13
12
11
10
9
8
ch2 000041H
ch3 000049H
DC15
DC14
DC13
DC12
DC11
DC10
DC09
DC08
Read/write
Initial value
R
1
R
1
R
1
R
1
R
1
R
1
R
1
R
1
PPG Down Counter Register (Lower)
Address : ch1 000038H
7
6
5
4
3
2
1
0
ch2 000040H
ch3 000048H
DC07
DC06
DC05
DC04
DC03
DC02
DC01
DC00
Read/write
Initial value
R
1
R
1
R
1
R
1
R
1
R
1
R
1
W
X
W
X
W
X
W
X
W
X
W
X
W
X
W
X
W
X
W
X
W
X
W
X
W
X
W
X
Bit number
PCSRH1 to
PCSRH3
W
X
PPG Period Setting Buffer Register (Lower)
Address : ch1 00003AH
7
6
5
4
3
2
1
0
ch2 000042H
ch3 00004AH
CS07
CS06
CS05
CS04
CS03
CS02
CS01
CS00
Read/write
Initial value
Bit number
PDCRL1 to
PDCRL3
R
1
PPG Period Setting Buffer Register (Upper)
Address : ch1 00003BH
15
14
13
12
11
10
9
8
ch2 000043H
ch3 00004BH
CS15
CS14
CS13
CS12
CS11
CS10
CS09
CS08
Read/write
Initial value
Bit number
PDCRH1 to
PDCRH3
Bit number
PCSRL1 to
PCSRL3
W
X
(Continued)
57
MB90370/375 Series
(Continued)
PPG Duty Setting Buffer Register (Upper)
Address : ch1 00003DH
15
14
13
12
11
10
9
8
ch2 000045H
ch3 00004DH
DU15
DU14
DU13
DU12
DU11
DU10
DU09
DU08
Read/write
Initial value
W
X
W
X
W
X
W
X
W
X
W
X
W
X
W
X
PPG Duty Setting Buffer Register (Lower)
Address : ch1 00003CH
7
6
5
4
3
2
1
0
ch2 000044H
ch3 00004CH
DU07
DU06
DU05
DU04
DU03
DU02
DU01
DU00
Read/write
Initial value
W
X
W
X
W
X
W
X
W
X
W
X
W
X
R/W
0
R/W
0
PPG Control Status Register (Lower)
Address : ch1 00003EH
7
ch2 000046H
ch3 00004EH
Read/write
Initial value
R/W
0
6
R/W
0
5
R/W
0
4
R/W
0
3
R/W
0
2
Bit number
PDUTL1 to
PDUTL3
W
X
PPG Control Status Register (Upper)
Address : ch1 00003FH
15
14
13
12
11
10
9
8
ch2 000047H
ch3 00004FH
CNTE
STGR MDSE RTRG
CKS2
CKS1
CKS0 PGMS
Read/write
Initial value
Bit number
PDUTH1 to
PDUTH3
Bit number
PCNTH1 to
PCNTH3
R/W
0
1
0
IREN
IRQF
IRS1
IRS0
POEN
OSEL
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit number
PCNTL1 to
PCNTL3
Note : Registers PDCR1 to PDCR3, PCSR1 to PCSR3 and PDUT1 to PDUT3 are word access only.
58
MB90370/375 Series
(2) Block diagram of PPG timer
Period setting buffer
register 1/2/3
Duty setting buffer
register 1/2/3
Prescaler
CLK
LOAD
16-bit down counter
STOP
START BORROW
MDSE PGMS OSEL POEN
P77/PPG1
or
PD6/PPG2
or
PD7/PPG3
Pin
Machine clock φ
S
Down counter
register 1/2/3
Q
R
Interrupt
selection
Gate input
F2MC-16LX bus
1/1
1/2
1/4
1/8
1/16
1/32
1/64
1/128
Duty setting
register 1/2/3
Comparator
Period setting
register 1/2/3
CKS2 CKS1 CKS0
Interrupt
#22 (for PPG1)
or
#27 (for PPG2/3)
IRS1 IRS0 IRQF IREN
STGR CNTE RTRG
59
MB90370/375 Series
7. 16-bit reload timer (×
× 4)
The 16-bit reload timer provides two operating modes, internal clock mode and event count mode. In each
operating mode, the 16-bit down counter can be reloaded (reload mode) or stopped when underflow (one-shot
mode) .
Output pins TO1 to TO4 are able to output different waveform according to the counter operating mode. TO1 to
TO4 toggles when counter underflow if counter is operated as reload mode. TO1 to TO4 output specified level
(“H” or “L”) when counter is counting if the counter is in one-shot mode.
Features of the 16-bit reload timer :
• Interrupt generated when timer underflow
• EI2OS supported
• Internal clock operating mode :
Three internal count clocks can be selected.
Counter can be activated by software or external trigger (signal at TIN1 to TIN4 pin) .
Counter can be reloaded or stopped when underflow after activated.
• Event count operating mode :
Counter counts down by one when specified edge at TIN1 to TIN4 pin.
Counter can be reloaded or stopped when underflow.
(1) Register configuration of reload timer
Timer Control Status Register (Upper)
Address : ch1 000071H
ch2 000075H
15
14
ch3 000079H
ch4 00007DH
Read/write
Initial value
Timer Control Status Register (Lower)
Address : ch1 000070H
ch2 000074H
7
6
ch3 000078H
MOD0
OUTE
ch4 00007CH
Read/write
R/W
R/W
0
0
Initial value
13
12
11
10
9
8
CSL1
CSL0
MOD2
MOD1
R/W
0
R/W
0
R/W
0
R/W
0
5
4
3
2
1
0
OUTL
RELD
INTE
UF
CNTE
TRG
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
16-bit Timer Register / 16-bit Reload Register (Upper)
Address : ch1 000073H
ch2 000077H
15
14
13
12
ch3 00007BH
D15
D14
D13
D12
ch4 00007FH
Read/write
R/W
R/W
R/W
R/W
Initial value
X
X
X
X
16-bit Timer Register / 16-bit Reload Register (Lower)
Address : ch1 000072H
ch2 000076H
7
6
5
4
ch3 00007AH
D07
D06
D05
D04
ch4 00007EH
Read/write
R/W
R/W
R/W
R/W
Initial value
X
X
X
X
60
11
10
9
8
D11
D10
D09
D08
R/W
X
R/W
X
R/W
X
R/W
X
3
2
1
0
D03
D02
D01
D00
R/W
X
R/W
X
R/W
X
R/W
X
Bit number
TMCSRH1 to
TMCSRH4
Bit number
TMCSRL1 to
TMCSRL4
Bit number
TMR1 to TMR4/
TMRD1 to
TMRD4
Bit number
TMR1 to TMR4/
TMRD1 to
TMRD4
MB90370/375 Series
(2) Block diagram of reload timer
F2MC-16LX Bus
TMRD1*1
<TMRD2, 3, 4>
16-bit reload register
Reload signal
TMR1*1
<TMR2, 3, 4>
Reload
control
circuit
16-bit timer register
CLK
Count clock generation
circuit
Machine
clock
Prescaler
3
Gate
input
Valid
clock
judgment
circuit
Pin
Input
control
circuit
To UART1*1
<UART2, UART3,
A/D converter>
CLK
Clear
PE0/TIN1/SEG0
PE2/TIN2/SEG2
PE4/TIN3/SEG4
PE6/TIN4/SEG6
Wait signal
Output control circuit
Internal
clock
External clock
3
2
Clock
selector
Output signal
generation
Invert circuit
Select
signal
Function selection
CSL1 CSL0 MOD2 MOD1 MOD0 OUTE OUTL RELD INTE
Timer control status register TMCSR1*1
<TMCSR2,3,4>
Pin
EN
PE1/TO1/SEG1
PE3/TO2/SEG3
PE5/TO3/SEG5
PE7/TO4/SEG7
Operation
control
circuit
UF CNTE TRG
Interrupt request signal
#32 (20H)*1, *2
<#34 (22H)>
*1 : This register includes channel 1, 2, 3 and 4. The register enclosed in “<” and “>” indicates the
channel 2, 3 and 4 register.
*2 : Interrupt numbers : channel 1 and 2 share one interrupt number, channel 3 and 4 share another.
61
MB90370/375 Series
8. I2C
The I2C (Inter IC Bus) interface is a simple structure bidirectional bus consisting of two wires : a serial data line
(SDA) and a serial clock line (SCL) . Among the devices connected with these two wires, information is transmitted
to one another. By recognizing the unique address of each device, it can operate as a transmitting or receiving
device in accordance with the function of each device. Among these devices, the master/slave relation is established.
The I2C interface can connect two or more devices to the bus provided the upper limit of the bus capacitance
does not exceed 400 pF. It is a full-fledged multi-master bus equipped with collision detection and communication
adjustment procedures designed to avoid the destruction of data if two or more masters attempt to start data
transfer simultaneously.
The communication adjustment procedure permits only one master to control the bus when two or more masters
attempt to control the bus so that messages are not lost or the contents of messages are not changed. Multimaster means that multiple masters attempt to control the bus simultaneously without losing messages.
This I2C interface includes MCU standby mode wake-up function, and a CRC-8 calculator that performs automatic
Packet Error Code (PEC) generation and verification.
(1) Register configuration of I2C
I2C Bus Control Register (Lower)
7
6
5
4
3
2
1
0
Address : 000080H
RES
PECE
LBT
WUE
Read/write
Initial value
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
Address : 000081H
BER
BEIE
SCC
MSS
ACK
GCAA
INTE
INT
Read/write
Initial value
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
3
2
1
0
BB
RSC
AL
LRB
TRX
AAS
GCA
FBT
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
15
14
13
12
11
10
9
8
Address : 000083H
PMATCH
WUF
TDR
TCR
MTR
STR
Read/write
Initial value
R
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
Bit number
IBCRL
I2C Bus Control Register (Upper)
Bit number
IBCRH
I2C Bus Status Register (Lower)
Address : 000082H
Read/write
Initial value
Bit number
IBSRL
I2C Bus Status Register (Upper)
Bit number
IBSRH
I2C Data Register
Address : 000084H
Read/write
Initial value
Bit number
IDAR
(Continued)
62
MB90370/375 Series
(Continued)
I2C Address Register
15
14
13
12
11
10
9
8
Address : 000085H
A6
A5
A4
A3
A2
A1
A0
Read/write
Initial value
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
7
6
5
4
3
2
1
0
DMBP
EN
CS4
CS3
CS2
CS1
CS0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
Address : 000087H
AAC
TOE
EXT
TS2
TS1
TS0
Read/write
Initial value
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
3
2
1
0
C7
C6
C5
C4
C3
C2
C1
C0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
D7
D6
D5
D4
D3
D2
D1
D0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
3
2
1
0
S6
S6
S5
S4
S3
S2
S1
S0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
Address : 00008BH
M7
M6
M5
M4
M3
M2
M1
M0
Read/write
Initial value
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit number
IADR
I2C Clock Control Register
Address : 000086H
Read/write
Initial value
Bit number
ICCR
I2C Timeout Control Register
Bit number
ITCR
I2C Timeout Clock Register
Address : 000088H
Read/write
Initial value
Bit number
ITOC
I2C Timeout Data Register
Address : 000089H
Read/write
Initial value
Bit number
ITOD
I2C Slave Timeout Register
Address : 00008AH
Read/write
Initial value
Bit number
ISTO
I2C Master Timeout Register
Bit number
IMTO
63
MB90370/375 Series
(2) Block diagram of I2C
I2C enable
ICCR
Peripheral clock
Clock frequency divider 1
DMBP
6
5
7
8
EN
Clock selector 1
CS4
CS3
Clock frequency divider 2
CS2
CS1
CS0
4
16
8
32
64
128
256
Sync
512
Shift clock
generator
Clock selector 2
IBSRL
Shift clock edge
BB
RSC
LRB
Bus busy
Repeat start
Start/stop condition
detector
Last bit
Transmission/
reception
Error
TRX
First byte
FBT
F2MC16LX Internal bus
AL
Arbitration lost detector
IBCRH
BER
BEIE
Interrupt #26
INTE
INT
End
Start
SCC
Master
Enables ACK
MSS
ACK
Start/stop condition
generator
Enables GC-ACK
GCAA
CRC-8 calculator
IBCRL
LBT
IDAR register
IBSRL
Slave
AAS
GCA
Slave address comparator
General call
IADR register
ITCR
Timeout detector
SCL line
IBSRH
TDR
TCR
MTR
SDA line
STR
ITOD
IBCRL
ITOC
ISTO
IMTO
64
Interrupt #31
WUE
WUF
IBSRH
MB90370/375 Series
9. MI2C
The Multi-address I2C (Inter IC Bus) interface is a simple structure bidirectional bus consisting of two wires : a
serial data line (SDA) and a serial clock line (SCL) . Among the devices connected with these two wires,
information is transmitted to one another. By recognizing the unique address of each device, it can operate as
a transmitting or receiving device in accordance with the function of each device. Among these devices, the
master/slave relation is established.
The Multi-address I2C interface can connect two or more devices to the bus provided the upper limit of the bus
capacitance does not exceed 400 pF. It is a full-fledged multi-master bus equipped with collision detection and
communication adjustment procedures designed to avoid the destruction of data if two or more masters attempt
to start data transfer simultaneously. This macro provides 6 addresses to implement the multi-address function.
The communication adjustment procedure permits only one master to control the bus when two or more masters
attempt to control the bus so that messages are not lost or the contents of messages are not changed. Multimaster means that multiple masters attempt to control the bus simultaneously without losing messages.
This Multi-address I2C interface includes MCU standby mode wake-up function, and a CRC-8 calculator that
performs automatic Packet Error Code (PEC) generation and verification.
(1) Register configuration of MI2C
Multi-address I2C Bus Control Register (Lower)
7
6
5
4
3
2
1
0
Address : 0000C0H
RES
PECE
LBT
WUE
Read/write
Initial value
R/W
0
R/W
0
R/W
0
R/W
0
Bit number
MBCRL
Multi-address I2C Bus Control Register (Upper)
15
14
13
12
11
10
9
8
Address : 0000C1H
BER
BEIE
SCC
MSS
ACK
GCAA
INTE
INT
Read/write
Initial value
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit number
MBCRH
Multi-address I2C Bus Status Register (Lower)
Address : 0000C2H
Read/write
Initial value
7
6
5
4
3
2
1
0
BB
RSC
AL
LRB
TRX
AAS
GCA
FBT
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Bit number
MBSRL
Multi-address I2C Bus Status Register (Upper)
15
14
13
12
11
10
9
8
Address : 0000C3H
PMATCH
WUF
TDR
TCR
MTR
STR
Read/write
Initial value
R
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
Bit number
MBSRH
Multi-address I2C Data Register
Address : 0000C4H
Read/write
Initial value
Bit number
MDAR
(Continued)
65
MB90370/375 Series
Multi-address I2C Alert Register
15
14
13
12
11
10
9
8
Address : 0000C5H
ARAE
ARO
ARF
AEN
Read/write
Initial value
R/W
0
R/W
0
R/W
0
R/W
0
Multi-address I2C Address Register 1/3/5
Address ch1 : 0000C6H
7
6
5
Address ch3 : 0000C8H
Address ch5 : 0000CAH
A6
A5
4
A4
3
A3
2
A2
1
A1
Bit number
MALR
0
A0
Read/write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
X
X
X
X
X
X
X
Initial value
2C Address Register 2/4/6
Multi-address I
Address ch2 : 0000C7H
15
14
13
12
11
10
9
8
Address ch4 : 0000C9H
Address ch6 : 0000CBH
A5
A4
A3
A2
A1
A0
A6
Read/write
R/W
X
Initial value
2C Clock Control Register
Multi-address I
Address :0000CCH
Read/write
Initial value
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
7
6
5
4
3
2
1
0
DMBP
EN
CS4
CS3
CS2
CS1
CS0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit number
MADR1/3/5
Bit number
MADR2/4/6
Bit number
MCCR
Multi-address I2C Timeout Control Register
15
14
13
12
11
10
9
8
Address :0000CDH
AAC
TOE
EXT
TS2
TS1
TS0
Read/write
Initial value
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit number
MTCR
Multi-address I2C Timeout Clock Register
Address : 0000CEH
Read/write
Initial value
7
6
5
4
3
2
1
0
C7
C6
C5
C4
C3
C2
C1
C0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit number
MTOC
Multi-address I2C Timeout Data Register
Address : 0000CFH
Read/write
Initial value
15
14
13
12
11
10
9
8
D7
D6
D5
D4
D3
D2
D1
D0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit number
MTOD
(Continued)
66
MB90370/375 Series
(Continued)
Multi-address I2C Slave Timeout Register
Address : 0000D0H
Read/write
Initial value
7
6
5
4
3
2
1
0
S6
S6
S5
S4
S3
S2
S1
S0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit number
MSTO
Multi-address I2C Master Timeout Register
15
14
13
12
11
10
9
8
Address : 0000D1H
M7
M6
M5
M4
M3
M2
M1
M0
Read/write
Initial value
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit number
MMTO
67
MB90370/375 Series
(2) Block diagram of MI2C
Multi-address I2C enable
MCCR
DMBP
Peripheral clock
Clock frequency divider 1
6
5
7
8
EN
Clock selector 1
CS4
CS3
Clock frequency divider 2
CS2
CS1
CS0
4
16
8
32
64
128
256
Sync
512
Shift clock
generator
Clock selector 2
MBSRL
Shift clock edge
BB
RSC
LRB
Bus busy
Repeat start
Start/stop condition
detector
Last bit
Transmission/
reception
Error
TRX
First byte
FBT
F2MC16LX Internal bus
AL
Arbitration lost detector
MBCRH
BER
BEIE
Interrupt #29
INTE
INT
End
Start
SCC
MSS
ACK
Master
Enables ACK
Start/stop condition
generator
Enables GC-ACK
GCAA
CRC-8 calculator
MBCRL
LBT
MDAR register
MBSRL
Slave
AAS
GCA
Slave address comparator
General call
MADR1~6 registers
MTCR
Timeout detector
SCL line
MBSRH
TDR TCR MTR STR
MALR
MTOD
MTOC
MMTO
MSTO
SDA line
ARAE
ARO
MBCRL
ALERT line
ARF
AEN
68
Interrupt #33
WUE
WUF
MBSRH
MB90370/375 Series
10. Bridge circuit
The bridge circuit can switch the I/O path of each port to I2C or Multi-address I2C.
(1) Register configuration of bridge circuit
Bridge Circuit Selection Register
7
6
5
4
3
2
1
0
Address : 00002CH
BM4
BI4
BM3
BI3
BM2
BI2
Read/write
Initial value
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit number
BRSR
(2) Block diagram of bridge circuit
I2C I/O
P81/SDA1
P80/SCL1
Multi-address I2C
BRSR
P91/SDA2
P90/SCL2
BM2
P93/SDA3
P92/SCL3
BM3
P95/SDA4
P94/SCL4
BM4
I2 C
BI2
BI3
BI4
69
MB90370/375 Series
11. Comparator
This comparator circuit monitors voltage of up to three batteries and automatically controls electric discharge.
Either parallel discharge or sequential discharge can be selected.
• Parallel discharge control
In parallel discharge control, all batteries are allowed to discharge when power is not being supplied from the
AC adapter.
• If power is being supplied from the AC adapter, the permission/prohibition of discharge for batteries is controlled
by software.
• Sequential discharge control
In sequential discharge control, the comparator controls discharge in a specified order, while monitoring
intermittent interruption of power, voltage level, and mount/dismount of batteries, when power is not being
supplied from the AC adapter.
• If power is being supplied from the AC adapter, the permission/prohibition of discharge for batteries is controlled
by software.
• Up to three batteries can be controlled, and the order of discharge can be selected.
• The affect of intermittent interruption of power is automatically filtered.
• Mount/dismount of batteries is automatically detected and discharge is controlled.
• Battery voltage is monitored, and if battery voltage is below the specified voltage, a change over to the next
battery is automatically done.
70
MB90370/375 Series
(1) Register configuration of comparator
Comparator Control Register (Lower)
7
6
5
4
3
2
1
0
Address : 0000D8H
BOF3
BOF2
BOF1
SPM2
SPM1
SPM0
Read/write
Initial value
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
Address : 0000D9H
SPL3
SPL2
SPL1
B3
B2
B1
DC2
DC1
Read/write
Initial value
R/W
0
R/W
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
7
6
5
4
3
2
1
0
COR8
COR7
COR6
COR5
COR4
COR3
COR2
COR1
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
Address : 0000DBH
SWR3
SWR2
SWR1
VAR3
VAR2
VAR1
Read/write
Initial value
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit number
COCRL
Comparator Control Register (Upper)
Bit number
COCRH
Comparator Status Register 1 (Lower)
Address : 0000DAH
Read/write
Initial value
Bit number
COSRL1
Comparator Status Register 1 (Upper)
Bit number
COSRH1
Comparator Interrupt Control Register (Lower)
Address :0000DCH
Read/write
Initial value
7
6
5
4
3
2
1
0
CEN8
CEN7
CEN6
CEN5
CEN4
CEN3
CEN2
CEN1
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit number
CICRL
(Continued)
71
MB90370/375 Series
(Continued)
Comparator Interrupt Control Register (Upper)
15
14
13
12
11
10
9
8
Address :0000DDH
SEN3
SEN2
SEN1
VEN3
VEN2
VEN1
Read/write
Initial value
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
3
2
1
0
COS8
COS7
COS6
COS5
COS4
COS3
COS2
COS1
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
15
14
13
12
11
10
9
8
Address : 0000DFH
SWS3
SWS2
SWS1
VAL3
VAL2
VAL1
Read/write
Initial value
R
X
R
X
R
X
R
X
R
X
R
X
Bit number
CICRH
Comparator Status Register 2 (Lower)
Address : 0000DEH
Read/write
Initial value
Bit number
COSRL2
Comparator Status Register 2 (Upper)
Bit number
COSRH2
Comparator Input Enable Register
72
7
6
5
4
3
2
1
0
Address : 0000E0H
BIE3
BIE2
BIE1
DIE2
DIE1
Read/write
Initial value
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
Bit number
CIER
MB90370/375 Series
(2) Block diagram of comparator
Pin
PB0/DCIN
Battery selection circuit
Pin
CVRH2
SW
+
−
Pin
Pin
PA3/ACO
Comparator 1
CVRL
IN
OUT
RH
RL (Voltage
comparator 2)
Pin
PB1/DCIN2
Pin
CVRH1
PB5/VSI2
−
+
Pin
PC1/AN1/SW2
SW
Battery
VSI supervisory
circuit 2
ALARM
IN
OUT
RH (Voltage
RL comparator 6)
Pin
SPL
VALID
VOL
IN
OUT
RH (Voltage
RL comparator 5)
Pin
PB4/VOL2
SW
Pin
PA4/OFB1
O12
SW
Pin
PA1/ALR2
OFB
Comparator 2
PB6/VOL3
IN
OUT
RH (Voltage
RL comparator 7)
Pin
PB7/VSI3
IN
OUT
RH (Voltage
RL comparator 8)
Pin
VALID
Battery
VSI supervisory
circuit 3
O13
ALARM
+
−
Pin
PC2/AN2/SW3
SPL
VOL
SW
SW
Pin
PA2/ALR3
OFB
Comparator 3
Pin
IN
OUT
RH (Voltage
RL comparator 3)
PB2/VOL1
Battery
VSI supervisory
circuit 1
IN
OUT
RH (Voltage
RL comparator 4)
Pin
PB3/VSI1
O21
O23
ALARM
+
−
Pin
PC0/AN0/SW1
SPL
VALID
VOL
SW
SW
Pin
PA5/OFB2
SW
Pin
PA0/ALR1
OFB
Comparator 4
Pin
Watch
prescaler
XOA
Pin
O31
X1A
Power-on
reset
Pin
SW
Pin
PA6/OFB3
O32
VCC
Pin
RST
8
3
3
SPL3 SPL2 SPL1 B3
B2
B1
DC2 DC1
3
(COCRH) Comparator control register (upper)
3
COS8 COS7 COS6 COS5 COS4 COS3 COS2 COS1
6
(COSRL2) Comparator status register 2 (lower)
COR8 COR7 COR6 COR5 COR4 COR3 COR2 COR1
SWR3 SWR2 SWR1 VAR3 VAR2 VAR1
(COSRL1) Comparator status register 1 (lower)
(COSRH1) Comparator status register 1 (upper)
interrupt request
#30
interrupt request
#28
(CICRH) Comparator interrupt control register (upper)
SEN3 SEN2 SEN1 VEN3 VEN2 VEN1
(CICRL) Comparator interrupt control register (lower)
CEN8 CEN7 CEN6 CEN5 CEN4 CEN3 CEN2 CEN1
Decoder
SWS3 SWS2 SWS1 VAL3 VAL2 VAL1
(COSRH2) Comparator status register 2 (upper)
BOF3 BOF2 BOF1 SPM2 SPM1 SPM0
(COCRL) Comparator control register (lower)
Internal data bus
73
MB90370/375 Series
12. UART (×
× 3)
The UART (Universal Asychronous Receiver Transmitter) is a serial I/O port for asynchronous (start-stop) communication or clock-synchronous communication.
The UART has the following features :
• Full-duplex double buffering
• Capable of asynchronous (start-stop bit) and CLK-synchronous communications
• Support for the multiprocessor mode
• Various method of baud rate generation :
- External clock input possible
- Internal clock (a clock supplied from 16-bit reload timer can be used)
- Embedded dedicated baud rate generator
Operation
Baud rate
Asynchronous
CLK synchronous
76923 / 38461 / 19230 / 9615 / 500K / 250K bps
16M / 8M / 4M / 2M / 1M / 500K bps
• Error detection functions (parity, framing, overrun)
• NRZ (Non Return to Zero) signal format
• Interrupt request :
- Receive interrupt (receive complete, receive error detection)
- Transmit interrupt (transmission complete)
- Transmit / receive conforms to extended intelligent I/O service (EI2OS)
74
MB90370/375 Series
(1) Register configuration of UART
Serial Mode Register
Address : ch1 000020H
ch2 0000D2H
ch3 0000E4H
MD1
MD0
CS2
CS1
CS0
SCKE
SOE
Read/write
Initial value
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
3
2
1
0
Serial Control Register
Address : ch1 000021H
ch2 0000D3H
ch3 0000E5H
PEN
P
SBL
CL
A/D
REC
RXE
TXE
Read/write
Initial value
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
W
1
R/W
0
R/W
0
15
14
13
12
11
10
9
SMR1/2/3
8
UART Status Register
Address : ch1 000023H
ch2 0000D5H
ch3 0000E7H
Read/write
Initial value
R/W
X
R/W
X
15
R/W
X
14
R/W
X
13
R/W
X
12
R/W
X
11
R/W
X
10
9
8
ORE
FRE
RDRF
TFRE
BDS
RIE
TIE
R
0
R
0
R
0
R
0
R
1
R/W
0
R/W
0
R/W
0
Mode 2 Control Register
Address : ch1 000024H
ch2 0000D6H
ch3 0000E8H
SCKL
M2L2
M2L1
M2L0
Read/write
Initial value
R/W
1
R/W
0
R/W
0
R/W
0
5
4
3
2
1
Bit number
SSR1/2/3
Clock Division Control Register
Address : ch1 000025H
15
14
13
12
11
10
9
8
ch2 0000D7H
ch3 0000E9H
MD
DIV3
DIV2
DIV1
DIV0
Read/write
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
Initial value
6
Bit number
SIDR1/2/3
SODR1/2/3
R/W
X
PE
7
Bit number
SCR1/2/3
UART Input Data Register / Output Data Register
Address : ch1 000022H
7
6
5
4
3
2
1
0
ch2 0000D4H
ch3 0000E6H
D7
D5
D4
D3
D2
D1
D0
D6
Read/write
Initial value
Bit number
0
Bit number
CDCR1/2/3
Bit number
M2CR1/2/3
75
MB90370/375 Series
(2) Block diagram of UART
From
communication
prescaler
Baud rate
generator
Reception status
judgement circuit
Reception control
circuit
Transmission control
circuit
Start bit detection
circuit
Transmission
start circuit
Reception bit
counter
Transmission bit
counter
Reception parity
counter
Transmission parity
counter
Reception shifter
SIDR1/2/3
Start of transmission
Control bus
P66/UCK1
<P71/UCK2> External clock
<P74/UCK3>
P70/UI1
<P73/UI2>
<P76/UI3>
Transmission clock
Reception clock
End of reception
16-bit reload timer 1/2/3
Clock
selection
circuit
Reception interrupt
#35 (23H)*
<#37 (25H)*>
<#39 (27H)*>
Transmission
interrupt
#36 (24H)*
<#38 (26H)*>
<#40 (28H)*>
P67/UO1
<P72/UO2>
<P75/UO3>
Transmission shifter
SODR1/2/3
EI2OS reception error
signal (to CPU)
F2MC-16LX bus
SMR1/2/3
registers
MD1
MD0
CS2
CS1
CS0
SCKE
SOE
SCR1/2/3
registers
PEN
P
SBL
CL
A/D
REC
RXE
TXE
SSR1/2/3
registers
PE
ORE
FRE
RDRF
TDRE
BDS
RIE
TIE
M2CR1/2/3
registers
Control signal
* : Interrupt number
76
SCKL
M2L2
M2L1
M2L0
MB90370/375 Series
13. LCD controller/driver (not for MB90F377)
The LCD (Liquid Crystal Display) controller/driver function displays the contents of a display data memory directly
to the LCD panel by segment and common outputs.
• Up to nine segment outputs (SEG0 to SEG8) and four common outputs (COM0 to COM3) may be used.
• Built-in display RAM.
• Three selectable duty ratios (1/2, 1/3, and 1/4) . However, not all duty ratios are available with all bias settings.
• Either the main or sub-clock can be selected as the drive clock.
• LCD can be driven directly.
Table below shows the duty ratios available with each bias setting.
Part number
Bias
1/2 duty ratio
1/3 duty ratio
1/4 duty ratio
X
X
1/2 bias
MB90370 series
1/3 bias
X
: Recommended mode
X : Do not use
(1) Register configuration of LCD
LCDC Control Register (Upper)
Address : 0000EFH
Read/write
Initial value
15
14
13
12
11
10
9
8
SS4
VS
CS1
CS0
SS3
SS2
SS1
SS0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
3
2
1
0
CSS
LCEN
VSEL
BK
MS1
MS0
FP1
FP0
R/W
0
R/W
0
R/W
0
R/W
1
R/W
0
R/W
0
R/W
0
R/W
0
Bit number
LCRH
LCDC Control Register (Lower)
Address : 0000EEH
Read/write
Initial value
Bit number
LCRL
77
MB90370/375 Series
(2) Block diagram of LCD
LCDC supply voltage (V1 to V3)
HCLK / 28
4
Timing
controller
4
V/I converter
Sub-clock
(32 kHz)
Segment output driver
Prescaler
Internal bus
Common output driver
LCDC control register
(LCR)
9
Display RAM
9 x 4 bit
Controller
78
Driver
COM0
COM1
COM2
COM3
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
MB90370/375 Series
14. A/D converter
The A/D (Analog to Digital) converter converts the analog voltage input to an analog input pin (input voltage) to
a digital value.
The converter has the following features :
• The minimum conversion time is 6.13 µs (for a machine clock of 16 MHz; includes the sampling time) .
• The minimum sampling time is 3.75 µs (for a machine clock of 16 MHz) .
• The converter uses the RC-type successive approximation conversion method with a sample and hold circuit.
• A resolution of 10 bits or 8 bits can be selected.
• Up to twelve channels for analog input pins can be selected by a program.
• Various conversion modes :
- Single conversion mode : Selectively convert one channel.
- Scan conversion mode : Continuously convert multiple channels. Maximum of 12 selectable channels.
- Continuous conversion mode : Repeatedly convert specified channels.
- Stop conversion mode : Convert one channel then halt until the next activation. (Enables synchronization of
the conversion start timing.)
• At the end of A/D conversion, an interrupt request can be generated and EI²OS can be activated.
• In the interrupt-enabled state, the conversion data protection function prevents any part of the data from being
lost through continuous conversion.
• The conversion can be activated by software, 16-bit reload timer 4 (rise edge) and ADTG.
(1) Register configuration of A/D converter
Analog Input Enable Register 2
15
14
13
12
11
10
9
8
Address : 00002BH
ADE11
ADE10
ADE9
ADE8
Read/write
Initial value
R/W
1
R/W
1
R/W
1
R/W
1
7
6
5
4
3
2
1
0
ADE7
ADE6
ADE5
ADE4
ADE3
ADE2
ADE1
ADE0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
15
14
13
12
11
10
9
8
BUSY
INT
INTE
PAUS
STS1
STS0
STRT
RESV
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
W
0
R/W
0
Bit number
ADER2
Analog Input Enable Register 1
Address : 00002AH
Read/write
Initial value
Bit number
ADER1
A/D Control Status Register 1
Address : 000031H
Read/write
Initial value
Bit number
ADCS1
A/D Control Status Register 0
7
6
5
4
3
2
1
0
Address : 000030H
MD1
MD0
Read/write
Initial value
R/W
0
R/W
0
Bit number
ADCS0
(Continued)
79
MB90370/375 Series
(Continued)
A/D Control Register
Address : 00002DH
Read/write
Initial value
15
14
13
12
11
10
9
8
ANS3
ANS2
ANS1
ANS0
ANE3
ANE2
ANE1
ANE0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit number
ADC0
A/D Data Register (Upper)
15
14
13
12
11
10
9
8
Address : 00002FH
S10
ST1
ST0
CT1
CT0
D9
D8
Read/write
Initial value
R/W
0
W
0
W
0
W
0
W
0
R
X
R
X
7
6
5
4
3
2
1
0
Address : 00002EH
D7
D6
D5
D4
D3
D2
D1
D0
Read/write
Initial value
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
Bit number
ADCR1
A/D Data Register (Lower)
(2) Block diagram of A/D converter
D/A converter
Sequential
comparison register
F2MC-16LX bus
MP
Comparator
Sample and holding circuit
Decoder
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AN8
AN9
AN10
AN11
AVSS
Input circuit
AVCC AVR
Data register
ADCR0/1
A/D control register
A/D control status register 0
A/D control status register 1
16-bit reload timer 4
P37/ADTG
φ
φ : Machine clock
80
ADCS0/1
Operation clock
Prescalar
Bit number
ADCR0
MB90370/375 Series
15. D/A converter
The D/A (Digital to Analog) converter is used to generate an analog output from an 8-bit digital input. By setting
the enable bit in the D/A control register (DACR) to 1, it will enable the corresponding D/A output channel. Hence,
setting this bit to 0 will disable that channel.
If D/A output is disabled, the analog switch inserted to the output of each D/A converter channel in series is
turned off. In the D/A converter, the bit is cleared to 0 and the direct-current path is shut off. The above is also
true in the stop mode.
The output voltage of the D/A converter ranges from 0 V to 255/256 x AVCC.
The D/A converter output does not have the internal buffer amplifier. The analog switch ( = 100 Ω) is inserted
to the output in series. To apply load to the output externally, estimate a sufficient stabilization time.
Table below lists the theoretical values of output voltage of the D/A converter.
Value written to DA07 to DA00 and DA17 to DA10
Theoretical value of output voltage
00H
0/256 × AVCC ( = 0 V)
01H
1/256 × AVCC
02H
2/256 × AVCC
:
:
FDH
253/256 × AVCC
FEH
254/256 × AVCC
FFH
255/256 × AVCC
81
MB90370/375 Series
(1) Register configuration of D/A converter
D/A converter register 1
15
14
13
12
11
10
9
8
Address : 00005BH
DA17
DA16
DA15
DA14
DA13
DA12
DA11
DA10
Read/write
Initial value
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
Bit number
DAT1
D/A converter register 0
7
6
5
4
3
2
1
0
Address : 00005AH
DA07
DA06
DA05
DA04
DA03
DA02
DA01
DA00
Read/write
Initial value
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
15
14
13
12
11
10
9
8
Address : 00005DH
DAE1
Read/write
Initial value
R/W
0
Bit number
DAT0
D/A control register 1
Bit number
DACR1
D/A control register 0
82
7
6
5
4
3
2
1
0
Address : 00005CH
DAE0
Read/write
Initial value
R/W
0
Bit number
DACR0
MB90370/375 Series
(2) Block diagram of D/A converter
F2MC-16LX BUS
DA DA DA DA DA DA DA DA
17 16 15 14 13 12 11 10
DA DA DA DA DA DA DA DA
07 06 05 04 03 02 01 00
AVCC
AVCC
DA17
DA07
2R
2R
R
DA16
R
DA06
2R
2R
R
R
DA15
DA05
DA11
DA01
2R
2R
R
DA10
R
DA00
2R
2R
2R
DAE1
Standby control
DA output ch.1
2R
DAE0
Standby control
DA output ch.0
83
MB90370/375 Series
16. LPC interface
The LPC (Low Pin Count) interface consists of an LPC bus interface, universal parallel interface (UPI ×
4 channels) , gate address A20 function and LPC data buffer array. By using the LPC bus interface and UPI,
data can be exchanged with an external host CPU synchronously via an external LPC bus.
• LPC bus interface
The LPC bus interface provides direct access of host CPU to UPI.
• It supports I/O read and I/O write cycle only. Other cycle types will be ignored.
• It supports LPC clock running at 33 MHz.
• Universal parallel interface, UPI × 4 channels
The UPI is used to exchange parallel data to serial data in LPC bus with host CPU.
• An 8-bit data will be transmitted or received.
• A buffer function is available for independent input and output.
• The I/O buffer status can be output externally through LPC bus interface.
• Gate address A20 function for UPI channel 0
The GA20 (Gate Address A20) is intended to implement the memory management in a PC architecture. This
allows the access to the extended memory needed by the operating system. On-chip logic is provided to speed
up the generation of GA20.
• Data buffer array
The data buffer array is consisted of 32 bytes UP data register and 16 bytes DOWN data register to speed up
the data transfer between MCU and external host through LPC bus.
(1) Register configuration of LPC bus interface register
LPC Control Register
84
7
6
5
4
3
2
1
0
Address : 00006EH
LRF
LRIE
LPE
Read/write
Initial value
R/W
0
R/W
0
R/W
0
Bit number
LCR
MB90370/375 Series
(2) Register configuration of UPI registers
UPI Address Register (Upper)
Address : ch1 00005FH
15
14
13
12
11
10
9
8
ch2 000061H
ch3 000063H
UPA15 UPA14 UPA13 UPA12 UPA11 UPA10 UPA09 UPA08
Bit number
UPAH1 to
UPAH3
Read/write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
X
X
X
X
X
X
X
X
Initial value
UPI Address Register (Lower)
Address : ch1 00005EH
7
6
5
4
3
2
1
0
ch2 000060H
ch3 000062H
UPA07 UPA06 UPA05 UPA04 UPA03 UPA02 UPA01 UPA00
Bit number
UPAL1 to
UPAL3
Read/write
R/W
X
Initial value
UPI Control Register (Upper)
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
15
14
13
12
11
10
9
8
Address : 000065H
UPE3
IBFE3
OBEE3
UPE2
IBFE2
OBEE2
Read/write
Initial value
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
3
2
1
0
DBAE
UPE1
IBFE1
UPE0
IBFE0
OBEE0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit number
UPCH
UPI Control Register (Lower)
Address : 000064H
Read/write
Initial value
OBEE1 GA20E
R/W
0
R/W
0
UPI Status Register
Address : ch0 000067H
15
14
13
12
11
10
9
8
ch1 000069H
ch2 00006BH
UF4
UF3
UF2
UF1
A2
UF0
IBF
OBF
ch3 00006DH
Read/write
R/W
R/W
R/W
R/W
R
R/W
R
R
0
0
0
0
0
0
0
0
Initial value
UPI Data Input Register / Data Output Register
Address : ch0 000066H
7
6
5
4
3
2
1
0
ch1 000068H
ch2 00006AH
UPD7
UPD6
UPD5
UPD4
UPD3
UPD2
UPD1
UPD0
ch3 00006CH
Read/write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
X
X
X
X
X
X
X
X
Initial value
Bit number
UPCL
Bit number
UPS0 to
UPS3
Bit number
UPDI0 to
UPDI3/
UPDO0 to
UPDO3
85
MB90370/375 Series
(3) Register configuration of LPC data buffer registers
Data Buffer Array Address Register (Upper)
15
14
13
12
11
10
9
8
Address : 003FF1H
DA15
DA14
DA13
DA12
DA11
DA10
DA09
DA08
Read/write
Initial value
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
Bit number
DBAAH
Data Buffer Array Address Register (Lower)
7
6
5
4
3
2
1
0
Address : 003FF0H
DA07
DA06
DA05
DA04
DA03
DA02
DA01
DA00
Read/write
Initial value
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
Bit number
DBAAL
UP Data Register (upper)
Address : ch0 003FC1H
ch1 003FC3H
to
chF 003FDFH
15
14
13
12
11
10
9
8
UP15
UP14
UP13
UP12
UP11
UP10
UP09
UP08
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Read/write
X
X
X
X
X
X
X
X
Initial value
UP Data Register (lower)
Address : ch0 003FC0H
7
6
5
4
3
2
1
0
ch1 003FC2H
to
UP07
UP05
UP04
UP03
UP02
UP01
UP00
UP06
chF 003FDEH
Read/write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
X
X
X
X
X
X
X
X
Initial value
DOWN Data Register (upper)
Address : ch0 003FE1H
15
14
13
12
11
10
9
8
ch1 003FE3H
to
DN15
DN14
DN13
DN12
DN11
DN10
DN09
DN08
ch7 003FEFH
Read/write
R
R
R
R
R
R
R
R
X
X
X
X
X
X
X
X
Initial value
DOWN Data Register (lower)
Address : ch0 003FE0H
7
6
5
4
3
2
1
0
ch1 003FE2H
to
DN07
DN06
DN05
DN04
DN03
DN02
DN01
DN00
ch7 003FEEH
Read/write
R
R
R
R
R
R
R
R
X
X
X
X
X
X
X
X
Initial value
Bit number
UDRH0 to
UDRHF
Bit number
UDRL0 to
UDRLF
Bit number
DNDH0 to
DNDH7
Bit number
DNDL0 to
DNDL7
(Continued)
86
MB90370/375 Series
(Continued)
Index Register
Address :
Read/write
Initial value
7
6
5
4
3
2
1
0
IX05
IX04
IX03
IX02
IX01
IX00
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
3
2
1
0
DP07
DP06
DP05
DP04
DP03
DP02
DP01
DP00
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
Bit number
IXR
Data Port Register
Address :
Read/write
Initial value
Bit number
DPR
(4) Block diagram of LPC interface
Address
comparator
UPI address register, UPAH1 to UPAH3, UPAL1 to UPAL3
Data buffer array address register, DBAA
UPE
LPC/RW
DBAE
R/W
comp
match
Interrupt
request #16
Interrupt
request #15
Interrupt
request #14
Interrupt
request #13
Interrupt
request #21
OBF0 to OBF3
UPI0 to UPI3
UPE
IBFE OBEE
UPS
UF4
UF3
UF2
UF1
A2
UF0
IBF
OBF
UPDI
UPD7 UPD6 UPD5 UPD4 UPD3 UPD2 UPD1 UPD0
UPDO
UPD7 UPD6 UPD5 UPD4 UPD3 UPD2 UPD1 UPD0
LPC internal data bus
F2MC-16LX internal data bus
UPC
LRF LRIE LPE
LA3 LA2 LA1 LA0
EN
R/W
State
machine
4
for UPI0 only
UPC
GA20E
EN
LCR
GA20 output
generator
LFRAME
LRESET
LCLK
LAD3 to
LAD0
LD7 LD6 LD5 LD4 LD3 LD2 LD1 LD0
LPC bus interface
GA20
DBAE
UPC
Data buffer array
IXR
UP data register (32 bytes)
Index register
DOWN data register (16 bytes)
Data port register
DPR
87
MB90370/375 Series
17. Serial IRQ controller
The serial IRQ controller consists of a 6-channel serial IRQ control circuit and an LPC clock monitor / control
circuit. By using this serial IRQ controller, host interrupt requests can be transferred serially through a single
signal wire (SERIRQ) , synchronized with the LPC clock.
6-channel serial IRQ control circuit
• The 6-channel serial IRQ control circuit consists of a serial interrupt control register (SICR) , 4 serial interrupt
frame number registers (SIFR1 to SIFR4) , a protocol state machine and a serial interrupt data latch and output
control.
• For channel 0A, 0B and 1 to 3, if SICR : OBE bit (OBF controlled enable bit) = 0, then serial IRQ can be
controlled by software setting of SICR : IRR bit. If SICR : OBE bit = 1, then software control is disabled and
serial IRQ is controlled by OBF flag (Output buffer full flag) from LPC UPI0 to UPI3.
• For channel 4, serial IRQ can be controlled by software setting of SICR : IRR bit.
• For channel 0A and 0B, additional enable bit (SICR : EN0A/0B bit) can be used to latch and keep the OBF0
or IRR0A/0B bit status.
• The serial interrupt data latch transfers serial IRQs serially according to their frame number. The frame number
for channel 0A is fixed to “IRQ1”, for channel 0B is fixed to “IRQ12”, and the frame number for channel 1 to
channel 4 are software programmable (IRQ1 to IRQ15, and IRQ21 to IRQ31) by setting the SIFR1 to SIFR4.
• By monitoring the SERIRQ and the LPC clock pin, the protocol state machine can detect the START frame
condition. Then it starts counting the DATA frame and transfers its serial IRQs through SERIRQ. Finally it can
switch to continuous/quiet mode operation by determine the STOP frame condition.
• The serial interrupt output control support both continuous and quiet mode operation. In continuous mode
operation, only the host can initiate the serial IRQs transfer; In quiet mode operation, both the host and slave
(e.g. the serial IRQ controller) can initiate the serial IRQs transfer.
LPC clock monitor / control circuit
• The LPC clock monitor / control circuit consists of a clock-run monitor / control circuit. By monitoring the clockrun pin (CLKRUN) , the clock monitor / control circuit can determine whether the host has stopped LPC clock
in quiet mode operation or not. If LPC clock is stopped and the controller wants to initiate the serial IRQs
transfer, then it can request the host to restart the LPC clock by controlling the CLKRUN pin.
88
MB90370/375 Series
(1) Register configuration of serial IRQ controller
Serial Interrupt Control Register (Lower)
Address : 000032H
Read/write
Initial value
7
6
5
4
3
2
1
0
EN0B
EN0A
IRR4
IRR3
IRR2
IRR1
IRR0B
IRR0A
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
9
8
Bit number
SICRL
Serial Interrupt Control Register (Upper)
Address : 000033H
Read/write
Initial value
15
14
13
12
11
10
IRQEN
RSEN
BUSY
OBE3
OBE2
OBE1
R/W
0
R/W
0
R
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
OBE0B OBE0A
Bit number
SICRH
Serial Interrupt Frame Number Register 1
7
6
5
4
3
2
1
0
Address : 000034H
LV1
FR14
FR13
FR12
FR11
FR10
Read/write
Initial value
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit number
SIFR1
Serial Interrupt Frame Number Register 2
15
14
13
12
11
10
9
8
Address : 000035H
LV2
FR24
FR23
FR22
FR21
FR20
Read/write
Initial value
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit number
SIFR2
Serial Interrupt Frame Number Register 3
7
6
5
4
3
2
1
0
Address : 000036H
LV3
FR34
FR33
FR32
FR31
FR30
Read/write
Initial value
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit number
SIFR3
Serial Interrupt Frame Number Register 4
15
14
13
12
11
10
9
8
Address : 000037H
LV4
FR44
FR43
FR42
FR41
FR40
Read/write
Initial value
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit number
SIFR4
89
MB90370/375 Series
(2) Block diagram of the serial IRQ controller
Serial IRQ controller
6-channel serial
IRQ control circuit
LCLK stop
status
OBF0
OBF1
OBF2
OBF3
OBF0
OBF1
OBF2
OBF3
from UPI0 to UPI3
in LPC
interface
SIRQ
Pin SERIRQ
LCLK
Pin LCK
Pin LRESET
F2MC-16LX bus
LRESET
LCLK restart
request
LPC clock
monitor / control
circuit
LCLK
LRESET
CRUN
90
Pin CLKRUN
MB90370/375 Series
(3) Block diagram of the 6-channel serial IRQ control circuit
IRQEN
OBF0
OBF1
OBF2
OBF3
IRR0A, IRR0B, IRR1 to IRR3
Software
Hardware
control
control
Serial IRQ control
selector for channel
0A, 0B, 1 to 3
IRR4
EN0A,
EN0B
Serial interrupt
frame number
register
Latches for
channel 0A, 0B
channel 1 to
channel 4
F2MC-16LX bus
Register
write
disable
Serial interrupt
control register
(lower)
OBE0A, OBE0B,
OBE1 to OBE3
Serial interrupt
control register
(upper)
SERIRQ
busy
SIRQ enable
Serial interrupt
data latch and
output control
Serial IRQs
frame no. for
channel 1 to channel 4
Serial IRQ
sample cycle
SIRQO
LCK
LRESET
Frame
cycle count
Initiate serial
IRQ transfer
request
Protocol
state
machine
SIRQI
LCK stop
status
LCK
restart
request
91
MB90370/375 Series
(4) Block diagram of the LPC clock monitor / control circuit
F2MC-16LX bus
RSEN
LCK
restart
request
IRQEN
CRUNO enable
LCK stop
status
LCK
restart
request
CRUNO
Clock-run
monitor /
control
CRUNI
LCK
LRESET
92
MB90370/375 Series
18. 3-channel PS/2 interface
The 3-channel PS/2 interface consists of 3 individual channels of PS/2 interface that can be operated concurrently. PS/2 interface is a two wires, bidirectional serial bus providing economical way for data exchange between
host (keyboard controller) and device (keyboard / mouse, etc) .
(1) Register configuration of 3-channel PS/2 interface
PS/2 Interface Mode Register
15
14
13
12
11
10
9
8
Address : 000059H
NFS1
NFS0
DIV1
DIV0
Read/write
Initial value
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
D7
D6
D5
D4
D3
D2
D1
D0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit number
PSMR
PS/2 Interface Data Register (Ch 1)
Address : 000057H
Read/write
Initial value
Bit number
PSDR1
PS/2 Interface Data Register (Ch 0, Ch 2)
7
Address : ch1 000056H
ch2 000058H
Read/write
Initial value
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
PS/2 Interface Status Register
Address : ch0 000051H
15
14
13
12
11
10
9
8
ch1 000053H
ch2 000055H
TS
TBC
BNR
TC
PE
FED FRE/NAK RAF
Read/write
Initial value
R
0
PS/2 Interface Control Register
Address : ch0 000050H
7
ch1 000052H
ch2 000054H
PS2E
Read/write
Initial value
R/W
0
R
0
R
0
6
R
0
5
R
0
4
R
0
3
R
0
2
Bit number
PSDR0/2
Bit number
PSSR0/1/2
R/W
0
1
0
FEDE
IE
BREQ
TE
RE
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit number
PSCR0/1/2
93
MB90370/375 Series
(2) Block diagram of 3-channel PS/2 interface
F2MC-16LX bus
NFS1 NFS0 DIV1 DIV0
2
PSMR
1/8
1/16
1/32
94
Selector
φ
Prescaler
circuit
1/4
PSCKI0
Noise filter
PSDAI0
Noise filter
PSCKI1
Noise filter
PSDAI1
Noise filter
PSCKI2
Noise filter
PSDAI2
Noise filter
Sampling clock
Channel 0
transmission/
reception
circuit
PSCKO0
PSDAO0
Channel 1
transmission/
reception
circuit
PSCKO1
PSDAO1
Channel 2
transmission/
reception
circuit
PSCKO2
PSDAO2
Interrupt
request 0
Interrupt
request 1
Interrupt
request 2
MB90370/375 Series
(3) Block diagram of PS/2 interface transmission/reception circuit (1 channel)
F2MC-16LX bus
Sampling
clock
PSDAI
PSCKI
SYNDA
SYNCK
Synchronous
circuit
PSDR
D7
D6
D5
D4
D3
D2
D1
Start of
reception
D0
PSDAO
Start of
transmission
Reception control
circuit
Transmission control
circuit
Reception
completion detector
Acknowledge
reception generator
Parity checker
Parity generator
Reception start bit
detection circuit
Reception
enable
Reception status
judgment circuit
PE & FRE Reception Reception
active
complete
Transfer
break
request
Transmission
completion detector
Transmission
enable
Acknowledge Transmission
result
complete
Transfer complete
processing circuit
PSCKO
Transfer
status flags
clear
Error flags
Falling edge
detection
PS2E
FEDE IE BREQ TE
PSCR
RE
PE
FED FRE/
NAK RAF
PSSR
TS
TBC BNR
TC
PS/2 interface
interrupt
#23 (17H)* ch0/1
#24 (18H)* ch2
F2MC-16LX bus
* : Interrupt number
95
MB90370/375 Series
19. Parity generator
The parity generator is a simple circuit that generates odd / even parity based on the input data. It consists of a
parity generator data register (PGDR) , an odd / even parity generation logic and a parity generator control status
register (PGCSR) .
An 8-bit data can be loaded into PGDR, then the parity generator will generate odd / even parity based on the
input data. Either odd or even parity can be generated by setting the PGCSR.
For odd parity generation, if the number of “1”s in the PGDR is even number, then the parity bit in PGCSR will
be set to “1”, otherwise the parity bit will be set to “0”.
For even parity generation, if the number of “1”s in the PGDR is even number, then the parity bit in PGCSR will
be set to “0”, otherwise the parity bit will be set to “1”.
Table shows some examples of odd / even parity generation.
Input data
Parity bit (odd parity)
0000 0000B
0101 0101B
1000 0000B
1010 1011B
Parity bit (even parity)
1
1
0
0
0
0
1
1
(1) Register configuration of parity generator
Parity Generator Data Register
Address : 000018H
Read/write
Initial value
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
Bit number
PGDR
Parity Generator Control Status Register
Address : 000019H
Read/write
Initial value
96
15
14
13
12
11
10
9
8
PRTY
PSEL
R
X
R/W
0
Bit number
PGCSR
MB90370/375 Series
(2) Block diagram of parity generator
8
F2MC16LX Internal bus
Parity generator data register
8
Parity generation logic
odd /
even
result
2
Parity generator
control status register
97
MB90370/375 Series
20. Bit decoder
The bit decoder is a simple one-hot decoder that can be used together with the keyscan inputs. It consists of a
bit data register (BDR) , a decoder logic and a bit result register (BRR) . A 4-bit encoded data can be loaded
into BDR, then the decoder logic will decode the data and store the 16-bit resulted data into BRR. A table below
shows the decoder’s logic.
4-bit encoded data
16-bit resulted data
0H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
0000 0000 0000 0001B
0000 0000 0000 0010B
0000 0000 0000 0100B
0000 0000 0000 1000B
0000 0000 0001 0000B
0000 0000 0010 0000B
0000 0000 0100 0000B
0000 0000 1000 0000B
0000 0001 0000 0000B
0000 0010 0000 0000B
0000 0100 0000 0000B
0000 1000 0000 0000B
0001 0000 0000 0000B
0010 0000 0000 0000B
0100 0000 0000 0000B
1000 0000 0000 0000B
(1) Register configuration of bit decoder
Bit Data Register
15
14
13
12
11
10
9
8
Address : 0000E1H
D3
D2
D1
D0
Read/write
Initial value
R/W
X
R/W
X
R/W
X
R/W
X
15
14
13
12
11
10
9
8
R15
R14
R13
R12
R11
R10
R9
R8
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
Bit number
BDR
Bit Result Register (Upper)
Address : 0000E3H
Read/write
Initial value
Bit number
BRRH
Bit Result Register (Lower)
98
7
6
5
4
3
2
1
0
Address : 0000E2H
R7
R6
R5
R4
R3
R2
R1
R0
Read/write
Initial value
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
Bit number
BRRL
MB90370/375 Series
(2) Block diagram of bit decoder
4
F2MC16LX Internal bus
Bit data register
4
Decoder logic
16
16
Bit result register
99
MB90370/375 Series
21. Wake-up interrupt
The wake-up interrupt circuit detects the signals of the “L” levels input to the external interrupt pins and to
generate interrupt request to the CPU. These interrupts can wake up the CPU from standby mode.
Wake-up interrupt pins :
8 pins (P00/KSI0 to P07/KSI7) .
Wake-up interrupt sources : “L” level signal input to a wake-up interrupt pin.
Enables or disables to input wake-up interrupt controlled by wake-up interrupt control
Interrupt control :
register (EICR) .
IRQ flag bit of wake-up interrupt flag register (EIFR) . Flag set
Interrupt flag :
when there is an IRQ.
Interrupt request :
Interrupt request #20 is generated if any enabled external interrupt pin goes LOW.
(1) Register configuration of wake-up interrupt
Wake-up Interrupt Flag Register
15
14
13
12
11
10
9
8
Address : 0000ADH
WIF
Read/write
Initial value
R/W
0
7
6
5
4
3
2
1
0
Address : 0000ACH
EN7
EN6
EN5
EN4
EN3
EN2
EN1
EN0
Read/write
Initial value
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit number
EIFR
Wake-up Interrupt Control Register
Bit number
EICR
(2) Block diagram of wake-up interrupt
7
6
5
4
3
2
1
0
EICR
P07/KSI7
P06/KSI6
P05/KSI5
EIFR
P04/KSI4
P03/KSI3
P02/KSI2
P01/KSI1
P00/KSI0
Interrupt Request Generator
100
MB90370/375 Series
22. DTP/External interrupts
The DTP (Data Transfer Peripheral) /external interrupt circuit is activated by the signal supplied to a DTP/external
interrupt pin. The CPU accepts the signal using the same as procedure used for normal hardware interrupts
and generates external interrupts or activates the extended intelligent I/O service (EI2OS) .
Features of DTP/External interrupt :
• Total 6 external interrupt channels
• Two request levels (“H” and “L”) are provided for the intelligent I/O service.
• Four request levels (rise/fall edge, fall edge, “H” level and “L” level) are provided for external interrupt requests .
(1) Register configuration
DTP/Interrupt Source Register
15
14
13
12
11
10
9
8
Address : 000027H
ER5
ER4
ER3
ER2
ER1
ER0
Read/write
Initial value
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
3
2
1
0
EN5
EN4
EN3
EN2
EN1
EN0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit number
EIRR
DTP/Interrupt Enable Register
Address : 000026H
Read/write
Initial value
Bit number
ENIR
Request Level Setting Register (Upper)
15
14
13
12
11
10
9
8
Address : 000029H
LB5
LA5
LB4
LA4
Read/write
Initial value
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
3
2
1
0
LB3
LA3
LB2
LA2
LB1
LA1
LB0
LA0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit number
ELVRH
Request Level Setting Register (Lower)
Address : 000028H
Read/write
Initial value
Bit number
ELVRL
101
MB90370/375 Series
(2) Block diagram of DTP/External interrupts
Request level setting register (ELVR)
LB5 LA5 LB4 LA4 LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0
2
2
2
2
2
2
Selector
Pin
P60/INT0
Selector
Pin
P61/INT1
Pin
Selector
Selector
Internal data bus
P65/INT5
Pin
P62/INT2
Selector
Pin
Selector
Pin
P64/INT4
P63/INT3
DTP/interrupt cause register
(EIRR)
ER5
ER4
ER3
ER2
ER1
ER0
Interrupt request number
#17(11H)
#18(12H)
#19(13H)
EN5
102
EN4
EN3
EN2
EN1
EN0
DTP/interrupt enable register
(ENIR)
MB90370/375 Series
23. Delayed interrupt generation module
The delayed interrupt generation module is used to generate a task switching interrupt. Interrupt requests to the
F2MC-16LX CPU can be generated and cleared by software using this module.
(1) Register configuration
Delayed Interrupt Generator Module Register
15
14
13
12
11
10
9
8
Address : 00009FH
R0
Read/write
Initial value
R/W
0
Bit number
DIRR
F2MC-16LX bus
(2) Block diagram
Delayed interrupt cause issuance / cancellation decoder
Interrupt cause latch
103
MB90370/375 Series
24. ROM correction function
When an address matches the value set in the address detection register, the instruction code to be loaded into
the CPU is forced to be replaced with the INT9 instruction code (01H) . When executing a set instruction, the
CPU executes the INT9 instruction. The ROM correction function is implemented by processing using the INT9
interrupt routine.
The device contains two address detection registers, each provided with a compare enable bit. When the value
set in the address detection register matches an address and the interrupt enable bit is “1”, the instruction code
to be loaded into the CPU is forced to be replaced with the INT9 instruction code.
(1) Register configuration
Program Address Detection Control / Status Register
7
6
5
4
3
2
1
0
Address : 00009EH
AD1E
AD1D
AD0E
AD0D
Read/write
Initial value
R/W
0
R/W
0
R/W
0
R/W
0
Bit number
PACSR
Program Address Detection Register 0 (Upper Byte)
7
6
5
4
3
2
1
0
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
Address : 001FF2H
Read/write
Initial value
Bit number
PADRH0
Program Address Detection Register 0 (Middle Byte)
15
14
13
12
11
10
9
8
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
Address : 001FF1H
Read/write
Initial value
Bit number
PADRM0
Program Address Detection Register 0 (Lower Byte)
7
6
5
4
3
2
1
0
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
Address : 001FF0H
Read/write
Initial value
Bit number
PADRL0
(Continued)
104
MB90370/375 Series
(Continued)
Program Address Detection Register 1 (Upper Byte)
Bit number
PADRH1
15
14
13
12
11
10
9
8
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
Address : 001FF5H
Read/write
Initial value
Program Address Detection Register 1 (Middle Byte)
Address : 001FF4H
Read/write
Initial value
Bit number
PADRM1
7
6
5
4
3
2
1
0
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
Program Address Detection Register 1 (Lower Byte)
Bit number
PADRL1
15
14
13
12
11
10
9
8
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
Address : 001FF3H
Read/write
Initial value
(2) Block diagram
Address latch
Comparator
INT9
command
F2MC-16LX bus
Address detection register 0/1
F2MC-16LX
CPU
AD0E/AD1E
AD0D/AD1D
PACSR
105
MB90370/375 Series
25. ROM mirroring function selection module
The ROM mirroring function selection module can select what the FF bank allocated the ROM sees through the
00 bank according to register settings.
(1) Register configuration
ROM Mirror Function Selection Register
15
14
13
12
11
10
9
8
Address : 0006FH
M1
Read/write
Initial value
W
1
(2) Block diagram
ROM mirroring register
F2MC-16LX bus
Address area
FF bank
00 bank
ROM
106
Bit number
ROMM
MB90370/375 Series
26. 512K bit flash memory
The 512K bit flash memory is allocated in the FFH banks on the CPU memory map. Like masked ROM, flash
memory is read-accessible and program-accessible to the CPU using the flash memory interface circuit. The
flash memory can be programmed/erased by the instruction from the CPU via the flash memory interface circuit.
The flash memory can therefore be reprogrammed (updated) while still on the circuit board under integrated
CPU control, allowing program code and data to be improved efficiently. Note that sector operations such as
“enable sector protect” cannot be used.
Features of 512K bit flash memory :
• 64 Kwords × 8 bits / 32 Kwords × 16 bits (16 K + 8 K + 8 K + 32 K) sector configuration
• Automatic program algorithm (same as the Embedded Algorithm* : MBM29F400TA)
• Installation of the deletion temporary stop/delete restart function
• Write/delete completion detected by the data polling or toggle bit
• Write/delete completion detected by the CPU interrupt
• Compatibility with the JEDEC standard-type command
• Each sector deletion can be executed (Sectors can be freely combined) .
• Number of write/delete operations 10,000 times guaranteed
* : Embedded Algorithm is a trademark of Advanced Micro Devices, Inc.
(1) Register configuration
Flash Memory Control Status Register
7
6
5
4
3
2
1
0
Address : 0000AEH
INTE
RDYINT
WE
RDY
Reserved
LPM1
Reserved
LPM0
Read/write
Initial value
R/W
0
R/W
0
R/W
0
R
1
W
0
R/W
0
W
0
R/W
0
Bit number
FMCS
107
MB90370/375 Series
(2) Sector configuration of 512K bits flash memory
The 512K bits flash memory has the sector configuration illustrated below. The addresses in the illustration are
the upper and lower addresses of each sector.
When accessed from the CPU, SA0 and SA1 to SA3 are allocated in the FF bank registers, respectively.
Flash memory
CPU address
*Writer address
FFFFFFH
7FFFFH
FFC000H
FFBFFFH
7C000H
7BFFFH
FFA000H
7A000H
FF9FFFH
79FFFH
FF8000H
78000H
FF7FFFH
77FFFH
FF0000H
70000H
SA3 (16 Kbytes)
SA2 (8 Kbytes)
SA1 (8 Kbytes)
SA0 (32 Kbytes)
* : Writer addresses correspond to CPU addresses when data is programmed in flash memory by a parallel writer.
Writer addresses are used to program/erase data using a general-purpose writer.
108
MB90370/375 Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter
Symbol
(VSS = AVSS = CVSS = 0.0 V)
Rating
Unit
Remarks
Min
Max
VCC
VSS − 0.3
VSS + 4.0
V
CVCC
VSS − 0.3
VSS + 4.0
V
VCC ≥ CVCC *1
AVCC
VSS − 0.3
VSS + 4.0
V
VCC ≥ AVCC *1
A/D converter reference
input voltage
AVR
VSS − 0.3
VSS + 4.0
V
AVCC ≥ AVR, AVR ≥ AVSS
Comparator reference
input voltage
CVRH1
CVRH2
CVRL
VSS − 0.3
VSS + 4.0
V
CVCC ≥ CVRH1, CVRH1 ≥ CVSS
CVCC ≥ CVRH2, CVRH2 ≥ CVSS
CVCC ≥ CVRL, CVRL ≥ CVSS
LCD power supply voltage
V1 to V3
VSS − 0.3
VSS + 4.0
V
V1 to V3 must not exceed VCC
Not for MB90F377
VI1
VSS − 0.3
VSS + 4.0
V
All pins except P40 to P45, P80 to
P82, P90 to P95 *2
VI2
VSS − 0.3
VSS + 6.0
V
P40 to P45, P80 to P82, P90 to P95
VO
VSS − 0.3
VSS + 4.0
V
*2
ICLAMP
−2.0
+2.0
mA
*4
Total maximum clamp current
Σ|ICLAMP|
20
mA
*4
“L” level maximum output
current
IOL1
10
mA
All pins except PF0 to PF7*3
IOL2
20
mA
PF0 to PF7*3
IOLAV1
4
mA
All pins except PF0 to PF7
Average output current = operating
current × operating efficiency
IOLAV2
12
mA
PF0 to PF7
Average output current = operating
current × operating efficiency
ΣIOL
100
mA
ΣIOLAV
50
mA
Average output current = operating
current × operating efficiency
IOH
−10
mA
*3
“H” level average output
current
IOHAV
−3
mA
Average output current = operating
current × operating efficiency
“H” level total maximum
output current
ΣIOH
−100
mA
ΣIOHAV
−50
mA
Power supply voltage
Input voltage
Output voltage
Maximum clamp current
“L” level average output
current
“L” level total maximum
output current
“L” level total average
output current
“H” level maximum output
current
“H” level total average
output current
Average output current = operating
current × operating efficiency
(Continued)
109
MB90370/375 Series
(Continued)
(VSS = AVSS = CVSS = 0.0 V)
Symbol
Parameter
Rting
Min
Max
Unit
Power consumption
PD
200
mW
Operating temperature
TA
−40
+85
°C
Tstg
−55
+150
°C
Storage temperature
Remarks
*1 : Set AVCC, CVCC and VCC at the same voltage. Take care so that AVR, CVRH1, CVRH2 and CVRL do not exceed
VCC + 0.3 V when the power is turned on.
*2 : VI and VO shall never exceed VCC + 0.3 V. VI should not exceed the specified ratings. However if the maximum
current to/from an input is limited by some means with external components, the ICLAMP rating supersedes
the VI rating.
*3 : The maximum output current is a peak value for a corresponding pin.
*4 : Applicable to pins : P00 to P07, P10 to P17, P20 to P27, P30 to P37, P47, P50 to P57, P60 to P67,
P70 to P77, PA0 to PA6, PC3 to PC7, PD0 to PD3, PD6, PD7
Use within recommended operating conditions.
Use at DC voltage (current) .
The +B signal should always be applied a limiting resistance placed between the +B signal and the
microcontroller.
The value of the limiting resistance should be set so that when the +B signal is applied the input current to the
microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.
Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input potential
may pass through the protective diode and increase the potential at the Vcc pin, and this may affect other
devices.
Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0V) , the power supply
is provided from the pins, so that incomplete operation may result.
Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting
supply voltage may not be sufficient to operate the power-on reset.
Care must be taken not to leave the +B input pin open.
Note that analog system input/output pins other than the A/D input pins (LCD drive pins, comparator input pins,
etc.) cannot accept +B signal input.
Sample recommended circuits :
Input/Output Equivalent circuits
Protective diode
Vcc
P-ch
Limiting
resistance
+B input (0V to 16V)
N-ch
R
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
110
MB90370/375 Series
2. Recommended Operating Conditions
Parameter
Power supply
voltage *1
A/D converter
reference input
voltage *2
LCD power supply
voltage
Operating
temperature
Symbol
(VSS = AVSS = CVSS = 0.0 V)
Value
Unit
Remarks
Min
Max
VCC
3.0
3.6
V
CVCC
3.3
3.6
V
VCC
1.8
3.6
V
Retains the RAM state in stop mode
AVR
0
AVCC
V
Normal operation assurance range
V1 to V3 pins
(The optimum value is dependent on the LCD
element in use.)
Not for MB90F377
V1 to V3
VSS
VCC
V
TA
−40
+85
°C
Normal operation assurance range
*1 : Set AVCC, CVCC and VCC at the same voltage.
*2 : Take care so that AVR, CVRH1, CVRH2 and CVRL do not exceed VCC + 0.3 V when power is turned on.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
111
MB90370/375 Series
3. DC Characteristics
Parameter
“H” level input
voltage
Symbol
(VCC = AVCC = CVCC = 3.0 V to 3.6 V, VSS = AVSS = CVSS = 0.0 V, TA = −40 °C to +85 °C)
Pin name
Condition
Value
Unit
Remarks
Min
Typ
Max
VIH
P10 to P17
P20 to P27
P30 to P37
P46, P47
P50 to P57
PA0 to PA6
PB0 to PB7
PC0 to PC7
PD0 to PD7
PF0 to PF7
0.7 VCC
VCC + 0.3
V
CMOS
input pins
VIHS
P00 to P07
P60 to P67
P70 to P77
PE0 to PE7
RST
0.8 VCC
VCC + 0.3
V
CMOS
hysteresis
input pins
VIHS5
P40 to P45
0.8 VCC
VSS + 5.5
V
5 V tolerant
CMOS
hysteresis
input pins
VIH5
P82
0.7 VCC
VSS + 5.5
V
5 V tolerant
CMOS
input pin
VIHSM
P80, P81
P90 to P95
2.1
VSS + 5.5
V
SMbus
input pins
VIHM
MD0 to MD2
VCC − 0.3
VCC + 0.3
V
Mode pins
VIL
P10 to P17
P20 to P27
P30 to P37
P46, P47
P50 to P57
P82
PA0 to PA6
PB0 to PB7
PC0 to PC7
PD0 to PD7
PF0 to PF7
VSS − 0.3
0.3 VCC
V
CMOS
input pins
VILS
P00 to P07
P40 to P45
P60 to P67
P70 to P77
PE0 to PE7
RST
VSS − 0.3
0.2 VCC
V
CMOS
hysteresis
input pins
“L” level input
voltage
(Continued)
112
MB90370/375 Series
(VCC = AVCC = CVCC = 3.0 V to 3.6 V, VSS = AVSS = CVSS = 0.0 V, TA = −40 °C to +85 °C)
Parameter
“L” level input
voltage
Open-drain
output pin
application
voltage
“H” level output
voltage
“L” level output
voltage
Symbol
Pin name
Condition
Value
Min
Typ
Max
Unit
Remarks
VILSM
P80, P81
P90 to P95
VSS − 0.3
0.8
V
SMbus
input pins
VILM
MD0 to MD2
VSS − 0.3
VSS + 0.3
V
Mode pins
VD5
P40 to P45
P80 to P82
P90 to P95
VSS − 0.3
VSS + 5.5
V
VD
P46
VSS − 0.3
VCC + 0.3
V
VOH1
All port pins
except
P40 to P46
P80 to P82
P90 to P95
PF0 to PF7
VCC = 3.0 V
IOH1 = −4.0 mA
VCC − 0.5
V
VOH2
PF0 to PF7
VCC = 3.0 V
IOH2 = −8.0 mA
VCC − 0.5
V
VOL1
All port pins
except
PF0 to PF7
IOL1 = 4.0 mA
0.4
V
VOL2
PF0 to PF7
IOL2 = 12.0 mA
0.4
V
All input pins
VCC = 3.3 V,
VSS < VI < VCC
−5
+5
µA
5
µA
37
45
mA
30
35
mA MB90372
VCC = 3.3 V,
Internal operation
at 16 MHz,
In sleep mode
15
20
mA
VCC = 3.3 V,
External 32 kHz,
Internal operation
at 8 kHz,
In sub-clock mode,
TA = +25 °C
23
80
µA
Input leakage
current (High-Z
output leakage
current)
IIL
Open-drain
output leakage
current
ILEAK
P40 to P46
P80 to P82
P90 to P95
VCC = 3.3 V,
Internal operation
at 16 MHz
ICC
ICCS
Power supply
current*
VCC
ICCL
MB90F372 /
F377
(Continued)
113
MB90370/375 Series
(VCC = AVCC = CVCC = 3.0 V to 3.6 V, VSS = AVSS = CVSS = 0.0 V, TA = −40 °C to +85 °C)
Parameter
Power supply
current*
Input
capacitance
Symbol
Pin name
Condition
Value
Unit
Min
Typ
Max
ICCLS
VCC = 3.3 V,
External 32 kHz,
Internal operation
at 8 kHz,
In sub-clock sleep
mode,
TA = +25 °C
10
50
µA
ICCWAT
VCC = 3.3 V,
External 32 kHz,
Internal operation
at 8 kHz,
In watch mode,
TA = +25 °C
1.5
30
µA
ICCT
VCC = 3.3 V,
Internal operation
at 16 MHz,
In timebase timer
mode
1.3
2
mA
ICCH
VCC = 3.3 V,
In stop mode,
TA = +25 °C
1
20
µA
5
15
pF
Between VCC and V3
at VCC = 3.3 V
100
200
400
CIN
VCC
All input pins
except VCC,
AVCC, CVCC,
VSS, AVSS, CVSS
LCD divided
resistance
RLCD
COM0 to
COM3 output
impedance
RVCOM
SEG0 to SEG8
output
impedance
RVSEG
SEG0 to SEG8
LCD leakage
current
LLCDL
V1 to V3
COM0 to COM3
SEG0 to SEG8
Between V3 and V2
Between V2 and V1
Between V1 and VSS
at VCC = 3.3 V
COM0 to COM3
kΩ
50
100
200
5
Not for
MB90F377
kΩ
Not for
MB90F377
V1 to V3 = 3.3 V
Remarks
5
kΩ
±1
µA
Not for
MB90F377
(Continued)
114
MB90370/375 Series
(Continued)
Parameter
(VCC = AVCC = CVCC = 3.0 V to 3.6 V, VSS = AVSS = CVSS = 0.0 V, TA = −40 °C to +85 °C)
Symbol
Pull-up
resistance
RUP
Pull-down
resistance
RDOWN
Pin name
Condition
Value
Min
Typ
Max
Unit
P00 to P07
P10 to P17
P20 to P27
P30 to P37
RST
25
50
100
kΩ
MD2
25
50
100
kΩ
Remarks
MB90V370,
MB90372
only
* : The power supply current is measured with an external clock.
115
MB90370/375 Series
4. AC Characteristics
(1) Clock Timings
Parameter
Clock frequency
Clock cycle time
Input clock pulse width
Input clock rise/fall time
Internal operating clock
frequency
Internal operating clock
cycle time
(VCC = AVCC = CVCC = 3.0 V to 3.6 V, VSS = AVSS = CVSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Symbol Pin name Condition
Unit
Remarks
Min
Typ
Max
FCH
X0, X1
3
16
MHz Crystal oscillator*
FCH
X0, X1
3
32
MHz External clock*
FCL
X0A, X1A
32.768
kHz
tHCYL
X0, X1
31.25
333
ns
tLCYL
X0A, X1A
30.5
µs
PWH
PWL
X0
5
ns
Recommend duty
ratio of 30% to 70%
PWHL
PWLL
X0A
15.2
µs
Recommend duty
ratio of 30% to 70%
tCR
tCF
X0
5
ns
External clock
operation
fCP
1.5
16
MHz Main clock operation
fLCP
8.192
kHz Sub-clock operation
tCP
62.5
666
ns
Main clock operation
tLCP
122.1
µs
Sub-clock operation
* : When selecting the PLL clock, the range of clock frequency is limited. Use this product within range as mentioned
in “Relationship between oscillating frequency and internal operating clock frequency” of “• PLL operation
guarantee range”.
X0, X1 clock timing
tHCYL
0.8 VCC
X0
0.2 VCC
PWH
PWL
tCF
tCR
X0A, X1A clock timing
tLCYL
0.8 VCC
0.2 VCC
X0A
PWHL
PWLL
tCF
116
tCR
MB90370/375 Series
• PLL operation guarantee range
Power supply voltage VCC (V)
Relationship between internal operating clock frequency and power supply voltage
3.6
Operation guarantee
range of PLL
3.0
Normal operation guarantee range
1.5
4
8
Internal operating clock fCP (MHz)
16
Internal operating clock fCP (MHz)
Relationship between oscillating frequency and internal operating clock frequency
Multiplied- Multipliedby-4
by-3
Multipliedby-2
Multipliedby-1
16
12
9
8
Not multiplied
4
3
4
8
16
Oscillation clock FC (MHz)
117
MB90370/375 Series
The AC ratings are measured for the following measurement reference voltages :
• Input signal waveform
Hysteresis input pin
Output pin
0.8 VCC
2.4 V
0.2 VCC
0.8 V
CMOS input pin
0.7 VCC
0.3 VCC
SMbus input pin
2.1 V
0.8 V
118
• Output signal waveform
MB90370/375 Series
(2) Reset Input Timing
Parameter
Reset input time
Symbol
(VCC = AVCC = CVCC = 3.0 V to 3.6 V, VSS = AVSS = CVSS = 0.0 V, TA = −40 °C to +85 °C)
Pin name
tRSTL
Value
Condition
RST
Unit
Remarks
Min
Max
16 tCP
ns
Normal
operation
Oscillation time of
oscillator* + 16 tCP
ms
In stop mode
and sub-clock
mode
* : Oscillation time of oscillator is the time to reach to 90% of the oscillation amplitude from stand still. In the crystal
oscillator, the oscillation time is between several ms to tens of ms. In FAR/ceramic oscillator, the oscillation time
is between hundreds of µs to several ms. In the external clock, the oscillation time is 0 ms.
• In stop mode and sub-clock mode
tRSTL
RST
0.2 Vcc
0.2 Vcc
90% of the oscillation amplitude
X0
Internal
operation
clock
Oscillation time of
oscillator
16 tCP
Oscillator stabilization time
Internal reset
Instruction
execution
119
MB90370/375 Series
(3) Power-on Reset
(VCC = AVCC = CVCC = 3.0 V to 3.6 V, VSS = AVSS = CVSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Symbol Pin name Condition
Unit
Remarks
Min
Max
Parameter
Power supply rise time
Power supply cut-off time
tR
VCC*
tOFF
VCC*
50
ms
1
ms
Due to repeated
operations
* : VCC must be kept lower than 0.2 V before power-on.
Notes : • The above values are used for causing a power-on reset.
Some registers in the device are initialized only upon a power-on reset. To initialize these registers, turn
on the power supply using the above values.
• Make sure that power supply rises within the selected oscillation stabilization time. If the power supply
voltage needs to be varied in the course of operation, a smooth voltage rise is recommended.
tR
tOFF
2.2 V
0.2 V
0.2 V
VCC
0.2 V
Sudden changes in the power supply voltage may cause a power-on reset.
To change the power supply voltage while the device is in operation, it is recommneded
to raise the voltage smoothly to suppress fluctuations as shown below. In this case,
change the supply voltage with the PLL clock not used. If the voltage drop is 1 V
or fewer per second, however, you can use the PLL clock.
VCC
1.8 V
RAM data hold
VSS
120
It is recommended to keep
the rising speed of the supply
voltage at 50 mV/ms or slower.
MB90370/375 Series
(4) UART1 to UART3
(VCC = AVCC = CVCC = 3.0 V to 3.6 V, VSS = AVSS = CVSS = 0.0 V, TA = −40 °C to +85 °C)
Parameter
Symbol
Pin name
Serial clock cycle time
tSCYC
UCK ↓ → UO delay time
tSLOV
Valid UI → UCK ↑
tIVSH
UCK ↑ → valid UI hold time
tSHIX
Serial clock “H” pulse width
Condition
Value
Unit Remarks
Min
Max
UCK1 to UCK3
8 tCP
ns
UCK1 to UCK3
CL = 80 pF + 1 TTL
UO1 to UO3
for an output pin of
UCK1 to UCK3 internal shift clock
UI1 to UI3
mode
UCK1 to UCK3
UI1 to UI3
−80
+80
ns
100
ns
tCP
ns
tSHSL
UCK1 to UCK3
4 tCP
ns
Serial clock “L” pulse width
tSLSH
UCK1 to UCK3
4 tCP
ns
UCK ↓ → UO delay time
tSLOV
150
ns
Valid UI → UCK ↑
tIVSH
60
ns
UCK ↑ → valid UI hold time
tSHIX
60
ns
UCK1 to UCK3 CL = 80 pF + 1 TTL
UO1 to UO3
for an output pin of
external shift clock
UCK1 to UCK3
mode
UI1 to UI3
UCK1 to UCK3
UI1 to UI3
Notes : • These are AC ratings in the CLK synchronous mode.
• CL is the load capacitance value connected to pins while testing.
• tCP is the internal operating clock cycle time.
121
MB90370/375 Series
• Internal shift clock mode
tSCYC
UCK
2.4 V
0.8 V
0.8 V
tSLOV
2.4 V
UO
0.8 V
tIVSH
UI
tSHIX
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
• External shift clock mode
tSLSH
tSHSL
UCK
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
tSLOV
2.4 V
UO
0.8 V
tIVSH
UI
122
tSHIX
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
MB90370/375 Series
(5) Resources Input Timing
(VCC = AVCC = CVCC = 3.0 V to 3.6 V, VSS = AVSS = CVSS = 0.0 V, TA = −40 °C to +85 °C)
Parameter
Timer input pulse width
Symbol
Pin name
Condition
tTIWH
tTIWL
TIN1 to TIN4
0.8 VCC
Value
Min
Max
4 tCP
Unit
Remarks
ns
0.8 VCC
TIN1 to TIN4
0.2 VCC
0.2 VCC
tTIWH
tTIWL
(6) Trigger Input Timing
Parameter
Input pulse width
(VCC = AVCC = CVCC = 3.0 V to 3.6 V, VSS = AVSS = CVSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Symbol
Pin name
Condition
Unit
Remarks
Min
Max
tTRGH
tTRGL
ADTG
INT0 to INT5
KSI0 to KSI7
0.8 VCC
5 tCP
ns
Normal operation
1
µs
Stop mode
0.8 VCC
INT0 to INT5
KSI0 to KSI7
0.2 VCC
tTRGH
0.7 VCC
0.2 VCC
tTRGL
0.7 VCC
ADTG
0.3 VCC
tTRGH
0.3 VCC
tTRGL
123
MB90370/375 Series
(7) I2C / MI2C Timing
Parameter
(VCC = AVCC = CVCC = 3.0 V to 3.6 V, VSS = AVSS = CVSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Symbol Pin name
Unit Remarks
Min
Max
Start condition output
tSTA
SCL
SDA
tCP (m × n/2 − 1) - 20 tCP (m × n/2 − 1) + 20
ns
Master
mode
Stop condition output
tSTO
SCL
SDA
tCP (m × n/2 + 3) - 20 tCP (m × n/2 + 3) + 20
ns
Master
mode
Start condition detect
tSTA
SCL
SDA
tCP + 40
ns
Stop condition detect
tSTO
SCL
SDA
tCP + 40
ns
Restart condition output
tSTASU
SCL
SDA
Restart condition detect
tSTASU
SCL
SDA
tCP + 40
ns
SCL output “L” width
tLOW
SCL
tCP × m x n/2 - 20
tCP × m × n/2 + 20
ns
Master
mode
SCL output “H” width
tHIGH
SCL
ns
Master
mode
tDO
SDA
tDOSU*3
SDA
SCL input “L” pulse
tLOW
SCL input “H” pulse
tCP (m × n/2 + 3) - 20 tCP (m × n/2 + 3) + 20
tCP (m × n/2 + 2) - 20 tCP (m × n/2 + 2) + 20
ns
Master
mode
tCP × 3 − 20
tCP × 3 + 20
ns
tCP × m × n/2 − 20
ns
*1
tCP × 4 − 20
ns
*2
SCL
tCP × 3 + 40
ns
tHIGH
SCL
tCP + 40
ns
SDA output setup time
tSU
SDA
40
ns
SDA hold time
tHO
SDA
0
ns
SDA output delay
SDA output setup time
after interrupt
*1 : At the stop condition or transferring of next byte.
*2 : After setting register bit IBCRH : SCC/MBCRH : SCC at restart.
*3 : tDOSU is longer than the “L” width of SCL.
Notes : • tCP is the internal operating clock cycle time.
• m is the setting bit of shift clock oscillation defined in the “ICCR register (CS4 to CS3) ” and “MCCR register
(CS4 to CS3) ”. Please refer to the MB90370/375 series H/W manual for details.
• n is the setting bit of shift clock oscillation defined in the “ICCR register (CS2 to CS0) ” and “MCCR register
(CS2 to CS0) ”. Please refer to the MB90370/375 series H/W manual for details.
• SDA and SCL output value is specified on condition that the rise/fall time is “0 ns”.
124
MB90370/375 Series
• Data transmit (master / slave)
tDO
tDO
tSU
tHO
tDOSU
ACK
SDA
tSTASU
tSTA
tLOW
tHO
1
SCL
9
• Data receive (master / slave)
tSU
tHO
tDO
tDOSU
ACK
SDA
tHIGH
SCL
tDO
6
7
tLOW
tSTO
8
9
125
MB90370/375 Series
(8) PS/2 Interface Timing
Parameter
Symbol
(VCC = AVCC = CVCC = 3.0 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Pin name
Condition
Unit Remarks
Min
Typ
Max
PSCK clock
cycle time
tPCYC
PSCK0 to PSCK2
PSDA0 to PSDA2
PSCK ↓ → PSDA
tPLOV
Valid PSDA →
PSCK ↓
4 tCP
ns
PSCK0 to PSCCK2 Transmission
PSDA0 to PSDA2 Mode
2 tCP
ns
tPIVSH
PSCK0 to PSCK2
PSDA0 to PSDA2
1 tCP
ns
PSCK ↓ → valid
PSDA hold time
tPHIX
PSCK0 to PSCK2
PSDA0 to PSDA2
1 tCP
ns
PSCK clock “H”
pulse width
tPHSL
PSCK0 to PSCK2
PSDA0 to PSDA2
2 tCP
ns
2 tCP
ns
Reception
Mode
PSCK0 to PSCK2
tPLSH
PSDA0 to PSDA2
Note : tCP is the internal operating clock cycle time.
PSCK clock “L”
pulse width
tPCYC
PSCK0
PSCK1
PSCK2
0.8 VCC
0.8 VCC
0.2 VCC
tPLOV
• Transmission Mode
2.4 V
PSDA0
PSDA1
PSDA2
0.8 V
tPIVSH
• Reception Mode
PSDA0
PSDA1
PSDA2
126
0.8 VCC
0.2 VCC
tPHIX
MB90370/375 Series
(9) LPC Timing
(VCC = AVCC = CVCC = 3.0 V to 3.6 V, VSS = AVSS = CVSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Symbol Pin name Condition
Unit
Remarks
Min
Typ
Max
Parameter
LCLK cycle time
tCYCLE
30
ns
LCLK high time
tHIGH
12
ns
LCLK low time
tLOW
12
ns
LCLK AC timing
tCYCLE
tHIGH
0.7 VCC
0.3 VCC
LCLK
tLOW
127
MB90370/375 Series
LAD, LFRAME, GA20 AC timing
0.4 VCC
LCLK
tVAL
OUTPUT
Delay
tON
Tri-state
OUTPUT
tOFF
0.4 VCC
LCLK
tS
INPUT
128
tH
MB90370/375 Series
5. A/D Converter Electrical Characteristics
(2.7 V ≤ AVR − AVSS, VCC = AVCC = CVCC = 3.0 V to 3.6 V, VSS = AVSS = CVSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Pin
Parameter
Symbol
Unit
Remarks
name
Min
Typ
Max
Resolution
10
bit
Total error
±3.0
LSB
Non-linear error
±2.5
LSB
Differential linearity
error
±1.9
LSB
Zero transition
voltage
VOT
Full-scale transition
voltage
VFST
Conversion time
AN0 to
AN11
AVSS −
1.5 LSB
AVSS +
0.5 LSB
AN0 to
AN11
AVR −
3.5 LSB
AVR −
1.5 LSB
3.1
AVSS +
5.5 LSB
AVSS +
2.5 LSB
AVR +
0.5 LSB
For MB90V370
mV
For MB90F372/F377/372
mV
µs
Actual value is specified as
a sum of values specified in
ADCR0 : CT1, CT0 and
ADCR0 : ST1, ST0. Be sure
that the setting value is
greater than the Min value.
Actual value is specified in
ADCR0 : ST1, ST0 bits. Be
sure that the setting value is
greater than the Min value.
Sampling period
2
µs
Analog port input
current
IAIN
AN0 to
AN11
0.1
10
µA
Analog input
voltage
VAIN
AN0 to
AN11
AVSS
AVR
V
Reference voltage
AVR
AVSS + 2.7
AVCC
V
Power supply
current
IA
1.4
6.4
mA
5
µA
94
300
µA
5
µA
4
LSB
Reference voltage
supply current
Offset between
channels
IAH
IR
IRH
—
AVCC
AVR
AN0 to
AN11
*
*
* : The current when the A/D converter is not operating or the CPU is in stop mode (for VCC = AVCC = AVR = 3.0 V) .
129
MB90370/375 Series
6. A/D Converter Glossary
Resolution :
Linearity error :
Analog changes that are identifiable with the A/D converter.
The deviation of the straight line connecting the zero transition point (“00 0000 0000”
↔ “00 0000 0001”) with the full-scale transition point (“11 1111 1110” ↔ “11 1111
1111”) from actual conversion characteristics.
Differential linearity error : The deviation of input voltage needed to change the output code by 1 LSB from the
theoretical value.
Total error :
The total error is defined as a difference between the actual value and the theoretical
value, which includes zero-transition error/full-scale transition error and linearity error.
Total error
3FF
3FE
Digital output
3FD
Actual conversion
value
0.5 LSB
{1 LSB × (N − 1) + 0.5 LSB}
004
VNT
(Measured value)
003
Actual conversion
value
002
Theoretical
characteristics
001
0.5 LSB
AVRL
AVRH
Analog input
Total error for digital output N =
1 LSB = (Theoretical value)
VNT − {1 LSB × (N − 1) + 0.5 LSB}
1 LSB
AVR − AVss [V]
1024
[LSB]
VOT (Theoretical value) = AVss + 0.5 LSB [V]
VFST (Theoretical value) = AVR − 1.5 LSB [V]
VNT : Voltage at a transition of digital output from (N - 1) to N
(Continued)
130
MB90370/375 Series
(Continued)
Linearity error
Actual conversion
value
3FE
{1 LSB × (N − 1)
+ VOT }
Digital output
3FD
Theoretical
characteristics
VFST
(Measured
value)
004
003
002
001
Actual conversion
value
N+1
VNT
(Measured value)
Actual conversion
value
Digital output
3FF
Differential linearity error
N
V (N + 1) T
(Measured
value)
N−1
VNT
(Measured value)
N−2
Actual conversion
value
Theoretical
characteristics
VOT (Measured value)
AVRL
AVRH
AVRL
Analog input
Linearity error of
=
digital output N
Differential linearity error
=
of digital output N
1 LSB =
AVRH
Analog input
VNT − {1 LSB × (N − 1) + VOT}
1 LSB
V (N + 1) T − VNT
1 LSB
VFST − VOT
1022
[LSB]
− 1 [LSB]
[V]
VOT : Voltage at transition of digital output from “000H” to “001H”
VFST : Voltage at transition of digital output from “3FEH” to “3FFH”
131
MB90370/375 Series
7. Notes on Using A/D Converter
Select the output impedance value for the external circuit of analog input according to the following conditions.
Output impedance values of the external circuit of 4 kΩ or lower are recommended.
When capacitors are connected to external pins, the capacitance of several thousand times the internal capacitor
value is recommended to minimized the effect of voltage distribution between the external capacitor and internal
capacitor.
When the output impedance of the external circuit is too high, the sampling period for analog voltages may not
be sufficient.
• Equipment of analog input circuit model
Sampling and hold circuit
Analog input
Comparator
R
C
R : about 1.9 kΩ
C : about 32.3 pF
Note : Listed values must be considered as standards.
• Error
The smaller the | AVR - AVSS | is, the greater the error would become relatively.
8. D/A Electrical Characteristics
Parameter
(VCC = AVCC = CVCC = 3.0 V to 3.6V, VSS = AVSS = CVSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Symbol Pin name Condition
Unit Remarks
Min
Typ
Max
Resolution
8
bit
Differential linearity error
±0.9
LSB
Non-linearity error
±1.5
LSB
Conversion time
0.6
µs
Analog output impedance
2.0
2.9
3.8
kΩ
Power supply
IDVR
AVCC
460
µA
Current
IDVRS
AVCC
0.1
µA
* : With load capacitance is 20 pF.
132
*
D/A stops
MB90370/375 Series
9. Comparator Electrical Characteristics
(VCC = AVCC = CVCC = 3.3 V to 3.6 V, VSS = AVSS = CVSS = 0.0 V, TA = −40 °C to +85 °C)
Parameter
Symbol
Pin name
Value
Condition
CVRH1
Max
1.1
2.9
V
CVRL
2.9
V
1.1
CVRH1
V
±1
µA
50
µA
active
10
µA
inactive
CVSS
CVCC
V
CVRL
Reference voltage
supply current
ICR
CVRH2
CVRH1
CVRL
Comparator
supply current
ICV
CVCC
VIH
DCIN
DCIN2
VOL1 to VOL3
VSI1 to VSI3
Analog input voltage
Remarks
Typ
CVRH2
Reference voltage
Unit
Min
*
*: Please use the reference voltage of CVRH2, CVRH1 and CVRL to 0.5VCC for MB90F377.
10. Serial IRQ Electrical Characteristics
Parameter
(VCC = AVCC = CVCC = 3.0 V to 3.6 V, VSS = AVSS = CVSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Symbol Pin name Condition
Unit Remarks
Min
Typ
Max
“H” level input voltage
VIH
0.7VCC
VCC
V
“L” level input voltage
VIL
VSS
0.3VCC
V
“H” level output voltage
VOH
VCC − 0.5
V
“L” level output voltage
VOL
0.4
V
11. Flash Memory Program/Erase Characteristics
Parameter
Condition
Sector erase time
Chip erase time
TA = +25 °C
VCC = 3.0 V
Word (16 bit width)
programing time
Program/Erase cycle
Value
Min
Typ
Max
1
15
4
16
10,000
Unit
Remarks
s
Excludes 00H programming prior
to erasure
s
Excludes 00H programming prior
to erasure
3,600
µs
Except for the over head time of
the system
cycle
133
MB90370/375 Series
■ EXAMPLE CHARACTERISTICS
• MB90F372
VCC vs. ICCS
VCC vs. ICC
18.0
50.0
Ta
25 °C
Ta
FCH = 16.0 MHz
25 °C
FCH = 16.0 MHz
16.0
40.0
14.0
FCH = 10.0 MHz
30.0
FCH = 8.0 MHz
20.0
ICCS (mA)
ICC (mA)
FCH = 12.0 MHz
12.0
FCH = 12.0 MHz
10.0
FCH = 10.0 MHz
8.0
FCH = 8.0 MHz
6.0
FCH = 4.0 MHz
4.0
FCH = 2.0 MHz
2.0
10.0
0.0
2.0
2.5
3.0
3.5
4.0
4.5
0.0
2.0
FCH = 4.0 MHz
FCH = 2.0 MHz
2.5
3.0
3.5
4.0
4.5
VCC (V)
VCC (V)
VCC vs. ICCL
30.0
Ta
25 °C
FCL = 32.0 kHz
25.0
ICCL ( A)
20.0
15.0
10.0
5.0
0.0
2.0
2.5
3.0
3.5
4.0
4.5
VCC (V)
(Continued)
134
MB90370/375 Series
(Continued)
IOH2 vs. VCC - VOH2
IOH1 vs. VCC - VOH1
0.7
2.0
Ta
25 °C
Ta
25 °C
0.6
1.5
Vcc = 2.5 V
Vcc = 2.5 V
1.0
Vcc = 3.0 V
Vcc = 3.5 V
VCC - VOH2 (V)
VCC - VOH1 (V)
0.5
0.4
Vcc = 3.0 V
0.3
Vcc = 3.5 V
0.2
0.5
0.1
0.0
0
-2
-4
-8
-6
-10
0.0
0
IOH1 (mA)
-2
-4
-6
-8
-10
IOH2 (mA)
IOL2 vs. VOL2
IOL1 vs. VOL1
0.8
0.3
Ta
25 °C
Ta
Vcc = 2.5 V
0.6
25 °C
Vcc = 3.0 V
Vcc = 2.5 V
Vcc = 3.0 V
Vcc = 3.5 V
VOL2 (V)
VOL1 (V)
0.2
0.4
Vcc = 3.5 V
0.1
0.2
0.0
0
2
4
IOL1 (mA)
6
8
10
0.0
0
2
4
6
8
10
IOL2 (mA)
135
MB90370/375 Series
• MB90372t
VCC vs. ICCS
VCC vs. ICC
40.0
Ta
18.0
25 °C
Ta
FCH = 16.0 MHz
25 °C
16.0
14.0
30.0
20.0
FCH = 8.0 MHz
ICCS (mA)
FCH = 12.0 MHz
FCH = 10.0 MHz
ICC (mA)
FCH = 16.0 MHz
12.0
FCH = 12.0 MHz
10.0
FCH = 10.0 MHz
8.0
FCH = 8.0 MHz
6.0
10.0
0.0
1.5
2.0
2.5
3.0
3.5
FCH = 4.0 MHz
4.0
FCH = 4.0 MHz
FCH = 2.0 MHz
2.0
FCH = 2.0 MHz
4.0
4.5
0.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
VCC (V)
VCC (V)
VCC vs. ICCL
30.0
Ta = + 25 °C
25.0
20.0
ICCL (mA)
FCL = 32.0 kHz
15.0
10.0
5.0
0.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
VCC (V)
(Continued)
136
MB90370/375 Series
(Continued)
IOH1 vs. VCC - VOH1
IOH2 vs. VCC - VOH2
1.0
0.4
Ta
25 °C
Ta
25 °C
Vcc = 2.5 V
Vcc = 2.5 V
Vcc = 3.0 V
0.6
Vcc = 3.5 V
0.4
0.3
VCC - VOH2 (V)
VCC - VOH1 (V)
0.8
Vcc = 3.0 V
Vcc = 3.5 V
0.2
0.1
0.2
0.0
0
-2
-4
-6
-8
0.0
-10
0
-2
IOH1 (mA)
-4
-6
-8
-10
IOH2 (mA)
IOL1 vs. VOL1
IOL2 vs. VOL2
0.25
0.8
Ta
25 °C
Vcc = 2.5 V
Ta
25 °C
Vcc = 2.5 V
0.20
Vcc = 3.0 V
Vcc = 3.0 V
0.6
0.4
VOL2 (V)
VOL1 (V)
Vcc = 3.5 V
Vcc = 3.5 V
0.15
0.10
0.2
0.05
0.0
0.0
0
2
4
6
IOL1 (mA)
8
10
0
2
4
6
8
10
IOL2 (mA)
137
MB90370/375 Series
■ ORDERING INFORMATION
Part number
MB90F372PFF-G
MB90F377PFF-G
MB90372PFF-G-XXX
138
Package
144-pin Plastic LQFP
(FPT-144P-M12)
Remarks
XXX is the ROM release number.
MB90370/375 Series
■ PACKAGE DIMENSION
144-pin plastic LQFP
(FPT-144P-M12)
Note 1) * : These dimensions include resin protrusion.
Resin protrusion is +0.25(.010)Max(each side).
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
18.00±0.20(.709±.008)SQ
+0.40
+.016
*16.00 –0.10 .630 –.004 SQ
73
108
72
109
0.08(.003)
Details of "A" part
+0.20
1.50 –0.10
+.008
(Mounting height)
.059 –.004
INDEX
0~8˚
37
144
LEAD No.
1
0.60±0.15
(.024±.006)
36
0.40(.016)
C
"A"
0.18±0.035
.007±.001
+0.05
0.07(.003)
M
0.145 –0.03
.006
0.10±0.05
(.004±.002)
(Stand off)
0.25(.010)
+.002
–.001
2003 FUJITSU LIMITED F144024S-c-3-3
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
139
MB90370/375 Series
FUJITSU LIMITED
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representatives before ordering.
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circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of
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operation of the device with respect to use based on such
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device based on such information, you must assume any
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and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
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and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile
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extremely high reliability (i.e., submersible repeater and artificial
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Please note that Fujitsu will not be liable against you and/or any
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If any products described in this document represent goods or
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F0402
FUJITSU LIMITED Printed in Japan