FUJITSU SEMICONDUCTOR DATA SHEET DS05-20883-2E FLASH MEMORY CMOS 16M (2M × 8/1M × 16) BIT MBM29LV160TE/BE -70/90/12 ■ GENERAL DESCRIPTION The MBM29LV160TE/BE is a 16M-bit, 3.0 V-only Flash memory organized as 2M bytes of 8 bits each or 1M words of 16 bits each. The MBM29LV160TE/BE is offered in a 48-pin TSOP (I), 48-pin CSOP and 48-ball FBGA packages. The device is designed to be programmed in-system with the standard system 3.0 V VCC supply. 12.0 V VPP and 5.0 V VCC are not required for write or erase operations. The device can also be reprogrammed in standard EPROM programmers. The standard MBM29LV160TE/BE offers access times of 70 ns, 90 ns and 120 ns, allowing operation of highspeed microprocessors without wait states. To eliminate bus contention the device has separate chip enable (CE), write enable (WE), and output enable (OE) controls. The MBM29LV160TE/BE is pin and command set compatible with JEDEC standard E2PROMs. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from 5.0 V and 12.0 V Flash or EPROM devices. The MBM29LV160TE/BE is programmed by executing the program command sequence. This will invoke the Embedded ProgramTM* Algorithm which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margins. Typically, each sector can be programmed and verified in about 0.5 seconds. Erase is accomplished by executing the erase command sequence. This will invoke the Embedded EraseTM* Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margins. Any individual sector is typically erased and verified in 1.0 second. (If already preprogrammed.) within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed one byte/word at a time using the EPROM programming mechanism of hot electron injection. (Continued) ■ PRODUCT LINE UP Part No. MBM29LV160TE/160BE VCC = 3.3 V +0.3 V –0.3 V 70 — — VCC = 3.0 V +0.6 V –0.3 V — 90 12 Max. Address Access Time (ns) 70 90 120 Max. CE Access Time (ns) 70 90 120 Max. OE Access Time (ns) 30 35 50 Ordering Part No. MBM29LV160TE/BE-70/90/12 (Continued) The device also features a sector erase architecture. The sector mode allows each sector to be erased and reprogrammed without affecting other sectors. The MBM29LV160TE/BE is erased when shipped from the factory. The device features single 3.0 V power supply operation for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. A low VCC detector automatically inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ7, by the Toggle Bit feature on DQ6, or the RY/BY output pin. Once the end of a program or erase cycle has been comleted, the device internally resets to the read mode. The MBM29LV160TE/BE also has a hardware RESET pin. When this pin is driven low, execution of any Embedded Program Algorithm or Embedded Erase Algorithm is terminated. The internal state machine is then reset to the read mode. The RESET pin may be tied to the system reset circuitry. Therefore, if a system reset occurs during the Embedded Program Algorithm or Embedded Erase Algorithm, the device is automatically reset to the read mode and will have erroneous data stored in the address locations being programmed or erased. These locations need re-writing after the Reset. Resetting the device enables the system’s microprocessor to read the boot-up firmware from the Flash memory. Fujitsu’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability, and cost effectiveness. The MBM29LV160TE/BE memory electrically erases all bits within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed one byte/word at a time using the EPROM programming mechanism of hot electron injection. * : Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc. ■ PACKAGES 48-pin plastic TSOP (I) 48-pin plastic TSOP (I) Marking Side Marking Side 2 (FPT-48P-M19) (FPT-48P-M20) 48-pin plastic CSOP 48-pin plastic FBGA (LCC-48P-M03) (BGA-48P-M11) MBM29LV160TE/BE-70/90/12 ■ FEATURES • 0.23 µm Process Technology • Single 3.0 V read, program and erase Minimizes system level power requirements • Compatible with JEDEC-standard commands Uses same software commands as E2PROMs • Compatible with JEDEC-standard world-wide pinouts 48-pin TSOP (I) (Package suffix: TN-Normal Bend Type, TR-Reversed Bend Type) 48-pin CSOP (Package suffix: PCV) 48-ball FBGA (Package suffix: PBT) • Minimum 100,000 program/erase cycles • High performance 70 ns maximum access time • Sector erase architecture One 8K word, two 4K words, one 16K word, and thirty-one 32K words sectors in word mode One 16K byte, two 8K bytes, one 32K byte, and thirty-one 64K bytes sectors in byte mode Any combination of sectors can be concurrently erased. Also supports full chip erase • Boot Code Sector Architecture T = Top sector B = Bottom sector • Embedded EraseTM Algorithms Automatically pre-programs and erases the chip or any sector • Embedded ProgramTM Algorithms Automatically programs and verifies data at specified address • Data Polling and Toggle Bit feature for detection of program or erase cycle completion • Ready/Busy output (RY/BY) Hardware method for detection of program or erase cycle completion • Automatic sleep mode When addresses remain stable, automatically switches themselves to low power mode • Low VCC write inhibit ≤ 2.5 V • Erase Suspend/Resume Suspends the erase operation to allow a read data and/or program in another sector within the same device • Sector protection Hardware method disables any combination of sectors from program or erase operations • Sector Protection Set function by Extended sector Protection command • Fast Programming Function by Extended command • Temporary sector unprotection Temporary sector unprotection via the RESET pin • In accordance with CFI (Common Flash Memory Interface) 3 MBM29LV160TE/BE-70/90/12 ■ PIN ASSIGNMENTS TSOP(I) A15 A14 A13 A12 A11 A10 A9 A8 A19 N.C. WE RESET N.C. N.C. RY/BY A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 (Marking Side) Standard Pinout 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 BYTE VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE VSS CE A0 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 45 45 46 47 48 A0 CE VSS OE DQ0 DQ8 DQ1 DQ9 DQ2 DQ10 DQ3 DQ11 VCC DQ4 DQ12 DQ5 DQ13 DQ6 DQ14 DQ7 DQ15/A-1 VSS BYTE A16 (FPT-48P-M19) A1 A2 A3 A4 A5 A6 A7 A17 A18 RY/BY N.C. N.C. RESET WE N.C. A19 A8 A9 A10 A11 A12 A13 A14 A15 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 (Marking Side) Reverse Pinout (FPT-48P-M20) (Continued) 4 MBM29LV160TE/BE-70/90/12 (Continued) CSOP (TOP VIEW) A1 A2 A3 A4 A5 A6 A7 A17 A18 RY/BY N.C. N.C. RESET WE N.C. A19 A8 A9 A10 A11 A12 A13 A14 A15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 (Marking side) A0 CE VSS OE DQ0 DQ8 DQ1 DQ9 DQ2 DQ10 DQ3 DQ11 VCC DQ4 DQ12 DQ5 DQ13 DQ6 DQ14 DQ7 DQ15/A-1 VSS BYTE A16 (LCC-48P-M03) FBGA (TOP VIEW) Marking side A1 A2 A3 A4 A5 A6 B1 B2 B3 B4 B5 B6 C1 C2 C3 C4 C5 C6 D1 D2 D3 D4 D5 D6 E1 E2 E3 E4 E5 E6 F1 F2 F3 F4 F5 F6 G1 G2 G3 G4 G5 G6 H1 H2 H3 H4 H5 H6 (BGA-48P-M11) A1 A3 A2 A7 A3 RY/BY A4 WE A5 A9 A6 A13 B1 A4 B2 A17 B3 N.C. B4 RESET B5 A8 B6 A12 C1 A2 C2 A6 C3 A18 C4 N.C. C5 A10 C6 A14 D1 A1 D2 A5 D3 N.C. D4 A19 D5 A11 D6 A15 E1 A0 E2 DQ0 E3 DQ2 E4 DQ5 E5 DQ7 E6 A16 F1 CE F2 DQ8 F3 DQ10 F4 DQ12 F5 DQ14 F6 BYTE G1 OE G2 DQ9 G3 DQ11 G4 VCC G5 DQ13 G6 DQ15/A-1 H1 VSS H2 DQ1 H3 DQ3 H4 DQ4 H5 DQ6 H6 VSS 5 MBM29LV160TE/BE-70/90/12 ■ BLOCK DIAGRAM DQ0 to DQ15 VCC VSS RY/BY Buffer RY/BY Input/Output Buffer Erase Voltage Generator WE BYTE State Control RESET Command Register Program Voltage Generator Chip Enable Output Enable Logic CE STB Data Latch OE STB Low VCC Detector A0 to A19 A-1 6 Timer for Program/Erase Address Latch Y-Decoder Y-Gating X-Decoder Cell Matrix MBM29LV160TE/BE-70/90/12 ■ LOGIC SYMBOL Table 1 MBM29LV160TE/BE Pin Configuration Pin A-1 20 A0 to A19 16 or 8 DQ0 to DQ15 CE OE RY/BY A-1, A0 to A19 Address Inputs DQ0 to DQ15 Data Inputs/Outputs CE Chip Enable OE Output Enable WE Write Enable RY/BY Ready/Busy Output RESET Hardware Reset Pin/ Temporary Sector Unprotection WE RESET BYTE Function BYTE Selects 8-bit or 16-bit mode N.C. Pin Not Connected Internally VSS Device Ground VCC Device Power Supply 7 MBM29LV160TE/BE-70/90/12 ■ DEVICE BUS OPERATIONS Table 2 MBM29LV160TE/BE User Bus Operation (BYTE = VIH) CE OE WE A0 A1 A6 A9 Auto-Select Manufacture Code (1) L L H L L L VID Code H Auto-Select Device Code (1) L L H H L L VID Code H Read (3) L L H A0 A1 A6 A9 DOUT H Standby H X X X X X X HIGH-Z H Output Disable L H H X X X X HIGH-Z H Write (Program/Erase) L H L A0 A1 A6 A9 DIN H Enable Sector Protection (2), (4) L VID L H L VID X H Verify Sector Protection (2), (4) L L H L H L VID Code H Temporary Sector Unprotection (5) X X X X X X X X VID Reset (Hardware)/Standby X X X X X X X HIGH-Z L Operation Table 3 DQ0 to DQ15 RESET MBM29LV160TE/BE User Bus Operation (BYTE = VIL) Operation 15 / WE DQ A-1 CE OE Auto-Select Manufacture Code (1) L L H Auto-Select Device Code (1) L L Read (3) L Standby A0 A1 A6 A9 DQ0 to DQ7 RESET L L L L VID Code H H L H L L VID Code H L H A-1 A0 A1 A6 A9 DOUT H H X X X X X X X HIGH-Z H Output Disable L H H X X X X X HIGH-Z H Write (Program/Erase) L H L A-1 A0 A1 A6 A9 DIN H Enable Sector Protection (2), (4) L VID L L H L VID X H Verify Sector Protection (2), (4) L L H L L H L VID Code H Temporary Sector Unprotection (5) X X X X X X X X X VID Reset (Hardware)/Standby X X X X X X X X HIGH-Z L Legend: L = VIL, H = VIH, X = VIL or VIH. = Pulse input. See DC Characteristics for voltage levels. Notes: 1. Manufacturer and device codes may also be accessed via a command register write sequence. See Table 7. 2. Refer to the section on Sector Protection. 3. WE can be VIL if OE is VIL, OE at VIH initiates the write operations. 4. VCC = 3.3 V ±10% 5. It is also used for the extended sector protection. 8 MBM29LV160TE/BE-70/90/12 ■ FLEXIBLE SECTOR-ERASE ARCHITECTURE • • • • One 8K word, two 4K words, one 16K word, and thirty-one 32K words sectors in word mode. One 16K byte, two 8K bytes, one 32K byte, and thirty-one 64K bytes sectors in byte mode. Individual-sector, multiple-sector, or bulk-erase capability. Individual or multiple-sector protection is user definable. Sector SA0 Sector Size 64 Kbytes or 32 Kwords (× 8) Address Range 00000H to 0FFFFH (× 16) Address Range 00000H to 07FFFH SA1 64 Kbytes or 32 Kwords 10000H to 1FFFFH 08000H to 0FFFFH SA2 64 Kbytes or 32 Kwords 20000H to 2FFFFH 10000H to 17FFFH SA3 64 Kbytes or 32 Kwords 30000H to 3FFFFH 18000H to 1FFFFH SA4 64 Kbytes or 32 Kwords 40000H to 4FFFFH 20000H to 27FFFH SA5 64 Kbytes or 32 Kwords 50000H to 5FFFFH 28000H to 2FFFFH SA6 64 Kbytes or 32 Kwords 60000H to 6FFFFH 30000H to 37FFFH SA7 64 Kbytes or 32 Kwords 70000H to 7FFFFH 38000H to 3FFFFH SA8 64 Kbytes or 32 Kwords 80000H to 8FFFFH 40000H to 47FFFH SA9 64 Kbytes or 32 Kwords 90000H to 9FFFFH 48000H to 4FFFFH SA10 64 Kbytes or 32 Kwords A0000H to AFFFFH 50000H to 57FFFH SA11 64 Kbytes or 32 Kwords B0000H to BFFFFH 58000H to 5FFFFH SA12 64 Kbytes or 32 Kwords C0000H to CFFFFH 60000H to 67FFFH SA13 64 Kbytes or 32 Kwords D0000H to DFFFFH 68000H to 6FFFFH SA14 64 Kbytes or 32 Kwords E0000H to EFFFFH 70000H to 77FFFH SA15 64 Kbytes or 32 Kwords F0000H to FFFFFH 78000H to 7FFFFH SA16 64 Kbytes or 32 Kwords 100000H to 10FFFFH 80000H to 87FFFH SA17 64 Kbytes or 32 Kwords 110000H to 11FFFFH 88000H to 8FFFFH SA18 64 Kbytes or 32 Kwords 120000H to 12FFFFH 90000H to 97FFFH SA19 64 Kbytes or 32 Kwords 130000H to 13FFFFH 98000H to 9FFFFH SA20 64 Kbytes or 32 Kwords 140000H to 14FFFFH A0000H to A7FFFH SA21 64 Kbytes or 32 Kwords 150000H to 15FFFFH A8000H to AFFFFH SA22 64 Kbytes or 32 Kwords 160000H to 16FFFFH B0000H to B7FFFH SA23 64 Kbytes or 32 Kwords 170000H to 17FFFFH B8000H to BFFFFH SA24 64 Kbytes or 32 Kwords 180000H to 18FFFFH C0000H to C7FFFH SA25 64 Kbytes or 32 Kwords 190000H to 19FFFFH C8000H to CFFFFH SA26 64 Kbytes or 32 Kwords 1A0000H to 1AFFFFH D0000H to D7FFFH SA27 64 Kbytes or 32 Kwords 1B0000H to 1BFFFFH D8000H to DFFFFH SA28 64 Kbytes or 32 Kwords 1C0000H to 1CFFFFH E0000H to E7FFFH SA29 64 Kbytes or 32 Kwords 1D0000H to 1DFFFFH E8000H to EFFFFH SA30 64 Kbytes or 32 Kwords 1E0000H to 1EFFFFH F0000H to F7FFFH SA31 32 Kbytes or 16 Kwords 1F0000H to 1F7FFFH F8000H to FBFFFH SA32 8 Kbytes or 4 Kwords 1F8000H to 1F9FFFH FC000H to FCFFFH SA33 8 Kbytes or 4 Kwords 1FA000H to 1FBFFFH FD000H to FDFFFH SA34 16 Kbytes or 8 Kwords 1FC000H to 1FFFFFH FE000H to FFFFFH MBM29LV160TE Top Boot Sector Architecture 9 MBM29LV160TE/BE-70/90/12 Sector SA0 Sector Size 16 Kbytes or 8 Kwords (× 8) Address Range 00000H to 03FFFH (× 16) Address Range 00000H to 01FFFH SA1 8 Kbytes or 4 Kwords 04000H to 05FFFH 02000H to 02FFFH SA2 8 Kbytes or 4 Kwords 06000H to 07FFFH 03000H to 03FFFH SA3 32 Kbytes or 16 Kwords 08000H to 0FFFFH 04000H to 07FFFH SA4 64 Kbytes or 32 Kwords 10000H to 1FFFFH 08000H to 0FFFFH SA5 64 Kbytes or 32 Kwords 20000H to 2FFFFH 10000H to 17FFFH SA6 64 Kbytes or 32 Kwords 30000H to 3FFFFH 18000H to 1FFFFH SA7 64 Kbytes or 32 Kwords 40000H to 4FFFFH 20000H to 27FFFH SA8 64 Kbytes or 32 Kwords 50000H to 5FFFFH 28000H to 2FFFFH SA9 64 Kbytes or 32 Kwords 60000H to 6FFFFH 30000H to 37FFFH SA10 64 Kbytes or 32 Kwords 70000H to 7FFFFH 38000H to 3FFFFH SA11 64 Kbytes or 32 Kwords 80000H to 8FFFFH 40000H to 47FFFH SA12 64 Kbytes or 32 Kwords 90000H to 9FFFFH 48000H to 4FFFFH SA13 64 Kbytes or 32 Kwords A0000H to AFFFFH 50000H to 57FFFH SA14 64 Kbytes or 32 Kwords B0000H to BFFFFH 58000H to 5FFFFH SA15 64 Kbytes or 32 Kwords C0000H to CFFFFH 60000H to 67FFFH SA16 64 Kbytes or 32 Kwords D0000H to DFFFFH 68000H to 6FFFFH SA17 64 Kbytes or 32 Kwords E0000H to EFFFFH 70000H to 77FFFH SA18 64 Kbytes or 32 Kwords F0000H to FFFFFH 78000H to 7FFFFH SA19 64 Kbytes or 32 Kwords 100000H to 10FFFFH 80000H to 87FFFH SA20 64 Kbytes or 32 Kwords 110000H to 11FFFFH 88000H to 8FFFFH SA21 64 Kbytes or 32 Kwords 120000H to 12FFFFH 90000H to 97FFFH SA22 64 Kbytes or 32 Kwords 130000H to 13FFFFH 98000H to 9FFFFH SA23 64 Kbytes or 32 Kwords 140000H to 14FFFFH A0000H to A7FFFH SA24 64 Kbytes or 32 Kwords 150000H to 15FFFFH A8000H to AFFFFH SA25 64 Kbytes or 32 Kwords 160000H to 16FFFFH B0000H to B7FFFH SA26 64 Kbytes or 32 Kwords 170000H to 17FFFFH B8000H to BFFFFH SA27 64 Kbytes or 32 Kwords 180000H to 18FFFFH C0000H to C7FFFH SA28 64 Kbytes or 32 Kwords 190000H to 19FFFFH C8000H to CFFFFH SA29 64 Kbytes or 32 Kwords 1A0000H to 1AFFFFH D0000H to D7FFFH SA30 64 Kbytes or 32 Kwords 1B0000H to 1BFFFFH D8000H to DFFFFH SA31 64 Kbytes or 32 Kwords 1C0000H to 1CFFFFH E0000H to E7FFFH SA32 64 Kbytes or 32 Kwords 1D0000H to 1DFFFFH E8000H to EFFFFH SA33 64 Kbytes or 32 Kwords 1E0000H to 1EFFFFH F0000H to F7FFFH SA34 64 Kbytes or 32 Kwords 1F0000H to 1FFFFFH F8000H to FFFFFH MBM29LV160BE Bottom Boot Sector Architecture 10 MBM29LV160TE/BE-70/90/12 ■ FUNCTIONAL DESCRIPTION • Read Mode The MBM29LV160TE/BE has two control functions which must be satisfied in order to obtain data at the outputs. CE is the power control and should be used for a device selection. OE is the output control and should be used to gate data to the output pins if a device is selected. Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable access time (tCE) is the delay from stable addresses and stable CE to valid data at the output pins. The output enable access time is the delay from the falling edge of OE to valid data at the output pins. (Assuming the addresses have been stable for at least tACC - tOE time.) When reading out a data without changing addresses after power-up, it is necessary to input hardware reset or to change CE pin from “H” or “L”. • Standby Mode There are two ways to implement the standby mode on the MBM29LV160TE/BE devices. One is by using both the CE and RESET pins; the other via the RESET pin only. When using both pins, a CMOS standby mode is achieved with CE and RESET inputs both held at VCC ±0.3 V. Under this condition the current consumed is less than 5 µA max. During Embedded Algorithm operation, VCC Active current (ICC2) is required even CE = “H”. The device can be read with standard access time (tCE) from either of these standby modes. When using the RESET pin only, a CMOS standby mode is achieved with the RESET input held at VSS ±0.3 V (CE = “H” or “L”). Under this condition the current consumed is less than 5 µA max. Once the RESET pin is taken high, the device requires tRH of wake up time before outputs are valid for read access. In the standby mode, the outputs are in the high-impedance state, independent of the OE input. • Automatic Sleep Mode There is a function called automatic sleep mode to restrain power consumption during read-out of MBM29LV160TE/BE data. This mode can be used effectively with an application requesting low power consumption such as handy terminals. To activate this mode, MBM29LV160TE/BE automatically switches itself to low power mode when addresses remain stable for 150 ns. It is not necessary to control CE, WE, and OE in this mode. During such mode, the current consumed is typically 1 µA (CMOS Level). Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. • Output Disable If the OE input is at a logic high level (VIH), output from the device is disabled. This will cause the output pins to be in a high-impedance state. • Autoselect The Autoselect mode allows the reading out of a binary code from the device and will identify its manufacturer and type. The intent is to allow programming equipment to automatically match the device to be programmed with its corresponding programming algorithm. The Autoselect command may also be used to check the status of write-protected sectors. (See Tables 4.1 and 4.2.) This mode is functional over the entire temperature range of the device. To activate this mode, the programming equipment must force VID (11.5 V to 12.5 V) on address pin A9. Two identifier bytes may then be sequenced from the devices outputs by toggling address A0 from VIL to VIH. All addresses are DON’T CARES except A0, A1, and A6 (A-1). (See Table 2 or Table 3.) 11 MBM29LV160TE/BE-70/90/12 The manufacturer and device codes may also be read via the command register, for instances when the MBM29LV160TE/BE is erased or programmed in a system without access to high voltage on the A9 pin. The command sequence is illustrated in Table 7, Command Definitions. Byte 0 (A0 = VIL) represents the manufacture’s code and byte 1 (A0 = VIH) represents the device identifier code. For the MBM29LV160TE/BE these two bytes are given in the Table 4.2. All identifiers for manufactures and device will exhibit odd parity with DQ7 defined as the parity bit. In order to read the proper device codes when executing the Autoselect, A1 must be VIL. (See Tables 2 or 3.) For device indentification in word mode (BYTE = VIH), DQ9 and DQ13 are equal to ‘1’ and DQ8, DQ10 to DQ12, DQ14, and DQ15 are equal to ‘0’. If BYTE = VIL (for byte mode), the device code is C4H (for top boot block) or 49H (for bottom boot block). If BYTE = VIH (for word mode), the device code is 22C4H (for top boot block) or 2249H (for bottom boot block). In order to determine which sectors are write protected, A1 must be at VIH while running through the sector addresses; if the selected sector is protected, a logical ‘1’ will be output on DQ0 (DQ0 =1). Table 4.1 MBM29LV160TE/BE Sector Protection Verify Autoselect Code Type A12 to A19 A6 A1 A0 A-1*1 Code (HEX) X VIL VIL VIL VIL 04H VIL C4H X VIL VIL VIH X 22C4H VIL 49H X 2249H VIL 01H*2 Manufacture’s Code Byte MBM29LV160TE Word Device Code Byte MBM29LV160BE X VIL VIL VIH Word Sector Addresses Sector Protection VIH VIL VIL *1: A-1 is for Byte mode. *2: Outputs 01H at protected sector addresses and outputs 00H at unprotected sector addresses. Table 4.2 Expanded Autoselect Code Table Type Code Manufacture’s Code DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 04H A-1/0 (B) 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 C4H A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z 1 1 0 0 0 1 0 0 1 1 0 0 0 1 0 0 49H A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z 0 1 0 0 1 0 0 1 MBM29LV160TE (W) 22C4H Device Code (B) 0 0 1 0 0 0 1 0 MBM29LV160BE (W) 2249H Sector Protection (B): Byte mode (W): Word mode 12 0 01H A-1/0 0 1 0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 MBM29LV160TE/BE-70/90/12 Table 5 Sector Address Tables (MBM29LV160TE) Sector Address A19 A18 A17 A16 A15 A14 A13 A12 (× 8) Address Range (× 16) Address Range SA0 0 0 0 0 0 X X X 00000H to 0FFFFH 00000H to 07FFFH SA1 0 0 0 0 1 X X X 10000H to 1FFFFH 08000H to 0FFFFH SA2 0 0 0 1 0 X X X 20000H to 2FFFFH 10000H to 17FFFH SA3 0 0 0 1 1 X X X 30000H to 3FFFFH 18000H to 1FFFFH SA4 0 0 1 0 0 X X X 40000H to 4FFFFH 20000H to 27FFFH SA5 0 0 1 0 1 X X X 50000H to 5FFFFH 28000H to 2FFFFH SA6 0 0 1 1 0 X X X 60000H to 6FFFFH 30000H to 37FFFH SA7 0 0 1 1 1 X X X 70000H to 7FFFFH 38000H to 3FFFFH SA8 0 1 0 0 0 X X X 80000H to 8FFFFH 40000H to 47FFFH SA9 0 1 0 0 1 X X X 90000H to 9FFFFH 48000H to 4FFFFH SA10 0 1 0 1 0 X X X A0000H to AFFFFH 50000H to 57FFFH SA11 0 1 0 1 1 X X X B0000H to BFFFFH 58000H to 5FFFFH SA12 0 1 1 0 0 X X X C0000H to CFFFFH 60000H to 67FFFH SA13 0 1 1 0 1 X X X D0000H to DFFFFH 68000H to 6FFFFH SA14 0 1 1 1 0 X X X E0000H to EFFFFH 70000H to 77FFFH SA15 0 1 1 1 1 X X X F0000H to FFFFFH 78000H to 7FFFFH SA16 1 0 0 0 0 X X X 100000H to 10FFFFH 80000H to 87FFFH SA17 1 0 0 0 1 X X X 110000H to 11FFFFH 88000H to 8FFFFH SA18 1 0 0 1 0 X X X 120000H to 12FFFFH 90000H to 97FFFH SA19 1 0 0 1 1 X X X 130000H to 13FFFFH 98000H to 9FFFFH SA20 1 0 1 0 0 X X X 140000H to 14FFFFH A0000H to A7FFFH SA21 1 0 1 0 1 X X X 150000H to 15FFFFH A8000H to AFFFFH SA22 1 0 1 1 0 X X X 160000H to 16FFFFH B0000H to B7FFFH SA23 1 0 1 1 1 X X X 170000H to 17FFFFH B8000H to BFFFFH SA24 1 1 0 0 0 X X X 180000H to 18FFFFH C0000H to C7FFFH SA25 1 1 0 0 1 X X X 190000H to 19FFFFH C8000H to CFFFFH SA26 1 1 0 1 0 X X X 1A0000H to 1AFFFFH D0000H to D7FFFH SA27 1 1 0 1 1 X X X 1B0000H to 1BFFFFH D8000H to DFFFFH SA28 1 1 1 0 0 X X X 1C0000H to 1CFFFFH E0000H to E7FFFH SA29 1 1 1 0 1 X X X 1D0000H to 1DFFFFH E8000H to EFFFFH SA30 1 1 1 1 0 X X X 1E0000H to 1EFFFFH F0000H to F7FFFH SA31 1 1 1 1 1 0 X X 1F0000H to 1F7FFFH F8000H to FBFFFH SA32 1 1 1 1 1 1 0 0 1F8000H to 1F9FFFH FC000H to FCFFFH SA33 1 1 1 1 1 1 0 1 1FA000H to 1FBFFFH FD000H to FDFFFH SA34 1 1 1 1 1 1 1 X 1FC000H to 1FFFFFH FE000H to FEFFFH 13 MBM29LV160TE/BE-70/90/12 Table 6 14 Sector Address Tables (MBM29LV160BE) Sector Address A19 A18 A17 A16 A15 A14 A13 A12 (× 8) Address Range (× 16) Address Range SA0 0 0 0 0 0 0 0 X 00000H to 03FFFH 00000H to 01FFFH SA1 0 0 0 0 0 0 1 0 04000H to 05FFFH 02000H to 02FFFH SA2 0 0 0 0 0 0 1 1 06000H to 07FFFH 03000H to 03FFFH SA3 0 0 0 0 0 1 0 X 08000H to 0FFFFH 04000H to 07FFFH SA4 0 0 0 0 1 X X X 10000H to 1FFFFH 08000H to 0FFFFH SA5 0 0 0 1 0 X X X 20000H to 2FFFFH 10000H to 17FFFH SA6 0 0 0 1 1 X X X 30000H to 3FFFFH 18000H to 1FFFFH SA7 0 0 1 0 0 X X X 40000H to 4FFFFH 20000H to 27FFFH SA8 0 0 1 0 1 X X X 50000H to 5FFFFH 28000H to 2FFFFH SA9 0 0 1 1 0 X X X 60000H to 6FFFFH 30000H to 37FFFH SA10 0 0 1 1 1 X X X 70000H to 7FFFFH 38000H to 3FFFFH SA11 0 1 0 0 0 X X X 80000H to 8FFFFH 40000H to 47FFFH SA12 0 1 0 0 1 X X X 90000H to 9FFFFH 48000H to 4FFFFH SA13 0 1 0 1 0 X X X A0000H to AFFFFH 50000H to 57FFFH SA14 0 1 0 1 1 X X X B0000H to BFFFFH 58000H to 5FFFFH SA15 0 1 1 0 0 X X X C0000H to CFFFFH 60000H to 67FFFH SA16 0 1 1 0 1 X X X D0000H to DFFFFH 68000H to 6FFFFH SA17 0 1 1 1 0 X X X E0000H to EFFFFH 70000H to 77FFFH SA18 0 1 1 1 1 X X X F0000H to FFFFFH 78000H to 7FFFFH SA19 1 0 0 0 0 X X X 100000H to 1FFFFFH 80000H to 87FFFH SA20 1 0 0 0 1 X X X 110000H to 11FFFFH 88000H to 8FFFFH SA21 1 0 0 1 0 X X X 120000H to 12FFFFH 90000H to 97FFFH SA22 1 0 0 1 1 X X X 130000H to 13FFFFH 98000H to 9FFFFH SA23 1 0 1 0 0 X X X 140000H to 14FFFFH A0000H to A7FFFH SA24 1 0 1 0 1 X X X 150000H to 15FFFFH A8000H to 8FFFFH SA25 1 0 1 1 0 X X X 160000H to 16FFFFH B0000H to B7FFFH SA26 1 0 1 1 1 X X X 170000H to 17FFFFH B8000H to BFFFFH SA27 1 1 0 0 0 X X X 180000H to 18FFFFH C0000H to C7FFFH SA28 1 1 0 0 1 X X X 190000H to 19FFFFH C8000H to CFFFFH SA29 1 1 0 1 0 X X X 1A0000H to 1AFFFFH D0000H to D7FFFH SA30 1 1 0 1 1 X X X 1B0000H to 1BFFFFH D8000H to DFFFFH SA31 1 1 1 0 0 X X X 1C0000H to 1CFFFFH E0000H to E7FFFH SA32 1 1 1 0 1 X X X 1D0000H to 1DFFFFH E8000H to EFFFFH SA33 1 1 1 1 0 X X X 1E0000H to 1EFFFFH F0000H to F7FFFH SA34 1 1 1 1 1 X X X 1F0000H to 1FFFFFH F8000H to FFFFFH MBM29LV160TE/BE-70/90/12 • Write Device erasure and programming are accomplished via the command register. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. The command register itself does not occupy any addressable memory location. The register is a latch used to store the commands, along with the address and data information needed to execute the command. The command register is written by bringing WE to VIL, while CE is at VIL and OE is at VIH. Addresses are latched on the falling edge of WE or CE, whichever happens later; while data is latched on the rising edge of WE or CE, whichever happens first. Standard microprocessor write timings are used. Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters. • Sector Protection The MBM29LV160TE/BE features hardware sector protection. This feature will disable both program and erase operations in any number of sectors (0 through 34). The sector protection feature is enabled using programming equipment at the user’s site. The device is shipped with all sectors unprotected. To activate this mode, the programming equipment must force VID on address pin A9 and control pin OE, CE = VIL, A0 = A6 = VIL, A1 = VIH. The sector addresses pins (A19, A18, A17, A16, A15, A14, A13, and A12) should be set to the sector to be protected. Tables 5 and 6 define the sector address for each of the thirty five (35) individual sectors. Programming of the protection circuitry begins on the falling edge of the WE pulse and is terminated with the rising edge of the same. Sector addresses must be held constant during the WE pulse. See Figures 17 and 24 for sector protection waveforms and algorithm. To verify programming of the protection circuitry, the programming equipment must force VID on address pin A9 with CE and OE at VIL and WE at VIH. Scanning the sector addresses (A19, A18, A17, A16, A15, A14, A13, and A12) while (A6, A1, A0) = (0, 1, 0) will produce a logical “1” at device output DQ0 for a protected sector. Otherwise the device will read 00H for an unprotected sector. In this mode, the lower order addresses, except for A0, A1, and A6 are DON’T CARES. Address locations with A1 = VIL are reserved for Autoselect manufacturer and device codes. A-1 requires to VIL in byte mode. It is also possible to determine if a sector is protected in the system by writing an Autoselect command. Performing a read operation at the address location XX02H, where the higher order addresses pins (A19, A18, A17, A16, A15, A14, A13, and A12) represents the sector address will produce a logical “1” at DQ0 for a protected sector. See Tables 4.1 and 4.2 for Autoselect codes. • Temporary Sector Unprotection This feature allows temporary unprotection of previously protected sectors of the MBM29LV160TE/BE devices in order to change data. The Sector Unprotection mode is activated by setting the RESET pin to high voltage (VID). During this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. Once the VID is taken away from the RESET pin, all the previously protected sectors will be protected again. (See Figures 18 and 25.) 15 MBM29LV160TE/BE-70/90/12 Table 7 Command Sequence Read/Reset Read/Reset Autoselect Program Chip Erase Sector Erase Byte Word Byte Word Byte Word Byte Word Byte Word Byte Second Bus Fifth Bus Bus First Bus Third Bus Fourth Sixth Bus Bus Read/Write Write Write Cycle Write Cycle Write Cycle Write Cycle Write Cycle Cycle Cycles Req’d Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data 1 3 3 4 6 6 XXXH F0H 555H AAAH 555H AAAH 555H AAAH 555H AAAH 555H AAAH AAH AAH AAH AAH AAH — 2AAH 555H 2AAH 555H 2AAH 555H 2AAH 555H 2AAH 555H — 55H 55H 55H 55H 55H — 555H AAAH 555H AAAH 555H AAAH 555H AAAH 555H AAAH — — — — — — — F0H RA RD — — — — 90H — — — — — — A0H PA PD — — — — 80H 80H 555H AAAH 555H AAAH AAH AAH 2AAH 555H 2AAH 555H 55H 555H AAAH 10H 55H SA 30H Erase Suspend 1 XXXH B0H — — — — — — — — — — Erase Resume 1 XXXH 30H — — — — — — — — — — 20H — — — — — — Set to Fast Mode Word Byte 3 Word Fast Program *1 Byte 2 Reset from Fast Mode *1 Word 2 Extended Sector Protection *2 Word Query *3 16 Word MBM29LV160TE/BE Standard Command Definitions Byte Byte Word Byte 555H AAAH XXXH XXXH AAH A0H XXXH 4 1 XXXH 90H XXXH 60H 55H AAH 98H 2AAH 555H 55H 555H AAAH PA PD — — — — — — — — XXXH *4 F0H — — — — — — — — SPA 60H SPA 40H SPA SD — — — — — — — — — — — — — — XXXH MBM29LV160TE/BE-70/90/12 Notes: 1. Address bits A11 to A19 = X = “H” or “L” for all address commands except or Program Address (PA) and Sector Address (SA). 2. Bus operations are defined in Tables 2 and 3. 3. RA =Address of the memory location to be read. PA =Address of the memory location to be programmed. Addresses are latched on the falling edge of the WE pulse. SA =Address of the sector to be erased. The combination of A19, A18, A17, A16, A15, A14, A13, and A12 will uniquely select any sector. 4. RD =Data read from location RA during read operation. PD =Data to be programmed at location PA. Data is latched on the rising edge of WE. 5. SPA =Sector address to be protected. Set sector address (SA) and (A6, A1, A0) = (0, 1, 0). SD =Sector protection verify data. Output 01H at protected sector addressed and output 00H at unprotected sector addresses. 6. The system should generate the following address patterns: Word Mode: 555H or 2AAH to addresses A0 to A10 Byte Mode: AAAH or 555H to addresses A-1 to A10 7. Both Read/Reset commands are functionally equivalent, resetting the device to the read mode. *1: This command is valid while Fast Mode. *2: This command is valid while RESET = VID. *3: The valid addresses are A6 to A0. The other addresses are “Don’t care”. *4: The data “00H” is also acceptable. 17 MBM29LV160TE/BE-70/90/12 ■ COMMAND DEFINITIONS Device operations are selected by writing specific address and data sequences into the command register. Writing incorrect address and data values or writing them in an improper sequence will reset the device to the read mode. Table 7 defines the valid register command sequences. Note that the Erase Suspend (B0H) and Erase Resume (30H) commands are valid only while the Sector Erase operation is in progress. Moreover both Read/Reset commands are functionally equivalent, resetting the device to the read mode. Please note that commands are always written at DQ0 to DQ7 and DQ8 to DQ15 bits are ignored. • Read/Reset Command In order to return from Autoselect mode or Exceeded Timing Limits (DQ5 = 1) to read mode, the read/reset operation is initiated by writing the Read/Reset command sequence into the command register. Microprocessor read cycles retrieve array data from the memory. The device remains enabled for reads until the command register contents are altered. The device will automatically power-up in the Read/Reset state. In this case, a command sequence is not required to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no spurious alteration of the memory contents occurs during the power transition. Refer to the AC Read Characteristics and Waveforms for specific timing parameters. (See Figure 5.1.) • Autoselect Command Flash memories are intended for use in applications where the local CPU alters memory contents. As such, manufactures and device codes must be accessible while the device resides in the target system. PROM programmers typically access the signature codes by raising A9 to a high voltage. However, multiplexing high voltage onto the address lines is not generally desired system design practice. The device contains an Autoselect command operation to supplement traditional PROM programming methodology. The operation is initiated by writing the Autoselect command sequence into the command register. Following the last command write, a read cycle from address XX00H retrieves the manufacture code of 04H. A read cycle from address XX01H for ×16 (XX02H for ×8) retrieves the device code (MBM29LV160TE = C4H and MBM29LV160BE = 49H for ×8 mode; MBM29LV160TE = 22C4H and MBM29LV160BE = 2249H for ×16 mode). (See Tables 4.1 and 4.2.) All manufactures and device codes will exhibit odd parity with DQ7 defined as the parity bit. The sector state (protection or unprotection) will be indicated by address XX02H for ×16 (XX04H for ×8). Scanning the sector addresses (A19, A18, A17, A16, A15, A14, A13, and A12) while (A6, A1, A0) = (0, 1, 0) will produce a logical “1” at device output DQ0 for a protected sector. The programming verification should be perform margin mode verification on the protected sector. (See Tables 2 and 3.) To terminate the operation, it is necessary to write the Read/Reset command sequence into the register and, also to write the Autoselect command during the operation, by executing it after writing the Read/Reset command sequence. • Byte/Word Programming The device is programmed on a byte-by-byte (or word-by-word) basis. Programming is a four bus cycle operation. There are two “unlock” write cycles. These are followed by the program set-up command and data write cycles. Addresses are latched on the falling edge of CE or WE, whichever happens later and the data is latched on the rising edge of CE or WE, whichever happens first. The rising edge of the last CE or WE (whichever happens first) begins programming. Upon executing the Embedded Program Algorithm command sequence, the system is not required to provide further controls or timings. The device will automatically provide adequate internally generated program pulses and verify the programmed cell margin. (See Figures 6 and 7.) The automatic programming operation is completed when the data on DQ7 is equivalent to data written to this bit at which time the device return to the read mode and addresses are no longer latched. (See Table 8, Hardware Sequence Flags.) Therefore, the device requires that a valid address be supplied by the system at this time. Hence, Data Polling must be performed at the memory location which is being programmed. Any commands written to the chip during this period will be ignored. If hardware reset occures during the programming operation, it is impossible to guarantee whether the data being written is correct or not. 18 MBM29LV160TE/BE-70/90/12 Programming is allowed in any sequence and across sector boundaries. Beware that a data “0” cannot be programmed back to a “1”. Attempting to do so may either hang up the device or result in an apparent success according to the data polling algorithm but a read from read/reset mode will show that the data is still “0”. Only erase operations can convert “0”s to “1”s. Figure 20 illustrates the Embedded ProgramTM Algorithm using typical command strings and bus operations. • Chip Erase Chip erase is a six-bus cycle operation. There are two “unlock” write cycles. These are followed by writing the “set-up” command. Two more “unlock” write cycles are then followed by the chip erase command. Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded Erase Algorithm command sequence the device will automatically program and verify the entire memory for an all zero data pattern prior to electrical erase. (Preprogram Function.) The system is not required to provide any controls or timings during these operations. The automatic erase begins on the rising edge of the last WE pulse in the command sequence and terminates when the data on DQ7 is “1” (See Write Operation Status section.) at which time the device returns to read mode. (See Figure 8.) Figure 21 illustrates the Embedded EraseTM Algorithm using typical command strings and bus operations. • Sector Erase Sector erase is a six-bus cycle operation. There are two “unlock” write cycles, followed by writing the “set-up” command. Two more “unlock” write cycles are then followed by the Sector Erase command. The sector address (any address location within the desired sector) is latched on the falling edge of WE, while the command (Data = 30H) is latched on the rising edge of WE. After a time-out of “tTOW” from the rising edge of the last sector erase command, the sector erase operation will begin. Multiple sectors may be erased concurrently by writing six-bus cycle operations on Table 7. This sequence is followed with writes of the Sector Erase command to addresses in other sectors desired to be concurrently erased. The time between writes must be less than “tTOW” otherwise that command will not be accepted and erasure will start. It is recommended that processor interrupts be disabled during this time to guarantee this condition. The interrupts can be re-enabled after the last Sector Erase command is written. A time-out of “tTOW” from the rising edge of the last WE will initiate the execution of the Sector Erase command(s). If another falling edge of the WE occurs within the “tTOW” time-out window the timer is reset. Monitor DQ3 to determine if the sector erase timer window is still open. (See section DQ3, Sector Erase Timer.) Any command other than Sector Erase or Erase Suspend during this time-out period will reset the device to the read mode, ignoring the previous command string. Resetting the device once excution has begun will corrupt the data in the sector. In that case, restart the erase on those sectors and allow them to complete. (Refer to the Write Operation Status section for Sector Erase Timer operation.) Loading the sector erase buffer may be done in any sequence and with any number of sectors (0 to 34). Sector erase does not require the user to program the device prior to erase. The device automatically programs all memory locations in the sector(s) to be erased prior to electrical erase (Preprogram Function). When erasing a sector or sectors the remaining unselected sectors are not affected. The system is not required to provide any controls or timings during these operations. The automatic sector erase begins after the “tTOW” time out from the rising edge of the WE pulse for the last sector erase command pulse and terminates when the data on DQ7 is “1” (See Write Operation Status section) at which time the device returns to the read mode. Data polling must be performed at an address within any of the sectors being erased. Multiple Sector Erase Time; [Sector Program Time (Preprogramming) + Sector Erase Time] × Number of Sector Erase. Figure 21 illustrates the Embedded EraseTM Algorithm using typical command strings and bus operations. • Erase Suspend/Resume The Erase Suspend command allows the user to interrupt a Sector Erase operation and then perform data reads from or program to a sector not being erased. This command is applicable ONLY during the Sector Erase operation which includes the time-out period for sector erase. The Erase Suspend command will be ignored if 19 MBM29LV160TE/BE-70/90/12 written during the Chip Erase operation or Embedded Program Algorithm. Writting the Erase Suspend command during the Sector Erase time-out results in immediate termination of the time-out period and suspension of the erase operation. Writing the Erase Resume command resumes the erase operation. The addresses are “DON’T CARES” when writing the Erase Suspend or Erase Resume commands. When the Erase Suspend command is written during the Sector Erase operation, the device will take a maximum of “tSPD” to suspend the erase operation. When the devices have entered the erase-suspended mode, the RY/BY output pin and the DQ7 bit will be at logic “1”, and DQ6 will stop toggling. The user must use the address of the erasing sector for reading DQ6 and DQ7 to determine if the erase operation has been suspended. Further writes of the Erase Suspend command are ignored. When the erase operation has been suspended, the device defaults to the erase-suspend-read mode. Reading data in this mode is the same as reading from the standard read mode except that the data must be read from sectors that have not been erase-suspended. Successively reading from the erase-suspended sector while the device is in the erase-suspend-read mode will cause DQ2 to toggle. (See the section on DQ2.) After entering the erase-suspend-read mode, the user can program the device by writing the appropriate command sequence for Program. This Program mode is known as the erase-suspend-program mode. Again, programming in this mode is the same as programming in the regular Program mode except that the data must be programmed to sectors that are not erase-suspended. Successively reading from the erase-suspended sector while the devices are in the erase-suspend-program mode will cause DQ2 to toggle. The end of the erasesuspended Program operation is detected by the RY/BY output pin, Data polling of DQ7, or the Toggle Bit (DQ6) which is the same as the regular Program operation. Note that DQ7 must be read from the Program address while DQ6 can be read from any address. To resume the operation of Sector Erase, the Resume command (30H) should be written. Any further writes of the Resume command at this point will be ignored. Another Erase Suspend command can be written after the chip has resumed erasing. 20 MBM29LV160TE/BE-70/90/12 • Extended Command (1) Fast Mode MBM29LV160TE/BE has Fast Mode function. This mode dispenses with the initial two unlock cycles required in the standard program command sequence writing Fast Mode command into the command register. In this mode, the required bus cycle for programming is two cycles instead of four bus cycles in standard program command. (Do not write erase command in this mode.) The read operation is also executed after exiting this mode. To exit this mode, it is necessary to write Fast Mode Reset command into the command register. (Refer to the Figure 26 Extended algorithm.) The VCC active current is required even CE = VIH during Fast Mode. (2) Fast Programming During Fast Mode, the programming can be executed with two bus cycles operation. The Embedded Program Algorithm is executed by writing program set-up command (A0H) and data write cycles (PA/PD). (Refer to the Figure 26 Extended algorithm.) (3) Extended Sector Protection In addition to normal sector protection, the MBM29LV160TE/BE has Extended Sector Protection as extended function. This function enable to protect sector by forcing VID on RESET pin and write a commnad sequence. Unlike conventional procedure, it is not necessary to force VID and control timing for control pins. The only RESET pin requires VID for sector protection in this mode. The extended sector protect requires VID on RESET pin. With this condition, the operation is initiated by writing the set-up command (60H) into the command register. Then, the sector addresses pins (A19, A18, A17, A16, A15, A14, A13 and A12) and (A6, A1, A0) = (0, 1, 0) should be set to the sector to be protected (recommend to set VIL for the other addresses pins), and write extended sector protect command (60H). A sector is typically protected in 250 µs. To verify programming of the protection circuitry, the sector addresses pins (A19, A18, A17, A16, A15, A14, A13 and A12) and (A6, A1, A0) = (0, 1, 0) should be set and write a command (40H). Following the command write, a logical “1” at device output DQ0 will produce for protected sector in the read operation. If the output data is logical “0”, please repeat to write extended sector protect command (60H) again. To terminate the operation, it is necessary to set RESET pin to VIH. (4) CFI (Common Flash Memory Interface) The CFI (Common Flash Memory Interface) specification outlines device and host system software interrogation handshake which allows specific vendor-specified software algorithms to be used for entire families of devices. This allows device-independent, JEDEC ID-independent, and forward-and backwardcompatible software support for the specified flash device families. Refer to CFI specification in detail. The operation is initiated by writing the query command (98H) into the command register. Following the command write, a read cycle from specific address retrives device information. Please note that output data of upper byte (DQ8 to DQ15) is “0” in word mode (16 bit) read. Refer to the CFI code table. To terminate operation, it is necessary to write the read/reset command sequence into the register. 21 MBM29LV160TE/BE-70/90/12 • Write Operation Status Table 8 Hardware Sequence Flags Status DQ7 DQ6 DQ5 DQ3 DQ2 Embedded Program Algorithm DQ7 Toggle 0 0 1 0 Toggle 0 1 Toggle 1 1 0 0 Toggle Data Data Data Data Data DQ7 Toggle (Note 1) 0 0 1 (Note 2) DQ7 Toggle 1 0 1 0 Toggle 1 1 N/A DQ7 Toggle 1 0 N/A Embedded/Erase Algorithm In Progress Erase Suspend Read (Erase Suspended Sector) Erase Erase Suspend Read Suspend (Non-Erase Suspended Sector) Mode Erase Suspend Program (Non-Erase Suspended Sector) Embedded Program Algorithm Exceeded Time Limits Embedded/Erase Algorithm Erase Suspend Program (Non-Erase Suspended Sector) Notes: 1. Performing successive read operations from any address will cause DQ6 to toggle. 2. Reading the byte address being programmed while in the erase-suspend program mode will indicate logic “1” at the DQ2 bit. However, successive reads from the erase-suspended sector will cause DQ2 to toggle. 3. DQ0 and DQ1 are reserve pins for future use. 4. DQ4 is Fujitsu internal use only. • DQ7 Data Polling The MBM29LV160TE/BE device features Data Polling as a method to indicate to the host that the Embedded Algorithms are in progress or completed. During the Embedded Program Algorithm, an attempt to read the devices will produce the complement of the data last written to DQ7. Upon completion of the Embedded Program Algorithm, an attempt to read the device will produce the true data last written to DQ7. During the Embedded Erase Algorithm, an attempt to read the device will produce a “0” at the DQ7 output. Upon completion of the Embedded Erase Algorithm an attempt to read the device will produce a “1” at the DQ7 output. The flowchart for Data Polling (DQ7) is shown in Figure 22. For chip erase and sector erase, Data Polling is valid after the rising edge of the sixth WE pulse in the six-write pulse sequence. Data Polling must be performed at a sector address within any of the sectors being erased and not at a protected sector. Otherwise, the status may not be valid. Once the Embedded Algorithm operation is close to being completed, the MBM29LV160TE/BE data pins (DQ7) may change asynchronously while the output enable (OE) is asserted low. This means that the device is driving status information on DQ7 at one instant of time and then that byte’s valid data at the next instant of time. Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the device has completed the Embedded Program Algorithm operation and DQ7 has a valid data, the data outputs on DQ0 to DQ6 may be still invalid. The valid data on DQ0 to DQ7 will be read on successive read attempts. The Data Polling feature is only active during the Embedded Programming Algorithm, Embedded Erase Algorithm or sector erase time-out. See Figure 9 for the Data Polling timing specifications and diagram. 22 MBM29LV160TE/BE-70/90/12 • DQ6 Toggle Bit I The MBM29LV160TE/BE also feature the “Toggle Bit I” as a method to indicate to the host system that the Embedded Algorithms are in progress or completed. During an Embedded Program or Erase Algorithm cycle, successive attempts to read (OE toggling) data from the device will result in DQ6 toggling between one and zero. Once the Embedded Program or Erase Algorithm cycle is completed, DQ6 will stop toggling and valid data can be read on the next successive attempts. During programming, the Toggle Bit I is valid after the rising edge of the fourth WE pulse in the four write pulse sequence. For chip erase and sector erase, the Toggle Bit I is valid after the rising edge of the sixth WE pulse in the sixwrite pulse sequence. The Toggle Bit I is active during the sector time out. In programming, if the sector being written to is protected, the toggle bit will toggle for about 2 µs and then stop toggling without the data having changed. In erase, the device will erase all the selected sectors except for the ones that are protected. If all selected sectors are protected, the chip will toggle the Toggle Bit I for about 200 µs and then drop back into read mode, having changed none of the data. Either CE or OE toggling will cause the DQ6 to toggle. In addition, an Erase Suspend/Resume command will cause the DQ6 to toggle. See Figure 10 and Figure 23 for the Toggle Bit I timing specifications and diagram. • DQ5 Exceeded Timing Limits DQ5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count). Under these conditions DQ5 will produce a “1”. This is a failure condition which indicates that the program or erase cycle was not successfully completed. Data Polling is the only operating function of the device under this condition. The CE circuit will partially power down the device under these conditions. The OE and WE pins will control the output disable functions as described in Tables 2 and 3. The DQ5 failure condition may also appear if a user tries to program a non blank location without erasing. In this case the device locks out and never completes the Embedded Algorithm operation. Hence, the system never reads a valid data on DQ7 and DQ6 never stops toggling. Once the device has exceeded timing limits, the DQ5 bit will indicate a “1.” Please note that this is not a device failure condition since the device was incorrectly used. If this occurs, reset the device with command sequence. • DQ3 Sector Erase Timer After the completion of the initial sector erase command sequence the sector erase time-out will begin. DQ3 will remain low until the time-out is complete. Data Polling and Toggle Bit I are valid after the initial sector erase command sequence. If Data Polling or the Toggle Bit I indicates the device has been written with a valid erase command, DQ3 may be used to determine if the sector erase timer window is still open. If DQ3 is high (“1”) the internally controlled erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase operation is completed as indicated by Data Polling or Toggle Bit I. If DQ3 is low (“0”), the device will accept additional sector erase commands. To insure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent sector erase command. If DQ3 is high on the second status check, the command may not have been accepted. See Table 8: Hardware Sequence Flags. 23 MBM29LV160TE/BE-70/90/12 • DQ2 Toggle Bit II This Toggle Bit II, along with DQ6, can be used to determine whether the device is in the Embedded Erase Algorithm or in Erase Suspend. Successive reads from the erasing sector will cause DQ2 to toggle during the Embedded Erase Algorithm. If the device is in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause DQ2 to toggle. When the device is in the erase-suspended-program mode, successive reads from the byte address of the non-erase suspended sector will indicate a logic “1” at DQ2. DQ6 is different from DQ2 in that DQ6 toggles only when the standard program or Erase, or Erase Suspend Program operation is in progress. For example, DQ2 and DQ6 can be used together to determine if the erase-suspend-read mode is in progress. (DQ2 toggles while DQ6 does not.) See also Table 9 and Figure 11. Furthermore, DQ2 can also be used to determine which sector is being erased. When the device is in the erase mode, DQ2 toggles if this bit is read from an erasing sector. Table 9 Toggle Bit Status DQ7 DQ6 DQ2 DQ7 Toggle 1 Erase 0 Toggle Toggle Erase Suspend Read (Erase Suspended Sector) (Note 1) 1 1 Toggle DQ7 Toggle (Note 1) 1 (Note 2) Mode Program Erase-Suspend Program Notes: 1. Performing successive read operations from any address will cause DQ6 to toggle. 2. Reading the byte address being programmed while in the erase-suspend program mode will indicate logic “1” at the DQ2 bit. However, successive reads from the erase-suspended sector will cause DQ2 to toggle. • RY/BY Ready/Busy Pin The MBM29LV160TE/BE provides a RY/BY open-drain output pin as a way to indicate to the host system that the Embedded Algorithms are either in progress or has been completed. If the output is low, the device is busy with either a program or erase operation. If the output is high, the device is ready to accept any read/write or erase operation. When the RY/BY pin is low, the devices will not accept any additional program or erase commands with the exception of the Erase Suspend command. If the MBM29LV160TE/BE is placed in an Erase Suspend mode, the RY/BY output will be high, by means of connecting with a pull-up resister to VCC. During programming, the RY/BY pin is driven low after the rising edge of the fourth WE pulse. During an erase operation, the RY/BY pin is driven low after the rising edge of the sixth WE pulse. The RY/BY pin will indicate a busy condition during the RESET pulse. See Figures 12 and 13 for a detailed timing diagram. The RY/BY pin is pulled high in standby mode. Since this is an open-drain output, RY/BY pins can be tied together in parallel with a pull-up resistor to VCC. 24 MBM29LV160TE/BE-70/90/12 • RESET Hardware Reset Pin The MBM29LV160TE/BE device may be reset by driving the RESET pin to VIL. The RESET pin has a pulse requirement and has to be kept low (VIL) for at least “tRP” in order to properly reset the internal state machine. Any operation in the process of being executed will be terminated and the internal state machine will be reset to the read mode “tREADY” after the RESET pin is driven low. Furthermore, once the RESET pin goes high, the device requires an additional “tRH” before it allows read access. When the RESET pin is low, the device will be in the standby mode for the duration of the pulse and all the data output pins will be tri-stated. If a hardware reset occurs during a program or erase operation, the data at that particular location will be corrupted. Please note that the RY/BY output signal should be ignored during the RESET pulse. Refer to Figure 13 for the timing diagram. Refer to Temporary Sector Unprotection for additional functionality. If hardware reset occurs during Embedded Erase Algorithm, there is a possibility that the erasing sector(s) will need to be erased again before they can be programmed. • Byte/Word Configuration The BYTE pin selects the byte (8-bit) mode or word (16-bit) mode for the MBM29LV160TE/BE device. When this pin is driven high, the device operates in the word (16-bit) mode. The data is read and programmed at DQ0 to DQ15. When this pin is driven low, the device operates in byte (8-bit) mode. Under this mode, DQ15/A-1 pin becomes the lowest address bit and DQ8 to DQ14 bits are tri-stated. However, the command bus cycle is always an 8-bit operation and hence commands are written at DQ0 to DQ7 and DQ8 to DQ15 bits are ignored. Refer to Figures 14, 15 and 16 for the timing diagram. • Data Protection The MBM29LV160TE/BE is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transitions. During power up the device automatically resets the internal state machine to the Read mode. Also, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific multi-bus cycle command sequence. The device also incorporates several features to prevent inadvertent write cycles resulting form VCC power-up and power-down transitions or system noise. • Low VCC Write Inhibit To avoid initiation of a write cycle during VCC power-up and power-down, a write cycle is locked out for VCC less than VLKO (min.). If VCC < VLKO, the command register is disabled and all internal program/erase circuits are disabled. Under this condition, the device will reset to the read mode. Subsequent writes will be ignored until the VCC level is greater than VLKO. It is the users responsibility to ensure that the control pins are logically correct to prevent unintentional writes when VCC is above VLKO (min.). If the Embedded Erase Algorithm is interrupted, there is possibility that the erasing sector(s) will need to be erased again prior to programming. • Write Pulse “Glitch” Protection Noise pulses of less than 5 ns (typical) on OE, CE, or WE will not change the command registers. • Logical Inhibit Writing is inhibited by holding any one of OE = VIL, CE = VIH, or WE = VIH. To initiate a write, CE and WE must be a logical zero while OE is a logical one. • Power-up Write Inhibit Power-up of the devices with WE = CE = VIL and OE = VIH will not accept commands on the rising edge of WE. The internal state machine is automatically reset to read mode on power-up. 25 MBM29LV160TE/BE-70/90/12 Table 10 A0 to A6 DQ0 to DQ15 A0 to A6 DQ0 to DQ15 Query-unique ASCII string “QRY” 10h 11h 12h 0051h 0052h 0059h Erase Block Region 1 Information 2Dh 2Eh 2Fh 30h 0000h 0000h 0040h 0000h Primary OEM Command Set 2h: AMD/FJ standard type 13h 14h 0002h 0000h Erase Block Region 2 Information 31h 32h 33h 34h 0001h 0000h 0020h 0000h Address for Primary Extended Table 15h 16h 0040h 0000h Alternate OEM Command Set (00h = not applicable) 17h 18h 0000h 0000h Erase Block Region 3 Information 35h 36h 37h 38h 0000h 0000h 0080h 0000h Address for Alternate OEM Extended Table 19h 1Ah 0000h 0000h VCC Min. (write/erase) D7-4: volt, D3-0: 100 mvolt 1Bh 0027h Erase Block Region 4 Information 39h 3Ah 3Bh 3Ch 001Eh 0000h 0000h 0001h VCC Max. (write/erase) D7-4: volt, D3-0: 100 mvolt 1Ch 0036h VPP Min. voltage 1Dh 0000h Query-unique ASCII string “PRI” 40h 41h 42h 0050h 0052h 0049h VPP Max. voltage 1Eh 0000h Typical timeout per single byte/word write 2N µs 1Fh 0004h Major version number, ASCII 43h 0031h Typical timeout for Min. size buffer write 2N µs 20h 0000h Minor version number, ASCII 44h 0031h 45h 0000h 21h 000Ah Address Sensitive Unlock 0 = Required 1 = Not Required Typical timeout per individual block erase 2N ms Typical timeout for full chip erase 2N ms 22h 0000h 46h 0002h Max. timeout for byte/word write 2N times typical 23h 0005h Erase Suspend 0 = Not Supported 1 = To Read Only 2 = To Read & Write Max. timeout for buffer write 2N times typical 24h 0000h 47h 0001h Max. timeout per individual block erase 2N times typical 25h 0004h Sector Protect 0 = Not Supported X = Number of sectors in per group 48h 0001h Max. timeout for full chip erase 2N times typical 26h 0000h Sector Temporary Unprotect 00 = Not Supported 01 = Supported Device Size = 2N byte 27h 0015h Sector Protection Algorithm 49h 04h Flash Device Interface description 28h 29h 0002h 0000h Number of Sector for Bank 2 00h = Not Supported 4Ah 00h Max. number of byte in multi-byte write = 2N 2Ah 2Bh 0000h 0000h Burst Mode Type 00h = Not Supported 4Bh 00h Number of Erase Block Regions within device 2Ch 0004h Page Mode Type 00h = Not Supported 4Ch 00h Description 26 Common Flash Memory Interface Code Description MBM29LV160TE/BE-70/90/12 ■ ABSOLUTE MAXIMUM RATINGS Parameter Symbol Rating Unit Min. Max. Tstg –55 +125 °C TA –40 +85 °C VIN, VOUT –0.5 VCC+0.5 V Power Supply Voltage (Note 1) VCC –0.5 +5.5 V A9, OE, and RESET (Note 2) VIN –0.5 +13.0 V Storage Temperature Ambient Temperature with Power Applied Voltage with Respect to Ground All pins except A9, OE, RESET (Note 1) Notes: 1. Minimum DC voltage on input or l/O pins are –0.5 V. During voltage transitions, inputs may negative overshoot VSS to –2.0 V for periods of up to 20 ns. Maximum DC voltage on output and l/O pins are VCC +0.5 V. During voltage transitions,outputs may positive overshoot to VCC +2.0 V for periods of up to 20 ns. 2. Minimum DC input voltage on A9, OE, and RESET pins are –0.5 V. During voltage transitions, A9, OE, and RESET pins may negative overshoot VSS to –2.0 V for periods of up to 20 ns. Maximum DC input voltage on A9, OE, and RESET pins are +13.0 V which may positive overshoot to 14.0 V for periods of up to 20 ns. Voltage difference between input voltage and supply voltage (VIN – VCC) do not exceed 9 V. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. ■ RECOMMENDED OPERATING CONDITIONS Parameter Ambient Temperature Power Supply Voltage Symbol (-70) (-90/12) (-70) (-90/12) TA VCC Value Unit Min. Typ. Max. –20 +70 °C –40 +85 °C +3.0 +3.6 V +2.7 +3.6 V Operating ranges define those limits between which the functionality of the device is quaranteed. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 27 MBM29LV160TE/BE-70/90/12 ■ MAXIMUM OVERSHOOT +0.6 V 20 ns 20 ns -0.5 V -2.0 V 20 ns Figure 1 Maximum Negative Overshoot Waveform 20 ns VCC + 2.0 V VCC + 0.5 V +2.0 V 20 ns 20 ns Figure 2 Maximum Positive Overshoot Waveform 1 20 ns +14.0 V +13.0 V VCC + 0.5 V 20 ns 20 ns Note : This waveform is applied for A9, OE, and RESET. Figure 3 Maximum Positive Overshoot Waveform 2 28 MBM29LV160TE/BE-70/90/12 ■ ELECTRICAL CHARACTERISTICS 1. DC Characteristics Parameter Symbol Parameter Description Test Conditions Min. Max. Unit ILI Input Leakage Current VIN = VSS to VCC, VCC = VCC Max. –1.0 +1.0 µA ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCC Max. –1.0 +1.0 µA ILIT A9, OE, RESET Inputs Leakage Current VCC = VCC Max., A9, OE, RESET = 12.5 V — 35 µA ICC1 CE = VIL, OE = VIH f = 10 MHz Byte CE = VIL, OE = VIH f = 5 MHz Byte 30 — Word mA 35 VCC Active Current (Note 1) 15 — Word mA 17 ICC2 VCC Active Current (Note 2) CE = VIL, OE = VIH — 35 mA ICC3 VCC Current (Standby) VCC = VCC Max., CE = VCC ±0.3 V, RESET = VCC ±0.3 V — 5 µA ICC4 VCC Current (Standby, RESET) VCC = VCC Max., RESET = VSS ±0.3 V — 5 µA ICC5 VCC = VCC Max., CE = VSS ±0.3 V, VCC Current RESET = VCC ±0.3 V, (Automatic Sleep Mode) (Note 3) VIN = VCC ±0.3 V or VSS ±0.3 V — 5 µA VIL Input Low Level — –0.5 0.6 V VIH Input High Level — 2.0 VCC + 0.3 V VID Voltage for Autoselect,Sector Protection, and Temporary Sector Unprotection (A9, OE, RESET) (Note 4) — 11.5 12.5 V VOL Output Low Voltage Level IOL = 4.0 mA, VCC = VCC Min. — 0.45 V IOH = –2.0 mA, VCC = VCC Min. 2.4 — V VCC – 0.4 — V 2.3 2.5 V VOH1 Output High Voltage Level VOH2 VLKO Notes: 1. 2. 3. 4. IOH = –100 µA Low VCC Lock-Out Voltage — The lCC current listed includes both the DC operating current and the frequency dependent component. lCC active while Embedded Erase or Embedded Program is in progress. Automatic sleep mode enables the low power mode when address remain stable for 150 ns. (VID – VCC) do not exceed 9 V. 29 MBM29LV160TE/BE-70/90/12 2. AC Characteristics • Read Only Operations Characteristics Parameter Symbols Description JEDEC Standard tAVAV tRC Read Cycle Time tAVQV tACC tELQV Test Setup 70 (Note) 90 (Note) 12 (Note) Unit — Min. 70 90 120 ns Address to Output Delay CE = VIL OE = VIL Max. 70 90 120 ns tCE Chip Enable to Output Delay OE = VIL Max. 70 90 120 ns tGLQV tOE Output Enable to Output Delay — Max. 30 35 50 ns tEHQZ tDF Chip Enable to Output HIGH-Z — Max. 25 30 30 ns tGHQZ tDF Output Enable to Output HIGH-Z — Max. 25 30 30 ns tAXQX tOH Output Hold Time From Address, CE or OE, Whichever Occurs First — Min. 0 0 0 ns — tREADY RESET Pin Low to Read Mode — Max. 20 20 20 µs — tELFL tELFH CE or BYTE Switching Low or High — Max. 5 5 5 ns Note : Test Conditions: Output Load:1 TTL gate and 30 pF (MBM29LV160TD/BD-70) 1 TTL gate and 100 pF (MBM29LV160TD/BD-90/12) Input rise and fall times: 5 ns Input pulse levels: 0.0 V to 3.0 V Timing measurement reference level Input: 1.5 V Output:1.5 V 3.3 V IN3064 or Equivalent Device Under Test 2.7 kΩ 6.2 kΩ CL Diodes = IN3064 or Equivalent Figure 4 Test Conditions 30 MBM29LV160TE/BE-70/90/12 • Write (Erase/Program) Operations Parameter Symbols Description 70 90 12 Unit Min. 70 90 120 ns Address Setup Time Min. 0 0 0 ns tAH Address Hold Time Min. 45 45 50 ns tDVWH tDS Data Setup Time Min. 35 45 50 ns tWHDX tDH Data Hold Time Min. 0 0 0 ns — tOES Output Enable Setup Time Min. 0 0 0 ns 0 0 0 ns tOEH Output Enable Read Hold Time Toggle and Data Polling Min. — Min. 10 10 10 ns JEDEC Standard tAVAV tWC Write Cycle Time tAVWL tAS tWLAX tGHWL tGHWL Read Recover Time Before Write Min. 0 0 0 ns tGHEL tGHEL Read Recover Time Before Write (OE High to CE Low) Min. 0 0 0 ns tELWL tCS CE Setup Time Min. 0 0 0 ns tWLEL tWS WE Setup Time Min. 0 0 0 ns tWHEH tCH CE Hold Time Min. 0 0 0 ns tEHWH tWH WE Hold Time Min. 0 0 0 ns tWLWH tWP Write Pulse Width Min. 35 45 50 ns tELEH tCP CE Pulse Width Min. 35 45 50 ns tWHWL tWPH Write Pulse Width High Min. 25 25 30 ns tEHEL tCPH CE Pulse Width High Min. 25 25 30 ns 8 8 8 tWHWH1 tWHWH1 16 16 16 Byte Programming Operation Typ. Word tWHWH2 tWHWH2 — µs Sector Erase Operation (Note 1) Typ. 1 1 1 s tVCS VCC Setup Time Min. 50 50 50 µs — tVIDR Rise Time to VID (Note 2) Min. 500 500 500 ns — tVLHT Voltage Transition Time (Note 2) Min. 4 4 4 µs — tWPP Write Pulse Width (Note 2) Min. 100 100 100 µs — tOESP OE Setup Time to WE Active (Note 2) Min. 4 4 4 µs — tCSP CE Setup Time to WE Active (Note 2) Min. 4 4 4 µs — tRB Recover Time From RY/BY Min. 0 0 0 ns (Continued) 31 MBM29LV160TE/BE-70/90/12 (Continued) Parameter Symbols Description 70 90 12 Unit Min. 500 500 500 ns RESET High Level Period Before Read Min. 200 200 200 ns tBUSY Program/Erase Valid to RY/BY Delay Max. 90 90 90 ns — tEOE Delay Time from Embedded Output Enable Max. 70 90 120 ns — tFLQZ BYTE Switching Low to Output HIGH-Z Max. 30 35 50 ns — tFHQV BYTE Switching High to Output Active Min. 30 35 50 ns — tTOW Erase Time-out Time Min. 50 50 50 µs — tSPD Erase Suspend Transition Time Max. 20 20 20 µs JEDEC Standard — tRP RESET Pulse Width — tRH — Notes: 1. This does not include the preprogramming time. 2. This timing is for Sector Protection operation. 32 MBM29LV160TE/BE-70/90/12 ■ ERASE AND PROGRAMMING PERFORMANCE Limits Parameter Min. Typ. Max. Sector Erase Time — 1 10 Byte Programming Time — 8 300 Unit Comments s Excludes programming time prior to erasure µs Excludes system-level overhead Excludes system-level overhead Word Programming Time — 16 360 Chip Programming Time — 16.8 50 s 100,000 — — cycle Erase/Program Cycle — ■ PIN CAPACITANCE Parameter Symbol Test Setup Typ. Max. Unit Input Capacitance CIN VIN = 0 6 7.5 pF Output Capacitance COUT VOUT = 0 8 10 pF Control Pin Capacitance CIN2 VIN = 0 7.5 9 pF Note: Test conditions TA = 25°C, f = 1.0 MHz 33 MBM29LV160TE/BE-70/90/12 ■ TIMING DIAGRAM • Key to Switching Waveforms WAVEFORM INPUTS OUTPUTS Must Be Steady Will Be Steady May Change from H to L Will Be Change from H to L May Change from L to H Will Be Change from L to H “H” or “L”; Any Change Permitted Changing, State Unknown Does Not Apply Center Line Is HighImpedance “Off” State tRC Addresses Addresses Stable tACC CE tOE tDF OE tOEH WE tCE Outputs HIGH-Z tOH Output Valid Figure 5.1 Read Operation Timing Diagram 34 HIGH-Z MBM29LV160TE/BE-70/90/12 t RC Addresses Addresses Stable tACC tRH RESET tOH Outputs High-Z Output Valid Figure 5.2 Hardware Reset/Read Operation Timing Diagram 35 MBM29LV160TE/BE-70/90/12 3rd Bus Cycle Data Polling 555H Addresses tWC PA tAS PA tRC tAH CE tCS tCH tCE OE tGHWL tWP tWPH tOE tWHWH1 WE tDS Data Notes: 1. 2. 3. 4. 5. 6. A0H tDF tDH PD DQ7 DOUT tOH DOUT PA is address of the memory location to be programmed. PD is data to be programmed at word address. DQ7 is the output of the complement of the data written to the device. DOUT is the output of the data written to the device. Figure indicates last two bus cycles out of four bus cycle sequence. These waveforms are for the ×16 mode. (The addresses differ from ×8 mode.) Figure 6 Alternate WE Controlled Program Operation Timing Diagram 36 MBM29LV160TE/BE-70/90/12 3rd Bus Cycle Data Polling PA 555H Addresses tWC tAS PA tAH WE tWS tWH OE tGHEL tCP tCPH tWHWH1 CE tDS Data Notes: 1. 2. 3. 4. 5. 6. A0H tDH PD DQ7 DOUT PA is address of the memory location to be programmed. PD is data to be programmed at word address. DQ7 is the output of the complement of the data written to the device. DOUT is the output of the data written to the device. Figure indicates last two bus cycles out of four bus cycle sequence. These waveforms are for the ×16 mode. (The addresses differ from ×8 mode.) Figure 7 Alternate CE Controlled Program Operation Timing Diagram 37 MBM29LV160TE/BE-70/90/12 Addresses 555H tWC 2AAH tAS 555H 555H 2AAH SA* tAH CE tCH tCS OE tGHWL tWP tWPH WE tDS AAH Data tDH 30H for Sector Erase 55H 80H AAH 55H 10H tVCS VCC * : 1. SA is the sector address for Sector Erase. Addresses = 555H (Word), AAAH (Byte) for Chip Erase. 2. These waveforms are for the ×16 mode. (The addresses differ from ×8 mode.) Figure 8 Chip/Sector Erase Operation Timing Diagram 38 MBM29LV160TE/BE-70/90/12 CE tCH tOE tDF OE tOEH WE tCE * DQ7 Data DQ7 = Valid Data DQ7 High-Z tWHWH1 or 2 DQ0 to DQ6 Data DQ0 to DQ6 = Output Flag tBUSY DQ0 to DQ6 Valid Data High-Z tEOE RY/BY * : DQ7 = Valid Data (The device has completed the Embedded operation). Figure 9 Data Polling during Embedded Algorithm Operation Timing Diagram 39 MBM29LV160TE/BE-70/90/12 CE tOEH WE tOES OE * tOH DQ6 DQ6 = Toggle Data (DQ0 to DQ7) DQ6 = Toggle DQ6 = Stop Toggling DQ0 to DQ7 Data Valid tOE * : DQ6 = Stops toggling. (The device has completed the Embedded operation.) Figure 10 Taggle Bit I during Embedded Algorithm Operation Timing Diagram Enter Embedded Erasing WE Erase Suspend Erase Enter Erase Suspend Program Erase Suspend Read Erase Suspend Program DQ6 DQ2 Toggle DQ2 and DQ6 With OE Note: DQ2 is read from the erase-suspended sector. Figure 11 DQ2 vs. DQ6 40 Erase Rasume Erase Suspend Read Erase Erase Complate MBM29LV160TE/BE-70/90/12 CE The rising edge of the last WE signal WE Entlre programming or erase operations RY/BY tBUSY Figure 12 RY/BY Timing Diagram during Program/Erase Operation Timing Diagram WE RESET tRB tRP RY/BY tREADY Figure 13 RESET, RY/BY Timing Diagram 41 MBM29LV160TE/BE-70/90/12 CE tCE BYTE Data Output (DQ0 to DQ14) Data Output (DQ0 to DQ7) DQ0 to DQ14 tELFH tFHQV A -1 DQ15 DQ15/A -1 Figure 14 Timing Diagram for Word Mode Configuration CE BYTE tELFL Data Output (DQ0 to DQ14) Data Output (DQ0 to DQ7) DQ0 to DQ14 tACC A -1 DQ15 DQ15/A -1 tFLQZ Figure 15 Timing Diagram for Byte Mode Configuration The falling edge of the last write signal CE or WE Input Valid BYTE tSET (tAS) tHOLD (tAH) Figure 16 BYTE Timing Diagram for Write Operations 42 MBM29LV160TE/BE-70/90/12 A19, A18, A17 A16, A15, A14 A13, A12 SAX SAY A0 A1 A6 VID 3V A9 tVLHT VID 3V OE tVLHT tVLHT t VLHT tWPP WE tOESP tCSP CE Data 01H tVCS tOE VCC SAX : Sector Address for initial sector SAY : Sector Address for next sector Note: A-1 is VIL on byte mode. Figure 17 Sector Protection Timing Diagram 43 MBM29LV160TE/BE-70/90/12 VCC tVIDR tVCS tVLHT VID 3V 3V RESET CE WE tVLHT Program or Erase Command Sequence RY/BY Unprotection period Figure 18 Temporary Sector Unprotection Timing Diagram 44 tVLHT MBM29LV160TE/BE-70/90/12 VCC tVCS tVLHT RESET tVIDR tWC Add tWC SPAX SPAX SPAY A0 A1 A6 CE OE TIME-OUT tWP WE Data 60H 60H 40H 01H 60H tOE SPAX : Sector Address to be protected SPAY : Next Sector Address to be protected TIME-OUT : Time-Out window = 250 µs (min) Figure 19 Extended Sector Protection Timing Diagram 45 MBM29LV160TE/BE-70/90/12 ■ FLOW CHART EMBEDDED ALGORITHM Start Write Program Command Sequence (See Below) Data Polling Davice Verify Byte ? No Yes Increment Address No Last Address ? Yes Programming Completed Program Command Sequence* (Address/Command) : 555H/AAH 2AAH/55H 555H/A0H Program Address/Program Data * : The sequence is applied for ×16 mode. The addresses differ from ×8 mode. Figure 20 Embedded ProgramTM Algorithm 46 MBM29LV160TE/BE-70/90/12 EMBEDDED ALGORITHM Start Write Erase Command Sequence (See Below) Data Polling or Toggle Bit from Device No Data = FFH ? Yes Erasure Completed Chip Erase Command Sequence* (Address/Command) : Individual Sector/Multlple Sector* Erase Command Sequence (Address/Command) : 555H/AAH 555H/AAH 2AAH/55H 2AAH/55H 555H/80H 555H/80H 555H/AAH 555H/AAH 2AAH/55H 2AAH/55H 555H/10H Sector Address /30H Sector Address /30H Sector Address /30H Additional sector erase commands are optional. * : The sequence is applied for ×16 mode. The addresses differ from ×8 mode. Figure 21 Embedded EraseTM Algorithm 47 MBM29LV160TE/BE-70/90/12 Start Read Byte (DQ0 to DQ7) Addr. = VA DQ7 = Data ? Yes VA =Address for programming =Any of the sector addresses within the sector being erased during sector erase or multiple erases operation. =Any of the sector addresses within the sector not being protected during sector erase or multiple sector erases operation. No No DQ5 = 1 ? Yes Read Byte (DQ0 to DQ7) Addr. = VA DQ7 = Data ? * Yes No Fail Pass * : DQ7 is rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5. Figure 22 Data Polling Algorithm 48 MBM29LV160TE/BE-70/90/12 Start Read (DQ0 to DQ7) Addr. = “H” or “L” DQ6 = Toggle ? No Yes No DQ5 = 1 ? Yes Read Byte (DQ0 to DQ7) Addr. = “H” or “L” DQ6 = Toggle ?* No Yes Fail Pass * : DQ6 is rechecked even if DQ5 = “1” because DQ6 may stop toggling at the same time as DQ5 changing to “1”. Figure 23 Toggle Bit Algorithm 49 MBM29LV160TE/BE-70/90/12 Start Setup Sector Addr, (A19, A18, A17, A16, A15, A14, A13, A12) PLSCNT = 1 OE = VID, A9 = VID A6 = CE = VIL, RESET = VIH A0 = VIL, A1 = VIH Increment PLSCNT Activate WE Pulse Time out 100 µs WE = VIH, CE = OE = VIL (A9 should remain VID) Read from Sector (A1 = VIH, A0 = VIL Addr. = SA, A6 = VIL) * No PLSCNT = 25 ? Yes Pemove VID from A9 Write Reset Command No Data = 01H ? Yes Protect Another Sector ? No Device Failed Remove VID from A9 Write Reset Command Sector Protection Completed * : A-1 is VIL on byte mode. Figure 24 Sector Protection Algorithm 50 Yes MBM29LV160TE/BE-70/90/12 Start RESET = VID (Note 1) Perform Erase or Program Operations RESET = VIH Temporary Sector Unprotection Completed (Note 2) Notes: 1. All protected sectors are unprotected. 2. All previously protected sectors are protected once again. Figure 25 Temporary Sector Unprotection Algorithm 51 MBM29LV160TE/BE-70/90/12 FAST MODE ALGORITHM Start 555H/AAH 2AAH/55H Set Fast Mode* 555H/20H XXXXH/A0H Program Address/Program Data Data Polling Device Verify Byte ? No in Fast Program Yes Increment Address No Last Address ? Yes Programming Completed XXXXH/90H Reset Fast Mode XXXXH/F0H * : The sequence is applied for ×16 mode. * : The addresses differ from ×8 mode. Figure 26 Embedded Programming Algorithm for Fast Mode 52 MBM29LV160TE/BE-70/90/12 Start RESET = VID Wait to 4 µs Device Is Operating in Temporary Sector Unprotect Mode No Extended Sector Protect Entry ? Yes To Setup Sector Protect Write XXXH/60H PLSCNT = 1 To Sector Protect Write 60H to Sector Address (A0 = V1L, A1 = VIH, A6 = VIL) Time Out 250 µs To Verify Sector Protect Write 40H to Sector Address (A0 = V1L, A1 = VIH, A6 = VIL) Increment PLSCNT Read from Sector Protect (A0 = V1L, A1 = VIH, A6 = VIL) No Setup Next Sector Address PLSCNT = 25 ? Yes Remove VID from RESET Write Reset Command No Data = 01H ? Yes Protect Other Sector ? Yes No Device Failed Remove VID from RESET Write Reset Command Sector Protection Completed Figure 27 Extended Sector Protection Algorithm 53 MBM29LV160TE/BE-70/90/12 ■ ORDERING INFORMATION Standard Products Fujitsu standard products are available in several packages. The order number is formed by a combination of: MBM29LV160 T E 70 TN PACKAGE TYPE TN = 48-Pin Thin Small Outline Package (TSOP) Standard Pinout TR = 48-Pin Thin Small Outline Package (TSOP) Reverse Pinout PCV = 48-Pin C- leaded Small Outline Package (CSOP) PBT = 48-Pin Fine Pitch Ball Grid Array Package (FBGA) SPEED OPTION See Product Selector Guide DEVICE REVISION BOOT CODE SECTOR ARCHITECTURE T = Top sector B = Bottom sector DEVICE NUMBER/DESCRIPTION MBM29LV160 16 Mega-bit (2M × 8-Bit or 1M × 16-Bit) CMOS Flash Memory 3.0 V-only Read, Write, and Erase Valid Combinations Valid Combinations MBM29LV160TE/BE 54 70 90 12 TN TR PCV PBT Valid Combinations list configurations planned to be supported in volume for this device. Consult the local Fujitsu sales office to confirm availability of specific valid combinations and to check on newly released combinations. MBM29LV160TE/BE-70/90/12 ■ PACKAGE DIMENSIONS 48-pin plastic TSOP (I) (FPT-48P-M19) *: Resin protruction. (Each side: 0.15(.006) Max) LEAD No. 1 48 Details of "A" part INDEX 0.15(.006) MAX 0.35(.014) MAX "A" 0.15(.006) 24 25 * 12.00±0.20 20.00±0.20 (.787±.008) * 18.40±0.20 (.724±.008) 0.10(.004) (.472±.008) 11.50REF (.460) 19.00±0.20 (.748±.008) 1996 FUJITSU LIMITED F48029S-2C-2 +0.10 1.10 –0.05 +.004 .043 –.002 (Mounting height 0.50(.0197) TYP 0.15±0.05 (.006±.002) C 0.25(.010) 0.05(0.02)MIN (STAND OFF) 0.20±0.10 (.008±.004) 0.10(.004) M 0.50±0.10 (.020±.004) Dimensions in mm (inches) (Continued) 55 MBM29LV160TE/BE-70/90/12 48-pin plastic TSOP (I) (FPT-48P-M20) *: Resin protrusion. (Each side: 0.15(.006) Max) LEAD No. 1 48 Details of "A" part INDEX 0.15(.006) MAX 0.35(.014) MAX "A" 0.15(.006) 24 0.25(.010) 25 19.00±0.20 (.748±.008) 0.50±0.10 (.020±.004) 0.15±0.10 (.006±.002) 0.10(.004) 0.20±0.10 (.008±.004) 0.50(.0197) TYP 0.10(.004) M 0.05(0.02)MIN (STAND OFF) +0.10 1.10 –0.05 * 18.40±0.20 (.724±.008) 20.00±0.20 (.787±.008) C 1996 FUJITSU LIMITED F48030S-2C-2 11.50(.460)REF +.004 .043 –.002 (Mounting height) * 12.00±0.20(.472±.008) Dimensions in mm (inches) (Continued) 56 MBM29LV160TE/BE-70/90/12 48-pin plastic CSOP (LCC-48P-M03) 48 "A" 25 10.00±0.20 (.394±.008) 9.50±0.10 (.374±.004) INDEX INDEX 0.05 +0.05 –0 +.002 –.0 .002 (Stand off) LEAD No. 1 24 10.00±0.10(.394±.004) 0.95±0.05(.037±.002) (Mounting height) 0.22±0.035 (.009±.001) Details of "A" part 0°~10° 0.40(.016) TYP 0.08(.003) 0.65(.026) 1.15(.045) 9.20(.362)REF C 1998 FUJITSU LIMITED C48056S-1C-1 Dimensions in mm (inches) (Continued) 57 MBM29LV160TE/BE-70/90/12 (Continued) 48-pin plastic FBGA (BGA-48P-M11) Note: The actual shape of corners may differ from the dimension. +0.15 8.00±0.20(.315±.008) +.006 1.05 –0.10 .041 –.004 (Mounting height) 0.38±0.10(.015±.004) (Stand off) 5.60(.221) 0.80(.031)TYP 6 5 INDEX 6.00±0.20 (.236±.008) 4 4.00(.157) 3 2 1 H C0.25(.010) G F E D 48-Ø0.45±0.10 (48-.018±.004) C B A Ø0.08(.003) M 0.10(.004) C 58 1998 FUJITSU LIMITED B480011S-1C-1 Dimensions in mm (inches) MBM29LV160TE/BE-70/90/12 FUJITSU LIMITED For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa 211-8588, Japan Tel: +81-44-754-3763 Fax: +81-44-754-3329 http://www.fujitsu.co.jp/ North and South America FUJITSU MICROELECTRONICS, INC. 3545 North First Street, San Jose, CA 95134-1804, USA Tel: +1-408-922-9000 Fax: +1-408-922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: +1-800-866-8608 Fax: +1-408-922-9179 http://www.fujitsumicro.com/ Europe FUJITSU MICROELECTRONICS EUROPE GmbH Am Siebenstein 6-10, D-63303 Dreieich-Buchschlag, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://www.fujitsu-fme.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LTD #05-08, 151 Lorong Chuan, New Tech Park, Singapore 556741 Tel: +65-281-0770 Fax: +65-281-0220 http://www.fmap.com.sg/ F0001 FUJITSU LIMITED Printed in Japan All Rights Reserved. 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