FUJITSU SEMICONDUCTOR DATA SHEET DS05-20890-1E PAGE MODE FLASH MEMORY CMOS 32 M (2 M × 16/1 M × 32) BIT MBM29PL3200TE/BE 70/90 ■ DESCRIPTION The MBM29PL3200TE/BE is 32 M-bit, 3.0 V-only Page mode Flash memory organized as 2 M words of 16 bits each or 1 M words of 32 bits each. The device is offered in 90-pin SSOP and 84-ball FBGA packages. This device is designed to be programmed in-system with the standard system 3.0 V VCC supply. 12.0 V VPP and 5.0 V VCC are not required for write or erase operations. The device can also be reprogrammed in standard EPROM programmers. (Continued) ■ PRODUCT LINE-UP Part No. MBM29PL3200TE/BE VCC = 3.3 V +0.3 V −0.3 V 70 VCC = 3.0 V +0.6 V −0.3 V 90 Max. Random Address Access Time (ns) 70 90 Max. Page Address Access Time (ns) 25 35 Max. CE Access Time (ns) 70 90 Max. OE Access Time (ns) 25 35 Ordering Part No. ■ PACKAGES 90-pin plastic SSOP 84-ball plastic FBGA (FPT-90P-M01) (BGA-84P-M01) MBM29PL3200TE/BE70/90 (Continued) The device provides truly high performance non-volatile Flash memory solution. The device offers fast page access times of 25 ns and 35 ns with random access times of 70 ns and 90 ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention, the device has separate chip enable (CE), write enable (WE) and output enable (OE) controls. The page size is 8 words or 4 double words. The device is command set compatible with JEDEC standard E2PROMs. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal statemachine which controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from 5.0 V and 12.0 V Flash or EPROM devices. The device is programmed by executing the program command sequence. This will invoke the Embedded ProgramTM * Algorithm, which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margins. Typically, each sector can be programmed and verified in about 2.2 seconds. Erase is accomplished by executing the erase command sequence. This will invoke the Embedded EraseTM * Algorithm, which is an internal algorithm that automatically preprograms the array if it is not already programmed before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margins. Any individual sector is typically erased and verified in 4.8 second. (If already preprogrammed.) The device also features a sector erase architecture. The sector mode allows each sector to be erased and reprogrammed without affecting other sectors. The device is erased when shipped from the factory. The device features single 3.0 V power supply operation for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. A low VCC detector automatically inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ7, by the Toggle Bit feature on DQ6, output pin. Once the end of a program or erase cycle has been completed, the device internally resets to the read mode. Fujitsu’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability, and cost effectiveness. The device memory electrically erases all bits within a sector simultaneously via Fowler-Nordhiem tunneling. The words/double words are programmed one word/double word at a time using the EPROM programming mechanism of hot electron injection. *: Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc. ■ FEATURES • 0.23 µm Process Technology • Single 3.0 V read, program and erase Minimized system level power requirements • High Performance Page Mode 25 ns maximum page access time (70 ns random access time) • 8 words Page ( × 16) /4 double words ( × 32) size • Compatible with JEDEC-standard commands Uses same software commands as E2PROMs • Compatible with JEDEC-standard world-wide pinouts 90-pin SSOP (Package suffix : PFV) 84-ball FBGA (Package suffix : PBT) • Minimum 100,000 program/erase cycles • Sector erase architecture One 16 K word, two 8 K words, one 96 K word, and fifteen 128 K words sectors in word mode ( × 16) One 8 K double word, two 4 K double words, one 48 K double word, and fifteen 64 K double words sectors in double word mode ( × 32) Any combination of sectors can be concurrently erased. Also supports full chip erase 2 MBM29PL3200TE/BE70/90 • Boot Code Sector Architecture T = Top sector B = Bottom sector • Embedded EraseTM Algorithms Automatically pre-programs and erases the chip or any sector • Embedded ProgramTM Algorithms Automatically programs and verifies data at specified address • Data Polling and Toggle Bit feature for detection of program or erase cycle completion • Automatic sleep mode When addresses remain stable, automatically switches themselves to low power mode • Low VCC write inhibit ≤ 2.5 V • Erase Suspend/Resume Suspends the erase operation to allow a read data and/or program in another sector within the same device • Sector protection Hardware method disables any combination of sectors from program or erase operations • Fast Programming Function by Extended command • Temporary sector unprotection Temporary sector unprotection with the software command • In accordance with CFI (Common Flash Memory Interface) 3 MBM29PL3200TE/BE70/90 ■ PIN ASSIGNMENTS SSOP (TOP VIEW) N.C. N.C. N.C. N.C. N.C. A0 A1 A2 A3 A4 A5 VCC DQ0 DQ16 DQ1 DQ17 VSS VCC DQ2 DQ18 DQ3 DQ19 DQ4 DQ20 DQ5 DQ21 VSS VCC DQ6 DQ22 DQ7 DQ23 VSS A6 A7 A8 A9 A10 A11 A12 N.C. N.C. N.C. N.C. N.C. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 N.C. N.C. ACC WP WE N.C. N.C. N.C. DW/W OE CE VSS DQ31/A-1 DQ15 DQ30 DQ14 VSS VCC DQ29 DQ13 DQ28 DQ12 DQ27 DQ11 DQ26 DQ10 VSS VCC DQ25 DQ9 DQ24 DQ8 VCC A19 A18 A17 A16 A15 A14 A13 N.C. N.C. N.C. N.C. N.C. FPT-90P-M01 (Continued) 4 MBM29PL3200TE/BE70/90 (Continued) FBGA (TOP VIEW) Marking Side B9 C9 D9 E9 F9 G9 H9 J9 DQ30 VCC DQ13 DQ12 DQ27 DQ26 VCC DQ9 A8 B8 C8 D8 E8 F8 G8 H8 J8 K8 CE VSS DQ15 DQ29 DQ28 DQ11 VSS DQ24 VCC A19 A7 B7 C7 D7 E7 F7 G7 H7 J7 K7 N.C. DW/W OE DQ14 VSS DQ10 DQ25 A18 A17 A16 C6 D6 E6 A6 B6 WE N.C. N.C. DQ31/A-1 N.C. F6 G6 H6 J6 K6 N.C. DQ8 A15 A14 A13 A5 B5 C5 D5 E5 F5 G5 H5 J5 K5 N.C. ACC WP N.C. N.C. N.C. N.C. N.C. N.C. N.C. A4 B4 C4 D4 E4 F4 G4 H4 J4 K4 A1 A2 A3 A0 DQ2 N.C. A12 A11 A9 A10 A3 B3 C3 D3 E3 F3 G3 H3 J3 K3 A4 A5 DQ0 DQ16 DQ18 DQ5 DQ21 A8 A6 A7 B2 C2 D2 E2 F2 G2 H2 J2 K2 VCC DQ1 VSS DQ19 DQ4 DQ6 DQ7 DQ23 VSS C1 D1 E1 F1 G1 H1 J1 DQ17 VCC DQ3 DQ20 VSS VCC DQ22 BGA-84P-M01 5 MBM29PL3200TE/BE70/90 ■ PIN DESCRIPTIONS Table 1 MBM29PL3200TE/BE Pin Configuration Function Pin Name A19 to A0, A-1 Address Input DQ31 to DQ0 Data Input/Output CE Chip Enable OE Output Enable WE Write Enable Selects 32-bit or 16-bit mode DW/W WP Hardware Write Protection ACC Program Acceleration N.C. Pin Not Connected Internally VSS Device Ground VCC Device Power Supply ■ BLOCK DIAGRAM DQ31 to DQ0 VCC VSS Erase Voltage Generator WE DW/W WP ACC Input/Output Buffers State Control Circuit (Command Register) Program Voltage Generator Chip Enable Output Enable Logic CE STB Data Latch OE STB Low VCC Detector A19 to A29 A1, A0 (A−1) 6 Timer for Program/Erase Y-Decoder Address X-Decoder Latch Y-Gating 33,554,432 Cell Matrix MBM29PL3200TE/BE70/90 ■ LOGIC SYMBOL A-1 20 A19 to A0 32 or 16 DQ31 to DQ0 CE OE WE DW/W 7 MBM29PL3200TE/BE70/90 ■ DEVICE BUS OPERATION Table 2 MBM29PL3200TE/BE User Bus Operations (DW/W = VIH) Operation OE WE CE Auto-Select Manufacturer Code *1 A0 A1 A2 A3 A6 A9 DQ31 to DQ0 WP L L H L L L L L VID Code X L L H H L L L L VID Code X L L H H H H H L VID Code X L L H A0 A1 A2 A3 A6 A9 DOUT X Standby H X X X X X X X X HIGH-Z X Output Disable L H H X X X X X X HIGH-Z X L H L A0 A1 A2 A3 A6 A9 DIN X L VID L H L L L VID X X Verify Sector Protection *2, *4 L L H L H L L L VID Code X Boot Block Sector Write Protection *5 X X X X X X X X X X L Auto-Select Device Code *1 Extended Auto-Select Device Code * Read * 1 3 Write (Program/Erase) 2, Enable Sector Protection * * 4 Legend : L = VIL, H = VIH, X = VIL or VIH, = Pulse input. See DC Characteristics for voltage levels. *1: Manufacturer and device codes may also be accessed via a command register write sequence. See Table 4. *2: Refer to section on Sector Protection. *3: WE can be VIL if OE is VIL, OE at VIH initiates the write operations. *4: VCC = 3.3 V ± 10% *5: Protect “outermost” 16 K words (8 K double words) of the boot block sectors. Table 3 MBM29PL3200TE/BE User Bus Operations (DW/W = VIL) Operation CE OE WE DQ31/A-1 A0 A1 A2 A3 A6 A9 DQ15 to DQ0 WP Auto-Select Manufacturer Code *1 L L H L L L L L L VID Code X Auto-Select Device Code *1 L L H L H L L L L VID Code X Extended Auto-Select Device Code *1 L L H L H H H H L VID Code X L L H A-1 A0 A1 A2 A3 A6 A9 DOUT X Standby H X X X X X X X X X HIGH-Z X Output Disable L H H X X X X X X X HIGH-Z X L H L A-1 A0 A1 A2 A3 A6 A9 DIN X L VID L L H L L L VID X X Verify Sector Protection * * L L H L L H L L L VID Code X Boot Block Sector Write Protection *5 X X X X X X X X X X X L Read * 3 Write (Program/Erase) 2, Enable Sector Protection * * 2, 4 4 Legend : L = VIL, H = VIH, X = VIL or VIH, = Pulse input. See DC Characteristics for voltage levels. *1: Manufacturer and device codes may also be accessed via a command register write sequence. See Table 4. *2: Refer to section on Sector Protection. *3: WE can be VIL if OE is VIL, OE at VIH initiates the write operations. *4: VCC = 3.3 V ± 10% *5: Protect “outermost” 16 K words (8 K double words) of the boot block sectors. 8 MBM29PL3200TE/BE70/90 Table 4 MBM29PL3200TE/BE Command Definitions Fourth Bus Bus Fifth Bus Sixth Bus First Bus Second Bus Third Bus Write Write Cycle Write Cycle Write Cycle Read/Write Write Cycle Write Cycle Cycle Cycles Req’d Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Command Sequence Read/Reset Read/Reset Autoselect Program Chip Erase Sector Erase DW W DW W DW W DW W DW W DW W 1 3 3 4 6 6 XXXh F0h 555h AAAh 555h AAAh 555h AAAh 555h AAAh 555h AAAh AAh AAh AAh AAh AAh 2AAh 555h 2AAh 555h 2AAh 555h 2AAh 555h 2AAh 555h 55h 55h 55h 55h 55h 555h AAAh 555h AAAh 555h AAAh 555h AAAh 555h AAAh F0h RA RD 90h A0h PA PD 80h 80h 555h AAAh 555h AAAh AAh AAh 2AAh 555h 2AAh 555h 55h 555h AAAh 10h 55h SA 30h Erase Suspend 1 XXXh B0h Erase Resume 1 XXXh 30h 20h Set to Fast Mode DW Fast Program *1 DW W W 3 2 DW Reset from 1 Fast Mode * W 2 Temporary DW Unprotection W Enable 4 Temporary DW Unprotection W Disable 4 Query *2 DW W Hi-ROM Entry DW Hi-ROM Program *3 DW Hi-ROM Exit *3 DW W W W 555h AAAh XXXh XXXh XXXh XXXh AAh A0h 90h 555h AAAh 1 3 4 4 55h AAh 555h AAAh 555h AAAh 555h AAAh 555h 55h 98h AAh AAh AAh AAAh *4 XXXh F0h E0h XXXh 01h E0h XXXh 00h XXXh 555h 555h 55h 2AAh AAh 555h PD PA 2AAh AAh 555h AAAh 2AAh 555h 2AAh 555h 2AAh 555h 2AAh 555h AAAh 555h 55h 55h 55h 55h AAAh 555h AAAh 555h AAAh 555h AAAh 88h A0h (HRA) PA PD 90h XXXh 00h (Continued) 9 MBM29PL3200TE/BE70/90 (Continued) DW : Double Word W : Word *1: This command is valid while Fast Mode. *2: The valid addresses are A6 to A0. *3: This command is valid while Hi-ROM mode. *4: The data “00h” is also acceptable. Notes : 1.Address bits A19 to A11 = X = “H” or “L” for all address commands except or Program Address (PA), and Sector Address (SA). 2.Bus operations are defined in Tables 2 and 3. 3.RA = Address of the memory location to be read PA = Address of the memory location to be programmed Addresses are latched on the falling edge of the write pulse. SA = Address of the sector to be erased. The combination of A19, A18, A17, A16, A15, A14, A13 and A12 will uniquely select any sector. 4.RD = Data read from location RA during read operation. PD = Data to be programmed at location PA. Data is latched on the falling edge of write pulse. 5.HRA = Address of the Hi-ROM area Word Mode : 000000h to 000100h Double Word Mode : 000000h to 000080h 6.The system should generate the following address patterns : DW (Double Word) Mode : 555h or 2AAh to addresses A10 to A0 W (Word) Mode : AAAh or 555h to addresses A10 to A0, and A-1 7.Both Read/Reset commands are functionally equivalent, resetting the device to the read mode. 10 MBM29PL3200TE/BE70/90 Type Table 5.1 MBM29PL3200TE Sector Protection Verify Autoselect Codes A6 A3 A2 A1 A0 A19 to A12 A-1 *1 Manufacture’s Code X VIL VIL VIL VIL VIL X VIL VIL VIL VIL VIH Word Device Code Double Word Word Code (HEX) VIL 04h VIL 227Eh X 2222227Eh VIL 2203h X 22222203h VIL 2201h X 22222201h X VIL VIH VIH VIH VIL X VIL VIH VIH VIH VIH Sector Protection Sector Addresses VIL VIL VIL VIH VIL VIL 01h *2 Temporary Sector Unprotection X VIL VIL VIL VIH VIH VIL 01h *3 Extended Device Code Double Word Word Double Word *1 : A-1 is for Word mode. In double word mode, DQ15 to DQ30 become “High-Z” and DQ31 becomes the lower address “A-1”. *2 : Outputs 01h at protected sector addresses and outputs 00h at unprotected sector addresses. *3 : Outputs 01h at Temporary Sector Unprotection and outputs 00h at Non Temporary Sector Unprotection. 11 MBM29PL3200TE/BE70/90 Table 5.2 Expanded Autoselect Code Code DQ31 DQ30 DQ29 DQ28 DQ27 DQ26 DQ25 DQ24 DQ23 DQ22 DQ21 DQ20 DQ19 DQ18 DQ17 DQ16 Type Manufacturer’s Code Device Code (W) (DW) (W) 04h A-1/0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 227Eh A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z 2222 227Eh 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 2203h A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z 2222 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 Extended (DW) 2203h 0 Device (W) 2201h A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z Code (DW) 2222 2201h 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 Sector Protection 01h A-1/0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Temporary Sector Unprotection 01h A-1/0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Type DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 Manufacturer’s Code 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 (W) 0 0 1 0 0 0 1 0 0 1 1 1 1 1 1 0 (DW) 0 0 1 0 0 0 1 0 0 1 1 1 1 1 1 0 (W) 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 1 (DW) 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 1 (W) 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 1 (DW) 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 1 Sector Protection 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Temporary Sector Unprotection 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Device Code Extended Device Code (W) : Word mode (DW) : Double Word mode 12 0 MBM29PL3200TE/BE70/90 Type Table 5.3 MBM29PL3200BE Sector Protection Verify Autoselect Codes A6 A3 A2 A1 A0 A19 to A12 A-1 *1 Manufacture’s Code X VIL VIL VIL VIL VIL X VIL VIL VIL VIL VIH Word Device Code Double Word Word Code (HEX) VIL 04h VIL 227Eh X 2222227Eh VIL 2203h X 22222203h VIL 2200h X 22222200h X VIL VIH VIH VIH VIL X VIL VIH VIH VIH VIH Sector Protection Sector Addresses VIL VIL VIL VIH VIL VIL 01h *2 Temporary Sector Unprotection X VIL VIL VIL VIH VIH VIL 01h *3 Extended Device Code Double Word Word Double Word *1 : A-1 is for Word mode. In double word mode, DQ15 to DQ30 become “High-Z” and DQ31 becomes the lower address “A-1”. *2 : Outputs 01h at protected sector addresses and outputs 00h at unprotected sector addresses. *3 : Outputs 01h at Temporary Sector Unprotection and outputs 00h at Non Temporary Sector Unprotection. 13 MBM29PL3200TE/BE70/90 Table 5.4 Expanded Autoselect Code Code DQ31 DQ30 DQ29 DQ28 DQ27 DQ26 DQ25 DQ24 DQ23 DQ22 DQ21 DQ20 DQ19 DQ18 DQ17 DQ16 Type Manufacturer’s Code Device Code (W) 04h A-1/0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 227Eh A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z (DW) 2222 227Eh (W) 2203h 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z 2222 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 Extended (DW) 2203h 0 Device (W) 2200h A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z Code 2222 2200h 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 Sector Protection 01h A-1/0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Temporary Sector Unprotection 01h A-1/0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DW) Type DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 Manufacturer’s Code 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 (W) 0 0 1 0 0 0 1 0 0 1 1 1 1 1 1 0 (DW) 0 0 1 0 0 0 1 0 0 1 1 1 1 1 1 0 (W) 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 1 (DW) 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 1 (W) 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 (DW) 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 Sector Protection 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Temporary Sector Unprotection 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Device Code Extended Device Code (W) : Word mode (DW) : Double Word mode 14 MBM29PL3200TE/BE70/90 Sector Table 7 Sector Address (MBM29PL3200TE) Sector Address Sector Size (Kwords/ ( × 16) Address Range ( × 32) Address Range A17 A16 A15 A14 A13 A12 Double kwords) A19 A18 SA0 0 0 0 0 X X X X 128/64 000000h to 01FFFFh 00000h to 0FFFFh SA1 0 0 0 1 X X X X 128/64 020000h to 03FFFFh 10000h to 1FFFFh SA2 0 0 1 0 X X X X 128/64 040000h to 05FFFFh 20000h to 2FFFFh SA3 0 0 1 1 X X X X 128/64 060000h to 07FFFFh 30000h to 3FFFFh SA4 0 1 0 0 X X X X 128/64 080000h to 09FFFFh 40000h to 4FFFFh SA5 0 1 0 1 X X X X 128/64 0A0000h to 0BFFFFh 50000h to 5FFFFh SA6 0 1 1 0 X X X X 128/64 0C0000h to 0DFFFFh 60000h to 6FFFFh SA7 0 1 1 1 X X X X 128/64 0E0000h to 0FFFFFh 70000h to 7FFFFh SA8 1 0 0 0 X X X X 128/64 100000h to 11FFFFh 80000h to 8FFFFh SA9 1 0 0 1 X X X X 128/64 120000h to 13FFFFh 90000h to 9FFFFh SA10 1 0 1 0 X X X X 128/64 140000h to 15FFFFh A0000h to AFFFFh SA11 1 0 1 1 X X X X 128/64 160000h to 17FFFFh B0000h to BFFFFh SA12 1 1 0 0 X X X X 128/64 180000h to 19FFFFh C0000h to CFFFFh SA13 1 1 0 1 X X X X 128/64 1A0000h to 1BFFFFh D0000h to DFFFFh SA14 1 1 1 0 X X X X 128/64 1C0000h to 1DFFFFh E0000h to EFFFFh SA15 1 1 1 1 96/48 1E0000h to 1F7FFFh F0000h to FBFFFh SA16 1 1 1 1 1 1 0 0 8/4 1F8000h to 1F9FFFh FC000h to FEFFFh SA17 1 1 1 1 1 1 0 1 8/4 1FA000h to 1FBFFFh FD000h to FDFFFh SA18 1 1 1 1 1 1 1 X 16/8 1FC000h to 1FFFFFh FE000h to FFFFFh 0000 to 1011 Note : The address range is A19 to A-1 if in word mode (DW/W = VIL). The address range is A19 to A0 if in double word mode (DW/W = VIH). 15 MBM29PL3200TE/BE70/90 Sector A19 A18 Table 8 Sector Address (MBM29PL3200BE) Sector Address Sector Size (Kwords/ ( × 16) Address Range ( × 32) Address Range A17 A16 A15 A14 A13 A12 Double kwords) SA0 0 0 0 0 0 0 0 X 16/8 000000h to 003FFFh 00000h to 01FFFh SA1 0 0 0 0 0 0 1 0 8/4 004000h to 005FFFh 02000h to 02FFFh SA2 0 0 0 0 0 0 1 1 8/4 006000h to 007FFFh 03000h to 03FFFh SA3 0 0 0 0 96/48 008000h to 01FFFFh 04000h to 0FFFFh SA4 0 0 0 1 X X X X 128/64 020000h to 03FFFFh 10000h to 1FFFFh SA5 0 0 1 0 X X X X 128/64 040000h to 05FFFFh 20000h to 2FFFFh SA6 0 0 1 1 X X X X 128/64 060000h to 07FFFFh 30000h to 3FFFFh SA7 0 1 0 0 X X X X 128/64 080000h to 09FFFFh 40000h to 4FFFFh SA8 0 1 0 1 X X X X 128/64 0A0000h to 0BFFFFh 50000h to 5FFFFh SA9 0 1 1 0 X X X X 128/64 0C0000h to 0DFFFFh 60000h to 6FFFFh SA10 0 1 1 1 X X X X 128/64 0E0000h to 0FFFFFh 70000h to 7FFFFh SA11 1 0 0 0 X X X X 128/64 100000h to 11FFFFh 80000h to 8FFFFh SA12 1 0 0 1 X X X X 128/64 120000h to 13FFFFh 90000h to 9FFFFh SA13 1 0 1 0 X X X X 128/64 140000h to 15FFFFh A0000h to AFFFFh SA14 1 0 1 1 X X X X 128/64 160000h to 17FFFFh B0000h to BFFFFh SA15 1 1 0 0 X X X X 128/64 180000h to 19FFFFh C0000h to CFFFFh SA16 1 1 0 1 X X X X 128/64 1A0000h to 1BFFFFh D0000h to DFFFFh SA17 1 1 1 0 X X X X 128/64 1C0000h to 1DFFFFh E0000h to EFFFFh SA18 1 1 1 1 X X X X 128/64 1E0000h to 1FFFFFh F0000h to FFFFFh 0100 to 1111 Note : The address range is A19 to A-1 if in word mode (DW/W = VIL). The address range is A19 to A0 if in double word mode (DW/W = VIH). 16 MBM29PL3200TE/BE70/90 Table 9 Common Flash Memory Interface Code A6 to A0 DQ15 to DQ0 Description 10h 11h 12h 0051h 0052h 0059h Query-unique ASCII string “QRY” 13h 14h 0002h 0000h Primary OEM Command Set 2h : AMD/FJ standard type 15h 16h 0040h 0000h Address for Primary Extended Table 17h 18h 0000h 0000h Alternate OEM Command Set (00h = not applicable) 19h 1Ah 0000h 0000h Address for Alternate OEM Extended Table 1Bh 0027h VCC Min. (write/erase) D7-4 : 1 V, D3-0 : 100 mV 1Ch 0036h VCC Max. (write/erase) D7-4 : 1 V, D3-0 : 100 mV 1Dh 0000h 1Eh 1Fh A6 to A0 DQ15 to DQ0 Description 2Dh 2Eh 2Fh 30h 0000h 0000h 0080h 0000h Erase Block Region 1 Information 31h 32h 33h 34h 0001h 0000h 0040h 0000h Erase Block Region 2 Information 35h 36h 37h 38h 0000h 0000h 0000h 0003h Erase Block Region 3 Information 0050h 0052h 0049h Query-unique ASCII string “PRI” VPP Min. voltage 40h 41h 42h 0000h VPP Max. voltage 43h 0031h Major version number, ASCII Typical timeout per single byte/word write (2N µs) 44h 0033h Minor version number, ASCII 0004h 45h 0000h Address Sensitive Unlock 0h = Required 1h = Not Required 0002h Erase Suspend 0h = Not Supported 1h = To Read Only 2h = To Read & Write 0001h Sector Protection 0h = Not Supported X = Number of sectors per group Bit0 to 15: y = Number of sectors Bit16 to 31: z = Size (Z × 256 Byte) Bit0 to 15: y = Number of sectors Bit16 to 31: z = Size (Z × 256 Byte) Bit0 to 15: y = Number of sectors Bit16 to 31: z = Size (Z × 256 Byte) 20h 0000h Typical timeout for Min. size buffer write (2N µs) 21h 000Ah Typical timeout per individual block erase (2N ms) 22h 0000h Typical timeout for full chip erase (2N ms) 23h 0005h Max. timeout for byte/word write (2N × typical time) 24h 0000h Max. timeout for buffer write (2N × typical time) 25h 0006h Max. timeout per individual block erase (2N × typical time) 48h 0001h 26h 0000h Max. timeout for full chip erase (2N × typical time) Sector Temporary Unprotection 00h = Not Supported 01h = Supported 49h 0003h Sector Protection Algorithm 27h 0016h Device Size = 2N byte 28h 29h 0005h 0000h Flash Device Interface description 4Ah 0000h 00h = Not Supported, X = Total number of sectors in all Banks except Bank 1 2Ah 2Bh 0000h 0000h Max. number of bytes in multi-byte write = 2N 4Bh 0000h Burst Mode Type 00h = Not Supported 0004h Number of Erase Block Regions within device 4Ch 0002h Page Mode Type 00h = Not Supported 2Ch 46h 47h (Continued) 17 MBM29PL3200TE/BE70/90 (Continued) A6 to A0 DQ15 to DQ0 Description 00B5h ACC (Acceleration) Supply Minimum 00h = Not Supported, D7-4 : 1 V, D3-0 : 100 mV 4Eh 00C5h ACC (Acceleration) Supply Maximum 00h = Not Supported, D7-4 : 1 V, D3-0 : 100 mV 4Fh 00XXh Boot Type 02h = MBM29PL3200BE 03h = MBM29PL3200TE 4Dh Note : DQ31 to DQ16 = “0000h” 18 MBM29PL3200TE/BE70/90 ■ FUNCTIONAL DESCRIPTION Read Mode The device has two control functions which must be satisfied in order to obtain data at the outputs. CE is the power control and should be used for device selection. OE is the output control and should be used to gate data to the output pins when a device is selected. Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable access time (tCE) is the delay from stable addresses and stable CE to valid data at the output pins. The output enable access time is the delay from the falling edge of OE to valid data at the output pins (assuming the addresses have been stable prior to tACC − tOE time). When reading out data without changing addresses after power-up, it is necessary to input hardware reset or to change CE pin from “H” to “L”. Page Mode Read The device is capable of fast Page mode read and is compatible with the Page mode Mask ROM read operation. This mode provides faster read access speed for random locations within a page. The Page size of the device is 8 words, or 4 double words, within the appropriate Page being selected by the higher address bits A19 to A2 and the LSB bits A1 to A0 (in double word mode) and A1 to A-1 (in word mode) determining the specific double word/word within that page. This is an asynchronous operation with the microprocessor supplying the specific double word or word location. The random or initial page access is equal to tACC and subsequent Page read access (as long as the locations specified by the microprocessor fall within that Page) is equivalent to tPACC. Here again, CE selects the device and OE is the output control and should be used to gate data to the output pins if the device is selected. Fast Page mode accesses are obtained by keeping A19 to A2 constant and changing A1 and A0 to select the specific double word, or changing A1 to A-1 to select the specific word within that page. See Figure 5.2 for timing specifications. Standby Mode The device has CMOS standby mode (CE input held at VCC ± 0.3 V.), when the current consumed is less than 50 µA. In the standby mode, the output pins are in a high impedance state, independent of OE input. During Embedded Algorithm operation, VCC Active current (ICC2) is required even if CE = “H”. The device can be read with standard access time (tCE) from either of these standby modes. In the standby mode, the output pins are in the high impedance state, independent of OE input. Automatic Sleep Mode Automatic sleep mode lower consumption during read-out of the device data. This mode can be useful for applications such as a handy terminal that requires low power consumption. To activate this mode, the device automatically switches itself to low power mode when addresses remain stable during access time of 150 ns. It is not necessary to control CE, WE and OE in this mode. In this mode, the current consumed is typically 50 µA (CMOS Level). Since the data are latched during this mode, they are read out continuously. If the addresses are changed, this mode is canceled automatically, and the device reads the data for changed addresses. Output Disable With the OE input is at a logic high level (VIH), output from the device is disabled. This will put the output pins in a high impedance state. Autoselect The autoselect mode allows the reading out of a binary code from the device and will identify its manufacturer and type. This mode is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. This mode is functional over the entire temperature range of the device. 19 MBM29PL3200TE/BE70/90 To activate this mode, the programming equipment must force VID on address pin A9. Three identifier words may then be sequenced from the device outputs by toggling address A0 and A1 from VIL to VIH. All addresses are DON’T CAREs except A6, A3, A2, A1, and A0 (A-1). (See Tables 2 and 3.) The manufacturer and device codes may also be read via the command register, for instance when the device is erased or programmed in a system without access to high voltage on the A9 pin. The command sequence is illustrated in Table 11. (Refer to Autoselect Command section.) A read cycle from address 00h returns the manufacturer’s code (Fujitsu = 04h). A read cycle from address 01h, 0Eh to 0Fh returns the device code. (See Tables 5.1 to 5.4.) In order to determine which sectors are write protected, A1 must be at VIH while running through the sector addresses; if the selected sector is protected, a logical ‘1’ will be output on DQ0 (DQ0 = 1). Write The device erasure and programming are accomplished via the command register. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. The command register itself does not occupy any addressable memory location. The register is a latch used to store the commands, along with the address and data information needed to execute the command. The command register is written by bringing WE to VIL, while CE is at VIL and OE is at VIH. Addresses are latched on the falling edge of WE or CE, whichever happens later, while data is latched on the rising edge of WE or CE, whichever happens first. Standard microprocessor write timings are used. Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters. Sector Protection The device features hardware sector protection. This feature will disable both program and erase operations in any number of sectors (0 through 18). The sector protection feature is enabled using programming equipment at the user’s site. The device is shipped with all sectors unprotected. To activate this mode, the programming equipment must force VID on address pin A9 and control pin OE, CE = VIL, A6 = A3 = A2 = A0 = VIL, A1 = VIH. The sector address pins (A19, A18, A17, A16, A15, A14, A13, and A12) should be set to the sector to be protected. Tables 7 and 8 define the sector address for each of the nineteen (19) individual sectors. Programming of the protection circuitry begins on the falling edge of the WE pulse and is terminated with the rising edge of the same. Sector addresses must be held constant during the WE pulse. See Figures 15 and 21 for sector protection waveforms and algorithms. To verify programming of the protection circuitry, the programming equipment must force VID on address pin A9 with CE and OE at VIL and WE at VIH. Scanning the sector addresses (A19, A18, A17, A16, A15, A14, A13, and A12) while (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0) will produce a logical “1” at device output DQ0 for a protected sector. Otherwise the device will read 00h for an unprotected sector. In this mode, the lower order address, except for A0, A1 and A6 are DON’T CAREs. Address locations with A1 = VIL are reserved for Autoselect manufacturer and device codes. A-1 requires to VIL in word mode. It is also possible to determine if a sector is protected in the system by writing an Autoselect command. Performing a read operation at the address location XX02h, where the higher order address pins (A19, A18, A17, A16, A15, A14, A13 and A12) represents the sector address will produce a logical “1” at DQ0 for a protected sector. See Tables 5.1 to 5.4 for Autoselect codes. Temporary Sector Unprotection This feature allows temporary unprotection of previously protected sectors of the device in order to change data. The Sector Unprotection mode is activated by the command register. In this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. Once the mode is taken away using the command register, all previously protected sectors will be protected again. (See Figure 22.) 20 MBM29PL3200TE/BE70/90 Boot Block Sector Protection The Write Protection function provides a hardware method of protecting certain “outermost” 16 K word ( × 16 mode) sector without using VID. If the system asserts VIL on the WP pin, the device disables program and erase functions in the “outermost” 16 K word sector independently of whether this sector was protected or unprotected using the method described in “Sector Protection/Unprotection”. The outermost 16 K word sector is the highest addresses in MBM29PL3200TE, or the lowest addresses in MBM29PL3200BE. (MBM29PL3200TE : SA18, MBM29PL3200BE : SA0) If the system asserts VIL on the WP pin, the device reverts to whether the outermost 16 K word sector was last set to be protected or unprotected. That is, sector protection or unprotection for this sector depends on whether this was last protected or unprotected using the method described in “Sector protection/unprotection”. Accelerated Program Operation The device offers accelerated program operation which enables high-speed programming. If the system asserts VACC to the ACC pin, the device automatically enters the acceleration mode and the time required for program operation will reduce to about 60%. This function is primarily intended to allow high-speed programming, so caution is needed as the sector group will temporarily be unprotected. The system would use a fast program command sequence when programming during acceleration mode. Set command to fast mode and reset command from fast mode are not necessary. When the device enters the acceleration mode, the device is automatically set to fast mode. Therefore, the present sequence could be used for programming and detection of completion in acceleration mode. Removing VACC from the ACC pin returns the device to normal operation. Do not remove VACC from the ACC pin while programming. See Figure 16. 21 MBM29PL3200TE/BE70/90 ■ COMMAND DEFINITIONS The device operations are selected by writing specific address and data sequences into the command register. Writing incorrect address and data values or writing them in an improper sequence will reset the device to the read mode. Table 4 defines the valid register command sequences. Note that the Erase Suspend (B0h) and Erase Resume (30h) commands are valid only while the Sector Erase operation is in progress. Moreover both Read/Reset commands are functionally equivalent, resetting the device to the read mode. Please note that commands are always written at DQ15 to DQ0 and DQ31 to DQ16 bits are ignored. Read/Reset Command In order to return from Autoselect mode or Exceeded Timing Limits (DQ5 = 1) to Read/Reset mode, the Read/ Reset operation is initiated by writing the Read/Reset command sequence into the command register. Microprocessor read cycles retrieve array data from the memory. The device remains enabled for reads until the command register contents are altered. The device will automatically power-up in the Read/Reset state. In this case, a command sequence is not required to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no spurious alteration of the memory content occurs during the power transition. Refer to the AC Read Characteristics and Waveforms for specific timing parameters. Autoselect Command Flash memories are intended for use in applications where the local CPU alters memory contents. As such, both manufacture and device codes must be accessible while the device resides in the target system. PROM programmers typically access the signature codes by raising A9 to a high voltage. However, multiplexing high voltage onto the address lines is not generally desired system design practice. The device contains an Autoselect command operation to supplement traditional PROM programming methodology. The operation is initiated by writing the Autoselect command sequence into the command register. Following the last command write, a read cycle from address XX00h retrieves the manufacture code of 04h. A read cycle at address XX01h (XX02h for ×8) returns 7Eh indicating that this device uses an extended device code. The successive read cycle from XX0Eh to XX0Fh returns this extended device code for this device. (See Tables 5.1 to 5.4.) The sector state (protection or unprotection) will be indicated by address XX02h for × 32 (XX04h for × 16). Scanning the sector addresses (A19, A18, A17, A16, A15, A14, A13 and A12) while (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0) will produce a logical “1” at device output DQ0 for a protected sector. The programming verification should perform margin mode verification on the protected sector. (See Tables 2 and 3.) To terminate the operation, it is necessary to write the Read/Reset command sequence into the register and to write the Autoselect command during the operation by executing it after writing the Read/Reset command sequence. Word/Double Word Programming The device is programmed on a word-by-word (or double word-by-double word) basis. Programming is a four bus cycle operation. There are two “unlock” write cycles. These are followed by the program set-up command and data write cycles. Addresses are latched on the falling edge of CE or WE, whichever happens later, and the data is latched on the rising edge of CE or WE, whichever happens first. The rising edge of the last CE or WE (whichever happens first) begins programming. Upon executing the Embedded Program Algorithm command sequence, the system is not required to provide further controls or timings. The device will automatically provide adequate internally generated program pulses and verify the programmed cell margin. (See Figures 6 and 7.) The system can determine the status of the program operation by using DQ7 (Data Polling), or DQ6 (Toggle Bit). The Data Polling and Toggle Bit must be performed at the memory location which is being programmed. The automatic programming operation is completed when the data on DQ7 is equivalent to data written to this bit. Then, the device return to the read mode and addresses are no longer latched. (See Table 10, Hardware Sequence Flags.) Therefore, the device requires that a valid address be supplied by the system at this time. Hence, Data Polling must be performed at the memory location which is being programmed. 22 MBM29PL3200TE/BE70/90 Any commands written to the chip during this period will be ignored. Programming is allowed in any sequence and across sector boundaries. Beware that a data “0” cannot be programmed back to a “1”. Attempting to do so may either hang up the device or result in an apparent success according to the data polling algorithm but a read from Read/Reset mode will show that the data is still “0”. Only erase operations can convert “0”s to “1”s. Figure 17 illustrates the Embedded ProgramTM Algorithm using typical command strings and bus operations. Chip Erase Chip erase is a six-bus cycle operation. There are two “unlock” write cycles. These are followed by writing the “set-up” command. Two more “unlock” write cycles are then followed by the chip erase command. Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded Erase Algorithm command sequence, the device will automatically program and verify the entire memory for an allzero data pattern prior to electrical erase (Preprogram Function). The system is not required to provide any controls or timings during these operations. The system can determine the status of the erase operation by using DQ7 (Data Polling), or DQ6 (Toggle Bit). The chip erase begins on the rising edge of the last CE or WE, whichever happens first in the command sequence and terminates when the data on DQ7 is “1” (See Write Operation Status section), at which time the device returns to the read mode. Chip Erase Time = Sector Erase Time × All sectors + Chip Program Time (Preprogramming) Figure 18 illustrates the Embedded EraseTM Algorithm using typical command strings and bus operations. Sector Erase Sector erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the “set-up” command. Two more “unlock” write cycles are then followed by the Sector Erase command. The sector address (any address location within the desired sector) is latched on the falling edge of CE or WE, whichever happens later, while the command (Data = 30h) is latched on the rising edge of CE or WE, which happens first. After time-out of “tTOW” from the rising edge of the last sector erase command, the sector erase operation will begin. Multiple sectors may be erased concurrently by writing the six bus cycle operations on Table 4. This sequence is followed with writes of the Sector Erase command (30h) to addresses in other sectors desired to be concurrently erased. The time between writes must be less than “tTOW”, or that command will not be accepted and erasure will not start. It is recommended that processor interrupts be disabled during this time to guarantee this condition. The interrupts can be re-enabled after the last Sector Erase command is written. A time-out of “tTOW” from the rising edge of last CE or WE, whichever happens first, will initiate the execution of the Sector Erase command (s). If another falling edge of CE or WE, whichever happens first, occurs within the “tTOW” time-out window, the timer is reset. (Monitor DQ3 to determine if the sector erase timer window is still open; see section DQ3, Sector Erase Timer.) Any command other than Sector Erase or Erase Suspend during this time-out period will reset the device to the read mode, ignoring the previous command string. In that case, restart the erase on those sectors and allow them to complete. (Refer to Write Operation Status section for Sector Erase Timer operation.) Loading the sector erase buffer may be done in any sequence and with any number of sectors (0 to 19). Sector erase does not require the user to program the device prior to erase. The device automatically programs all memory locations in the sector (s) to be erased prior to electrical erase (Preprogram function). When erasing a sector or sectors, the remaining unselected sectors are not affected. The system is not required to provide any controls or timings during these operations. The system can determine the status of the erase operation by using DQ7 (Data Polling) or DQ6 (Toggle Bit). The sector erase begins after the “tTOW” time out from the rising edge of CE or WE, whichever happens first ,for the last sector erase command pulse and terminates when the data on DQ7 is “1” (See Write Operation Status section), at which time the device returns to the read mode. Data polling and Toggle Bit must be performed at an address within any of the sectors being erased. Multiple Sector Erase Time = [Sector Erase Time + Sector Program Time (Preprogramming)] × Number of Sector Erase. 23 MBM29PL3200TE/BE70/90 Erase Suspend/Resume The Erase Suspend/Resume command allows the user to interrupt a Sector Erase operation and then perform data reads from or programs to a sector not being erased. Erase suspend command is applicable ONLY during the Sector Erase operation, which includes the time-out period for sector erase. The Erase Suspend command will be ignored if written during the Chip Erase operation or Embedded Program Algorithm. Writing the Erase Suspend command (B0h) during the Sector Erase time-out results in immediate termination of the time-out period and suspension of the erase operation. Writing the Erase Resume command (30h) resumes the erase operation. The addresses are “DON’T CAREs” when writing the Erase Suspend or Erase Resume command. When the Erase Suspend command is written during the Sector Erase operation, the device will take a maximum of “tSPD” to suspend the erase operation. When the device has entered the erase-suspended mode, the DQ7 bit will be at logic “1” and DQ6 will stop toggling. The user must use the address of the erasing sector for reading DQ6 and DQ7 to determine if the erase operation has been suspended. Further writes of the Erase Suspend command are ignored. When the erase operation has been suspended, the device defaults to the erase-suspend-read mode. Reading data in this mode is the same as reading from the standard read mode except that the data must be read from sectors that have not been erase-suspended. Successively reading from the erase-suspended sector while the device is in the erase-suspend-read mode will cause DQ2 to toggle. (See the section on DQ2.) After entering the erase-suspend-read mode, the user can program the device by writing the appropriate command sequence for Program. This program mode will become the erase-suspend-program mode. Again, programming in this mode is the same as programming in the regular Program mode except that the data must be programmed to sectors that are not erase-suspended. Successively reading from the erase-suspended sector while the device is in the erase-suspend-program mode will cause DQ2 to toggle. The end of the erase-suspended Program operation is detected by the Data polling of DQ7 or by the Toggle Bit I (DQ6), which is the same as the regular Program operation. Note that DQ7 must be read from the Program address while DQ6 can be read from any address. To resume the operation of Sector Erase, the Resume command (30h) should be written. Any further writes of the Resume command at this point will be ignored. Another Erase Suspend command can be written after the chip has resumed erasing. 24 MBM29PL3200TE/BE70/90 Extended Command (1) Fast Mode The device has a Fast Mode function. This mode dispenses with the initial two unlock cycles required in the standard program command sequence by writing a Fast Mode command into the command register. In this mode, the required bus cycle for programming is two cycles instead of four bus cycles in standard program command. (Do not write erase command in this mode.) The read operation is also executed after exiting this mode. To exit this mode, it is necessary to write a Fast Mode Reset command into the command register. (Refer to Figure 23.) The VCC active current is required even if CE = VIH during Fast Mode. (2) Fast Programming In Fast Mode, the programming can be executed with two bus cycle operation. The Embedded Program Algorithm is executed by writing a program set-up command (A0h) and data write cycles (PA/PD). (Refer to Figure 23.) (3) CFI (Common Flash Memory Interface) The CFI (Common Flash Memory Interface) specification outlines the device and host system software interrogation handshake which allows specific vendor-specified software algorithms to be used for entire families of the device. This allows device-independent, JEDEC ID-independent, and forward-and backward-compatible software support for the specified flash device families. Refer to CFI specification in detail. The operation is initiated by writing the query command (98h) into the command register. Following the command write, a read cycle from specific address retrieves device information. Please note that output data of upper byte (DQ15 to DQ8) is “0” in word mode (16 bit) read. Refer to the CFI code table. To terminate operation, it is necessary to write the Read/Reset command sequence into the register. 25 MBM29PL3200TE/BE70/90 Hidden ROM (Hi-ROM) Region The Hi-ROM feature provides a Flash memory region that the system may access through a new command sequence. This is primarily intended for customers who wish to use an Electronic Serial Number (ESN) in the device with the ESN protected against modification. Once the Hi-ROM region is protected, any further modification of that region is impossible. This ensures the security of the ESN once the product is shipped to the field. The Hi-ROM region is 512 words in length. After the system has written the Enter Hi-ROM command sequence, it may read the Hidden ROM region by using device addresses A7 to A0 (A11 to A8 are “00”, A19 to A12 are don’t care). That is, the device sends only program command that would normally be sent to the address to the HiROM region. This mode of operation continues until the system issues the Exit Hi-ROM command sequence, or until power is removed from the device. On power-up, or following a hardware reset, the device reverts to sending commands to the address. Hidden ROM (Hi-ROM) Entry Command The device has a Hidden ROM area with One Time Protect function. This area is to enter the security code and to unable the change of the code once set. Program/erase is possible in this area until it is protected. However, once it is protected, it is impossible to unprotect, so please use this with caution. Hidden ROM area is 512 words. This area is normally the “outermost” 16 K word boot block area. Therefore, write the Hidden ROM entry command sequence to enter the Hidden ROM area. It is called Hidden ROM mode when the Hidden ROM area appears. Hidden ROM (Hi-ROM) Program Command To program the data to the Hidden ROM area, write the Hidden ROM program command sequence during Hidden ROM mode. This command is the same as the program command in usual except to write the command during Hidden ROM mode. Therefore the detection of completion method is the same as in the past, using the DQ7 data polling, and DQ6 toggle bit. Need to pay attention to the address to be programmed. If the address other than the Hidden ROM area is selected to program, data of the address will be changed. Hidden ROM (Hi-ROM) Protect Command The method to protect the Hidden ROM is to apply high voltage (VID) to A9 and OE, set the sector address in the Hidden ROM area and (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0), and apply the write pulse during the Hidden ROM mode. To verify the protect circuit, apply high voltage (VID) to A9, specify (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0) and the sector address in the Hidden ROM area, and read. When “1” appears on DQ0, the protect setting is completed. “0” will appear on DQ0 if it is not protected. Please apply write pulse agian. The same command sequence could be used for the above method because other than the Hidden ROM mode, it is the same as the sector protect in the past. Please refer to “Function Explanation Secor Protection” for details of the sector protect setting. Other sector will be effected if the address other than those for Hidden ROM area is selected for the sector address, so please be carefull. Once it is protected, protection can not be cancelled, so please pay the closest attention. 26 MBM29PL3200TE/BE70/90 Write Operation Status Detailed in Table 10 are all the status flags that can be used to check the status of the device for current mode operation. During sector erase, the part provides the status flags automatically to the I/O ports. The information on DQ2 is address sensitive. This means that if an address from an erasing sector is consecutively read, then the DQ2 bit will toggle. However, DQ2 will not toggle if an address from a non-erasing sector is consecutively read. This allows users to determine which sectors are in erase and which are not. Once erase suspend is entered, address sensitivity still applies. If the address of a non-erasing sector (that is, one available for read) is provided, then stored data can be read from the device. If the address of an erasing sector (that is, one unavailable for read) is applied, the device will output its status bits. Status Table 10 Hardware Sequence Flags DQ6 DQ7 Embedded Program Algorithm Embedded Erase Algorithm In Progress Erase Suspend Read (Erase Suspended Sector) Erase Erase Suspend Read Suspended (Non-Erase Suspended Sector) Mode Erase Suspend Program (Non-Erase Suspended Sector) Embedded Program Algorithm Exceeded Embedded Erase Algorithm Time Limits Erase Suspend Program (Non-Erase Suspended Sector) DQ5 DQ3 DQ2 DQ7 Toggle 0 0 1 0 Toggle 0 1 Toggle * 1 1 0 0 Toggle Data Data Data Data Data DQ7 Toggle 0 0 1* DQ7 Toggle 1 0 1 0 Toggle 1 1 N/A DQ7 Toggle 1 0 N/A *: Successive reads from the erasing or erase-suspend sector will cause DQ2 to toggle. Reading from non-erase suspend sector address will indicate logic “1” at the DQ2 bit. Notes : 1.DQ0 and DQ1 are reserve pins for future use. 2.DQ4 is Fujitsu internal use only. 27 MBM29PL3200TE/BE70/90 DQ7 Data Polling The device features Data Polling as a method to indicate to the host that the Embedded Algorithms are in progress or completed. During the Embedded Program Algorithm an attempt to read the device will produce a complement of data last written to DQ7. Upon completion of the Embedded Program Algorithm, an attempt to read the device will produce true data last written to DQ7. During the Embedded Erase Algorithm, an attempt to read the device will produce a “0” at the DQ7 output. Upon completion of the Embedded Erase Algorithm an attempt to read the device will produce a “1” on DQ7. The flowchart for Data Polling (DQ7) is shown in Figure 19. For programming, the Data Polling is valid after the rising edge of the fourth write pulse in the four write pulse sequence. For chip erase and sector erase, the Data Polling is valid after the rising edge of the sixth write pulse in the six write pulse sequence. Data Polling must be performed at the sector address of sectors being erased, not protected sectors. Otherwise, the status may be invalid. Once the Embedded Algorithm operation is close to being completed, the device data pins (DQ7) may change asynchronously while the output enable (OE) is asserted low. This means that the device is driving status information on DQ7 at one instant and then that byte’s valid data at the next instant of time. Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the device has completed the Embedded Algorithm operation and DQ7 has valid data, data outputs on DQ6 to DQ0 may be still invalid. The valid data on DQ7 to DQ0 will be read on successive read attempts. The Data Polling feature is active only during the Embedded Programming Algorithm, Embedded Erase Algorithm or sector erase time-out. (See Table 10.) See Figure 9 for the Data Polling timing specifications and diagrams. DQ6 Toggle Bit I The device also features the “Toggle Bit I” as a method to indicate to the host system that the Embedded Algorithms are in progress or completed. During the Embedded Program or Erase Algorithm cycle, successive attempts to read (OE toggling) data from the device will result in DQ6 toggling between one and zero. Once the Embedded Program or Erase Algorithm cycle is completed, DQ6 will stop toggling and valid data will be read on the next successive attempts. During programming, the Toggle Bit I is valid after the rising edge of the fourth write pulse in the four write pulse sequence. For chip erase and sector erase, the Toggle Bit I is valid after the rising edge of the sixth write pulse in the six write pulse sequence. The Toggle Bit I is active during the sector time out. In programming, if the sector being written is protected, the toggle bit will toggle for about 1 µs and then stop toggling with data unchanged. In erase, device will erase all selected sectors except for ones that are protected. If all selected sectors are protected, the chip will toggle the toggle bit for about 400 µs and then drop back into read mode, having data unchanged. Either CE or OE toggling will cause DQ6 to toggle. In addition, an Erase Suspend/Resume command will cause DQ6 to toggle. See Figure 10 and Figure 20 for the Toggle Bit I timing specifications and diagrams. 28 MBM29PL3200TE/BE70/90 DQ5 Exceeded Timing Limits DQ5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count). Under these conditions DQ5 will produce a “1”. This is a failure condition which indicates that the program or erase cycle was not successfully completed. Data Polling is only operating function of device under this condition. The CE circuit will partially power down the device under these conditions (to approximately 2 mA). The OE and WE pins will control the output disable functions as described in Tables 2 and 3. The DQ5 failure condition may also appear if a user tries to program a non-blank location without pre-erase. In this case the device locks out and never completes the Embedded Algorithm operation. Hence, the system never reads valid data on DQ7 bit and DQ6 never stops toggling. Once the device has exceeded timing limits, the DQ5 bit will indicate a “1.” Please note that this is not a device failure condition since the device was incorrectly used. If this occurs, reset the device with the command sequence. DQ3 Sector Erase Timer After completion of the initial sector erase command sequence, sector erase time-out will begin. DQ3 will remain low until the time-out is completed. Data Polling and Toggle Bit are valid after the initial sector erase command sequence. If Data Polling or the Toggle Bit I indicates that the device has been written with a valid erase command, DQ3 may be used to determine whether the sector erase timer window is still open. If DQ3 is high (“1”), the internally controlled erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase operation is completed as indicated by Data Polling or Toggle Bit I. If DQ3 is low (“0”), the device will accept additional sector erase commands. To insure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent Sector Erase command. If DQ3 is high on the second status check, the command may not have been accepted. See Table 10 : Hardware Sequence Flags. DQ2 Toggle Bit II This toggle bit II, along with DQ6, can be used to determine whether the device is in the Embedded Erase Algorithm or in Erase Suspend. Successive reads from the erasing sector will cause DQ2 to toggle during the Embedded Erase Algorithm. If the device is in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause DQ2 to toggle. When the device is in the erase-suspended-program mode, successive reads from the byte address of the non-erase suspended sector will indicate a logic “1” at the DQ2 bit. DQ6 is different from DQ2 in that DQ6 toggles only when the standard program or Erase, or Erase Suspend Program operation is in progress. The behavior of these two status bits, along with that of DQ7, is summarized as follows : For example, DQ2 and DQ6 can be used together to determine whether the erase-suspend-read mode is in progress. (DQ2 toggles while DQ6 does not.) See also Table 11 and Figure 11. Furthermore, DQ2 can also be used to determine which sector is being erased. When the device is in the erase mode, DQ2 toggles if this bit is read from an erasing sector. 29 MBM29PL3200TE/BE70/90 Reading Toggle Bits DQ6/DQ2 Whenever the system initially begins reading toggle bit status, it must read DQ7 to DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, a system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ7 to DQ0 on the following read cycle. However, if, after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see the section on DQ5). If it is the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation. (Refer to Figure 20.) Mode Program Table 11 Toggle Bit Status DQ6 DQ7 DQ2 DQ7 Toggle 1 Erase 0 Toggle Toggle (Note) Erase-Suspend Read (Erase-Suspended Sector) 1 1 Toggle DQ7 Toggle 1 (Note) Erase-Suspend Program Note : Successive reads from the erasing or erase-suspend sector will cause DQ2 to toggle. Reading from nonerase suspend sector address will indicate logic “1” at the DQ2 bit. Double Word/Word Configuration DW/W pin selects double word (32-bit) mode or word (16-bit) mode for the device. When this pin is driven high, the device operates in the double word (32-bit) mode. Data is read and programmed at DQ31 to DQ0. When this pin is driven low, the device operates in word (16-bit) mode. In this mode, the DQ31/A-1 pin becomes the lowest address bit, and DQ30 to DQ16 bits are tri-stated. However, the command bus cycle is always an 16-bit operation and hence commands are written at DQ31 to DQ16 and DQ15 to DQ0 bits are ignored. Refer to Figures 12, 13 and 14 for the timing diagram. Data Protection The device is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transitions. During power-up, the device automatically resets the internal state machine to Read mode. Also, with its control register architecture, alteration of memory contents only occurs after successful completion of the specific multi-bus cycle command sequence. The device also incorporates several features to prevent inadvertent write cycles resulting from VCC power-up and power-down transitions or system noise. 30 MBM29PL3200TE/BE70/90 Low VCC Write Inhibit To avoid initiation of a write cycle during VCC power-up and power-down, a write cycle is locked out for VCC less than VLKO (Min.). If VCC < VLKO, the command register is disabled and all internal program/erase circuits are disabled. Under this condition, the device will reset to the read mode. Subsequent writes will be ignored until the VCC level is greater than VLKO. It is the user’s responsibility to ensure that the control pins are logically correct to prevent unintentional writes when VCC is above VLKO (Min.). If the Embedded Erase Algorithm is interrupted, there is possibility that the erasing sector (s) can not be used. Write Pulse “Glitch” Protection Noise pulses of less than 5 ns (typical) on OE, CE, or WE will not initiate a write cycle. Logical Inhibit Writing is inhibited by holding any one of OE = VIL, CE = VIH, or WE = VIH. To initiate a write cycle, CE and WE must be “L” while OE is a logical one. Power-up Write Inhibit Power-up of the device with WE = CE = VIL and OE = VIH will not accept commands on the rising edge of WE. The internal state machine is automatically reset to read mode on power-up. 31 MBM29PL3200TE/BE70/90 ■ ABSOLUTE MAXIMUM RATINGS Parameter Symbol Rating Unit Min. Max. Tstg −55 +125 °C Ta −40 +85 °C VIN, VOUT −0.5 VCC + 0.5 V Power Supply Voltage *1 VCC −0.5 +4.0 V A9, OE, and ACC *2 VIN −0.5 +13.0 V Storage Temperature Ambient Temperature with Power Applied Voltage with Respect to Ground All pins except A9, OE, and ACC *1 *1: Minimum DC voltage on input or l/O pins is −0.5 V. During voltage transitions, input or I/O pins may undershoot VSS to −2.0 V for periods of up to 20 ns. Maximum DC voltage on input or l/O pins is VCC +0.5 V. During voltage transitions, input or I/O pins may overshoot to VCC +2.0 V for periods of up to 20 ns. *2: Minimum DC input voltage on A9, OE and ACC pins is −0.5 V. During voltage transitions, A9, OE and ACC pins may undershoot VSS to −2.0 V for periods of up to 20 ns. Voltage difference between input and supply voltage (VIN − VCC) does not exceed 9.0 V. Maximum DC input voltage on A9, OE and ACC pins is +13.0 V which may overshoot to 14.0 V for periods of up to 20 ns. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. ■ RECOMMENDED OPERATING CONDITIONS Parameter Symbol Ambient Temperature Ta Power Supply Voltage VCC Part No. Value Min. Max. MBM29PL3200TE/BE 70 −20 +70 MBM29PL3200TE/BE 90 −40 +85 MBM29PL3200TE/BE 70 +3.0 +3.6 MBM29PL3200TE/BE 90 +2.7 +3.6 Unit °C V Operating ranges define those limits between which the functionality of the device is quaranteed. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 32 MBM29PL3200TE/BE70/90 ■ MAXIMUM OVERSHOOT/UNDERSHOOT 20 ns 20 ns +0.6 V −0.5 V −2.0 V 20 ns Figure 1 Maximum Undershoot Waveform 20 ns VCC + 2.0 V VCC + 0.5 V +2.0 V 20 ns Figure 2 20 ns Maximum Overshoot Waveform 1 20 ns +14.0 V +13.0 V VCC + 0.5 V 20 ns 20 ns Note : This waveform is applied for A9, OE and ACC. Figure 3 Maximum Overshoot Waveform 2 33 MBM29PL3200TE/BE70/90 ■ ELECTRICAL CHARACTERISTICS 1. DC Characteristics Parameter Symbol Conditions Value Min. Max. Input Leakage Current (except WP, ACC) ILI VIN = VSS to VCC, VCC = VCC Max. −1.0 +1.0 µA Output Leakage Current (except WP, ACC) ILO VOUT = VSS to VCC, VCC = VCC Max. −1.0 +1.0 µA Input Leakage Current (WP, ACC) ILI VIN = VSS to VCC, VCC = VCC Max. −2.0 +2.0 µA Output Leakage Current (WP, ACC) ILO VOUT = VSS to VCC, VCC = VCC Max. −2.0 +2.0 µA A9, OE, ACC Inputs Leakage Current ILIT VCC = VCC Max., A9, OE, ACC = 12.5 V 35 µA CE = VIL, OE = VIH f = 10 MHz VCC Active Current (Read) * 1 ICC1 CE = VIL, OE = VIH f = 5 MHz Word Double Word Word Double Word 80 80 50 50 mA mA VCC Active Current (Program/Erase) *2 ICC2 CE = VIL, OE = VIH 80 mA VCC Current (Standby) ICC3 VCC = VCC Max., CE = VCC ± 0.3 V 5 µA VCC Current (Automatic Sleep Mode) *3 ICC4 VCC = VCC Max., CE = VSS ± 0.3 V, VIN = VCC ± 0.3 V or VSS ± 0.3 V 5 µA VCC Active Current (Page Read Mode) ICC5 CE = VIL, OE = VIH 30 MHz 12 40 MHz 15 ACC Accelerated Program Current IACC VCC = VCC Max., ACC = VACC Max. 20 mA Input Low Level VIL −0.5 0.8 V Input High Level VIH 2.0 VCC + 0.3 V Voltage for Program Acceleration *4 VACC 11.5 12.5 V Voltage for Autoselect and Sector Protection (A9, OE) *4 VID 11.5 12.5 V Output Low Voltage Level VOL IOL = 4.0 mA, VCC = VCC Min. 0.45 V VOH1 IOH = −2.0 mA, VCC = VCC Min. 2.4 V VOH2 IOH = −100 µA VCC − 0.4 V 2.3 2.5 V Output High Voltage Level Low VCC Lock-Out Voltage VLKO *1: The lCC current listed includes both the DC operating current and the frequency dependent component. *2: lCC active while Embedded Erase or Embedded Program is in progress. *3: Automatic sleep mode enables the low power mode when address remains stable for 150 ns. *4: (VID − VCC) do not exceed 9 V. 34 Unit mA MBM29PL3200TE/BE70/90 2. AC Characteristics (1) Read Only Operations Characteristics Value Symbol Parameter Condition 1 Unit 90 *2 70 * JEDEC Standard Read Cycle Time tAVAV tRC 70 90 ns Address to Output Delay tAVQV tACC CE = VIL OE = VIL 70 90 ns Page Read Cycle Time tPRC 25 Page Address to Output Delay tPACC CE = VIL OE = VIL 25 35 ns Chip Enable to Output Delay tELQV tCE OE = VIL 70 90 ns Output Enable to Output Delay tGLQV tOE 25 35 ns Chip Enable to Output HIGH-Z tEHQZ tDF 25 30 ns Output Enable to Output HIGH-Z tGHQZ tDF 25 30 ns Output Hold Time From Address, CE or OE, Whichever Occurs First tAXQX tOH 4 5 ns tELFL tELFH 5 5 ns CE or DW/W Switching Low or High *1: Test Conditions : Output Load : 1 TTL gate and 50 pF Input rise and fall times : 5 ns Input pulse levels : 0.0 V to 3.0 V Timing measurement reference level Input : 1.5 V Output : 1.5 V Min. Max. Min. Max. 35 ns *2 Test Conditions : Output Load : 1 TTL gate and 100 pF Input rise and fall times : 5 ns Input pulse levels : 0.0 V to 3.0 V Timing measurement reference level Input : 1.5 V Output : 1.5 V 3.3 V IN3064 or Equivalent 2.7 kΩ Device Under Test 6.2 kΩ CL Diodes = IN3064 or Equivalent Figure 4 Test Conditions 35 MBM29PL3200TE/BE70/90 (2) Write (Erase/Program) Operations Value Symbol 70 *1 Unit 90 *2 JEDEC Standard tAVAV tWC Write Cycle Time 70 90 ns tAVWL tAS Address Setup Time 0 0 ns tWLAX tAH Address Hold Time 45 45 ns tDVWH tDS Data Setup Time 35 45 ns tWHDX tDH Data Hold Time 0 0 ns tOES Output Enable Setup Time 0 0 ns tOEH Output Enable Read Hold Time Toggle and Data Polling 0 0 ns 10 10 ns tGHWL tGHWL Read Recover Time Before Write 0 0 ns tGHEL tGHEL Read Recover Time Before Write (OE High to CE Low) 0 0 ns tELWL tCS CE Setup Time 0 0 ns tWLEL tWS WE Setup Time 0 0 ns tWHEH tCH CE Hold Time 0 0 ns tEHWH tWH WE Hold Time 0 0 ns tWLWH tWP Write Pulse Width 35 35 ns tELEH tCP CE Pulse Width 35 35 ns tWHWL tWPH Write Pulse Width High Level 30 30 ns tEHEL tCPH CE Pulse Width High Level 30 30 ns tWHWH1 tWHWH1 Programming Operation Double Word 18.3 18.3 Word 14.3 14.3 tWHWH2 tWHWH2 Sector Erase Operation *3 4 4 s tVCS VCC Setup Time 50 50 µs tVIDR Rise Time to VID *4 500 500 ns 500 500 ns 4 4 µs 100 100 µs 36 Parameter tVACCR Min. Typ. Max. Min. Typ. Max. 5 Rise Time to VACC * µs tVLHT Voltage Transition Time * tWPP Write Pulse Width *4 tOESP OE Setup Time to WE Active *4 4 4 µs 4 4 tCSP CE Setup Time to WE Active * 4 4 µs tEOE Delay Time from Embedded Output Enable 70 90 ns tFLQZ DW/W Switching Low to Output HIGH-Z 30 30 ns tFHQV DW/W Switching High to Output Active 35 30 ns tTOW Erase Time-out Time 50 50 µs tSPD Erase Suspend Transition Time 20 20 µs MBM29PL3200TE/BE70/90 *1: Test Conditions : Output Load : 1 TTL gate and 50 pF Input rise and fall times : 5 ns Input pulse levels : 0.0 V to 3.0 V Timing measurement reference level Input : 1.5 V Output : 1.5 V *2 Test Conditions : Output Load : 1 TTL gate and 100 pF Input rise and fall times : 5 ns Input pulse levels : 0.0 V to 3.0 V Timing measurement reference level Input : 1.5 V Output : 1.5 V *3: This does not include the preprogramming time. *4: This timing is for Sector Protection operation. *5: This timing is for Accelerated Program operation. 37 MBM29PL3200TE/BE70/90 ■ ERASE AND PROGRAMMING PERFORMANCE Parameter Value Unit Comments s Excludes programming time prior to erasure µs Excludes system-level overhead 280 s Excludes system-level overhead cycle Min. Typ. Max. Sector Erase Time 4 40 Word Programming Time 14.3 360 Double Word Programming Time 18.3 480 Chip Programming Time 20 100,000 Erase/Program Cycle ■ PIN CAPACITANCE Parameter Input Capacitance Symbol CIN Condition Value Unit Typ. Max. VIN = 0 6 7.5 pF Output Capacitance COUT VOUT = 0 8 10.0 pF Control Pin Capacitance CIN2 VIN = 0 8 10.0 pF Note : Test conditions Ta = 25 °C, f = 1.0 MHz ■ FBGA PIN CAPACITANCE Parameter Input Capacitance Symbol CIN Value Unit Typ. Max. VIN = 0 TBD TBD pF Output Capacitance COUT VOUT = 0 TBD TBD pF Control Pin Capacitance CIN2 VIN = 0 TBD TBD pF Note : Test conditions Ta = 25 °C, f = 1.0 MHz 38 Condition MBM29PL3200TE/BE70/90 ■ SWITCHING WAVEFORMS • Key to Switching Waveforms WAVEFORM INPUTS OUTPUTS Must Be Steady Will Be Steady May Change from H to L Will Be Change from H to L May Change from L to H Will Be Change from L to H "H" or "L": Any Change Permitted Changing, State Unknown Does Not Apply Center Line is HighImpedance "Off" State tRC Address Address Stable tACC CE tOE tDF OE tOEH WE tCE HIGH-Z Outputs tOH Output Valid HIGH-Z Figure 5.1 Read Operation Timing Diagram 39 MBM29PL3200TE/BE70/90 A19 to A2 Same page Address A1 to A0 (A-1) Aa Ab tRC tPRC Ac tACC CE OE tCE tOEH tOE tDF tPACC WE tOH Output High-Z Figure 5.2 40 Da tPACC tOH Db Page Read Operation Timing Diagram tOH Dc MBM29PL3200TE/BE70/90 3rd Bus Cycle Data Polling 555h Address tWC PA tAS PA tRC tAH CE tCS tCH tCE OE tGHWL tWP tOE tWPH tWHWH1 WE A0h Data tOH tDF tDS tDH PD DQ7 DOUT DOUT Notes : 1.PA is address of the memory location to be programmed. 2.PD is data to be programmed at word address. 3.DQ7 is the output of the complement of the data written to the device. 4.DOUT is the output of the data written to the device. 5.Figure indicates last two bus cycles out of four bus cycle sequence. 6.These waveforms are for the × 32 mode. (The addresses differ from × 16 mode.) Figure 6 Alternate WE Controlled Program Operation Timing Diagram 41 MBM29PL3200TE/BE70/90 3rd Bus Cycle Data Polling 555h Address tWC PA tAS PA tAH WE tWS tWH OE tGHEL tCP tCPH tWHWH1 CE tDS Data A0h tDH PD DQ7 DOUT Notes : 1.PA is address of the memory location to be programmed. 2.PD is data to be programmed at word address. 3.DQ7 is the output of the complement of the data written to the device. 4.DOUT is the output of the data written to the device. 5.Figure indicates last two bus cycles out of four bus cycle sequence. 6.These waveforms are for the × 32 mode. (The addresses differ from × 16 mode.) Figure 7 Alternate CE Controlled Program Operation Timing Diagram 42 MBM29PL3200TE/BE70/90 555h Address 2AAh tWC tAS 555h 555h 2AAh SA* tAH CE tCS tCH OE tGHWL tWP tWPH tDS tDH WE AAh 30h for Sector Erase 55h 80h AAh 55h 10h Data tVCS VCC Note : 1.SA is the sector address for Sector Erase. Addresses = 555h (Double Word), AAAh (Word) for Chip Erase. 2.These waveforms are for the × 32 mode. (The addresses differ from × 16 mode.) Figure 8 Chip/Sector Erase Operation Timing Diagram 43 MBM29PL3200TE/BE70/90 CE tCH tDF tOE OE tOEH WE tCE * DQ7 Data DQ7 DQ7 = Valid Data High-Z tWHWH1 or 2 DQ6 to DQ0 Data DQ6 to DQ0 = Output Flag DQ6 to DQ0 Valid Data High-Z tEOE * : DQ7 = Valid Data (The device has completed the Embedded operation) Figure 9 Data Polling during Embedded Algorithm Operation Timing Diagram 44 MBM29PL3200TE/BE70/90 CE tOEH WE tOES OE tDH DQ6 Data (DQ0 to DQ7) * DQ6 = Toggle DQ6 = Toggle DQ6 = Stop Toggling DQ0 to DQ7 Data Valid tOE * : DQ6 = Stops toggling. (The device has completed the Embedded operation.) Figure 10 Enter Embedded Erasing WE Toggle Bit I during Embedded Algorithm Operation Timing Diagram Erase Suspend Erase Enter Erase Suspend Program Erase Suspend Read Erase Suspend Program Erase Resume Erase Suspend Read Erase Erase Complete DQ6 DQ2 Toggle DQ2 and DQ6 with OE Note : DQ2 is read from the erase-suspended sector. Figure 11 DQ2 vs. DQ6 45 MBM29PL3200TE/BE70/90 CE tCE DW/W Data Output DQ30 to DQ0 Data Output (DQ30 to DQ0) (DQ15 to DQ0) tELFH tFHQV A-1 DQ31/A-1 Figure 12 DQ31 Double Word Mode Configuration Timing Diagram CE DW/W tELFL DQ30 to DQ0 Data Output Data Output (DQ30 to DQ0) (DQ15 to DQ0) tACC DQ31/A-1 A-1 DQ31 tFLQZ Figure 13 Word Mode Configuration Timing Diagram The falling edge of the last write signal CE or WE Input Valid DW/W tAS tAH Figure 14 DW/W Timing Diagram for Write Operations 46 MBM29PL3200TE/BE70/90 A19, A18, A17 A16, A15, A14 A13, A12 SAX SAY A0 A1 A6 VID 3V A9 VID 3V OE tVLHT tVLHT tVLHT tVLHT tWPP WE tOESP tCSP CE 01h Data tOE tVCS VCC SAX : Sector Address for initial sector SAY : Sector Address for next sector Note : A-1 is VIL on word mode. Figure 15 Sector Protection Timing Diagram 47 MBM29PL3200TE/BE70/90 VCC tVACCR tVCS tVLHT VACC VIH ACC CE WE tVLHT Program or Erase Command Sequence Acceleration period Figure 16 48 Accelerated Program Timing Diagram tVLHT MBM29PL3200TE/BE70/90 EMBEDDED ALGORITHM Start Write Program Command Sequence (See Below) Data Polling Device No Increment Address No Verify Byte ? Yes Embedded Program Algorithm in progress Last Address ? Yes Programming Completed Program Command Sequence* (Address/Command): 555h/AAh 2AAh/55h 555h/A0h Program Address/Program Data * : The sequence is applied for × 32 mode. The addresses differ from × 16 mode. Figure 17 Embedded ProgramTM Algorithm 49 MBM29PL3200TE/BE70/90 EMBEDDED ALGORITHM Start Write Erase Command Sequence (See Below) Data Polling or Toggle Bit from Device No Data = FFh ? Yes Embedded Erase Algorithm in progress Erasure Completed Chip Erase Command Sequence* (Address/Command): Individual Sector/Multiple Sector* Erase Command Sequence (Address/Command): 555h/AAh 555h/AAh 2AAh/55h 2AAh/55h 555h/80h 555h/80h 555h/AAh 555h/AAh 2AAh/55h 2AAh/55h 555h/10h Sector Address /30h Sector Address /30h Sector Address /30h Additional sector erase commands are optional. * : The sequence is applied for × 32 mode. The addresses differ from × 16 mode. Figure 18 50 Embedded EraseTM Algorithm MBM29PL3200TE/BE70/90 VA = Address for programming = Any of the sector addresses within the sector being erased during sector erase or multiple erases operation. = Any of the sector addresses within the sector not being protected during sector erase or multiple sector erases operation. Start Read Byte (DQ7 to DQ0) Addr. = VA DQ7 = Data? Yes No No DQ5 = 1? Yes Read Byte (DQ7 to DQ0) Addr. = VA DQ7 = Data? * No Fail Yes Pass * : DQ7 should be rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5. Figure 19 Data Polling Algorithm 51 MBM29PL3200TE/BE70/90 Start Read (DQ7 to DQ0) Addr. = "H" or "L" Read (DQ7 to DQ0) Addr. = "H" or "L" Toggle Bit = Toggle? (Note 1) No Yes No DQ5 = 1? Yes (Notes 1, 2) Read (DQ7 to DQ0) Twice Addr. = "H" or "L" Toggle Bit = Toggle? No Yes Program/Erase Operation Not Complete.Write Reset Command Program/Erase Operation Complete Notes : 1.Read toggle bit twice to determine whether or not it is toggling. 2.Recheck toggle bit because it may stop toggling as DQ5 changes to “1”. Figure 20 Toggle Bit Algorithm 52 MBM29PL3200TE/BE70/90 Start Setup Sector Group Addr. A19, A18, A17,A16, A15, A14, A13, A12 ( ) PLSCNT = 1 OE = VID, A9 = VID, CE = VIL, A6 = A3 = A2 = A0 = VIL, A1 = VIH Activate WE Pulse Increment PLSCNT Time out 100 µs WE = VIH, CE = OE = VIL (A9 should remain VID) Read from Sector = SA, A1 = VIH * ( AAddr. 6 = A3 = A2 = A0 = VIL ) No PLSCNT = 25? Yes Remove VID from A9 Write Reset Command No Data = 01h? Yes Protect Another Sector ? Yes No Device Failed Remove VID from A9 Write Reset Command Sector Protection Completed * : A-1 is V IL on word mode. Figure 21 Sector Protection Algorithm 53 MBM29PL3200TE/BE70/90 Start Temporary Unprotect Enable Command Write (Note 1) Perform Erase or Program Operations Temporary Unprotect Disable Command Write Temporary Sector Unprotection Completed (Note 2) Notes : 1.All protected sectors are unprotected. 2.All previously protected sectors are protected once again. Figure 22 Temporary Sector Unprotection Algorithm 54 MBM29PL3200TE/BE70/90 FAST MODE ALGORITHM Start 555h/AAh Set Fast Mode 2AAh/55h 555h/20h XXXh/A0h Program Address/Program Data Data Polling Device In Fast Program Verify Data? No Yes Increment Address No Last Address? Yes Programming Completed XXXXh/90h Reset Fast Mode XXXXh/F0h Notes 1 : The sequence is applied for × 32 mode. 2 : The addresses differ from × 16 mode. Figure 23 Embedded Programming Algorithm for Fast Mode 55 MBM29PL3200TE/BE70/90 ■ ORDERING INFORMATION Standard Products Fujitsu standard products are available in several packages. The order number is formed by a combination of: MBM29PL3200 T E 70 PFV PACKAGE TYPE PFV = 90-Pin Shrink Outline L-leaded Package (SSOP) PBT = 84-Ball Fine Pitch Ball Grid Array Package (FBGA) SPEED OPTION See Product Selector Guide DEVICE REVISION BOOT CODE SECTOR ARCHITECTURE T = Top sector B = Bottom sector DEVICE NUMBER/DESCRIPTION MBM29PL3200 32 Mega-bit (2 M × 16-Bit or 1 M × 32-Bit) CMOS Page Mode Flash Memory 3.0 V-only Read, Write, and Erase Valid Combinations Valid Combinations MBM29PL3200TE/BE 56 70 90 PFV PBT Valid Combinations list configurations planned to be supported in volume for this device. Consult the local Fujitsu sales office to confirm availability of specific valid combinations and to check on newly released combinations. MBM29PL3200TE/BE70/90 ■ PACKAGE DIMENSIONS 90-pin plastic SSOP (FPT-90P-M01) 23.70±0.30(.933±.012) 90 1.80±0.10 (Mounting height) (.071±.004) 0.55±0.10 (Stand off) (.022±.004) 46 "A" 16.00±0.30 (.630±.012) 13.30±0.20 (.524±.008) INDEX 1 Details of "A" part 45 0.50(.020) 0.22±0.05 (.009±.002) 0.08(.003) M 0.17 .007 +0.05 –0.03 +.002 –.001 0°~8° 0.73/1.00 (.029/.039) 0.25(.010) 0.08(.003) C 2000 FUJITSU LIMITED F90001S-1c-1 Dimensions in mm (inches) (Continued) 57 MBM29PL3200TE/BE70/90 (Continued) 84-ball plastic FBGA (BGA-84P-M01) +0.15 11.00±0.10(.433±.004) 1.05 –0.10 +.006 .041 –.004 (Mounting height) 7.20(.283)REF 0.38±0.10 (Stand off) (.015±.004) 8.00±0.10 (.315±.004) INDEX-MARK AREA 0.80(.031) TYP 9 8 7 6 5 4 3 2 1 6.40(.252) REF K J H G F E D C B A INDEX SIDE 84-Ø0.45±0.05 (84-Ø.018Ø.002) 0.08(.003) M 0.10(.004) C 2000 FUJITSU LIMITED B84001S-1c-1 Dimensions in mm (inches) 58 MBM29PL3200TE/BE70/90 FUJITSU LIMITED For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices Shinjuku Dai-Ichi Seimei Bldg. 7-1, Nishishinjuku 2-chome, Shinjuku-ku, Tokyo 163-0721, Japan Tel: +81-3-5322-3347 Fax: +81-3-5322-3386 http://edevice.fujitsu.com/ North and South America FUJITSU MICROELECTRONICS, INC. 3545 North First Street, San Jose, CA 95134-1804, U.S.A. Tel: +1-408-922-9000 Fax: +1-408-922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: +1-800-866-8608 Fax: +1-408-922-9179 http://www.fujitsumicro.com/ Europe FUJITSU MICROELECTRONICS EUROPE GmbH Am Siebenstein 6-10, D-63303 Dreieich-Buchschlag, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://www.fujitsu-fme.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LTD. #05-08, 151 Lorong Chuan, New Tech Park, Singapore 556741 Tel: +65-281-0770 Fax: +65-281-0220 http://www.fmap.com.sg/ Korea FUJITSU MICROELECTRONICS KOREA LTD. 1702 KOSMO TOWER, 1002 Daechi-Dong, Kangnam-Gu,Seoul 135-280 Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111 F0101 FUJITSU LIMITED Printed in Japan All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. 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