MC100LVEP14 2.5V / 3.3V1:5 Differential ECL/PECL/HSTL Clock Driver Description The MC100LVEP14 is a low skew 1−to−5 differential driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The ECL/PECL input signals can be either differential or single−ended (if the VBB output is used). HSTL inputs can be used when the LVEP14 is operating under PECL conditions. The LVEP14 specifically guarantees low output−to−output skew. Optimal design, layout, and processing minimize skew within a device and from device to device. To ensure that the tight skew specification is realized, both sides of any differential output need to be terminated identically into 50 W even if only one output is being used. If an output pair is unused, both outputs may be left open (unterminated) without affecting skew. The common enable (EN) is synchronous, outputs are enabled/ disabled in the LOW state. This avoids a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control. The internal flip flop is clocked on the falling edge of the input clock; therefore, all associated specification limits are referenced to the negative edge of the clock input. The MC100LVEP14, as with most other ECL devices, can be operated from a positive VCC supply in PECL mode. This allows the LVEP14 to be used for high performance clock distribution in +3.3 V or +2.5 V systems. Single−ended CLK input pin operation is limited to a VCC ≥ 3.0 V in PECL mode, or VEE ≤ −3.0 V in NECL mode. Designers can take advantage of the LVEP14’s performance to distribute low skew clocks across the backplane or the board. Features • • • • • • • http://onsemi.com TSSOP−20 DT SUFFIX CASE 948E MARKING DIAGRAM* 20 100 VP14 ALYWG G 1 A L Y W G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) 100 ps Device−to−Device Skew 25 ps Within Device Skew *For additional marking information, refer to Application Note AND8002/D. 400 ps Typical Propagation Delay Maximum Frequency > 2 GHz Typical ORDERING INFORMATION The 100 Series Contains Temperature Compensation See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. PECL and HSTL Mode: VCC = 2.375 V to 3.8 V with VEE = 0 V NECL Mode: VCC = 0 V with VEE = −2.375 V to −3.8 V LVDS Input Compatible • • Open Input Default State • Pb−Free Packages are Available* *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2006 November, 2006 − Rev. 11 1 Publication Order Number: MC100LVEP14/D MC100LVEP14 VCC EN VCC CLK1 CLK1 VBB CLK0 20 19 18 17 16 15 14 13 12 11 1 D CLK0 CLK_SEL VEE 0 Q 1 2 3 4 5 6 7 8 9 10 Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 Q4 Q4 Warning: All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation. Figure 1. 20−Lead Pinout (Top View) and Logic Diagram Table 1. PIN DESCRIPTION Pin Table 2. FUNCTION TABLE Function CLK0*, CLK0** ECL/PECL/HSTL CLK Input CLK1*, CLK1** ECL/PECL/HSTL CLK Input Q0:4, Q0:4 ECL/PECL Outputs CLK_SEL* ECL/PECL Active Clock Select Input EN* ECL Sync Enable VBB Reference Voltage Output VCC Positive Supply VEE Negative Supply CLK0 CLK1 CLK_SEL EN Q L H X X X X X L H X L L H H X L L L L H L H L H L* *On next negative transition of CLK0 or CLK1 * Pins will default low when left open. **Pins will default to VCC/2 when left open. Table 3. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 75 kW Internal Input Pullup Resistor ESD Protection 37.5 kW Human Body Model Machine Model Charged Device Model Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) TSSOP−20 Flammability Rating Oxygen Index: 28 to 34 Transistor Count > 2 kV > 100 V > 2 kV Pb Pkg Pb−Free Pkg Level 1 Level 1 UL 94 V−0 @ 0.125 in 357 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. http://onsemi.com 2 MC100LVEP14 Table 4. MAXIMUM RATINGS Rating Unit VCC Symbol PECL Mode Power Supply Parameter VEE = 0 V Condition 1 Condition 2 6 V VEE NECL Mode Power Supply VCC = 0 V −6 V VI PECL Mode Input Voltage NECL Mode Input Voltage VEE = 0 V VCC = 0 V 6 −6 V V Iout Output Current Continuous Surge 50 100 mA mA IBB VBB Sink/Source ± 0.5 mA TA Operating Temperature Range −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm TSSOP−20 TSSOP−20 140 100 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) Standard Board TSSOP−20 23 to 41 °C/W Tsol Wave Solder 265 265 °C VI VCC VI VEE Pb Pb−Free Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Table 5. 100LVEP DC CHARACTERISTICS, PECL VCC = 2.5 V, VEE = 0 V (Note 2) −40°C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 45 60 75 45 60 75 45 60 75 mA 1355 1480 1605 1355 1480 1605 1355 1480 1605 mV 730 730 730 IEE Power Supply Current VOH Output HIGH Voltage (Note 3) VOL Output LOW Voltage (Note 3) 555 900 555 900 555 900 mV VIH Input HIGH Voltage (Single−Ended) (Note 4) 1335 1620 1335 1620 1275 1620 mV VIL Input LOW Voltage (Single−Ended) (Note 4) 555 900 555 900 555 900 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 5) 1.2 2.5 1.2 2.5 1.2 2.5 V IIH Input HIGH Current 150 mA IIL Input LOW Current 150 CLK CLK 0.5 −150 150 0.5 −150 0.5 −150 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 2. Input and output parameters vary 1:1 with VCC. VEE can vary +0.125 V to −1.3 V. 3. All loading with 50 W to VCC − 2.0 V. 4. Do not use VBB at VCC < 3.0 V. 5. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. http://onsemi.com 3 MC100LVEP14 Table 6. 100LVEP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 6) −40°C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 45 60 75 45 60 75 45 60 75 mA Output HIGH Voltage (Note 7) 2155 2280 2405 2155 2280 2405 2155 2280 2405 mV VOL Output LOW Voltage (Note 7) 1355 1530 1700 1355 1530 1700 1355 1530 1700 mV VIH Input HIGH Voltage (Single−Ended) 2135 2420 2135 2420 2135 2420 mV VIL Input LOW Voltage (Single−Ended) 1355 1700 1355 1700 1355 1700 mV VBB Output Reference Voltage (Note 8) 1775 1975 1775 1975 1775 1975 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 9) 1.2 3.3 1.2 3.3 1.2 3.3 V IIH Input HIGH Current 150 mA IIL Input LOW Current IEE Power Supply Current VOH 1875 1875 150 CLK CLK 1875 150 0.5 −150 0.5 −150 0.5 −150 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 6. Input and output parameters vary 1:1 with VCC. VEE can vary +0.925 V to −0.5 V. 7. All loading with 50 W to VCC − 2.0 V. 8. Single−ended input operation is limited to VCC 3.0 V in PECL mode. 9. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Table 7. 100LVEP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = −3.8 V to −2.375 V (Note 10) −40°C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 45 60 75 45 60 75 45 60 95 mA IEE Power Supply Current VOH Output HIGH Voltage (Note 11) −1145 −1020 −895 −1145 −1020 −895 −1145 −1020 −895 mV VOL Output LOW Voltage (Note 11) −1945 −1770 −1600 −1945 −1770 −1600 −1945 −1770 −1600 mV VIH Input HIGH Voltage (Single−Ended) −1165 −880 −1165 −880 −1165 −880 mV VIL Input LOW Voltage (Single−Ended) −1945 −1600 −1945 −1600 −1945 −1600 mV VBB Output Reference Voltage (Note 12) −1525 −1325 −1525 −1325 −1525 −1325 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 13) 0.0 V IIH Input HIGH Current 150 mA IIL Input LOW Current −1425 VEE + 1.2 0.0 VEE + 1.2 150 CLK CLK 0.5 −150 −1425 0.0 VEE + 1.2 150 0.5 −150 −1425 0.5 −150 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 10. Input and output parameters vary 1:1 with VCC. 11. All loading with 50 W to VCC − 2.0 V. 12. Single−ended input operation is limited to VEE 3.0 V in NECL mode. 13. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. http://onsemi.com 4 MC100LVEP14 Table 8. DC CHARACTERISTICS, HSTL VCC = 2.375 V to 3.8 V, VEE = 0 V −40°C Symbol Min Characteristic VIH Input HIGH Voltage VIL Input LOW Voltage 25°C Typ Max 1200 Min Typ 85°C Max 1200 Min Typ Max 1200 400 Unit mV 400 400 mV NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. Table 9. AC CHARACTERISTICS VCC = 0 V, VEE = −2.375 V to −3.8 V or VCC = 2.375 V to 3.8 V; VEE = 0 V (Note 14) −40°C 25°C Symbol Characteristic Min Typ VOUTPP Output Voltage Amplitude @ 2.5 GHz (Figure 2) 330 425 tPLH tPHL Propagation Delay to Output Differential 300 375 425 tskew Within−Device Skew (Note 15) Device−to−Device Skew (Note 15) 10 100 25 125 ts th Setup Time Hold Time tJITTER CLOCK Random Jitter (RMS) @ v 1.0 GHz @ v 1.5 GHz @ v 2.0 GHz @ v 2.5 GHz VPP Minimum Input Swing tr/tf Output Rise/Fall Time (20%−80%) EN EN 100 200 Max 50 140 Min Typ 280 375 300 400 475 15 150 25 175 100 200 0.157 0.163 0.180 0.179 0.3 0.2 0.3 0.3 150 800 1200 125 165 225 85°C Max 50 140 Min Typ 230 295 300 430 525 ps 15 200 25 225 ps 100 200 0.181 0.176 0.201 0.208 0.3 0.3 0.3 0.3 150 800 1200 125 180 250 Max Unit mV 50 140 ps ps 0.212 0.218 0.235 0.253 0.3 0.3 0.3 0.4 150 800 1200 mV 125 200 275 ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 14. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to VCC − 2.0 V. 15. Skew is measured between outputs under identical transitions. http://onsemi.com 5 MC100LVEP14 900 5.0 V VOUTpp (mVpp) 800 3.3 V 700 600 500 400 300 200 100 0 0.0 0.5 1.0 1.5 2.0 2.5 FREQUENCY (GHz) Figure 2. Typical VOUTPP (mVpp) versus Frequency (GHz) @ 255C Q Zo = 50 W D Receiver Device Driver Device Q D Zo = 50 W 50 W 50 W VTT VTT = VCC − 2.0 V Figure 3. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D − Termination of ECL Logic Devices.) ORDERING INFORMATION Package Shipping † MC100LVEP14DT TSSOP−20* 75 Units / Rail MC100LVEP14DTG TSSOP−20* 75 Units / Rail MC100LVEP14DTR2 TSSOP−20* 2500 / Tape & Reel MC100LVEP14DTR2G TSSOP−20* 2500 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb−Free. http://onsemi.com 6 MC100LVEP14 Resource Reference of Application Notes AN1405/D − ECL Clock Distribution Techniques AN1406/D − Designing with PECL (ECL at +5.0 V) AN1503/D − ECLinPSt I/O SPiCE Modeling Kit AN1504/D − Metastability and the ECLinPS Family AN1568/D − Interfacing Between LVDS and ECL AN1672/D − The ECL Translator Guide AND8001/D − Odd Number Counters Design AND8002/D − Marking and Date Codes AND8020/D − Termination of ECL Logic Devices AND8066/D − Interfacing with ECLinPS AND8090/D − AC Characteristics of ECL Devices http://onsemi.com 7 MC100LVEP14 PACKAGE DIMENSIONS TSSOP−20 CASE 948E−02 ISSUE C 20X 0.15 (0.006) T U 2X L K REF 0.10 (0.004) S L/2 20 M T U S V K K1 ÍÍÍÍ ÍÍÍÍ ÍÍÍÍ S J J1 11 B −U− PIN 1 IDENT SECTION N−N 0.25 (0.010) N 1 10 M 0.15 (0.006) T U S A −V− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. N F DETAIL E −W− C G D H DETAIL E 0.100 (0.004) −T− SEATING DIM A B C D F G H J J1 K K1 L M PLANE SOLDERING FOOTPRINT* 7.06 1 0.65 PITCH 16X 0.36 16X 1.26 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 8 MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 −−− 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.252 0.260 0.169 0.177 −−− 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ MC100LVEP14 ECLinPS is a trademark of Semiconductor Components INdustries, LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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