MC100EL38 5VECL ÷2, ÷4/6 Clock Generation Chip The MC100EL38 is a low skew ÷2, ÷4/6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The device can be driven by http://onsemi.com either a differential or single-ended ECL or, if positive power supplies are used, PECL input signal. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 mF capacitor and limit current sourcing or sinking SO−20 WB to 0.5 mA. When not used, VBB should be left open. DW SUFFIX CASE 751D The common enable (EN) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state. This avoids any chance of generating a runt MARKING DIAGRAM* clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. An internal runt pulse 20 could lead to losing synchronization between the internal divider stages. The internal enable flip−flop is clocked on the falling edge of the input clock, therefore, all associated specification limits are 100EL38 AWLYYWWG referenced to the negative edge of the clock input. The Phase_Out output will go HIGH for one clock cycle whenever the ÷2 and the ÷4/6 outputs are both transitioning from a LOW to a 1 HIGH. This output allows for clock synchronization within the system. Upon startup, the internal flip-flops will attain a random state; A = Assembly Location therefore, for systems which utilize multiple EL38s, the master reset WL = Wafer Lot YY = Year (MR) input must be asserted to ensure synchronization. For systems WW = Work Week which only use one EL38, the MR pin need not be exercised as the G = Pb−Free Package internal divider design ensures synchronization between the ÷2 and the ÷4/6 outputs of a single device. *For additional marking information, refer to • 50 ps Output-to-Output Skew Application Note AND8002/D. • Synchronous Enable/Disable • Master Reset for Synchronization ORDERING INFORMATION • ESD Protection: > 2 kV Human Body Model, See detailed ordering and shipping information in the package > 100 V Machine Model dimensions section on page 6 of this data sheet. • The 100 Series Contains Temperature Compensation • PECL Mode Operating Range: VCC = 4.2 V to 5.7 V • Moisture Sensitivity Level 1 with VEE = 0 V For Additional Information, see Application Note AND8003/D • NECL Mode Operating Range: VCC = 0 V with • Flammability Rating: UL 94 V−0 @ 0.125 in, VEE = −4.2 V to −5.7 V Oxygen Index: 28 to 34 • Internal 75 kW Input Pulldown Resistors on CLK, EN, • Transistor Count = 388 devices MR, and DIVSEL • Q Output will Default LOW with Inputs Open or at • Pb−Free Packages are Available* VEE • Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2006 October, 2006 − Rev. 7 1 Publication Order Number: MC100EL38/D MC100EL38 VCC Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 VEE 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 CLK VBB MR VCC EN DIV_SEL CLK VCC Phase_Out Phase_Out * All VCC pins are tied together on the die. Warning: All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation. Figure 1. Pinout Assignment (Top View) Q0 CLK P2 CLK R Q0 Q1 Q1 EN Q2 R P4/6 Q2 R Q3 MR Q3 DIVSEL PHASE_OUT Phase Out R Logic PHASE_OUT Figure 2. Logic Diagram Table 1. PIN DESCRIPTION Pin Table 2. FUNCTION TABLE Function CLK, CLK ECL Diff Clock Inputs Q0, Q1; Q0, Q1 ECL Diff ÷2 Outputs Q2, Q3; Q2, Q3 ECL Diff ÷4/6 Outputs EN ECL Sync Enable Input MR ECL Master Reset Input DIVSEL ECL Frequency Select Input Phase_Out, Phase_Out ECL Phase Sync Diff. Signal Output VBB Reference Voltage Output VCC Positive Supply VEE Negative Supply CLK EN MR Z ZZ X L H X L L H Function Divide Hold Q0−3 Reset Q0−3 Z = Low-to-High Transition ZZ = High-to-Low Transition X = Don’t Care DIVSEL L H http://onsemi.com 2 Q2, Q3 OUTPUTS Divide by 4 Divide by 6 MC100EL38 Table 3. MAXIMUM RATINGS Symbol Rating Unit VCC PECL Mode Power Supply Parameter VEE = 0 V Condition 1 8 V VEE NECL Mode Power Supply VCC = 0 V −8 V VI PECL Mode Input Voltage NECL Mode Input Voltage VEE = 0 V VCC = 0 V 6 −6 V V Iout Output Current Continuous Surge 50 100 mA mA IBB VBB Sink/Source ± 0.5 mA TA Operating Temperature Range −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm SOIC−20 SOIC−20 90 60 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) Standard Board SOIC−20 30 to 35 °C/W Tsol Wave Solder <2 to 3 sec @ 248°C <2 to 3 sec @ 260°C 265 265 °C Pb Pb−Free Condition 2 VI ≤ VCC VI ≥ VEE Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Table 4. 100EL SERIES PECL DC CHARACTERISTICS VCC = 5.0 V; VEE = 0.0 V (Note 1) −40°C Symbol Characteristic Min 25°C Typ Max 50 60 Min 85°C Typ Max 50 60 Min Typ Max Unit 54 65 mA IEE Power Supply Current VOH Output HIGH Voltage (Note 2) 3915 3995 4120 3975 4045 4120 3975 4050 4120 mV VOL Output LOW Voltage (Note 2) 3170 3305 3445 3190 3295 3380 3190 3295 3380 mV VIH Input HIGH Voltage (Single−Ended) 3835 4120 3835 4120 3835 4120 mV VIL Input LOW Voltage (Single−Ended) 3190 3525 3190 3525 3190 3525 mV VBB Output Voltage Reference 3.62 3.74 3.62 3.74 3.62 3.74 V VIHCMR Input HIGH Voltage Common Mode Range (Differential) (Note 3) 1.65 4.45 1.65 4.45 1.65 4.45 V IIH Input HIGH Current 150 mA IIL Input LOW Current 150 0.5 150 0.5 0.5 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 1. Input and output parameters vary 1:1 with VCC. VEE can vary +0.8 V / −0.5 V. 2. Outputs are terminated through a 50 W resistor to VCC − 2.0 V. 3. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPPmin and 1 V. http://onsemi.com 3 MC100EL38 Table 5. 100EL SERIES NECL DC CHARACTERISTICS VCC = 0.0 V; VEE = −5.0 V (Note 4) −40°C Symbol Min Characteristic 25°C Typ Max 50 60 Min 85°C Typ Max 50 60 Min Typ Max Unit 54 65 mA IEE Power Supply Current VOH Output HIGH Voltage (Note 5) −1085 −1005 −880 −1025 −955 −880 −1025 −955 −880 mV VOL Output LOW Voltage (Note 5) −1830 −1695 −1555 −1810 −1705 −1620 −1810 −1705 −1620 mV VIH Input HIGH Voltage (Single−Ended) −1165 −880 −1165 −880 −1165 −880 mV VIL Input LOW Voltage (Single−Ended) −1810 −1475 −1810 −1475 −1810 −1475 mV VBB Output Voltage Reference −1.38 −1.26 −1.38 −1.26 −1.38 −1.26 V VIHCMR Input HIGH Voltage Common Mode Range (Differential) (Note 6) −3.35 −0.55 −3.35 −0.55 −3.35 −0.55 V IIH Input HIGH Current 150 mA IIL Input LOW Current 150 150 0.5 0.5 0.5 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 4. Input and output parameters vary 1:1 with VCC. VEE can vary +0.8 V / −0.5 V. 5. Outputs are terminated through a 50 W resistor to VCC − 2.0 V. 6. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPPmin and 1 V. Table 6. AC CHARACTERISTICS VCC = 5.0 V; VEE = 0.0 V or VCC = 0.0 V; VEE = −5.0 V (Note 7) −40°C Symbol Min Characteristic fmax Maximum Toggle Frequency tPLH tPHL Propagation Delay to Output CLK → Q (Differential) CLK → Q (Single−Ended) CLK → Phase_Out (Differential) CLK → Phase_Out (Single−Ended) MR → Q tSKEW Within-Device Skew (Note 8) tJITTER Cycle−to−Cycle Jitter Typ 25°C Max Min TBD 810 710 800 750 510 Max Min TBD 1010 1010 1000 1050 810 Q0 − Q3 All Typ 85°C 850 750 840 790 540 900 800 890 840 570 50 75 TBD 200 240 ps ps ps TBD Part-to-Part Q0 − Q3 (Differential) All tS Setup Time EN → CLK DIVSEL → CLK 150 150 150 ps tH Hold Time CLK → EN CLK → Div_Sel 150 200 150 200 150 200 ps VPP Input Swing (Note 9) tRR Reset Recovery Time tPW Minimum Pulse Width tr, tf Output Rise/Fall Times Q (20% − 80%) 150 1000 200 240 Unit GHz 1100 1100 1090 1140 870 50 75 TBD Max TBD 1050 1050 1040 1090 840 50 75 Typ 150 100 CLK MR 800 700 1000 550 150 100 800 700 280 200 240 280 1000 mV 100 ps 800 700 550 280 ps 550 ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 7. VEE can vary +0.8 V / −0.5 V. 8. Skew is measured between outputs under identical transitions. 9. VPP(min) is minimum input swing for which AC parameters guaranteed. The device has a DC gain of ≈40. http://onsemi.com 4 MC100EL38 tRR MR CLK Q (P2) Q (P4) Q (P6) Phase_Out (P4) Phase_Out (P6) Figure 3. Timing Diagram Q Zo = 50 W D Receiver Device Driver Device Q D Zo = 50 W 50 W 50 W VTT VTT = VCC − 2.0 V Figure 4. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D − Termination of ECL Logic Devices.) http://onsemi.com 5 MC100EL38 ORDERING INFORMATION Package Package† MC100EL38DW SOIC−20 38 Units / Rail MC100EL38DWG SOIC−20 (Pb−Free) 38 Units / Rail MC100EL38DWR2 SOIC−20 1000 / Tape & Reel MC100EL38DWR2G SOIC−20 (Pb−Free) 1000 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Resource Reference of Application Notes AN1405/D − ECL Clock Distribution Techniques AN1406/D − Designing with PECL (ECL at +5.0 V) AN1503/D − ECLinPS I/O SPiCE Modeling Kit AN1504/D − Metastability and the ECLinPS Family AN1568/D − Interfacing Between LVDS and ECL AN1672/D − The ECL Translator Guide AND8001/D − Odd Number Counters Design AND8002/D − Marking and Date Codes AND8020/D − Termination of ECL Logic Devices AND8066/D − Interfacing with ECLinPS AND8090/D − AC Characteristics of ECL Devices http://onsemi.com 6 MC100EL38 PACKAGE DIMENSIONS SO−20 WB DW SUFFIX CASE 751D−05 ISSUE G A 20 q X 45 _ E h H M 10X 0.25 NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. 11 B M D 1 10 20X B B 0.25 M T A S B S L A 18X e A1 SEATING PLANE C T DIM A A1 B C D E e H h L q MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_ ECLinPS are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 http://onsemi.com 7 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative MC100EL38/D