MOTOROLA MC14099BCL

SEMICONDUCTOR TECHNICAL DATA
The MC14099B and MC14599B are 8–bit addressable latches. Data is
entered in serial form when the appropriate latch is addressed (via address
pins A0, A1, A2) and write disable is in the low state. Chip enable must be
high for writing into MC14599B. For the MC14599B the data pin is a
bidirectional data port and for the MC14099B the input is a unidirectional
write only port. The Write/Read line controls this port in the MC14599B.
The data is presented in parallel at the output of the eight latches
independently of the state of Write Disable, Write/Read or Chip Enable.
A Master Reset capability is available on both parts.
L SUFFIX
CERAMIC
CASE 620
P SUFFIX
PLASTIC
CASE 648
•
•
•
•
•
Serial Data Input
Parallel Output
Master Reset
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two Low–power TTL Loads or One Low–Power
Schottky TTL Load over the Rated Temperature Range
• MC14099B pin for pin compatible with CD4099B
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MAXIMUM RATINGS* (Voltages Referenced to VSS)
Symbol
Parameter
VDD
Vin, Vout
Value
Unit
– 0.5 to + 18.0
V
Input or Output Voltage (DC or Transient)
– 0.5 to VDD + 0.5
V
Input or Output Current (DC or Transient),
per Pin
± 10
mA
Power Dissipation, per Package†
500
mW
– 65 to + 150
_C
DC Supply Voltage
Iin, Iout
PD
Tstg
Storage Temperature
DW SUFFIX
SOIC
CASE 751G
ORDERING INFORMATION
MC14099BCP
MC14099BCL
MC14099BDW
TA = – 55° to 125°C for all packages.
L SUFFIX
CERAMIC
CASE 726
TL
Lead Temperature (8–Second Soldering)
260
_C
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C
MC14099B
5
6
DECODER
7
A0
A1
A2
RESET
9
10
11
12
8
13
LATCHES 14
15
1
4
3
WRITE DISABLE
DATA
P SUFFIX
PLASTIC
CASE 707
MC14599B
8
2
VDD = 16
VSS = 8
8
10
4
3
CHIP ENABLE
WRITE/READ
WRITE DISABLE
Q0
DATA
Q1
Q2
A0
Q3
A1
Q4
A2
Q5
Q6
RESET
Q7
5
6
7
8
DECODER
2
11
12
13
8
14
LATCHES
15
16
17
1
VDD = 18
VSS = 9
PIN ASSIGNMENT
PIN ASSIGNMENT
Q7
1
18
VDD
RESET
2
17
Q6
3
16
Q5
4
15
Q4
5
14
Q3
Q7
1
16
VDD
RESET
2
15
Q6
DATA
WRITE
DISABLE
A0
3
14
Q5
4
13
Q4
DATA
WRITE
DISABLE
A0
5
12
Q3
A1
6
13
Q2
A1
6
11
Q2
A2
7
12
Q1
A2
7
10
Q1
CE
8
11
VSS
8
9
Q0
VSS
9
10
Q0
WRITE/
READ
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Plastic
Ceramic
SOIC
ORDERING INFORMATION
MC14599BCP
MC14599BCL
Plastic
Ceramic
TA = – 55° to 125°C for all packages.
This device contains protection circuitry to
guard against damage due to high static
voltages or electric fields. However, precautions must be taken to avoid applications of
any voltage higher than maximum rated voltages to this high–impedance circuit. For proper
operation, Vin and Vout should be constrained
to the range VSS
(Vin or Vout)
VDD.
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either VSS
or VDD). Unused outputs must be left open.
v
v
REV 0
1/94
MC14099B
Motorola, Inc. 1995
MC14599B
246
MOTOROLA CMOS LOGIC DATA
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ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Characteristic
Output Voltage
Vin = VDD or 0
Symbol
– 55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
“0” Level
VOL
5.0
10
15
—
—
—
0.05
0.05
0.05
—
—
—
0
0
0
0.05
0.05
0.05
—
—
—
0.05
0.05
0.05
Vdc
“1” Level
VOH
5.0
10
15
4.95
9.95
14.95
—
—
—
4.95
9.95
14.95
5.0
10
15
—
—
—
4.95
9.95
14.95
—
—
—
Vdc
5.0
10
15
—
—
—
1.5
3.0
4.0
—
—
—
2.25
4.50
6.75
1.5
3.0
4.0
—
—
—
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
—
—
—
3.5
7.0
11
2.75
5.50
8.25
—
—
—
3.5
7.0
11
—
—
—
5.0
5.0
10
15
– 3.0
– 0.64
– 1.6
– 4.2
—
—
—
—
– 2.4
– 0.51
– 1.3
– 3.4
– 4.2
– 0.88
– 2.25
– 8.8
—
—
—
—
– 1.7
– 0.36
– 0.9
– 2.4
—
—
—
—
IOL
5.0
10
15
0.64
1.6
4.2
—
—
—
0.51
1.3
3.4
0.88
2.25
8.8
—
—
—
0.36
0.9
2.4
—
—
—
mAdc
Input Current
Iin
15
—
± 0.1
—
± 0.00001
± 0.1
—
± 1.0
µAdc
Input Capacitance
(Vin = 0)
Cin
—
—
—
—
5.0
7.5
—
—
pF
Input Capacitance
MC14599B — Data (pin 3)
(Vin = 0)
Cin
—
—
—
—
15
22.5
—
—
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
—
—
—
5.0
10
20
—
—
—
0.005
0.010
0.015
5.0
10
20
—
—
—
150
300
600
µAdc
IT
5.0
10
15
Vin = 0 or VDD
Input Voltage
“0” Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
“1” Level
VIH
(VO = 0.5 or 4.5 Vdc)
(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
Output Drive Current
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
Vdc
Vdc
IOH
Source
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Sink
Total Supply Current**†
(Dynamic plus Quiescent,
Per Package)
(CL = 50 pF on all outputs, all
buffers switching)
mAdc
IT = (1.5 µA/kHz) f + IDD
IT = (3.0 µA/kHz) f + IDD
IT = (4.5 µA/kHz) f + IDD
µAdc
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.004.
MOTOROLA CMOS LOGIC DATA
MC14099B MC14599B
247
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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)
VDD
Vdc
Min
Typ #
Max
5.0
10
15
—
—
—
100
50
40
200
100
80
5.0
10
15
—
—
—
200
75
50
400
150
100
Write Disable to Output Q
5.0
10
15
—
—
—
200
80
60
400
160
120
ns
Reset to Output Q
5.0
10
15
—
—
—
175
80
65
350
160
130
ns
CE to Output Q (MC14599B only)
5.0
10
15
—
—
—
225
100
75
450
200
150
ns
5.0
10
15
—
—
—
200
80
65
400
160
130
5.0
10
15
—
—
—
200
90
75
400
180
150
5.0
10
15
150
75
50
75
40
25
—
—
—
5.0
10
15
320
160
120
160
80
60
—
—
—
5.0
10
15
100
50
35
50
25
20
—
—
—
5.0
10
15
150
75
50
75
40
25
—
—
—
Characteristic
Symbol
Output Rise and Fall Time
tTLH, tTHL = (1.35 ns/pF) CL + 32 ns
tTLH, tTHL = (0.6 ns/pF) CL + 20 ns
tTLH, tTHL = (0.4 ns/pF) CL + 20 ns
tTLH,
tTHL
Propagation Delay Time
Data to Output Q
tPHL,
tPLH
Propagation Delay Time, MC14599B only
Chip Enable, Write/Read to Data
tPHL,
tPLH
Address to Data
Pulse Widths
Reset
tw(H)
tw(L)
Write Disable
Unit
ns
ns
ns
ns
ns
ns
Set Up Time
Data to Write Disable
tsu
ns
Hold Time
Write Disable to Data
th
Set Up Time
Address to Write Disable
tsu
5.0
10
15
100
80
40
45
30
10
—
—
—
ns
Removal Time
Write Disable to Address
trem
5.0
10
15
0
0
0
– 80
– 40
– 40
—
—
—
ns
ns
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
MC14099B MC14599B
248
MOTOROLA CMOS LOGIC DATA
MC14099B
FUNCTION DIAGRAM
RESET 2
9 Q0
DATA 3
WRITE
4
DISABLE
EACH LATCH
TO
OTHER
LATCHES
ZERO
SELECT
10 Q1
A0 5
11 Q2
12 Q3
ADDRESS
DECODER
A1 6
13 Q4
OTHER LATCHES
14 Q5
15 Q6
A2 7
(M.S.B.)
1 Q7
TRUTH TABLE
Write
Disable
Reset
Addressed
Latch
Unaddressed
Latches
0
0
Data
Qn*
0
1
Data
Reset†
1
0
Qn*
Qn*
1
1
Reset
Reset
CAUTION: To avoid unintentional data changes in the latches, Write
Disable must be active (high) during transitions on the
address inputs A0, A1, and A2.
* Qn is previous state of latch.
†Reset to zero state.
SWITCHING WAVEFORMS
VDD
DATA OR
WRITE DISABLE
50%
VSS
VDD
tPLH
OUTPUT Q
tPHL
ADDRESS
90%
50%
10%
50%
VSS
tsu
tw(L)
trem
VDD
tTLH
tTHL
WRITE
DISABLE
50%
VSS
tw(H)
tsu
VDD
RESET
50%
VDD
DATA
VSS
th
50%
VSS
tPHL
OUTPUT Q
MOTOROLA CMOS LOGIC DATA
MC14099B MC14599B
249
MC14599B
FUNCTION DIAGRAM
RESET 2
11 Q0
DATA 3
VDD
TO
OTHER
LATCHES
VSS
EACH LATCH
ZERO
SELECT
CHIP
8
ENABLE
WRITE/READ 10
WRITE
4
DISABLE
12 Q1
A0 5
13 Q2
14 Q3
ADDRESS
DECODER
A1 6
OTHER LATCHES
15 Q4
16 Q5
17 Q6
A2 7
(M.S.B.)
1 Q7
TRUTH TABLE
Chip
Enable
Write/Read
Write
Disable
Reset
Addressed
Latch
Other
Latches
Data
Pin
0
X
X
0
*
*
Z
1
1
0
0
Data
*
Input
1
1
1
0
*
*
Z
1
0
X
0
*
*
Qn
X
X
X
1
0
0
Z/0
X = Don’t care.
* = No change in state of latch.
Z = High impedance.
Qn = State of addressed latch.
CAUTION: To avoid unintentional data changes in the latches, Write Disable must be active (high) during transitions on
the address inputs A0, A1, and A2.
MC14099B MC14599B
250
MOTOROLA CMOS LOGIC DATA
MC14599B
SWITCHING WAVEFORMS
DATA WRITE
50%
Q0
Q7
tPHL
tTLH
90%
10%
tPHL
90%
10%
tTHL
tPLH
tPLH
VDD
RESET
VSS
tw(H)
VDD
CE
VSS
VDD
50%
A2, A1, A0
VSS
VDD
DATA
50%
VSS
tsu
tw(L)
trem
tsu
90%
WRITE DISABLE
10%
50%
10%
20 ns
th
50%
VDD
VSS
20 ns
DATA READ
VDD
W/R
ÇÇÇÇÇÇÇ
ÇÇÇÇÇÇÇ
ÇÇÇÇÇÇÇ
ÇÇÇÇÇÇÇ
50%
tPLH,
tPHL
CE
DATA
VSS
VDD
VSS
50%
1
tPLH,
tPHL
VDD
VSS
VDD
A2, A1, A0
VSS
NOTE: 1. Invalid Data Output
2. Reset in LOW State
MOTOROLA CMOS LOGIC DATA
MC14099B MC14599B
251
OUTLINE DIMENSIONS
L SUFFIX
CERAMIC DIP PACKAGE
CASE 620–10
ISSUE V
–A–
16
9
1
8
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
–B–
C
L
DIM
A
B
C
D
E
F
G
H
K
L
M
N
–T–
K
N
SEATING
PLANE
M
E
F
J
G
D
16 PL
0.25 (0.010)
16 PL
0.25 (0.010)
M
T A
T B
M
S
INCHES
MIN
MAX
0.750
0.785
0.240
0.295
–––
0.200
0.015
0.020
0.050 BSC
0.055
0.065
0.100 BSC
0.008
0.015
0.125
0.170
0.300 BSC
0_
15 _
0.020
0.040
MILLIMETERS
MIN
MAX
19.05
19.93
6.10
7.49
–––
5.08
0.39
0.50
1.27 BSC
1.40
1.65
2.54 BSC
0.21
0.38
3.18
4.31
7.62 BSC
0_
15 _
0.51
1.01
S
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648–08
ISSUE R
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
–A–
16
9
1
8
B
F
C
L
S
–T–
SEATING
PLANE
K
H
G
D
16 PL
0.25 (0.010)
MC14099B MC14599B
252
J
M
T A
M
M
DIM
A
B
C
D
F
G
H
J
K
L
M
S
INCHES
MIN
MAX
0.740
0.770
0.250
0.270
0.145
0.175
0.015
0.021
0.040
0.70
0.100 BSC
0.050 BSC
0.008
0.015
0.110
0.130
0.295
0.305
0_
10 _
0.020
0.040
MILLIMETERS
MIN
MAX
18.80
19.55
6.35
6.85
3.69
4.44
0.39
0.53
1.02
1.77
2.54 BSC
1.27 BSC
0.21
0.38
2.80
3.30
7.50
7.74
0_
10 _
0.51
1.01
MOTOROLA CMOS LOGIC DATA
OUTLINE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
–A–
16
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
9
–B–
1
P
8 PL
0.25 (0.010)
8
M
B
S
G
R
K
F
X 45 _
C
–T–
SEATING
PLANE
J
M
D
16 PL
0.25 (0.010)
T B
M
A
S
S
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
9.80
10.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.386
0.393
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0_
7_
0.229
0.244
0.010
0.019
L SUFFIX
CERAMIC DIP PACKAGE
CASE 726–04
ISSUE G
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F FOR FULL LEADS. HALF
LEADS OPTIONAL AT LEAD POSITIONS 1, 9,
10, AND 18.
–A–
18
10
1
9
–B–
OPTIONAL LEAD
CONFIGURATION (1, 9, 10, 18)
DIM
A
B
C
D
F
G
J
K
L
M
N
L
C
N
–T–
SEATING
PLANE
K
F
M
G
D 18 PL
0.25 (0.010)
M
MOTOROLA CMOS LOGIC DATA
T A
S
J 18 PL
0.25 (0.010)
M
T B
INCHES
MIN
MAX
0.880
0.910
0.240
0.295
–––
0.200
0.015
0.021
0.055
0.070
0.100 BSC
0.008
0.012
0.125
0.170
0.300 BSC
0_
15 _
0.020
0.040
MILLIMETERS
MIN
MAX
22.35
23.11
6.10
7.49
–––
5.08
0.38
0.53
1.40
1.78
2.54 BSC
0.20
0.30
3.18
4.32
7.62 BSC
0_
15_
0.51
1.02
S
MC14099B MC14599B
253
P SUFFIX
PLASTIC DIP PACKAGE
CASE 707–02
ISSUE C
18
NOTES:
1. POSITIONAL TOLERANCE OF LEADS (D),
SHALL BE WITHIN 0.25 (0.010) AT MAXIMUM
MATERIAL CONDITION, IN RELATION TO
SEATING PLANE AND EACH OTHER.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
10
B
1
9
A
L
C
N
F
H
D
K
SEATING
PLANE
G
M
J
DIM
A
B
C
D
F
G
H
J
K
L
M
N
MILLIMETERS
MIN
MAX
22.22
23.24
6.10
6.60
3.56
4.57
0.36
0.56
1.27
1.78
2.54 BSC
1.02
1.52
0.20
0.30
2.92
3.43
7.62 BSC
0_
15_
0.51
1.02
INCHES
MIN
MAX
0.875
0.915
0.240
0.260
0.140
0.180
0.014
0.022
0.050
0.070
0.100 BSC
0.040
0.060
0.008
0.012
0.115
0.135
0.300 BSC
0_
15 _
0.020
0.040
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MC14099B MC14599B
254
◊
*MC14099B/D*
MOTOROLA CMOS LOGIC
DATA
MC14099B/D