SEMICONDUCTOR TECHNICAL DATA
" ! L SUFFIX
CERAMIC
CASE 620
The MC14076B 4–Bit Register consists of four D–type flip–flops operating
synchronously from a common clock. OR gated output–disable inputs force
the outputs into a high–impedance state for use in bus organized systems.
OR gated data–disable inputs cause the Q outputs to be fed back to the D
inputs of the flip–flops. Thus they are inhibited from changing state while the
clocking process remains undisturbed. An asynchronous master root is
provided to clear all four flip–flops simultaneously independent of the clock
or disable inputs.
• Three–State Outputs with Gated Control Lines
• Fully Independent Clock Allows Unrestricted Operation for the Two
Modes: Parallel Load and Do Nothing
• Asynchronous Master Reset
• Four Bus Buffer Registers
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Capable of Driving Two Low–Power TTL Loads or One Low–Power
Schottky TTL Load Over the Rated Temperature Range
P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
CASE 751B
ORDERING INFORMATION
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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
Plastic
Ceramic
SOIC
TA = – 55° to 125°C for all packages.
MAXIMUM RATINGS* (Voltages Referenced to VSS)
Symbol
VDD
Parameter
Value
Unit
– 0.5 to + 18.0
V
– 0.5 to VDD + 0.5
V
DC Supply Voltage
Vin, Vout
Input or Output Voltage (DC or Transient)
Iin, Iout
Input or Output Current (DC or Transient),
per Pin
± 10
mA
PD
Power Dissipation, per Package†
500
mW
Tstg
Storage Temperature
– 65 to + 150
_C
260
_C
TL
Lead Temperature (8–Second Soldering)
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C
BLOCK DIAGRAM
15
14
13
12
11
10
9
7
2
1
Q0
3
Q1
4
DATA
DISABLE
Q2
5
CLOCK
B OUTPUT
A DISABLE
Q3
6
RESET
D0
D1
D2
D3
B
A
VDD = PIN 16
VSS = PIN 8
FUNCTION TABLE
Inputs
Data Disable
Reset
Clock
A
B
Data
D
Output
Q
1
X
X
X
X
0
0
0
X
X
X
Qn
0
1
X
X
Qn
0
X
1
X
Qn
0
0
0
0
0
0
0
0
1
1
When either output disable A or B (or both) is (are) high the
output is disabled to the high–impedance state; however
sequential operation of the flip–flops is not affected.
X = Don’t Care.
REV 3
1/94
MOTOROLA
Motorola, Inc. 1995
CMOS LOGIC DATA
MC14076B
1
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ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Characteristic
Output Voltage
Vin = VDD or 0
Symbol
– 55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
“0” Level
VOL
5.0
10
15
—
—
—
0.05
0.05
0.05
—
—
—
0
0
0
0.05
0.05
0.05
—
—
—
0.05
0.05
0.05
Vdc
“1” Level
VOH
5.0
10
15
4.95
9.95
14.95
—
—
—
4.95
9.95
14.95
5.0
10
15
—
—
—
4.95
9.95
14.95
—
—
—
Vdc
5.0
10
15
—
—
—
1.5
3.0
4.0
—
—
—
2.25
4.50
6.75
1.5
3.0
4.0
—
—
—
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
—
—
—
3.5
7.0
11
2.75
5.50
8.25
—
—
—
3.5
7.0
11
—
—
—
5.0
5.0
10
15
– 3.0
– 0.64
– 1.6
– 4.2
—
—
—
—
– 2.4
– 0.51
– 1.3
– 3.4
– 4.2
– 0.88
– 2.25
– 8.8
—
—
—
—
– 1.7
– 0.36
– 0.9
– 2.4
—
—
—
—
IOL
5.0
10
15
0.64
1.6
4.2
—
—
—
0.51
1.3
3.4
0.88
2.25
8.8
—
—
—
0.36
0.9
2.4
—
—
—
mAdc
Input Current
Iin
15
—
± 0.1
—
± 0.00001
± 0.1
—
± 1.0
µAdc
Input Capacitance
(Vin = 0)
Cin
—
—
—
—
5.0
7.5
—
—
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
—
—
—
5.0
10
20
—
—
—
0.005
0.010
0.015
5.0
10
20
—
—
—
150
300
600
µAdc
Total Supply Current**†
(Dynamic plus Quiescent,
Per Package)
(CL = 50 pF on all outputs, all
buffers switching)
IT
5.0
10
15
Three–State Leakage Current
ITL
15
Vin = 0 or VDD
Input Voltage
“0” Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
“1” Level
VIH
(VO = 0.5 or 4.5 Vdc)
(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
Output Drive Current
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
Vdc
Vdc
IOH
Source
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Sink
mAdc
IT = (0.75 µA/kHz) f + IDD
IT = (1.50 µA/kHz) f + IDD
IT = (2.25 µA/kHz) f + IDD
—
± 0.1
—
± 0.0001
± 0.1
µAdc
—
± 3.0
µAdc
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.002.
MC14076B
2
MOTOROLA CMOS LOGIC DATA
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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
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SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)
Characteristic
Symbol
Output Rise and Fall Time
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns
tTLH, tTHL
Propagation Delay Time
Clock to Q
tPLH, tPHL = (1.7 ns/pF) CL + 215 ns
tPLH, tPHL = (0.66 ns/pF) CL + 92 ns
tPLH, tPHL = (0.5 ns/pF) CL + 65 ns
tPLH, tPHL
Reset to Q
tPLH, tPHL = (1.7 ns/pF) CL + 215 ns
tPLH, tPHL = (0.66 ns/pF) CL + 92 ns
tPLH, tPHL = (0.5 ns/pF) CL + 65 ns
VDD
Vdc
Min
Typ #
Max
5.0
10
15
—
—
—
100
50
40
200
100
80
Unit
ns
ns
5.0
10
15
—
—
—
300
125
90
600
250
180
5.0
10
15
—
—
—
300
125
90
600
250
180
3–State Propagation Delay, Output “1” or “0”
to High Impedance
tPHZ, tPLZ
5.0
10
15
—
—
—
150
60
45
300
120
90
ns
3–State Propagation Delay, High Impedance
to “1” or “0” Level
tPZH, tPZL
5.0
10
15
—
—
—
200
80
60
400
160
120
ns
Clock Pulse Width
tWH
5.0
10
15
260
110
80
130
55
40
—
—
—
ns
Reset Pulse Width
tWH
5.0
10
15
370
150
110
185
75
55
—
—
—
ns
Data Setup Time
tsu
5.0
10
15
30
10
4
15
5
2
—
—
—
ns
Data Hold Time
th
5.0
10
15
130
60
50
65
30
25
—
—
—
ns
Data Disable Setup Time
tsu
5.0
10
15
220
80
50
110
40
25
—
—
—
ns
tTLH, tTHL
5.0
10
15
—
—
—
—
—
—
15
5
4
µs
fcl
5.0
10
15
—
—
—
3.6
9.0
12
1.8
4.5
6.0
MHz
Clock Pulse Rise and Fall Time
Clock Pulse Frequency
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However,
precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance
circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must
be left open.
MOTOROLA CMOS LOGIC DATA
MC14076B
3
20 ns
D
INPUT RISE AND FALL 20 ns
90%
50%
10%
th
tsu
INPUT
INFORMATION
tsu
OUTPUT
DISABLE
A OR B
th
90%
10%
tWL
fcl
90%
OUTPUT
ANY Q
OUTPUT
10%
tPHZ
90%
ANY Q
OUTPUT
tTHL
OUTPUTS
DISCONNECTED
VOH
RESET = 0
DATA DISABLE A AND B = 0
OUTPUT DISABLE A AND B = 0
OTHER
INPUTS
OUTPUT
DISABLE
A OR B
Figure 1. Timing Diagram
tPZH
10%
OUTPUTS
CONNECTED
VOL
tPZL
90%
ANY Q
OUTPUT
RL = 1 kΩ
50%
10%
tTLH
VSS
tPHL
tPLH
Q
VDD
VDD
10%
tPLZ
20 ns
50%
tWH
50%
VDD
VSS
20 ns
90%
50%
CL
Figure 2. Three–State Propagation Delay
Waveshape and Circuit
OUTPUT
DISABLE
D
C
DATA DISABLE A 9
DATA DISABLE B 10
D1 13
D
C
CLOCK
PIN ASSIGNMENT
1
2
D0 14
VOH
≈ 2.5 V @ VDD = 5 V,
10 V, AND 15 V
≈ 2 V @ VDD = 5 V
≈ 6 V @ VDD = 10 V
≈ 10 V @ VDD = 15 V
VOL
OUTPUTS
CONNECTED
VDD FOR tPLZ AND tPZL
VSS FOR tPHZ AND tPZH
MC14076B
EQUIVALENT
FUNCTIONAL BLOCK DIAGRAM
OUTPUT DISABLE A
OUTPUT DISABLE B
VSS
Q
R Q
3 Q0
Q
R Q
{B
1
16
VDD
2
15
R
Q0
3
14
D0
Q1
4
13
D1
Q2
5
12
D2
Q3
6
11
D3
C
7
10
B
VSS
8
9
A
A
} DATA
DISABLE
4 Q1
7
D2 12
D3 11
D
Q
C
R Q
D
Q
C
R Q
5 Q2
6 Q3
RESET 15
MC14076B
4
MOTOROLA CMOS LOGIC DATA
OUTLINE DIMENSIONS
L SUFFIX
CERAMIC DIP PACKAGE
CASE 620–10
ISSUE V
–A–
16
9
1
8
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
–B–
C
L
DIM
A
B
C
D
E
F
G
H
K
L
M
N
–T–
K
N
SEATING
PLANE
M
E
F
J
G
D
16 PL
0.25 (0.010)
16 PL
0.25 (0.010)
M
T A
T B
M
S
INCHES
MIN
MAX
0.750
0.785
0.240
0.295
–––
0.200
0.015
0.020
0.050 BSC
0.055
0.065
0.100 BSC
0.008
0.015
0.125
0.170
0.300 BSC
0_
15 _
0.020
0.040
MILLIMETERS
MIN
MAX
19.05
19.93
6.10
7.49
–––
5.08
0.39
0.50
1.27 BSC
1.40
1.65
2.54 BSC
0.21
0.38
3.18
4.31
7.62 BSC
0_
15 _
0.51
1.01
S
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648–08
ISSUE R
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
–A–
16
9
1
8
B
F
C
L
S
–T–
SEATING
PLANE
K
H
G
D
J
16 PL
0.25 (0.010)
MOTOROLA CMOS LOGIC DATA
M
T A
M
M
DIM
A
B
C
D
F
G
H
J
K
L
M
S
INCHES
MIN
MAX
0.740
0.770
0.250
0.270
0.145
0.175
0.015
0.021
0.040
0.70
0.100 BSC
0.050 BSC
0.008
0.015
0.110
0.130
0.295
0.305
0_
10 _
0.020
0.040
MILLIMETERS
MIN
MAX
18.80
19.55
6.35
6.85
3.69
4.44
0.39
0.53
1.02
1.77
2.54 BSC
1.27 BSC
0.21
0.38
2.80
3.30
7.50
7.74
0_
10 _
0.51
1.01
MC14076B
5
OUTLINE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
–A–
16
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
9
–B–
1
P
8 PL
0.25 (0.010)
8
M
B
S
G
R
K
F
X 45 _
C
–T–
SEATING
PLANE
M
D
16 PL
0.25 (0.010)
M
T B
S
A
S
J
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
9.80
10.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.386
0.393
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0_
7_
0.229
0.244
0.010
0.019
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MC14076B
6
◊
*MC14076B/D*
MOTOROLA CMOS LOGIC
DATA
MC14076B/D