MCP3426/7/8 16-Bit, Multi-Channel ΔΣ Analog-to-Digital Converter with I2C™ Interface and On-Board Reference Features Description • 16-bit ΔΣ ADC with Differential Inputs: - 2 channels: MCP3426 and MCP3427 - 4 channels: MCP3428 • Differential Input Full Scale Range: -VREF to +VREF • Self Calibration of Internal Offset and Gain per Each Conversion • On-Board Voltage Reference (VREF): - Accuracy: 2.048V ± 0.05% - Drift: 15 ppm/°C • On-Board Programmable Gain Amplifier (PGA): - Gains of 1,2, 4 or 8 • INL: 10 ppm of Full Scale Range • Programmable Data Rate Options: - 15 SPS (16 bits) - 60 SPS (14 bits) - 240 SPS (12 bits) • One-Shot or Continuous Conversion Options • Low Current Consumption (VDD= 3V): - Continuous Conversion: 135 µA typical - One-Shot Conversion with 1 SPS: - 9 µA typical for 16 bit mode - 2.25 µA typical for 14 bit mode - 0.56 µA typical for 12 bit mode • On-Board Oscillator • I2C™ Interface: - Standard, Fast and High Speed Modes - User configurable two external address selection pins for MCP3427 and MCP3428 • Single Supply Operation: 2.7V to 5.5V • Extended Temperature Range: -40°C to +125°C The MCP3426, MCP3427 and MCP3428 devices (MCP3426/7/8) are the low noise and high accuracy 16 Bit Delta-Sigma Analog-to-Digital (ΔΣ A/D) Converter family members of the MCP342X series from Microchip Technology Inc. These devices can convert analog inputs to digital codes with up to 16 bits of resolution. Typical Applications • Portable Instrumentation and Consumer Goods • Temperature Sensing with RTD, Thermistor, and Thermocouple • Bridge Sensing for Pressure, Strain, and Force • Weigh Scales and Battery Fuel Gauges • Factory Automation Equipment © 2009 Microchip Technology Inc. The MCP3426 and MCP3427 devices have two differential input channels and the MCP3428 has four differential input channels. All electrical properties of these three devices are the same except the differences in the number of input channels and I2C address bit selection options. These devices can output analog-to-digital conversion results at rates of 15 (16-bit mode), 60 (14-bit mode), or 240 (12-bit mode) samples per second depending on the user controllable configuration bit settings using the two-wire I2C serial interface. During each conversion, the device calibrates offset and gain errors automatically. This provides accurate conversion results from conversion to conversion over variations in temperature and power supply fluctuation. The device has an on-board 2.048V reference voltage, which enables an input range of ± 2.048V differentially (full scale range = 4.096/PGA). The user can select the gain of the on-board programmable gain amplifier (PGA) using the configuration register bits (gain of x1, x2, x4, or x8). This allows the MCP3426/7/8 devices to convert a very weak input signal with high resolution. The MCP3426/7/8 devices have two conversion modes: (a) One-Shot Conversion mode and (b) Continuous Conversion mode. In the One-Shot conversion mode, the device performs a single conversion and enters a low current standby (shutdown) mode automatically until it receives another conversion command. This reduces current consumption greatly during idle periods. In continuous conversion mode, the conversion takes place continuously at the configured conversion speed. The device updates its output buffer with the most recent conversion data. The devices operate from a single 2.7V to 5.5V power supply and have a two-wire I2C compatible serial interface for a standard (100 kHz), fast (400 kHz), or high-speed (3.4 MHz) mode. DS22226A-page 1 MCP3426/7/8 The I2C address bits for the MCP3427 and MCP3428 are selected by using two external I2C address selection pins (Adr0 and Adr1). The user can configure the device to one of eight available addresses by connecting these two address selection pins to VDD, VSS or float. The I2C address bits of the MCP3426 are programmed at the factory during production. The MCP3426 is available in 8-pin SOIC, DFN, and MSOP packages. The MCP3427 is available in 10-pin DFN, and MSOP packages. The MCP3428 is available in 14-pin SOIC and TSSOP packages. Package Types MSOP, SOIC SDA 4 CH1+ 1 CH1- 2 8 CH27 CH2+ 6 VSS 5 SCL VSS CH2+ 3 4 CH2- 5 CH1- 2 VDD 3 EP 9 SDA 4 CH1+ 1 14 CH4- 9 CH1- 13 CH4+ 12 CH3- Adr0 8 SCL 7 SDA 6 VDD 8 CH2- CH1+ 1 7 CH2+ CH1- 2 2 CH2+ 3 CH2- 4 VSS 5 MCP3427 3x3 DFN * MCP3426 2x3 DFN * CH1+ 1 10 Adr1 MCP3428 CH1- 2 VDD 3 SOIC, TSSOP MCP3427 MCP3426 CH1+ 1 MSOP 11 CH3+ 10 Adr1 VDD 6 9 Adr0 SDA 7 8 SCL 10 Adr1 EP 11 9 Adr0 6 VSS VSS 3 5 SCL CH2+ 4 8 SCL 7 SDA CH2- 5 6 VDD * Includes Exposed Thermal Pad (EP); see Table 3-1. MCP3426 Functional Block Diagram VDD VSS Voltage Reference (2.048V) MCP3426 VREF CH1+ CH2+ CH2- MUX CH1- SCL PGA ΔΣ ADC Converter I2C Interface SDA Gain = 1, 2, 4, or 8 Clock Oscillator DS22226A-page 2 © 2009 Microchip Technology Inc. MCP3426/7/8 MCP3427 Functional Block Diagram VSS VDD MCP3427 Adr1 Voltage Reference (2.048V) Adr0 VREF CH1CH2+ MUX CH1+ CH2- ΔΣ ADC Converter PGA I2C SCL Interface SDA Gain = 1, 2, 4, or 8 Clock Oscillator MCP3428 Functional Block Diagram VSS VDD MCP3428 CH1+ Adr1 Voltage Reference (2.048V) CH1- Adr0 VREF CH2- MUX CH2+ PGA ΔΣ ADC Converter CH3+ CH3CH4+ I2C Interface SCL SDA Gain = 1, 2, 4, or 8 Clock Oscillator CH4- © 2009 Microchip Technology Inc. DS22226A-page 3 MCP3426/7/8 NOTES: DS22226A-page 4 © 2009 Microchip Technology Inc. MCP3426/7/8 1.0 ELECTRICAL CHARACTERISTICS †Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Absolute Maximum Ratings† VDD...................................................................................7.0V All inputs and outputs ............. ..........VSS –0.4V to VDD+0.4V Differential Input Voltage ...................................... |VDD - VSS| Output Short Circuit Current ................................ Continuous Current at Input Pins ....................................................±2 mA Current at Output and Supply Pins ............................±10 mA Storage Temperature ....................................-65°C to +150°C Ambient Temp. with power applied ...............-55°C to +125°C ESD protection on all pins ................ ≥ 6 kV HBM, ≥ 400V MM Maximum Junction Temperature (TJ). .........................+150°C ELECTRICAL CHARACTERISTICS Electrical Specifications: Unless otherwise specified, all parameters apply for TA = -40°C to +85°C, VDD = +5.0V, VSS = 0V, CHn+ = CHn- = VREF/2, VINCOM = VREF /2. All ppm units use 2*VREF as differential full scale range. Parameters Sym Min Typ Max Units FSR — ±2.048/PGA — V Conditions Analog Inputs Differential Full Scale Input Voltage Range VIN = [CHn+ - CHn-] VSS-0.3 — VDD+0.3 V Differential Input Impedance ZIND (f) — 2.25/PGA — MΩ During normal mode operation (Note 2) Common Mode input Impedance ZINC (f) — 25 — MΩ PGA = 1, 2, 4, 8 12 — — Bits DR = 240 SPS 14 — — Bits DR = 60 SPS 16 — — Bits DR = 15 SPS 176 240 328 SPS 12 bits mode Maximum Input Voltage Range (Note 1) System Performance Resolution and No Missing Codes (Effective Number of Bits) (Note 3) Data Rate (Note 4) DR 44 60 82 SPS 14 bits mode 11 15 20.5 SPS 16 bits mode — 2.5 — µVRMS TA = +25°C, DR =15 SPS, PGA = 1, VIN+ = VIN- = GND INL — 10 — ppm of FSR DR = 15 SPS (Note 5) VREF Output Noise Integral Non-Linearity — 2.048 — V Gain Error (Note 6) — 0.1 — % PGA = 1, DR = 15 SPS PGA Gain Error Match (Note 6) — 0.1 — % Between any 2 PGA settings Gain Error Drift (Note 6) — 15 — ppm/°C Internal Reference Voltage PGA=1, DR=15 SPS Note 1: Any input voltage below or greater than this voltage causes leakage current through the ESD diodes at the input pins. This parameter is ensured by characterization and not 100% tested. 2: This input impedance is due to 3.2 pF internal input sampling capacitor. 3: This parameter is ensured by design and not 100% tested. 4: The total conversion speed includes auto-calibration of offset and gain. 5: INL is the difference between the endpoints line and the measured code at the center of the quantization band. 6: Includes all errors from on-board PGA and VREF. 7: This parameter is ensured by characterization and not 100% tested. 8: MCP3427 and MCP3428 only. 9: Addr_Float voltage is applied at address pin. 10: No voltage is applied at address pin (left “floating”). © 2009 Microchip Technology Inc. DS22226A-page 5 MCP3426/7/8 ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise specified, all parameters apply for TA = -40°C to +85°C, VDD = +5.0V, VSS = 0V, CHn+ = CHn- = VREF/2, VINCOM = VREF /2. All ppm units use 2*VREF as differential full scale range. Parameters Offset Error Sym Min Typ Max Units VOS — 30 — µV Conditions PGA = 1 DR = 15 SPS Offset Drift vs. Temperature — 50 — nV/°C Common-Mode Rejection — 105 — dB at DC and PGA =1, — 110 — dB at DC and PGA =8, TA = +25°C Gain vs. VDD — 5 — ppm/V TA = +25°C, VDD = 2.7V to 5.5V, PGA = 1 Power Supply Rejection at DC Input — 100 — dB TA = +25°C, VDD = 2.7V to 5.5V, PGA = 1 Power Requirements Voltage Range VDD 2.7 — 5.5 V Supply Current during Conversion IDDA — 145 180 µA VDD = 5.0V — 135 — µA VDD = 3.0V Supply Current during Standby Mode IDDS — 0.3 1 µA VDD = 5.0V I2C Digital Inputs and Digital Outputs High level input voltage VIH 0.7VDD — VDD V at SDA and SCL pins Low level input voltage VIL — — 0.3VDD V at SDA and SCL pins VOL — — 0.4 V IOL = 3 mA Hysteresis of Schmidt Trigger for inputs (Note 7) VHYST 0.05VDD — — V fSCL = 100 kHz Supply Current when I2C bus line is active IDDB — — 10 µA Device is in standby mode while I2C bus is active Input Leakage Current IILH — — 1 µA VIH = 5.5V IILL -1 — — µA VIL = GND Low level output voltage Logic Status of I2C Address Pins (Note 8) Adr0 and Adr1 Pins Addr_Low VSS — 0.2VDD V The device reads logic low. Adr0 and Adr1 Pins Addr_High 0.75VDD — VDD V The device reads logic high. Adr0 and Adr1 Pins Addr_Float 0.35VDD — 0.6VDD V Read pin voltage if voltage is applied to the address pin. (Note 9) — VDD/2 — CPIN — 4 10 pF Cb — — 400 pF Device outputs float output voltage (VDD/2) on the address pin, if left “floating”. (Note 10) Pin Capacitance and I2C Bus Capacitance Pin capacitance 2 I C Bus Capacitance Note 1: Any input voltage below or greater than this voltage causes leakage current through the ESD diodes at the input pins. This parameter is ensured by characterization and not 100% tested. 2: This input impedance is due to 3.2 pF internal input sampling capacitor. 3: This parameter is ensured by design and not 100% tested. 4: The total conversion speed includes auto-calibration of offset and gain. 5: INL is the difference between the endpoints line and the measured code at the center of the quantization band. 6: Includes all errors from on-board PGA and VREF. 7: This parameter is ensured by characterization and not 100% tested. 8: MCP3427 and MCP3428 only. 9: Addr_Float voltage is applied at address pin. 10: No voltage is applied at address pin (left “floating”). DS22226A-page 6 © 2009 Microchip Technology Inc. MCP3426/7/8 TEMPERATURE CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, TA = -40°C to +125°C, VDD = +5.0V, VSS = 0V. Parameters Sym Min Typ Max Units Specified Temperature Range TA -40 — +85 °C Operating Temperature Range TA -40 — +125 °C Storage Temperature Range TA -65 — +150 °C Thermal Resistance, 8L-DFN (2x3) θJA — 84.5 — °C/W Thermal Resistance, 8L-MSOP θJA — 211 — °C/W Thermal Resistance, 8L-SOIC θJA — 149.5 — °C/W Thermal Resistance, 10L-DFN (3x3) θJA — 57 — °C/W Thermal Resistance, 10L-MSOP θJA — 202 — °C/W Thermal Resistance, 14L-SOIC θJA — 120 — °C/W Thermal Resistance, 14L-TSSOP θJA — 100 — °C/W Conditions Temperature Ranges Thermal Package Resistances © 2009 Microchip Technology Inc. DS22226A-page 7 MCP3426/7/8 NOTES: DS22226A-page 8 © 2009 Microchip Technology Inc. MCP3426/7/8 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. 0.005 12 Output Noise (µV, rms) Integral Nonlinearity (% FSR) Note: Unless otherwise indicated, TA = -40°C to +85°C, VDD = +5.0V, VSS = 0V, CHn+ = CHn- = VREF/2, VINCOM = VREF/2. 0.004 0.003 PGA = 1 PGA = 4 0.002 PGA = 8 0.001 PGA = 2 0 2.5 3 3.5 4 4.5 5 PGA = 1 10 8 6 PGA = 2 4 PGA = 4 2 0 -100 5.5 PGA = 8 -75 -50 FIGURE 2-1: (VDD). INL vs. Supply Voltage FIGURE 2-4: Voltage. 0.005 0 25 Total Error (mV) 0.003 2.7V 0.002 50 75 100 Output Noise vs. Input 2 0.001 TA = +25°C PGA = 1 1.5 0.004 INL (% FSR) -25 Input Signal (% of FSR) VDD (V) PGA = 8 1 0.5 0 -0.5 PGA = 4 PGA = 2 -1 -1.5 5V 0 -2 -60 -40 -20 0 20 40 60 80 100 120 140 -100 -75 Temperature (oC) FIGURE 2-2: INL vs. Temperature. -50 -25 0 25 50 75 Input Voltage (% of Full-Scale) FIGURE 2-5: 100 Total Error vs. Input Voltage. VDD = 5V Offset Error (µV) 15 PGA = 4 10 PGA = 8 5 0 -5 -10 -15 -20 PGA = 2 PGA = 1 Gain Error (% of FSR) 0.2 20 0.1 PGA = 8 0 PGA = 1 -0.1 -0.2 -0.3 -0.4 PGA = 2 -0.5 PGA = 4 -0.6 -25 -40 -20 FIGURE 2-3: Temperature. 0 20 40 60 80 100 120 140 Temperature (oC) Offset Error vs. © 2009 Microchip Technology Inc. -60 -40 -20 FIGURE 2-6: 0 20 40 60 80 100 120 140 Temperature (°C) Gain Error vs. Temperature. DS22226A-page 9 MCP3426/7/8 Note: Unless otherwise indicated, TA = -40°C to +85°C, VDD = +5.0V, VSS = 0V, CHn+ = CHn- = VREF/2, VINCOM = VREF/2. 5 180 V DD = 5.5V IDDA (µA) 160 140 120 VDD = 2.7V 100 V DD = 5.0V 80 Oscillator Drift (%) 200 60 4 3 2 VDD = 2.7V 1 0 VDD = 5.0V -1 -60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 0 Temperature (°C) IDDA vs. Temperature. 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 VDD = 5.5V VDD = 5.0V VDD = 2.7V -60 -40 -20 0 20 40 60 FIGURE 2-10: Temperature. Magnitude (dB) IDDS (µA) FIGURE 2-7: 40 60 80 100 120 140 80 100 120 140 IDDS vs. Temperature. Oscillator Drift vs. 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 Data Rate = 15 SPS 0.1 Temperature (°C) FIGURE 2-8: 20 Temperature (°C) 1 10 100 1k 1000 10k 10000 Input Signal Frequency (Hz) FIGURE 2-11: Frequency Response. 14 12 VDD = 5.5V VDD = 5.0V IDDB (µA) 10 8 6 VDD = 4.5V 4 2 VDD = 2.7V 0 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C) FIGURE 2-9: DS22226A-page 10 IDDB vs. Temperature. © 2009 Microchip Technology Inc. MCP3426/7/8 3.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 3-1. TABLE 3-1: PIN FUNCTION TABLE MCP3426 MCP3427 MCP3428 MSOP, SOIC DFN MSOP SOIC, TSSOP Sym DFN Function 1 1 1 1 1 CH1+ Positive Differential Analog Input Pin of Channel 1 2 2 2 2 2 CH1- Negative Differential Analog Input Pin of Channel 1 7 7 4 4 3 CH2+ Positive Differential Analog Input Pin of Channel 2 8 8 5 5 4 CH2- Negative Differential Analog Input Pin of Channel 2 6 6 3 3 5 VSS Ground Pin 3 3 6 6 6 VDD Positive Supply Voltage Pin 4 4 7 7 7 SDA Bidirectional Serial Data Pin of the I2C Interface 5 5 8 8 8 SCL Serial Clock Pin of the I2C Interface — — 9 9 9 Adr0 I2C Address Selection Pin. See Section 5.3.2. — — 10 10 10 Adr1 I2C Address Selection Pin. See Section 5.3.2. — — — — 11 CH3+ Positive Differential Analog Input Pin of Channel 3 — — — — 12 CH3- Negative Differential Analog Input Pin of Channel 3 — — — — 13 CH4+ Positive Differential Analog Input Pin of Channel 4 — — — — 14 CH4- Negative Differential Analog Input Pin of Channel 4 9 — 11 — — EP Exposed Thermal Pad (EP); must be connected to VSS 3.1 Analog Inputs (CHn+, CHn-) CHn+ and CHn- are differential input pins for channel n. The user can also connect CHn- pin to VSS for a single-ended operation. See Figure 6-4 for differential and single-ended connection examples. The maximum voltage range on each differential input pin is from VSS-0.3V to VDD+0.3V. Any voltage below or above this range will cause leakage currents through the Electrostatic Discharge (ESD) diodes at the input pins. This ESD current can cause unexpected performance of the device. The input voltage at the input pins should be within the specified operating range defined in Section 1.0 “Electrical Characteristics” and Section 4.0 “Description of Device Operation”. See Section 4.5 “Input Voltage Range” for more details of the input voltage range. 3.2 Supply Voltage (VDD, VSS) VDD is the power supply pin for the device. This pin requires an appropriate bypass ceramic capacitor of about 0.1 µF to ground to attenuate high frequency noise presented in application circuit board. An additional 10 µF capacitor (tantalum) in parallel is also recommended to further attenuate current spike noises. The supply voltage (VDD) must be maintained in the 2.7V to 5.5V range for specified operation. VSS is the ground pin and the current return path of the device. The user must connect the VSS pin to a ground plane through a low impedance connection. If an analog ground path is available in the application PCB (printed circuit board), it is highly recommended that the VSS pin be tied to the analog ground path or isolated within an analog ground plane of the circuit board. Figure 3-1 shows the input structure of the device. The device uses a switched capacitor input stage at the front end. CPIN is the package pin capacitance and typically about 4 pF. D1 and D2 are the ESD diodes. CSAMPLE is the differential input sampling capacitor. © 2009 Microchip Technology Inc. DS22226A-page 11 MCP3426/7/8 VDD RSS D1 VT = 0.6V CPIN D 2 4 pF VT = 0.6V CHn V Sampling Switch SS ILEAKAGE (~ ±1 nA) RS CSAMPLE (3.2 pF) VSS LEGEND V Rss CHn CPIN VT FIGURE 3-1: 3.3 = = = = = Signal Source Source Impedance Analog Input Pin Input Pin Capacitance Threshold Voltage ILEAKAGE SS Rs CSAMPLE D1, D2 = = = = = Leakage Current at Analog Pin Sampling Switch Sampling Switch Resistor Sample Capacitance ESD Protection Diode Equivalent Analog Input Circuit. Serial Clock Pin (SCL) I 2C SCL is the serial clock pin of the interface. The device acts only as a slave and the SCL pin accepts only external serial clocks. The input data from the Master device is shifted into the SDA pin on the rising edges of the SCL clock and output from the slave device occurs at the falling edges of the SCL clock. The SCL pin is an open-drain N-channel driver. Therefore, it needs a pull-up resistor from the VDD line to the SCL Serial pin. Refer to Section 5.3 “I2C Communications” for more details on I2C Serial Interface communication. 3.4 Serial Data Pin (SDA) SDA is the serial data pin of the I2C interface. The SDA pin is used for input and output data. In read mode, the conversion result is read from the SDA pin (output). In write mode, the device configuration bits are written (input) though the SDA pin. The SDA pin is an open-drain N-channel driver. Therefore, it needs a pull-up resistor from the VDD line to the SDA pin. Except for start and stop conditions, the data on the SDA pin must be stable during the high period of the clock. The high or low state of the SDA pin can only change when the clock signal on the SCL pin is low. Refer to Section 5.3 “I2C Serial Communications” for more details on I2C Serial Interface communication. The typical range of the pull-up resistor value for SCL and SDA is from 5 kΩ to 10 kΩ for standard (100 kHz) and fast (400 kHz) modes, and less than 1 kΩ for high speed mode (3.4 MHz). 3.5 Exposed Thermal Pad (EP) There is an internal electrical connection between the Exposed Thermal Pad (EP) and the VSS pin; they must be connected to the same potential on the Printed Circuit Board (PCB). DS22226A-page 12 © 2009 Microchip Technology Inc. MCP3426/7/8 4.0 DESCRIPTION OF DEVICE OPERATION 4.1 General Overview The MCP3426/7/8 devices are differential multi-channel low-power, 16-Bit Delta-Sigma A/D converters with an I2C serial interface. The devices contain an input channel selection multiplexer (mux), a programmable gain amplifier (PGA), an on-board voltage reference (2.048V), and an internal oscillator. When the device powers up (POR is set), it automatically resets the configuration bits to default settings. 4.1.1 • • • • DEVICE DEFAULT SETTINGS ARE: Conversion bit resolution: 12 bits (240 sps) Input channel: Channel 1 PGA gain setting: x1 Continuous conversion Once the device is powered-up, the user can reprogram the configuration bits using I2C serial interface any time. The configuration bits are stored in the volatile memory. 4.1.2 • • • • USER SELECTABLE OPTIONS ARE: Conversion bit resolution: 12, 14, or 16 bits Input channel selection: CH1, CH2, CH3, or CH4. PGA Gain selection: x1, x2, x4, or x8 Continuous or one-shot conversion In the Continuous Conversion mode, the device converts the inputs continuously. While in the One-Shot Conversion mode, the device converts the input one time and stays in the low-power standby mode until it receives another command for a new conversion. During the standby mode, the device consumes less than 1 µA maximum. 4.2 Power-On-Reset (POR) The device contains an internal Power-On-Reset (POR) circuit that monitors power supply voltage (VDD) during operation. This circuit ensures correct device start-up at system power-up and power-down events. The device resets all configuration register bits to default settings as soon as the POR is set. The threshold voltage is set at 2.2V with a tolerance of approximately ±5%. If the supply voltage falls below this threshold, the device will be held in a reset condition. The typical hysteresis value is approximately 200 mV. The POR circuit is shut down during the low-power standby mode. Once a power-up event has occurred, the device requires additional delay time (approximately 300 µs) before a conversion takes place. During this time, all internal analog circuitries are settled before the first conversion occurs. Figure 4-1 illustrates the conditions for power-up and power-down events under typical start-up conditions. VDD 2.2V 2.0V 300 µS Time Reset Start-up FIGURE 4-1: 4.3 Normal Operation Reset POR Operation. Internal Voltage Reference The device contains an on-board 2.048V voltage reference. This reference voltage is for internal use only and not directly measurable. The specification of the reference voltage is part of the device’s gain and drift specifications. Therefore, there is no separate specification for the on-board reference. 4.4 Analog Input Channels The user can select the input channel using the configuration register bits. Each channel can be used for differential or single-ended input. Each input channel has a switched capacitor input structure. The internal sampling capacitor (3.2 pF for PGA = 1) is charged and discharged to process a conversion. The charging and discharging of the input sampling capacitor creates dynamic input currents at each input pin. The current is a function of the differential input voltages, and inversely proportional to the internal sampling capacitance, sampling frequency, and PGA setting. The POR has built-in hysteresis and a timer to give a high degree of immunity to potential ripples and noises on the power supply. A 0.1 µF decoupling capacitor should be mounted as close as possible to the VDD pin for additional transient immunity. © 2009 Microchip Technology Inc. DS22226A-page 13 MCP3426/7/8 4.5 Input Voltage Range The differential (VIN) and common mode voltage (VINCOM) at the input pins without considering PGA setting are defined by: V IN = ( CHn+ ) – ( CHn- ) CHn+ ) + ( CHn- )V INCOM = (---------------------------------------------2 Where: n = nth input channel (n=1, 2, 3, or 4) The input signal levels are amplified by the internal programmable gain amplifier (PGA) at the front end of the ΔΣ modulator. The user needs to consider two conditions for the input voltage range: (a) Differential input voltage range and (b) Absolute maximum input voltage range. 4.5.1 DIFFERENTIAL INPUT VOLTAGE RANGE The device performs conversions using its internal reference voltage (VREF = 2.048V). Therefore, the absolute value of the differential input voltage (VIN), with PGA setting is included, needs to be less than the internal reference voltage. The device will output saturated output codes (all 0s or all 1s except sign bit) if the absolute value of the input voltage (VIN), with PGA setting is included, is greater than the internal reference voltage (VREF = 2.048V). The input full scale voltage range is given by: EQUATION 4-1: – V REF ≤ ( V IN • PGA ) ≤ ( V REF – 1LSB ) Where: VIN = CHn+ - CHn- VREF = 2.048V If the input voltage level is greater than the above limit, the user can use a voltage divider and bring down the input level within the full scale range. See Figure 6-7 for more details of the input voltage divider circuit. 4.5.2 ABSOLUTE MAXIMUM INPUT VOLTAGE RANGE The input voltage at each input pin must be less than the following absolute maximum input voltage limits: • Input voltage < VDD+0.3V • Input voltage > VSS-0.3V Any input voltage outside this range can turn on the input ESD protection diodes, and result in input leakage current, causing conversion errors, or permanently damage the device. DS22226A-page 14 Care must be taken in setting the input voltage ranges so that the input voltage does not exceed the absolute maximum input voltage range. 4.6 Input Impedance The device uses a switched-capacitor input stage using a 3.2 pF sampling capacitor. This capacitor is switched (charged and discharged) at a rate of the sampling frequency that is generated by on-board clock. The differential input impedance varies with the PGA settings. The typical differential input impedance during a normal mode operation is given by: ZIN(f) = 2.25 MΩ /PGA Since the sampling capacitor is only switching to the input pins during a conversion process, the above input impedance is only valid during conversion periods. In a low power standby mode, the above impedance is not presented at the input pins. Therefore, only a leakage current due to ESD diode is presented at the input pins. The conversion accuracy can be affected by the input signal source impedance when any external circuit is connected to the input pins. The source impedance adds to the internal impedance and directly affects the time required to charge the internal sampling capacitor. Therefore, a large input source impedance connected to the input pins can degrade the system performance, such as offset, gain, and Integral Non-Linearity (INL) errors. Ideally, the input source impedance should be zero. This can be achievable by using an operational amplifier with a closed-loop output impedance of tens of ohms. 4.7 Aliasing and Anti-aliasing Filter Aliasing occurs when the input signal contains time-varying signal components with frequency greater than half the sample rate. In the aliasing conditions, the device can output unexpected output codes. For applications that are operating in electrical noise environments, the time-varying signal noise or high frequency interference components can be easily added to the input signals and cause aliasing. Although the device has an internal first order sinc filter, the filter response (Figure 2-11) may not give enough attenuation to all aliasing signal components. To avoid the aliasing, an external anti-aliasing filter, which can be accomplished with a simple RC low-pass filter, is typically used at the input pins. The low-pass filter cuts off the high frequency noise components and provides a band-limited input signal to the input pins. 4.8 Self-Calibration The device performs a self-calibration of offset and gain for each conversion. This provides reliable conversion results from conversion-to-conversion over variations in temperature as well as power supply fluctuations. © 2009 Microchip Technology Inc. MCP3426/7/8 4.9 Digital Output Codes and Conversion to Real Values 4.9.1 DIGITAL OUTPUT CODE FROM DEVICE The digital output code is proportional to the input voltage and PGA settings. The output data format is a binary two’s complement. With this code scheme, the MSB can be considered a sign indicator. When the MSB is a logic ‘0’, the input is positive. When the MSB is a logic ‘1’, the input is negative. The following is an example of the output code: Table 4-1 shows the LSB size of each conversion rate setting. The measured unknown input voltage is obtained by multiplying the output codes with LSB. See the following section for the input voltage calculation using the output codes. TABLE 4-1: Resolution Setting (a) for a negative full scale input voltage: 100...000 Example: (CHn+ - CHn-) •PGA = -2.048V (b) for a zero differential input voltage: 000...000 Example: (CHn+ - CHn-) = 0 (c) for a positive full scale input voltage: 011...111 The output codes will not roll-over even if the input voltage exceeds the maximum input range. In this case, the code will be locked at 0111...11 for all voltages greater than (VREF - 1 LSB)/PGA and 1000...00 for voltages less than -VREF/PGA. Table 4-2 shows an example of output codes of various input levels for 16-bit conversion mode. Table 4-3 shows an example of minimum and maximum output codes for each conversion rate option. The number of output code is given by: EQUATION 4-2: Number of Output Code = ( CHn+ – CHn- ) = ( Maximum Code + 1 ) × PGA × ----------------------------------------2.048V Where: See Table 4-3 for Maximum Code The LSB of the data conversion is given by: EQUATION 4-3: LSB 12 bits 1 mV 14 bits 250 µV 16 bits 62.5 µV TABLE 4-2: EXAMPLE OF OUTPUT CODE FOR 16 BITS (NOTE 1, NOTE 2) Input Voltage: [CHn+ - CHn-] • PGA Example: (CHn+ - CHn-) • PGA = 2.048V The MSB (sign bit) is always transmitted first through the I2C serial data line. The resolution for each conversion is 16, 14, or 12 bits depending on the conversion rate selection bit settings by the user. RESOLUTION SETTINGS VS. LSB Digital Output Code ≥ VREF 0111111111111111 VREF - 1 LSB 0111111111111111 2 LSB 0000000000000010 1 LSB 0000000000000001 0 0000000000000000 -1 LSB 1111111111111111 -2 LSB 1111111111111110 - VREF 1000000000000000 < -VREF 1000000000000000 Note 1: 2: MSB is a sign indicator: 0: Positive input (CHn+ > CHn-) 1: Negative input (CHn+ < CHn-) Output data format is binary two’s complement. TABLE 4-3: MINIMUM AND MAXIMUM OUTPUT CODES (NOTE) Resolution Setting Data Rate 12 240 SPS -2048 2047 14 60 SPS -8192 8191 16 15 SPS -32768 32767 Note: Minimum Code Maximum Code 2N-1 Maximum n-bit code = -1 Minimum n-bit code = -1 x 2N-1 2 × V REF × 2.048V LSB = --------------------- = 2-------------------------N N 2 2 Where: N = Resolution, which is programmed in the Configuration Register: 12, 14, or 16. © 2009 Microchip Technology Inc. DS22226A-page 15 MCP3426/7/8 4.9.2 CONVERTING THE DEVICE OUTPUT CODE TO INPUT SIGNAL VOLTAGE EQUATION 4-4: CONVERTING OUTPUT CODES TO INPUT VOLTAGE When the user gets the digital output codes from the device as described in Section 4.9.1 “Digital output code from device”, the next step is converting the digital output codes to a measured input voltage. Equation 4-4 shows an example of converting the output codes to its corresponding input voltage. If MSB = 0 (Positive Output Code): If the sign indicator bit (MSB) is ‘0’, the input voltage is obtained by multiplying the output code with the LSB and divided by the PGA setting. Where: If the sign indicator bit (MSB) is ‘1’, the output code needs to be converted to two’s complement before multiplied by LSB and divided by the PGA setting. Table 4-4 shows an example of converting the device output codes to input voltage. TABLE 4-4: LSB Input Voltage = (Output Code) • -----------PGA If MSB = 1 (Negative Output Code): LSB Input Voltage = (2 ′ s complement of Output Code) • -----------PGA LSB = See Table 4-1 2’s complement = 1’s complement + 1 EXAMPLE OF CONVERTING OUTPUT CODE TO VOLTAGE (WITH 16 BIT SETTING) Input Voltage [CHn+ - CHn-] • PGA] Digital Output Code MSB ≥ VREF 0111111111111111 0 (214+213+212+211+210+29+28+27+26+25+24+23+22+21+20)x LSB(62.5μV)/PGA = 2.048 (V) for PGA = 1 VREF - 1 LSB 0111111111111111 0 (214+213+212+211+210+29+28+27+26+25+24+23+22+21+20)x LSB(62.5μV)/PGA = 2.048 (V) for PGA = 1 2 LSB 0000000000000010 0 (0+0+0+0+0+0+0+0+0+0+0+0+0+21+0)x LSB(62.5μV)/PGA = 125 (μV) for PGA = 1 1 LSB 0000000000000001 0 (0+0+0+0+0+0+0+0+0+0+0+0+0+0+20)x LSB(62.5μV)/PGA = 62.5 (μV)for PGA = 1 0 0000000000000000 0 (0+0+0+0+0+0+0+0+0+0+0+0+0+0+0)x LSB(62.5μV)/PGA = 0 V (V) for PGA = 1 -1 LSB 1111111111111111 1 -(0+0+0+0+0+0+0+0+0+0+0+0+0+0+20)x LSB(62.5μV)/ PGA = - 62.5 (μV)for PGA = 1 -2 LSB 1111111111111110 1 -(0+0+0+0+0+0+0+0+0+0+0+0+0+21+0)x LSB(62.5μV)/ PGA = - 125 (μV)for PGA = 1 - VREF 1000000000000000 1 -(215+0+0+0+0+0+0+0+0+0+0+0+0+0+0) x LSB(62.5μV)/ PGA = - 2.048 (V) for PGA = 1 ≤ -VREF 1000000000000000 1 -(215+0+0+0+0+0+0+0+0+0+0+0+0+0+0) x LSB(62.5μV)/ PGA = - 2.048 (V) for PGA = 1 Note: Example of Converting Output Codes to Input Voltage MSB = sign bit (1: “-”, 0: “+”) DS22226A-page 16 © 2009 Microchip Technology Inc. MCP3426/7/8 5.0 5.1 USING THE DEVICES Operating Modes The user operates the device by setting up the device configuration register using a write command (see Figure 5-3) and reads the conversion data using a read command (see Figure 5-4 ). The device operates in two modes: (a) Continuous Conversion Mode or (b) One-Shot Conversion Mode (single conversion). This mode selection is made by setting the O/C bit in the Configuration Register. Refer to Section 5.2 “Configuration Register” for more information. 5.1.1 CONTINUOUS CONVERSION MODE (O/C BIT = 1) The device performs a Continuous Conversion if the O/C bit is set to logic “high”. Once the conversion is completed, RDY bit is toggled to ‘0’ and the result is placed at the output data register. The device immediately begins another conversion and overwrites the output data register with the most recent result. The device clears the data ready flag (RDY bit = 0) when the conversion is completed. The device sets the ready flag bit (RDY bit = 1), if the latest conversion result has been read by the Master. • When writing configuration register: - Setting RDY bit in continuous mode does not affect anything. • When reading conversion data: - RDY bit = 0 means the latest conversion result is ready. - RDY bit = 1 means the conversion result is not updated since the last reading. A new conversion is under processing and the RDY bit will be cleared when the new conversion result is ready. © 2009 Microchip Technology Inc. 5.1.2 ONE-SHOT CONVERSION MODE (O/C BIT = 0) Once the One-Shot Conversion (single conversion) Mode is selected, the device performs only one conversion, updates the output data register, clears the data ready flag (RDY = 0), and then enters a low power standby mode. A new One-Shot Conversion is started again when the device receives a new write command with RDY = 1. • When writing configuration register: - The RDY bit needs to be set to begin a new conversion in one-shot mode. • When reading conversion data: - RDY bit = 0 means the latest conversion result is ready. - RDY bit = 1 means the conversion result is not updated since the last reading. A new conversion is under processing and the RDY bit will be cleared when the new conversion is done. This One-Shot Conversion Mode is highly recommended for low power operating applications where the conversion result is needed by request on demand. During the low current standby mode, the device consumes less than 1 µA maximum (or 300 nA typical). For example, if the user collects 16-bit conversion data once a second in One-Shot Conversion mode, the device draws only about onefifteenth of the operating currents for the continuous conversion mode. In this example, the device consumes approximately 9 µA (135 µA / 15 SPS = 9 µA), when the device performs only one conversion per second (1 SPS) in 16-bit conversion mode with 3V power supply. DS22226A-page 17 MCP3426/7/8 5.2 Configuration Register The user can rewrite the configuration byte any time during the device operation. Register 5-1 shows the configuration register bits. The device has an 8-bit wide configuration register to select for: input channel, conversion mode, conversion rate, and PGA gain. This register allows the user to change the operating condition of the device and check the status of the device operation. REGISTER 5-1: CONFIGURATION REGISTER R/W-1 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 RDY C1 C0 O/C S1 S0 G1 G0 1* 0* 0* 1* 0* 0* 0* 0* bit 7 bit 0 * Default Configuration after Power-On Reset Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 x = Bit is unknown RDY: Ready Bit This bit is the data ready flag. In read mode, this bit indicates if the output register has been updated with a latest conversion result. In One-Shot Conversion mode, writing this bit to “1” initiates a new conversion. Reading RDY bit with the read command: 1 = Output register has not been updated. 0 = Output register has been updated with the latest conversion result. Writing RDY bit with the write command: Continuous Conversion mode: No effect One-Shot Conversion mode: 1 = Initiate a new conversion. 0 = No effect. bit 6-5 C1-C0: Channel Selection Bits 00 = Select Channel 1 (Default) 01 = Select Channel 2 10 = Select Channel 3 (MCP3428 only, treated as “00” by the MCP3426/MCP3427) 11 = Select Channel 4 (MCP3428 only, treated as “01” by the MCP3426/MCP3427) bit 4 O/C: Conversion Mode Bit 1 = Continuous Conversion Mode (Default). The device performs data conversions continuously. 0 = One-Shot Conversion Mode. The device performs a single conversion and enters a low power standby mode until it receives another write or read command. bit 3-2 S1-S0: Sample Rate Selection Bit 00 = 240 SPS (12 bits) (Default) 01 = 60 SPS (14 bits) 10 = 15 SPS (16 bits) bit 1-0 G1-G0: PGA Gain Selection Bits 00 = x1 (Default) 01 = x2 10 = x4 11 = x8 DS22226A-page 18 © 2009 Microchip Technology Inc. MCP3426/7/8 If the configuration byte is read repeatedly by clocking continuously after reading the data bytes (i.e., after the 4th byte in the 16-bit conversion mode), the state of the RDY bit indicates whether the device is ready with new conversion result. When the Master finds the RDY bit is cleared, it can send a not-acknowledge (NAK) bit and a stop bit to exit the current read operation and send a new read command for the latest conversion data. Once the conversion data has been read, the ready bit toggles to ‘1’ until the next new conversion data is ready. The conversion data in the output register is overwritten every time a new conversion is completed. Figure 5-3 shows an example of writing configuration register, and Figure 5-4 shows an example of reading conversion data. The user can rewrite the configuration byte any time for a new setting. Table 5-1 and Table 52 show the examples of the configuration bit operation. TABLE 5-1: WRITE CONFIGURATION BITS R/W O/C RDY 0 0 Operation No effect if all other bits remain the same - operation continues with the previous settings. 0 0 0 1 Initiate One-Shot Conversion. 0 1 0 Initiate Continuous Conversion. 0 1 1 Initiate Continuous Conversion. TABLE 5-2: READ CONFIGURATION BITS R/W O/C RDY Operation 1 0 0 New conversion result in OneShot conversion mode has just been read. The RDY bit remains low until set by a new write command. 1 0 1 One-Shot Conversion is in progress. The conversion result is not updated yet. The RDY bit stays high until the current conversion is completed. 1 1 0 New conversion result in Continuous Conversion mode has just been read. The RDY bit changes to high after reading the conversion data. 1 1 1 The conversion result in Continuous Conversion mode was already read. The next new conversion data is not ready. The RDY bit stays high until a new conversion is completed. © 2009 Microchip Technology Inc. 5.3 I2C Serial Communications The device communicates with the Master (microcontroller) through a serial I2C (Inter-Integrated Circuit) interface and support standard (100 kbits/sec), fast (400 kbits/sec) and high-speed (3.4 Mbits/sec) modes. The serial I2C is a bidirectional 2-wire data bus communication protocol using open-drain SCL and SDA lines. The device can only be addressed as a slave. Once addressed, it can receive configuration bits with a write command or transmit the latest conversion results with a read command. The serial clock pin (SCL) is an input only and the serial data pin (SDA) is bidirectional. The Master starts communication by sending a START bit and terminates the communication by sending a STOP bit. In read mode, the device releases the SDA line after receiving NAK and STOP bits. An example of a hardware connection diagram is shown in Figure 6-1. More details of the I2C bus characteristic is described in Section 5.6 “I2C Bus Characteristics”. 5.3.1 I2C DEVICE ADDRESSING The first byte after the START bit is always the address byte of the device, which includes the device code (4 bits), address bits (3 bits), and R/W bit. The device code for the devices is 1101, which is programmed at the factory. The I2C address bits (A2, A1, A0 bits) are as follows: • MCP3426: Programmed at factory • MCP3427 and MCP3428: Progammed by the user. It is determined by the logic status of the two external address selection pins on the user’s application board (Adr0 and Adr1 pins). The Master must know the Adr0 and Adr1 pin conditions before sending read or write command. See Section 5.3.2 “Device Address Bits (A2, A1, A0) and Address Selection Pins (MCP3427 and MCP3428)” for more details Figure 5-1 shows the details of the address byte. The three I2C address bits allow up to eight devices on the same I2C bus line. The (R/W) bit determines if the Master device wants to read the conversion data or write to the Configuration register. If the (R/W) bit is set (read mode), the device outputs the conversion data in the following clocks. If the (R/W) bit is cleared (write mode), the device expects a configuration byte in the following clocks. When the device receives the correct address byte, it outputs an acknowledge bit after the R/W bit. DS22226A-page 19 MCP3426/7/8 Acknowledge bit Start bit Read/Write bit R/W ACK Address It is recommended to issue a General Call Reset or General Call Latch command once after the device has powered up. This will ensure that the device reads the address pins in a stable condition, and avoid latching the address bits while the power supply is ramping up. This might cause inaccurate address pin detection. Address Byte When the address pin is left “floating”: Address Byte: Device Code Address Bits (Note 1) 1 Note 1: 2: 1 A2 A1 A0 MCP3427 and MCP3428: Configured by the user. See Table 5-4 for address bit configurations. MCP3426: Programmed at the factory during production. FIGURE 5-1: 5.3.2 1 0 Address Byte. DEVICE ADDRESS BITS (A2, A1, A0) AND ADDRESS SELECTION PINS (MCP3427 AND MCP3428) The MCP3427 and MCP3428 have two external device address pins (Adr1, Adr0). These pins can be set to a logic high (or tied to VDD), low (or tied to VSS), or left floating (not connected to anything, or tied to VDD/2), These combinations of logic level using the two pins allow eight possible addresses. Table 5-3 shows the device address depending on the logic status of the address selection pins. The device samples the logic status of the Adr0 and Adr1 pins in the following events: (a) Device power-up. (b) General Call Reset (See Section 5.4 “General Call”). (c) General Call Latch (See Section 5.4 “General Call”). The device samples the logic status (address pins) during the above events, and latches the values until a new latch event occurs. During normal operation (after the address pins are latched), the address pins are internally disabled from the rest of the internal circuit. DS22226A-page 20 When the address pin is left “floating”, the address pin momentarily outputs a short pulse with an amplitude of about VDD/2 during the latch event. The device also latches this pin voltage at the same time. If the “floating” pin is connected to a large parasitic capacitance (> 20 pF) or to a long PCB trace, this short floating voltage output can be altered. As a result, the device may not latch the pin correctly. It is strongly recommended to keep the “floating” pin pad as short as possible in the customer application PCB and minimize the parasitic capacitance to the pin as small as possible (< 20 pF). Figure 5-2 shows an example of the Latch voltage output at the address pin when the address pin is left “floating”. The waveform at the Adr0 pin is captured by using an oscilloscope probe with 15 pF of capacitance. The device latches the floating condition immediately after the General Call Latch command. Float waveform (output) at address pin SCL SDA FIGURE 5-2: General Call Latch Command and Voltage Output at Address Pin Left “Floating” (MCP3427 and MCP3428). © 2009 Microchip Technology Inc. MCP3426/7/8 TABLE 5-3: I2C Device Address Bits A1 A0 Adr0 Pin Adr1 Pin 0 0 0 0 (Addr_Low) 0 (Addr_Low) 0 0 1 0 (Addr_Low) Float 0 1 0 0 (Addr_Low) 1 (Addr_High) 1 0 0 1 (Addr_High) 0 (Addr_Low) 1 0 1 1 (Addr_High) Float 1 1 0 1 (Addr_High) 1 (Addr_High) 0 1 1 Float 0 (Addr_Low) 1 1 1 Float 1 (Addr_High) 0 0 0 Float Float 2: 3: WRITING A CONFIGURATION BYTE TO THE DEVICE When the Master sends an address byte with the R/W bit low (R/W = 0), the device expects one configuration byte following the address. Any byte sent after this second byte will be ignored. The user can change the operating mode of the device by writing the configuration register bits. Logic Status of Address Selection Pins A2 Note 1: 5.3.3 ADDRESS BITS VS. ADDRESS SELECTION PINS FOR (MCP3427 AND MCP3428 ONLY) (NOTE 1, 2, 3) If the device receives a write command with a new configuration setting, the device immediately begins a new conversion and updates the conversion data. Float: (a) Leave pin without connecting to anything (left floating), or (b) apply Addr_Float voltage. The user can tie the pins to VSS or VDD: - Tie to VSS for Addr_Low - Tie to VDD for Addr_High See Addr_Low, Addr_High, and Addr_Float parameters in Electrical Characteristics Table. 1 9 1 9 SCL 1 SDA 1 0 Start Bit by Master 1 A2 A1 A0 R/W ACK by MCP3426/7/8 C1 C0 S1 S0 G1 G0 O/C ACK by MCP3426/7/8 Stop Bit by Master RDY (a) One-Shot Mode: 1 (b) Continuous Mode: not effected 1st Byte: Address Byte with Write command Note: 2nd Byte: Configuration Byte – Stop bit can be issued any time during writing. – MCP3426/7/8 device code is 1101 (programmed at the factory). – See Figure 5-1 for details in Address Byte. FIGURE 5-3: Timing Diagram For Writing To The MCP3426/7/8. © 2009 Microchip Technology Inc. DS22226A-page 21 MCP3426/7/8 5.3.4 READING OUTPUT CODES AND CONFIGURATION BYTE FROM THE DEVICE When the Master sends a read command (R/W = 1), the device outputs both the conversion data and configuration bytes. Each byte consists of 8 bits with one acknowledge (ACK) bit. The ACK bit after the address byte is issued by the device and the ACK bits after each conversion data bytes are issued by the Master. When the device receives a read command, it outputs two data bytes followed by a configuration register. In 16-bit conversion mode, the MSB (= sign bit) of the first data byte is D15. In 14-bit conversion mode, the first two bits in the first data byte are repeated MSB bits and can be ignored, and the 3rd bit (D13) is the MSB (=sign bit) of the conversion data. In 12-bit conversion mode, the first four bits are repeated MSB bits and can be ignored. The 5th bit (D11) of the byte represents the MSB (= sign bit) of the conversion data. Table 5-4 summarizes the conversion data output of each conversion mode. The configuration byte follows the output data bytes. The device repeatedly outputs the configuration byte only if the Master sends clocks repeatedly after the data bytes. The device terminates the current outputs when it receives a Not-Acknowledge (NAK) with a repeated start or a stop bit at the end of each output byte. It is not required to read the configuration byte. However, the Master may read the configuration byte to check the RDY bit condition.The Master may continuously send clock (SCL) to repeatedly read the configuration byte (to check the RDY bit status). Figure 5-4 shows the timing diagram for reading the ADC conversion data. TABLE 5-4: OUTPUT CODES OF EACH RESOLUTION OPTION Conversion Option Digital Output Codes 16-bits D15 ~ D8 (1st data byte) - D7 ~ D0 (2nd data byte) - Configuration byte. (Note 1) 14-bits MMD13D ~ D8 (1st data byte) - D7 ~ D0 (2nd data byte) - Configuration byte. (Note 2) 12-bits MMMMD11 ~ D8 (1st data byte) - D7 ~ D0 (2nd data byte) - Configuration byte. (Note 3) Note 1: D15 is MSB (= sign bit). 2: D13 is MSB (= sign bit), M is repeated MSB of the data byte. 3: D11 is MSB (= sign bit), M is repeated MSB of the data byte. DS22226A-page 22 © 2009 Microchip Technology Inc. FIGURE 5-4: © 2009 Microchip Technology Inc. Note: Start Bit by Master SDA SCL 0 1 R/W A2 A1 A0 1st Byte MCP3426/7/8 Address Byte 1 D 15 1 D 12 D 11 D 10 2nd Byte Upper Data Byte D D 14 13 ACK by MCP3426/7/8 9 D 9 D 8 D 7 1 1 ACK by Master 9 RDY C 1 D 6 – MCP3426/7/8 device code is 1101. – See Figure 5-1 for details in Address Byte. – Stop bit or NAK bit can be issued at the end of each output byte. – In 14 - bit mode: D15 and D14 are repeated MSB and can be ignored. – In 12 - bit mode: D15 - D12 are repeated MSB and can be ignored. – Configuration byte repeats as long as clock is provided after the 4th byte. 1 1 D 4 D 3 D 2 O/C S 1 S 0 (Optional) G 0 D 0 9 1 RDY C 1 Stop Bit by Master ACK by Master NAK by Master D 1 G 1 Nth Repeated Byte: Configuration Byte C 0 3rd Byte Lower Data Byte D 5 9 C 0 S 0 G 1 G 0 To continue: ACK by Master To end: NAK by Master (Optional) 4th Byte Configuration Byte O/C S 1 9 MCP3426/7/8 Timing Diagram For Reading From The MCP3426/7/8 With 12-Bit to 16-Bit Modes. DS22226A-page 23 MCP3426/7/8 5.4 General Call 5.5 The device acknowledges the general call address (0x00 in the first byte). The meaning of the general call address is always specified in the second byte. Refer to Figure 5-5. The device supports the following three general calls. For more information on the general call, or other I2C modes, refer to the Phillips I2C specification. 5.4.1 GENERAL CALL RESET The general call reset occurs if the second byte is ‘00000110’ (06h). At the acknowledgement of this byte, the device will abort current conversion and perform the following tasks: (a) Internal reset similar to a Power-On-Reset (POR). All configuration and data register bits are reset to default values. (b) Latch the logic status of external address selection pins (Adr0 and Adr1 pins). 5.4.2 GENERAL CALL LATCH (MCP3427 AND MCP3428) The general call latch occurs if the second byte is ‘00000100’ (04h). The device will latch the logic status of the external address selection pins (Adr0 and Adr1 pins), but will not perform a reset. 5.4.3 GENERAL CALL CONVERSION The general call conversion occurs if the second byte is ‘00001000’ (08h). All devices on the bus initiate a conversion simultaneously. When the device receives this command, the configuration will be set to the One-Shot Conversion mode and a single conversion will be performed. The PGA and data rate settings are unchanged with this general call. START LSB STOP S 0 0 0 0 0 0 0 0 A X X X X X X X X A S ACK First Byte (General Call Address) Note: Second Byte ACK The I2C specification does not allow ‘00000000’ (00h) in the second byte. FIGURE 5-5: Format. DS22226A-page 24 General Call Address High-Speed (HS) Mode The I2C specification requires that a high-speed mode device must be ‘activated’ to operate in high-speed mode. This is done by sending a special address byte of “00001XXX” following the START bit. The “XXX” bits are unique to the High-Speed (HS) mode Master. This byte is referred to as the High-Speed (HS) Master Mode Code (HSMMC). The MCP3426/7/8 devices do not acknowledge this byte. However, upon receiving this code, the device switches on its HS mode filters and communicates up to 3.4 MHz on SDA and SCL bus lines. The device will switch out of the HS mode on the next STOP condition. For more information on the HS mode, or other I2C modes, refer to the Philips I2C specification. 5.6 I2C Bus Characteristics The I2C specification defines the following bus protocol: • Data transfer may be initiated only when the bus is not busy • During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH will be interpreted as a START or STOP condition Accordingly, the following bus conditions have been defined using Figure 5-6. 5.6.1 BUS NOT BUSY (A) Both data and clock lines remain HIGH. 5.6.2 START DATA TRANSFER (B) A HIGH to LOW transition of the SDA line while the clock (SCL) is HIGH determines a START condition. All commands must be preceded by a START condition. 5.6.3 STOP DATA TRANSFER (C) A LOW to HIGH transition of the SDA line while the clock (SCL) is HIGH determines a STOP condition. All operations can be ended with a STOP condition. 5.6.4 DATA VALID (D) The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal. The data on the line must be changed during the LOW period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a START condition and terminated with a STOP condition. © 2009 Microchip Technology Inc. MCP3426/7/8 5.6.5 ACKNOWLEDGE AND NON-ACKNOWLEDGE The Master (microcontroller) and the slave (MCP3426/ 7/8) use an acknowledge pulse (ACK) as a hand shake of communication for each byte. The ninth clock pulse of each byte is used for the acknowledgement. The clock pulse is always provided by the Master (microcontroller) and the acknowledgement is issued by the receiving device of the byte (Note: The transmitting device must release the SDA line during the acknowledge pulse.). The acknowledgement is achieved by pulling-down the SDA line “LOW” during the 9th clock pulse by the receiving device. (A) (B) During reads, the Master (microcontroller) can terminate the current read operation by not providing an acknowledge bit (not Acknowledge (NAK)) on the last byte. In this case, the MCP3426/7/8 devices release the SDA line to allow the Master (microcontroller) to generate a STOP or repeated START condition. The non-acknowledgement (NAK) is issued by providing the SDA line to “HIGH” during the 9th clock pulse. (D) (D) (C) (A) SCL SDA START CONDITION FIGURE 5-6: ADDRESS OR DATA ACKNOWLEDGE ALLOWED VALID TO CHANGE 2 STOP CONDITION Data Transfer Sequence on I C Serial Bus. © 2009 Microchip Technology Inc. DS22226A-page 25 MCP3426/7/8 TABLE 5-5: I2C SERIAL TIMING SPECIFICATIONS Electrical Specifications: Unless otherwise specified, all limits are specified for TA = -40 to +85°C, VDD = +2.7V to +5.0V, VSS = 0V, CHn+ = CHn- = VREF/2. Parameters Sym Min Typ Max Units Conditions Standard Mode (100 kHz) Clock frequency fSCL 0 — 100 kHz Clock high time THIGH 4000 — — ns Clock low time TLOW 4700 — — ns SDA and SCL rise time TR — — 1000 ns SDA and SCL fall time TF — — 300 ns From VIH to VIL (Note 1) START condition hold time THD:STA 4000 — — ns After this period, the first clock pulse is generated. Repeated START condition setup time TSU:STA 4700 — — ns Only relevant for repeated Start condition Data hold time THD:DAT 0 — 3450 ns (Note 3) Data input setup time TSU:DAT 250 — — ns STOP condition setup time TSU:STO 4000 — — ns TAA 0 — 3750 ns (Note 2, Note 3) TBUF 4700 — — ns Time between START and STOP conditions. kHz Output valid from clock Bus free time From VIL to VIH (Note 1) Fast Mode (400 kHz) Clock frequency TSCL 0 — 400 Clock high time THIGH 600 — — ns Clock low time TLOW 1300 — — ns TR 20 + 0.1Cb — 300 ns SDA and SCL rise time From VIL to VIH (Note 1) TF 20 + 0.1Cb — 300 ns From VIH to VIL (Note 1) START condition hold time THD:STA 600 — — ns After this period, the first clock pulse is generated Repeated START condition setup time TSU:STA 600 — — ns Only relevant for repeated Start condition Data hold time THD:DAT 0 — 900 ns (Note 4) Data input setup time TSU:DAT 100 — — ns STOP condition setup time TSU:STO 600 — — ns TAA 0 — 1200 ns (Note 2, Note 3) TBUF 1300 — — ns Time between START and STOP conditions. TSP 0 — 50 ns SDA and SCL pins (Note 5) SDA and SCL fall time Output valid from clock Bus free time Input filter spike suppression Note 1: 2: 3: 4: 5: This parameter is ensured by characterization and not 100% tested. This specification is not a part of the I2C specification. This specification is equivalent to the Data Hold Time (THD:DAT) plus SDA Fall (or rise) time: TAA = THD:DAT + TF (OR TR). If this parameter is too short, it can create an unintended Start or Stop condition to other devices on the bus line. If this parameter is too long, Clock Low time (TLOW) can be affected. For Data Input: This parameter must be longer than tSP. If this parameter is too long, the Data Input Setup (TSU:DAT) or Clock Low time (TLOW) can be affected. For Data Output: This parameter is characterized, and tested indirectly by testing TAA parameter. This parameter is ensured by characterization and not 100% tested. This parameter is not available for Standard Mode. DS22226A-page 26 © 2009 Microchip Technology Inc. MCP3426/7/8 TABLE 5-5: I2C SERIAL TIMING SPECIFICATIONS (CONTINUED) Electrical Specifications: Unless otherwise specified, all limits are specified for TA = -40 to +85°C, VDD = +2.7V to +5.0V, VSS = 0V, CHn+ = CHn- = VREF/2. Parameters Sym Min Typ Max Units Conditions High Speed Mode (3.4 MHz) Clock frequency fSCL 0 — 3.4 MHz Cb = 100 pF 0 — 1.7 MHz Cb = 400 pF — — ns Clock high time THIGH 60 120 — — ns Cb = 400 pF, fSCL = 1.7 MHz Clock low time TLOW 160 — — ns Cb = 100 pF, fSCL = 3.4 MHz 320 — — ns Cb = 400 pF, fSCL = 1.7 MHz SCL rise time (Note 1) TR — — 40 ns From VIL to VIH, Cb = 100 pF, fSCL = 3.4 MHz — — 80 ns From VIL to VIH, Cb = 400 pF, fSCL = 1.7 MHz — — 40 ns From VIH to VIL, Cb = 100 pF, fSCL = 3.4 MHz — — 80 ns From VIH to VIL, Cb = 400 pF, fSCL = 1.7 MHz — — 80 ns From VIL to VIH, Cb = 100 pF, fSCL = 3.4 MHz — — 160 ns From VIL to VIH, Cb = 400 pF, fSCL = 1.7 MHz — — 80 ns From VIH to VIL, Cb = 100 pF, fSCL = 3.4 MHz — — 160 ns From VIH to VIL, Cb = 400 pF, fSCL = 1.7 MHz THD:DAT 0 — 70 ns Cb = 100 pF, fSCL = 3.4 MHz 0 — 150 ns Cb = 400 pF, fSCL = 1.7 MHz TAA — — 150 ns Cb = 100 pF, fSCL = 3.4 MHz — — 310 ns Cb = 400 pF, fSCL = 1.7 MHz SCL fall time (Note 1) SDA rise time (Note 1) SDA fall time (Note 1) Data hold time (Note 4) Output valid from clock (Notes 2 and 3) TF TR: DAT TF: DATA Cb = 100 pF, fSCL = 3.4 MHz START condition hold time THD:STA 160 — — ns After this period, the first clock pulse is generated Repeated START condition setup time TSU:STA 160 — — ns Only relevant for repeated Start condition Data input setup time TSU:DAT 10 — — ns STOP condition setup time TSU:STO 160 — — ns TSP 0 — 10 ns Input filter spike suppression Note 1: 2: 3: 4: 5: SDA and SCL pins (Note 5) This parameter is ensured by characterization and not 100% tested. This specification is not a part of the I2C specification. This specification is equivalent to the Data Hold Time (THD:DAT) plus SDA Fall (or rise) time: TAA = THD:DAT + TF (OR TR). If this parameter is too short, it can create an unintended Start or Stop condition to other devices on the bus line. If this parameter is too long, Clock Low time (TLOW) can be affected. For Data Input: This parameter must be longer than tSP. If this parameter is too long, the Data Input Setup (TSU:DAT) or Clock Low time (TLOW) can be affected. For Data Output: This parameter is characterized, and tested indirectly by testing TAA parameter. This parameter is ensured by characterization and not 100% tested. This parameter is not available for Standard Mode. © 2009 Microchip Technology Inc. DS22226A-page 27 MCP3426/7/8 TF SCL TSU:STA TLOW SDA TR THIGH TSP THD:STA TSU:DAT THD:DAT TSU:STO TBUF 0.7VDD 0.3VDD TAA FIGURE 5-7: DS22226A-page 28 I2C Bus Timing Data. © 2009 Microchip Technology Inc. MCP3426/7/8 6.0 BASIC APPLICATION CONFIGURATION The MCP3426/7/8 devices can be used for various precision analog-to-digital converter applications. These devices operate with very simple connections to the application circuit. The following sections discuss the examples of the device connections and applications. 6.1 6.1.1 Connecting to the Application Circuits The user can tie the Adr0 and Adr1 pins to VSS, VDD, or left floating. See more details in Section 5.3.2 “Device Address Bits (A2, A1, A0) and Address Selection Pins (MCP3427 and MCP3428)”. MCP3428 Input Input Signal 1 1 CH1+ 2 CH13 CH2+ Input Signal 2 BYPASS CAPACITORS ON VDD PIN For an accurate measurement, the application circuit needs a clean supply voltage and must block any noise signal to the MCP3426/7/8 devices. Figure 6-1 shows an example of using two bypass capacitors (a 10 µF tantalum capacitor and a 0.1 µF ceramic capacitor) on the VDD line of the MCP3428. These capacitors are helpful to filter out any high frequency noises on the VDD line and also provide the momentary bursts of extra currents when the device needs from the supply. These capacitors should be placed as close to the VDD pin as possible (within one inch). If the application circuit has separate digital and analog power supplies, the VDD and VSS of the MCP3426/7/8 devices should reside on the analog plane. 6.1.2 I2C ADDRESS SELECTION PINS (MCP3427 AND MCP3428) 6.1.3 CONNECTING TO I2C BUS USING PULL-UP RESISTORS The SCL and SDA pins of the MCP3426/7/8 are open-drain configurations. These pins require a pull-up resistor as shown in Figure 6-1. The value of these pull-up resistors depends on the operating speed (standard, fast, and high speed) and loading capacitance of the I2C bus line. Higher value of pull-up resistor consumes less power, but increases the signal transition time (higher RC time constant) on the bus. Therefore, it can limit the bus operating speed. The lower value of resistor, on the other hand, consumes higher power, but allows higher operating speed. If the bus line has higher capacitance due to long bus line or high number of devices connected to the bus, a smaller pull-up resistor is needed to compensate the long RC time constant. The pull-up resistor is typically chosen between 5 kΩ and 10 kΩ ranges for standard and fast modes, and less than 1 kΩ for high speed mode depending on the presence of bus loading capacitance. C1 CH4- 14 Signal 4 CH4+ 13 CH3- 12 4 CH25 VSS CH3+ 11 6 VDD 7 SDA Adr0 9 SCL 8 Input Signal 3 I2C Address Selection Pins Adr1 10 C2 TO MCU (MASTER) RP RP VDD Rp is the pull-up resistor: 5 kΩ - 10 kΩ for fSCL = 100 kHz to 400 kHz ~700Ω for fSCL = 3.45 MHz C1: 0.1 µF, Ceramic capacitor C2: 10 µF, Tantalum capacitor FIGURE 6-1: Typical Connection. Figure 6-2 shows an example of multiple device connections. The I2C bus loading capacitance increases as the number of device connected to the I2C bus line increases. The bus loading capacitance affects on the bus operating speed. For example, the highest bus operating speed for the 400 pF bus capacitance is 1.7 MHz, and 3.4 MHz for 100 pF. Therefore, the user needs to consider the relationship between the maximum operation speed versus. the number of I2C devices that are connected to the I2C bus line. SDA SCL Microcontroller (PIC16F876) MCP3426 MCP3427 MCP3428 MCP4725 FIGURE 6-2: Example of Multiple Device Connection on I2C Bus. © 2009 Microchip Technology Inc. DS22226A-page 29 MCP3426/7/8 6.1.4 DEVICE CONNECTION TEST 6.1.5 The user can test the presence of the MCP3426/7/8 on the I2C bus line without performing an input data conversion. This test can be achieved by checking an acknowledge response from the MCP3426/7/8 after sending a read or write command. Here is an example using Figure 6-3: a. b. c. Set the R/W bit “HIGH” in the address byte. Check the ACK pulse after sending the address byte. If the device acknowledges (ACK = 0), then the device is connected, otherwise it is not connected. Send STOP or START bit. DIFFERENTIAL AND SINGLE-ENDED CONFIGURATION Figure 6-4 shows typical connection examples for differential and single-ended inputs. Differential input signals can be connected to the CHn+ and CHn- input pins, where n = the channel number (1, 2, 3, or 4). For the single-ended input, the input signal is applied to one of the input pins (typically connected to the CHn+ pin) while the other input pin (typically CHn- pin) is grounded. All device characteristics hold for the single-ended configuration, but this configuration loses one bit resolution because the input can only stand in positive half scale. Refer to Section 1.0 “Electrical Characteristics”. (a) Differential Input Signal Connection: Address Byte Excitation 1 SCL 2 3 4 5 6 7 8 Sensor 9 CHn+ Start Bit 1 0 Device bits 1 A2 A1 A0 1 ACK 1 SDA Input Signal Stop Bit Address bits R/W MCP342X Response FIGURE 6-3: CHnMCP342X (b) Single-ended Input Signal Connection: Excitation R1 I2C Bus Connection Test. CHn+ Sensor Input Signal R2 CHnMCP342X FIGURE 6-4: Differential and Single-Ended Input Connections. DS22226A-page 30 © 2009 Microchip Technology Inc. MCP3426/7/8 6.2 Application Examples Therefore, the current measurement often prefers to use a current sensor with smaller resistance value, which, in turn, requires high resolution ADC device. The MCP3426/7/8 devices can be used for broad ranges of sensor and data acquisition applications. The device can measure the input voltage as low as 7.8 µV range (or current in ~ µA range) with 16 bit resolution and PGA = 8 settings. Figure 6-5 shows a circuit example measuring both the battery voltage and current using the MCP3426 device. Channels 1 and 2 are measuring the voltage and the current, respectively. The MSB (= sign bit) of the output code determines the direction of the current, which identifies the charging or the discharging current. When the input voltage is greater than the internal reference voltage (VREF = 2.048V), it needs a voltage divider circuit to prevent the output code from being saturated. In the example, R1 and R2 form a voltage divider. The R1 and R2 are set to yield VIN to be less than the internal reference voltage (VREF = 2.048V). For the current measurement, the device measure the voltage across the current sensor, and converts it by dividing the measured voltage by a known resistance value. The voltage drops across the sensor is waste. Discharging Current To Load Current Sensor Charging Current To Battery R1 Battery (Rechargeable) VBAT MCP3426 VIN R2 1 CH1+ 2 CH1- 0.1 µF 3 VDD 4 SDA CH2- 8 CH2+ 7 VSS 6 SCL 5 SCL 10 µF TO MCU (MASTER) SDA R2 V IN = ------------------ × V BAT R1 + R2 5 kΩ 5 kΩ R1 and R2 = Voltage Divider FIGURE 6-5: VDD Battery Voltage and Charging/Discharging Current Measurement. © 2009 Microchip Technology Inc. DS22226A-page 31 MCP3426/7/8 Figure 6-6, shows an example of using the MCP3428 for four-channel thermocouple temperature measurement applications. Thermocouple Sensor Isothermal Block Isothermal Block MCP9800 MCP3428 MCP9800 SCL SDA 0.1 µF 1 2 3 4 5 6 7 CH1+ CH1CH2+ CH2VSS VDD SDA CH4- 14 13 12 11 CH4+ CH3CH3+ Adr1 Adr0 SCL SDA SCL 10 9 8 VDD MCP9800 MCP9800 10 µF SDA Heat SCL SCL SCL SDA TO MCU (MASTER) SDA 5 kΩ FIGURE 6-6: VDD Four-Channel Thermocouple Applications. With Type K thermocouple, it can measure temperature from 0°C to +1250°C degrees. The full scale output range of the Type K thermocouple is about 50 mV. This provides 40 µV/°C (= 50 mV/ 1250°C) of measurement resolution. Equation 6-1 shows the measurement budget for sensor signal using the MCP3426/7/8 device with 16 bits and PGA = 8 settings. With this configuration, the MCP3428 can detect the input signal level as low as approximately 7.8 µV. By setting the internal PGA option to x8, the 40 µV/°C input from the thermocouple is amplified internally to 320 µV/°C before the conversion takes place. This results in about 5 LSB output codes per 1°C of change in temperature, with 16-bit conversion mode. DS22226A-page 32 5 kΩ EQUATION 6-1: Detectable Input Signal Level = 62.5 μ V/PGA = 7.8125μV for PGA = 8 Input Signal Level after gain of 8: = ( 40 μ V/°C ) • 8 = 320 μ V/°C μ V/°C- = 5.12 Codes/°C No. of LSB/°C = 320 -----------------------62.5 μ V Where: 1 LSB = 62.5 µV with 16 bit configuration © 2009 Microchip Technology Inc. MCP3426/7/8 Equation 6-2 shows an example of calculating the expected number of output code with various PGA gain settings for Type K thermocouple output. EQUATION 6-2: EXPECTED NUMBER OF OUTPUT CODE FOR TYPE K THERMOCOUPLE Expected Number of Output Code = = ⎛ ⎞ 50 mV log 2 ⎜ ------------------⎟ ⎜ 62.5μV⎟ ⎝ ------------------⎠ PGA ln ( 800 • PGA -)⎞ ⎛ -----------------------------------⎝ ⎠ ln ( 2 ) = 9.6 bits for PGA = 1 = 10.6 bits for PGA = 2 = 11.6 bits for PGA = 4 = 12.6 bits for PGA = 8 Where: 1 LSB = 62.5 µV with 16 Bit configuration. VDD VDD Pressure Sensor (NPP301) Pressure Sensor (NPP301) MCP3428 VIN 1 CH1+ CH4- 14 2 CH1- CH4+ CH3CH3+ Adr1 3 CH2+ 4 CH2- VDD 5 VSS 0.1 µF R1 6 VDD 7 SDA 13 12 11 10 VDD R1 Adr0 9 SCL 8 R2 10 µF Thermistor VDD VIN Thermistor TO MCU (MASTER) R2 5 kΩ 5 kΩ VDD R2 V IN = ------------------ × V DD R1 + R2 R1 and R2 = Voltage Divider FIGURE 6-7: Example of Pressure and Temperature Measurement. © 2009 Microchip Technology Inc. DS22226A-page 33 MCP3426/7/8 Figure 6-7 shows an example of measuring both pressure and temperature. The pressure is measured by using NPP 301 (manufactured by GE NovaSensor), and temperature is measured by a thermistor. The pressure sensor output is 20 mV/V. This gives 100 mV of full scale output for VDD of 5V (sensor excitation voltage). Equation 6-3 shows an example of calculating the number of output code for the full scale output of the NPP301. EQUATION 6-3: EXPECTED NUMBER OF OUTPUT CODE FOR NPP301 PRESSURE SENSOR Expected Number of Output Code = ⎛ ⎞ 100 mV log 2 ⎜⎜ ---------------------⎟⎟ 62.5μV ⎝ ------------------ ⎠ PGA ln ( 1600 • PGA )-⎞ = ⎛ --------------------------------------⎝ ⎠ ln ( 2 ) = 10.6 bits for PGA = 1 = 11.6 bits for PGA = 2 = 12.6 bits for PGA = 4 = 13.6 bits for PGA = 8 Where: 1 LSB = 62.5 µV with 16 Bit configuration. The thermistor temperature sensor can measure the temperature range from -100°C to +300°C. The resistance of the thermistor sensor decreases as temperature increases (negative temperature coefficient). As shown in Figure 6-7, the thermistor (R2) forms a voltage divider with R1. The thermistor sensor is simple to use and widely used for the temperature measurement applications. It has both linear and non-linear responses over temperature range. R1 is used to adjust the linear region of interest for measurement. DS22226A-page 34 © 2009 Microchip Technology Inc. MCP3426/7/8 7.0 PACKAGING INFORMATION 7.1 Package Marking Information 8-Lead DFN (2x3) (MCP3426) XXX YWW NN Example: ABX 945 25 8-Lead MSOP (MCP3426) Example: XXXXXX 3426A0 YWWNNN 945256 8-Lead SOIC (300 mil) (MCP3426) XXXXXXXX XXXXYYWW NNN Legend: XX...X Y YY WW NNN e3 * Note: Example: 3426A0E e3 SN^^0945 256 Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. © 2009 Microchip Technology Inc. DS22226A-page 35 MCP3426/7/8 Package Marking Information (Continued) 10-Lead DFN (3x3) (MCP3427) 1 10 1 9 2 8 3 7 4 6 5 XXXX YYWW NNN 2 3 4 5 10-Lead MSOP (MCP3427) XXXXXX YWWNNN 14-Lead SOIC (150 mil) (MCP3428) XXXXXXXXXXX XXXXXXXXXXX YYWWNNN 14-Lead TSSOP (4.4 mm) (MCP3428) XXXXXXXX DS22226A-page 36 Example: 10 3427 0945 256 9 8 7 6 Example: 3427E 945256 Example: MCP3428 e3 E/SL^^ 0945256 Example: MCP3428E YYWW 0945 NNN 256 © 2009 Microchip Technology Inc. MCP3426/7/8 !""#$%& ' 2%& %!% *") ' % * $%%"% %% 133)))& &3 * e D b N N L K E2 E EXPOSED PAD NOTE 1 NOTE 1 2 1 2 1 D2 BOTTOM VIEW TOP VIEW A A3 A1 NOTE 2 4% & 5&% 6!&($ 55,, 6 6 67 8 9 % 7:% 9 %"$$ . 0%%* + ,2 75% /0 7;"% , ,# ""5% + < ,# "";"% , . < . ( . + 0%%5% 5 + . 0%%%,# "" = < < 0%%;"% ./0 +/0 ' !"#$%!&'(!%&! %(%")%%%" *&&# "%( %" + * ) !%" & "% ,-. /01 / & %#%! ))%!%% ,21 $& '! !)%!%%'$$&% ! .. ) 0+0 © 2009 Microchip Technology Inc. DS22226A-page 37 MCP3426/7/8 !""#$%& ' 2%& %!% *") ' % * $%%"% %% 133)))& &3 * DS22226A-page 38 © 2009 Microchip Technology Inc. MCP3426/7/8 ()" * +)%)*& ' 2%& %!% *") ' % * $%%"% %% 133)))& &3 * D N E E1 NOTE 1 1 2 e b A2 A c φ L L1 A1 4% & 5&% 6!&($ 55,, 6 6 67 8 9 % 7:% < >./0 < ""** . 9. . %"$$ < . 7;"% , ""*;"% , +/0 75% +/0 2%5% 5 2% % 5 /0 > 9 .,2 2% I ? < 9? 5"* 9 < + 5";"% ( < ' !"#$%!&'(!%&! %(%")%%%" & ","%!"&"$ %! "$ %! %#".&& " + & "% ,-. /01 / & %#%! ))%!%% ,21 $& '! !)%!%%'$$&% ! ) 0/ © 2009 Microchip Technology Inc. DS22226A-page 39 MCP3426/7/8 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS22226A-page 40 © 2009 Microchip Technology Inc. MCP3426/7/8 )" * +)((, !""#$%)*-& ' 2%& %!% *") ' % * $%%"% %% 133)))& &3 * D e N E E1 NOTE 1 1 2 3 α h b h A2 A c φ L A1 β L1 4% & 5&% 6!&($ 55,, 6 6 67 8 9 % 7:% < /0 < ""** . < < %"$$@ < . 7;"% , ""*;"% , +/0 75% /0 . >/0 0&$A %B . < . 2%5% 5 < 2% % 5 ,2 2% ? < 9? 5"* < . 5";"% ( + < . "$% .? < .? "$%/%%& .? < .? ' !"#$%!&'(!%&! %(%")%%%" @$%0% % + & ","%!"&"$ %! "$ %! %#".&& " & "% ,-. /01 / & %#%! ))%!%% ,21 $& '! !)%!%%'$$&% ! ) 0./ © 2009 Microchip Technology Inc. DS22226A-page 41 MCP3426/7/8 )" * +)((, !""#$%)*-& ' 2%& %!% *") ' % * $%%"% %% 133)))& &3 * DS22226A-page 42 © 2009 Microchip Technology Inc. MCP3426/7/8 . !""#$%& ' 2%& %!% *") ' % * $%%"% %% 133)))& &3 * D e b N N L K E E2 EXPOSED PAD NOTE 1 NOTE 1 1 2 2 1 D2 BOTTOM VIEW TOP VIEW A A1 A3 NOTE 2 4% & 5&% 6!&($ 55,, 6 6 67 8 % 7:% 9 ./0 %"$$ . 0%%* + ,2 75% ,# ""5% 7;"% , ,# "";"% , .9 . ( 9 . + 0%%5% 5 + . 0%%%,# "" = < < 0%%;"% +/0 +. 9 +/0 ' !"#$%!&'(!%&! %(%")%%%" *&&# "%( %" + * ) !%" & "% ,-. /01 / & %#%! ))%!%% ,21 $& '! !)%!%%'$$&% ! ) 0>+/ © 2009 Microchip Technology Inc. DS22226A-page 43 MCP3426/7/8 . !""#$%& ' 2%& %!% *") ' % * $%%"% %% 133)))& &3 * DS22226A-page 44 © 2009 Microchip Technology Inc. MCP3426/7/8 . ()" * +/%)*& ' 2%& %!% *") ' % * $%%"% %% 133)))& &3 * D N E E1 NOTE 1 1 2 b e A A2 c φ L A1 L1 4% & 5&% 6!&($ 55,, 6 6 67 8 % 7:% < ./0 < ""** . 9. . %"$$ < . 7;"% , ""*;"% , +/0 75% +/0 2%5% 5 2% % 5 /0 > 9 .,2 2% ? < 9? 5"* 9 < + 5";"% ( . < ++ ' !"#$%!&'(!%&! %(%")%%%" & ","%!"&"$ %! "$ %! %#".&& " + & "% ,-. /01 / & %#%! ))%!%% ,21 $& '! !)%!%%'$$&% ! ) 0/ © 2009 Microchip Technology Inc. DS22226A-page 45 MCP3426/7/8 .0 )" * +)((, !""#$%)*-& ' 2%& %!% *") ' % * $%%"% %% 133)))& &3 * D N E E1 NOTE 1 1 2 3 e h b α h A A2 c φ L A1 β L1 4% & 5&% 6!&($ 55,, 6 6 67 8 % 7:% < /0 < ""** . < < %"$$@ < . 7;"% , ""*;"% , +/0 75% 9>./0 . >/0 0&$A %B . < . 2%5% 5 < 2% % 5 ,2 2% ? < 9? 5"* < . 5";"% ( + < . "$% .? < .? "$%/%%& .? < .? ' !"#$%!&'(!%&! %(%")%%%" @$%0% % + & ","%!"&"$ %! "$ %! %#".&& " & "% ,-. /01 / & %#%! ))%!%% ,21 $& '! !)%!%%'$$&% ! ) 0>./ DS22226A-page 46 © 2009 Microchip Technology Inc. MCP3426/7/8 ' 2%& %!% *") ' % * $%%"% %% 133)))& &3 * © 2009 Microchip Technology Inc. DS22226A-page 47 MCP3426/7/8 .0 12+)2(+)" * +)10 0""#$%1))*& ' 2%& %!% *") ' % * $%%"% %% 133)))& &3 * D N E E1 NOTE 1 1 2 e b c φ A2 A A1 4% & 5&% 6!&($ L L1 55,, 6 6 67 8 % 7:% < >./0 < ""** 9 . %"$$ . < . 7;"% , ""*;"% , + >/0 ""*5% . . 2%5% 5 . > . 2% % 5 . ,2 2% ? < 9? 5"* < 5";"% ( < + ' !"#$%!&'(!%&! %(%")%%%" & ","%!"&"$ %! "$ %! %#".&& " + & "% ,-. /01 / & %#%! ))%!%% ,21 $& '! !)%!%%'$$&% ! ) 09/ DS22226A-page 48 © 2009 Microchip Technology Inc. MCP3426/7/8 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging © 2009 Microchip Technology Inc. DS22226A-page 49 MCP3426/7/8 NOTES: DS22226A-page 50 © 2009 Microchip Technology Inc. MCP3426/7/8 APPENDIX A: REVISION HISTORY Revision A (December 2009) • Original Release of this Document. © 2009 Microchip Technology Inc. DS22226A-page 51 MCP3426/7/8 NOTES: DS22226A-page 52 © 2009 Microchip Technology Inc. MCP3426/7/8 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. -X /XX Device Temperature Range Package Device: Examples: a) b) MCP3426: 2-Channel 16-Bit ADC MCP3426T: 2-Channel 16-Bit ADC (Tape and Reel) MCP3427: 2-Channel 16-Bit ADC MCP3427T: 2-Channel 16-Bit ADC (Tape and Reel) MCP3428: 4-Channel 16-Bit ADC MCP3428T: 4-Channel 16-Bit ADC (Tape and Reel) c) d) e) f) Temperature Range: E = -40°C to +125°C Package: MC MS SN MF UN SL ST = = = = = = = Plastic Dual Flat, No Lead (2x3 DFN), 8-lead Plastic Micro Small Outline (MSOP), 8-lead Plastic Small Outline SOIC, 8-lead Plastic Dual Flat, No Lead (3x3 DFN) 10-lead Plastic Micro Small Outline (MSOP), 10-lead Plastic Small Outline SOIC (150 mil Body), 14-lead Plastic TSSOP (4.4mm Body), 14-lead © 2009 Microchip Technology Inc. MCP3426A0-E/MC: 2-Channel ADC, 8LD DFN package. MCP3426A0T-E/MC: Tape and Reel, 2-Channel ADC, 8LD DFN package. MCP3426A0-E/MS: 2-Channel ADC, 8LD MSOP package. MCP3426A0T-E/MS: Tape and Reel, 2-Channel ADC, 8LD MSOP package. MCP3426A0-E/SN: 2-Channel ADC, 8LD SOIC package. MCP3426A0T-E/SN: Tape and Reel, 2-Channel ADC, 8LD SOIC package. a) MCP3427-E/MF: b) MCP3427T-E/MF: c) MCP3427-E/UN: d) MCP3427T-E/UN: a) MCP3428-E/SL: b) MCP3428T-E/SL: c) MCP3428-E/ST: d) MCP3428T-E/ST: 2-Channel ADC, 10LD DFN package. Tape and Reel, 2-Channel ADC, 10LD DFN package. 2-Channel ADC, 10LD MSOP package. Tape and Reel, 2-Channel ADC, 10LD MSOP package. 4-Channel ADC, 14LD SOIC package. Tape and Reel, 4-Channel ADC, 14LD SOIC package. 4-Channel ADC, 14LD TSSOP package. Tape and Reel, 4-Channel ADC, 14LD TSSOP package. DS22226A-page 53 MCP3426/7/8 NOTES: DS22226A-page 54 © 2009 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, PIC32 logo, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2009, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. © 2009 Microchip Technology Inc. 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