MITSUBISHI MH32S64PFJ-6L

Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without
notice.
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
DESCRIPTION
The MH32S64PFJ is 33554432 - word by 64-bit
Synchronous DRAM module. This consists of eight
industry standard 16Mx16 Synchronous DRAMs in
TSOP and one industory standard EEPROM in
TSSOP.
The mounting of TSOP on a card edge Dual
Inline package provides any application where
high densities and large quantities of memory are
required.
This is a socket type - memory modules, suitable
for easy interchange or addition of modules.
Utilizes industry standard 16M x 16 Synchronous
DRAMs TSOP and industry standard EEPROM in
TSSOP
144-pin (72-pin dual in-line package)
single 3.3V±0.3V power supply
Fully synchronous operation referenced to clock rising
edge
4 bank operation controlled by BA0,1(Bank Address)
/CAS latency- 2/3(programmable)
Burst length- 1/2/4/8/Full Page(programmable)
Burst type- sequential / interleave(programmable)
FEATURES
Frequency
CLK Access Time
(Component SDRAM)
-6,-6L
133MHz
5.4ns(CL=3)
-7,-7L
100MHz
6.0ns(CL=2)
Column access - random
Auto precharge / All bank precharge controlled by A10
Auto refresh and Self refresh
8192 refresh cycle /64ms
LVTTL Interface
PC133/100 Compliant
APPLICATION
main memory or graphic memory in computer systems
PCB Outline
(Front)
(Back)
MIT-DS-0337-0.2
1
2
143
144
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Preliminary Spec.
MITSUBISHI LSIs
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notice.
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
PIN CONFIGURATION
PIN
Number
1
3
5
7
9
Front side
Pin Name
PIN
Number
Vss
DQ0
DQ1
DQ2
2
4
6
Back side
Pin Name
PIN
Number
Front side
Pin Name
PIN
Number
Back side
Pin Name
Vss
73
Reserved
74
DQ32
DQ33
DQ34
75
76
77
Vss
Reserved
78
CLK1
Vss
Reserved
79
Reserved
80
Reserved
DQ35
81
Vcc
82
Vcc
DQ3
8
10
11
13
Vcc
DQ4
12
14
Vcc
DQ36
83
DQ16
84
DQ48
85
DQ17
86
DQ49
15
DQ5
16
DQ37
87
DQ18
88
DQ50
17
DQ6
18
DQ38
89
DQ19
90
DQ51
19
21
DQ7
Vss
20
DQ39
91
Vss
92
Vss
22
93
DQ20
94
95
DQ21
96
DQ52
DQ53
97
DQ22
98
DQ54
23
DQMB0
24
Vss
DQMB4
25
DQMB1
26
DQMB5
27
Vcc
28
Vcc
99
DQ23
100
DQ55
29
A0
30
A3
101
Vcc
102
Vcc
31
A1
32
A4
103
A6
104
A7
33
A2
34
A5
105
A8
106
BA0
35
Vss
36
Vss
107
Vss
108
Vss
37
DQ8
38
DQ40
109
A9
110
BA1
39
DQ9
40
DQ41
111
A10
112
A11
41
DQ10
42
DQ42
113
Vcc
114
43
DQ11
44
DQ43
115
DQMB2
116
DQMB6
45
Vcc
46
Vcc
117
DQMB3
118
DQMB7
47
DQ12
48
DQ44
119
Vss
120
Vss
49
DQ13
50
DQ45
121
DQ24
122
DQ56
51
DQ14
52
DQ46
123
DQ25
124
DQ57
53
DQ15
54
DQ47
125
DQ26
126
DQ58
55
Vss
56
127
DQ27
128
DQ59
57
Reserved
58
Vss
Reserved
129
Vcc
130
Vcc
59
Reserved
60
Reserved
131
DQ28
132
DQ60
61
CLK0
62
CKE0
133
DQ29
134
DQ61
63
Vcc
64
Vcc
135
DQ30
136
DQ62
65
/RAS
66
/CAS
137
DQ31
138
DQ63
67
/WE
68
CKE1
139
Vss
140
Vss
69
/S0
70
A12
141
SDA
142
SCL
71
/S1
A13
143
Vcc
144
Vcc
72
Vcc
NC = No Connection
MIT-DS-0337-0.2
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Preliminary Spec.
MITSUBISHI LSIs
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notice.
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
Block Diagram
/S0
/S1
DQMB0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQMB1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQML /CS
DQML /CS
I/O 0
I/O 1 D0
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1 D4
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQMU
DQMU
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
8
9
10
11
12
13
14
15
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQML /CS
DQML /CS
I/O 0
I/O 1 D1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1 D5
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQMB3
DQMU
DQMU
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
8
9
10
11
12
13
14
15
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQMB5
8
9
10
11
12
13
14
15
DQMB2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
8
9
10
11
12
13
14
15
DQMB4
DQMB6
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQMB7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQML /CS
DQML /CS
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1 D2
2
3
4
5
6
7
0
1 D6
2
3
4
5
6
7
DQMU
DQMU
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
8
9
10
11
12
13
14
15
8
9
10
11
12
13
14
15
DQML /CS
DQML /CS
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1 D3
2
3
4
5
6
7
0
1 D7
2
3
4
5
6
7
DQMU
DQMU
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
8
9
10
11
12
13
14
15
8
9
10
11
12
13
14
15
10Ω
CLK0
CLK1
CKE0
CKE1
/RAS
/CAS
/WE
BA0,BA1,A<12:0>
Vcc
Vss
MIT-DS-0337-0.2
4loads
4loads
D0 - D3
D4 - D7
D0 - D7
D0 - D7
D0 - D7
D0 - D7
D0 - D7
SERIAL PD
SCL
A0
A1
A2
SDA
D0 - D7
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Preliminary Spec.
MITSUBISHI LSIs
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MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
Serial Presence Detect Table I
Byte
Function described
SPD enrty data
SPD DATA(hex)
0
Defines # bytes written into serial memory at module mfgr
128
80
1
Total # bytes of SPD memory device
256 Bytes
08
2
Fundamental memory type
SDRAM
04
3
# Row Addresses on this assembly
A0-A12
0D
4
# Column Addresses on this assembly
A0-A8
09
5
# Module Banks on this assembly
2BANK
02
6
Data Width of this assembly...
x64
40
7
... Data Width continuation
0
00
8
Voltage interface standard of this assembly
LVTTL
7.5ns
01
75
9
10
SDRAM Cycletime at Max. Supported CAS Latency (CL).
-6
Cycle time for CL=3
-7
10ns
A0
SDRAM Access from Clock
-6
5.4ns
54
tAC for CL=3
-7
6ns
60
11
DIMM Configuration type (Non-parity,Parity,ECC)
Non-PARITY
12
Refresh Rate/Type
self refresh(7.8125uS)
82
13
SDRAM width,Primary DRAM
x16
10
Error Checking SDRAM data width
N/A
00
14
15
Minimum Clock Delay,Back to Back Random Column Addresses
1
1/2/4/8/Full page
00
01
16
Burst Lengths Supported
17
# Banks on Each SDRAM device
CAS# Latency
4bank
8F
04
2/3
06
19
CS# Latency
0
01
20
Write Latency
0
01
18
21
SDRAM Module Attributes
non-buffered,non-registered
00
22
SDRAM Device Attributes:General
Precharge All,Auto precharge
0E
23
SDRAM Cycle time(2nd highest CAS latency)
-6
10ns
A0
-7
10ns
A0
-6
6ns
60
-7
6ns
60
Cycle time for CL=2
24
SDRAM Access form Clock(2nd highest CAS latency)
tAC for CL=2
25
SDRAM Cycle time(3rd highest CAS latency)
N/A
00
26
SDRAM Access form Clock(3rd highest CAS latency)
N/A
00
27
Precharge to Active Minimum
14
-6
20ns
15ns
-7
20ns
14
20ns
14
-6
45ns
2D
-7
50ns
32
28
Row Active to Row Active Min.
29
30
MIT-DS-0337-0.2
RAS to CAS Delay Min
Active to Precharge Min
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26.Apr.2001
Preliminary Spec.
MITSUBISHI LSIs
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notice.
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
Serial Presence Detect Table II
31
128MByte
20
Command and Address signal input setup time
-6
1.5ns
15
Command and Address signal input hold time
-7
-6
2ns
0.8ns
20
08
-7
1ns
10
-6
1.5ns
15
-7
2ns
-6
0.8ns
20
08
-7
1ns
10
option
00
rev 1.2B
12
Check sum for -6
BA
Check sum for -7
21
Manufactures Jedec ID code per JEP-108E
MITSUBISHI
1CFFFFFFFFFFFFFF
Manufacturing location
Miyoshi,Japan
01
Tajima,Japan
02
NC,USA
03
Germany
04
Density of each bank on module
32
33
34
Data signal input setup time
Data signal input hold time
35
36-61
Superset Information (may be used in future)
62
SPD Revision
63
Checksum for bytes 0-62
64-71
72
73-90
Manufactures Part Number
91-92
MH32S64PFJ-6
4D48333253363450464A2D36202020202020
MH32S64PFJ-6L
4D48333253363450464A2D364C2020202020
MH32S64PFJ-7
4D48333253363450464A2D37202020202020
MH32S64PFJ-7L
4D48333253363450464A2D374C2020202020
Revision Code
PCB revision
yyww
rrrr
93-94
Manufacturing date
year/week code
95-98
Assembly Serial Number
serial number
ssssssss
99-125
Manufacture Specific Data
option
00
126
Intetl specification frequency
100MHz
64
127
Intel specification CAS# Latency support
128+
Unused storage locations
-6,-7
CL=2/3,AP,CK0,1
CF
open
00
The -6, -7 indicate also -6L, -7L.
MIT-DS-0337-0.2
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Preliminary Spec.
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MITSUBISHI LSIs
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
PIN FUNCTION
Input
Master Clock:All other inputs are referenced to the rising
edge of CK
CKE0
CKE1
Input
Clock Enable:CKE controls internal clock.When CKE is
low,internal clock for the following cycle is ceased. CKE is
also used to select auto / self refresh. After self refresh
mode is started, CKE E becomes asynchronous input.Self
refresh is maintained as long as CKE is low.
/S0, /S1
Input
Chip Select: When /S is high,any command means
No Operation.
/RAS,/CAS,/WE
Input
Combination of /RAS,/CAS,/WE defines basic commands.
Input
A0-12 specify the Row/Column Address in conjunction with
BA0,1.The Row Address is specified by A0-12.The Column
Address is specified by A0-8.A10 is also used to indicate
precharge option.When A10 is high at a read / write
command, an auto precharge is performed. When A10 is
high at a precharge command, both banks are precharged.
Input
Bank Address:BA0,1 is not simply BA.BA specifies the
bank to which a command is applied.BA0,1 must be set
with ACT,PRE,READ,WRITE commands
CLK0, CLK1
A0-12
BA0,1
DQ0-63
DQMB0-7
Vdd,Vss
Input/Output Data In and Data out are referenced to the rising edge
of CLK
Input
Din Mask/Output Disable:When DQMB is high in burst
write.Din for the current cycle is masked.When DQMB is
high in burst read,Dout is disabled at the next but one cycle.
Power Supply Power Supply for the memory mounted module.
SCL
Input
Serial clock for serial PD
SDA
Output
Serial data for serial PD
MIT-DS-0337-0.2
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Preliminary Spec.
MITSUBISHI LSIs
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MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
BASIC FUNCTIONS
The MH32S64PFJ provides basic functions,bank(row)activate,burst read / write,
bank(row) precharge,and auto / self refresh.
Each command is defined by control signals of /RAS,/CAS and /WE at CLK rising edge.
In addition to 3 signals,/S,CKE and A10 are used as chip select,refresh option,and
precharge option,respectively.
To know the detailed definition of commands please see the command truth table.
CK
/S
Chip Select : L=select, H=deselect
/RAS
Command
/CAS
Command
/WE
Command
CKE
Ref resh Option @ref resh
command
Precharge Option @precharge or read/write
command
A10
def ine basic commands
Activate(ACT) [/RAS =L, /CAS = /WE =H]
ACT command activates a row in an idle bank indicated by BA.
Read(READ) [/RAS =H,/CAS =L, /WE =H]
READ command starts burst read from the active bank indicated by BA.First output
data appears after /CAS latency. When A10 =H at this command,the bank is
deactivated after the burst read(auto-precharge,READA).
Write(WRITE) [/RAS =H, /CAS = /WE =L]
WRITE command starts burst write to the active bank indicated by BA. Total data
length to be written is set by burst length. When A10 =H at this command, the bank is
deactivated after the burst write(auto-precharge,WRITEA).
Precharge(PRE) [/RAS =L, /CAS =H,/WE =L]
PRE command deactivates the active bank indicated by BA. This command also
term inates burst read / write operation. When A10 =H at this command, both banks
are deactivated(precharge all, PREA).
Auto-Refresh(REFA) [/RAS =/CAS =L, /WE =CKE =H]
PEFA command starts auto-refresh cycle. Refresh address including bank address
are generated internally. After this command, the banks are precharged automatically.
MIT-DS-0337-0.2
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Preliminary Spec.
MITSUBISHI LSIs
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MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
COMMAND TRUTH TABLE
CKE CKE
n-1
n
/RAS /CAS
A0-9,
/WE BA0,1 A10 11-12 note
COMMAND
MNEMONIC
Deselect
No Operation
DESEL
NOP
H
H
X
X
H
L
X
H
X
H
X
H
X
X
X
X
X
X
ACT
H
X
L
L
H
H
V
V
V
Single Bank Precharge
Precharge All Bank
PRE
PREA
H
H
X
X
L
L
L
L
H
H
L
L
V
X
L
H
X
X
Column Address Entry
& Write
WRITE
H
X
L
H
L
L
V
L
V
Column Address Entry
& Write with AutoPrecharge
WRITEA
H
X
L
H
L
L
V
H
V
Column Address Entry
& Read
READ
H
X
L
H
L
H
V
L
V
Column Address Entry
& Read with Auto
Precharge
READA
H
X
L
H
L
H
V
H
V
Auto-Refresh
Self-Refresh Entry
Self-Refresh Exit
REFA
REFS
REFSX
Burst Terminate
Mode Register Set
TERM
MRS
H
H
L
L
H
H
H
L
H
H
X
X
L
L
H
L
L
L
L
L
X
H
H
L
L
L
X
H
H
L
H
H
X
H
L
L
X
X
X
X
X
L
X
X
X
X
X
L
X
X
X
X
X
V
Row Adress Entry &
Bank Activate
/S
1
H =High Level, L = Low Level, V = Valid, X = Don't Care, n = CLK cycle number
NOTE:
1.A7-8,11-12 = L, A0-6,A9 = Mode Address
MIT-DS-0337-0.2
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Preliminary Spec.
MITSUBISHI LSIs
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MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
FUNCTION TRUTH TABLE
/S
IDLE
H
L
X
H
X
H
X
H
X
X
DESEL
NOP
L
H
H
L
X
TBST
L
H
L
X
BA,CA,A10
L
L
H
H
BA,RA
ACT
L
L
H
L
L
L
L
H
BA,A10
X
PRE/PREA
REFA
ROW ACTIVE
READ
/RAS /CAS
/WE
Address
Command
Current State
Op-Code,
Action
NOP
NOP
ILLEGAL*2
READ/WRITE ILLEGAL*2
Bank Active,Latch RA
NOP*4
Auto-Refresh*5
L
L
L
L
H
X
X
X
X
DESEL
NOP
L
H
H
H
X
NOP
NOP
L
H
H
L
X
TBST
NOP
L
H
L
H
BA,CA,A10
L
H
L
L
BA,CA,A10
L
L
H
H
BA,RA
ACT
Bank Active/ILLEGAL*2
L
L
H
L
BA,A10
PRE/PREA
Precharge/Precharge All
L
L
L
H
X
L
L
L
L
H
X
X
X
X
DESEL
NOP(Continue Burst to END)
L
H
H
H
X
NOP
NOP(Continue Burst to END)
L
H
H
L
X
TBST
Terminate Burst
Mode-Add
Op-Code,
Mode-Add
MRS
READ/READA
Mode Register Set*5
Begin Read,Latch CA,
Determine Auto-Precharge
WRITE/
Begin Write,Latch CA,
WRITEA
Determine Auto-Precharge
REFA
ILLEGAL
MRS
ILLEGAL
Terminate Burst,Latch CA,
L
H
L
H
BA,CA,A10
READ/READA Begin New Read,Determine
Auto-Precharge*3
Terminate Burst,Latch CA,
L
H
L
L
BA,CA,A10 WRITE/WRITEA Begin Write,Determine AutoPrecharge*3
MIT-DS-0337-0.2
L
L
H
H
BA,RA
ACT
L
L
H
L
BA,A10
PRE/PREA
L
L
L
H
X
L
L
L
L
Op-Code,
Mode-Add
Bank Active/ILLEGAL*2
Terminate Burst,Precharge
REFA
ILLEGAL
MRS
ILLEGAL
MITSUBISHI
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26.Apr.2001
Preliminary Spec.
MITSUBISHI LSIs
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notice.
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
FUNCTION TRUTH TABLE(continued)
Current State
/S
/RAS /CAS
/WE
Address
WRITE
H
L
L
X
H
H
X
H
H
X
H
L
X
X
X
L
H
L
H
BA,CA,A10
Command
NOP(Continue Burst to END)
NOP(Continue Burst to END)
Terminate Burst
Terminate Burst,Latch CA,
READ/READA Begin Read,Determine AutoPrecharge*3
WRITE/
L
H
L
L
BA,CA,A10
L
L
H
H
BA,RA
ACT
L
L
L
L
H
L
L
H
BA,A10
X
PRE/PREA
REFA
L
L
L
L
H
L
L
L
X
H
H
H
X
H
H
L
X
H
L
H
Op-Code,
Mode-Add
X
X
X
BA,CA,A10
L
H
L
L
BA,CA,A10
L
L
H
H
BA,RA
L
L
L
L
H
L
L
H
L
L
L
L
WRITE with
H
X
X
X
BA,A10
X
Op-Code,
Mode-Add
X
AUT O
PRECHARGE
L
L
L
H
H
H
H
H
L
H
L
H
X
L
H
L
L
BA,CA,A10
L
L
L
L
L
L
H
H
L
H
L
H
BA,RA
L
L
L
L
READ with
AUT O
PRECHARGE
MIT-DS-0337-0.2
X
BA,CA,A10
BA,A10
X
Action
DESEL
NOP
TBST
WRITEA
MRS
DESEL
NOP
TBST
READ/READA
WRITE/
WRITEA
ACT
PRE/PREA
REFA
MRS
Terminate Burst,Latch CA,
Begin Write,Determine AutoPrecharge*3
Bank Active/ILLEGAL*2
Terminate Burst,Precharge
ILLEGAL
ILLEGAL
NOP(Continue Burst to END)
NOP(Continue Burst to END)
ILLEGAL
ILLEGAL
ILLEGAL
Bank Active/ILLEGAL*2
ILLEGAL*2
ILLEGAL
ILLEGAL
DESEL
NOP(Continue Burst to END)
NOP
TBST
READ/READA
WRITE/
WRITEA
NOP(Continue Burst to END)
ILLEGAL
ILLEGAL
ACT
PRE/PREA
REFA
Op-Code,
Mode-Add
MITSUBISHI
ELECTRIC
( 10 / 55 )
MRS
ILLEGAL
Bank Active/ILLEGAL*2
ILLEGAL*2
ILLEGAL
ILLEGAL
26.Apr.2001
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without
notice.
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
FUNCTION TRUTH TABLE(continued)
/S
PRE -
H
X
X
X
X
DESEL
NOP(Idle after tRP)
CHARGING
L
H
H
H
X
NOP
NOP(Idle after tRP)
L
H
H
L
X
TBST
ILLEGAL*2
L
H
L
X
BA,CA,A10
L
L
H
H
BA,RA
ACT
L
L
H
L
BA,A10
PRE/PREA
L
L
L
H
X
L
L
L
L
ROW
H
X
X
X
X
DESEL
NOP(Row Active after tRCD
ACT IVATING
L
H
H
H
X
NOP
NOP(Row Active after tRCD
L
H
H
L
X
TBST
ILLEGAL*2
L
H
L
X
BA,CA,A10
L
L
H
H
BA,RA
ACT
ILLEGAL*2
L
L
H
L
BA,A10
PRE/PREA
ILLEGAL*2
L
L
L
H
X
L
L
L
L
WRITE RE-
H
X
X
X
X
DESEL
NOP
COVERING
L
H
H
H
X
NOP
NOP
L
H
H
L
X
TBST
ILLEGAL*2
L
H
L
X
BA,CA,A10
L
L
H
H
BA,RA
ACT
ILLEGAL*2
L
L
H
L
BA,A10
PRE/PREA
ILLEGAL*2
L
L
L
H
X
L
L
L
L
MIT-DS-0337-0.2
/RAS /CAS
/WE
Address
Command
Current State
Action
READ/WRITE ILLEGAL*2
Op-Code,
Mode-Add
ILLEGAL*2
NOP*4(Idle after tRP)
REFA
ILLEGAL
MRS
ILLEGAL
READ/WRITE ILLEGAL*2
Op-Code,
Mode-Add
REFA
ILLEGAL
MRS
ILLEGAL
READ/WRITE ILLEGAL*2
Op-Code,
Mode-Add
MITSUBISHI
ELECTRIC
( 11 / 55 )
REFA
ILLEGAL
MRS
ILLEGAL
26.Apr.2001
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without
notice.
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
FUNCTION TRUTH TABLE(continued)
Current State
/S
/RAS /CAS
/WE
Address
Command
Action
RE-
H
X
X
X
X
DESEL
NOP(Idle after tRC)
FRESHING
L
H
H
H
X
NOP
NOP(Idle after tRC)
L
H
H
L
BA
TBST
ILLEGAL
L
H
L
X
BA,CA,A10
L
L
H
H
BA,RA
ACT
ILLEGAL
L
L
H
L
BA,A10
PRE/PREA
ILLEGAL
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
MRS
ILLEGAL
MODE
H
X
X
X
X
DESEL
NOP(Idle after tRSC)
REGISTER
L
H
H
H
X
NOP
NOP(Idle after tRSC)
SETTING
L
H
H
L
BA
TBST
ILLEGAL
L
H
L
X
BA,CA,A10
L
L
H
H
BA,RA
ACT
ILLEGAL
L
L
H
L
BA,A10
PRE/PREA
ILLEGAL
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
MRS
ILLEGAL
READ/WRITE ILLEGAL
Op-Code,
Mode-Add
READ/WRITE ILLEGAL
Op-Code,
Mode-Add
ABBREVIATIONS:
H = Hige Level, L = Low Level, X = Don't Care
BA = Bank Address, RA = Row Address, CA = Column Address, NOP = No Operation
NOTES:
1. All entries assume that CKE was High during the preceding clock cycle and the current
clock cycle.
2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA,
depending on the state of that bank.
3. Mus t satisfy bus contention, bus turn around, write recovery requirements.
4. NOP to bank precharging or in idle state.May precharge bank indicated by BA.
5. ILLEGAL if any bank is not idle.
ILLEGAL = Device operation and / or date-integrity are not guaranteed.
MIT-DS-0337-0.2
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ELECTRIC
( 12 / 55 )
26.Apr.2001
Preliminary Spec.
MITSUBISHI LSIs
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notice.
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
FUNCTION TRUTH TABLE FOR CKE
Current State
CK
n-1
CK
n
/S
SELF -
H
X
X
X
REFRESH*1
L
H
H
L
H
L
/RAS /CAS
Action
/WE
Add
X
X
X
INVALID
X
X
X
X
Exit Self-Refresh(Idle after tRC)
L
H
H
H
X
Exit Self-Refresh(Idle after tRC)
H
L
H
H
L
X
ILLEGAL
L
H
L
H
L
X
X
ILLEGAL
L
H
L
L
X
X
X
ILLEGAL
L
L
X
X
X
X
X
NOP(Maintain Self-Refresh)
POWER
H
X
X
X
X
X
X
INVALID
DOWN
L
H
X
X
X
X
X
Exit Power Down to Idle
L
L
X
X
X
X
X
NOP(Maintain Self-Refresh)
ALL BANKS
H
H
X
X
X
X
X
Refer to Function Truth Table
IDLE*2
H
L
L
L
L
H
X
Enter Self-Refresh
H
L
H
X
X
X
X
Enter Power Down
H
L
L
H
H
H
X
Enter Power Down
H
L
L
H
H
L
X
ILLEGAL
H
L
L
H
L
X
X
ILLEGAL
H
L
L
L
X
X
X
ILLEGAL
L
X
X
X
X
X
X
Refer to Current State = Power Down
ANY STATE
H
H
X
X
X
X
X
Refer to Function Truth Table
other than
H
L
X
X
X
X
X
Begin CK0 Suspend at Next Cycle*3
listed above
L
H
X
X
X
X
X
Exit CK0 Suspend at Next Cycle*3
L
L
X
X
X
X
X
Maintain CK0 Suspend
ABBREVIATIONS:
H = High Level, L = Low Level, X = Don't Care
NOTES:
1. CKE Low to High transition will re-enable CK and other inputs asynchronously.
A minimum setup time must be satisfied before any command other than EXIT.
2. Power-Down and Self-Refresh can be entered only form the All banks idle State.
3. Mus t be legal command.
MIT-DS-0337-0.2
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ELECTRIC
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26.Apr.2001
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without
notice.
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
SIMPLIFIED STATE DIAGRAM
SELF
REFRESH
REFS
REFSX
MRS
MODE
REGISTER
SET
REFA
AUTO
REFRESH
IDLE
CKEL
CKEH
CLK
SUSPEND
ACT
POWER
DOWN
CKEL
CKEH
ROW
ACTIVE
WRITE
READA
WRITEA
CKEL
WRITE
SUSPEND
READ
READ
WRITE
WRITE
CKEL
READ
CKEH
CKEH
WRITEA
READA
WRITEA
READA
CKEL
WRITEA
SUSPEND
CKEL
PRE
WRITEA
READA
CKEH
PRE
POWER
APPLIED
READ
SUSPEND
POWER
ON
PRE
PRE
CKEH
READA
SUSPEND
PRE
CHARGE
Automatic Sequence
Command Sequence
MIT-DS-0337-0.2
MITSUBISHI
ELECTRIC
( 14 / 55 )
26.Apr.2001
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without
notice.
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
POWER ON SEQUENCE
Before s tarting normal operation, the following power on sequence is necessary to prevent
a SDRAM from damaged or malfunctioning.
1. Clock will be applied at power up along with power.Attempt to maintain CKE high,DQM0-7
high and NOP condition at the inputs along with power.
2. Maintain s table power, stable cock, and NOP input conditions for a m inimum of 200us.
3. Issue precharge commands for all banks. (PRE or PREA)
4. After all banks become idle state (after tRP), issue 8 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
After these sequence, the SDRAM is idle state and ready for normal operation.
MODE REGISTER
Burst Length, Burst Type and /CAS Latency can be programmed by setting the mode
register(MRS). The mode register stores these date until the next MRS command, which
may be issued when both banks are in idle state. After tRSC from a MRS command, the
SDRAM is ready for new command.
CK
/S
A12 BA0 BA1 A11 A10 A9
A8
A7 A6
A5
A4 A3
A2
A1 A0
/RAS
/CAS
0
0
0
0
0
WM
0
0
LTMODE
BT
BL
/WE
BA0,1 A12-0
LATENCY
MODE
0
0
0
0
1
1
1
1
WRITE
MODE
MIT-DS-0337-0.2
CL
00
01
10
11
00
01
10
11
0
1
/CAS LATENCY
R
R
2
3
R
R
R
R
BURST
SINGLE BIT
BURST
LENGTH
BURST
TYPE
V
BL
BT= 0
BT= 1
0
0
1
1
0
0
1
0
1
0
1
2
4
8
R
1
2
4
8
R
101
110
111
R
R
FP
R
R
R
0
0
0
0
1
0
1
SEQUENTIAL
INTERLEAVED
R:Reserved for Future Use
FP: Full Page
MITSUBISHI
ELECTRIC
( 15 / 55 )
26.Apr.2001
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without
notice.
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
[ /CAS LATENCY]
/CAS latency,CL,is used to synchronize the first output data with the CLK
frequency,i.e.,the speed of CLK determines which CL should be used.First output data is
available after CL cycles from READ command.
/CAS Latency Timing(BL=4)
CK
ACT
Command
READ
tRCD
Y
X
Address
CL=2
DQ
Q0
Q1
Q2
Q3
Q0
Q1
Q2
CL=2
CL=3
DQ
CL=3
Q3
[ BURST LENGTH ]
The burst length,BL,determines the number of consecutive wrutes or reads that will be
automatically performed after the initial write or read command.For BL=1,2,4,8,full page
the output data is tristated(Hi-Z) after the last read.For BL=FP (Full Page),the TBST (Burs t
Terminate) command should be issued to stop the output of data.
Burst Length Timing(CL=2)
tRCD
CK
Command
Address
ACT
READ
X
Y
DQ
Q0
DQ
Q0
Q1
DQ
Q0
Q1 Q2
Q3
DQ
Q0
Q1 Q2
Q3
Q4 Q5
Q6
Q7
DQ
Q0
Q1 Q2
Q3
Q4 Q5
Q6
Q7
BL=1
BL=2
BL=4
m=511
MIT-DS-0337-0.2
MITSUBISHI
ELECTRIC
( 16 / 55 )
BL=8
Q8
Qm
Q0
Q1
BL=FP
Full Page counter rolls over
and continues to count.
26.Apr.2001
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without
notice.
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
CK
Command
Read
Write
Y
Y
Address
Q0
DQ
CL= 3
BL= 4
Q1
Q2
D0
Q3
D1
D2
D3
/CAS Latency
Burst Length
Initial Address BL
Burst Type
Burst Length
Column Addressing
A2
A1
A0
0
0
0
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
0
1
1
2
3
4
5
6
7
0
1
0
3
2
5
4
7
6
0
1
0
2
3
4
5
6
7
0
1
2
3
0
1
6
7
4
5
0
1
1
3
4
5
6
7
0
1
2
3
2
1
0
7
6
5
4
Sequential
Interleaved
8
1
0
0
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
1
0
1
5
6
7
0
1
2
3
4
5
4
7
6
1
0
3
2
1
1
0
6
7
0
1
2
3
4
5
6
7
4
5
2
3
0
1
1
1
1
7
0
1
2
3
4
5
6
7
6
5
4
3
2
1
0
-
0
0
0
1
2
3
0
1
2
3
-
0
1
1
2
3
0
1
0
3
2
4
-
1
0
2
3
0
1
2
3
0
1
-
1
1
3
0
1
2
3
2
1
0
-
-
0
0
1
0
1
1
0
1
0
2
-
-
1
MIT-DS-0337-0.2
MITSUBISHI
ELECTRIC
( 17 / 55 )
26.Apr.2001
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without
notice.
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
OPERATION DESCRIPTION
BANK ACTIVATE
One of four banks is activated by an ACT command.
An bank is selected by BA0-1. A row is selected by A0-12.
Multiple banks can be active state concurrently by issuing multiple ACT commands.
Minimum activation interval between one bank and another bank is tRRD.
PRECHARGE
An open bank is deactivated by a PRE command.
A bank to be deactivated is designated by BA0-1.
When multiple banks are active, a precharge all command (PREA, PRE + A10=H) deactivates all of open
banks at the same time. BA0-1 are "Don't Care" in this case.
Minimum delay time of an ACT command after a PRE command to the same bank is tRP.
Bank Activation and Precharge All (BL=4, CL=3)
CK
Command ACT
ACT
READ
ACT
tRP
A0-9,11-12
Xa
Xb
Yb
A10
Xa
Xb
0
BA0,1
00
01
01
DQ
PRE
tRCD
tRRD
Xa
Xa
1
00
Qa0
Qa1
Qa2
Qa3
Precharge all
READ
A READ command can be issued to any active bank. The start address is specified by A0-8
(x16) . 1s t output data is available after the /CAS Latency from the READ. The consecutive
data length is defined by the Burst Length. The address sequence of the burst data is
defined by the Burst Type. Minimum delay time of a READ command after an ACT command
to the same bank is tRCD.
When A10 is high at a READ command, auto-precharge (READA) is performed. Any
command (READ, WRITE, PRE, ACT, TBST) to the same bank is inhibited till the internal
precharge is complete. The internal precharge starts at the BL after READA. The next ACT
command can be issued after (BL + tRP) from the previous READA. In any case, tRCD+BL >
tRASmin must be met.
MIT-DS-0337-0.2
MITSUBISHI
ELECTRIC
( 18 / 55 )
26.Apr.2001
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without
notice.
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
Multi Bank Interleaving READ (BL=4, CL=2)
CK
Command ACT
READ
ACT
tRCD
A0-9, 11-12
A10
BA0,1
READ PRE
tRCD
tRCD
Xa
Ya
Xb
Yb
Xa
0
Xb
0
0
00
01
01
00
Qa2
Qa3
00
DQ
Qa0
Qa1
ACT
Xa
Xa
00
Qb0
Qb1
Qb2
READ with Auto-Precharge (BL=4, CL=2)
CK
Command ACT
READ
tRCD
ACT
tRP
BL
A0-9, 11-12
Xa
Ya
Xa
A10
Xa
1
Xa
00
00
BA0,1
00
DQ
Qa0
Qa1
Qa2
Qa3
Internal precharge starts
READ Auto-Precharge Timing (BL=4)
CK
Command ACT
READ
tRCD
CL=3
DQ
CL=2
DQ
ACT
BL
Qa0
Qa0
Qa1
Qa2
Qa1
Qa2
Qa3
Qa3
Internal Precharge Start Timing
MIT-DS-0337-0.2
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ELECTRIC
( 19 / 55 )
26.Apr.2001
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without
notice.
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
WRITE
A WRITE command can be issued to any active bank. The start address is specified by A0-8
(x16). 1st input data is set at the same cycle as the WRITE. The consecutive data length to
be written is defined by the Burst Length. The address sequence of burst data is defined by
the Burst Type. Minimum delay time of a WRITE command after an ACT command to the
same bank is tRCD. From the last input data to the PRE command, the write recovery time
(tWR) is required. When A10 is high at a WRITE command, auto-precharge (WRITEA) is
performed. Any command (READ, WRITE, PRE, ACT, TBST) to the same bank is inhibited till
the internal precharge is complete. The internal precharge starts at tWR after the last input
data cycle. The next ACT command can be issued after (BL + tWR -1 + tRP) from the
previous WRITEA. In any case, tRCD + BL + tWR -1 > tRASmin must be met.
WRITE (BL=4)
CK
Command ACT
Write
PRE
tRCD
BL
Xa
Ya
A10
Xa
0
BA0,1
00
00
A0-9, 11-12
ACT
tRP
Xa
0
Xa
00
tWR
DQ
Da0
Da1
Da2
Da3
WRITE with Auto-Precharge (BL=4)
CK
Command ACT
Write
ACT
tRP
tRCD
A0-9, 11-12
A10
BA0,1
Xa
Ya
Xa
Xa
1
Xa
00
00
00
tWR
DQ
Da0
Da1
Da2
Da3
Internal precharge begins
MIT-DS-0337-0.2
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26.Apr.2001
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without
notice.
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
BURST INTERRUPTION
[ Read Interrupted by Read ]
Burst read option can be interrupted by new read of the same or the other bank. Random
column access is allowed READ to READ interval is minimum 1 CK
Read Interrupted by Read (BL=4, CL=2)
CK
Command
READ
A0-9,11-12
READ READ
Ya
Yb
Yc
A10
0
0
0
BA0,1
00
00
10
Qa1
Qa2
DQ
Qa0
Qb0
Qc0
Qc1
Qc2
Qc3
[ Read Interrupted by Write ]
Burs t read operation can be interrupted by write of the same or the other bank. Random
column access is allowed. In this case, the DQ should be controlled adequately by us ing the
DQMB0-7 to prevent the bus contention. The output is disabled automatically 2 cycle after
WRITE assertion.
Read Interrupted by Write (BL=4, CL=2)
CK
Command ACT
READ
Write
A0-9,11-12
Xa
Ya
Ya
A10
Xa
0
0
00
00
BA0,1
00
DQMB0-7
DQ
Qa0
Da0
Da1
Output disable by DQM
MIT-DS-0337-0.2
Da2
Da3
by WRITE
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ELECTRIC
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26.Apr.2001
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without
notice.
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
[ Read Interrupted by Precharge ]
Burs t read operation can be interrupted by precharge of the same or the other bank.
Read to PRE interval is minimum 1 CK. A PRE command output disable latency is
equivalent to the /CAS Latency.As a result, READ to PRE interval determines valid data
length to be output.The figure below shows examples of BL=4.
Read Interrupted by Precharge (BL=4)
CK
Command
READ
PRE
DQ
Q0
Q1
Q0
Q1
Q2
CL=3
Command
READ
PRE
DQ
Command
READ PRE
DQ
Command
Q0
PRE
READ
DQ
Q0
Q1
Q2
CL=2
Command
READ
DQ
Command
DQ
MIT-DS-0337-0.2
PRE
Q0
Q1
READ PRE
Q0
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ELECTRIC
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26.Apr.2001
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without
notice.
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
[ Read Interrupted by Burst Terminate ]
Similarly to the precharge, burst terminate command,TBST, can interrupt burst read
operation and disable the data output. READ to TBST interval is minimum of 1 CK. TBST
is mainly used to interrupt FP bursts.The figure below show examples, of how the output
data is terminated with TBST.
Read Interrupted by Terminate (BL=4)
CK
Command
READ
TBST
DQ
Command
CL=3
READ
CL=2
TBST
READ
DQ
MIT-DS-0337-0.2
Q0
Q1
Q2
TBST
READ
DQ
Command
Q1
Q0
DQ
Command
Q0
Q2
READ TBST
DQ
Command
Q1
TBST
DQ
Command
Q0
Q0
Q1
READ TBST
Q0
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ELECTRIC
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26.Apr.2001
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without
notice.
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
[ Write Interrupted by Write ]
Burs t write operation can be interrupted by new write of the same or the other bank.
Random column access is allowed. WRITE to WRITE interval is minimum 1 CK.
Write Interrupted by Write (BL=4)
CK
Command
Write
A0-9, 11-12
Ya
Write Write
Yb
Yc
A10
0
0
0
BA0,1
00
00
10
DQ
Da0
Db0
Dc0
Da1
Da2
Dc1
Dc2
Dc3
[ Write Interrupted by Read ]
Burs t write operation can be interrupted by read of the same or the other bank.
Random column access is allowed. WRITE to READ interval is minimum 1 CK. The
input data on DQ at the interrupting READ cycle is "don't care".
Write Interrupted by Read (BL=4, CL=2)
CK
Command ACT
A0-9,11-12
Write
READ
Xa
Ya
Yb
A10
Xa
0
0
BA0,1
00
00
00
DQ
Da0
Da1
Qb0
Qb1
Qb2
Qb3
don't care
MIT-DS-0337-0.2
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ELECTRIC
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26.Apr.2001
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without
notice.
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
[ Write Interrupted by Precharge ]
Burs t write operation can be interrupted by precharge of the same bank. Random
column access is allowed. Because the write recovery time(tWR) is required from
the last data to PRE command.
Write Interrupted by Precharge (BL=4)
CK
Command
ACT
Write
PRE
ACT
tRP
A0-9,11-12
Xa
Ya
Xa
A10
0
0
0
0
BA0,1
00
00
00
00
DQMB0-7
tWR
DQ
Da0
Da1
[ Write Interrupted by Burst Terminate ]
A burs t terminate command TBST can terminate burst write operation. In this case,
the write recovery time is not required and the bank remains active (Please see the
waveforms below).The WRITE to TBST minimum interval is 1CK.
Write Interrupted by Burst Terminate (BL=4)
CK
Command
ACT
Write
A0-9,11-12
Xa
Ya
Yb
A10
0
0
0
BA0,1
00
00
00
DQ
MIT-DS-0337-0.2
Da0
TBST
Da1
Write
Db0
Db1
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ELECTRIC
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Db2
Db3
26.Apr.2001
Preliminary Spec.
Some contents are subject to change without
notice.
MITSUBISHI LSIs
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
AUTO REFRESH
Single cycle of auto-refresh is initiated with a REFA(/CS=/RAS=/CAS=L,
/WE=/CKE=H) command. The refresh address is generated internally. 4096 REFA
cycle within 64ms refresh 128Mbit memory cells. The auto-refresh is performed on
4bank alternately(ping-pong refresh). Before performing an auto-refresh, both banks
must be in the idle state. Additional commands must not be supplied to the device
before tRC from the REFA command.
Auto-Refresh
CK
/S
NOP or DESLECT
/RAS
/CAS
/WE
CKE
minimum tRC
A0-12
BA0,1
Auto Refresh on All Banks
MIT-DS-0337-0.2
Auto Refresh on All Banks
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26.Apr.2001
Preliminary Spec.
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MITSUBISHI LSIs
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
SELF REFRESH
Self-refresh mode is entered by issuing a REFS command (/CS=/RAS=/CAS=L,
/WE=H, CKE=L). Once the self-refresh is initiated, it is maintained as log as CKE is
kept low.During the self-refresh mode, CKE is asynchronous and the only enabled
input , all other inputs including CK are disabled and ignored, so that power
consumption due to synchronous inputs is saved. To exit the self-refresh, supplying
stable CK inputs, asserting DESEL or NOP command and then asserting
CKE(REFSX) for longer than tSRX. After tRC from REFSX all banks are in the idle
state and a new command can be issued after tRC, but DESEL or NOP commands
must be asserted till then.
Self-Refresh
CK
Stable CK
/S
NOP
/RAS
/CAS
/WE
CKE
new command
A0-11
X
BA0,1
00
Self Refresh Entry
MIT-DS-0337-0.2
Self Refresh Exit
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ELECTRIC
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minimum tRFC
for recovery
26.Apr.2001
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without
notice.
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
CLK SUSPEND and POWER DOWN
CKE controls the internal CLK at the following cycle. Figure below shows how CKE
works. By negating CKE, the next internal CLK is suspended. The purpose of CLK
suspend is power down, output suspend or input suspend. CKE is a synchronous
input except during the self-refresh mode. CLK suspend can be performed either
when the banks are active or idle, but a command at the following cycle is ignored.
CK
(ext.CLK)
tIH
tIS
tIH
tIS
CKE
int.CLK
Power Down by CKE
CK
Standby Power Down
CKE
Command
PRE
NOP NOP
NOP
Activ e Power Down
CKE
Command
ACT
NOP NOP
NOP
DQ Suspend by CKE
CK
CKE
Command
DQ
MIT-DS-0337-0.2
Write
D0
READ
D1
D2
D3
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Q0
Q1
Q2
Q3
26.Apr.2001
Preliminary Spec.
MITSUBISHI LSIs
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notice.
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
DQM CONTROL
DQMB0-7 is a dual function signal defined as the data mask for writes and the
output disable for reads. During writes, DQMB0-7 masks input data word by word.
DQMB0-7 to write mask latency is 0.
During reads, DQMB0-7 forces output to Hi-Z word by word. DQMB0-7 to output Hi-Z
latency is 2.
DQM Function
CK
Command
READ
Write
DQMB0-7
DQ
D0
D2
D3
Q0
masked by DQMU/L=H
MIT-DS-0337-0.2
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ELECTRIC
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Q1
Q3
disabled by DQMU/L=H
26.Apr.2001
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without
notice.
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Condition
Ratings
Unit
Vdd
Supply Voltage
with respect to Vss
-0.5 ~ 4.6
V
VI
Input Voltage
with respect to Vss
-0.5 ~ Vdd+0.5
V
VO
Output Voltage
with respect to Vss -0.5 ~ VddQ+0.5
IO
Output Current
Pd
Power Dissipation
Topr
Tstg
V
50
mA
8
W
Operating Temperature
0 ~ 70
°C
Storage Temperature
-40 ~ 100
°C
Ta=25°C
RECOM M ENDED OPERATING CONDITION
(Ta=0 ~ 70°C, unless otherwise noted)
Limits
Parameter
Symbol
Min.
Typ.
Max.
Unit
Vdd
Supply Voltage
3.0
3.3
3.6
V
Vss
Supply Voltage
0
0
0
V
VIH
High-Level Input Voltage all inputs
2.0
Vdd+0.3
V
VIL
Low-Level Input Voltage all inputs
-0.3
0.8
V
Note:* VIH (max) = 5.5V for pulse width less than 10ns.
VIL (min) = -1.0V for pulse width less than 10ns.
CAPACITANCE
(Ta=0 ~ 70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)
Symbol
Parameter
CI(A)
Input Capacitance, address pin
CI(C)
Input Capacitance, control pin
Test Condition
CI(K)
Input Capacitance, CK pin
CI/O
Input Capacitance, I/O pin
MIT-DS-0337-0.2
VI = Vss
f=1MHz
Vi=25mVrm s
MITSUBISHI
ELECTRIC
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Limits(max.)
Unit
58
pF
50
pF
40
pF
22
pF
26.Apr.2001
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without
notice.
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
AVERAGE SUPPLY CURRENT from Vdd
(Ta=0 ~70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, Output Open, unless otherwise noted)
Symbol
Parameter
Limits
(max)
Test Condition
-6,-6L
-7,-7L
Unit Note
Operating current
one bank active (discrete)
Icc1
tRC=min.tCLK=min, BL=1, CL=3
500
440
mA *1
Idle Standby Current in
Normal Mode
Icc2N
tCLK=min, CKE>VIHmin
200
160
Icc2NS tCLK=L, CKE>VIHmin
48
48
mA *2,3
mA *2,4
Idle Standby Current in
Power Down Mode
Icc2P
tCLK=min, CKE<VILmax
Icc2PS CLK= L, CKE<VILmax
12
8
8
8
Active Standby Current
in Normal Mode
Icc3N tCLK=min, CKE>VIHmin
Icc3NS CLK=L, CKE=>VIHmin
240
120
200
120
Burst Operating Current
Icc4
580
1440
24
480
1360
24
16
16
tCLK=min, BL=4, gapless data
Auto-Refresh Current
Icc5
tRFC=min, tCLK=min
Self-Refresh Current
Icc6
CKE <VILmax
6,7
6L,7L
mA
mA
*2
mA *3,5
mA *4,5
mA
*5
mA
mA
mA
Notes
1. addresses are charged 3 times during tRC, only 1 bank is active & all other banks are idle
2. all banks are idle
3. input signals are charged one time during 3xtCLK
4. input signals are stable
5. all banks are active
AC OPERATING CONDITIONS AND CHARACTERISTICS
(Ta=0 ~ 70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)
Symbol
VOH(DC)
VOL(DC)
VOH(AC)
IOZ
VOL(AC)
Ii
Limits
Unit
Min. Max.
High-Level Output Voltage(DC) IOH=-2mA
2.4
V
Low-Level Output Voltage(DC) IOL=2mA
0.4
V
20 uA
Off-stare
High-Level
Output
Output
Current
Voltage(AC) Q
CL=50pF,
floating VO=0
IOH=- ~ Vdd -20
2
V
2mA
Input
Current
-80 0.8
80 uA
Low-Level
Output Voltage(AC) CL=50pF,
VIH=0 ~ Vdd+0.3V
IOL=2mA
V
MIT-DS-0337-0.2
Parameter
Test Condition
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26.Apr.2001
Preliminary Spec.
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MITSUBISHI LSIs
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
AC TIMING REQUIREMENTS (SDRAM Component)
(Ta=0 ~ 70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)
Input Pulse Levels:
0.8V to 2.0V
Input Timing Measurement Level: 1.4V
Limits
-6,-6L
Min.
Max.
Symbol Parameter
tCLK
CK cycle time
tCH CK High pulse width
tCL CK Low pilse width
tT
Transition time of CK
tIS
Input Setup time(all inputs)
Input Hold time(all inputs)
tIH
tRC Row cycle time
tRFC Refresh Cycle tim e
tRCD Row to Column Delay
tRAS Row Active time
tRP Row Precharge time
tWR Write Recovery time
tRRD Act to Act Deley tim e
tRSC Mode Register Set Cycle time
tREF
-7,-7L
Min. Max.
Unit
CL=2
10
10
ns
CL=3
7.5
2.5
2.5
1
1.5
0.8
67.5
75
20
45
20
15
15
15
10
3
3
1
2
1
70
80
20
50
20
20
20
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
Refresh Interval time
10
120K
7.8
1.4V
CLK
10
120K
7.8
Any AC timing is
referenced to the input
1.4V
Signal
signal crossing through
1.4V.
MIT-DS-0337-0.2
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Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without
notice.
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
SWITCHING CHARACTERISTICS (SDRAM Component)
(Ta=0 ~ 70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)
Limits
-6,-6L
-7,-7L
Unit
Min. Max. Min. Max.
Symbol Parameter
tAC
tOH
tOLZ
tOHZ
Access time from CK
CL=2
6
6
ns
CL=3
5.4
6
ns
Output Hold time
from CK
Delay time, output low
impedance from CK
Delay time, output high
impedance from CK
3
3
ns
0
0
ns
3
6
3
6
ns
Output Load
Condition
CK
1.4V
DQ
1.4V
V OUT
50pF
Output Timing
Measurement
Reference Point
CK
1.4V
DQ
1.4V
tAC
MIT-DS-0337-0.2
tOH
tOHZ
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Preliminary Spec.
MITSUBISHI LSIs
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MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
Burst Write (single bank) @BL=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
tRC
/CS
tRAS
tRP
/RAS
tRCD
tRCD
/CAS
/WE
tWR
CKE
DQM
A0-9,11
X
Y
A10
X
X
A12
X
X
BA0,1
0
0
D0
DQ
ACT#0
X
0
D0
WRITE#0
D0
0
D0
Y
0
D0
PRE#0
ACT#0
D0
D0
D0
WRITE#0
Italic parameter indicates minimum case
MIT-DS-0337-0.2
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26.Apr.2001
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without
notice.
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
Burst Write (multi bank) @BL=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
tRC
/CS
tRRD
tRRD
tRAS
tRP
/RAS
tRCD
tRCD
/CAS
/WE
tWR
tWR
CKE
DQM
A0-9,11
X
X
A10
X
A12
BA0,1
Y
X
X
X
X
X
X
X
X
X
0
1
0
D0
DQ
ACT#0
Y
D0
WRITE#0
ACT#1
D0
D0
1
0
D1
D1
0
D1
PRE#0
WRITE#1
D1
1
2
Y
0
D0
ACT#0
D0
D0
D0
ACT#2 WRITE#0
PRE#1
Italic parameter indicates minimum case
MIT-DS-0337-0.2
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26.Apr.2001
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without
notice.
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
Burst Read (single bank) @BL=4 CL=3
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
tRC
/CS
tRAS
tRP
/RAS
tRCD
tRCD
/CAS
/WE
CKE
DQM
DQM read latency =2
A0-9,11
X
A10
X
X
A12
X
X
BA0,1
0
Y
X
0
0
0
Y
0
CL=3
Q0
DQ
ACT#0
READ#0
Q0
Q0
Q0
PRE#0
Q0
ACT#0
Q0
READ#0
READ to PRE ≥BL allows full data out
Italic parameter indicates minimum case
MIT-DS-0337-0.2
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Preliminary Spec.
MITSUBISHI LSIs
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MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
Burst Read (multiple bank) @BL=4 CL=3
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
tRC
/CS
tRRD
tRRD
tRAS
tRP
/RAS
tRCD
tRCD
/CAS
/WE
CKE
DQM
DQM read latency =2
A0-9,11
X
X
A10
X
A12
BA0,1
Y
Y
X
X
X
X
X
X
X
X
X
0
1
0
1
CL=3
ACT#0
READ#0
ACT#1
0
1
2
Q1
Q1
Q1
0
CL=3
Q0
DQ
0
Y
Q0
Q0
Q0
PRE#0
READ#1
Q1
Q0
ACT#0
READ#0
PRE#1 ACT#2
Italic parameter indicates minimum case
MIT-DS-0337-0.2
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Preliminary Spec.
MITSUBISHI LSIs
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MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
Burst Write (multi bank) with Auto-Precharge @BL=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
tRC
/CS
tRRD
tRRD
/RAS
tRCD
tRCD
tRCD
/CAS
BL-1+ tWR + tRP
BL-1+ tWR + tRP
/WE
CKE
DQM
A0-9,11
X
X
A10
X
X
X
X
A12
X
X
X
X
BA0,1
0
1
Y
0
D0
DQ
ACT#0
ACT#1
Y
X
1
D0
D0
D0
WRITE#0 with
AutoPrecharge
D1
D1
D1
Y
X
0
0
1
D1
D0
D0
ACT#0
WRITE#1 with
AutoPrecharge
Y
1
D0
WRITE#0
ACT#1
D0
D1
WRITE#1
Italic parameter indicates minimum case
MIT-DS-0337-0.2
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Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without
notice.
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
Burst Read (multiple bank) with Auto-Precharge @BL=4 CL=3
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
tRC
/CS
tRRD
tRRD
/RAS
tRCD
tRCD
/CAS
tRCD
BL+tRP
BL+tRP
/WE
CKE
DQM
DQM read latency =2
A0-9,11
X
X
Y
Y
A10
X
X
X
X
A12
X
X
X
X
BA0,1
0
1
0
1
CL=3
ACT#0
ACT#1
Y
0
0
CL=3
Q0
DQ
X
READ#0 with
Auto-Precharge
Q0
Q0
X
Y
1
1
CL=3
Q0
Q1
Q1
ACT#0
READ#1 with
Auto-Precharge
Q1
Q1
Q0
Q0
READ#0
ACT#1
Italic parameter indicates minimum case
MIT-DS-0337-0.2
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Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without
notice.
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
Page Mode Burst Write (multi bank) @BL=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
/CS
tRRD
/RAS
tRCD
/CAS
/WE
CKE
DQM
A0-9,11
X
X
A10
X
X
A12
X
X
BA0,1
0
1
Y
Y
Y
Y
0
0
1
0
D0
DQ
ACT#0
D0
WRITE#0
ACT#1
D0
D0
D0
D0
D0
D0
D1
D1
WRITE#0
D1
D1
D0
D0
D0
WRITE#0
WRITE#1
Italic parameter indicates minimum case
MIT-DS-0337-0.2
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Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without
notice.
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
Page Mode Burst Read (multi bank) @BL=4 CL=3
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
/CS
tRRD
/RAS
tRCD
/CAS
/WE
CKE
DQM
DQM read latency=2
A0-9,11
X
X
A10
X
X
A12
X
X
BA0,1
0
1
Y
Y
Y
Y
0
0
1
0
CL=3
CL=3
Q0
DQ
ACT#0
READ#0
ACT#1
Q0
Q0
CL=3
Q0
Q0
Q0
Q0
READ#0
Q0
Q1
Q1
Q1
Q1
READ#0
READ#1
Italic parameter indicates minimum case
MIT-DS-0337-0.2
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Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without
notice.
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
Write Interrupted by Write / Read @BL=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
/CS
tRRD
/RAS
tRCD
tCCD
/CAS
/WE
CKE
DQM
A0-9,11
X
X
A10
X
X
A12
X
X
BA0,1
0
1
Y
Y
Y
Y
Y
0
0
0
1
0
D0
D0
CL=3
D0
DQ
D0
D0
D0
D1
D1
Q0
Q0
Q0
Q0
ACT#0
WRITE#0 WRITE#0 WRITE#0
READ#0
ACT#1
WRITE#1
Burst Write can be interrupted by Write or Read of any active bank.
Italic parameter indicates minimum case
MIT-DS-0337-0.2
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Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without
notice.
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
Read Interrupted by Read / Write @BL=4 CL=3
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
/CS
tRRD
/RAS
tRCD
/CAS
/WE
CKE
DQM
DQM read latency=2
A0-9,11
X
X
A10
X
X
A12
X
X
BA0,1
0
1
DQ
ACT#0
Y
Y
Y
Y
Y
Y
0
0
0
1
0
0
Q0
Q0
Q0
Q0
Q0
Q0
Q1
Q1
Q0
D0
D0
READ#0 READ#0 READ#0
READ#0
WRITE#0
ACT#1
READ#1
blank to prevent bus contention
Burst Read can be interrupted by Read or Write of any active bank.
Italic parameter indicates minimum case
MIT-DS-0337-0.2
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Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without
notice.
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
Write Interrupted by Precharge @BL=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
/CS
tRRD
/RAS
tRCD
/CAS
/WE
CKE
DQM
A0-9,11
X
X
Y
A10
X
X
X
A12
X
X
X
BA0,1
0
1
0
D0
DQ
Y
D0
ACT#0
WRITE#0
ACT#1
D0
D0
X
1
0
D1
D1
1
1
1
D1
PRE#0
WRITE#1
PRE#1
Burst Write is not interrupted
by Precharge of the other bank.
Y
ACT#1
D1
D1
WRITE#1
Burst Write is interrupted by
Precharge of the same bank.
Italic parameter indicates minimum case
MIT-DS-0337-0.2
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26.Apr.2001
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without
notice.
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
Read Interrupted by Precharge @BL=4 CL=3
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
/CS
tRRD
tRP
/RAS
tRCD
tRCD
/CAS
/WE
CKE
DQM
DQM read latency=2
A0-9,11
X
X
Y
Y
A10
X
X
X
A12
X
X
X
BA0,1
0
1
0
Q0
DQ
ACT#0
READ#0
ACT#1
X
1
0
1
Q0
Q0
Q0
1
Q1
PRE#0
READ#1
PRE#1
Burst Read is not interrupted
by Precharge of the other bank.
Y
1
Q1
ACT#1
READ#1
Burst Read is interrupted
by Precharge of the same bank.
Italic parameter indicates minimum case
MIT-DS-0337-0.2
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Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without
notice.
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
Mode Register Setting
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
/CS
tRSC
tRC
/RAS
tRCD
/CAS
/WE
CKE
DQM
M
A0-9,11
X
A10
X
A12
X
0
BA0,1
0
Y
0
D0
DQ
Auto-Ref (last of 8 cycles)
Mode
Register
Setting
ACT#0
D0
D0
D0
WRITE#0
Italic parameter indicates minimum case
MIT-DS-0337-0.2
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26.Apr.2001
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without
notice.
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
Auto-Refresh @BL=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
/CS
tRC
/RAS
tRCD
/CAS
/WE
CKE
DQM
A0-9,11
X
A10
X
A12
X
BA0,1
0
Y
0
D0
DQ
D0
D0
Auto-Refresh
ACT#0
Before Auto-Refresh,
all banks must be idle state.
After tRC from Auto-Refresh,
all banks are idle state.
D0
WRITE#0
Italic parameter indicates minimum case
MIT-DS-0337-0.2
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ELECTRIC
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26.Apr.2001
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without
notice.
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
Self-Refresh
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
CLK can be stopped
tRC
/CS
/RAS
/CAS
/WE
tSRX
CKE
CKE must be low to maintain Self-Refresh
DQM
X
A0-9,11
A10
X
A12
X
BA0,1
0
DQ
Self-Refresh Entry
Before Self-Refresh Entry,
all banks must be idle state.
Self-Refresh Exit
ACT#0
After tRC from Self-Refresh Exit,
all banks are idle state.
Italic parameter indicates minimum case
MIT-DS-0337-0.2
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Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without
notice.
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
DQM Write Mask @BL=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
/CS
/RAS
tRCD
/CAS
/WE
CKE
DQM
A0-9,11
X
A10
X
A12
X
BA0,1
0
Y
Y
Y
0
0
0
masked
D0
DQ
ACT#0
D0
WRITE#0
D0
D0
masked
D0
WRITE#0
D0
D0
WRITE#0
Italic parameter indicates minimum case
MIT-DS-0337-0.2
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ELECTRIC
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26.Apr.2001
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without
notice.
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
DQM Read Mask @BL=4 CL=3
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
/CS
/RAS
tRCD
/CAS
/WE
CKE
DQM read latency=2
DQM
A0-9,11
X
A10
X
A12
X
BA0,1
0
Y
Y
Y
0
0
0
masked
Q0
DQ
ACT#0
READ#0
Q0
Q0
Q0
READ#0
masked
Q0
Q0
Q0
READ#0
Italic parameter indicates minimum case
MIT-DS-0337-0.2
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Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without
notice.
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
Power Down
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
/CS
/RAS
/CAS
/WE
Standby Power Down
Active Power Down
CKE
CKE latency=1
DQM
A0-9,11
X
A10
X
A12
X
BA0,1
0
DQ
Precharge All
ACT#0
Italic parameter indicates minimum case
MIT-DS-0337-0.2
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26.Apr.2001
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without
notice.
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
CLK Suspend @BL=4 CL=3
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
/CS
/RAS
tRCD
/CAS
/WE
CKE
CKE latency=1
CKE latency=1
DQM
A0-9,11
X
A10
X
A12
X
BA0,1
0
Y
Y
0
0
D0
DQ
ACT#0
D0
D0
D0
WRITE#0
READ#0
CLK suspended
Q0
Q0
Q0
Q0
CLK suspended
Italic parameter indicates minimum case
MIT-DS-0337-0.2
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Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without
notice.
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
OUTLINE
31.75
20.00
4.00
MIT-DS-0337-0.2
6.00
MITSUBISHI
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26.Apr.2001
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without
notice.
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
EEPROM Components A.C. and D.C. Characteristics
Symbol
VCC
VSS
VIH
Parameter
VIL
Supply Voltage
Supply Voltage
Input High Voltage
Input Low Voltage
VOL
Output Low Voltage
Limits
Typ.
Min.
3.0
0
Vddx0.7
-0.3
3.3
0
Max.
Units
3.6
0
Vccx0.3
V
V
V
V
0.4
V
EEPROM A.C.Tim ing Parameters (Ta=0 to 70C)
Symbol
Limits
Min.
Max.
80
100
0.3
7.0
Parameter
SCL Clock Frequency
fSCL
TI
TAA
Noise Supression Time Constant at SCL, SDA inputs
SCL Low to SDA Data Out Valid
TBUF
Time the Bus Must Be Free before a New
T ransmission Can Start
Units
KHz
ns
us
6.7
us
THD:STA Start Condition Hold Time
4.5
us
TLOW
Clock Low Time
6.7
us
THIGH
Clock High Time
4.5
us
TSU:STA
Start Condition Setup Time
6.7
us
0
THD:DAT Data In Hold Time
TSU:DAT
Data In Setup Time
TR
TF
us
500
1
ns
SDA and SCL Rise Time
1
us
SDA and SCL Fall Time
300
ns
TSU:STO Stop Condition Setup Time
6.7
us
TDH
Data Out Hold Time
300
ns
TWR
Write Cycle Time
15
ms
tWR is the time from a valid stop condition of a write sequence to the end of the EEPROM internal erase/program cycle.
TF
TR
T HIGH
T LOW
54
SCL
T SU:STO
T SU:STA
T HD:DAT
T HD:STA
T SU:DAT
SDA
IN
T AA
T DH
T BUF
SDA
OUT
MIT-DS-0337-0.2
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26.Apr.2001
Preliminary Spec.
Some contents are subject to change without
notice.
MITSUBISHI LSIs
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
Keep safety first in your circuit designs!
Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products
better and more reliable, but there is always the possibility that trouble may occur with them.
Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with
appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1.These materials are intended as a reference to assist our customers in the selection of the
Mitsubishi semiconductor product best suited to the customer's application; they do not
convey any license under any intellectual property rights, or any other rights, belonging to
Mitsubishi Electric Corporation or a third party.
2.Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement
of any third-party's rights, originating in the use of any product data, diagrams, charts,
programs, algorithms, or circuit application examples contained in these materials.
3.All information contained in these materials, including product data, diagrams, charts,
programs and algorithms represents information on products at the time of publication of
these materials, and are subject to change by Mitsubishi Electric Corporation without notice
due to product improvements or other reasons. It is therefore recommended that customers
contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product
distributor for the latest product information before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors.
Mitsubishi Electric Corporation assumes no responsibility for any damage, liability, or other
loss rising from these inaccuracies or errors.
Please also pay attention to information published by Mitsubishi Electric Corporation by
various means, including the Mitsubishi Semiconductor home page
(http://www.mitsubishichips.com).
4.When using any or all of the information contained in these materials, including product
data, diagrams, charts, programs and algorithms, please be sure to evaluate all information
as a total system before making a final decision on the applicability of the information and
products.
Mitsubishi Electric Corporation assumes no responsibility for any damage, liability or other
loss resulting from the information contained herein.
5.Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in
a device or system that is used under circumstances in which human life is potentially at stake.
Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor
product distributor when considering the use of a product contained herein for any specific
purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace,
nuclear, or undersea repeater use.
6.The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or
reproduce in whole or in part these materials.
7.If these products or technologies are subject to the Japanese export control restrictions, they
must be exported under a license from the Japanese government and cannot be imported
into a country other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or
the country of destination is prohibited.
8.Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor
product distributor for further details on these materials or the products contained therein.
MIT-DS-0337-0.2
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26.Apr.2001