E2D0019-39-92 ¡ Semiconductor MSM98P05 ¡ Semiconductor Pr el im in This version: MSM98P05 Sep. 1999 ar y Previous version: May. 1997 Voice Synthesis IC with Built-in 2-Mbit OTP ROM GENERAL DESCRIPTION The MSM98P05 is a PCM-based voice synthesis IC with built-in 2-Mbit OTP (One Time PROM). This IC employs OKI nonlinear PCM algorithm and straight PCM algorithm for playback and contains a current mode 10-bit D/A converter and a low-pass filter. External control can be made easily by the built-in edit ROM that can form sentences by linking phrases. With OKI Voice Analyzing/Editing Tool, the built-in edit ROM can be set up and also the built-in ROM data can be created and evaluated easily. With the stand-alone mode/microcontroller interface mode switching pin, the MSM98P05 can support various applications. The products with build-in OTP are suited to applications to be produced in small quantities in a wide variety or in short delivery time. Demand like these, that is, production in small quantities in a wide variety and delivery with an early deadline is what the MSM9800 family of products with built-in mask ROM cannot meet. FEATURES • 8-bit OKI nonlinear PCM algorithm and 8-bit straight PCM algorithm • Built-in edit ROM • Random playback function • Sampling frequency : 4.0 kHz/5.3 kHz/6.4 kHz/8.0 kHz/10.6 kHz/12.8 kHz/ 16.0 kHz Note: If RC oscillation is selected, 10.6 kHz, 12.8 kHz, and 16.0 kHz cannot be selected. • Maximum number of phrases : 63 (Microcontroller interface mode) 56 (Stand-alone mode) • Built-in current mode 10-bit D/A converter • Built-in low-pass filter (LPF) • Standby function • RC oscillation (256 kHz)/ceramic oscillation (4.096 MHz) selectable • Package options: 20-pin plastic DIP (DIP20-P-300-2.54-W1) (Product name : MSM98P05RS) 24-pin plastic SOP (SOP24-P-430-1.27-K) (Product name : MSM98P05GS-K) 1/13 A2 A1 A0 SW2 SW1 SW0 CPU/STD RND BUSY Address & Switching Controller 6 2-Mbit OTP ROM (Including 11 Kbits of Edit ROM & Address ROM) 18-Bit Multiplexer 8 Random Circuit 18-Bit Address Counter DATA Controller PCM Synthesizer I/O Interface ¡ Semiconductor Program Circuit STAND-ALONE MODE (CPU/STD: "L" level) PGM BLOCK DIAGRAM VPP 10 OSC1 OSC2 OSC XT/RC 10-Bit DAC & LPF Timing Controller OSC3/TEST RESET VDD GND VREF AOUT MSM98P05 2/13 XT/CR ¡ Semiconductor MSM98P05 PIN CONFIGURATION (TOP VIEW) VPP 1 20 PGM A0 2 19 SW2 A1 3 18 SW1 A2 4 17 SW0 RESET 5 16 RND XT/CR 6 15 CPU/STD BUSY 7 14 OSC3/TEST GND 8 13 OSC2 VREF 9 12 OSC1 AOUT 10 11 VDD 20-Pin Plastic DIP Note: Applies to MSM98P05RS VDD 1 24 AOUT OSC1 2 23 VREF OSC2 3 22 GND NC 4 21 NC OSC3/TEST 5 20 BUSY NC 6 19 NC CPU/STD 7 18 XT/CR RND 8 17 RESET PGM 9 16 VPP SW0 10 15 A2 SW1 11 14 A1 SW2 12 13 A0 NC: No connection 24-Pin Plastic SOP Note: Applies to MSM98P05GS-K 3/13 ¡ Semiconductor MSM98P05 PIN DESCRIPTIONS Pin DIP SOP Symbol Type Description The IC enters the standby state if this pin is set to "L" level. At this time, 5 17 RESET I oscillation stops and AOUT drives a current of 0mA and becomes GND level, then the IC returns to the initial state. Apply a "L" pulse during power-on. This pin has an internal pull-up resistor. 7 20 BUSY O 6 18 XT/CR I 15 7 CPU/STD I Outputs "L" level while voice is being played back. In "H" level when power is turned ON. XT/RC switching pin. Set to "H" level if ceramic oscillation is used. Set to "L" level if RC oscillation is used. Microcontroller interface/stand-alone mode switching pin. Set to "L" level if the IC is used in stand-alone mode. Volume setting pin. If this pin is set to GND level, the maximum amplitude is 9 23 VREF I delivered. If this pin is set to VDD level, the minimum amplitude is delivered. This pin is internally connected to a pull-down resistor of approx. 10 kW during IC operation. Voice output pin. 10 24 AOUT O The voice signals are output as current changes. A logic "L" is output from 8 22 GND — Ground pin. 11 1 VDD — this pin in standby state. Power supply pin. Insert a bypass capacitor of 0.1 mF or more between VDD and GND pins. Ceramic oscillator connection pin when ceramic oscillation is selected. 12 2 OSC1 I RC connection pin when RC oscillation is selected. Input from this pin if external clock is used. Ceramic oscillator connection pin when ceramic oscillation is selected. 13 3 OSC2 O RC connection pin when RC oscillation is selected. Leave this pin open if external clock is used. Outputs "L" level in standby state. Leave this pin open when ceramic oscillation is used. 14 5 OSC3/TEST O RC connection pin when RC oscillation is selected. Outputs "H" level in standby state when RC oscillation is selected. Random playback starts if RND pin is set to "L" level. 16 8 RND I Fetches addresses from random address generation circuit in the IC at the falling edge of RND. Set to "H" level when the random playback function is not used. This pin has internal pull-up resistor. 4/13 ¡ Semiconductor Pin DIP SOP Symbol MSM98P05 Type Description Phrase input pins corresponding to playback sound. 17-19 10-12 SW0 - SW2 I If input changes, SW0 to SW2 pins fetch addresses after 16 ms and start voice synthesis. Each of these pins has internal pull-down resistor. 2-4 13-15 A0 - A2 I 1 16 VPP — 20 9 PGM I Phrase input pins corresponding to playback sound. Logic input to A0 pin becomes invalid if the random playback function is used. Power supply pin for writing to the built-in OTP. This pin should be set to "H" level or be open during playback. Interface pin for writing to the built-in OTP. This pin should be set to "L" level or be open during playback. 5/13 ¡ Semiconductor MSM98P05 APPLICATION CIRCUITS VDD S3 S2 S1 SW0 AOUT SW1 VPP SW2 PGM VREF RND BUSY A0 S4 RESET A1 A2 OSC3 OSC2 XT/CR OSC1 CPU/STD GND S4="L" S4="H" A2 A1 A0 SW2 SW1 SW0 Address [HEX] S1 0 0 0 0 0 1 01 S2 0 0 0 0 1 0 02 S3 0 0 0 1 0 0 04 S1 0 0 1 0 0 1 09 S2 0 0 1 0 1 0 0A S3 0 0 1 1 0 0 0C Application Circuit for Playing Six Phrases Using Four Switches 6/13 2 3 4 5 6 7 VDD SW0 AOUT ¡ Semiconductor 1 SW1 Application Circuit Using Switches SW2 VREF VPP PGM XT/CR BUSY CPU/STD RND RESET A0 OSC3 A1 OSC2 OSC1 A2 GND MSM98P05 7/13 I5 I4 I3 I2 I1 I0 CPU/STD ST Address Controller 6 2-Mbit OTP ROM (Including 11 Kbits of Edit ROM & Address ROM) 18-Bit Multiplexer 8 18-Bit Address Counter I/O Interface DATA Controller PCM Synthesizer NAR 10 OSC1 OSC2 OSC XT/RC 10-Bit DAC & LPF Timing Controller OSC3/TEST RESET VDD GND VREF AOUT MSM98P05 8/13 XT/CR ¡ Semiconductor Program Circuit MICROCONTROLLER INTERFACE MODE (CPU/STD: "H" level) PGM BLOCK DIAGRAM VPP ¡ Semiconductor MSM98P05 PIN CONFIGURATION (TOP VIEW) VPP 1 20 PGM I3 2 19 I2 I4 3 18 I1 I5 4 17 I0 RESET 5 16 ST XT/CR 6 15 CPU/STD NAR 7 14 OSC3/TEST GND 8 13 OSC2 VREF 9 12 OSC1 AOUT 10 11 VDD 20-Pin Plastic DIP Note: Applies to MSM98P05RS VDD 1 24 AOUT OSC1 2 23 VREF OSC2 3 22 GND NC 4 21 NC OSC3/TEST 5 20 NAR NC 6 19 NC CPU/STD 7 18 XT/CR ST 8 17 RESET PGM 9 16 VPP I0 10 15 I5 I1 11 14 I4 I2 12 13 I3 NC: No connection 24-Pin Plastic SOP Note: Applies to MSM98P05GS-K 9/13 ¡ Semiconductor MSM98P05 PIN DESCRIPTIONS Pin DIP SOP Symbol Type Description The IC enters the standby state if this pin is set to "L" level. At this time, 5 17 RESET I oscillation stops and AOUT drives a current of 0mA and becomes GND level, then the IC returns to the initial state. If the power cannot be applied within 1ms, apply an "L" pulse during power-on. This pin has an internal pull-up resistor. Signal output pin that indicates whether the register in the address controller 7 20 NAR O to latch the 10-15 addresses (see Block Diagram) is idle. NAR at "H" level indicates that the LATCH is empty and ST input is enabled. 6 18 XT/CR I 15 7 CPU/STD I XT/RC switching pin. Set to "H" level if ceramic oscillation is used. Set to "L" level if RC oscillation is used. Microcontroller interface/stand-alone mode switching pin. Set to "H" level if the IC is used in microcontroller interface mode. Volume setting pin. If this pin is set to GND level, the maximum amplitude is 9 23 VREF I delivered. If this pin is set to VDD level, the minimum amplitude is delivered. This pin is internally connected to a pull-down resistor of approx. 10 kW during IC operation. Voice output pin. 10 24 AOUT O The voice signals are output as current changes. A logic "L" is output from 8 22 GND — Ground pin. 11 1 VDD — this pin in standby state. Power supply pin. Insert a bypass capacitor of 0.1 mF or more between this pin and the GND pin. Ceramic oscillator connection pin when ceramic oscillation is selected. 12 2 OSC1 I RC connection pin when RC oscillation is selected. Input from this pin if external clock is used. Ceramic oscillator connection pin when ceramic oscillation is selected. 13 3 OSC2 O RC connection pin when RC oscillation is selected. Leave this pin open if external clock is used. Outputs "L" level in standby state. Leave this pin open when ceramic oscillation is used. 14 5 OSC3/TEST O RC connection pin when RC oscillation is selected. Outputs "H" level in standby state when RC oscillation is selected. Voice synthesis starts at fall of ST, and addresses I0 to I5 are fetched at rise 16 8 ST I of ST. Input ST when NAR, the status signal, is at "H" level. This pin has internal pull-up resistor. 17-19 10-15 I0 - I5 I 1 16 VPP — 20 9 PGM I 2-4 Phrase input pins corresponding to vocalized sound. Power supply pin for writing to the built-in OTP. This pin should be set to "H" level or be open. Interface pin for writing to the built-in OTP. This pin should be set to "L" level or be open. 10/13 ¡ Semiconductor MSM98P05 APPLICATION CIRCUIT + – VCC P2.2 ST P2.1 RESET P3.0 NAR RESET XTAL1 XTAL2 VPP PGM OSC3 VREF AIN AOUT CPU/STD XT/CR OSC2 OSC1 GND STBY VR GND MSC1157 (Speaker AMP) I5 I4 I3 I2 I1 I0 MSM98P05 MSM83C154 (MCU) VDD P1.5 P1.4 P1.3 P1.2 P1.1 P1.0 SP SP SEL + – Application Circuit when Used as Microcontroller Interface 11/13 ¡ Semiconductor MSM98P05 PACKAGE DIMENSIONS (Unit : mm) DIP20-P-300-2.54-W1 Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 1.50 TYP. 12/13 ¡ Semiconductor MSM98P05 (Unit : mm) SOP24-P-430-1.27-K Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.58 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 13/13 E2Y0002-29-62 NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party’s right which may result from the use thereof. 6. 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The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. No part of the contents contained herein may be reprinted or reproduced without our prior permission. 9. MS-DOS is a registered trademark of Microsoft Corporation. Copyright 1999 Oki Electric Industry Co., Ltd. Printed in Japan