OKI MSM6789L

¡ Semiconductor
MSM6789A/6789L
¡ Semiconductor
MSM6789A/6789L
SBC Solid-State Recorder IC
GENERAL DESCRIPTION
The MSM6789A/6789L, an improved version of MSM6788, is a solid-state recorder developed using
the Sub Band Coding (SBC) method.
Just like MSM6788, the MSM6789A/6789L has a stand-alone mode and a microcontroller interface
mode. In the stand-alone mode, record/playback conditions can be selected from pins and the
MSM6789A/6789L can be controlled by a simple drive timing. In the microcontroller interface mode,
record/playback can be controlled by commands from the microcontroller, and more functions are
available than in the stand-alone mode.
The MSM6789A/6789L can directly drive serial voice ROM as external memory as well as serial
register or general-purpose DRAM* (1-bit ¥ or 4-bit ¥ type selectable) as external memories, which
allows a recording and playback circuit with fixed messages to be built easily. The method from
microcontroller is the same as the MSM6788.
* Only for MSM6789A
• Difference between MSM6788 and MSM6789A
MSM6788
MSM6789A
General DRAM
Unavailable
Available
Unvoiced-part elimination function No
Yes
PCM playback
No
Yes
• SBC method:
The SBC method divides voice frequencies into five bands and codes the component for each of
the bands separately, as shown below.
@fs=8.0 Hz
Gain
ch 1
0
ch 2
1
ch 3
ch 4
2
ch 5
3
kHz
f (Hz)
Note:
This data sheet explains a stand-alone mode and a microcontroller interface mode, separately.
MSM6789A/6789L
¡ Semiconductor
• Difference between MSM6789A and MSM6789L
Parameter
MSM6789A
4.5 to 5.5 V
3.0 to 3.6 V
External memory
General-purpose DRAM, 32 Mbits (max.)
16 Mbits (max.)
1-Mbit DRAM (MSM514256B, MSM511000B)
4-Mbit DRAM (MSM514400C, MSM514100C)
16-Mbit DRAM (MSM511740CA, MSM5116100A)
ARAM*, 32 Mbits (max.)
Serial register, 32 Mbits (max.)
4 Mbits (MSM6684B)
8 Mbits (MSM6685)
*
MSM6789L
Operating voltage
Use ARAM which has no failed bits in its first 64 Kbits.
4 Mbits (MSM66V84B)
¡ Semiconductor
MSM6789A/6789L
STAND-ALONE MODE
FEATURES
• SBC method
• Built-in 12-bit AD converter
• Built-in 12-bit DA converter
• Built-in microphone amplifier
• Built-in low-pass filter
Attenuation characteristics –40 dB/oct
• External memories
MSM6789A (5 V version)
General-purpose DRAM, 32 Mbits maximum (for variable messages)
1-Mbit DRAM : Can be directly driven (MSM514256B, MSM511000B)
4-Mbit DRAM : Can be directly driven (MSM514400C, MSM514100C)
16-Mbit DRAM : Can be directly driven (MSM5117400A, MSM5116100A)
ARAM, 32 Mbits maximum (for variable messages)
Note :Use the first 64 Kbits with no failed bits for the ARAM.
Serial register, 32 Mbits maximum (for variable messages)
4-Mbit serial register : Can be directly driven (MSM6684B)
8-Mbit serial register : Can be directly driven (MSM6685)
MSM6789L (3.3 V version)
Serial register, 16 Mbits maximum (for variable messages)
4-Mbit serial resister: Can be directly driven (MSM66V84B)
MSM6789A (5 V version) and MSM6789L (3.3 V version)
Serial voice ROM, 4 Mbits maximum (for fixed messages)
1-Mbit serial voice ROM : Can be directly driven (MSM6595A)
2-Mbit serial voice ROM : Can be directly driven (MSM6596A)
3-Mbit serial voice ROM : Can be directly driven (MSM6597A)
• Bit rate
10.0, 12.6, 16.0 kbps (at 8 kHz sampling freq.)
7.5, 9.5, 12.0 kbps (at 6 kHz sampling freq.)
• Maximum recording time (when one 8-Mbit serial register is connected)
13.8 minutes (for 10.0 kbps SBC)
18.4 minutes (for 7.5 kbps SBC)
11.0 minutes (for 12.6 kbps SBC)
14.6 minutes (for 9.5 kbps SBC)
8.6 minutes (for 16.0 kbps SBC)
11.5 minutes (for 12.0 kbps SBC)
• Number of phrases
63 phrases for variable messages
63 phrases for fixed messages
• Standard linear PCM playback or OKI nonlinear PCM playback can be selected.
• Voice triggered starting function (voice detect level can be set)
• Unvoiced-part elimination function (voice detect level can be set)
• Pausing function
• Master clock frequency:
6.0 MHz to 8.192 MHz
• Power supply voltage:
MSM6789A : Single 5 V power supply
MSM6789L : Single 3.3 V power supply
• Package options:
MSM6789A : 100-pin plastic QFP (QFP100-P-1420-BK) (Product name: MSM6789AGS-BK)
MSM6789L : 100-pin plastic QFP (QFP100-P-1420-BK) (Product name: MSM6789LGS-BK)
LIN
–
+
+
–
Latch
OSC
LOUT
Controller
Timing
AMON FIN
Compare
Circuit
LPF
PAUSE VDS VD0 VD1VD2VD3
AOUT FOUT
ADIN
12-bit
ADC
Analyzer/Synthesizer
SBC
Address Controller
Phrase Register
CA0CA1CA2CA3CA4CA5
12-bit
DAC
PCM
Synthesizer
SG SGC
SG
Circuit
Test Circuit
Data
I/O
OSC
(RC)
Memory Controller
MOUT
MIN
REC/PLAY
BR0
BR1
XT
XT
NAR
MON
ROM
4B/1B
DRAM/SR
PDMD
PDWN
RESET
MCUM
DEL ST SP
TMD0
to
TMD3 TMD4 TST TCK TEST TEST SYNC
DVDD
AVDD
DGND
AGND
LOWPWR
MSEL1
MSEL2
RSEL1
RSEL2
A0(SADY)
A1(SADX)
A2(TAS)
A3(SAS)
A4(RWCK)
A5 to A10
RAS
CAS0 to CAS7
WE
CS1
CS2
CS3
CS4
TDT4 to TDT7
TDT0 to TDT3 [DQ1 to DQ4]
DI/O
DROM
MSM6789A/6789L
¡ Semiconductor
BLOCK DIAGRAM (for MSM6789A (5 V Version))
¡ Semiconductor
MSM6789A/6789L
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
CAS7
CAS6
CAS5
CAS4
CAS3
CAS2
CAS1
CAS0
XT
XT
DVDD
RAS
4B/1B
LOWPWR
NC
DROM
CS4
CS3
CS2
CS1
PIN CONFIGURATION (TOP VIEW) (for MSM6789A (5 V Version))
A10
A9
A8
A7
A6
A5
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
AOUT
FIN
AMON
AVDD
SG
SGC
LOUT
DEL
PAUSE
PDMD
MCUM
BR0
BR1
TEST
VDS
ROM
DGND
NC
ADIN
FOUT
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
[DQ4]
[DQ3]
[DQ2]
[DQ1]
NC
TMD4
TMD3
TMD2
TMD1
TMD0
TDT7
TDT6
TDT5
TDT4
TDT3
TDT2
TDT1
TDT0
SYNC
TST
TCK
CA0
CA1
CA2
CA3
NC
CA4
CA5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100-Pin Plastic QFP
( ) :
[ ]:
NC :
Pins for connecting serial voice ROM
Pins for connecting 4-bit ¥ type DRAM
No-connection pin
NC
A0 (SADY)
A1 (SADX)
A2 (TAS)
A3 (SAS)
A4 (RWCK)
WE
DI/O
MON
NAR
VD3
VD2
VD1
VD0
DRAM/SR
REC/PLAY
ST
SP
RESET
TEST
PDWN
MSEL2
MSEL1
RSEL2
RSEL1
DGND
AGND
MIN
MOUT
LIN
MSM6789A/6789L
¡ Semiconductor
PIN DESCRIPTIONS (for MSM6789A (5 V Version))
Pin
Symbol Type
Description
Digital power supply. Insert a bypass capacitor of 0.1 mF or more between this
90
DVDD
—
47
AVDD
—
40, 55
DGND
—
Digital ground.
54
AGND
—
Analog ground.
SG, SGC
—
Output for analog circuit reference voltage (signal ground).
48, 49
pin and the DGND pin.
Analog power supply. Insert a bypass capacitor of 0.1 mF or more between this
pin and the AGND pin.
53
MIN
51
LIN
52
MOUT
50
LOUT
46
AMON
45
FIN
I
Input of the built-in LPF.
43
FOUT
O
Output of the built-in LPF. This pin connects the AD converter input (ADIN pin).
42
ADIN
I
Input of the built-in 12-bit AD converter.
44
AOUT
O
66
DRAM/SR
I
I
O
O
Inverting input of the built-in OP amplifier. The non-inverting input pin is
internally connected to SG (signal ground).
Output of the built-in OP amplifier for MIN and LIN.
Connected to the LOUT pin in the recording mode and to the DA converter
output in the playback mode. This pin connects the built-in LPF input (FIN pin).
Output of the built-in LPF. This pin outputs playback waveforms and connects
an external speaker drive amplifier.
This pin selects whether memory to be connected externally is DRAM or serial register.
Low level : Serial register
High level : DRAM
This pin selects either 1-bit ¥ type DRAM or 4-bit ¥ type DRAM.
88
4B/1B
I
Low level : 1-bit ¥ type
High level : 4-bit ¥ type
79
A0 (SADY)
78
A1 (SADX)
These pins connect to A0 and A1 of DRAM at the time of DRAM selection. They also
O
connect to SAD pin of serial register and serial voice ROM at the time of serial
register selection. These pins output leading addresses of read/write.
This pin connects to A2 of DRAM at the time of DRAM selection. It also connects
77
A2 (TAS)
O
to TAS pin of serial register and serial voice ROM at the time of serial register selection.
This pin is used to set serial addresses from the SADX and SADY pins into the
internal address counter of the serial register and serial voice ROM.
This pin connects to A3 of DRAM at the time of DRAM selection. It also connects
76
A3 (SAS)
O
to the SAS pin of the serial register and the SASX and SASY pins of the serial voice
ROM at the time of serial register selection. Clock pin to write serial addresses.
This pin connects to A4 of DRAM at the time of DRAM selection. It also connects
75
A4 (RWCK)
O
to the RWCK pin of the serial register and the RDCK pin of the serial voice ROM at
the time of serial register selection. Clock pin to read data from and write data into
the serial register.
1-6
A10-A5
O
This pin connects to pins A5-A10 of DRAM at the time of DRAM selection.
This pin outputs addresses of read/write.
¡ Semiconductor
MSM6789A/6789L
PIN DESCRIPTIONS (for MSM6789A (5 V Version)) (Continued)
Pin
Symbol
74
WE
O
73
DI/O
I/O
85
DROM
I
Data ROM. This pin connects to the DOUT pin of the serial voice ROM.
89
RAS
O
This is a row address strobe pin of DRAM at the time of DRAM selection.
93-100
CAS0CAS7
Description
Type
Write Enable. This pin connects to the WE pin of the serial register and DRAM.
This pin selects either read or write mode.
Data I/O. This pin connects to the DIN and DOUT pins of the serial register and
DRAM. This pin outputs write data and inputs read data.
These are the column address strobe pins of DRAM at the time of DRAM selection.
O
CAS7, an addresss output pin, is connected to pin A11 of DRAM at the time 16-Mbit
DRAM selection.
81
CS1
82
CS2
83
CS3
84
CS4
58
MSEL1
I
59
MSEL2
I
O
Chip Select. These pins connect to CS pin of the serial register and the CS (CS1,
CS2, CS3) pins of the serial voice ROM.
These pins select the capacity of the memory to be connected externally.
These pins select the number of DRAMs and serial registers to be connected externallly.
• When DRAM is selected (DRAM/SR = High level)
MSEL2
MSEL1
RSEL2
RSEL1
Memory capacity
L
L
L
L
1M ¥ 4
L
L
L
H
4M ¥ 1
L
L
H
L
1M ¥ 8
L
L
H
H
1M ¥ 4 + 4M ¥ 1
L
H
L
L
4M ¥ 2
L
H
L
H
4M ¥ 2
56
RSEL1
I
L
H
H
L
4M ¥ 3
57
RSEL2
I
L
H
H
H
4M ¥ 3
H
L
L
L
4M ¥ 4
H
L
L
H
16M ¥ 1
H
L
H
L
4M ¥ 6
H
L
H
H
4M ¥ 6
H
H
L
L
4M ¥ 8
H
H
L
H
4M ¥ 8
H
H
H
L
16M ¥ 2
H
H
H
H
16M ¥ 2
MSM6789A/6789L
¡ Semiconductor
PIN DESCRIPTIONS (for MSM6789A (5 V Version)) (Continued)
Pin
Symbol
Description
Type
• When serial register is selected (DRAM/SR = Low level)
56
57
RSEL1
RSEL2
MSEL2
MSEL1
RSEL2
RSEL1
Memory capacity
L
L
L
L
L
L
4M ¥ 1
L
H
4M ¥ 2
I
L
L
H
L
4M ¥ 3
I
L
L
H
H
4M ¥ 4
L
H
L
L
8M ¥ 1
L
H
L
H
8M ¥ 2
L
H
H
L
8M ¥ 3
L
H
H
H
8M ¥ 4
This pin selects CAS-before-RAS refresh period of DRAM at the time of
87
LOWPWR
I
power down when DRAM is selected.
Low level : 15 µs max.
High level : 125 µs max.
Mode Selection.
34
MCUM
I
Low level : Stand-alone mode
High level : Microcontroller interface mode
62
RESET
I
A high input level causes the MSM6789A to be initialized and to go into the power
down state.
Power Down. When a low level is input, the MSM6789A goes to the power down
state. Unlike the RESET pin, this pin does not force the MSM6789A to be reset.
60
PDWN
I
When a Low level is applied to this pin during recording operation, the MSM6789A
is halted, and will be maintained in the power down state while PDWN is low level.
After this pin is restored to a high level, postprocessing for recording will be performed.
91
XT
92
XT
37
TEST
61
TEST
9-12
TMD3-TMD0
13-20
TDT7-TDT0
21
17-20
I
O
I
I/O
Oscillator Connection. When an external clock is used, input the clock through
this pin. During the power down state, this pin must be set to the ground level.
Oscillator Connection. When an external clock is used, this pin must be left
open.
MSM6789A Test. Input a low level to the TEST pin and a high level to the TEST pin.
MSM6789A Test. This pin must be left open.
SYNC
TDT3-TDT0
[DQ4]-[DQ1]
22
TST
23
TCK
8
TMD4
I/O
I
Connect these pins to DQ1-DQ4 of DRAM at the time of 4-bit ¥ type DRAM
selection. Otherwise these pins must be left open as they are MSM6789A test pins.
MSM6789A Test. Input a low level signal.
¡ Semiconductor
MSM6789A/6789L
PIN DESCRIPTIONS (for MSM6789A (5 V Version)) (Continued)
Pin
Symbol
Description
Type
Playback Operation. When set to low, this pin selects the record/playback
39
ROM
I
operation (only for the SBC method). When set to high, it selects the ROM playback
operation (for the SBC and PCM methods).
Recording mode or playback mode selection. This pin is invalid during
65
REC/PLAY
I
the ROM playback operation. When set to low, it selects the playback mode.
When set to high, it selects the recording mode.
64
ST
I
63
SP
I
32
PAUSE
I
Start Playback. When a low-level pulse is applied to this pin, the record/playback
or ROM playback is started.
Stop Playback.When a low-level pulse is applied to this pin, the record/playback
or ROM playback is stopped.
Playback Pause. When a low-level pulse is applied to this pin, the record/playback
or ROM operation is stopped temporarily.
Phrase Delection. When a low level pulse is applied to this pin, all phrase deletion
or specified phrase deletion can be performed according to the setting of pins CA0
31
DEL
I
through CA5,
ch00:All phrase deletion
ch01 to ch3F:Specified phrase deletion
After power up, be sure to input a RESET signal and then delete all phrases.
After completing this procedure, start the record/playback operation.
Desired Phrase Specification.
A total of 63 phrases can be specified indepedently for the record/playback operation
and the ROM playback operation.
CA5 CA4 CA3 CA2 CA1 CA0
24-30
CA0-CA5
I
Phrase No.
Remarks
All phrase deletion
L
L
L
L
L
L
ch00
L
L
L
L
L
H
ch01
L
..
.
L
..
.
L
..
.
L
..
.
H
..
.
L
..
.
ch02
A total of 63 phrases can
..
.
be used for both record
H
H
H
H
H
L
ch3E
H
H
H
H
H
H
ch3F
/playback and ROM
playback operation.
MSM6789A/6789L
¡ Semiconductor
PIN DESCRIPTIONS (for MSM6789A (5 V Version)) (Continued)
Pin
Symbol Type
Description
Bit Rate Selection. This pin selects one of the following three types of bit rate (master
clock frequency fOSC = 8.192 MHz). This pin is invalid during the ROM playback operation.
35
BRO
36
BR1
I
BR1
BR0
Bit rate
L
L
L
H
12.6 kbps
H
L
10.0 kbps
H
H
Unused
16.0 kbps
Transition to the Power-down State.
Low level: The MSM6789A automatically goes to the power-down state, except
when the record/playback operation is performed.
High level: The MSM6789A automatically goes to the standby state, instead of the
33
PDMD*1
power-down state, except when the record/playback operation
I
is performed. In this case, the MSM6789A can be placed in the
power-down state by setting the RESET or PDWN pin to a high level.
If an external circuit is used for the built-in LPF, this standby mode
must be selected by applying a high level to the PDMD pin.
67-70
VD0-VD3
I
These pins set the voice detect level for the voice triggered starting and unvoiced-part
elimination.
This pin selects the voice triggered starting or the unvoiced-part elimination.
Voice triggered starting:
Input a High level to the VDS pin. Then set the voice
detect level with VD0 to VD3 pins.
38
VDS
I
Unvoiced-part elimination:Input a Low level to the VDS pin. Then set the voice
detect level with VD0 to VD3 pins.
Note: When neither the voice triggered starting nor the unvoiced-part elimination is
used, input a Low level to VD0 to VD3.
72
MON
O
71
NAR
O
This pin outputs a high level while the record/playback operation is being performed.
Output to indicate the enable or disable state of the operation for specifying a
phrase. When continuous ROM playback is performed, the next phrase can
be specified after the NAR pin goes to high positively.
*1 When DRAM is selected, be sure to set the PDMD pin to a High level.
¡ Semiconductor
MSM6789A/6789L
ABSOLUTE MAXIMUM RATINGS (for MSM6789A (5 V Version))
Parameter
Symbol
Condition
Rating
Unit
Power supply voltage
V DD
Ta=25°C
–0.3 to +7.0
V
Input voltage
V IN
Ta=25°C
–0.3 to VDD +0.3
V
Storage temperature
T STG
—
–55 to +150
°C
RECOMMENDED OPERATING CONDITIONS (for MSM6789A (5 V Version))
Parameter
Symbol
Condition
Range
Unit
VDD
DGND=AGND=0 V
+3.5 to +5.5*4
V
Operating temperature
Top
—
0 to +70
°C
Master clock frequencuy
fOSC
—
6.0 to 8.192
MHz
Power supply voltage
ELECTRICAL CHARACTERISTICS (for MSM6789A (5 V Version))
DC Characteristics
Parameter
High input voltage
DVDD=AVDD=4.5 to 5.5 V*4
DGND=AGND=0 V, Ta=0 to 70°C
Symbol
Condition
—
V IH
—
Low input voltage
V IL
High output voltage
V OH
IOH=–40 mA
Low output voltage
Min.
Typ.
Max.
Unit
0.8¥VDD
—
—
V
—
—
0.2¥VDD
V DD–0.3
—
—
V
V
V OL
IOL=2 mA
—
—
0.45
High input current *1
IIH1
VIH=VDD
—
—
10
*2
V
mA
IIH2
VIH=VDD
—
—
20
mA
Low input currcent *1
IIL1
VIL=GND
–10
—
—
mA
Low input current *2
IIL2
VIL=GND
–20
—
—
mA
Low input current *3
IIL3
VIL=GND
–400
—
–20
mA
Operating current consumption
I DD
fOSC=8 MHz, no load
—
20
35
—
—
10
mA
—
200
—
mA
High input current
IDDS1
Power down current
IDDS2
*1
*2
*3
*4
No load
Serial register connected
No load
DRAM connected
mA
Applies to all inputs excluding the XT pin.
Applies to the XT pin.
Applies to the input pins with pull-up resistor (ST, SP, PAUSE, DEL) excluding the XT pin.
The record/playback operation must be performed at the power supply voltage of 4.5 to 5.5 V.
The MSM6789A operates at 3.5 to 5.5 V when the serial register is backed up.
MSM6789A/6789L
¡ Semiconductor
Analog Characteristics
Parameter
DVDD=AVDD=4.5 to 5.5 V
DGND=AGND=0 V Ta=0 to 70°C
Symbol
Condition
ΩVDAEΩ
no load
FIN admissible input voltage range
V FIN
—
FIN input impedance
R FIN
—
Op-map open loop gain
G OP
fIN=0 to 4kHz
Op-amp input impedance
R INA
—
Op-amp load resistance
R OUTA
AOUT load resistance
R AOUT
FOUT load resistance
R FOUT
DA output relative error
Min.
Typ.
Max.
Unit
—
—
10
mV
1
—
VDD–1
V
1
—
—
M W
40
—
—
dB
1
—
—
M W
—
200
—
—
k W
—
50
—
—
k W
—
50
—
—
k W
LIN
MOUT
MIN
REC/PLAY
BR0
BR1
XT
XT
NAR
MON
–
+
+
–
Latch
OSC
LOUT
Controller
PDMD
ROM
Timing
PDWN
RESET
MCUM
AMON FIN
Compare
Circuit
LPF
AOUT FOUT
ADIN
12-bit
ADC
Analyzer/Synthesizer
SBC
Address Controller
Phrase Register
12-bit
DAC
PCM
Synthesizer
SG SGC
SG
Circuit
Test Circuit
Data
I/O
TMD0
to
DEL ST SP PAUSE VDS VD0 VD1 VD2 VD3 CA0 CA1 CA2 CA3 CA4 CA5 TMD3 TMD4 TST TCK TEST TEST SYNC
DVDD
AVDD
DGND
AGND
CS4
CS1
CS2
CS3
SAS
RWCK
WE
TAS
SADY
SADX
MSEL1
MSEL2
RSEL1
RSEL2
TDT4 to TDT7
TDT0 to TDT3
DI/O
DROM
¡ Semiconductor
MSM6789A/6789L
BLOCK DIAGRAM (for MSM6789L (3.3 V Version))
Memory Controller
MSM6789A/6789L
¡ Semiconductor
TEST
TEST
NC
DROM
CS4
CS3
CS2
CS1
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
NC
NC
NC
NC
NC
NC
NC
NC
XT
XT
DVDD
PIN CONFIGURATION (TOP VIEW) (for MSM6789L (3.3 V Version))
NC
NC
NC
NC
NC
NC
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
AOUT
FIN
AMON
AVDD
SG
SGC
LOUT
DEL
PAUSE
PDMD
MCUM
BR0
BR1
TEST
VDS
ROM
DGND
NC
ADIN
FOUT
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
NC
TMD4
TMD3
TMD2
TMD1
TMD0
TDT7
TDT6
TDT5
TDT4
TDT3
TDT2
TDT1
TDT0
SYNC
TST
TCK
CA0
CA1
CA2
CA3
NC
CA4
CA5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100-Pin Plastic QFP
NC :
No-connection pin
NC
SADY
SADX
TAS
SAS
RWCK
WE
DI/O
MON
NAR
VD3
VD2
VD1
VD0
TEST
REC/PLAY
ST
SP
RESET
TEST
PDWN
MSEL2
MSEL1
RSEL2
RSEL1
DGND
AGND
MIN
MOUT
LIN
¡ Semiconductor
MSM6789A/6789L
PIN DESCRIPTIONS (for MSM6789L (3.3 V Version))
Pin
Symbol Type
Description
Digital power supply. Insert a bypass capacitor of 0.1 mF or more between this
90
DVDD
—
47
AVDD
—
40, 55
DGND
—
Digital ground.
54
AGND
—
Analog ground.
SG, SGC
—
Output for analog circuit reference voltage (signal ground).
48, 49
pin and the DGND pin.
Analog power supply. Insert a bypass capacitor of 0.1 mF or more between this
pin and the AGND pin.
53
MIN
51
LIN
52
MOUT
50
LOUT
46
AMON
45
FIN
I
Input of the built-in LPF.
43
FOUT
O
Output of the built-in LPF. This pin connects the AD converter input (ADIN pin).
42
ADIN
I
Input of the built-in 12-bit AD converter.
44
AOUT
O
79
SADY
78
SADX
I
O
O
O
Inverting input of the built-in OP amplifier. The non-inverting input pin is
internally connected to SG (signal ground).
Output of the built-in OP amplifier for MIN and LIN.
Connected to the LOUT pin in the recording mode and to the DA converter
output in the playback mode. This pin connects the built-in LPF input (FIN pin).
Output of the built-in LPF. This pin outputs playback waveforms and connects
an external speaker drive amplifier.
They also connect to SAD pin of serial register and serial voice ROM. These pins
output leading addresses of read/write.
This pin connects to TAS pin of serial register and serial voice ROM.
77
TAS
O
This pin is used to set serial addresses from the SADX and SADY pins into the
internal address counter of the serial register and serial voice ROM.
76
SAS
O
75
RWCK
O
74
WE
O
73
DI/O
I/O
85
DROM
81
CS1
82
CS2
83
CS3
84
CS4
I
O
This pin connects to the SAS pin of the serial register and the SASX and SASY pins
of the serial voice ROM. Clock pin to write serial addresses.
This pin connects to the RWCK pin of the serial register and the RDCK pin of the
serial voice ROM. Clock pin to read data from and write data into the serial register.
Write Enable. This pin connects to the WE pin of the serial register and DRAM.
This pin selects either read or write mode.
Data I/O. This pin connects to the DIN and DOUT pins of the serial register and
DRAM. This pin outputs write data and inputs read data.
Data ROM. This pin connects to the DOUT pin of the serial voice ROM.
Chip Select. These pins connect to CS pin of the serial register and the CS (CS1,
CS2, CS3) pins of the serial voice ROM.
MSM6789A/6789L
¡ Semiconductor
PIN DESCRIPTIONS (for MSM6789L (3.3 V Version)) (Continued)
Pin
Symbol
58
MSEL1
I
59
MSEL2
I
Description
Type
These pins select the capacity of the memory to be connected externally.
These pins select the number of and serial registers to be connected externallly.
56
RSEL1
I
57
RSEL2
I
MSEL2
MSEL1
RSEL2
RSEL1
Memory capacity
L
L
L
L
4M ¥ 1
L
L
L
H
4M ¥ 2
L
L
H
L
4M ¥ 3
L
L
H
H
4M ¥ 4
Mode Selection.
34
MCUM
I
Low level : Stand-alone mode
High level : Microcontroller interface mode
62
RESET
I
A high input level causes the MSM6789L to be initialized and to go into the power
down state.
Power Down. When a low level is input, the MSM6789L goes to the power down
state. Unlike the RESET pin, this pin does not force the MSM6789L to be reset.
60
PDWN
I
When a Low level is applied to this pin during recording operation, the MSM6789L
is halted, and will be maintained in the power down state while PDWN is low level.
After this pin is restored to a high level, postprocessing for recording will be performed.
91
92
XT
XT
37
TEST
61
TEST
9-12
TMD3-TMD0
13-20
TDT7-TDT0
21
17-20
I
O
I
Oscillator Connection. When an external clock is used, input the clock through
this pin. During the power down state, this pin must be set to the ground level.
Oscillator Connection. When an external clock is used, this pin must be left
open.
MSM6789L Test. Input a low level to the TEST pin and a high level to the TEST pin.
I/O
MSM6789L Test. This pin must be left open.
I/O
These pins must be left open as they are MSM6789L test pins.
SYNC
TDT3-TDT0
22
TST
23
TCK
8
TMD4
I
MSM6789L Test. Input a low level signal.
¡ Semiconductor
MSM6789A/6789L
PIN DESCRIPTIONS (for MSM6789L (3.3 V Version)) (Continued)
Pin
Symbol
Description
Type
Playback Operation. When set to low, this pin selects the record/playback
39
ROM
I
operation (only for the SBC method). When set to high, it selects the ROM playback
operation (for the SBC and PCM methods).
Recording mode or playback mode selection. This pin is invalid during
65
REC/PLAY
I
the ROM playback operation. When set to low, it selects the playback mode.
When set to high, it selects the recording mode.
64
ST
I
63
SP
I
32
PAUSE
I
Start Playback. When a low-level pulse is applied to this pin, the record/playback
or ROM playback is started.
Stop Playback.When a low-level pulse is applied to this pin, the record/playback
or ROM playback is stopped.
Playback Pause. When a low-level pulse is applied to this pin, the record/playback
or ROM operation is stopped temporarily.
Phrase Delection. When a low level pulse is applied to this pin, all phrase deletion
or specified phrase deletion can be performed according to the setting of pins CA0
31
DEL
I
through CA5,
ch00:All phrase deletion
ch01 to ch3F:Specified phrase deletion
After power up, be sure to input a RESET signal and then delete all phrases.
After completing this procedure, start the record/playback operation.
Desired Phrase Specification.
A total of 63 phrases can be specified indepedently for the record/playback operation
and the ROM playback operation.
CA5 CA4 CA3 CA2 CA1 CA0
24-30
CA0-CA5
I
Phrase No.
Remarks
All phrase deletion
L
L
L
L
L
L
ch00
L
L
L
L
L
H
ch01
L
..
.
L
..
.
L
..
.
L
..
.
H
..
.
L
..
.
ch02
A total of 63 phrases can
..
.
be used for both record
H
H
H
H
H
L
ch3E
H
H
H
H
H
H
ch3F
/playback and ROM
playback operation.
MSM6789A/6789L
¡ Semiconductor
PIN DESCRIPTIONS (for MSM6789L (3.3 V Version)) (Continued)
Pin
Symbol Type
Description
Bit Rate Selection. This pin selects one of the following three types of bit rate (master
clock frequency fOSC = 8.192 MHz). This pin is invalid during the ROM playback operation.
35
BRO
36
BR1
I
BR1
BR0
Bit rate
L
L
L
H
12.6 kbps
H
L
10.0 kbps
H
H
Unused
16.0 kbps
Transition to the Power-down State.
Low level: The MSM6789L automatically goes to the power-down state, except
when the record/playback operation is performed.
High level: The MSM6789L automatically goes to the standby state, instead of the
33
PDMD*1
power-down state, except when the record/playback operation
I
is performed. In this case, the MSM6789L can be placed in the
power-down state by setting the RESET or PDWN pin to a high level.
If an external circuit is used for the built-in LPF, this standby mode
must be selected by applying a high level to the PDMD pin.
67-70
VD0-VD3
I
These pins set the voice detect level for the voice triggered starting and unvoiced-part
elimination.
This pin selects the voice triggered starting or the unvoiced-part elimination.
Voice triggered starting:
Input a High level to the VDS pin. Then set the voice
detect level with VD0 to VD3 pins.
38
VDS
I
Unvoiced-part elimination:Input a Low level to the VDS pin. Then set the voice
detect level with VD0 to VD3 pins.
Note: When neither the voice triggered starting nor the unvoiced-part elimination is
used, input a Low level to VD0 to VD3.
72
MON
O
This pin outputs a high level while the record/playback operation is being performed.
Output to indicate the enable or disable state of the operation for specifying a
71
NAR
O
phrase. When continuous ROM playback is performed, the next phrase can
be specified after the NAR pin goes to high positively.
*1 When DRAM is selected, be sure to set the PDMD pin to a High level.
¡ Semiconductor
MSM6789A/6789L
ABSOLUTE MAXIMUM RATINGS (for MSM6789L (3.3 V Version))
Parameter
Symbol
Condition
Rating
Unit
Power supply voltage
VDD
Ta=25°C
–0.3 to +7.0
V
Input voltage
VIN
Ta=25°C
–0.3 to VDD +0.3
V
Storage temperature
TSTG
—
–55 to +150
°C
RECOMMENDED OPERATING CONDITIONS (for MSM6789L (3.3 V Version))
Parameter
Symbol
Condition
Range
Unit
VDD
DGND=AGND=0 V
+3.0 to +3.6
V
Operating temperature
Top
—
0 to +70
°C
Master clock frequencuy
fOSC
—
6.0 to 8.192
MHz
Power supply voltage
ELECTRICAL CHARACTERISTICS (for MSM6789L (3.3 V Version))
DC Characteristics
Parameter
High input voltage
DVDD=AVDD=3.0 to 3.6 V
DGND=AGND=0 V, Ta=0 to 70°C
Symbol
Condition
—
V IH
—
Low input voltage
V IL
High output voltage
V OH
IOH=–40 mA
Low output voltage
Min.
Typ.
Max.
Unit
0.85¥VDD
—
—
V
—
—
0.15¥VDD
V DD–0.3
—
—
V
V
V OL
IOL=2 mA
—
—
0.45
High input current *1
IIH1
VIH=VDD
—
—
10
*2
V
mA
IIH2
VIH=VDD
—
—
20
mA
Low input currcent *1
IIL1
VIL=GND
–10
—
—
mA
Low input current *2
IIL2
VIL=GND
–20
—
—
mA
IIL3
VIL=GND
–400
—
–20
I DD
fOSC=8 MHz, no load
—
20
35
—
—
10
mA
—
200
—
mA
High input current
Low input current
*3
Operating current consumption
IDDS1
Power down current
IDDS2
No load
Serial register connected
No load
DRAM connected
mA
mA
*1 Applies to all inputs excluding the XT pin.
*2 Applies to the XT pin.
*3 Applies to the input pins with pull-up resistor (ST, SP, PAUSE, DEL) excluding the XT pin.
MSM6789A/6789L
¡ Semiconductor
Analog Characteristics
Parameter
DVDD=AVDD=3.0 to 3.6 V
DGND=AGND=0 V Ta=0 to 70°C
Symbol
Condition
Min.
Typ.
Max.
Unit
ΩVDAEΩ
no load
—
—
20
mV
FIN admissible input voltage range
VFIN
—
1
—
VDD–1
V
FIN input impedance
RFIN
—
1
—
—
MW
Op-map open loop gain
GOP
fIN=0 to 4kHz
40
—
—
dB
Op-amp input impedance
RINA
—
1
—
—
MW
Op-amp load resistance
ROUTA
—
400
—
—
kW
AOUT load resistance
RAOUT
—
100
—
—
kW
FOUT load resistance
RFOUT
—
100
—
—
kW
DA output relative error
8.192 MHz
MSM6789A
AGND
SG
SGC
LOUT
AMON
FIN
FOUT
ADIN
AOUT
LIN
MOUT
MIN
CS4
CS3
CS2
+
+
MSM6685
Circuit 1 :
Speaker drive amplifier
RWCK
WE
DIN
DOUT
TEST
RFSH NC
RS/A
CS VSS
TAS
SAS
MSM6685
MSM6685
MSM6685
VCC
CS1 CS2 VSS
TEST
DOUT
SASY
TAS
RDCK
SASX
SADY
SADX
Application circuit in stand-alone mode with 8-Mbit serial registers
and 2-Mbit serial voice ROMs.
DROM
RWCK
TAS
SAS
SADY
SADX
MSM6596A-XXX
DGND
MON
NAR
SYNC
TDT0-7
TMD0-3
XT
XT
ROM
CA5
CA4
CA3
CA2
CA1
CA0
TST
TCK
TMD4
RECORDER IC
SW
Phrase
Selection
HEX SW
VD3
VD2
VD1
VD0
CS1
VCC
SAD
8M Serial Register
VDS
RWCK
WE
DI/O
TAS
SAS
SADX
2M Serial Voice ROM
MSM6596A-XXX
DVDD
SADY
SAS
SADX
AVDD
RESET
TAS
PDWN
RWCK
TEST
MSEL1
WE
MSEL2
DI/O
DRAM/SR
RSEL1
RSEL2
BR0
DROM
BR1
A5-A10
PDMD
MCUM
RAS
LOWPWR
TEST
CAS0-CAS7
4B/1B
ST
SP
PAUSE
DEL
DVDD
REC/PLAY
¡ Semiconductor
MSM6789A/6789L
APPLICATION CIRCUITS (for MSM6789A (5 V version))
This is an application circuit example when the MSM6789A is used in stand-alone mode with four
8-Mbit serial registers and two 2-Mbit serial voice ROMs.
8.192 MHz
SW
Phrase
Selection
MSM6789A
AGND
SG
SGC
LOUT
AMON
FIN
FOUT
ADIN
AOUT
LIN
MOUT
MIN
+
+
Speaker drive amplifier
Circuit 2 :
DROM
RWCK
TAS
SAS
SADY
SADX
VCC
CS1 CS2 VSS
TEST
DOUT
SASY
TAS
RDCK
SASX
SADY
SADX
Application circuit in stand-alone mode with 4-Mbit DRAMs and
2-Mbit serial voice ROMs.
CAS VSS
VCC
MSM6596A-XXX
DGND
MON
NAR
SYNC
TDT0-7
TMD0-3
XT
XT
ROM
TST
TCK
TMD4
CA5
CA4
CA3
CA2
CA1
CA0
VD0
RECORDER IC
HEX SW
CAS VSS
CAS VSS
VCC
MSM514100C
CS1
CS2
CS3
CS4
CAS VSS
VCC
MSM514100C
VD1
VCC
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
WE
DIN
DOUT
RAS
4-Mbit DRAM MSM514100C
CAS0
CAS1
CAS2
CAS3
CAS4
CAS5
CAS6
CAS7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
WE
DI/O
MSM514100C
VD2
AVDD
A0(SADY)
A1(SADX)
A2(TAS)
A3(SAS)
A4(RWCK)
A5
A6
A7
A8
A9
A10
WE
DI/O
DROM
RAS
2M Serial Voice ROM
MSM6596A-XXX
VD3
RESET
PDWN
DRAM/SR
TEST
MSEL2
MSEL1
RSEL2
RSEL1
BR0
BR1
PDMD
MCUM
LOWPWR
TEST
4B/1B
VDS
PAUSE
SP
ST
DEL
DVDD
REC/PLAY
MSM6789A/6789L
¡ Semiconductor
APPLICATION CIRCUITS (for MSM6789A (5 V version)) (Continued)
This is an application circuit example when the MSM6789A is used in stand-alone mode with four
4-Mbit DRAMs (1-bit ¥ type) and two 2-Mbit serial voice ROMs.
MSM6789A
AGND
SG
SGC
LOUT
AMON
FIN
FOUT
ADIN
AOUT
+
+
Speaker drive amplifier
Circuit 3 :
CAS VSS
10
CAS VSS
VCC
DROM
A4(RWCK)
A2(TAS)
A3(SAS)
A0(SADY)
A1(SADX)
VCC
CS1 CS2 VSS
TEST
DOUT
SASY
TAS
RDCK
SASX
SADY
SADX
Application circuit in stand-alone mode with 4-Mbit DRAMs,
1-Mbit DRAMs and 2-Mbit serial voice ROMs.
CAS VSS
10
VCC
MSM6596A-XXX
DGND
MON
NAR
SYNC
TDT0-7
TMD0-3
XT
XT
ROM
LIN
MOUT
MIN
4-Mbit DRAM MSM514100C
8.192 MHz
SW
Phrase
Selection
CA5
CA4
CA3
CA2
CA1
CA0
TST
TCK
TMD4
VD0
RECORDER IC
HEX SW
CS1
CS2
CS3
CS4
1-Mbit DRAM MSM511000B
CAS VSS
10
VCC
MSM511000B
VD1
WE
DIN
DOUT
RAS
CAS VSS
10
A0~A
A0~A9
VCC
MSM511000B
VD2
11
A0-A10
VCC
MSM511000B
CAS0
CAS1
CAS2
CAS3
CAS4
CAS5
CAS6
CAS7
WE
DI/O
DROM
RAS
A0-A10
AVDD
A0-A4
2M Serial Voice ROM
MSM6596A-XXX
VD3
RESET
PDWN
TEST
DRAM/SR
MSEL2
MSEL1
RSEL2
RSEL1
BR0
BR1
PDMD
MCUM
LOWPWR
TEST
4B/1B
VDS
PAUSE
SP
ST
DEL
DVDD
REC/PLAY
5
¡ Semiconductor
MSM6789A/6789L
APPLICATION CIRCUITS (for MSM6789A (5 V version)) (Continued)
This is an application circuit example when the MSM6789A is used in stand-alone mode with one
4-Mbit DRAM, four 1-Mbit DRAMs (1-bit ¥ type) and two 2-Mbit serial voice ROMs.
8.192 MHz
MSM6789A
AGND
SG
SGC
LOUT
AMON
FIN
FOUT
ADIN
AOUT
LIN
MOUT
MIN
+
+
Circuit 4 :
Speaker Drive Amplifier
CAS VSS
DROM
A4(RWCK)
A2(TAS)
A3(SAS)
A0(SADY)
A1(SADX)
VCC
CS1 CS2 VSS
TEST
DOUT
SASY
TAS
RDCK
SASX
SADY
SADX
Application circuit in stand-alone mode with 16Mbit DRAMs, and 2-Mbit serial voice ROMs.
A0-A10
11
VCC
MSM6596A-XXX
DGND
MON
NAR
SYNC
TDT0-7
TMD0-3
XT
XT
ROM
TST
TCK
TMD4
CA5
CA4
CA3
CA2
CA1
CA0
VD0
RECORDER IC
SW
Phrase
Slection
HEX SW
CS1
CS2
CS3
CS4
CAS VSS
WE
DIN
DOUT
RAS
A11
A0-A10
16-Mbit DRAM MSM5116100A
VD1
A0-A10
11
VCC
MSM5116100A
CAS0
CAS1
CAS2
CAS3
CAS4
CAS5
CAS6
CAS7
WE
DI/O
DROM
RAS
A0-A10
AVDD
2M Serial Voice ROM
MSM6596A-XXX
VD2
RESET
PDWN
TEST
DRAM/SR
MSEL2
MSEL1
RSEL2
RSEL1
BR0
BR1
PDMD
MCUM
TEST
LOWPWR
4B/1B
VDS
VD3
PAUSE
SP
ST
DEL
DVDD
REC/PLAY
5
A0-A4
MSM6789A/6789L
¡ Semiconductor
APPLICATION CIRCUITS (for MSM6789A (5 V version)) (Continued)
This is an application circuit example when the MSM6789A is used in stand-alone mode with two
16-Mbit DRAMs (1-bit ¥ type) and two 2-Mbit serial voice ROMs.
8.192 MHz
SW
Phrace
Slection
HEX SW
RECORDER IC MSM6789A
AGND
SG
SGC
LOUT
AMON
FIN
FOUT
ADIN
AOUT
LIN
MOUT
MIN
CS1
CS2
CS3
CS4
+
+
Circuit 5 :
Speaker Drive Amplifier
CAS VSS
10
CAS VSS
A4(RWCK)
A2(TAS)
A3(SAS)
A0(SADY)
A1(SADX)
VCC
CS1 CS2 VSS
TEST
DOUT
SASY
TAS
RDCK
SASX
SADY
SADX
VCC
Application circuit in stand-alone mode with 4-Mbit DRAMs and
2-Mbit serial voice ROMs.
10
VCC
MSM6596A-XXX
DGND
MON
NAR
SYNC
TDT4-7
TMD0-3
XT
XT
ROM
CA5
CA4
CA3
CA2
CA1
CA0
TST
TCK
TMD4
VD0
VD1
4-Mbit DRAM MSM514400C
VD2
CAS VSS
MSM514400C
CAS0
CAS1
CAS2
CAS3
CAS4
CAS5
CAS6
CAS7
WE
RAS
OE
WE
RAS
DI/O
DROM
10
VCC
MSM514400C
CAS VSS
DQ1
DQ2
DQ3
DQ4
A0~A9
VCC
MSM514400C
VD3
10
VCC
[TDT0]DQ1
[TDT1]DQ2
[TDT2]DQ3
[TDT3]DQ4
A0-A9
A10
AVDD
A0-A4
2M Serial Voice ROM
MSM6596A-XXX
VDS
PDWN
DRAM/SR
TEST
4B/1B
MSEL2
MSEL1
RSEL2
RSEL1
BR0
BR1
PDMD
MCUM
LOWPWR
TEST
RESET
PAUSE
SP
ST
DEL
DVDD
REC/PLAY
5
¡ Semiconductor
MSM6789A/6789L
APPLICATION CIRCUITS (for MSM6789A (5 V version)) (Continued)
This is an application circuit example when the MSM6789A is used in stand-alone mode with four
4-Mbit DRAMs (4-bit ¥ type) and two 2-Mbit serial voice ROMs.
8.192 MHz
SW
Phrase
selection
MSM6789A
AGND
SG
SGC
LOUT
AMON
FIN
FOUT
ADIN
AOUT
LIN
MOUT
MIN
CS1
CS2
CS3
CS4
+
+
Speaker drive amplifier
Circuit 6 :
CAS VSS
9
CAS VSS
VCC
VCC
SASX
SADY
SADX
DROM
CS1 CS2 VSS
TEST
DOUT
SASY
TAS
A4(RWCK)
RDCK
A2(TAS)
A3(SAS)
A0(SADY)
A1(SADX)
Application circuit in stand-alone mode with 4-Mbit DRAMs,
1-Mbit DRAM, and 2M-bit serial voice ROMs.
CAS VSS
9
VCC
MSM6596A-XXX
DGND
MON
NAR
SYNC
TDT4-7
TMD0-3
XT
XT
ROM
CA5
CA4
CA3
CA2
CA1
CA0
TST
TCK
TMD4
VD0
RECORDER IC
HEX SW
VD1
4-Mbit DRAM MSM514400C
VD2
1-Mbit DRAM MSM514256B
CAS VSS
9
VCC
MSM514256B
CAS VSS
RAS
OE
DQ1
DQ2
DQ3
DQ4
WE
A0-A8
9
VCC
MSM514256B
VD3
A0-A9
10
VCC
MSM514256B
CAS0
CAS1
CAS2
CAS3
CAS4
CAS5
CAS6
CAS7
DI/O
DROM
RAS
[TDT0]DQ1
[TDT1]DQ2
[TDT2]DQ3
[TDT3]DQ4
WE
A10
A0-A9
AVDD
A0-A4
2M Serial Voice ROM
MSM6596A-XXX
VDS
RESET
PDWN
TEST
DRAM/SR
4B/1B
MSEL2
MSEL1
RSEL2
RSEL1
BR0
BR1
PDMD
MCUM
LOWPWR
TEST
PAUSE
SP
ST
DEL
DVDD
REC/PLAY
5
MSM6789A/6789L
¡ Semiconductor
APPLICATION CIRCUITS (for MSM6789A (5 V version)) (Continued)
This is an application circuit example when the MSM6789A is used in stand-alone mode with one
4-Mbit DRAM, four 1-Mbit DRAMs (4-bit ¥ type), and two 2-Mbit serial voice ROMs.
8.192 MHz
MSM6789A
AGND
SG
SGC
LOUT
AMON
FIN
FOUT
ADIN
AOUT
LIN
MOUT
MIN
CS1
CS2
CS3
CS4
+
+
Circuit 7 :
Speaker drive amplifier
VCC
CS1 CS2 VSS
TEST
DOUT
SASY
TAS
RDCK
SASX
SADY
SADX
Application circuit in stand-alone mode with 16-Mbit
DRAMs and 2-Mbit serial voice ROMs.
CAS VSS
DROM
A4(RWCK)
A2(TAS)
A3(SAS)
A0(SADY)
A1(SADX)
MSM6596A-XXX
DGND
MON
NAR
SYNC
TDT4-7
TMD0-3
XT
XT
ROM
CA5
CA4
CA3
CA2
CA1
CA0
TST
TCK
TMD4
VD0
RECORDER IC
SW
Phrase
selection
HEX SW
VD1
16-Mbit DRAM MSM5117400A
CAS VSS
RAS
OE
A0-A10
11
VCC
MSM5117400A
CAS0
CAS1
CAS2
CAS3
CAS4
CAS5
CAS6
CAS7
WE
DQ1
DQ2
DQ3
DQ4
A0-A10
WE
A0-A10
11
VCC
RAS
DI/O
DROM
[TDT0]DQ1
[TDT1]DQ2
[TDT2]DQ3
[TDT3]DQ4
A0-A10
AVDD
2M Serial Voice ROM
MSM6596A-XXX
VD2
RESET
PDWN
TEST
DRAM/SR
MSEL2
MSEL1
4B/1B
RSEL2
RSEL1
BR0
BR1
PDMD
LOWPWR
MCUM
TEST
VDS
VD3
PAUSE
SP
ST
DEL
DVDD
REC/PLAY
5
A0-A4
¡ Semiconductor
MSM6789A/6789L
APPLICATION CIRCUITS (for MSM6789A (5 V version)) (Continued)
This is an application circuit example when the MSM6789A is used in stand-alone mode with two
16-Mbit DRAMs (4-bit ¥ type) and two 2-Mbit serial voice ROMs.
HEX SW
8.192 MHz
MSM6789L
AGND
SG
SGC
LOUT
AMON
FIN
FOUT
ADIN
AOUT
LIN
MOUT
MIN
CS4
CS3
CS2
+
VCC
+
Speaker drive amplifier
RWCK
WE
DIN
DOUT
TEST
RFSH NC
RS/A
CS VSS
TAS
SAS
SAD
MSM66V84B
Circuit 8 :
MSM66V84B
DROM
RWCK
TAS
SAS
SADY
SADX
VCC
CS1 CS2 VSS
TEST
DOUT
SASY
TAS
RDCK
SASX
SADY
SADX
Application circuit in stand-alone mode with 4-Mbit serial
registers and 2-Mbit serial voice ROMs.
MSM66V84B
DGND
MON
NAR
SYNC
TDT0-7
TMD0-3
XT
XT
ROM
CA5
CA4
CA3
CA2
CA1
CA0
TST
TCK
TMD4
VD3
VD2
VD1
VD0
RECORDER IC
SW
Phrase
Selection
DVDD
CS1
RWCK
WE
DI/O
TAS
SAS
SADX
2M Serial Voice ROM
MSM6596A-XXX
VDS
DROM
RWCK
WE
DI/O
TAS
SADY
SAS
SADX
AVDD
4M Serial Register
RSEL1
RSEL2
BR0
BR1
PDMD
MCUM
TEST
RESET
PDWN
TEST
MSEL1
MSEL2
ST
SP
PAUSE
DEL
DVDD
REC/PLAY
MSM6789A/6789L
¡ Semiconductor
APPLICATION CIRCUITS (for MSM6789L (3.3 V Version))
This is an application circuit example when the MSM6789L is used in stand-alone mode with four
4-Mbit serial registers and two 2-Mbit serial voice ROMs.
MSM6596A-XXX
MSM66V84B
¡ Semiconductor
MSM6789A/6789L
MICROCONTROLLER INTERFACE MODE
FEATURES
• SBC method
• Built-in 12-bit AD converter
• Built-in 12-bit DA converter
• Built-in microphone amplifier
• Built-in low-pass filter
Attenuation characteristics –40 dB/oct
• External memories
MSM6789A (5 V version)
General-purpose DRAM, 32 Mbits maximum (for variable messages)
1-Mbit DRAM : Can be directly driven (MSM514256B, MSM511000B)
4-Mbit DRAM : Can be directly driven (MSM514400C, MSM514100C)
16-Mbit DRAM : Can be directly driven (MSM5117400A, MSM5116100A)
ARAM, 32 Mbits maximum (for variable messages)
Note: Use the first 64 Kbits with no failed bits for the ARAM.
Serial register, 32 Mbits maximum (for variable messages)
4-Mbit serial register : Can be directly driven (MSM6684B)
8-Mbit serial register : Can be directly driven (MSM6685)
MSM6789L (3.3 V version)
Serial register, 16 Mbits maximum (for variable messages)
4-Mbit serial register: Can be directly driven (MSM66V84B)
MSM6789A (5 V version) and MSM6789L (3.3 V version)
Serial voice ROM, 4 Mbits maximum (for fixed messages)
1-Mbit serial voice ROM : Can be directly driven (MSM6595A)
2-Mbit serial voice ROM : Can be directly driven (MSM6596A)
3-Mbit serial voice ROM : Can be directly driven (MSM6597A)
• Bit rate
10.0, 12.6, 16.0 kbps (at 8 kHz sampling freq.)
7.5, 9.5, 12.0 kbps (at 6 kHz sampling freq.)
• Maximum recording time (when one 8-Mbit serial register is connected)
13.8 minutes (for 10.0 kbps SBC)
18.4 minutes (for 7.5 kbps SBC)
11.0 minutes (for 12.6 kbps SBC)
14.6 minutes (for 9.5 kbps SBC)
8.6 minutes (for 16.0 kbps SBC)
11.5 minutes (for 12.0 kbps SBC)
• Number of phrases
63 phrases for variable messages
255 phrases for fixed messages
• Standard linear PCM playback or OKI nonlinear PCM playback can be selected.
• Voice triggered starting function (voice detect level can be set)
• Uuvoiced-part elimination function (voice detect level can be set)
• Pausing function
• Master clock frequency:
6.0 MHz to 8.192 MHz
• Power supply voltage:
MSM6789A: Single 5 V power supply
MSM6789L: Single 3.3 V power supply
• Package options:
MSM6789A: 100-pin plastic QFP (QFP100-P-1420-BK) (Product name: MSM6789AGS-BK)
MSM6789L: 100-pin plastic QFP (QFP100-P-1420-BK) (Product name: MSM6789LGS-BK)
TMD4
Circuit
SYNC
LIN
MOUT
–
MIN
–
+
+
OSC
XT
XT
MCUM
RESET
PDWN
ACON
EXTD
MON
DRAM/SR
4B/1B
TEST
TEST
Test
TDT4 to TDT7
TMD0 to TMD3
TST TCK
LOUT
Controller
Timing
AMON FIN
Register
Status
LPF
NAR VPM RPM BUSY
AOUT FOUT
WR RD CE CE
ADIN
12-bit
ADC
12-bit
DAC
PCM
Synthesizer
Analyzer/Synthesizer
SBC
Address Controller
Microcontroller I/F
D3 D2 D1 D0
SG SGC
SG
Circuit
OSC
(RC)
Data
I/O
DVDD
AVDD
DGND
AGND
LOWPWR
MSEL2
MSEL1
RSEL1
RSEL2
A0(SADY)
A1(SADX)
A2(TAS)
A3(SAS)
A4(RWCK)
A5 to A10
RAS
CAS0 to CAS7
WE
CS1
CS2
CS3
CS4
DI/O
DROM
TDT0 to TDT3
[DQ1] to [DQ4]
MSM6789A/6789L
¡ Semiconductor
BLOCK DIAGRAM (for MSM6789A (5 V Version))
Memory Controller
¡ Semiconductor
MSM6789A/6789L
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
CAS7
CAS6
CAS5
CAS4
CAS3
CAS2
CAS1
CAS0
XT
XT
DVDD
RAS
4B/1B
LOWPWR
NC
DROM
CS4
CS3
CS2
CS1
PIN CONFIGURATION (TOP VIEW) (for MSM6789A (5 V Version))
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
AOUT
FIN
AMON
AVDD
SG
SGC
LOUT
VPM
ACON
TEST
MCUM
CE
TEST
EXTD
TEST
TEST
DGND
NC
ADIN
FOUT
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
[DQ4]
[DQ3]
[DQ2]
[DQ1]
A10
A9
A8
A7
A6
A5
NC
TMD4
TMD3
TMD2
TMD1
TMD0
TDT7
TDT6
TDT5
TDT4
TDT3
TDT2
TDT1
TDT0
SYNC
TST
TCK
D0
D1
D2
D3
NC
BUSY
RPM
100-Pin Plastic QFP
( ) :
[ ]:
NC :
Pins for connecting serial voice ROM.
Pins for connecting 4-bit ¥ type DRAM.
No-connection pin
A0 (SADY)
A1 (SADX)
A2 (TAS)
A3 (SAS)
A4 (RWCK)
WE
DI/O
MON
NAR
TEST
TEST
TEST
TEST
DRAM/SR
CE
RD
WR
RESET
TEST
PDWN
MSEL2
MSEL1
RSEL2
RSEL1
DGND
AGND
MIN
MOUT
LIN
MSM6789A/6789L
¡ Semiconductor
PIN DESCRIPTIONS (for MSM6789A (5 V Version))
Pin
Symbol
Description
Type
Digital power supply. Insert a bypass capacitor of 0.1mF or more between this
90
DVDD
—
47
AVDD
—
40, 55
DGND
—
Digital ground.
54
AGND
—
Analog ground.
SG, SGC
O
Output for analog circuit reference voltage (signal ground).
48, 49
pin and the DGND pin.
Analog power supply. Insert a bypass capacitor of 0.1mF or more between this
pin and the AGND pin.
53
MIN
51
LIN
52
MOUT
50
LOUT
46
AMON
45
FIN
I
Input of the built-in LPF.
43
FOUT
O
Output of the built-in LPF. This pin connects the AD converter input (ADIN pin).
42
ADIN
I
Input of the built-in 12-bit AD converter.
44
AOUT
O
I
O
O
Inverting input of the built-in OP amplifier. The non-inverting input pin is
internally connected to SG (signal ground).
Output of the built-in OP amplifier for MIN and LIN.
Connected to the LOUT pin in the recording mode and to the DA converter
output in the playback mode. This pin connects the built-in LPF input (FIN pin).
Output of the built-in LPF. This pin outputs playback waveforms and connects
an external speaker drive amplifier.
This pin selects whether memory to be connected externally is DRAM or serial
66
DRAM/SR
I
register.
Low level : Serial register
High level : DRAM
This pin selects either 1-bit ¥ type DRAM or 4-bit ¥ type DRAM.
88
4B/1B
I
Low level : 1-bit ¥ type
High level : 4-bit ¥ type
79
A0 (SADY)
78
A1 (SADX)
These pins connect to A0 and A1 of DRAM at the time of DRAM selection. They also
O
connect to SAD pin of serial register and serial voice ROM at the time of serial
register selection. These pins output leading addresses of read/write.
This pin connects to A2 of DRAM at the time of DRAM selection. It also connects
77
A2 (TAS)
O
to TAS pin of serial register and serial voice ROM at the time of serial register selection.
This pin is used to set serial addresses from the SADX and SADY pins into the
internal address counter of the serial register and serial voice ROM.
This pin connects to A3 of DRAM at the time of DRAM selection. It also connects
76
A3 (SAS)
O
to the SAS pin of the serial register and the SASX and SASY pins of the serial voice
ROM at the time of serial register selection. Clock pin to write serial addresses.
This pin connects to A4 of DRAM at the time of DRAM selection. It also connects
75
A4 (RWCK)
O
to the RWCK pin of the serial register and the RDCK pin of the serial voice ROM at
the time of serial register selection. Clock pin to read data from and write data into
the serial register.
1-6
A10-A5
O
These pins connect to pins A5-A10 of DRAM at the time of DRAM selection.
These pins output addresses of read/write.
¡ Semiconductor
MSM6789A/6789L
PIN DESCRIPTIONS (for MSM6789A (5 V Version)) (Continued)
Pin
Symbol Type
Description
Write Enable. This pin connects to the WE pin of the serial register and DRAM.
74
WE
O
73
DI/O
I/O
85
DROM
I
Data ROM. This pin connects to the DOUT pin of the serial voice ROM.
89
RAS
O
This is a row address strobe pin of DRAM at the time of DRAM selection.
93-100
CAS0CAS7
This pin selects either read or write mode.
Data I/O. This pin connects to the DIN and DOUT pins of the serial register and
DRAM. This pin is used to output write data and inputs read data.
These are the column address strobe pins of DRAM at the time of DRAM selection.
O
CAS7, an addresss output pin, is connected to pin A11 of DRAM at the time of 16Mbit DRAM selection.
81
CS1
82
CS2
83
CS3
84
CS4
58
MSEL1
I
59
MSEL2
I
O
Chip Slect. These pins connect CS pin of the serial register and the CS (CS1,
CS2, CS3) pins of the serial voice ROM.
These pins select the capacity of the memory to be connected externally.
These pins select the number of DRAMs and serial registers to be connected
externallly.
• When DRAM is selected (DRAM/SR = High level)
MSEL2
56
RSEL1
I
57
RSEL2
I
MSEL1
RSEL2
RSEL1
Memory capacity
L
L
L
L
L
L
1M ¥ 4
L
H
4M ¥ 1
L
L
H
L
1M ¥ 8
L
L
H
H
1M ¥ 4 + 4M ¥ 1
L
H
L
L
4M ¥ 2
L
H
L
H
4M ¥ 2
L
H
H
L
4M ¥ 3
L
H
H
H
4M ¥ 3
H
L
L
L
4M ¥ 4
H
L
L
H
16M ¥ 1
H
L
H
L
4M ¥ 6
H
L
H
H
4M ¥ 6
H
H
L
L
4M ¥ 8
H
H
L
H
4M ¥ 8
H
H
H
L
16M ¥ 2
H
H
H
H
16M ¥ 2
MSM6789A/6789L
¡ Semiconductor
PIN DESCRIPTIONS (for MSM6789A (5 V Version)) (Continued)
Pin
Symbol
Description
Type
• When serial register is selected (DRAM/SR = Low level)
56
57
RSEL1
RSEL2
MSEL2
MSEL1
RSEL2
RSEL1
Memory capacity
L
L
L
L
L
L
4M ¥ 1
L
H
4M ¥ 2
I
L
L
H
L
4M ¥ 3
I
L
L
H
H
4M ¥ 4
L
H
L
L
8M ¥ 1
L
H
L
H
8M ¥ 2
L
H
H
L
8M ¥ 3
L
H
H
H
8M ¥ 4
This pin selects CAS-before-RAS refresh period of DRAM at the time of
87
LOWPWR
I
power down when DRAM is selected.
Low level : 15 µs max.
High level : 125 µs max.
Mode Selection.
34
MCUM
I
Low level : Stand-alone mode
High level : Microcontroller interface mode
62
RESET
I
A high input level causes the MSM6789A to be initialized and to go into the power
down state.
Power Down. When a low level is input the MSM6789A goes to the power down
state. Unlike the RESET pin, this pin does not force the MSM6789A to be reset.
60
PDWN
I
When an Low level is applied to this pin during recording operation, the MSM6789A
is halted, and will be maintained in the power down state while PDWN is low level.
After this pin is restored to a high level, postprocessing for recording will be
performed.
24
D0
25
D1
26
D2
27
D3
63
WR
I
64
RD
I
I/O
Bidirectional data bus to transfer commands and data to and from an external
microcontroller.
Write Pulse Input. Inputting a low pulse to WR pin causes a command or data
to be input via D0 to D3 pins.
Read Pulse Input. Inputting a low pulse to RD pin causes status bits or data to
be output via D0 to D3 pins.
Chip Enable Input. When the CE pin is set to low level and the CE pin is set to a
65
CE
35
CE
high level, the write pulse (WR) or read pulse (RD) can be accepted.
I
When the CE pin is set to a high level or CE pin is set to a low level, the write pulse
(WR) and read pulse (RD) cannot be accepted so that data cannot be communicated
via D0 to D3 pins.
¡ Semiconductor
MSM6789A/6789L
PIN DESCRIPTIONS (for MSM6789A (5 V Version)) (Continued)
Pin
Symbol
29
BUSY
Description
Type
Busy. This pin outputs a high level while a command is being executed. When this
O
pin is held high, do not apply any data to D0 to D3 pins. The state of this pin is the
same as the contents of the BUSY bit of the status register.
30
RPM
O
RPM. This pin outputs a high level during recording or playback operation. The
state of this pin is the same as the contents of the RPM bit of the status register.
VPM. This pin outputs a high level during standby for voice incoming after the start of
recording by voice triggered starting or unvoiced-part elimination. Also outputs a high
31
VPM
O
level when the record/playback is stopped temporarily by inputting the PAUSE
command. The state of this pin is the same as the contents of the VPM bit of the
status register.
NAR. This NAR pin indicates whether the phrase designation by the CHAN command
71
NAR
O
is enabled or disabled.
In the ROM play back operation, specify the next phrase after verifying that the NAR
pin is at high level and input the START command.
POP Noise Suppression Select. This pin selects whether the pop noise
suppression circuit is used.
32
ACON
Low level : the pop noise suppression circuit is not used.
I
High level : the pop noise suppression circuit is used.
The DC level is shifted by the LEV command.
EXTD. In the record/playback operation by the EXT command, input a high level for
37
EXTD
I
91
XT
I
92
XT
O
72
MON
O
read/write of SBC data. Input a low level for usual command input and status output.
Oscillator Connect. When an external clock is used, input the clock through
this pin. At the power-down state, this pin must be set to the ground level.
Oscillator Connect. When an external clock is uesd, this pin must be left open.
MON. This pin outputs a high level while the record/playback operation is being
performed. Outputs a synchronizing clock while record/playback activated by the
EXT command is being performed.
36, 37-39, TEST
61, 67-70
TEST
33
9-12
TMD3-TMD0
13-20
21
17-20
TDT7-TDT0
I
I/O
MSM6789A Test. Input a low level to the TEST pin and a high level to the
TEST pin.
MSM6789A Test. This pin must be left open.
SYNC
TDT3-TDT0
[DQ4]-[DQ1]
22
TST
23
TCK
8
TMD4
I/O
I
Connect these pins to DQ1 to DQ4 of DRAM at the time of 4-bit ¥ type DRAM
selection. Otherwise these pins must be left open as they are MSM6789A test pins.
MSM6789A Test. Input a low level.
MSM6789A/6789L
¡ Semiconductor
ABSOLUTE MAXIMUM RATINGS (for MSM6789A (5 V Version))
Parameter
Symbol
Condition
V DD
Ta=25°C
–0.3 to +7.0
Input Voltage
V IN
Ta=25°C
–0.3 ~ VDD +0.3
V
Storage temperature
T STG
—
–55 to +150
°C
Power supply voltage
Rating
Unit
V
RECOMMENDED OPERATING CONDITIONS (for MSM6789A (5 V Version))
Parameter
Symbol
Condition
Range
Unit
Power supply voltage
VDD
DGND=AGND=0 V
+3.5 to +5.5*3
V
Operating temperature
Top
—
0 to +70
°C
Master clock frequencuy
fOSC
—
6.0 to 8.192
MHz
ELECTRIAL CHARACTERISTICS (for MSM6789A (5 V Version))
DC Characteristics
Parameter
DVDD=AVDD=4.5 to 5.5 V*3
DGND=AGND=0 V Ta=0 to 70°C
Symbol
Condition
Min.
Typ.
Max.
Unit
High input voltage
V IH
—
0.8¥VDD
—
—
V
Low input voltage
V IL
—
—
—
0.2¥VDD
V
High output voltage
V OH
IOH=–40 mA
V DD–0.3
—
—
V
Low output voltage
V OL
IOL=2 mA
—
—
0.45
V
High input current*1
IIH1
VIH=VDD
—
—
10
current*2
IIH2
VIH=VDD
—
—
20
mA
Low input current*1
IIL1
VIL=GND
–10
—
—
mA
Low input current*2
IIL2
VIL=GND
–20
—
—
Operating current consumption
I DD
fOSC=8 MHz, no load
—
20
35
—
—
10
mA
—
200
—
mA
High input
IDDS1
Power down current
IDDS2
No load
Serial register connected
No load
DRAM connected
mA
mA
mA
*1 Applies to all inputs excluding the XT pin.
*2 Applies to the XT pin.
*3 The record/playback operation must be performed at the power supply voltage of 4.5 to 5.5 V.
The MSM6789A operates at 3.5 to 5.5 V when the serial register is backed up.
¡ Semiconductor
MSM6789A/6789L
Analog Characteristics
Parameter
DVDD=AVDD=4.5 to 5.5 V
DGND=AGND=0 V Ta=0 to 70°C
Symbol
Condition
Min.
Typ.
Max.
Unit
ΩVDAEΩ
No load
—
—
10
mV
FIN admissible input voltage range
VFIN
—
1
—
VDD–1
V
FIN input impedance
RFIN
—
1
—
—
MW
OP-amp open loop gain
GOP
fIN=0 to 4 kHz
40
—
—-
dB
OP-amp input impedance
RINA
—
1
—
—
MW
OP-amp load resistance
ROUTA
—
200
—
—
kW
AOUT load resistance
RAOUT
—
50
—
—
kW
FOUT load resistance
RFOUT
—
50
—
—
kW
DA output relative error
TMD4
Circuit
SYNC
LIN
MOUT
–
MIN
–
+
+
OSC
XT
XT
LOUT
Controller
ACON
EXTD
MON
Timing
PDWN
MCUM
RESET
TEST
TEST
Test
TCK
TDT4 to TDT7
TMD0 to TMD3
TST
AMON FIN
Register
Status
LPF
NAR VPM RPM BUSY
AOUT FOUT
WR RD CE CE
ADIN
12-bit
ADC
12-bit
DAC
PCM
Synthesizer
Analyzer/Synthesizer
SBC
Address Controller
Microcontroller I/F
D3 D2 D1 D0
SG SGC
SG
Circuit
Data
I/O
DVDD
AVDD
DGND
AGND
MSEL2
MSEL1
RSEL1
RSEL2
SADY
SADX
TAS
SAS
RWCK
WE
CS1
CS2
CS3
CS4
TDT0 to TDT3
DI/O
DROM
MSM6789A/6789L
¡ Semiconductor
BLOCK DIAGRAM (for MSM6789L (3.3 V Version))
Memory Controller
¡ Semiconductor
MSM6789A/6789L
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
NC
NC
NC
NC
NC
NC
NC
NC
XT
XT
DVDD
NC
TEST
TEST
NC
DROM
CS4
CS3
CS2
CS1
PIN CONFIGURATION (TOP VIEW) (for MSM6789L (3.3V Version))
NC
NC
NC
NC
NC
NC
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
AOUT
FIN
AMON
AVDD
SG
SGC
LOUT
VPM
ACON
TEST
MCUM
CE
TEST
EXTD
TEST
TEST
DGND
NC
ADIN
FOUT
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
NC
TMD4
TMD3
TMD2
TMD1
TMD0
TDT7
TDT6
TDT5
TDT4
TDT3
TDT2
TDT1
TDT0
SYNC
TST
TCK
D0
D1
D2
D3
NC
BUSY
RPM
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100-Pin Plastic QFP
NC :
No-connection pin
NC
SADY
SADX
TAS
SAS
RWCK
WE
DI/O
MON
NAR
TEST
TEST
TEST
TEST
TEST
CE
RD
WR
RESET
TEST
PDWN
MSEL2
MSEL1
RSEL2
RSEL1
DGND
AGND
MIN
MOUT
LIN
MSM6789A/6789L
¡ Semiconductor
PIN DESCRIPTIONS (for MSM6789L (3.3 V Version))
Pin
Symbol
Description
Type
Digital power supply. Insert a bypass capacitor of 0.1mF or more between this
90
DVDD
—
47
AVDD
—
40, 55
DGND
—
Digital ground.
54
AGND
—
Analog ground.
SG, SGC
O
Output for analog circuit reference voltage (signal ground).
48, 49
pin and the DGND pin.
Analog power supply. Insert a bypass capacitor of 0.1mF or more between this
pin and the AGND pin.
53
MIN
51
LIN
52
MOUT
50
LOUT
46
AMON
O
45
FIN
I
43
FOUT
O
Output of the built-in LPF. This pin connects the AD converter input (ADIN pin).
42
ADIN
I
Input of the built-in 12-bit AD converter.
44
AOUT
O
79
SADY
78
SADX
77
TAS
I
O
O
Inverting input of the built-in OP amplifier. The non-inverting input pin is
internally connected to SG (signal ground).
Output of the built-in OP amplifier for MIN and LIN.
Connected to the LOUT pin in the recording mode and to the DA converter
output in the playback mode. This pin connects the built-in LPF input (FIN pin).
Input of the built-in LPF.
Output of the built-in LPF. This pin outputs playback waveforms and connects
an external speaker drive amplifier.
These pins connect to SAD pin of serial register and serial voice ROM. These pins
output leading addresses of read/write.
This pin connects to TAS pin of serial register and serial voice ROM. This pin is used
O
to set serial addresses from the SADX and SADY pins into the internal address
counter of the serial register and serial voice ROM.
76
SAS
O
75
RWCK
O
74
WE
O
73
DI/O
I/O
85
DROM
81
CS1
82
CS2
I
O
83
CS3
84
CS4
58
MSEL1
I
59
MSEL2
I
This pin connects to the SAS pin of the serial register and the SASX and SASY pins
of the serial voice ROM. Clock pin to write serial addresses.
This pin connects to the RWCK pin of the serial register and the RDCK pin of the
serial voice ROM. Clock pin to read data from and write data into the serial register.
Write Enable. This pin connects to the WE pin of the serial register and DRAM.
This pin selects either read or write mode.
Data I/O. This pin connects to the DIN and DOUT pins of the serial register and
DRAM. This pin is used to output write data and inputs read data.
Data ROM. This pin connects to the DOUT pin of the serial voice ROM.
Chip Slect. These pins connect CS pin of the serial register and the CS (CS1,
CS2, CS3) pins of the serial voice ROM.
These pins select the capacity of the memory to be connected externally.
¡ Semiconductor
MSM6789A/6789L
PIN DESCRIPTIONS (for MSM6789L (3.3 V Version)) (Continued)
Pin
Symbol
Description
Type
These pins select the number of serial registers to be connected
externallly.
56
57
RSEL1
RSEL2
I
MSEL2
MSEL1
RSEL2
RSEL1
I
L
L
L
L
Memory capacity
4M
¥1
L
L
L
H
4M
¥2
L
L
H
L
4M
¥3
L
L
H
H
4M
¥4
Mode Selection.
34
MCUM
Low level : Stand-alone mode
I
High level : Microcontroller interface mode
62
RESET
A high input level causes the MSM6789L to be initialized and to go into the power
I
down state.
Power Down. When a low level is input the MSM6789L goes to the power down
state. Unlike the RESET pin, this pin does not force the MSM6789L to be reset.
60
PDWN
I
When an Low level is applied to this pin during recording operation, the MSM6789L
is halted, and will be maintained in the power down state while PDWN is low level.
After this pin is restored to a high level, postprocessing for recording will be
performed.
24
D0
25
D1
26
D2
27
D3
63
WR
I
64
RD
I
I/O
Bidirectional data bus to transfer commands and data to and from an external
microcontroller.
Write Pulse Input. Inputting a low pulse to WR pin causes a command or data
to be input via D0 to D3 pins.
Read Pulse Input. Inputting a low pulse to RD pin causes status bits or data to
be output via D0 to D3 pins.
Chip Enable Input. When the CE pin is set to low level and the CE pin is set to a
65
CE
35
CE
high level, the write pulse (WR) or read pulse (RD) can be accepted.
I
When the CE pin is set to a high level or CE pin is set to a low level, the write pulse
(WR) and read pulse (RD) cannot be accepted so that data cannot be communicated
via D0 to D3 pins.
Busy. This pin outputs a high level while a command is being executed. When this
29
BUSY
O
pin is held high, do not apply any data to D0 to D3 pins. The state of this pin is the
same as the contents of the BUSY bit of the status register.
30
RPM
O
RPM. This pin outputs a high level during recording or playback operation. The
state of this pin is the same as the contents of the RPM bit of the status register.
MSM6789A/6789L
¡ Semiconductor
PIN DESCRIPTIONS (for MSM6789L (3.3 V Version)) (Continued)
Pin
Symbol
Description
Type
VPM. This pin outputs a high level during standby for voice incoming after the start of
recording by voice triggered starting or unvoiced-part elimination. Also outputs a high
31
VPM
O
level when the record/playback is stopped temporarily by inputting the PAUSE
command. The state of this pin is the same as the contents of the VPM bit of the
status register.
NAR. This NAR pin indicates whether the phrase designation by the CHAN command
71
NAR
O
is enabled or disabled.
In the ROM play back operation, specify the next phrase after verifying that the NAR
pin is at high level and input the START command.
POP Noise Suppression Select. This pin selects whether the pop noise
suppression circuit is used.
32
ACON
Low level : the pop noise suppression circuit is not used.
I
High level : the pop noise suppression circuit is used.
The DC level is shifted by the LEV command.
EXTD. In the record/playback operation by the EXT command, input a high level for
37
EXTD
I
91
XT
I
92
XT
O
read/write of SBC data. Input a low level for usual command input and status output.
Oscillator Connect. When an external clock is used, input the clock through
this pin. At the power-down state, this pin must be set to the ground level.
Oscillator Connect. When an external clock is uesd, this pin must be left open.
MON. This pin outputs a high level while the record/playback operation is being
72
MON
O
performed. Outputs a synchronizing clock while record/playback activated by the
EXT command is being performed.
36, 37-39, TEST
61, 67-70
TEST
33
9-12
TMD3-TMD0
13-20
21
17-20
TDT7-TDT0
I
MSM6789L Test. Input a low level to the TEST pin and a high level to the
TEST pin.
I/O
MSM6789L Test. This pin must be left open.
I/O
These pins must be left open as they are MSM6789L test pins.
SYNC
TDT3-TDT0
22
TST
23
TCK
8
TMD4
I
MSM6789L Test. Input a low level.
¡ Semiconductor
MSM6789A/6789L
ABSOLUTE MAXIMUM RATINGS (for MSM6789L (3.3 V Version))
Parameter
Symbol
Condition
Rating
Unit
VDD
Ta=25°C
–0.3 to +7.0
V
Input Voltage
VIN
Ta=25°C
–0.3 ~ VDD +0.3
V
Storage temperature
TSTG
—
–55 to +150
°C
Power supply voltage
RECOMMENDED OPERATING CONDITIONS (for MSM6789L (3.3 V Version))
Parameter
Power supply voltage
Symbol
Condition
Range
Unit
VDD
DGND=AGND=0 V
+3.0 to +3.6
V
Operating temperature
Top
—
0 to +70
°C
Master clock frequencuy
fOSC
—
6.0 to 8.192
MHz
ELECTRIAL CHARACTERISTICS (for MSM6789L (3.3 V Version))
DC Characteristics
Parameter
High input voltage
DVDD=AVDD=3.0 to 3.6 V
DGND=AGND=0 V Ta=0 to 70°C
Symbol
Condition
Min.
Typ.
Max.
Unit
VIH
—
0.85¥VDD
—
—
V
—
—
0.15¥VDD
V
VDD–0.3
—
—
V
—
Low input voltage
VIL
High output voltage
VOH
IOH=–40 mA
Low output voltage
VOL
IOL=2 mA
—
—
0.45
V
High input current*1
IIH1
VIH=VDD
—
—
10
mA
High input current*2
IIH2
VIH=VDD
—
—
20
mA
Low input current*1
IIL1
VIL=GND
–10
—
—
mA
Low input current*2
IIL2
VIL=GND
–20
—
—
mA
Operating current consumption
IDD
fOSC=8 MHz, no load
—
20
35
mA
—
—
10
mA
—
200
—
mA
IDDS1
Power down current
IDDS2
No load
Serial register connected
No load
DRAM connected
*1 Applies to all inputs excluding the XT pin.
*2 Applies to the XT pin.
MSM6789A/6789L
¡ Semiconductor
Analog Characteristics
Parameter
DVDD=AVDD=3.0 to 3.6 V
DGND=AGND=0 V Ta=0 to 70°C
Symbol
Condition
Min.
Typ.
Max.
Unit
ΩVDAEΩ
No load
—
—
20
mV
FIN admissible input voltage range
VFIN
—
1
—
VDD–1
V
FIN input impedance
RFIN
—
1
—
—
MW
OP-amp open loop gain
GOP
fIN=0 to 4 kHz
40
—
—-
dB
OP-amp input impedance
RINA
—
1
—
—
MW
OP-amp load resistance
ROUTA
—
400
—
—
kW
AOUT load resistance
RAOUT
—
100
—
—
kW
FOUT load resistance
RFOUT
—
100
—
—
kW
DA output relative error
RECORDER IC
AGND
MSM6789A
+
VCC
Speaker drive amplifier
+
8M Serial Register MSM6685
RWCK
WE
DIN
DOUT
TEST
RFSH NC
RS/A
CS VSS
TAS
SAS
SAD
MSM6685
Circuit 1 :
MSM6685
DROM
RWCK
TAS
SAS
SADY
SADX
VCC
CS1 CS2 VSS
TEST
DOUT
SASY
TAS
RDCK
SASX
SADY
SADX
Application circuit in microcontroller interface mode with 8-Mbit
serial registers and 2-Mbit serial voice ROMs.
MSM6685
SG
SGC
LOUT
AMON
FIN
FOUT
ADIN
AOUT
RWCK
WE
DI/O
TAS
SAS
SADX
MSM6596A-XXX
DGND
MON
NAR
XT
MCUM
LOWPWR
DRAM/SR
A5-A10
MSEL2
RAS
MSEL1
CAS0-CAS7
RSEL1
RSEL2
CE
CS1
TEST
4B/1B
CS2
ACON
CS3
EXTD
TST
CS4
TCK
TEST
MIN
BUSY
RPM
VPM
MOUT
SYNC
TDT0-7
TMD0-3
TMD4
LIN
XT
RWCK
WE
DI/O
DROM
TAS
SADY
SAS
SADX
AVDD
2M Serial Voice ROM
MSM6596A-XXX
8.192 MHz
Microcontroller
RESET
PDWN
RD
WR
CE
D3
D2
D1
D0
DVDD
¡ Semiconductor
MSM6789A/6789L
APPLICATION CIRCUITS (for MSM6789A (5 V Version))
This is an application circuit example when the MSM6789A is used in microcontroller interface mode
with four 8-Mbit serial registers and two 2-Mbit serial voice ROMs.
RECORDER IC MSM6789A
AGND
SG
SGC
LOUT
AMON
FIN
FOUT
ADIN
AOUT
LIN
MOUT
+
+
Speaker drive amplifier
Circuit 2 :
VCC
CAS VSS
DROM
RWCK
TAS
SAS
SADY
SADX
VCC
CS1 CS2 VSS
TEST
DOUT
SASY
TAS
RDCK
SASX
SADY
SADX
Application circuit in microcontroller interface mode with 4-Mbit
DRAMs and 2-Mbit serial voice ROMs.
CAS VSS
VCC
MSM6596A-XXX
DGND
MON
NAR
TDT0-7
TMD0-3
XT
XT
BUSY
RPM
VPM
SYNC
TMD4
MIN
MSM514100A
CS1
CS2
CS3
CS4
CAS VSS
MSM514100A
CAS VSS
VCC
MSM514100A
MCUM
TEST
CE
DRAM/SR
MSEL2
MSEL1
RSEL2
RSEL1
LOWPWR
4B/1B
ACON
EXTD
TST
TCK
TEST
VCC
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
WE
DIN
DOUT
RAS
MSM514100A
CAS0
CAS1
CAS2
CAS3
CAS4
CAS5
CAS6
CAS7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
WE
DI/O
2M Serial Voice ROM
MSM6596A-XXX
8.192 MHz
Microcontroller
RESET
PDWN
AVDD
A0(SADY)
A1(SADX)
A2(TAS)
A3(SAS)
A4(RWCK)
A5
A6
A7
A8
A9
A10
WE
DI/O
DROM
RAS
4-Mbit DRAM
RD
WR
CE
D3
D2
D1
D0
DVDD
MSM6789A/6789L
¡ Semiconductor
APPLICATION CIRCUITS (for MSM6789A (5 V Version)) (Continued)
This is an application circuit example when the MSM6789A is used in microcontroller interface mode
with four 4-Mbit DRAMs (1-bit ¥ type) and two 2-Mbit serial voice ROMs.
MSM6789A
AGND
SG
SGC
AOUT
LOUT
AMON
FIN
FOUT
ADIN
LIN
MOUT
+
+
Speaker drive amplifier
Circuit 3 :
CAS VSS
10
CAS VSS
VCC
VCC
SASX
SADY
SADX
DROM
CS1 CS2 VSS
TEST
DOUT
SASY
TAS
A4(RWCK)
RDCK
A2(TAS)
A3(SAS)
A0(SADY)
A1(SADX)
Application circuit in microcontroller interface mode with 4-Mbit
DRAMs, 1-Mbit DRAMs, and 2-Mbit serial voice ROMs.
CAS VSS
10
VCC
MSM6596A-XXX
DGND
MON
NAR
TDT0-7
TMD0-3
XT
XT
BUSY
RPM
VPM
SYNC
TMD4
RECORDER IC
MIN
1-Mbit DRAM MSM511000A
CAS VSS
10
VCC
MSM511000A
CS1
CS2
CS3
CS4
4-Mbit DRAM MSM514100A
WE
DIN
DOUT
RAS
CAS VSS
A0-A9
10
VCC
MSM511000A
MCUM
TEST
CE
LOWPWR
DRAM/SR
MSEL2
MSEL1
RSEL2
RSEL1
ACON
EXTD
TST
TCK
TEST
4B/1B
A0-A10
11
VCC
MSM511000A
CAS0
CAS1
CAS2
CAS3
CAS4
CAS5
CAS6
CAS7
WE
DI/O
DROM
RAS
A0-A10
AVDD
A0-A4
2M Serial Voice ROM
MSM6596A-XXX
8.192 MHz
Microcontroller
RESET
PDWN
RD
WR
CE
D3
D2
D1
D0
DVDD
5
¡ Semiconductor
MSM6789A/6789L
APPLICATION CIRCUITS (for MSM6789A (5 V Version)) (Continued)
This is an application circuit example when the MSM6789A is used in microcontroller interface mode
with one 4-Mbit DRAM, four 1-Mbit DRAMs (1-bit ¥ type), and two 2-Mbit serial voice ROMs.
MSM6789A
LOUT
AMON
FIN
FOUT
ADIN
LIN
MOUT
MIN
CS1
CS2
CS3
CS4
MON
AOUT
NAR
TDT0-7
SGC
TMD0-3
SG
DGND AGND
XT
XT
RECORDER IC
BUSY
RPM
VPM
SYNC
TMD4
MCUM
TEST
CE
LOWPWR
DRAM/SR
MSEL2
MSEL1
RSEL2
RSEL1
4B/1B
ACON
EXTD
TST
TCK
TEST
+
Circuit 4 :
Speaker drive amplifier
+
MSM5116100A
CAS VSS
WE
DIN
DOUT
RAS
A11
A0-A10
11
CAS VSS
DROM
A4(RWCK)
A2(TAS)
A3(SAS)
A0(SADY)
A1(SADX)
VCC
CS1 CS2 VSS
TEST
DOUT
SASY
TAS
RDCK
SASX
SADY
SADX
MSM6596A-XXX
Application circuit in microcontroller interface mode
with 16-Mbit DRAMs and 2-Mbit serial voice ROMs.
A0-A10
VCC
MSM5116100A
CAS0
CAS1
CAS2
CAS3
CAS4
CAS5
CAS6
CAS7
WE
DI/O
DROM
RAS
A0-A10
11
VCC
2M Serial Voice ROM
MSM6596A-XXX
8.192 MHz
Microcontroller
RESET
PDWN
A0-A10
AVDD
16-Mbit DRAM
RD
WR
CE
D3
D2
D1
D0
DVDD
5
A0-A4
MSM6789A/6789L
¡ Semiconductor
APPLICATION CIRCUITS (for MSM6789A (5 V Version)) (Continued)
This is an application circuit example when the MSM6789A is used in microcontroller interface mode
with two 16-Mbit DRAMs (1-bit ¥ type) and two 2-Mbit serial voice ROMs.
MSM6789A
AGND
SG
SGC
LOUT
AMON
FIN
FOUT
ADIN
AOUT
LIN
MOUT
+
+
Speaker drive amplifier
Circuit 5 :
CAS VSS
DROM
A4(RWCK)
A2(TAS)
A3(SAS)
A0(SADY)
A1(SADX)
VCC
CS1 CS2 VSS
TEST
DOUT
SASY
TAS
RDCK
SASX
SADY
SADX
Application circuit in microcontroller interface mode with 4-Mbit
DRAMs and 2-Mbit serial voice ROMs.
CAS VSS
10
VCC
MSM6596A-XXX
DGND
MON
NAR
TDT4-7
TMD0-3
XT
XT
BUSY
RPM
VPM
SYNC
TMD4
RECORDER IC
MIN
4-Mbit DRAM MSM514400C
CS1
CS2
CS3
CS4
CAS VSS
MSM514400C
CAS VSS
WE
RAS
OE
WE
RAS
DI/O
DROM
10
VCC
MSM514400C
CAS0
CAS1
CAS2
CAS3
CAS4
CAS5
CAS6
CAS7
DQ1
DQ2
DQ3
DQ4
10
VCC
MSM514400C
MCUM
TEST
CE
DRAM/SR
4B/1B
MSEL2
MSEL1
RSEL2
RSEL1
LOWPWR
ACON
EXTD
TST
TCK
TEST
10
VCC
[TDT0]DQ1
[TDT1]DQ2
[TDT2]DQ3
[TDT3]DQ4
A0-A9
A10
AVDD
2M Serial Voice ROM
MSM6596A-XXX
8.192 MHz
Microcontroller
RESET
PDWN
RD
WR
CE
D3
D2
D1
D0
DVDD
5
¡ Semiconductor
MSM6789A/6789L
APPLICATION CIRCUITS (for MSM6789A (5 V Version)) (Continued)
This is an application circuit example when the MSM6789A is used in microcontroller interface mode
with four 4-Mbit DRAMs (4-bit ¥ type) and two 2-Mbit serial voice ROMs.
MSM6789A
AGND
SG
SGC
AOUT
LOUT
AMON
FIN
FOUT
ADIN
LIN
MOUT
+
+
Speaker drive amplifier
Circuit 6 :
CAS VSS
9
CAS VSS
VCC
VCC
SASX
SADY
SADX
DROM
CS1 CS2 VSS
TEST
DOUT
SASY
TAS
A4(RWCK)
RDCK
A2(TAS)
A3(SAS)
A0(SADY)
A1(SADX)
Application circuit in microcontroller interface mode with 4-Mbit
DRAM, 1-Mbit DRAMs, and 2-Mbit serial voice ROMs.
CAS VSS
9
VCC
MSM6596A-XXX
DGND
MON
NAR
TDT4-7
TMD0-3
XT
XT
RECORCDER IC
BUSY
RPM
VPM
SYNC
TMD4
4-Mbit DRAM MSM514400C
MIN
CAS VSS
1-Mbit DRAM MSM514256B
CS1
CS2
CS3
CS4
A0-A8
9
VCC
MSM514256B
CAS VSS
RAS
DQ1
DQ2
DQ3
DQ4
WE
OE
9
VCC
MSM514256B
CAS0
CAS1
CAS2
CAS3
CAS4
CAS5
CAS6
CAS7
A0-A9
10
VCC
MSM514256B
MCUM
TEST
CE
4B/1B
DRAM/SR
LOWPWR
RSEL2
RSEL1
MSEL2
MSEL1
ACON
EXTD
TST
TCK
TEST
A10
[TDT0]DQ1
[TDT1]DQ2
[TDT2]DQ3
[TDT3]DQ4
WE
DI/O
DROM
RAS
A0-A9
AVDD
A0-A4
2M Serial Voice ROM
MSM6596A-XXX
8.192 MHz
Microctontroller
RESET
PDWN
RD
WR
CE
D3
D2
D1
D0
DVDD
5
MSM6789A/6789L
¡ Semiconductor
APPLICATION CIRCUITS (for MSM6789A (5 V Version)) (Continued)
This is an application circuit example when the MSM6789A is used in microcontroller interface mode
with one 4-Mbit DRAM, four 1-Mbit DRAMs (4-bit ¥ type), and two 2-Mbit serial voice ROMs.
MSM6789A
LOUT
AMON
FIN
FOUT
ADIN
LIN
MOUT
MIN
CS1
CS2
CS3
CS4
MON
AOUT
NAR
TDT4-7
SGC
TMD0-3
SG
DGND AGND
XT
XT
RECORDER IC
BUSY
RPM
VPM
SYNC
TMD4
MCUM
TEST
CE
LOWPWR
4B/1B
DRAM/SR
MSEL2
MSEL1
RSEL2
RSEL1
ACON
EXTD
TST
TCK
TEST
+
Circuit 7 :
Speaker drive amplifier
+
MSM5117400A
CAS VSS
RAS
DQ1
DQ2
DQ3
DQ4
WE
OE
A0~A10
11
CAS VSS
DROM
A4(RWCK)
A2(TAS)
A3(SAS)
A0(SADY)
A1(SADX)
VCC
CS1 CS2 VSS
TEST
DOUT
SASY
TAS
RDCK
SASX
SADY
SADX
MSM6596A-XXX
Application circuit in microcontroller interface mode
with 16-Mbit DRAMs and 2-Mbit serial voice ROMs.
A0-A10
VCC
MSM5117400A
CAS0
CAS1
CAS2
CAS3
CAS4
CAS5
CAS6
CAS7
11
A0-A10
VCC
2M Serial Voice ROM
MSM6596A-XXX
8.192 MHz
Microcontroller
RESET
PDWN
[TDT0]DQ1
[TDT1]DQ2
[TDT2]DQ3
[TDT3]DQ4
WE
DI/O
DROM
RAS
A0-A10
AVDD
16-Mbit DRAM
RD
WR
CE
D3
D2
D1
D0
DVDD
5
A0-A4
¡ Semiconductor
MSM6789A/6789L
APPLICATION CIRCUITS (for MSM6789A (5 V Version)) (Continued)
This is an application circuit example when the MSM6789A is used in microcontroller interface mode
with two 16-Mbit DRAMs (4-bit ¥ type) and two 2-Mbit serial voice ROMs.
AVDD
AGND
MSM6789A
DGND
MON
NAR
XT
XT
BUSY
RPM
VPM
SYNC
TDT0-7
TMD0-3
TMD4
SG
SGC
LOUT
AMON
FIN
FOUT
ADIN
AOUT
LIN
MOUT
MIN
PDWN
MCUM
LOWPWR
DROM
DRAM/SR
RAS
MSEL1
MSEL2
CAS0-CAS7
RSEL1
A5-A10
RSEL2
CE
CS1
TEST
CS2
ACON
4B/1B
CS3
TST
TCK
CS4
TEST
A4(RWCK)
WE
DI/O
A2(TAS)
A0(SADY)
A3(SAS)
A1(SADX)
RECORDER IC
8.192 MHz
Microcontroller
RESET
EXTD
RD
WR
CE
D3
D2
D1
D0
DVDD
+
+
Circuit 8 :
Speaker drive amplifier
Application circuit when EXT command is used.
MSM6789A/6789L
¡ Semiconductor
APPLICATION CIRCUITS (for MSM6789A (5 V Version)) (Continued)
This is an application circuit example when the EXT command is used for recording/playback.
RECORDER IC
AGND
MSM6789L
+
VCC
Speaker drive amplifier
+
4M Serial Register MSM66V84B
RWCK
WE
DIN
DOUT
TEST
RFSH NC
RS/A
CS VSS
TAS
SAS
SAD
MSM66V84B
Circuit 9 :
MSM66V84B
DROM
RWCK
TAS
SAS
SADY
SADX
VCC
CS1 CS2 VSS
TEST
DOUT
SASY
TAS
RDCK
SASX
SADY
SADX
Application circuit in microcontroller interface mode with 4-Mbit
serial registers and 2-Mbit serial voice ROMs.
MSM66V84B
SG
SGC
LOUT
AMON
FIN
FOUT
ADIN
AOUT
RWCK
WE
DI/O
TAS
SAS
SADX
MSM6596A-XXX
DGND
MON
NAR
XT
MCUM
LOWPWR
DRAM/SR
A5-A10
MSEL2
RAS
MSEL1
CAS0-CAS7
RSEL1
RSEL2
CE
CS1
TEST
4B/1B
CS2
ACON
CS3
EXTD
TST
CS4
TCK
TEST
MIN
BUSY
RPM
VPM
MOUT
SYNC
TDT0-7
TMD0-3
TMD4
LIN
XT
RWCK
WE
DI/O
DROM
TAS
SADY
SAS
SADX
AVDD
2M Serial Voice ROM
MSM6596A-XXX
8.192 MHz
Microcontroller
RESET
PDWN
RD
WR
CE
D3
D2
D1
D0
DVDD
¡ Semiconductor
MSM6789A/6789L
APPLICATION CIRCUITS (for MSM6789L (3.3 V Version))
This is an application circuit example when the MSM6789L is used in microcontroller interface mode
with four 4-Mbit serial registers and two 2-Mbit serial voice ROMs.