SLAS241H − SEPTEMBER 1999 − REVISED SEPTEMBER 2004 D Low Supply Voltage Range 1.8 V to 3.6 V D Ultralow-Power Consumption D D D D D D Serial Onboard Programming, − Active Mode: 160 µA at 1 MHz, 2.2 V − Standby Mode: 0.7 µA − Off Mode (RAM Retention): 0.1 µA Wake-Up From Standby Mode in less than 6 µs 16-Bit RISC Architecture, 125 ns Instruction Cycle Time Basic Clock Module Configurations: − Various Internal Resistors − Single External Resistor − 32-kHz Crystal − High-Frequency Crystal − Resonator − External Clock Source 16-Bit Timer_A With Three Capture/Compare Registers On-Chip Comparator for Analog Signal Compare Function or Slope A/D Conversion D D D No External Programming Voltage Needed Programmable Code Protection by Security Fuse Family Members Include: MSP430C1101: 1KB ROM, 128B RAM MSP430C1111: 2KB ROM, 128B RAM MSP430C1121: 4KB ROM, 256B RAM MSP430F1101A: 1KB + 128B Flash Memory 128B RAM MSP430F1111A: 2KB + 256B Flash Memory 128B RAM MSP430F1121A: 4KB + 256B Flash Memory 256B RAM Available in a 20-Pin Plastic Small-Outline Wide Body (SOWB) Package, 20-Pin Plastic Small-Outline Thin Package, 20-Pin TVSOP (F11x1A only) and 24-Pin QFN For Complete Module Descriptions, Refer to the MSP430x1xx Family User’s Guide, Literature Number SLAU049 description The Texas Instruments MSP430 family of ultralow power microcontrollers consist of several devices featuring different sets of peripherals targeted for various applications. The architecture, combined with five low power modes is optimized to achieve extended battery life in portable measurement applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that attribute to maximum code efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 6µs. The MSP430x11x1(A) series is an ultralow-power mixed signal microcontroller with a built-in 16-bit timer, versatile analog comparator and fourteen I/O pins. Typical applications include sensor systems that capture analog signals, convert them to digital values, and then process the data for display or for transmission to a host system. Stand alone RF sensor front end is another area of application. The I/O port inputs provide single slope A/D conversion capability on resistive sensors. AVAILABLE OPTIONS PACKAGED DEVICES TA −40°C to 85°C PLASTIC 20-PIN SOWB (DW) PLASTIC 20-PIN TSSOP (PW) MSP430C1101IDW MSP430C1111IDW MSP430C1121IDW MSP430F1101AIDW MSP430F1111AIDW MSP430F1121AIDW MSP430C1101IPW MSP430C1111IPW MSP430C1121IPW MSP430F1101AIPW MSP430F1111AIPW MSP430F1121AIPW PLASTIC 20-PIN TVSOP (DGV) MSP430F1101AIDGV MSP430F1111AIDGV MSP430F1121AIDGV PLASTIC 24-PIN QFN (RGE) MSP430C1101IRGE MSP430C1111IRGE MSP430C1121IRGE MSP430F1101AIRGE MSP430F1111AIRGE MSP430F1121AIRGE Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1999 − 2004 Texas Instruments Incorporated ! "#$ ! %#&'" ($) (#"! " !%$""! %$ *$ $! $! !#$! !(( +,) (#" %"$!!- ($! $"$!!', "'#($ $!- '' %$$!) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SLAS241H − SEPTEMBER 1999 − REVISED SEPTEMBER 2004 RGE PACKAGE (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 P1.7/TA2/TDO/TDI P1.6/TA1/TDI/TCLK P1.5/TA0/TMS P1.4/SMCLK/TCK P1.3/TA2 P1.2/TA1 P1.1/TA0 P1.0/TACLK P2.4/CA1/TA2 P2.3/CA0/TA1 NC VSS XOUT XIN RST/NMI P2.0/ACLK 1 23 22 21 20 2 3 4 5 6 8 9 10 11 18 17 16 15 14 13 P1.5/TA0/TMS P1.4/SMCLK/TCK P1.3/TA2 P1.2/TA1 P1.1/TA0 P1.0/TACLK P2.1/INCLK P2.2/CAOUT/TA0 NC P2.3/CA0/TA1 P2.4/CA1/TA2 NC TEST VCC P2.5/Rosc VSS XOUT XIN RST/NMI P2.0/ACLK P2.1/INCLK P2.2/CAOUT/TA0 P2.5/ROSC VCC TEST P1.7/TA2/TDO/TDI P1.6/TA1/TDI/TCLK NC DW, PW, or DGV PACKAGE (TOP VIEW) Note: NC pins not internally connected Power Pad connection to VSS recommended functional block diagram XIN XOUT VCC P1/JTAG RST/NMI VSS 8 ROSC Oscillator System Clock ACLK Flash/ROM 4KB RAM 256B 2KB 128B 1KB 128B SMCLK I/O Port 1 8 I/Os, with Interrupt Capability POR P2 6 I/O Port 2 6 I/Os, with Interrupt Capability MCLK Test MAB, 4 Bit MAB,MAB, 16 Bit16-Bit JTAG CPU TEST MCB Emulation Module Incl. 16 Reg. Bus Conv MDB, 16-Bit MDB, 16 Bit Watchdog Timer Timer_A3 Comparator A 3 CC Reg 15/16-Bit 2 POST OFFICE BOX 655303 MDB, 8 Bit • DALLAS, TEXAS 75265 SLAS241H − SEPTEMBER 1999 − REVISED SEPTEMBER 2004 Terminal Functions TERMINAL DW, PW, or DGV RGE NO. NO. P1.0/TACLK 13 13 I/O General-purpose digital I/O pin/Timer_A, clock signal TACLK input P1.1/TA0 14 14 I/O General-purpose digital I/O pin/Timer_A, capture: CCI0A input, compare: Out0 output/BSL transmit P1.2/TA1 15 15 I/O General-purpose digital I/O pin/Timer_A, capture: CCI1A input, compare: Out1 output P1.3/TA2 16 16 I/O General-purpose digital I/O pin/Timer_A, capture: CCI2A input, compare: Out2 output P1.4/SMCLK/TCK 17 17 I/O General-purpose digital I/O pin/SMCLK signal output/test clock, input terminal for device programming and test P1.5/TA0/TMS 18 18 I/O General-purpose digital I/O pin/Timer_A, compare: Out0 output/test mode select, input terminal for device programming and test P1.6/TA1/TDI/TCLK 19 20 I/O General-purpose digital I/O pin/Timer_A, compare: Out1 output/test data input or test clock input P1.7/TA2/TDO/TDI† 20 21 I/O General-purpose digital I/O pin/Timer_A, compare: Out2 output/test data output terminal or data input during programming P2.0/ACLK 8 6 I/O General-purpose digital I/O pin/ACLK output P2.1/INCLK 9 7 I/O General-purpose digital I/O pin/Timer_A, clock signal at INCLK P2.2/CAOUT/TA0 10 8 I/O General-purpose digital I/O pin/Timer_A, capture: CCI0B input/ comparator_A, output/BSL receive P2.3/CA0/TA1 11 10 I/O General-purpose digital I/O pin/Timer_A, compare: Out1 output/ comparator_A, input P2.4/CA1/TA2 12 11 I/O General-purpose digital I/O pin/Timer_A, compare: Out2 output/ comparator_A, input P2.5/ROSC 3 24 I/O General-purpose digital I/O pin/input for external resistor that defines the DCO nominal frequency RST/NMI 7 5 I Reset or nonmaskable interrupt input TEST 1 22 I Selects test mode for JTAG pins on Port1. The device protection fuse is connected to TEST. VCC VSS 2 23 4 2 XIN 6 4 XOUT 5 3 NAME QFN Pad NA Package Pad † TDO or TDI is selected via JTAG instruction. DESCRIPTION I/O Supply voltage Ground reference I Input terminal of crystal oscillator O Output terminal of crystal oscillator NA POST OFFICE BOX 655303 QFN package pad connection to VSS recommended. • DALLAS, TEXAS 75265 3 SLAS241H − SEPTEMBER 1999 − REVISED SEPTEMBER 2004 short-form description CPU The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand. Program Counter PC/R0 Stack Pointer SP/R1 SR/CG1/R2 Status Register Constant Generator The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-register operation execution time is one cycle of the CPU clock. Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and constant generator respectively. The remaining registers are general-purpose registers. Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all instructions. instruction set The instruction set consists of 51 instructions with three formats and seven address modes. Each instruction can operate on word and byte data. Table 1 shows examples of the three types of instruction formats; the address modes are listed in Table 2. CG2/R3 General-Purpose Register R4 General-Purpose Register R5 General-Purpose Register R6 General-Purpose Register R7 General-Purpose Register R8 General-Purpose Register R9 General-Purpose Register R10 General-Purpose Register R11 General-Purpose Register R12 General-Purpose Register R13 General-Purpose Register R14 General-Purpose Register R15 Table 1. Instruction Word Formats Dual operands, source-destination e.g. ADD R4,R5 R4 + R5 −−−> R5 Single operands, destination only e.g. CALL PC −−>(TOS), R8−−> PC Relative jump, un/conditional e.g. JNE R8 Jump-on-equal bit = 0 Table 2. Address Mode Descriptions ADDRESS MODE S D Register F F MOV Rs,Rd MOV R10,R11 Indexed F F MOV X(Rn),Y(Rm) MOV 2(R5),6(R6) Symbolic (PC relative) F F MOV EDE,TONI M(EDE) −−> M(TONI) Absolute F F MOV &MEM,&TCDAT M(MEM) −−> M(TCDAT) EXAMPLE OPERATION R10 −−> R11 M(2+R5)−−> M(6+R6) Indirect F MOV @Rn,Y(Rm) MOV @R10,Tab(R6) M(R10) −−> M(Tab+R6) Indirect autoincrement F MOV @Rn+,Rm MOV @R10+,R11 M(R10) −−> R11 R10 + 2−−> R10 F MOV #X,TONI MOV #45,TONI Immediate NOTE: S = source 4 SYNTAX D = destination POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 #45 −−> M(TONI) SLAS241H − SEPTEMBER 1999 − REVISED SEPTEMBER 2004 operating modes The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt event can wake up the device from any of the five low-power modes, service the request and restore back to the low-power mode on return from the interrupt program. The following six operating modes can be configured by software: D Active mode AM; − All clocks are active D Low-power mode 0 (LPM0); − CPU is disabled ACLK and SMCLK remain active. MCLK is disabled D Low-power mode 1 (LPM1); − CPU is disabled ACLK and SMCLK remain active. MCLK is disabled DCO’s dc-generator is disabled if DCO not used in active mode D Low-power mode 2 (LPM2); − CPU is disabled MCLK and SMCLK are disabled DCO’s dc-generator remains enabled ACLK remains active D Low-power mode 3 (LPM3); − CPU is disabled MCLK and SMCLK are disabled DCO’s dc-generator is disabled ACLK remains active D Low-power mode 4 (LPM4); − CPU is disabled ACLK is disabled MCLK and SMCLK are disabled DCO’s dc-generator is disabled Crystal oscillator is stopped POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SLAS241H − SEPTEMBER 1999 − REVISED SEPTEMBER 2004 interrupt vector addresses The interrupt vectors and the power-up starting address are located in the address range of 0FFFFh−0FFE0h. The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence. INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT WORD ADDRESS PRIORITY Power-up External reset Watchdog Flash Memory WDTIFG KEYV (see Note 1) Reset 0FFFEh 15, highest NMI Oscillator fault Flash memory access violation NMIIFG OFIFG ACCVIFG (see Notes 1 & 4) (non)-maskable, (non)-maskable, (non)-maskable 0FFFCh 14 0FFFAh 13 0FFF8h 12 Comparator_A CAIFG maskable 0FFF6h 11 Watchdog Timer WDTIFG maskable 0FFF4h 10 Timer_A3 TACCR0 CCIFG (see Note 2) maskable 0FFF2h 9 Timer_A3 TACCR1 CCIFG. TACCR2 CCIFG TAIFG (see Notes 1 & 2) maskable 0FFF0h 8 7 6 0FFEAh 5 0FFE8h 4 I/O Port P2 (eight flags; see Note 3) P2IFG.0 to P2IFG.7 (see Notes 1 & 2) maskable 0FFE6h 3 I/O Port P1 (eight flags) P1IFG.0 to P1IFG.7 (see Notes 1 & 2) maskable 0FFE4h 2 0FFE2h 1 0FFE0h 0, lowest NOTES: 1. 2. 3. 4. 6 0FFEEh 0FFECh Multiple source flags Interrupt flags are located in the module There are eight Port P2 interrupt flags, but only six Port P2 I/O pins (P2.0−5) implemented on the ’C11x1 and ’F11x1A devices. (non)-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot. Nonmaskable: neither the individual nor the general interrupt-enable bit will disable an interrupt event. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLAS241H − SEPTEMBER 1999 − REVISED SEPTEMBER 2004 special function registers Most interrupt and module enable bits are collected into the lowest address space. Special function register bits not allocated to a functional purpose are not physically present in the device. Simple software access is provided with this arrangement. interrupt enable 1 and 2 Address 7 6 0h 5 4 ACCVIE NMIIE rw-0 WDTIE: OFIE: NMIIE: ACCVIE: Address 3 2 1 OFIE rw-0 0 WDTIE rw-0 rw-0 Watchdog Timer interrupt enable. Inactive if watchdog mode is selected. Active if Watchdog Timer is configured in interval timer mode. Oscillator fault enable (Non)maskable interrupt enable Flash access violation interrupt enable 7 6 5 6 5 4 3 2 4 3 2 1 0 01h interrupt flag register 1 and 2 Address 7 02h NMIIFG rw-0 WDTIFG: OFIFG: NMIIFG: Address 1 OFIFG rw-1 0 WDTIFG rw-(0) Set on Watchdog Timer overflow (in watchdog mode) or security key violation. Reset on VCC power-up or a reset condition at RST/NMI pin in reset mode. Flag set on oscillator fault Set via RST/NMI-pin 7 6 5 4 3 2 1 0 03h Legend rw: rw-0,1: rw-(0,1): Bit can be read and written. Bit can be read and written. It is Reset or Set by PUC. Bit can be read and written. It is Reset or Set by POR. SFR bit is not present in device POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SLAS241H − SEPTEMBER 1999 − REVISED SEPTEMBER 2004 memory organization MSP430C1101 MSP430C1111 MSP430C1121 Memory Main: interrupt vector Main: code memory Size ROM ROM 1KB ROM 0FFFFh−0FFE0h 0FFFFh−0FC00h 2KB ROM 0FFFFh−0FFE0h 0FFFFh−0F800h 4KB ROM 0FFFFh−0FFE0h 0FFFFh−0F000h Information memory Size Flash Not applicable Not applicable Not applicable Boot memory Size ROM Not applicable Not applicable Not applicable Size 128 Byte 027Fh − 0200h 128 Byte 027Fh − 0200h 256 Byte 02FFh − 0200h 16-bit 8-bit 8-bit SFR 01FFh − 0100h 0FFh − 010h 0Fh − 00h 01FFh − 0100h 0FFh − 010h 0Fh − 00h 01FFh − 0100h 0FFh − 010h 0Fh − 00h RAM Peripherals MSP430F1101A MSP430F1111A MSP430F1121A Memory Main: interrupt vector Main: code memory Size Flash Flash 1KB Flash 0FFFFh−0FFE0h 0FFFFh−0FC00h 2KB Flash 0FFFFh−0FFE0h 0FFFFh−0F800h 4KB Flash 0FFFFh−0FFE0h 0FFFFh−0F000h Information memory Size Flash 128 Byte 010FFh − 01080h 256 Byte 010FFh − 01000h 256 Byte 010FFh − 01000h Boot memory Size ROM 1KB 0FFFh − 0C00h 1KB 0FFFh − 0C00h 1KB 0FFFh − 0C00h Size 128 Byte 027Fh − 0200h 128 Byte 027Fh − 0200h 256 Byte 02FFh − 0200h 16-bit 8-bit 8-bit SFR 01FFh − 0100h 0FFh − 010h 0Fh − 00h 01FFh − 0100h 0FFh − 010h 0Fh − 00h 01FFh − 0100h 0FFh − 010h 0Fh − 00h RAM Peripherals bootstrap loader (BSL) The MSP430 bootstrap loader (BSL) enables users to program the flash memory or RAM using a UART serial interface. Access to the MSP430 memory via the BSL is protected by user-defined password. For complete description of the features of the BSL and its implementation, see the Application report Features of the MSP430 Bootstrap Loader, Literature Number SLAA089. 8 BSL Function DW, PW & DGV Package Pins RGE Package Pins Data Transmit 14 - P1.1 14 - P1.1 Data Receive 10 - P2.2 8 - P2.2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLAS241H − SEPTEMBER 1999 − REVISED SEPTEMBER 2004 flash memory The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include: D Flash memory has n segments of main memory and two segments of information memory (A and B) of 128 bytes each. Each segment in main memory is 512 bytes in size. D Segments 0 to n may be erased in one step, or each segment may be individually erased. D Segments A and B can be erased individually, or as a group with segments 0−n. Segments A and B are also called information memory. D New devices may have some bytes programmed in the information memory (needed for test during manufacturing). The user should perform an erase of the information memory prior to the first use. 0FFFFh 0FE00h Segment0 w/ Interrupt Vectors 0FDFFh 0FC00h Segment1 0FBFFh 0FA00h Segment2 0F9FFh 0F800h Segment3 0F7FFh 0F600h Segment4 0F5FFh 0F400h Segment5 0F3FFh 0F200h Segment6 0F1FFh 0F000h Segment7 010FFh 01080h SegmentA 0107Fh 01000h SegmentB Flash Main Memory Information Memory NOTE: All segments not implemented on all devices. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 SLAS241H − SEPTEMBER 1999 − REVISED SEPTEMBER 2004 peripherals Peripherals are connected to the CPU through data, address, and control busses and can be handled using all instructions. For complete module descriptions, refer to the MSP430x1xx Family User’s Guide, literature number SLAU049. oscillator and system clock The clock system is supported by the basic clock module that includes support for a 32768-Hz watch crystal oscillator, an internal digitally-controlled oscillator (DCO) and a high frequency crystal oscillator. The basic clock module is designed to meet the requirements of both low system cost and low-power consumption. The internal DCO provides a fast turn-on clock source and stabilizes in less than 6 µs. The basic clock module provides the following clock signals: D Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high frequency crystal. D Main clock (MCLK), the system clock used by the CPU. D Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules. digital I/O There are two 8-bit I/O ports implemented—ports P1 and P2 (only six P2 I/O signals are available on external pins): D D D D All individual I/O bits are independently programmable. Any combination of input, output, and interrupt conditions is possible. Edge-selectable interrupt input capability for all the eight bits of port P1 and six bits of port P2. Read/write access to port-control registers is supported by all instructions. NOTE: Six bits of port P2, P2.0 to P2.5, are available on external pins − but all control and data bits for port P2 are implemented. watchdog timer The primary function of the watchdog timer (WDT) module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be configured as an interval timer and can generate interrupts at selected time intervals. comparator_A The primary function of the comparator_A module is to support precision slope analog-to-digital conversions, battery-voltage supervision, and monitoring of external analog signals. 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLAS241H − SEPTEMBER 1999 − REVISED SEPTEMBER 2004 timer_A3 Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. Timer_A3 Signal Connections Input Pin Number DW, PW, DGV RGE 13 - P1.0 13 - P1.0 Device Input Signal Module Input Name TACLK TACLK ACLK ACLK SMCLK SMCLK Module Block Timer Module Output Signal Output Pin Number DW, PW DGV RGE NA 9 - P2.1 7 - P2.1 INCLK INCLK 14 - P1.1 14 - P1.1 TA0 CCI0A 14 - P1.1 14 - P1.1 10 - P2.2 8 - P2.2 TA0 CCI0B 18 - P1.5 18 - P1.5 11 - P2.3 10 - P2.3 15 - P1.2 15 - P1.2 19 - P1.6 20 - P1.6 15 - P1.2 16 - P1.3 15 - P1.2 16 - P1.3 VSS VCC TA1 GND VCC CCI1A CAOUT (internal) CCI1B VSS VCC GND CCR0 CCR1 TA0 TA1 TA2 VCC CCI2A 12 - P2.4 11 - P2.4 ACLK (internal) CCI2B 16 - P1.3 16 - P1.3 VSS VCC GND 20 - P1.7 21 - P1.7 CCR2 TA2 VCC POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 SLAS241H − SEPTEMBER 1999 − REVISED SEPTEMBER 2004 peripheral file map PERIPHERALS WITH WORD ACCESS Timer_A Reserved Reserved Reserved Reserved Capture/compare register Capture/compare register Capture/compare register Timer_A register Reserved Reserved Reserved Reserved Capture/compare control Capture/compare control Capture/compare control Timer_A control Timer_A interrupt vector TACCTL2 TACCTL1 TACCTL0 TACTL TAIV 017Eh 017Ch 017Ah 0178h 0176h 0174h 0172h 0170h 016Eh 016Ch 016Ah 0168h 0166h 0164h 0162h 0160h 012Eh TACCR2 TACCR1 TACCR0 TAR Flash Memory Flash control 3 Flash control 2 Flash control 1 FCTL3 FCTL2 FCTL1 012Ch 012Ah 0128h Watchdog Watchdog/timer control WDTCTL 0120h PERIPHERALS WITH BYTE ACCESS 12 Comparator_A Comparator_A port disable Comparator_A control 2 Comparator_A control 1 CAPD CACTL2 CACTL1 05Bh 05Ah 059h Basic Clock Basic clock system control 2 Basic clock system control 1 DCO clock frequency control BCSCTL2 BCSCTL1 DCOCTL 058h 057h 056h Port P2 Port P2 selection Port P2 interrupt enable Port P2 interrupt edge select Port P2 interrupt flag Port P2 direction Port P2 output Port P2 input P2SEL P2IE P2IES P2IFG P2DIR P2OUT P2IN 02Eh 02Dh 02Ch 02Bh 02Ah 029h 028h Port P1 Port P1 selection Port P1 interrupt enable Port P1 interrupt edge select Port P1 interrupt flag Port P1 direction Port P1 output Port P1 input P1SEL P1IE P1IES P1IFG P1DIR P1OUT P1IN 026h 025h 024h 023h 022h 021h 020h Special Function SFR interrupt flag 2 SFR interrupt flag 1 SFR interrupt enable 2 SFR interrupt enable 1 IFG2 IFG1 IE2 IE1 003h 002h 001h 000h POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLAS241H − SEPTEMBER 1999 − REVISED SEPTEMBER 2004 absolute maximum ratings† Voltage applied at VCC to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4.1 V Voltage applied to any pin (see Note) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VCC+0.3 V Diode current at any device terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±2 mA Storage temperature, Tstg (unprogrammed device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 150°C Storage temperature, Tstg (programmed device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE: All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is applied to the TEST pin when blowing the JTAG fuse. recommended operating conditions MIN Supply voltage during program execution, VCC (see Note 1) Supply voltage during program/erase flash memory, VCC MAX 1.8 3.6 MSP430F11x1A 1.8 3.6 MSP430F11x1A 2.7 Supply voltage, VSS 3.6 0 Operating free-air temperature range, TA MSP430x11x1(A) LF mode selected, XTS=0 LFXT1 crystal frequency, f(LFXT1) (see Note 1 & 2) NOM MSP430C11x1 −40 Watch crystal Processor frequency f(system) (MCLK signal) 85 V °C Hz 450 8000 1000 8000 VCC = 1.8 V, MSP430x11x1(A) dc 4.15 VCC = 3.6 V, MSP430x11x1(A) dc 8 Crystal V V 32 768 Ceramic resonator XT1 mode selected, XTS=1 UNITS kHz MHz NOTES: 1. In LF mode, the LFXT1 oscillator requires a watch crystal. A 5.1MΩ resistor from XOUT to VSS is recommended when VCC < 2.5 V. In XT1 mode, the LFXT1 and XT2 oscillators accept a ceramic resonator or crystal up to 4.15MHz at VCC ≥ 2.2 V. In XT1 mode, the LFXT1 and XT2 oscillators accept a ceramic resonator or crystal up to 8MHz at VCC ≥ 2.8 V. 2. In LF mode, the LFXT1 oscillator requires a watch crystal. In XT1 mode, LFXT1 accepts a ceramic resonator or a crystal. fSYSTEM (MHz) 8.0 MHz ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ Supply voltage range, ’x11x1(A), during program execution 4.15 MHz 1.8 V 2.7 V 3 V Supply Voltage − V Supply voltage range, ’F11x1A, during flash memory programming 3.6 V NOTE: Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum VCC of 2.7 V. Figure 1. Frequency vs Supply Voltage, MSP430x11x1(A) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 SLAS241H − SEPTEMBER 1999 − REVISED SEPTEMBER 2004 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) supply current (into VCC) excluding external current PARAMETER I(AM) TEST CONDITIONS 160 200 VCC = 3 V 240 300 F11x1A Low-power mode, (LPM0) Low-power mode, (LPM2) C11x1 C11x1 3.2 200 250 300 350 3 5 VCC = 3 V 11 18 VCC = 2.2 V 30 40 VCC = 3 V 51 60 VCC = 2.2 V 32 45 VCC = 3 V 55 70 TA = −40°C to + 85°C, f(MCLK) = f(SMCLK) = 0 MHz, f(ACLK) = 32,768 Hz, SCG0 = 0 TA = −40°C to + 85°C, f(MCLK) = f(SMCLK) = 0 MHz, f(ACLK) = 32,768 Hz, SCG0 = 1 VCC = 2.2 V 11 14 VCC = 3 V 17 22 VCC = 2.2 V 1.2 1.7 2 2.7 0.8 1.2 0.7 1 1.6 2.3 1.8 2.2 1.6 1.9 2.3 3.4 0.1 0.5 0.1 0.5 0.4 0.8 0.1 0.5 0.1 0.5 0.8 1.9 TA = 85°C TA = −40°C f(MCLK) = 0 MHz, f(SMCLK) = 0 MHz, f(ACLK) = 32,768 Hz, SCG0 = 1 TA = −40°C TA = 25°C TA = 85°C F11x1A 2 2.5 VCC = 2.2 V TA = 25°C TA = 85°C Low-power mode, (LPM4) 1.3 TA = −40°C to + 85°C, Program executes in flash f(MCLK) = f(SMCLK) = f(ACLK) = 4096 Hz TA = −40°C to + 85°C, f(MCLK) = 0, f(SMCLK) = 1 MHz, f(ACLK) = 32,768 Hz TA = −40°C to + 85°C, f(MCLK) = 0, f(SMCLK) = 1 MHz, f(ACLK) = 32,768 Hz TA = −40°C TA = 25°C Low-power mode, (LPM3) F11x1A I(LPM4) VCC = 2.2 V VCC = 2.2 V TA = −40 −40°C C to + 85°C, 85 C, f(MCLK) = f(SMCLK) = f(ACLK) = 4096 Hz VCC = 3 V TA = −40°C to + 85°C, VCC = 2.2 V fMCLK = f(SMCLK) = 1 MHz, f(ACLK) = 32,768 Hz, VCC = 3 V Program executes in flash F11x1A I(LPM3) MAX C11x1 C11x1 I(LPM2) TYP TA = −40°C to + 85°C, f(MCLK) = f(SMCLK) = 1 MHz, f(ACLK) = 32,768 Hz Active mode I(CPUOff) MIN TA = −40°C TA = 25°C VCC = 3 V VCC = 2.2 V VCC = 3 V VCC = 2.2 V/3 V f(MCLK) = 0 MHz, f(SMCLK) = 0 MHz, f(ACLK) = 0 Hz, SCG0 = 1 VCC = 2.2 V/3 V TA = 85°C NOTE: All inputs are tied to 0 V or VCC. Outputs do not source or sink any current. current consumption of active mode versus system frequency, C version, F version IAM = IAM[1 MHz] × fsystem [MHz] current consumption of active mode versus supply voltage, C version IAM = IAM[3 V] + 105 µA/V × (VCC−3 V) current consumption of active mode versus supply voltage, F version IAM = IAM[3 V] + 120 µA/V × (VCC−3 V) 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT µA µA µA µA µA SLAS241H − SEPTEMBER 1999 − REVISED SEPTEMBER 2004 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) Schmitt-trigger inputs − Ports P1 and P2; (P1.0 to P1.7, P2.0 to P2.5) PARAMETER TEST CONDITIONS VIT+ Positive-going input threshold voltage VIT− Negative-going input threshold voltage Vhys Input voltage hysteresis (VIT+ − VIT−) MIN TYP MAX VCC = 2.2 V VCC = 3 V 1.1 1.5 1.5 1.9 VCC = 2.2 V VCC = 3 V VCC = 2.2 V 0.4 0.9 0.9 1.3 0.3 1.1 VCC = 3 V 0.5 1 UNIT V V V standard inputs − RST/NMI, JTAG: TCK, TMS, TDI/TCLK PARAMETER VIL VIH TEST CONDITIONS Low-level input voltage VCC = 2.2 V / 3 V High-level input voltage MIN TYP VSS 0.8×VCC MAX VSS+0.6 VCC UNIT V V inputs Px.x, TAx PARAMETER t(int) External interrupt timing TEST CONDITIONS VCC 2.2 V/3 V Port P1, P2: P1.x to P2.x, External trigger signal for the interrupt flag, (see Note 1) t(cap) Timer_A, capture timing TA0, TA1, TA2 f(TAext) Timer_A clock frequency externally applied to pin TACLK, INCLK t(H) = t(L) f(TAint) Timer_A clock frequency SMCLK or ACLK signal selected MIN TYP MAX 1.5 2.2 V 62 3V 50 2.2 V 62 3V 50 UNIT cycle ns ns 2.2 V 8 3V 10 2.2 V 8 3V 10 MHz MHz NOTES: 1. The external signal sets the interrupt flag every time the minimum t(int) cycle and time parameters are met. It may be set even with trigger signals shorter than t(int). Both the cycle and timing specifications must be met to ensure the flag is set. t(int) is measured in MCLK cycles. leakage current PARAMETER Ilkg(Px.x) High-impedance leakage current TEST CONDITIONS MIN TYP MAX Port P1: P1.x, 0 ≤ × ≤ 7 (see Notes 1, 2) VCC = 2.2 V/3 V, ±50 Port P2: P2.x, 0 ≤ × ≤ 5 (see Notes 1, 2) VCC = 2.2 V/3 V, ±50 UNIT nA NOTES: 1. The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted. 2. The leakage of the digital port pins is measured individually. The port pin must be selected for input and there must be no optional pullup or pulldown resistor. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 SLAS241H − SEPTEMBER 1999 − REVISED SEPTEMBER 2004 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) outputs − Ports P1 and P2; (P1.0 to P1.7, P2.0 to P2.5) PARAMETER VOH VOH VOL TEST CONDITIONS High-level output voltage Port 1 and Port 2 (C11x1) Port 1 (F11x1A) High-level output voltage Port 2 (F11x1A) Low-level output voltage Port 1 and Port 2 (C11x1, F11x1A) I(OHmax) = −1.5 mA I(OHmax) = −6 mA VCC = 2.2 V I(OHmax) = −1.5 mA I(OHmax) = −6 mA VCC = 3 V I(OHmax) = −1 mA I(OHmax) = −3.4 mA VCC = 2.2 V I(OHmax) = −1 mA I(OHmax) = −3.4 mA VCC = 3 V I(OLmax) = 1.5 mA I(OLmax) = 6 mA VCC = 2.2 V MIN See Note 1 MAX VCC VCC VCC−0.25 VCC−0.6 VCC VCC VCC−0.25 VCC−0.6 VCC VCC VCC−0.25 VCC−0.6 VCC VCC See Note 2 VSS VSS VSS+0.25 VSS+0.6 See Note 1 VSS VSS+0.25 See Note 2 See Note 1 See Note 2 See Note 3 See Note 3 See Note 3 See Note 3 See Note 1 I(OLmax) = 1.5 mA TYP VCC−0.25 VCC−0.6 UNIT V V V VCC = 3 V I(OLmax) = 6 mA See Note 2 VSS VSS+0.6 NOTES: 1. The maximum total current, IOHmax and IOLmax, for all outputs combined, should not exceed ±12 mA to hold the maximum voltage drop specified. 2. The maximum total current, IOHmax and IOLmax, for all outputs combined, should not exceed ±48 mA to hold the maximum voltage drop specified. 3. One output loaded at a time. output frequency PARAMETER fP20 fTAx Output frequency TEST CONDITIONS 2.2 V/3 V TA0, TA1, TA2, CL = 20 pF Internal clock source, SMCLK signal applied (see Note 1) 2.2 V/3 V P1.4/SMCLK, CL = 20 pF tXdc VCC P2.0/ACLK, CL = 20 pF Duty cycle of O/P frequency fSMCLK = fLFXT1 = fXT1 fSMCLK = fLFXT1 = fLF fSMCLK = fLFXT1/n fSMCLK = fDCOCLK P2.0/ACLK, CL = 20 pF 2.2 V/3 V fP20 = fLFXT1 = fXT1 fP20 = fLFXT1 = fLF fP20 = fLFXT1/n TA0, TA1, TA2, CL = 20 pF, duty cycle = 50% 2.2 V/3 V MIN dc fSystem 40% 60% 35% 65% 50%− 15 ns 50% 50%+ 15 ns 50%− 15 ns 50% 50%+ 15 ns 40% 2.2 V/3 V POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MAX UNIT fSystem MHz 60% 30% tTAdc 2.2 V/3 V NOTE 1: The limits of the system clock MCLK has to be met. MCLK and SMCLK can have different frequencies. 16 TYP 70% 50% 0 ±50 ns SLAS241H − SEPTEMBER 1999 − REVISED SEPTEMBER 2004 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) outputs − Ports P1 and P2 (continued) TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE 25 TA = 25°C VCC = 2.2 V P1.0 14 I OL − Typical Low-Level Output Current − mA I OL − Typical Low-Level Output Current − mA 16 12 TA = 85°C 10 8 6 4 2 0 0.0 0.5 1.0 1.5 2.0 VCC = 3 V P1.0 20 TA = 85°C 15 10 5 0 0.0 2.5 TA = 25°C 0.5 VOL − Low-Level Output Voltage − V 1.0 Figure 2 I OH − Typical High-Level Output Current − mA I OH − Typical High-Level Output Current − mA 3.0 3.5 0 VCC = 2.2 V P1.0 −4 −6 −8 −10 TA = 85°C −12 TA = 25°C 0.5 2.5 TYPICAL HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE 0 −14 0.0 2.0 Figure 3 TYPICAL HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE −2 1.5 VOL − Low-Level Output Voltage − V 1.0 1.5 2.0 2.5 VOH − High-Level Output Voltage − V VCC = 3 V P1.0 −5 −10 −15 −20 TA = 85°C −25 −30 0.0 TA = 25°C 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VOH − High-Level Output Voltage − V Figure 5 Figure 4 NOTE: One output loaded at a time. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17 SLAS241H − SEPTEMBER 1999 − REVISED SEPTEMBER 2004 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) optional resistors, individually programmable with ROM code (see Note 1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT R(opt1) 2.5 5 10 kΩ R(opt2) 3.8 7.7 15 kΩ R(opt3) 7.6 15 31 kΩ R(opt4) 11.5 23 46 kΩ R(opt5) 23 45 90 kΩ R(opt6) Resistors, individually programmable with ROM code, all port pins, values applicable for pulldown and pullup VCC = 2.2 V/3 V 46 90 180 kΩ R(opt7) 70 140 280 kΩ R(opt8) 115 230 460 kΩ R(opt9) 160 320 640 kΩ R(opt10) 205 420 830 kΩ MAX UNIT NOTE 1: Optional resistors Roptx for pulldown or pullup are not available in standard flash memory device MSP430F11x1A. wake-up from lower power modes (LPMx) PARAMETER TEST CONDITIONS MIN TYP t(LPM0) t(LPM2) VCC = 2.2 V/3 V VCC = 2.2 V/3 V f(MCLK) = 1 MHz, f(MCLK) = 2 MHz, VCC = 2.2 V/3 V VCC = 2.2 V/3 V 6 t(LPM3) f(MCLK) = 3 MHz, VCC = 2.2 V/3 V 6 f(MCLK) = 1 MHz, f(MCLK) = 2 MHz, VCC = 2.2 V/3 V VCC = 2.2 V/3 V 6 f(MCLK) = 3 MHz, NOTE 1: Parameter applicable only if DCOCLK is used for MCLK. VCC = 2.2 V/3 V 6 Delay time (see Note 1) t(LPM4) 100 ns 100 6 6 µs µs RAM PARAMETER MIN NOM MAX UNIT V(RAMh) CPU halted (see Note 1) 1.6 V NOTE 1: This parameter defines the minimum supply voltage VCC when the data in the program memory RAM remains unchanged. No program execution should happen during this supply voltage condition. 18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLAS241H − SEPTEMBER 1999 − REVISED SEPTEMBER 2004 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) Comparator_A (see Note 1) PARAMETER TEST CONDITIONS MIN TYP MAX VCC = 2.2 V VCC = 3 V 25 40 45 60 I(DD) CAON=1, CARSEL=0, CAREF=0 CAON=1, CARSEL=0, CAREF=1/2/3, no load at P2.3/CA0/TA1 and P2.4/CA1/TA2 VCC = 2.2 V 30 50 I(Refladder/RefDiode) VCC = 3 V 45 71 CAON =1 VCC = 2.2 V/3 V 0 PCA0=1, CARSEL=1, CAREF=1, No load at P2.3/CA0/TA1 and P2.4/CA1/TA2 VCC = 2.2 V/3 V 0.23 0.24 0.25 PCA0=1, CARSEL=1, CAREF=2, No load at P2.3/CA0/TA1 and P2.4/CA1/TA2 VCC = 2.2 V/3 V 0.47 0.48 0.5 VCC = 2.2 V 390 480 540 VCC = 3 V 400 490 550 −30 V(IC) V(Ref025) V(Ref050) Common-mode input voltage Voltage @ 0.25 V V node CC Voltage @ 0.5V V CC CC node CC VCC−1 V(RefVT) (see Figure 6 and Figure 7) V(offset) Vhys Offset voltage PCA0=1, CARSEL=1, CAREF=3, No load at P2.3/CA0/TA1 and P2.4/CA1/TA2, TA = 85°C See Note 2 Input hysteresis CAON=1 VCC = 2.2 V/3 V VCC = 2.2 V/3 V 0 TA = 25 25°C, C, Overdrive 10 mV, Without filter: CAF=0 VCC = 2.2 V VCC = 3 V 160 90 150 240 TA = 25 25°C, C, Overdrive 10 mV, With filter: CAF=1 VCC = 2.2 V VCC = 3 V 1.4 1.9 3.4 0.9 1.5 2.6 25°C, TA = 25 C, Overdrive 10 mV, Without filter: CAF=0 VCC = 2.2 V VCC = 3 V 130 210 300 80 150 240 TA = 25 25°C, C, Overdrive 10 mV, With filter: CAF=1 VCC = 2.2 V VCC = 3 V 1.4 1.9 3.4 0.9 1.5 2.6 t(response LH) t(response HL) UNIT µA µA V mV 30 mV 0.7 1.4 mV 210 300 ns µs ns µs NOTES: 1. The leakage current for the Comparator_A terminals is identical to Ilkg(Px.x) specification. 2. The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A inputs on successive measurements. The two successive measurements are then summed together. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 19 SLAS241H − SEPTEMBER 1999 − REVISED SEPTEMBER 2004 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) 650 650 VCC = 2.2 V V(REFVT) − Reference Volts −mV V(REFVT) − Reference Volts −mV VCC = 3 V 600 Typical 550 500 450 400 −45 −25 −5 15 35 55 75 600 Typical 550 500 450 400 −45 95 −25 −5 15 35 55 TA − Free-Air Temperature − °C 0 V VCC 1 CAF CAON Low Pass Filter V+ V− + _ 0 0 1 1 To Internal Modules CAOUT Set CAIFG Flag τ ≈ 2.0 µs Figure 8. Block Diagram of Comparator_A Module VCAOUT Overdrive V− 400 mV V+ t(response) Figure 9. Overdrive Definition 20 95 Figure 7. V(RefVT) vs Temperature, VCC = 2.2 V Figure 6. V(RefVT) vs Temperature, VCC = 3 V 0 75 TA − Free-Air Temperature − °C POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLAS241H − SEPTEMBER 1999 − REVISED SEPTEMBER 2004 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) PUC/POR PARAMETER TEST CONDITIONS t(POR_Delay) Internal time delay to release POR VPOR VCC threshold at which POR release delay time begins (see Note 1) TA = −40°C TA = 25°C VCC threshold required to generate a POR (see Note 2) VCC |dV/dt| ≥ 1V/ms V(min) MIN VCC = 2.2 V/3 V TA = 85°C TYP MAX UNIT 150 250 µs 1.4 1.8 V 1.1 1.5 V 0.8 1.2 V 0.2 V t(reset) RST/NMI low time for PUC/POR Reset is accepted internally 2 µs NOTES: 1. VCC rise time dV/dt ≥ 1V/ms. 2. When driving VCC low in order to generate a POR condition, VCC should be driven to 200mV or lower with a dV/dt equal to or less than −1V/ms. The corresponding rising VCC must also meet the dV/dt requirement equal to or greater than +1V/ms. V VCC V POR No POR POR V (min) POR t Figure 10. Power-On Reset (POR) vs Supply Voltage 2.0 1.8 1.8 V POR [V] 1.6 1.4 1.2 1.5 Max 1.2 1.4 1.0 Min 1.1 0.8 0.8 0.6 0.4 0.2 25°C 0 −40 −20 0 20 40 60 80 Temperature [°C] Figure 11. VPOR vs Temperature POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 21 SLAS241H − SEPTEMBER 1999 − REVISED SEPTEMBER 2004 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) DCO PARAMETER TEST CONDITIONS MIN TYP MAX 0.12 0.15 Rsel = 0, DCO = 3, MOD = 0, DCOR = 0, TA = 25°C VCC = 2.2 V VCC = 3 V 0.08 f(DCO03) 0.08 0.13 0.16 0.19 0.23 Rsel = 1, DCO = 3, MOD = 0, DCOR = 0, TA = 25°C VCC = 2.2 V VCC = 3 V 0.14 f(DCO13) 0.14 0.18 0.22 f(DCO23) Rsel = 2, DCO = 3, MOD = 0, DCOR = 0, TA = 25°C VCC = 2.2 V VCC = 3 V 0.22 0.30 0.36 0.22 0.28 0.34 f(DCO33) Rsel = 3, DCO = 3, MOD = 0, DCOR = 0, TA = 25°C VCC = 2.2 V VCC = 3 V 0.37 0.49 0.59 0.37 0.47 0.56 f(DCO43) Rsel = 4, DCO = 3, MOD = 0, DCOR = 0, TA = 25°C VCC = 2.2 V VCC = 3 V 0.61 0.77 0.93 0.61 0.75 0.9 f(DCO53) Rsel = 5, DCO = 3, MOD = 0, DCOR = 0, TA = 25°C VCC = 2.2 V VCC = 3 V 1 1.2 1.5 1 1.3 1.5 f(DCO63) Rsel = 6, DCO = 3, MOD = 0, DCOR = 0, TA = 25°C VCC = 2.2 V VCC = 3 V f(DCO73) Rsel = 7, DCO = 3, MOD = 0, DCOR = 0, TA = 25°C f(DCO77) Rsel = 7, DCO = 7, MOD = 0, DCOR = 0, TA = 25°C f(DCO47) Rsel = 4, DCO = 7, MOD = 0, DCOR = 0, TA = 25°C S(Rsel) S(DCO) 1.6 1.9 2.2 1.69 2 2.29 VCC = 2.2 V VCC = 3 V 2.4 2.9 3.4 2.7 3.2 3.65 VCC = 2.2 V 4 4.5 4.9 4.4 4.9 5.4 VCC = 2.2 V/3 V fDCO40 x1.7 fDCO40 x2.1 fDCO40 x2.5 SR = fRsel+1/fRsel VCC = 2.2 V/3 V 1.35 1.65 2 SDCO = fDCO+1/fDCO VCC = 2.2 V/3 V 1.07 1.12 1.16 Temperature drift, Rsel = 4, DCO = 3, MOD = 0 (see Note 1) VCC = 2.2 V −0.31 −0.36 −0.40 Dt VCC = 3 V −0.33 −0.38 −0.43 DV Drift with VCC variation, Rsel = 4, DCO = 3, MOD = 0 (see Note 1) 0 5 10 VCC = 3 V VCC = 2.2 V/3 V f(DCOx7) f(DCOx0) Max Min Max Min ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ 2.2 V 1 f DCOCLK Frequency Variance NOTE 1: These parameters are not production tested. 3V 0 1 VCC 3 4 5 6 DCO Steps Figure 12. DCO Characteristics 22 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 UNIT MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz ratio %/°C %/V SLAS241H − SEPTEMBER 1999 − REVISED SEPTEMBER 2004 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) main DCO characteristics D Individual devices have a minimum and maximum operation frequency. The specified parameters for f(DCOx0) to f(DCOx7) are valid for all devices. D All ranges selected by Rsel(n) overlap with Rsel(n+1): Rsel0 overlaps Rsel1, ... Rsel6 overlaps Rsel7. D DCO control bits DCO0, DCO1, and DCO2 have a step size as defined by parameter SDCO. D Modulation control bits MOD0 to MOD4 select how often f(DCO+1) is used within the period of 32 DCOCLK cycles. The frequency f(DCO) is used for the remaining cycles. The frequency is an average equal to: f average + MOD 32 f (DCO) f (DCO)1) f (DCO))(32*MOD) f (DCO)1) DCO when using ROSC (see Note 1) PARAMETER TEST CONDITIONS fDCO, DCO output frequency Rsel = 4, DCO = 3, MOD = 0, DCOR = 1, TA = 25°C Dt, Temperature drift Rsel = 4, DCO = 3, MOD = 0, DCOR = 1 Dv, Drift with VCC variation Rsel = 4, DCO = 3, MOD = 0, DCOR = 1 VCC 2.2 V MIN NOM MAX UNIT 1.8±15% MHz 1.95±15% MHz 2.2 V/3 V ±0.1 %/°C 2.2 V/3 V 10 %/V 3V NOTES: 1. ROSC = 100kΩ. Metal film resistor, type 0257. 0.6 watt with 1% tolerance and TK = ±50ppm/°C. crystal oscillator, LFXT1 PARAMETER CXIN CXOUT VIL VIH Input capacitance Output capacitance TEST CONDITIONS XTS=0; LF mode selected. VCC = 2.2 V / 3 V XTS=1; XT1 mode selected. VCC = 2.2 V / 3 V (see Note 1) XTS=0; LF mode selected. VCC = 2.2 V / 3 V XTS=1; XT1 mode selected. VCC = 2.2 V / 3 V (see Note 1) MIN TYP MAX 12 pF 2 12 pF 2 VSS 0.2×VCC 0.8×VCC VCC NOTES: 1. Requires external capacitors at both terminals. Values are specified by crystal manufacturers. 2. Applies only when using an external logic-level clock source. Not applicable when using a crystal or resonator. Input levels at XIN VCC = 2.2 V/3 V (see Note 2) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT V 23 SLAS241H − SEPTEMBER 1999 − REVISED SEPTEMBER 2004 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) Flash Memory TEST CONDITIONS PARAMETER VCC(PGM/ ERASE) VCC MIN NOM MAX UNIT Program and Erase supply voltage 2.7 3.6 V fFTG IPGM Flash Timing Generator frequency 257 476 kHz Supply current from VCC during program 2.7 V/ 3.6 V 3 5 mA IERASE tCPT Supply current from VCC during erase 2.7 V/ 3.6 V 3 7 mA Cumulative program time see Note 1 2.7 V/ 3.6 V 4 ms tCMErase Cumulative mass erase time see Note 2 2.7 V/ 3.6 V Program/Erase endurance TJ = 25°C 200 104 ms 105 tRetention Data retention duration tWord tBlock, 0 Word or byte program time Block program time for 1st byte or word tBlock, 1-63 tBlock, End Block program time for each additional byte or word tMass Erase tSeg Erase Mass erase time 5297 Segment erase time 4819 Block program end-sequence wait time cycles 100 years 35 30 21 see Note 3 tFTG 6 NOTES: 1. The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming methods: individual word/byte write and block write modes. 2. The mass erase duration generated by the flash timing generator is at least 11.1ms ( = 5297x1/fFTG,max = 5297x1/476kHz). To achieve the required cumulative mass erase time the Flash Controller’s mass erase operation can be repeated until this time is met. (A worst case minimum of 19 cycles are required). 3. These values are hardwired into the Flash Controller’s state machine (tFTG = 1/fFTG). JTAG Interface TEST CONDITIONS PARAMETER fTCK TCK input frequency see Note 1 RInternal Internal pull-down resistance on TEST see Note 2 VCC MIN 2.2 V 0 NOM MAX UNIT 5 MHz 3V 0 10 MHz 2.2 V/ 3 V 25 60 90 kΩ MIN NOM MAX NOTES: 1. fTCK may be restricted to meet the timing requirements of the module selected. 2. TEST pull-down resistor implemented in all versions. JTAG Fuse (see Note 1) TEST CONDITIONS PARAMETER VCC(FB) Supply voltage during fuse-blow condition TA = 25°C Voltage level on TEST for fuse-blow - ’C11x1 VFB IFB tFB VCC 2.5 3.5 Voltage level on TEST for fuse-blow - ’F11x1A 6 Supply current into TEST during fuse blow Time to blow fuse UNIT V 3.9 7 V V 100 mA 1 ms NOTES: 1. Once the fuse is blown, no further access to the MSP430 JTAG/Test and emulation features is possible. The JTAG block is switched to bypass mode. 24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLAS241H − SEPTEMBER 1999 − REVISED SEPTEMBER 2004 APPLICATION INFORMATION input/output schematic Port P1, P1.0 to P1.3, input/output with Schmitt-trigger VCC P1SEL.x 0 P1DIR.x (See Note 1) 1 Direction Control From Module (See Note 2) 0 P1OUT.x Pad Logic P1.0 − P1.3 1 Module X OUT (See Note 2) (See Note 1) P1IN.x GND EN Module X IN P1IRQ.x D P1IE.x P1IFG.x Q EN Set Interrupt Flag Interrupt Edge Select P1IES.x P1SEL.x NOTE: x = Bit/identifier, 0 to 3 for port P1 PnSel.x PnDIR.x Direction control from module PnOUT.x Module X OUT PnIN.x Module X IN PnIE.x PnIFG.x PnIES.x P1Sel.0 P1DIR.0 P1DIR.0 P1OUT.0 P1IN.0 P1IFG.0 P1IES.0 P1DIR.1 P1DIR.1 P1OUT.1 TACLK† CCI0A† P1IE.0 P1Sel.1 P1IE.1 P1IFG.1 P1IES.1 P1Sel.2 P1DIR.2 P1DIR.2 P1OUT.2 VSS Out0 signal† Out1 signal† CCI1A† CCI2A† P1IE.2 P1IFG.2 P1IES.2 P1Sel.3 P1DIR.3 P1DIR.3 P1OUT.3 P1IN.3 P1IE.3 P1IFG.3 † Signal from or to Timer_A NOTES: 1. Optional selection of pullup or pulldown resistors with ROM (masked) versions 2. Fuses for optional pullup and pulldown resistors can only be programmed at the factory (ROM versions only). P1IES.3 Out2 signal† POST OFFICE BOX 655303 P1IN.1 P1IN.2 • DALLAS, TEXAS 75265 25 SLAS241H − SEPTEMBER 1999 − REVISED SEPTEMBER 2004 APPLICATION INFORMATION Port P1, P1.4 to P1.7, input/output with Schmitt-trigger and in-system access features VCC P1SEL.x 0 P1DIR.x See Note 1 1 Direction Control From Module See Note 2 0 P1OUT.x Pad Logic P1.4−P1.7 1 Module X OUT See Note 2 See Note 1 GND TST Bus Keeper P1IN.x EN Module X IN D TEST TST P1IRQ.x P1IE.x P1IFG.x Q Interrupt Edge Select EN Set 60 kΩ Typical Fuse GND Interrupt Flag Control By JTAG P1IES.x P1SEL.x Fuse Blow TSTControl P1.x TDO Controlled By JTAG P1.7/TDI/TDO Controlled by JTAG TDI TST P1.x P1.6/TDI/TCLK NOTE: The test pin should be protected from potential EMI and ESD voltage spikes. This may require a smaller external pulldown resistor in some applications. TST P1.x TMS P1.5/TMS x = Bit identifier, 4 to 7 for port P1 During programming activity and during blowing of the fuse, the pin TDO/TDI is used to apply the test input for JTAG circuitry. PnSel.x PnDIR.x Direction control from module PnOUT.x P1Sel.4 P1DIR.4 P1DIR.4 P1Sel.5 P1DIR.5 P1DIR.5 P1Sel.6 P1DIR.6 P1DIR.6 P1Sel.7 P1DIR.7 P1DIR.7 TST P1.x TCK P1.4/TCK Module X OUT PnIN.x Module X IN PnIE.x PnIFG.x PnIES.x P1OUT.4 SMCLK P1IN.4 unused P1IE.4 P1IFG.4 P1IES.4 P1OUT.5 P1IN.5 unused P1IE.5 P1IFG.5 P1IES.5 P1OUT.6 Out0 signal† Out1 signal† P1IN.6 unused P1IE.6 P1IFG.6 P1IES.6 P1OUT.7 Out2 signal† P1IN.7 unused P1IE.7 P1IFG.7 P1IES.7 † Signal from or to Timer_A NOTES: 1. Optional selection of pullup or pulldown resistors with ROM (masked) versions 2. Fuses for optional pullup and pulldown resistors can only be programmed at the factory (ROM versions only). 26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLAS241H − SEPTEMBER 1999 − REVISED SEPTEMBER 2004 APPLICATION INFORMATION Port P2, P2.0 to P2.2, input/output with Schmitt-trigger P2SEL.x VCC 0 P2DIR.x 0: Input 1 Direction Control From Module See Note 2 Pad Logic 0 P2OUT.x See Note 1 1: Output P2.0 − P2.2 1 Module X OUT See Note 2 See Note 1 GND Bus Keeper P2IN.x EN D Module X IN CAPD.X P2IRQ.x P2IE.x P2IFG.x Q EN Set Interrupt Flag NOTE: x = Bit Identifier, 0 to 2 for port P2 Interrupt Edge Select P2IES.x P2SEL.x PnSel.x PnDIR.x Direction control from module PnOUT.x Module X OUT PnIN.x Module X IN PnIE.x PnIFG.x PnIES.x P2Sel.0 P2DIR.0 P2DIR.0 P2OUT.0 ACLK P2IN.0 P2IFG.0 P1IES.0 P2DIR.1 P2DIR.1 P2OUT.1 P2IN.1 P2IE.1 P2IFG.1 P1IES.1 P2Sel.2 P2DIR.2 P2DIR.2 P2OUT.2 VSS CAOUT unused INCLK† CCI0B† P2IE.0 P2Sel.1 P2IE.2 P2IFG.2 P1IES.2 P2IN.2 † Signal from or to Timer_A NOTES: 1. Optional selection of pullup or pulldown resistors with ROM (masked) versions 2. Fuses for optional pullup and pulldown resistors can only be programmed at the factory (ROM versions only). POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 27 SLAS241H − SEPTEMBER 1999 − REVISED SEPTEMBER 2004 APPLICATION INFORMATION Port P2, P2.3 to P2.4, input/output with Schmitt-trigger P2SEL.3 P2DIR.3 VCC 0 Direction Control From Module P2OUT.3 0: Input 1 1: Output 0 Pad Logic See Note 1 See Note 2 P2.3 1 Module X OUT See Note 2 See Note 1 P2IN.3 GND Bus Keeper EN D Module X IN P2IE.3 P2IRQ.3 P2IFG.3 Interrupt Edge Select EN Q Set Interrupt Flag CAPD.3 Comparator_A CAREF P2CA CAEX P2IES.3 P2SEL.3 CAF + _ CCI1B 0V Interrupt Flag P2IFG.4 P2IRQ.4 Q P2IES.4 P2SEL.4 Set EN P2IE.4 CAREF Reference Block Interrupt Edge Select CAPD.4 D Module X IN EN Bus Keeper P2IN.4 VCC See Note 1 See Note 2 Module X OUT P2OUT.4 Direction Control From Module P2DIR.4 P2SEL.4 1 0 Pad Logic See Note 2 1 1: Output See Note 1 P2.4 0: Input 0 GND PnSel.x PnDIR.x Direction control from module PnOUT.x Module X OUT PnIN.x Module X IN PnIE.x PnIFG.x PnIES.x P2Sel.3 P2DIR.3 P2DIR.3 P2OUT.3 P2IN.3 unused P2IE.3 P2IFG.3 P1IES.3 P2Sel.4 P2DIR.4 P2DIR.4 P2OUT.4 Out1 signal† Out2 signal† P2IN.4 unused P2IE.4 P2IFG.4 P1IES.4 † Signal from Timer_A NOTES: 1. Optional selection of pullup or pulldown resistors with ROM (masked) versions 2. Fuses for optional pullup and pulldown resistors can only be programmed at the factory (ROM versions only). 28 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLAS241H − SEPTEMBER 1999 − REVISED SEPTEMBER 2004 APPLICATION INFORMATION Port P2, P2.5, input/output with Schmitt-trigger and ROSC function for the Basic Clock module VCC P2SEL.5 0: Input 1: Output 0 P2DIR.5 Pad Logic See Note 1 1 Direction Control From Module See Note 2 0 P2OUT.5 P2.5 1 Module X OUT See Note 2 See Note 1 GND Bus Keeper P2IN.5 EN Module X IN P2IRQ.5 D P2IE.5 P2IFG.5 Q EN Set Interrupt Flag Internal to Basic Clock Module 0 VCC Interrupt Edge Select P2IES.5 1 DC Generator DCOR P2SEL.5 CAPD.5 NOTE: DCOR: Control bit from Basic Clock Module if it is set, P2.5 Is disconnected from P2.5 pad PnSel.x PnDIR.x Direction control from module PnOUT.x Module X OUT PnIFG.x PnIES.x P2Sel.5 P2DIR.5 P2DIR.5 P2OUT.5 VSS P2IN.5 unused P2IE.5 P2IFG.5 NOTES: 1. Optional selection of pullup or pulldown resistors with ROM (masked) versions 2. Fuses for optional pullup and pulldown resistors can only be programmed at the factory (ROM versions only). P2IES.5 POST OFFICE BOX 655303 PnIN.x Module X IN • DALLAS, TEXAS 75265 PnIE.x 29 SLAS241H − SEPTEMBER 1999 − REVISED SEPTEMBER 2004 APPLICATION INFORMATION Port P2, unbonded bits P2.6 and P2.7 P2SEL.x 0: Input 1: Output 0 P2DIR.x 1 Direction Control From Module 0 P2OUT.x 1 Module X OUT P2IN.x Node Is Reset With PUC EN Bus Keeper Module X IN P2IRQ.x D P2IE.x P2IFG.x Q PUC Interrupt Edge Select EN Set Interrupt Flag P2IES.x P2SEL.x NOTE: x = Bit/identifier, 6 to 7 for port P2 without external pins P2Sel.x P2DIR.x Direction control from module P2OUT.x Module X OUT P2IN.x Module X IN P2IE.x P2IFG.x P2IES.x P2Sel.6 P2DIR.6 P2DIR.6 P2OUT.6 P2IN.6 unused P2IE.6 P2IFG.6 P2IES.6 P2Sel.7 P2DIR.7 P2DIR.7 P2OUT.7 VSS VSS P2IN.7 unused P2IE.7 P2IFG.7 P2IES.7 NOTE 1: Unbonded bits 6 and 7 of port P2 can be used as software interrupt flags. The interrupt flags can only be influenced by software. They work then as a software interrupt. 30 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLAS241H − SEPTEMBER 1999 − REVISED SEPTEMBER 2004 JTAG fuse check mode MSP430 devices that have the fuse on the TEST terminal have a fuse check mode that tests the continuity of the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check current, ITF , of 1 mA at 3 V, 2.5 mA at 5 V can flow from the TEST pin to ground if the fuse is not burned. Care must be taken to avoid accidentally activating the fuse check mode and increasing overall system power consumption. When the TEST pin is taken back low after a test or programming session, the fuse check mode and sense currents are terminated. Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if TMS is being held low during power up. The second positive edge on the TMS pin deactivates the fuse check mode. After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR the fuse check mode has the potential to be activated. The fuse check current will only flow when the fuse check mode is active and the TMS pin is in a low state (see Figure 13). Therefore, the additional current flow can be prevented by holding the TMS pin high (default condition). Time TMS Goes Low After POR TMS ITEST ITF Figure 13. Fuse Check Mode Current, MSP430F11x1A and MSP430C11x1 NOTE: The CODE and RAM data protection is ensured if the JTAG fuse is blown and the 256-bit bootloader access key is used. Also, see the bootstrap loader section for more information. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 31 PACKAGE OPTION ADDENDUM www.ti.com 18-Jul-2006 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty MSP430C1101 ACTIVE MSP430F1101AIDGV ACTIVE TVSOP DGV 20 MSP430F1101AIDGVR ACTIVE TVSOP DGV 20 MSP430F1101AIDW ACTIVE SOIC DW 20 MSP430F1101AIDWR ACTIVE SOIC DW 20 MSP430F1101AIPW ACTIVE TSSOP PW 20 MSP430F1101AIPWR ACTIVE TSSOP PW MSP430F1101AIRGER ACTIVE QFN MSP430F1101AIRGET ACTIVE MSP430F1111AIDGV Lead/Ball Finish MSL Peak Temp (3) TBD Call TI Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM RGE 24 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR QFN RGE 24 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ACTIVE TVSOP DGV 20 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MSP430F1111AIDGVR ACTIVE TVSOP DGV 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MSP430F1111AIDW ACTIVE SOIC DW 20 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430F1111AIDWR ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430F1111AIPW ACTIVE TSSOP PW 20 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430F1111AIPWR ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430F1111AIRGER ACTIVE QFN RGE 24 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MSP430F1111AIRGET ACTIVE QFN RGE 24 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MSP430F1121AIDGV ACTIVE TVSOP DGV 20 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MSP430F1121AIDGVR ACTIVE TVSOP DGV 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MSP430F1121AIDW ACTIVE SOIC DW 20 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430F1121AIDWR ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430F1121AIPW ACTIVE TSSOP PW 20 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430F1121AIPWR ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430F1121AIRGER ACTIVE QFN RGE 24 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MSP430F1121AIRGET ACTIVE QFN RGE 24 250 CU NIPDAU Level-2-260C-1 YEAR 90 25 70 25 70 25 70 Addendum-Page 1 Green (RoHS & no Sb/Br) Call TI PACKAGE OPTION ADDENDUM www.ti.com 18-Jul-2006 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 2 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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