MSP430x23x, MSP430x24x(1), MSP430x2410 MIXED SIGNAL MICROCONTROLLER SLAS547A -- JUNE 2007 -- REVISED NOVEMBER 2007 D Low Supply-Voltage Range, 1.8 V to 3.6 V D Ultra-Low Power Consumption: D D D D D D D -- Active Mode: 270 μA at 1 MHz, 2.2 V -- Standby Mode (VLO): 0.3 μA -- Off Mode (RAM Retention): 0.1 μA Ultra-Fast Wake-Up From Standby Mode in Less Than 1 μs 16-Bit RISC Architecture, 62.5-ns Instruction Cycle Time Basic Clock Module Configurations: -- Internal Frequencies up to 16 MHz -- Internal Very Low Power LF Oscillator -- 32-kHz Crystal -- Internal Frequencies up to 16 MHz With Four Calibrated Frequencies to ±1% -- Resonator -- External Digital Clock Source -- External Resistor 12-Bit Analog-to-Digital (A/D) Converter With Internal Reference, Sample-and-Hold, and Autoscan Feature 16-Bit Timer_A With Three Capture/Compare Registers 16-Bit Timer_B With Seven Capture/Compare-With-Shadow Registers Four Universal Serial Communication Interfaces (USCI) -- USCI_A0 and USCI_A1 -- Enhanced UART Supporting Auto-Baudrate Detection -- IrDA Encoder and Decoder -- Synchronous SPI -- USCI_B0 and USCI_B1 -- I2Ct -- Synchronous SPI D On-Chip Comparator D Supply Voltage Supervisor/Monitor With Programmable Level Detection D Brownout Detector D Bootstrap Loader D Serial Onboard Programming, D D D † No External Programming Voltage Needed, Programmable Code Protection by Security Fuse Family Members Include: -- MSP430F233 8KB+256B Flash Memory, 1KB RAM -- MSP430F235 16KB+256B Flash Memory, 2KB RAM -- MSP430F247, MSP430F2471† 32KB+256B Flash Memory, 4KB RAM -- MSP430F248, MSP430F2481† 48KB+256B Flash Memory, 4KB RAM -- MSP430F249, MSP430F2491† 60KB+256B Flash Memory, 2KB RAM -- MSP430F2410 56KB+256B Flash Memory, 4KB RAM Available in 64-Pin QFP and 64-Pin QFN Packages (See Available Options) For Complete Module Descriptions, See MSP430x2xx Family User’s Guide, Literature Number SLAU144 The MSP430F24x1 devices are identical to the MSP430F24x devices, with the exception that the ADC12 module is not implemented. description The Texas Instruments MSP430 family of ultra-low power microcontrollers consists of several devices featuring different sets of peripherals targeted for various applications. The architecture, combined with five low-power modes, is optimized to achieve extended battery life in portable measurement applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency. The calibrated digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 1 μs. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. I2C is a registered trademark of NXP Semiconductors. Copyright © 2007, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 MSP430x23x, MSP430x24x(1), MSP430x2410 MIXED SIGNAL MICROCONTROLLER SLAS547A -- JUNE 2007 -- REVISED NOVEMBER 2007 description (continued) The MSP430F23x/24x(1)/2410 series are microcontroller configurations with two built-in 16-bit timers, a fast 12-bit A/D converter (not MSP430F24x1), a comparator, four (two in MSP430F23x) universal serial communication interface (USCI) modules, and up to 48 I/O pins. The MSP430F24x1 devices are identical to the MSP430F24x devices, with the exception that the ADC12 module is not implemented. The MSP430F23x devices are identical to the MSP430F24x devices, with the exception that a reduced Timer B, one USCI module, and less RAM is integrated. Typical applications include sensor systems, industrial control applications, hand-held meters, etc. AVAILABLE OPTIONS PACKAGED DEVICES TA --40°C to 105°C 2 PLASTIC 64-PIN QFP (PM) PLASTIC 64-PIN QFN (RGC) MSP430F233TPM MSP430F235TPM MSP430F247TPM MSP430F2471TPM MSP430F248TPM MSP430F2481TPM MSP430F249TPM MSP430F2491TPM MSP430F2410TPM MSP430F233TRGC MSP430F235TRGC MSP430F247TRGC MSP430F2471TRGC MSP430F248TRGC MSP430F2481TRGC MSP430F249TRGC MSP430F2491TRGC MSP430F2410TRGC POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MSP430x23x, MSP430x24x(1), MSP430x2410 MIXED SIGNAL MICROCONTROLLER SLAS547A -- JUNE 2007 -- REVISED NOVEMBER 2007 P5.7/TBOUTH/SVSOUT P5.6/ACLK P5.5/SMCLK AVCC DVSS AVSS P6.2/A2 P6.1/A1 P6.0/A0 RST/NMI TCK TMS TDI/TCLK TDO/TDI XT2IN XT2OUT pin designation -- MSP430F23x 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 DVCC P6.3/A3 1 2 48 47 P5.4/MCLK P5.3 P6.4/A4 P6.5/A5 3 4 46 45 P5.2 P5.1 P6.6/A6 P6.7/A7/SVSIN 5 6 44 43 P5.0 P4.7/TBCLK VREF+ XIN 7 8 42 41 P4.6 P4.5 XOUT 9 MSP430F23x 40 P4.4 VeREF+ VREF-/VeREF- 10 11 39 38 P4.3 P4.2/TB2 P1.0/TACLK/CAOUT P1.1/TA0 12 13 37 36 P4.1/TB1 P4.0/TB0 P1.2/TA1 P1.3/TA2 14 15 35 34 P3.7 P3.6 P1.4/SMCLK 16 33 P3.5/UCA0RXD/UCA0SOMI P3.0/UCB0STE/UCA0CLK P3.1/UCB0SIMO/UCB0SDA P3.2/UCB0SOMI/UCB0SCL P3.3/UCB0CLK/UCA0STE P3.4/UCA0TXD/UCA0SIMO P1.5/TA0 P1.6/TA1 P1.7/TA2 P2.0/ACLK/CA2 P2.1/TAINCLK/CA3 P2.2/CAOUT/TA0/CA4 P2.3/CA0/TA1 P2.4/CA1/TA2 P2.5/ROSC/CA5 P2.6/ADC12CLK/CA6 P2.7/TA0/CA7 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 MSP430x23x, MSP430x24x(1), MSP430x2410 MIXED SIGNAL MICROCONTROLLER SLAS547A -- JUNE 2007 -- REVISED NOVEMBER 2007 AVCC DVSS AVSS P6.2/A2 P6.1/A1 P6.0/A0 RST/NMI TCK TMS TDI/TCLK TDO/TDI XT2IN XT2OUT P5.7/TBOUTH/SVSOUT P5.6/ACLK P5.5/SMCLK pin designation -- MSP430F24x, MSP430F2410 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 DVCC 1 48 P5.4/MCLK P6.3/A3 P6.4/A4 2 3 47 46 P5.3/UCB1CLK/UCA1STE P5.2/UCB1SOMI/UCB1SCL P6.5/A5 P6.6/A6 4 5 45 44 P5.1/UCB1SIMO/UCB1SDA P5.0/UCB1STE/UCA1CLK P6.7/A7/SVSIN VREF+ 6 7 43 42 P4.7/TBCLK P4.6/TB6 XIN 8 41 P4.5/TB5 40 39 P4.4/TB4 P4.3/TB3 MSP430F2410, MSP430F24x XOUT VeREF+ 9 10 VREF-/VeREFP1.0/TACLK/CAOUT 11 12 38 37 P4.2/TB2 P4.1/TB1 P1.1/TA0 P1.2/TA1 13 14 36 35 P4.0/TB0 P3.7/UCA1RXD/UCA1SOMI P1.3/TA2 P1.4/SMCLK 15 16 34 33 P3.6/UCA1TXD/UCA1SIMO P3.5/UCA0RXD/UCA0SOMI P1.5/TA0 P1.6/TA1 P1.7/TA2 P2.0/ACLK/CA2 P2.1/TAINCLK/CA3 P2.2/CAOUT/TA0/CA4 P2.3/CA0/TA1 P2.4/CA1/TA2 P2.5/ROSC/CA5 P2.6/ADC12CLK/CA6 P2.7/TA0/CA7 P3.0/UCB0STE/UCA0CLK P3.1/UCB0SIMO/UCB0SDA P3.2/UCB0SOMI/UCB0SCL P3.3/UCB0CLK/UCA0STE P3.4/UCA0TXD/UCA0SIMO 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MSP430x23x, MSP430x24x(1), MSP430x2410 MIXED SIGNAL MICROCONTROLLER SLAS547A -- JUNE 2007 -- REVISED NOVEMBER 2007 AVCC DVSS AVSS P6.2 P6.1 P6.0 RST/NMI TCK TMS TDI/TCLK TDO/TDI XT2IN XT2OUT P5.7/TBOUTH/SVSOUT P5.6/ACLK P5.5/SMCLK pin designation -- MSP430F24x1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 DVCC P6.3 1 2 48 47 P5.4/MCLK P5.3/UCB1CLK/UCA1STE P6.4 P6.5 P6.6 3 4 5 46 45 44 P5.2/UCB1SOMI/UCB1SCL P5.1/UCB1SIMO/UCB1SDA P5.0/UCB1STE/UCA1CLK P6.7/SVSIN Reserved XIN 6 7 8 43 42 41 P4.7/TBCLK P4.6/TB6 P4.5/TB5 40 39 38 P4.4/TB4 P4.3/TB3 P4.2/TB2 MSP430F24x1 DVSS 9 10 11 P1.0/TACLK/CAOUT P1.1/TA0 P1.2/TA1 12 13 14 37 36 35 P4.1/TB1 P4.0/TB0 P3.7/UCA1RXD/UCA1SOMI P1.3/TA2 P1.4/SMCLK 15 16 34 33 P3.6/UCA1TXD/UCA1SIMO P3.5/UCA0RXD/UCA0SOMI 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 P1.5/TA0 P1.6/TA1 P1.7/TA2 P2.0/ACLK/CA2 P2.1/TAINCLK/CA3 P2.2/CAOUT/TA0/CA4 P2.3/CA0/TA1 P2.4/CA1/TA2 P2.5/ROSC/CA5 P2.6/ADC12CLK/CA6 P2.7/TA0/CA7 P3.0/UCB0STE/UCA0CLK P3.1/UCB0SIMO/UCB0SDA P3.2/UCB0SOMI/UCB0SCL P3.3/UCB0CLK/UCA0STE P3.4/UCA0TXD/UCA0SIMO XOUT DVSS POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 MSP430x23x, MSP430x24x(1), MSP430x2410 MIXED SIGNAL MICROCONTROLLER SLAS547A -- JUNE 2007 -- REVISED NOVEMBER 2007 functional block diagram -- MSP430F23x XIN/ XOUT/ XT2IN XT2OUT 2 2 DVCC Flash RAM 16kB 8kB 2kB 1kB MCLK AVSS P1.x/P2.x Ports P1/P2 ADC12 12-Bit 2x8 I/O Interrupt capability 8 Channels Ports P3/P4 P5/P6 4x8 I/O MDB Hardware Multiplier BOR SVS/SVM MPY, MPYS, MAC, MACS Timer_B3 Watchdog WDT+ 15/16-Bit Timer_A3 3 CC Registers 3 CC Registers, Shadow Reg RST/NMI 6 P3.x/P4.x P5.x/P6.x 4x8 MAB Emulation JTAG Interface AVCC 2x8 ACLK Oscillators Basic Clock SMCLK System+ 16MHz CPU incl. 16 Registers DVSS POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Comp_A+ USCI A0 UART/ LIN, IrDA, SPI USCI B0 SPI, I2C MSP430x23x, MSP430x24x(1), MSP430x2410 MIXED SIGNAL MICROCONTROLLER SLAS547A -- JUNE 2007 -- REVISED NOVEMBER 2007 functional block diagram -- MSP430F24x, MSP430F2410 XIN/ XOUT/ XT2IN XT2OUT 2 2 DVCC Flash RAM 60kB 56kB 48kB 32kB 2kB 4kB 4kB 4kB MCLK AVSS P1.x/P2.x Ports P1/P2 ADC12 12-Bit 2x8 I/O Interrupt capability 8 Channels P3.x/P4.x P5.x/P6.x 4x8 Ports P3/P4 P5/P6 4x8 I/O MAB MDB Emulation JTAG Interface AVCC 2x8 ACLK Oscillators Basic Clock SMCLK System+ 16MHz CPU incl. 16 Registers DVSS Hardware Multiplier BOR SVS/SVM MPY, MPYS, MAC, MACS Timer_B7 Watchdog WDT+ 15/16-Bit Timer_A3 3 CC Registers 7 CC Registers, Shadow Reg Comp_A+ USCI A0 UART/ LIN, IrDA, SPI USCI A1 UART/ LIN, IrDA, SPI USCI B0 SPI, I2C USCI B1 SPI, I2C RST/NMI POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 MSP430x23x, MSP430x24x(1), MSP430x2410 MIXED SIGNAL MICROCONTROLLER SLAS547A -- JUNE 2007 -- REVISED NOVEMBER 2007 functional block diagram -- MSP430F24x1 XIN/ XOUT/ XT2IN XT2OUT 2 2 DVCC Flash RAM 60kB 48kB 32kB 2kB 4kB 4kB MCLK AVSS P1.x/P2.x Ports P1/P2 2x8 I/O Interrupt capability Ports P3/P4 P5/P6 4x8 I/O MDB Hardware Multiplier BOR SVS/SVM MPY, MPYS, MAC, MACS Timer_B7 Watchdog WDT+ 15/16-Bit Timer_A3 3 CC Registers 7 CC Registers, Shadow Reg RST/NMI 8 P3.x/P4.x P5.x/P6.x 4x8 MAB Emulation JTAG Interface AVCC 2x8 ACLK Oscillators Basic Clock SMCLK System+ 16MHz CPU incl. 16 Registers DVSS POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Comp_A+ USCI A0 UART/ LIN, IrDA, SPI USCI A1 UART/ LIN, IrDA, SPI USCI B0 SPI, I2C USCI B1 SPI, I2C MSP430x23x, MSP430x24x(1), MSP430x2410 MIXED SIGNAL MICROCONTROLLER SLAS547A -- JUNE 2007 -- REVISED NOVEMBER 2007 Terminal Functions -- MSP430F23x TERMINAL NAME NO. I/O DESCRIPTION AVCC 64 Analog supply voltage, positive. Supplies only the analog portion of ADC12. AVSS 62 Analog supply voltage, negative. Supplies only the analog portion of ADC12. DVCC 1 Digital supply voltage, positive. Supplies all digital parts. DVSS 63 Digital supply voltage, negative. Supplies all digital parts. P1.0/TACLK/ CAOUT 12 I/O General-purpose digital I/O / Timer_A, clock signal TACLK input/Comparator_A output P1.1/TA0 13 I/O General-purpose digital I/O / Timer_A, capture: CCI0A input, compare: Out0 output/BSL transmit P1.2/TA1 14 I/O General-purpose digital I/O / Timer_A, capture: CCI1A input, compare: Out1 output P1.3/TA2 15 I/O General-purpose digital I/O / Timer_A, capture: CCI2A input, compare: Out2 output P1.4/SMCLK 16 I/O General-purpose digital I/O / SMCLK signal output P1.5/TA0 17 I/O General-purpose digital I/O / Timer_A, compare: Out0 output P1.6/TA1 18 I/O General-purpose digital I/O / Timer_A, compare: Out1 output P1.7/TA2 19 I/O General-purpose digital I/O / Timer_A, compare: Out2 output P2.0/ACLK/CA2 20 I/O General-purpose digital I/O / ACLK output/Comparator_A input P2.1/TAINCLK/ CA3 21 I/O General-purpose digital I/O / Timer_A, clock signal at INCLK P2.2/CAOUT/TA0 /CA4 22 I/O General-purpose digital I/O receive/Comparator_A input P2.3/CA0/TA1 23 I/O General-purpose digital I/O / Timer_A, compare: Out1 output/Comparator_A input P2.4/CA1/TA2 24 I/O General-purpose digital I/O / Timer_A, compare: Out2 output/Comparator_A input P2.5/Rosc/CA5 25 I/O General-purpose digital I/O / input for external resistor defining the DCO nominal frequency/Comparator_A input P2.6/ ADC12CLK†/CA6 26 I/O General-purpose digital I/O / conversion clock – 12-bit ADC/Comparator_A input P2.7/TA0/CA7 27 I/O General-purpose digital I/O / Timer_A, compare: Out0 output/Comparator_A input P3.0/UCB0STE/ UCA0CLK 28 I/O General-purpose digital I/O / USCI B0 slave transmit enable/USCI A0 clock input/output P3.1/UCB0SIMO/ UCB0SDA 29 I/O General-purpose digital I/O / USCI B0 slave in/master out in SPI mode, SDA I2C data in I2C mode P3.2/UCB0SOMI/ UCB0SCL 30 I/O General-purpose digital I/O / USCI B0 slave out/master in in SPI mode, SCL I2C clock in I2C mode P3.3/UCB0CLK/ UCA0STE 31 I/O General-purpose digital I/O / USCI B0 clock input/output, USCI A0 slave transmit enable P3.4/UCA0TXD/ UCA0SIMO 32 I/O General-purpose digital I/O / USCIA transmit data output in UART mode, slave data in/master out in SPI mode P3.5/UCA0RXD/ UCA0SOMI 33 I/O General-purpose digital I/O / USCI A0 receive data input in UART mode, slave data out/master in in SPI mode P3.6/UCA1TXD/ UCA1SIMO 34 I/O General-purpose digital I/O / USCI A1 transmit data output in UART mode, slave data in/master out in SPI mode P3.7/UCA1RXD/ UCA1SOMI 35 I/O General-purpose digital I/O / USCIA1 receive data input in UART mode, slave data out/master in in SPI mode P4.0/TB0 36 I/O General-purpose digital I/O / Timer_B, capture: CCI0A/B input, compare: Out0 output P4.1/TB1 37 I/O General-purpose digital I/O / Timer_B, capture: CCI1A/B input, compare: Out1 output / POST OFFICE BOX 655303 Timer_A, capture: • DALLAS, TEXAS 75265 CCI0B input/Comparator_A output/BSL 9 MSP430x23x, MSP430x24x(1), MSP430x2410 MIXED SIGNAL MICROCONTROLLER SLAS547A -- JUNE 2007 -- REVISED NOVEMBER 2007 Terminal Functions -- MSP430F23x (Continued) TERMINAL NAME NO. I/O DESCRIPTION P4.2/TB2 38 I/O General-purpose digital I/O / Timer_B, capture: CCI2A/B input, compare: Out2 output P4.3 39 I/O General-purpose digital I/O P4.4 40 I/O General-purpose digital I/O P4.5 41 I/O General-purpose digital I/O P4.6 42 I/O General-purpose digital I/O P4.7/TBCLK 43 I/O General-purpose digital I/O / Timer_B, clock signal TBCLK input P5.0 44 I/O General-purpose digital I/O P5.1 45 I/O General-purpose digital I/O P5.2 46 I/O General-purpose digital I/O P5.3 47 I/O General-purpose digital I/O P5.4/MCLK 48 I/O General-purpose digital I/O / main system clock MCLK output P5.5/SMCLK 49 I/O General-purpose digital I/O / submain system clock SMCLK output P5.6/ACLK 50 I/O General-purpose digital I/O / auxiliary clock ACLK output P5.7/TBOUTH/ SVSOUT 51 I/O General-purpose digital I/O / switch all PWM digital output ports to high impedance -- Timer_B TB0 to TB6/SVS comparator output P6.0/A0 59 I/O General-purpose digital I/O / analog input A0 – 12-bit ADC P6.1/A1 60 I/O General-purpose digital I/O / analog input A1 – 12-bit ADC P6.2/A2 61 I/O General-purpose digital I/O / analog input A2 – 12-bit ADC P6.3/A3 2 I/O General-purpose digital I/O / analog input A3 – 12-bit ADC P6.4/A4 3 I/O General-purpose digital I/O / analog input A4 – 12-bit ADC P6.5/A5 4 I/O General-purpose digital I/O / analog input A5 – 12-bit ADC P6.6/A6 5 I/O General-purpose digital I/O / analog input A6 – 12-bit ADC P6.7/A7/SVSIN 6 I/O General-purpose digital I/O / analog input A7 – 12-bit ADC/SVS input XT2OUT 52 O Output terminal of crystal oscillator XT2 XT2IN 53 I Input port for crystal oscillator XT2 RST/NMI 58 I Reset input, nonmaskable interrupt input port, or bootstrap loader start (in Flash devices). TCK 57 I Test clock (JTAG). TCK is the clock input port for device programming test and bootstrap loader start TDI/TCLK 55 I Test data input or test clock input. The device protection fuse is connected to TDI/TCLK. TDO/TDI 54 I/O TMS 56 I Test mode select. TMS is used as an input port for device programming and test. VeREF+ 10 I Input for an external reference voltage VREF+ 7 O Output of positive terminal of the reference voltage in the ADC12 VREF-- /VeREF-- 11 I Negative terminal for the reference voltage for both sources, the internal reference voltage, or an external applied reference voltage XIN 8 I Input port for crystal oscillator XT1. Standard or watch crystals can be connected. XOUT 9 O Output port for crystal oscillator XT1. Standard or watch crystals can be connected. NA NA QFN Pad 10 Test data output port. TDO/TDI data output or programming data input terminal QFN package pad connection to DVSS recommended POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MSP430x23x, MSP430x24x(1), MSP430x2410 MIXED SIGNAL MICROCONTROLLER SLAS547A -- JUNE 2007 -- REVISED NOVEMBER 2007 Terminal Functions -- MSP430F24x, MSP430F2410 TERMINAL NAME NO. I/O DESCRIPTION AVCC 64 Analog supply voltage, positive terminal. Supplies only the analog portion of ADC12. AVSS 62 Analog supply voltage, negative terminal. Supplies only the analog portion of ADC12. DVCC 1 Digital supply voltage, positive terminal. Supplies all digital parts. DVSS 63 Digital supply voltage, negative terminal. Supplies all digital parts. P1.0/TACLK/ CAOUT 12 I/O General-purpose digital I/O / Timer_A, clock signal TACLK input/Comparator_A output P1.1/TA0 13 I/O General-purpose digital I/O / Timer_A, capture: CCI0A input, compare: Out0 output/BSL transmit P1.2/TA1 14 I/O General-purpose digital I/O / Timer_A, capture: CCI1A input, compare: Out1 output P1.3/TA2 15 I/O General-purpose digital I/O / Timer_A, capture: CCI2A input, compare: Out2 output P1.4/SMCLK 16 I/O General-purpose digital I/O / SMCLK signal output P1.5/TA0 17 I/O General-purpose digital I/O / Timer_A, compare: Out0 output P1.6/TA1 18 I/O General-purpose digital I/O / Timer_A, compare: Out1 output P1.7/TA2 19 I/O General-purpose digital I/O / Timer_A, compare: Out2 output P2.0/ACLK/CA2 20 I/O General-purpose digital I/O / ACLK output/Comparator_A input P2.1/TAINCLK/ CA3 21 I/O General-purpose digital I/O / Timer_A, clock signal at INCLK P2.2/CAOUT/TA0 /CA4 22 I/O General-purpose digital I/O / Timer_A, capture: CCI0B input / Comparator_A output/BSL receive/Comparator_A input P2.3/CA0/TA1 23 I/O General-purpose digital I/O / Timer_A, compare: Out1 output / Comparator_A input P2.4/CA1/TA2 24 I/O General-purpose digital I/O / Timer_A, compare: Out2 output / Comparator_A input P2.5/Rosc/CA5 25 I/O General-purpose digital I/O / Input for external resistor defining the DCO nominal frequency / Comparator_A input P2.6/ ADC12CLK†/CA6 26 I/O General-purpose digital I/O / Conversion clock – 12-bit ADC / Comparator_A input P2.7/TA0/CA7 27 I/O General-purpose digital I/O / Timer_A, compare: Out0 output / Comparator_A input P3.0/UCB0STE/ UCA0CLK 28 I/O General-purpose digital I/O / USCI B0 slave transmit enable / USCI A0 clock input/output P3.1/UCB0SIMO/ UCB0SDA 29 I/O General-purpose digital I/O / USCI B0 slave in/master out in SPI mode, SDA I2C data in I2C mode P3.2/UCB0SOMI/ UCB0SCL 30 I/O General-purpose digital I/O / USCI B0 slave out/master in in SPI mode, SCL I2C clock in I2C mode P3.3/UCB0CLK/ UCA0STE 31 I/O General-purpose digital I/O / USCI B0 clock input/output, USCI A0 slave transmit enable P3.4/UCA0TXD/ UCA0SIMO 32 I/O General-purpose digital I/O / USCIA transmit data output in UART mode, slave data in/master out in SPI mode P3.5/UCA0RXD/ UCA0SOMI 33 I/O General-purpose digital I/O / USCI A0 receive data input in UART mode, slave data out/master in in SPI mode P3.6/UCA1TXD/ UCA1SIMO 34 I/O General-purpose digital I/O / USCI A1 transmit data output in UART mode, slave data in/master out in SPI mode P3.7/UCA1RXD/ UCA1SOMI 35 I/O General-purpose digital I/O / USCIA1 receive data input in UART mode, slave data out/master in in SPI mode P4.0/TB0 36 I/O General-purpose digital I/O / Timer_B, capture: CCI0A/B input, compare: Out0 output P4.1/TB1 37 I/O General-purpose digital I/O / Timer_B, capture: CCI1A/B input, compare: Out1 output POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 MSP430x23x, MSP430x24x(1), MSP430x2410 MIXED SIGNAL MICROCONTROLLER SLAS547A -- JUNE 2007 -- REVISED NOVEMBER 2007 Terminal Functions -- MSP430F24x, MSP430F2410 (Continued) TERMINAL NAME NO. I/O DESCRIPTION P4.2/TB2 38 I/O General-purpose digital I/O / Timer_B, capture: CCI2A/B input, compare: Out2 output P4.3/TB3 39 I/O General-purpose digital I/O / Timer_B, capture: CCI3A/B input, compare: Out3 output P4.4/TB4 40 I/O General-purpose digital I/O / Timer_B, capture: CCI4A/B input, compare: Out4 output P4.5/TB5 41 I/O General-purpose digital I/O / Timer_B, capture: CCI5A/B input, compare: Out5 output P4.6/TB6 42 I/O General-purpose digital I/O / Timer_B, capture: CCI6A input, compare: Out6 output P4.7/TBCLK 43 I/O General-purpose digital I/O / Timer_B, clock signal TBCLK input P5.0/UCB1STE/ UCA1CLK 44 I/O General-purpose digital I/O / USCI B1 slave transmit enable / USCI A1 clock input/output P5.1/UCB1SIMO/ UCB1SDA 45 I/O General-purpose digital I/O / USCI B1slave in/master out in SPI mode, SDA I2C data in I2C mode P5.2/UCB1SOMI/ UCB1SCL 46 I/O General-purpose digital I/O / USCI B1slave out/master in in SPI mode, SCL I2C clock in I2C mode P5.3/UCB1CLK/ UCA1STE 47 I/O General-purpose digital I/O / USCI B1 clock input/output, USCI A1 slave transmit enable P5.4/MCLK 48 I/O General-purpose digital I/O / main system clock MCLK output P5.5/SMCLK 49 I/O General-purpose digital I/O / submain system clock SMCLK output P5.6/ACLK 50 I/O General-purpose digital I/O / auxiliary clock ACLK output P5.7/TBOUTH/ SVSOUT 51 I/O General-purpose digital I/O / switch all PWM digital output ports to high impedance -- Timer_B TB0 to TB6/SVS comparator output P6.0/A0 59 I/O General-purpose digital I/O / analog input A0 – 12-bit ADC P6.1/A1 60 I/O General-purpose digital I/O / analog input A1 – 12-bit ADC P6.2/A2 61 I/O General-purpose digital I/O / analog input A2 – 12-bit ADC P6.3/A3 2 I/O General-purpose digital I/O / analog input A3 – 12-bit ADC P6.4/A4 3 I/O General-purpose digital I/O / analog input A4 – 12-bit ADC P6.5/A5 4 I/O General-purpose digital I/O / analog input A5 – 12-bit ADC P6.6/A6 5 I/O General-purpose digital I/O / analog input A6 – 12-bit ADC P6.7/A7/SVSIN 6 I/O General-purpose digital I/O / analog input A7 – 12-bit ADC/SVS input XT2OUT 52 O Output of crystal oscillator XT2 XT2IN 53 I Input for crystal oscillator XT2 RST/NMI 58 I Reset input, nonmaskable interrupt input port, or bootstrap loader start (in flash devices). TCK 57 I Test clock (JTAG). TCK is the clock input port for device programming test and bootstrap loader start TDI/TCLK 55 I Test data input or test clock input. The device protection fuse is connected to TDI/TCLK. TDO/TDI 54 I/O TMS 56 I Test mode select. TMS is used as an input port for device programming and test. VeREF+ 10 I Input for an external reference voltage VREF+ 7 O Output of positive of the reference voltage in the ADC12 VREF-- /VeREF-- 11 I Negativefor the reference voltage for both sources, the internal reference voltage, or an external applied reference voltage XIN 8 I Input for crystal oscillator XT1. Standard or watch crystals can be connected. XOUT 9 O Output for crystal oscillator XT1. Standard or watch crystals can be connected. NA NA QFN Pad 12 Test data output. TDO/TDI data output or programming data input terminal QFN package pad connection to DVSS recommended (RTD package only) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MSP430x23x, MSP430x24x(1), MSP430x2410 MIXED SIGNAL MICROCONTROLLER SLAS547A -- JUNE 2007 -- REVISED NOVEMBER 2007 Terminal Functions -- MSP430F24x1 TERMINAL NAME NO. I/O DESCRIPTION AVCC 64 Analog supply voltage, positive. Supplies only the analog portion of ADC12. AVSS 62 Analog supply voltage, negative. Supplies only the analog portion of ADC12. DVCC 1 Digital supply voltage, positive. Supplies all digital parts. DVSS 63 Digital supply voltage, negative. Supplies all digital parts. P1.0/TACLK/ CAOUT 12 I/O General-purpose digital I/O / Timer_A, clock signal TACLK input / Comparator_A output P1.1/TACLK 13 I/O General-purpose digital I/O / Timer_A, capture: CCI0A input, compare: Out0 output / BSL transmit P1.2/TA0 14 I/O General-purpose digital I/O / Timer_A, capture: CCI1A input, compare: Out1 output P1.3/TA1 15 I/O General-purpose digital I/O / Timer_A, capture: CCI2A input, compare: Out2 output P1.4/SMCLK 16 I/O General-purpose digital I/O / SMCLK signal output P1.5/TA0 17 I/O General-purpose digital I/O / Timer_A, compare: Out0 output P1.6/TA1 18 I/O General-purpose digital I/O / Timer_A, compare: Out1 output P1.7/TA2 19 I/O General-purpose digital I/O / Timer_A, compare: Out2 output P2.0/ACLK/CA2 20 I/O General-purpose digital I/O / ACLK output/Comparator_A input P2.1/TAINCLK/ CA3 21 I/O General-purpose digital I/O / Timer_A, clock signal at INCLK P2.2/CAOUT/TA0 /CA4 22 I/O General-purpose digital I/O / Timer_A, capture: CCI0B input / Comparator_A output/BSL receive/Comparator_A input P2.3/CA0/TA1 23 I/O General-purpose digital I/O / Timer_A, compare: Out1 output / Comparator_A input P2.4/CA1/TA2 24 I/O General-purpose digital I/O / Timer_A, compare: Out2 output / Comparator_A input P2.5/Rosc/CA5 25 I/O General-purpose digital I/O / input for external resistor defining the DCO nominal frequency / Comparator_A input P2.6/ ADC12CLK†/CA6 26 I/O General-purpose digital I/O / conversion clock – 12-bit ADC / Comparator_A input P2.7/TA0/CA7 27 I/O General-purpose digital I/O / Timer_A, compare: Out0 output/Comparator_A input P3.0/UCB0STE/ UCA0CLK 28 I/O General-purpose digital I/O / USCI B0 slave transmit enable/USCI A0 clock input/output P3.1/UCB0SIMO/ UCB0SDA 29 I/O General-purpose digital I/O / USCI B0 slave in/master out in SPI mode, SDA I2C data in I2C mode P3.2/UCB0SOMI/ UCB0SCL 30 I/O General-purpose digital I/O / USCI B0 slave out/master in in SPI mode, SCL I2C clock in I2C mode P3.3/UCB0CLK/ UCA0STE 31 I/O General-purpose digital I/O / USCI B0 clock input/output, USCI A0 slave transmit enable P3.4/UCA0TXD/ UCA0SIMO 32 I/O General-purpose digital I/O / USCIA transmit data output in UART mode, slave data in/master out in SPI mode P3.5/UCA0RXD/ UCA0SOMI 33 I/O General-purpose digital I/O / USCI A0 receive data input in UART mode, slave data out/master in in SPI mode P3.6/UCA1TXD/ UCA1SIMO 34 I/O General-purpose digital I/O / USCI A1 transmit data output in UART mode, slave data in/master out in SPI mode P3.7/UCA1RXD/ UCA1SOMI 35 I/O General-purpose digital I/O / USCIA1 receive data input in UART mode, slave data out/master in in SPI mode P4.0/TB0 36 I/O General-purpose digital I/O / Timer_B, capture: CCI0A/B input, compare: Out0 output P4.1/TB1 37 I/O General-purpose digital I/O / Timer_B, capture: CCI1A/B input, compare: Out1 output POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 MSP430x23x, MSP430x24x(1), MSP430x2410 MIXED SIGNAL MICROCONTROLLER SLAS547A -- JUNE 2007 -- REVISED NOVEMBER 2007 Terminal Functions -- MSP430F24x1 (Continued) TERMINAL NAME NO. I/O DESCRIPTION P4.2/TB2 38 I/O General-purpose digital I/O / Timer_B, capture: CCI2A/B input, compare: Out2 output P4.3/TB3 39 I/O General-purpose digital I/O / Timer_B, capture: CCI3A/B input, compare: Out3 output P4.4/TB4 40 I/O General-purpose digital I/O / Timer_B, capture: CCI4A/B input, compare: Out4 output P4.5/TB5 41 I/O General-purpose digital I/O / Timer_B, capture: CCI5A/B input, compare: Out5 output P4.6/TB6 42 I/O General-purpose digital I/O / Timer_B, capture: CCI6A input, compare: Out6 output P4.7/TBCLK 43 I/O General-purpose digital I/O / Timer_B, clock signal TBCLK input P5.0/UCB1STE/ UCA1CLK 44 I/O General-purpose digital I/O / USCI B1 slave transmit enable/USCI A1 clock input/output P5.1/UCB1SIMO/ UCB1SDA 45 I/O General-purpose digital I/O / USCI B1 slave in/master out in SPI mode, SDA I2C data in I2C mode P5.2/UCB1SOMI/ UCB1SCL 46 I/O General-purpose digital I/O / USCI B1 slave out/master in in SPI mode, SCL I2C clock in I2C mode P5.3/UCB1CLK/ UCA1STE 47 I/O General-purpose digital I/O / USCI B1 clock input/output, USCI A1 slave transmit enable P5.4/MCLK 48 I/O General-purpose digital I/O / main system clock MCLK output P5.5/SMCLK 49 I/O General-purpose digital I/O / submain system clock SMCLK output P5.6/ACLK 50 I/O General-purpose digital I/O / auxiliary clock ACLK output P5.7/TBOUTH/ SVSOUT 51 I/O General-purpose digital I/O / switch all PWM digital output ports to high impedance -- Timer_B TB0 to TB6/SVS comparator output P6.0 59 I/O General-purpose digital I/O P6.1 60 I/O General-purpose digital I/O P6.2 61 I/O General-purpose digital I/O P6.3 2 I/O General-purpose digital I/O P6.4 3 I/O General-purpose digital I/O P6.5 4 I/O General-purpose digital I/O P6.6 5 I/O General-purpose digital I/O P6.7/SVSIN 6 I/O General-purpose digital I/O / SVS input XT2OUT 52 O Output terminal of crystal oscillator XT2 XT2IN 53 I Input port for crystal oscillator XT2 RST/NMI 58 I Reset input, nonmaskable interrupt input port, or bootstrap loader start (in Flash devices). TCK 57 I Test clock (JTAG). TCK is the clock input port for device programming test and bootstrap loader start TDI/TCLK 55 I Test data input or test clock input. The device protection fuse is connected to TDI/TCLK. TDO/TDI 54 I/O TMS 56 I Test mode select. TMS is used as an input port for device programming and test. DVSS 10 I Connected to DVSS Reserved 7 O Reserved, do not connect externally DVSS 11 I Connected to DVSS XIN 8 I Input port for crystal oscillator XT1. Standard or watch crystals can be connected. XOUT 9 O Output port for crystal oscillator XT1. Standard or watch crystals can be connected. NA NA QFN Pad 14 Test data output port. TDO/TDI data output or programming data input terminal QFN package pad connection to DVSS recommended (RTD package only) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MSP430x23x, MSP430x24x(1), MSP430x2410 MIXED SIGNAL MICROCONTROLLER SLAS547A -- JUNE 2007 -- REVISED NOVEMBER 2007 short-form description CPU The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand. Program Counter PC/R0 Stack Pointer SP/R1 SR/CG1/R2 Status Register Constant Generator The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-register operation execution time is one cycle of the CPU clock. Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and constant generator, respectively. The remaining registers are general-purpose registers. Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all instructions. instruction set The instruction set consists of 51 instructions with three formats and seven address modes. Each instruction can operate on word and byte data. Table 1 shows examples of the three types of instruction formats; the address modes are listed in Table 2. CG2/R3 General-Purpose Register R4 General-Purpose Register R5 General-Purpose Register R6 General-Purpose Register R7 General-Purpose Register R8 General-Purpose Register R9 General-Purpose Register R10 General-Purpose Register R11 General-Purpose Register R12 General-Purpose Register R13 General-Purpose Register R14 General-Purpose Register R15 Table 1. Instruction Word Formats Dual operands, source-destination e.g., ADD R4,R5 R4 + R5 ------> R5 Single operands, destination only e.g., CALL PC ---->(TOS), R8----> PC Relative jump, un/conditional e.g., JNE R8 Jump-on-equal bit = 0 Table 2. Address Mode Descriptions ADDRESS MODE Register Indexed Symbolic (PC relative) Absolute Indirect S D D D D D D D D D D SYNTAX EXAMPLE MOV Rs,Rd MOV R10,R11 MOV X(Rn),Y(Rm) MOV 2(R5),6(R6) MOV EDE,TONI OPERATION R10 ----> R11 M(2+R5)----> M(6+R6) M(EDE) ----> M(TONI) MOV &MEM,&TCDAT M(MEM) ----> M(TCDAT) MOV @Rn,Y(Rm) MOV @R10,Tab(R6) M(R10) ----> M(Tab+R6) M(R10) ----> R11 R10 + 2----> R10 Indirect autoincrement D MOV @Rn+,Rm MOV @R10+,R11 Immediate D MOV #X,TONI MOV #45,TONI #45 ----> M(TONI) NOTE: S = source, D = destination POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 MSP430x23x, MSP430x24x(1), MSP430x2410 MIXED SIGNAL MICROCONTROLLER SLAS547A -- JUNE 2007 -- REVISED NOVEMBER 2007 operating modes The MSP430 has one active mode and five software-selectable low-power modes of operation. An interrupt event can wake up the device from any of the five low-power modes, service the request, and restore back to the low-power mode on return from the interrupt program. The following six operating modes can be configured by software: D Active mode (AM) -- All clocks are active D Low-power mode 0 (LPM0) -- CPU is disabled ACLK and SMCLK remain active, MCLK is disabled D Low-power mode 1 (LPM1) -- CPU is disabled ACLK and SMCLK remain active, MCLK is disabled DCO’s dc-generator is disabled if DCO not used in active mode D Low-power mode 2 (LPM2) -- CPU is disabled MCLK and SMCLK are disabled DCO’s dc-generator remains enabled ACLK remains active D Low-power mode 3 (LPM3) -- CPU is disabled MCLK and SMCLK are disabled DCO’s dc-generator is disabled ACLK remains active D Low-power mode 4 (LPM4) -- 16 CPU is disabled ACLK is disabled MCLK and SMCLK are disabled DCO’s dc-generator is disabled Crystal oscillator is stopped POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MSP430x23x, MSP430x24x(1), MSP430x2410 MIXED SIGNAL MICROCONTROLLER SLAS547A -- JUNE 2007 -- REVISED NOVEMBER 2007 interrupt vector addresses The interrupt vectors and the power-up starting address are located in the address range 0xFFFF to 0xFFC0. The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence. If the reset vector (0xFFFE) contains 0xFFFF (e.g., flash is not programmed) the CPU enters LPM4 after power-up. INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT WORD ADDRESS PRIORITY Power-up External reset Watchdog Flash key violation PC out of range (see Note 1) PORIFG WDTIFG RSTIFG KEYV (see Note 2) Reset 0xFFFE 31, highest NMI Oscillator fault Flash memory access violation NMIIFG OFIFG ACCVIFG (see Notes 2 and 7) (Non)maskable (Non)maskable (Non)maskable 0xFFFC Timer_B7 (see Note 3) TBCCR0 CCIFG (see Note 4) Maskable 0xFFFA 29 Timer_B7 (see Note 3) TBCCR1 to TBCCR6 CCIFGs, TBIFG (see Notes 2 and 4) Maskable 0xFFF8 28 Comparator_A+ CAIFG Maskable 0xFFF6 27 Watchdog timer+ WDTIFG Maskable 0xFFF4 26 Timer_A3 TACCR0 CCIFG (see Note 4) Maskable 0xFFF2 25 Timer_A3 TACCR1 CCIFG TACCR2 CCIFG TAIFG (see Note 2 and 4) Maskable 0xFFF0 24 USCI_A0/USCI_B0 receive USCI_B0 I2C status UCA0RXIFG, UCB0RXIFG (see Note 2 and 5) Maskable 0xFFEE 23 USCI_A0/USCI_B0 transmit USCI_B0 I2C receive / transmit UCA0TXIFG, UCB0TXIFG (see Note 2 and 6) Maskable 0xFFEC 22 ADC12 (see Note 8) ADC12IFG (see Notes 2 and 4) Maskable 0xFFEA 21 0xFFE8 20 I/O port P2 (eight flags) P2IFG.0 to P2IFG.7 (see Notes 2 and 4) Maskable 0xFFE6 19 Maskable 0xFFE4 18 I/O port P1 (eight flags) P1IFG.0 to P1IFG.7 (see Notes 2 and 4) 30 USCI A1/B1 receive UCA1RXIFG, UCB1RXIFG (see Note 2) Maskable 0xFFE2 17 USCI A1/B1 transmit UCA1TXIFG, UCB1TXIFG (see Note 2) Maskable 0xFFE0 16 Reserved (see Notes 9 and 10) Reserved 0xFFDE to 0xFFC0 15 to 0, 0 lowest NOTES: 1. A reset is executed if the CPU tries to fetch instructions from within the module register memory address range (0x0000 --0x01FF) or from within unused address ranges. 2. Multiple source flags. 3. Timer_B7 in MSP430F24x(1), MSP430F2410 family has 7 CCRs, Timer_B3 in MSP430F23x family has three CCRs. In Timer_B3, there are only interrupt flags TBCCR0, 1, and 2 CCIFGs, and the interrupt enable bits TBCCTL0, 1, and 2 CCIE. 4. Interrupt flags are located in the module. 5. In SPI mode: UCB0RXIFG. In I2C mode: UCALIFG, UCNACKIFG, ICSTTIFG, UCSTPIFG. 6. In UART/SPI mode: UCB0TXIFG. In I2C mode: UCB0RXIFG, UCB0TXIFG. 7. (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot. 8. ADC12 is not implemented in the MSP430F24x1 family. 9. The address 0xFFDE is used as bootstrap loader security key (BSLSKEY). A 0xAA55 at this location disables the BSL completely. A zero disables the erasure of the flash if an invalid password is supplied. 10. The interrupt vectors at addresses 0xFFDE to 0xFFC0 are not used in this device and can be used for regular program code if necessary. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17 MSP430x23x, MSP430x24x(1), MSP430x2410 MIXED SIGNAL MICROCONTROLLER SLAS547A -- JUNE 2007 -- REVISED NOVEMBER 2007 special function registers Most interrupt enable bits are collected in the lowest address space. Special-function register bits not allocated to a functional purpose are not physically present in the device. This arrangement provides simple software access. interrupt enable 1 and 2 Address 7 6 0x0h 5 4 ACCVIE rw-0 3 2 1 0 NMIIE OFIE WDTIE rw-0 rw-0 rw-0 Interrupt Enable register 1 WDTIE Watchdog timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdog timer is configured as general-purpose timer. OFIE Oscillator-fault-interrupt enable NMIIE Nonmaskable-interrupt enable ACCVIE Flash memory access violation interrupt enable Address 7 6 5 4 0x1h 3 2 1 0 UCB0TXIE UCB0RXIE UCA0TXIE UCA0RXIE rw-0 rw-0 rw-0 rw-0 Interrupt Enable register 2 18 UCA0RXIE USCI_A0 receive-interrupt enable UCA0TXIE USCI_A0 transmit-interrupt enable UCB0RXIE USCI_B0 receive-interrupt enable UCB0TXIE USCI_B0 transmit-interrupt enable POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MSP430x23x, MSP430x24x(1), MSP430x2410 MIXED SIGNAL MICROCONTROLLER SLAS547A -- JUNE 2007 -- REVISED NOVEMBER 2007 interrupt flag register 1 and 2 7 Address 6 5 0x2h 4 3 2 1 0 NMIIFG RSTIFG PORIFG OFIFG WDTIFG rw-0 rw-(0) rw-(1) rw-1 rw-(0) Interrupt Flag register 1 WDTIFG Set on watchdog-timer overflow or security key violation. Reset on VCC power-on, or a reset condition at the RST/NMI pin in reset mode. OFIFG Flag set on oscillator fault PORIFG Power-on interrupt flag. Set on VCC power-up. RSTIFG External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset on VCC power--up. NMIIFG Set via RST/NMI pin Address 7 6 5 4 0x3h 3 2 1 0 UCB0TXIFG UCB0RXIFG UCA0TXIFG UCA0RXIFG rw-1 rw-0 rw-1 rw-0 Interrupt Flag register 2 UCA0RXIFG USCI_A0 receive-interrupt flag UCA0TXIFG USCI_A0 transmit-interrupt flag UCB0RXIFG USCI_B0 receive-interrupt flag UCB0TXIFG USCI_B0 transmit-interrupt flag L e g en d rw : rw -0 ,1 : rw -(0,1) B it c an b e rea d a n d w ritten . B it c an b e rea d a n d w ritten . It is R eset o r S et b y P U C . B it c an b e rea d a n d w ritten . It is R eset o r S et b y P O R . S F R b it is n o t p rese n t in d e vic e . POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 19 MSP430x23x, MSP430x24x(1), MSP430x2410 MIXED SIGNAL MICROCONTROLLER SLAS547A -- JUNE 2007 -- REVISED NOVEMBER 2007 memory organization (MSP430F23x, MSP430F24x(1), MSP430F2410) MSP430F233 MSP430F235 MSP430F249 MSP430F2491 Size Flash Flash 8KB 0xFFFF to 0xFFC0 0xFFFF to 0xE000 16KB 0xFFFF to 0xFFC0 0xFFFF to 0xC000 60KB 0xFFFF to 0xFFC0 0xFFFF to 0x1100 Size 1KB 0x05FF to 0x0200 2KB 0x09FF to 0x0200 2KB 0x09FF to 0x0200 Information memory Size Flash 256 Byte 0x10FF to 0x1000 256 Byte 0x10FF to 0x1000 256 Byte 0x10FF to 0x1000 Boot memory Size ROM 1KB 0x0FFF to 0x0C00 1KB 0x0FFF to 0x0C00 1KB 0x0FFF to 0x0C00 Size 1KB 0x05FF to 0x0200 2KB 0x09FF to 0x0200 2KB 0x09FF to 0x0200 16-bit 8-bit SFR 0x01FF to 0x0100 0x00FF to 0x0010 0x000F to 0x0000 0x01FF to 0x0100 0x00FF to 0x0010 0x000F to 0x0000 0x01FF to 0x0100 0x00FF to 0x0010 0x000F to 0x0000 MSP430F247 MSP430F2471 MSP430F248 MSP430F2481 MSP430F2410 Size Flash Flash 32KB 0xFFFF to 0xFFC0 0xFFFF to 0x8000 48KB 0xFFFF to 0xFFC0 0xFFFF to 0x4000 56KB 0xFFFF to 0xFFC0 0xFFFF to 0x2100 RAM (Total) Size Extended Size Mirrored Size 4KB 0x20FF to 0x1100 2KB 0x20FF to 0x1900 2KB 0x18FF to 0x1100 4KB 0x20FF to 0x1100 2KB 0x20FF to 0x1900 2KB 0x18FF to 0x1100 4KB 0x20FF to 0x1100 2KB 0x20FF to 0x1900 2KB 0x18FF to 0x1100 Memory Main: interrupt vector Main: code memory RAM (total) RAM Peripherals Memory Main: interrupt vector Main: code memory Information memory Size Flash 256 Byte 0x10FF to 0x1000 256 Byte 0x10FF to 0x1000 256 Byte 0x10FF to 0x1000 Boot memory Size ROM 1KB 0x0FFF to 0x0C00 1KB 0x0FFF to 0x0C00 1KB 0x0FFF to 0x0C00 Size 2KB 0x09FF to 0x0200 2KB 0x09FF to 0x0200 2KB 0x09FF to 0x0200 16-bit 8-bit SFR 0x01FF to 0x0100 0x00FF to 0x0010 0x000F to 0x0000 0x01FF to 0x0100 0x00FF to 0x0010 0x000F to 0x0000 0x01FF to 0x0100 0x00FF to 0x0010 0x000F to 0x0000 RAM (mirrored at 0x18FF to 0x01100) Peripherals bootstrap loader (BSL) The MSP430 BSL enables users to program the flash memory or RAM using a UART serial interface. Access to the MSP430 memory via the BSL is protected by user-defined password. For complete description of the features of the BSL and its implementation, see the application report Features of the MSP430 Bootstrap Loader (literature number SLAA089). 20 BSL FUNCTION PM, RTD PACKAGE PINS Data Transmit 13 - P1.1 Data Receive 22 - P2.2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MSP430x23x, MSP430x24x(1), MSP430x2410 MIXED SIGNAL MICROCONTROLLER SLAS547A -- JUNE 2007 -- REVISED NOVEMBER 2007 flash memory The flash memory can be programmed via the JTAG port, the BSL, or in-system by the CPU. The CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include: D Flash memory has n segments of main memory and four segments of information memory (A to D) of 64 bytes each. Each segment in main memory is 512 bytes in size. D Segments 0 to n may be erased in one step, or each segment may be individually erased. D Segments A to D can be erased individually, or as a group with segments 0--n. Segments A to D are also called information memory. D Segment A contains calibration data. After reset segment A is protected against programming or erasing. It can be unlocked but care should be taken not to erase this segment if the calibration data is required. D Flash content integrity check with marginal read modes. peripherals Peripherals are connected to the CPU through data, address, and control busses and can be handled using all instructions. For complete module descriptions, see the MSP430x2xx Family User’s Guide, literature number SLAU144. oscillator and system clock The clock system in the MSP430x23x, MSP43x24x(1), and MSP430F2410 family of devices is supported by the basic clock module that includes support for a 32768-Hz watch crystal oscillator, an internal very-low-power, low-frequency oscillator, an internal digitally-controlled oscillator (DCO), and a high-frequency crystal oscillator. The basic clock module is designed to meet the requirements of both low system cost and low power consumption. The internal DCO provides a fast turn-on clock source and stabilizes in less than 1 μs. The basic clock module provides the following clock signals: D Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal, a high frequency crystal, or a very low power LF oscillator D Main clock (MCLK), the system clock used by the CPU D Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 21 MSP430x23x, MSP430x24x(1), MSP430x2410 MIXED SIGNAL MICROCONTROLLER SLAS547A -- JUNE 2007 -- REVISED NOVEMBER 2007 calibration data stored in information memory segment A Calibration data is stored for the DCO and for the ADC12. It is organized in a tag--length--value (TLV) structure. TAGS USED BY THE ADC CALIBRATION TAGS NAME ADDRESS VALUE TAG_DCO_30 0x10F6 0x01 DCO frequency calibration at VCC = 3 V and TA = 25°C at calibration TAG_ADC12_1 0x10DA 0x10 ADC12_1 calibration tag -- 0xFE Identifier for empty memory areas TAG_EMPTY DESCRIPTION LABELS USED BY THE ADC CALIBRATION TAGS LABEL CONDITION AT CALIBRATION / DESCRIPTION SIZE ADDRESS OFFSET CAL_ADC_25T85 INCHx = 0x1010; REF2_5 = 1, TA = 85°C word 0x000E CAL_ADC_25T30 INCHx = 0x1010; REF2_5 = 1, TA = 30°C word 0x000C CAL_ADC_25VREF_FACTOR REF2_5 = 1, TA = 30°C, IVREF+ = 1.0 mA word 0x000A CAL_ADC_15T85 INCHx = 0x1010; REF2_5 = 0, TA = 85°C word 0x0008 CAL_ADC_15T30 INCHx = 0x1010; REF2_5 = 0, TA = 30°C word 0x0006 CAL_ADC_15VREF_FACTOR REF2_5 = 0, TA = 30°C, IVREF+ = 0.5 mA word 0x0004 CAL_ADC_OFFSET External Vref = 1.5 V, fADC12CLK = 5 MHz word 0x0002 CAL_ADC_GAIN_FACTOR External Vref = 1.5 V, fADC12CLK = 5 MHz word 0x0000 CAL_BC1_1MHz -- byte 0x0007 CAL_DCO_1MHz -- byte 0x0006 CAL_BC1_8MHz -- byte 0x0005 CAL_DCO_8MHz -- byte 0x0004 CAL_BC1_12MHz -- byte 0x0003 CAL_DCO_12MHz -- byte 0x0002 CAL_BC1_16MHz -- byte 0x0001 CAL_DCO_16MHz -- byte 0x0000 brownout, supply voltage supervisor The brownout circuit is implemented to provide the proper internal reset signal to the device during power on and power off. The supply voltage supervisor (SVS) circuitry detects if the supply voltage drops below a user-selectable level and supports both supply voltage supervision (the device is automatically reset) and supply voltage monitoring (SVM, the device is not automatically reset). The CPU begins code execution after the brownout circuit releases the device reset. However, VCC may not have ramped to VCC(min) at that time. The user must ensure that the default DCO settings are not changed until VCC reaches VCC(min). If desired, the SVS circuit can be used to determine when VCC reaches VCC(min). 22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MSP430x23x, MSP430x24x(1), MSP430x2410 MIXED SIGNAL MICROCONTROLLER SLAS547A -- JUNE 2007 -- REVISED NOVEMBER 2007 digital I/O There are up to six 8-bit I/O ports implemented—ports P1 through P6. D D D D D All individual I/O bits are independently programmable. Any combination of input, output, and interrupt conditions is possible. Edge-selectable interrupt input capability for all eight bits of ports P1 and P2. Read/write access to port-control registers is supported by all instructions. Each I/O has an individually programmable pullup/pulldown resistor. watchdog timer + (WDT+) The primary function of the WDT+ module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be configured as an interval timer and can generate interrupts at selected time intervals. hardware multiplier The multiplication operation is supported by a dedicated peripheral module. The module performs 16×16, 16×8, 8×16, and 8×8 bit operations. The module is capable of supporting signed and unsigned multiplication as well as signed and unsigned multiply and accumulate operations. The result of an operation can be accessed immediately after the operands have been loaded into the peripheral registers. No additional clock cycles are required. timer_A3 Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. TIMER_A3 SIGNAL CONNECTIONS INPUT PIN NUMBER DEVICE INPUT SIGNAL MODULE INPUT NAME 12 - P1.0 TACLK TACLK ACLK ACLK SMCLK SMCLK 21 - P2.1 TAINCLK INCLK 13 - P1.1 TA0 CCI0A 22 - P2.2 14 - P1.2 15 - P1.3 † TA0 CCI0B DVSS GND DVCC VCC TA1 CCI1A CAOUT (internal) CCI1B DVSS GND MODULE BLOCK MODULE OUTPUT SIGNAL Timer NA OUTPUT PIN NUMBER 13 - P1.1 CCR0 TA0 17 - P1.5 27 - P2.7 14 - P1.2 CCR1 TA1 18 - P1.6 23 - P2.3 DVCC VCC ADC12{ (internal) TA2 CCI2A 15 - P1.3 ACLK (internal) CCI2B DVSS GND DVCC VCC CCR2 TA2 19 - P1.7 24 - P2.4 Not available in the MSP430F24x1 devices POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 23 MSP430x23x, MSP430x24x(1), MSP430x2410 MIXED SIGNAL MICROCONTROLLER SLAS547A -- JUNE 2007 -- REVISED NOVEMBER 2007 timer_B7 (MSP430F24x(1) and MSP430F2410 devices) Timer_B7 is a 16-bit timer/counter with seven capture/compare registers. Timer_B7 can support multiple capture/compares, PWM outputs, and interval timing. Timer_B7 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. TIMER_B7 SIGNAL CONNECTIONS INPUT PIN NUMBER DEVICE INPUT SIGNAL MODULE INPUT NAME 43 - P4.7 TBCLK TBCLK MODULE OUTPUT SIGNAL Timer NA ACLK SMCLK SMCLK 43 - P4.7 TBCLK INCLK 36 - P4.0 TB0 CCI0A 36 - P4.0 36 - P4.0 TB0 CCI0B ADC12{ (internal) DVSS GND 37 - P4.1 DVCC VCC TB1 CCI1A TB1 CCI1B DVSS GND DVCC VCC 38 - P4.2 TB2 CCI2A 38 - P4.2 TB2 CCI2B DVSS GND 39 - P4.3 39 - P4.3 DVCC VCC TB3 CCI3A TB3 CCI3B DVSS GND DVCC VCC 40 - P4.4 TB4 CCI4A 40 - P4.4 TB4 CCI4B DVSS GND 41 - P4.5 41 - P4.5 42 - P4.6 DVCC VCC TB5 CCI5A TB5 CCI5B DVSS GND DVCC VCC TB6 CCI6A ACLK (internal) CCI6B DVSS GND DVCC VCC CCR0 POST OFFICE BOX 655303 TB0 37 - P4.1 CCR1 TB1 ADC12{ (internal) 38 - P4.2 CCR2 TB2 39 - P4.3 CCR3 TB3 40 - P4.4 CCR4 TB4 41 - P4.5 CCR5 TB5 42 - P4.6 CCR6 Not available in the MSP430F24x1 devices 24 OUTPUT PIN NUMBER ACLK 37 - P4.1 † MODULE BLOCK • DALLAS, TEXAS 75265 TB6 MSP430x23x, MSP430x24x(1), MSP430x2410 MIXED SIGNAL MICROCONTROLLER SLAS547A -- JUNE 2007 -- REVISED NOVEMBER 2007 timer_B3 (MSP430F23x devices) Timer_B3 is a 16-bit timer/counter with seven capture/compare registers. Timer_B3 can support multiple capture/compares, PWM outputs, and interval timing. Timer_B3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. TIMER_B3 SIGNAL CONNECTIONS INPUT PIN NUMBER DEVICE INPUT SIGNAL MODULE INPUT NAME 43 - P4.7 TBCLK TBCLK MODULE BLOCK MODULE OUTPUT SIGNAL Timer NA OUTPUT PIN NUMBER ACLK ACLK SMCLK SMCLK 43 - P4.7 TBCLK INCLK 36 - P4.0 TB0 CCI0A 36 - P4.0 36 - P4.0 TB0 CCI0B ADC12 (internal) DVSS GND 37 - P4.1 37 - P4.1 DVCC VCC TB1 CCI1A TB1 CCI1B DVSS GND DVCC VCC 38 - P4.2 TB2 CCI2A 38 - P4.2 TB2 CCI2B DVSS GND DVCC VCC CCR0 TB0 37 - P4.1 CCR1 TB1 ADC12 (internal) 38 - P4.2 CCR2 TB2 universal serial communications interface (USCI) The USCI modules are used for serial data communication. The USCI module supports synchronous communication protocols such as SPI (3 or 4 pin) or I2C and asynchronous combination protocols such UART, enhanced UART with automatic baudrate detection (LIN), and IrDA. The USCI A module provides support for SPI (3 or 4 pin), UART, enhanced UART, and IrDA. The USCI B module provides support for SPI (3 or 4 pin) and I2C. comparator_A+ The primary function of the comparator_A+ module is to support precision slope analog--to--digital conversions, battery--voltage supervision, and monitoring of external analog signals. ADC12 (MSP430F23x, MSP430F24x, and MSP430F2410 devices only) The ADC12 module supports fast, 12-bit analog-to-digital conversions. The module implements a 12-bit SAR core, sample select control, reference generator, and a 16-word conversion-and-control buffer. The conversion-and-control buffer allows up to 16 independent ADC samples to be converted and stored without any CPU intervention. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 25 MSP430x23x, MSP430x24x(1), MSP430x2410 MIXED SIGNAL MICROCONTROLLER SLAS547A -- JUNE 2007 -- REVISED NOVEMBER 2007 peripheral file map PERIPHERAL FILE MAP ADC12 (MSP430F24x, MSP430F2410 MSP430F2410, and MSP430F23x) 26 Interrupt-vector-word register ADC12IV 0x01A8 Inerrupt-enable register ADC12IE 0x01A6 Inerrupt-flag register ADC12IFG 0x01A4 Control register 1 ADC12CTL1 0x01A2 Control register 0 ADC12CTL0 0x01A0 Conversion memory 15 ADC12MEM15 0x015E Conversion memory 14 ADC12MEM14 0x015C Conversion memory 13 ADC12MEM13 0x015A Conversion memory 12 ADC12MEM12 0x0158 Conversion memory 11 ADC12MEM11 0x0156 Conversion memory 10 ADC12MEM10 0x0154 Conversion memory 9 ADC12MEM9 0x0152 Conversion memory 8 ADC12MEM8 0x0150 Conversion memory 7 ADC12MEM7 0x014E Conversion memory 6 ADC12MEM6 0x014C Conversion memory 5 ADC12MEM5 0x014A Conversion memory 4 ADC12MEM4 0x0148 Conversion memory 3 ADC12MEM3 0x0146 Conversion memory 2 ADC12MEM2 0x0144 Conversion memory 1 ADC12MEM1 0x0142 Conversion memory 0 ADC12MEM0 0x0140 ADC memory-control register15 ADC12MCTL15 0x008F ADC memory-control register14 ADC12MCTL14 0x008E ADC memory-control register13 ADC12MCTL13 0x008D ADC memory-control register12 ADC12MCTL12 0x008C ADC memory-control register11 ADC12MCTL11 0x008B ADC memory-control register10 ADC12MCTL10 0x008A ADC memory-control register9 ADC12MCTL9 0x0089 ADC memory-control register8 ADC12MCTL8 0x0088 ADC memory-control register7 ADC12MCTL7 0x0087 ADC memory-control register6 ADC12MCTL6 0x0086 ADC memory-control register5 ADC12MCTL5 0x0085 ADC memory-control register4 ADC12MCTL4 0x0084 ADC memory-control register3 ADC12MCTL3 0x0083 ADC memory-control register2 ADC12MCTL2 0x0082 ADC memory-control register1 ADC12MCTL1 0x0081 ADC memory-control register0 ADC12MCTL0 0x0080 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MSP430x23x, MSP430x24x(1), MSP430x2410 MIXED SIGNAL MICROCONTROLLER SLAS547A -- JUNE 2007 -- REVISED NOVEMBER 2007 peripheral file map (continued) PERIPHERAL FILE MAP (CONTINUED) Timer_B7 _ (MSP430F24x(1) and MSP430F2410) Timer_B3 _ (MSP430F23x) Timer_A3 _ Capture/compare register 6 TBCCR6 0x019E Capture/compare register 5 TBCCR5 0x019C Capture/compare register 4 TBCCR4 0x019A Capture/compare register 3 TBCCR3 0x0198 Capture/compare register 2 TBCCR2 0x0196 Capture/compare register 1 TBCCR1 0x0194 Capture/compare register 0 TBCCR0 0x0192 Timer_B register TBR 0x0190 Capture/compare control 6 TBCCTL6 0x018E Capture/compare control 5 TBCCTL5 0x018C Capture/compare control 4 TBCCTL4 0x018A Capture/compare control 3 TBCCTL3 0x0188 Capture/compare control 2 TBCCTL2 0x0186 Capture/compare control 1 TBCCTL1 0x0184 Capture/compare control 0 TBCCTL0 0x0182 Timer_B control TBCTL 0x0180 Timer_B interrupt vector TBIV 0x011E Capture/compare register 2 TBCCR2 0x0196 Capture/compare register 1 TBCCR1 0x0194 Capture/compare register 0 TBCCR0 0x0192 Timer_B register TBR 0x0190 Capture/compare control 2 TBCCTL2 0x0186 Capture/compare control 1 TBCCTL1 0x0184 Capture/compare control 0 TBCCTL0 0x0182 Timer_B control TBCTL 0x0180 Timer_B interrupt vector TBIV 0x011E Capture/compare register 2 TACCR2 0x0176 Capture/compare register 1 TACCR1 0x0174 Capture/compare register 0 TACCR0 0x0172 Timer_A register TAR 0x0170 Reserved 0x016E Reserved 0x016C Reserved 0x016A Reserved 0x0168 Capture/compare control 2 TACCTL2 0x0166 Capture/compare control 1 TACCTL1 0x0164 Capture/compare control 0 TACCTL0 0x0162 Timer_A control TACTL 0x0160 Timer_A interrupt vector TAIV 0x012E POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 27 MSP430x23x, MSP430x24x(1), MSP430x2410 MIXED SIGNAL MICROCONTROLLER SLAS547A -- JUNE 2007 -- REVISED NOVEMBER 2007 peripheral file map (continued) PERIPHERAL FILE MAP (CONTINUED) Hardware Multiplier Flash 28 Sum extend SUMEXT 0x013E Result high word RESHI 0x013C Result low word RESLO 0x013A Second operand OP2 0x0138 Multiply signed +accumulate/operand1 MACS 0x0136 Multiply+accumulate/operand1 MAC 0x0134 Multiply signed/operand1 MPYS 0x0132 Multiply unsigned/operand1 MPY 0x0130 Flash control 4 FCTL4 0x01BE Flash control 3 FCTL3 0x012C Flash control 2 FCTL2 0x012A Flash control 1 FCTL1 0x0128 Watchdog Watchdog Timer control WDTCTL 0x0120 USCI A0/B0 / USCI A0 auto baud rate control UCA0ABCTL 0x005D USCI A0 transmit buffer UCA0TXBUF 0x0067 USCI A0 receive buffer UCA0RXBUF 0x0066 USCI A0 status UCA0STAT 0x0065 USCI A0 modulation control UCA0MCTL 0x0064 USCI A0 baud rate control 1 UCA0BR1 0x0063 USCI A0 baud rate control 0 UCA0BR0 0x0062 USCI A0 control 1 UCA0CTL1 0x0061 USCI A0 control 0 UCA0CTL0 0x0060 USCI A0 IrDA receive control UCA0IRRCTL 0x005F USCI A0 IrDA transmit control UCA0IRTCLT 0x005E USCI B0 transmit buffer UCB0TXBUF 0x006F USCI B0 receive buffer UCB0RXBUF 0x006E USCI B0 status UCB0STAT 0x006D USCI B0 I2C Interrupt enable UCB0CIE 0x006C USCI B0 baud rate control 1 UCB0BR1 0x006B USCI B0 baud rate control 0 UCB0BR0 0x006A USCI B0 control 1 UCB0CTL1 0x0069 USCI B0 control 0 UCB0CTL0 0x0068 USCI B0 I2C slave address UCB0SA 0x011A USCI B0 I2C own address UCB0OA 0x0118 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MSP430x23x, MSP430x24x(1), MSP430x2410 MIXED SIGNAL MICROCONTROLLER SLAS547A -- JUNE 2007 -- REVISED NOVEMBER 2007 peripheral file map (continued) PERIPHERAL FILE MAP (CONTINUED) USCI A1/B1 / (MSP430F24x(1) and MSP430F2410) USCI A1 auto baud rate control UCA1ABCTL 0x00CD USCI A1 transmit buffer UCA1TXBUF 0x00D7 USCI A1 receive buffer UCA1RXBUF 0x00D6 USCI A1 status UCA1STAT 0x00D5 USCI A1 modulation control UCA1MCTL 0x00D4 USCI A1 baud rate control 1 UCA1BR1 0x00D3 USCI A1 baud rate control 0 UCA1BR0 0x00D2 USCI A1 control 1 UCA1CTL1 0x00D1 USCI A1 control 0 UCA1CTL0 0x00D0 USCI A1 IrDA receive control UCA1IRRCTL 0x00CF USCI A1 IrDA transmit control UCA1IRTCLT 0x00CE USCI B1 transmit buffer UCB1TXBUF 0x00DF USCI B1 receive buffer UCB1RXBUF 0x00DE USCI B1 status UCB1STAT 0x00DD USCI B1 I2C Interrupt enable UCB1CIE 0x00DC USCI B1 baud rate control 1 UCB1BR1 0x00DB USCI B1 baud rate control 0 UCB1BR0 0x00DA USCI B1 control 1 UCB1CTL1 0x00D9 USCI B1 control 0 UCB1CTL0 0x00D8 USCI B1 I2C slave address UCB1SA 0x017E USCI B1 I2C own address UCB1OA 0x017C USCI A1/B1 interrupt enable UC1IE 0x0006 USCI A1/B1 interrupt flag UC1IFG 0x0007 Comparator_A port disable CAPD 0x005B Comparator_A control2 CACTL2 0x005A Comparator_A control1 CACTL1 0x0059 Basic clock system control3 BCSCTL3 0x0053 Basic clock system control2 BCSCTL2 0x0058 Basic clock system control1 BCSCTL1 0x0057 DCO clock frequency control DCOCTL 0x0056 Brownout, SVS SVS control register (reset by brownout signal) SVSCTL 0x0055 Port P6 Port P6 resistor enable P6REN 0x0013 Port P6 selection P6SEL 0x0037 Port P6 direction P6DIR 0x0036 Port P6 output P6OUT 0x0035 Port P6 input P6IN 0x0034 Port P5 resistor enable P5REN 0x0012 Port P5 selection P5SEL 0x0033 Port P5 direction P5DIR 0x0032 Port P5 output P5OUT 0x0031 Port P5 input P5IN 0x0030 Port P4 resistor enable P4REN 0x0011 Port P4 selection P4SEL 0x001F Port P4 direction P4DIR 0x001E Port P4 output P4OUT 0x001D Port P4 input P4IN 0x001C Comparator_A+ p _ Basic Clock Port P5 Port P4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 29 MSP430x23x, MSP430x24x(1), MSP430x2410 MIXED SIGNAL MICROCONTROLLER SLAS547A -- JUNE 2007 -- REVISED NOVEMBER 2007 peripheral file map (continued) PERIPHERAL FILE MAP (CONTINUED) Port P3 Port P2 Port P1 Special p Functions 30 Port P3 resistor enable P3REN 0x0010 Port P3 selection P3SEL 0x001B Port P3 direction P3DIR 0x001A Port P3 output P3OUT 0x0019 Port P3 input P3IN 0x0018 Port P2 resistor enable P2REN 0x002F Port P2 selection P2SEL 0x002E Port P2 interrupt enable P2IE 0x002D Port P2 interrupt-edge select P2IES 0x002C Port P2 interrupt flag P2IFG 0x002B Port P2 direction P2DIR 0x002A Port P2 output P2OUT 0x0029 Port P2 input P2IN 0x0028 Port P1 resistor enable P1REN 0x0027 Port P1 selection P1SEL 0x0026 Port P1 interrupt enable P1IE 0x0025 Port P1 interrupt-edge select P1IES 0x0024 Port P1 interrupt flag P1IFG 0x0023 Port P1 direction P1DIR 0x0022 Port P1 output P1OUT 0x0021 Port P1 input P1IN 0x0020 SFR interrupt flag2 IFG2 0x0003 SFR interrupt flag1 IFG1 0x0002 SFR interrupt enable2 IE2 0x0001 SFR interrupt enable1 IE1 0x0000 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MSP430x23x, MSP430x24x(1), MSP430x2410 MIXED SIGNAL MICROCONTROLLER SLAS547A -- JUNE 2007 -- REVISED NOVEMBER 2007 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† † Voltage applied at VCC to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . --0.3 V to 4.1 V Voltage applied to any pin‡ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . --0.3 V to VCC + 0.3 V Diode current at any device terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±2 mA Storage temperature§, Tstg:Unprogrammed device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . --55°C to 150°C Programmed device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . --40°C to 105°C Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. ‡ All voltages referenced to V . The JTAG fuse-blow voltage, V , is allowed to exceed the absolute maximum rating. The voltage is applied to SS FB the TDI/TCLK pin when blowing the JTAG fuse. § Higher temperature may be applied during board soldering process according to the current JEDEC J-STD-020 specification with peak reflow temperatures not higher than classified on the device label on the shipping boxes or reels. recommended operating conditions PARAMETER MIN MAX UNITS Supply voltage during program execution, VCC AVCC = DVCC = VCC (see Note 1) 1.8 3.6 V Supply voltage during flash memory programming, VCC AVCC = DVCC = VCC (see Note 1) 2.2 3.6 V Supply voltage, VSS AVSS = DVSS = VSS 0.0 0.0 V I version --40 85 °C T version --40 105 °C VCC = 1.8 V, Duty cycle = 50% ± 10% dc 4.15 VCC = 2.7 V, Duty cycle = 50% ± 10% dc 12 VCC ≥ 3.3 V, Duty cycle = 50% ± 10% dc 16 Operating free-air free air temperature temperat re range, range TA Processor frequency fSYSYTEM (maximum MCLK frequency) (see Notes 2 and 3 and Figure 1) MHz NOTES: 1. It is recommended to power AVCC and DVCC from the same source. A maximum difference of 0.3 V between AVCC and DVCC can be tolerated during power-up. 2. The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse width of the specified maximum frequency. 3. Modules might have a different maximum input clock specification. See the specification of the respective module in this data sheet. Legend: System Frequency --MHz 16 MHz Supply voltage range during flash memory programming 12 MHz Supply voltage range during program execution 7.5 MHz 4.15 MHz 1.8 V 2.2 V 2.7 V 3.3 V 3.6 V Supply Voltage --V NOTE: Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum VCC of 2.2 V. Figure 1. Operating Area POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 31 MSP430x23x, MSP430x24x(1), MSP430x2410 MIXED SIGNAL MICROCONTROLLER SLAS547A -- JUNE 2007 -- REVISED NOVEMBER 2007 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) active mode supply current into VCC excluding external current (see Notes 1 and 2) PARAMETER IAM, 1MHz IAM, 1MHz IAM, 4kHz Active mode (AM) current (1 MHz) Active mode (AM) current (1 MHz) Active mode (AM) current (4 kHz) TEST CONDITIONS TA TYP MAX 275 312 295 318 386 445 417 449 230 261 248 267 321 366 344 370 1.5 3.8 105_C 6 10.5 --40_C to 85_C 2 4.7 7 12.2 fDCO = fMCLK = fSMCLK = 1 MHz, fACLK = 32,768 32 768 Hz, Hz Program executes from flash, BCSCTL1 = CALBC1_1MHZ, CALBC1 1MHZ DCOCTL = CALDCO_1MHZ, _ CPUOFF = 0, 0 SCG0 = 0 0, SCG1 = 0, 0 OSCOFF = 0 --40_C to 85_C fDCO = fMCLK = fSMCLK = 1MHz, fACLK = 32,768Hz, 32 768Hz Program executes in RAM, BCSCTL1 = CALBC1_1MHZ, CALBC1 1MHZ DCOCTL = CALDCO_1MHZ, _ CPUOFF = 0, 0 SCG0 = 0 0, SCG1 = 0, 0 OSCOFF = 0 --40_C to 85_C fMCLK = fSMCLK = fACLK = 32,768Hz/8 = 4,096Hz, fDCO = 0Hz, Program executes in flash, SELMx = 11, SELS = 1, DIVMx = DIVSx = DIVAx = 11, CPUOFF = 0, SCG0 = 1, SCG1 = 0, OSCOFF = 0 --40_C to 85_C 105_C --40_C to 85_C 105_C 105_C --40_C to 85_C 105_C VCC 22V 2.2 3V 22V 2.2 3V MIN UNIT μA μA 22V 2.2 μA 3V 105_C fMCLK = fSMCLK = fDCO(0, 0) ≈ 100kHz, --40_C to 85_C 55 72 22V 2.2 fACLK = 0Hz 0Hz, 105_C 70 81 IAM,100kH Active mode (AM) Program executes in flash, μA RSELx = 0, DCOx = 0, current (100 kHz) z --40_C to 85_C 67 89 CPUOFF = 0, 0 SCG0 = 0 0, SCG1 = 0, 0 3V 105_C 84 100 OSCOFF = 1 NOTES: 1. All inputs are tied to 0 V or VCC. Outputs do not source or sink any current. 2. The currents are characterized with a micro crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external load capacitance is chosen to closely match the required 9 pF. 32 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MSP430x23x, MSP430x24x(1), MSP430x2410 MIXED SIGNAL MICROCONTROLLER SLAS547A -- JUNE 2007 -- REVISED NOVEMBER 2007 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) typical characteristics -- active mode supply current (into DVCC + AVCC) 8.0 5.0 fDCO = 16 MHz 6.0 fDCO = 12 MHz 5.0 fDCO = 8 MHz 4.0 3.0 2.0 4.0 TA = 25 °C 3.0 VCC = 3 V 2.0 TA = 85 °C TA = 25 °C 1.0 VCC = 2.2 V fDCO = 1 MHz 1.0 0.0 1.5 TA = 85 °C Active Mode Current -- mA Active Mode Current -- mA 7.0 2.0 2.5 3.0 3.5 4.0 0.0 0.0 VCC -- Supply Voltage -- V Figure 2. Active Mode Current vs VCC, TA = 25°C POST OFFICE BOX 655303 4.0 8.0 12.0 16.0 fDCO -- DCO Frequency -- MHz Figure 3. Active Mode Current vs DCO Frequency • DALLAS, TEXAS 75265 33 MSP430x23x, MSP430x24x(1), MSP430x2410 MIXED SIGNAL MICROCONTROLLER SLAS547A -- JUNE 2007 -- REVISED NOVEMBER 2007 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) low-power mode supply current into VCC excluding external current (see Notes 1 and 2) PARAMETER ILPM0, 1MHz ILPM0, 100kHz ILPM2 ILPM3,LFXT1 Low-power mode 0 (LPM0) current ((see Note 3)) Low-power mode 0 (LPM0) current (see Note 3) Low-power mode 2 (LPM2) current (see Note 4) Low-power mode 3 (LPM3) current (see Note 4) TEST CONDITIONS TA TYP MAX 60 70 μA 63 75 μA 75 90 μA 80 95 μA 33 40 μA 36 45 μA 36 46 μA 40 50 μA 20 27 μA 25 30 μA 23 30 μA 28 35 μA --40°C 0.8 1.2 25°C 0.9 1.3 3.0 5.0 105°C 9.0 15.0 --40°C 0.9 1.3 1.0 1.4 3.9 6.0 105°C 10.0 17.0 --40°C 0.3 0.9 25°C 0.3 0.9 2.5 4.5 105°C 8.0 15.0 --40°C 0.4 1.0 0.4 1.0 3.1 5.5 9.0 16.0 0.1 0.5 0.1 0.5 1.9 3.6 6.5 13.0 fMCLK = 0 MHz, fSMCLK = fDCO = 1 MHz, MHz fACLK = 32,768Hz, CALBC1 1MHZ BCSCTL1 = CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ, _ CPUOFF = 1, 1 SCG0 = 0 0, SCG1 = 0, 0 OSCOFF = 0 --40_C to 85_C fMCLK = 0MHz, fSMCLK = fDCO(0, 0) ≈ 100kHz, 100kHz fACLK = 0Hz, RSELx = 0, DCOx = 0, CPUOFF = 1, 1 SCG0 = 0 0, SCG1 = 0, 0 OSCOFF = 1 fMCLK = fSMCLK = 0MHz, fDCO = 1 MHz, fACLK = 32 32,768Hz, 768Hz BCSCTL1 = CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ, CPUOFF = 1, 1 SCG0 = 0 0, SCG1 = 1, 1 OSCOFF = 0 --40_C to 85_C fDCO = fMCLK = fSMCLK = 0 MHz, MHz fACLK = 32,768Hz, CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 105_C --40_C to 85_C 105_C 105_C --40_C to 85_C 105_C --40_C to 85_C 105_C --40_C to 85_C 105_C 85°C 25°C 85°C ILPM3,VLO Low-power mode 3 current, ((LPM3)) ( (see Note N t 4) fDCO = fMCLK = fSMCLK = 0 MHz, MHz fACLK from internal LF oscillator (VLO), CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 85°C 25°C 85°C VCC 22V 2.2 3V 22V 2.2 3V 22V 2.2 3V 22V 2.2 3V 22V 2.2 3V 105°C ILPM4 Low-power mode 4 (LPM4) current (see Note 5) fDCO = fMCLK = fSMCLK = 0MHz, 0MHz fACLK = 0Hz, CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1 --40°C 25°C 85°C 105°C 2.2 V and 3V MIN NOTES: 1. All inputs are tied to 0 V or VCC. Outputs do not source or sink any current. 2. The currents are characterized with a micro crystal CC4V--T1A SMD crystal with a load capacitance of 9 pF. The internal and external load capacitance is chosen to closely match the required 9 pF. 3. Current for Brownout and WDT+ is included. The WDT+ is clocked by SMCLK. 4. Current for Brownout and WDT+ is included. The WDT+ is clocked by ACLK. 5. Current for Brownout included. 34 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT μA μA μA μA μA A MSP430x23x, MSP430x24x(1), MSP430x2410 MIXED SIGNAL MICROCONTROLLER SLAS547A -- JUNE 2007 -- REVISED NOVEMBER 2007 typical characteristics -- LPM4 current ILPM4 -- Low--power mode current -- uA 10.0 9.0 8.0 7.0 6.0 5.0 Vcc = 3.6 V 4.0 Vcc = 3 V 3.0 Vcc = 2.2V 2.0 1.0 0.0 --40.0 --20.0 0.0 Vcc = 1.8 V 20.0 40.0 60.0 80.0 100.0 120.0 TA -- Temperature -- °C Figure 4. ILPM4 -- LPM4 Current vs Temperature POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 35 MSP430x23x, MSP430x24x(1), MSP430x2410 MIXED SIGNAL MICROCONTROLLER SLAS547A -- JUNE 2007 -- REVISED NOVEMBER 2007 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) Schmitt-trigger inputs -- ports P1, P2, P3, P4, P5, P6, RST/NMI, JTAG, XIN, and XT2IN (see Note 6) PARAMETER VIT+ VIT-- TEST CONDITIONS Positive-going Positive going input threshold voltage Negative-going Negative going input threshold voltage Vhys Input voltage hysteresis (VIT+ -- VIT-- ) RPull Pullup/pulldown resistor Pullup: VIN = VSS, Pulldown: VIN = VCC CI Input Capacitance VIN = VSS or VCC VCC MIN TYP MAX 0.45 VCC 0.75 VCC 2.2 V 1.0 1.65 3V 1.35 2.25 0.25 VCC 0.55 VCC 2.2 V 0.55 1.2 3V 0.75 1.65 2.2 V 0.2 1.0 3V 0.3 1.0 20 35 50 5 UNIT V V V kΩ pF NOTE 6. XIN and XT2IN only in bypass mode inputs -- ports P1 and P2 PARAMETER TEST CONDITIONS Port P1, P2: P1.x to P2.x, external trigger pulse width to set the interrupt flag (see Note 1) tint External interrupt timing tcap Timer A Timer Timer_A, Timer_B B capture timing fTAext Timer_A, Timer_B clock frequency externally applied to pin TACLK TBCLK TACLK, TBCLK, INCLK: t(H) = t(L) Timer A Timer Timer_A, Timer_B B clock frequency SMCLK or ACLK signal selected fTBext fTAint fTBint VCC MIN 2.2 V/3 V 20 2.2 V 62 3V 50 TA0, TA1, TA2 TB0, TB1, TB2, TB3, TB4, TB5, TB6 MAX UNIT ns ns 2.2 V 8 3V 10 2.2 V 8 3V 10 MHz MHz NOTE 1. The external signal sets the interrupt flag every time the minimum t(int) parameters are met. It may be set even with trigger signals shorter than t(int). leakage current -- ports P1, P2, P3, P4, P5, and P6 (see Note 1 and 2) PARAMETER Ilkg(Px.x) High impedance leakage current TEST CONDITIONS See Notes 1 and 2 VCC MIN 2.2 V/3 V MAX UNIT ±50 nA NOTES: 1. The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted. 2. The leakage of digital port pins is measured individually. The port pin is selected for input and the pullup/pull--down resistor is disabled.. standard inputs -- RST/NMI PARAMETER TEST CONDITIONS VCC MIN MAX UNIT VIL Low-level input voltage 2.2 V/3 V VSS VSS + 0.6 V VIH High-level input voltage 2.2 V/3 V 0.8 VCC VCC V 36 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MSP430x23x, MSP430x24x(1), MSP430x2410 MIXED SIGNAL MICROCONTROLLER SLAS547A -- JUNE 2007 -- REVISED NOVEMBER 2007 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) outputs -- ports P1, P2, P3, P4, P5, and P6 PARAMETER VOH VOL High le el output High-level o tp t voltage oltage TEST CONDITIONS VCC IOH(max) = --1.5 mA, (see Note 1) 2.2 V IOH(max) = --6 mA, (see Note 2) NOTES: 1. The maximum total current, voltage drop specified. 2. The maximum total current, voltage drop specified. MAX VCC 2.2 V VCC -- 0.6 VCC 3V VCC -- 0.25 VCC IOH(max) = --6 mA, (see Note 2) 3V VCC -- 0.6 VCC IOL(max) = 1.5 mA, (see Note 1) 2.2 V VSS VSS + 0.25 IOL(max) = 6 mA, (see Note 2) 2.2 V VSS VSS + 0.6 IOL(max) = 1.5 mA, (see Note 1) 3V VSS VSS + 0.25 IOL(max) = 6 mA, (see Note 2) 3V VSS VSS + 0.6 IOH(max) = --1.5 mA, (see Note 1) Low level output voltage Low-level MIN VCC -- 0.25 UNIT V V IOH(max) and IOL(max), for all outputs combined, should not exceed ±12 mA to satisfy the maximum IOH(max) and IOL(max), for all outputs combined, should not exceed ±48 mA to satisfy the maximum output frequency -- ports P1, P2, P3, P4, P5, and P6 PARAMETER TEST CONDITIONS VCC MIN DC TYP MAX 10 fPx.y Port output frequency with load P1.4/SMCLK, CL = 20 pF, RL = 1 kΩ (see Notes 1 and 2) 2.2 V 3V DC 12 fPort_CLK Clock output frequency P2.0/ACLK/CA2, P1.4/SMCLK, CL = 20 pF, RL = 1 kΩ (see Note 2) 2.2 V DC 12 3.3 V DC 16 t(Xdc) Duty cycle of output frequency P1.0/TACLK/CAOUT, CL = 20 pF, LF mode 30 50 70 P1.0/TACLK/CAOUT, CL = 20 pF, XT1 mode 40 50 60 P1.1/TA0, CL = 20 pF, XT1 mode 40 P1.1/TA0, CL = 20 pF, DCO 50% -- 15 ns P1.4/SMCLK, CL = 20 pF, XT2 mode P1.4/SMCLK, CL = 20 pF, DCO UNIT MHz MHz % 60 50 50% + 15 ns 40 60 50% -- 15 ns 50% + 15 ns % NOTES: 1. A resistive divider with 2 times 0.5 kΩ between VCC and VSS is used as load. The output is connected to the center tap of the divider. 2. The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 37 MSP430x23x, MSP430x24x(1), MSP430x2410 MIXED SIGNAL MICROCONTROLLER SLAS547A -- JUNE 2007 -- REVISED NOVEMBER 2007 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) typical characteristics -- outputs VCC = 2.2 V P4.5 TA = 25°C 20.0 TA = 85°C 15.0 10.0 5.0 0.0 0.0 0.5 1.0 1.5 2.0 50.0 I OL -- Typical Low-Level Output Current -- mA I OL -- Typical Low-Level Output Current -- mA 25.0 TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE of one pin TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE of one pin VCC = 3 V P4.5 TA = 85°C 30.0 20.0 10.0 0.0 0.0 2.5 0.5 VOL -- Low-Level Output Voltage -- V I OH -- Typical High-Level Output Current -- mA I OH -- Typical High-Level Output Current -- mA 2.5 3.0 3.5 0.0 VCC = 2.2 V P4.5 --5.0 --10.0 --15.0 TA = 85°C TA = 25°C 1.0 1.5 2.0 2.5 VOH -- High-Level Output Voltage -- V VCC = 3 V P4.5 --10.0 --20.0 --30.0 --40.0 TA = 85°C --50.0 0.0 TA = 25°C 0.5 1.0 1.5 Figure 8 POST OFFICE BOX 655303 2.0 2.5 3.0 VOH -- High-Level Output Voltage -- V Figure 7 38 2.0 TYPICAL HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE of one pin 0.0 0.5 1.5 Figure 6 TYPICAL HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE of one pin --25.0 0.0 1.0 VOL -- Low-Level Output Voltage -- V Figure 5 --20.0 TA = 25°C 40.0 • DALLAS, TEXAS 75265 3.5 MSP430x23x, MSP430x24x(1), MSP430x2410 MIXED SIGNAL MICROCONTROLLER SLAS547A -- JUNE 2007 -- REVISED NOVEMBER 2007 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) POR/brownout reset (BOR) (see Notes 3 and 4) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT VCC(start) Operating voltage dVCC/dt ± 3 V/s 0.7 ¢ V(B_IT--) V V(B_IT--) Negative going VCC reset threshold voltage dVCC/dt ± 3 V/s 1.71 V Vhys(B_IT--) VCC reset threshold hysteresis dVCC/dt ± 3 V/s 210 mV td(BOR) BOR reset release delay time 2000 μs treset Pulse length at RST/NMI pin to accept a reset 70 2.2 V / 3 V 2 130 μs NOTES: 3. The current consumption of the brownout module is included in the ICC current consumption data. The voltage level V(B_IT--) + Vhys(B_IT--) is ≤ 1.8 V. 4. During power-up, the CPU begins code execution following a period of td(BOR) after VCC = V(B_IT--) + Vhys(B_IT--). The default DCO settings must not be changed until VCC ≥ VCC(MIN), where VCC(min) is the minimum supply voltage for the desired operating frequency. VCC Vhys(B_IT-) V(B_IT-) VCC(Start) 1 0 td(BOR) Figure 9. POR/Brownout Reset (BOR) vs Supply Voltage POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 39 MSP430x23x, MSP430x24x(1), MSP430x2410 MIXED SIGNAL MICROCONTROLLER SLAS547A -- JUNE 2007 -- REVISED NOVEMBER 2007 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) typical characteristics -- POR/brownout reset (BOR) VCC 3V VCC(drop) -- V 2 VCC = 3 V Typical Conditions 1.5 t pw 1 VCC(drop) 0.5 0 0.001 1 1000 1 ns tpw -- Pulse Width -- μs 1 ns tpw -- Pulse Width -- μs Figure 10. VCC(drop) Level With a Square Voltage Drop to Generate a POR/Brownout Signal VCC 2 3V VCC(drop) -- V VCC = 3 V 1.5 t pw Typical Conditions 1 VCC(drop) 0.5 0 0.001 tf = tr 1 1000 tf tr tpw -- Pulse Width -- μs tpw -- Pulse Width -- μs Figure 11. VCC(drop) Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal 40 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MSP430x23x, MSP430x24x(1), MSP430x2410 MIXED SIGNAL MICROCONTROLLER SLAS547A -- JUNE 2007 -- REVISED NOVEMBER 2007 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) SVS (supply voltage supervisor/monitor) PARAMETER t(SVSR) TEST CONDITIONS MIN dVCC/dt > 30 V/ms (see Figure 12) 1 MAX 150 dVCC/dt ≤ 30 V/ms 2000 td(SVSon) SVSON, switch from VLD = 0 to VLD ≠ 0, VCC = 3 V tsettle VLD ≠ 0‡ V(SVSstart) VLD ≠ 0, VCC/dt ≤ 3 V/s (see Figure 12) 20 1.55 VLD = 1 VCC/dt ≤ 3 V/s (see Figure 12) VLD = 2 to 14 Vhys(SVS_IT--) hys(SVS IT--) VCC/dt ≤ 3 V/s (see Figure 12), External voltage applied on A7 VCC/dt ≤ 3 V/s (see Figure 12 and Figure 13) V(SVS_IT--) (SVS IT ) VCC/dt ≤ 3 V/s (see Figure 12 and Figure 13), External voltage applied on A7 ICC(SVS)§ TYP VLD = 15 70 120 0.001 × μs 150 μs 12 μs 1.7 V 210 mV 0.016 × V(SVS_IT--) V(SVS_IT--) 4.4 20 VLD = 1 1.8 1.9 2.05 VLD = 2 1.94 2.1 2.25 VLD = 3 2.05 2.2 2.37 VLD = 4 2.14 2.3 2.48 VLD = 5 2.24 2.4 2.6 VLD = 6 2.33 2.5 2.71 VLD = 7 2.46 2.65 2.86 VLD = 8 2.58 2.8 3 VLD = 9 2.69 2.9 3.13 VLD = 10 2.83 3.05 3.29 VLD = 11 2.94 3.2 3.42 VLD = 12 3.11 3.35 3.61† VLD = 13 3.24 3.5 3.76† VLD = 14 3.43 3.7† 3.99† VLD = 15 1.1 1.2 1.3 10 15 VLD ≠ 0, VCC = 2.2 V/3 V UNIT mV V μA † The recommended operating voltage range is limited to 3.6 V. ‡t settle is the settling time that the comparator output must have a stable level after VLD is switched VLD ≠ 0 to a different VLD value somewhere between 2 and 15. The overdrive is assumed to be >50 mV. § The current consumption of the SVS module is not included in the I CC current consumption data. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 41 MSP430x23x, MSP430x24x(1), MSP430x2410 MIXED SIGNAL MICROCONTROLLER SLAS547A -- JUNE 2007 -- REVISED NOVEMBER 2007 typical characteristics AVCC V(SVS_IT--) V(SVSstart) Software sets VLD >0: SVS is active Vhys(SVS_IT--) Vhys(B_IT--) V(B_IT--) VCC(start) Brownout Brownout Region Brownout Region 1 0 SVS out td(BOR) 1 0 td(SVSon) Set POR 1 t d(BOR) SVS Circuit is Active From VLD > to VCC < V(B_IT--) td(SVSR) undefined 0 Figure 12. SVS Reset (SVSR) vs Supply Voltage VCC 3V t pw 2 Rectangular Drop VCC(min) VCC(min) -- V 1.5 Triangular Drop 1 1 ns 1 ns VCC 0.5 t pw 3V 0 1 10 100 1000 tpw -- Pulse Width -- μs VCC(min) tf = tr tf tr t -- Pulse Width -- μs Figure 13. VCC(min): Square Voltage Drop and Triangle Voltage Drop to Generate an SVS Signal (VLD = 1) 42 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MSP430x23x, MSP430x24x(1), MSP430x2410 MIXED SIGNAL MICROCONTROLLER SLAS547A -- JUNE 2007 -- REVISED NOVEMBER 2007 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) main DCO characteristics D All ranges selected by RSELx overlap with RSELx + 1: RSELx = 0 overlaps RSELx = 1, ... RSELx = 14 overlaps RSELx = 15. D DCO control bits DCOx have a step size as defined by parameter SDCO. D Modulation control bits MODx select how often fDCO(RSEL,DCO+1) is used within the period of 32 DCOCLK cycles. The frequency fDCO(RSEL,DCO) is used for the remaining cycles. The frequency is an average equal to: f average = 32 × f DCO(RSEL,DCO) × f DCO(RSEL,DCO+1) MOD × f DCO(RSEL,DCO)+(32−MOD) × f DCO(RSEL,DCO+1) DCO frequency PARAMETER Vcc Supply voltage range TEST CONDITIONS VCC MIN TYP MAX RSELx < 14 1.8 3.6 RSELx = 14 2.2 3.6 RSELx = 15 3.0 3.6 UNIT V fDCO(0,0) DCO frequency (0, 0) RSELx = 0, DCOx = 0, MODx = 0 2.2 V/3 V 0.06 0.14 MHz fDCO(0,3) DCO frequency (0, 3) RSELx = 0, DCOx = 3, MODx = 0 2.2 V/3 V 0.07 0.17 MHz fDCO(1,3) DCO frequency (1, 3) RSELx = 1, DCOx = 3, MODx = 0 2.2 V/3 V 0.10 0.20 MHz fDCO(2,3) DCO frequency (2, 3) RSELx = 2, DCOx = 3, MODx = 0 2.2 V/3 V 0.14 0.28 MHz fDCO(3,3) DCO frequency (3, 3) RSELx = 3, DCOx = 3, MODx = 0 2.2 V/3 V 0.20 0.40 MHz fDCO(4,3) DCO frequency (4, 3) RSELx = 4, DCOx = 3, MODx = 0 2.2 V/3 V 0.28 0.54 MHz fDCO(5,3) DCO frequency (5, 3) RSELx = 5, DCOx = 3, MODx = 0 2.2 V/3 V 0.39 0.77 MHz fDCO(6,3) DCO frequency (6, 3) RSELx = 6, DCOx = 3, MODx = 0 2.2 V/3 V 0.54 1.06 MHz fDCO(7,3) DCO frequency (7, 3) RSELx = 7, DCOx = 3, MODx = 0 2.2 V/3 V 0.80 1.50 MHz fDCO(8,3) DCO frequency (8, 3) RSELx = 8, DCOx = 3, MODx = 0 2.2 V/3 V 1.10 2.10 MHz fDCO(9,3) DCO frequency (9, 3) RSELx = 9, DCOx = 3, MODx = 0 2.2 V/3 V 1.60 3.00 MHz fDCO(10,3) DCO frequency (10, 3) RSELx = 10, DCOx = 3, MODx = 0 2.2 V/3 V 2.50 4.30 MHz fDCO(11,3) DCO frequency (11, 3) RSELx = 11, DCOx = 3, MODx = 0 2.2 V/3 V 3.00 5.50 MHz fDCO(12,3) DCO frequency (12, 3) RSELx = 12, DCOx = 3, MODx = 0 2.2 V/3 V 4.30 7.30 MHz fDCO(13,3) DCO frequency (13, 3) RSELx = 13, DCOx = 3, MODx = 0 2.2 V/3 V 6.00 9.60 MHz fDCO(14,3) DCO frequency (14, 3) RSELx = 14, DCOx = 3, MODx = 0 2.2 V/3 V 8.60 13.9 MHz fDCO(15,3) DCO frequency (15, 3) RSELx = 15, DCOx = 3, MODx = 0 3V 12.0 18.5 MHz fDCO(15,7) DCO frequency (15, 7) RSELx = 15, DCOx = 7, MODx = 0 3V 16.0 26.0 MHz SRSEL Frequency step between range RSEL and RSEL+1 SRSEL = fDCO(RSEL+1,DCO)/fDCO(RSEL,DCO) 2.2 V/3 V 1.55 ratio SDCO Frequency step between tap DCO and DCO+1 SDCO = fDCO(RSEL,DCO+1)/fDCO(RSEL,DCO) 2.2 V/3 V 1.05 1.08 1.12 ratio Measured at P1.4/SMCLK 2.2 V/3 V 40 50 60 Duty cycle POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 % 43 MSP430x23x, MSP430x24x(1), MSP430x2410 MIXED SIGNAL MICROCONTROLLER SLAS547A -- JUNE 2007 -- REVISED NOVEMBER 2007 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) calibrated DCO frequencies -- tolerance at calibration PARAMETER TEST CONDITIONS Frequency tolerance at calibration TA VCC MIN TYP MAX UNIT 25°C 3V --1 ±0.2 +1 % 25°C 3V 0.990 1 1.010 MHz fCAL(1MHz) 1-MHz calibration value BCSCTL1= CALBC1_1MHz, DCOCTL = CALDCO_1MHz, Gating time: 5 ms fCAL(8MHz) 8-MHz calibration value BCSCTL1= CALBC1_8MHz, DCOCTL = CALDCO_8MHz, Gating time: 5 ms 25°C 3V 7.920 8 8.080 MHz fCAL(12MHz) 12-MHz calibration value BCSCTL1= CALBC1_12MHz, DCOCTL = CALDCO_12MHz, Gating time: 5 ms 25°C 3V 11.88 12 12.12 MHz fCAL(16MHz) 16-MHz calibration value BCSCTL1= CALBC1_16MHz, DCOCTL = CALDCO_16MHz, Gating time: 2 ms 25°C 3V 15.84 16 16.16 MHz calibrated DCO frequencies -- tolerance over temperature 0°C to 85°C TA VCC MIN TYP MAX UNIT 1-MHz tolerance over temperature PARAMETER 0°C to 85°C 3V --2.5 ±0.5 +2.5 % 8-MHz tolerance over temperature 0°C to 85°C 3V --2.5 ±1.0 +2.5 % 12-MHz tolerance over temperature 0°C to 85°C 3V --2.5 ±1.0 +2.5 % 16-MHz tolerance over temperature 0°C to 85°C % fCAL(1MHz) fCAL(8MHz) fCAL(12MHz) fCAL(16MHz) 44 1-MHz 1 MHz calibration value 8-MHz 8 MHz calibration value 12-MHz 12 MHz calibration value 16 MHz calibration value 16-MHz TEST CONDITIONS BCSCTL1= CALBC1_1MHz, CALBC1 1MHz, DCOCTL = CALDCO_1MHz, Gating time: 5 ms BCSCTL1= CALBC1_8MHz, CALBC1 8MHz, DCOCTL = CALDCO_8MHz, Gating time: 5 ms 0°C 0 C to 85°C 85 C 0°C 0 C to 85°C 85 C BCSCTL1= CALBC1_12MHz, CALBC1 12MHz, DCOCTL = CALDCO_12MHz, Gating time: 5 ms 0°C 0 C to 85°C 85 C BCSCTL1= CALBC1_16MHz, DCOCTL = CALDCO_16MHz, CALDCO 16MHz Gating time: 2 ms 0°C to 85°C POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3V --3.0 ±2.0 +3.0 2.2 V 0.970 1 1.030 3V 0.975 1 1.025 3.6 V 0.970 1 1.030 2.2 V 7.760 8 8.400 3V 7.800 8 8.200 3.6 V 7.600 8 8.240 2.2 V 11.64 12 12.36 3V 11.64 12 12.36 3.6 V 11.64 12 12.36 3V 15.52 16 16.48 3.6 V 15.00 16 16.48 MHz MHz MHz MHz MSP430x23x, MSP430x24x(1), MSP430x2410 MIXED SIGNAL MICROCONTROLLER SLAS547A -- JUNE 2007 -- REVISED NOVEMBER 2007 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) calibrated DCO frequencies -- tolerance over supply voltage VCC PARAMETER TEST CONDITIONS TA VCC MIN TYP MAX UNIT 1-MHz tolerance over VCC 25°C 1.8 V to 3.6 V --3 ±2 +3 % 8-MHz tolerance over VCC 25°C 1.8 V to 3.6 V --3 ±2 +3 % 12-MHz tolerance over VCC 25°C 2.2 V to 3.6 V --3 ±2 +3 % 16-MHz tolerance over VCC 25°C 3 V to 3.6 V --6 ±2 +3 % 25°C 1.8 V to 3.6 V 0.970 1 1.030 MHz fCAL(1MHz) 1-MHz calibration value BCSCTL1= CALBC1_1MHz, DCOCTL = CALDCO_1MHz, Gating time: 5 ms fCAL(8MHz) 8-MHz calibration value BCSCTL1= CALBC1_8MHz, DCOCTL = CALDCO_8MHz, Gating time: 5 ms 25°C 1.8 V to 3.6 V 7.760 8 8.240 MHz fCAL(12MHz) 12-MHz calibration value BCSCTL1= CALBC1_12MHz, DCOCTL = CALDCO_12MHz, Gating time: 5 ms 25°C 2.2 V to 3.6 V 11.64 12 12.36 MHz fCAL(16MHz) 16-MHz calibration value BCSCTL1= CALBC1_16MHz, DCOCTL = CALDCO_16MHz, Gating time: 2 ms 25°C 3 V to 3.6 V 15.00 16 16.48 MHz TA VCC MIN MAX UNIT 1-MHz tolerance overall --40°C to 105°C 1.8 V to 3.6 V --5 ±2 +5 % 8-MHz tolerance overall --40°C to 105°C 1.8 V to 3.6 V --5 ±2 +5 % 12-MHz tolerance overall --40°C to 105°C 2.2 V to 3.6 V --5 ±2 +5 % --6 ±3 +6 % calibrated DCO frequencies -- overall tolerance PARAMETER TEST CONDITIONS 16-MHz tolerance overall TYP --40°C to 105°C 3 V to 3.6 V --40°C to 105°C 1.8 V to 3.6 V 0.950 1 1.050 MHz fCAL(1MHz) 1-MHz calibration value BCSCTL1= CALBC1_1MHz, DCOCTL = CALDCO_1MHz, Gating time: 5 ms fCAL(8MHz) 8-MHz calibration value BCSCTL1= CALBC1_8MHz, DCOCTL = CALDCO_8MHz, Gating time: 5 ms --40°C to 105°C 1.8 V to 3.6 V 7.600 8 8.400 MHz fCAL(12MHz) 12-MHz calibration value BCSCTL1= CALBC1_12MHz, DCOCTL = CALDCO_12MHz, Gating time: 5 ms --40°C to 105°C 2.2 V to 3.6 V 11.40 12 12.60 MHz fCAL(16MHz) 16-MHz calibration value BCSCTL1= CALBC1_16MHz, DCOCTL = CALDCO_16MHz, Gating time: 2 ms --40°C to 105°C 3 V to 3.6 V 15.00 16 17.00 MHz POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 45 MSP430x23x, MSP430x24x(1), MSP430x2410 MIXED SIGNAL MICROCONTROLLER SLAS547A -- JUNE 2007 -- REVISED NOVEMBER 2007 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) typical characteristics -- calibrated 1-MHz DCO frequency 1.04 Frequency -- MHz 1.03 1.02 TA = --40 °C 1.01 TA = 25 °C 1.00 TA = 85 °C TA = 105 °C 0.99 1.5 2.0 2.5 3.0 3.5 4.0 VCC -- Supply Voltage -- V Figure 14. Calibrated 1 MHz Frequency vs. VCC typical characteristics -- calibrated 8-MHz DCO frequency 8.20 8.15 Frequency -- MHz 8.10 TA = --40 °C TA = 85 °C 8.05 8.00 TA = 25 °C 7.95 7.90 7.85 7.80 1.5 TA = 105 °C 2.0 2.5 3.0 VCC -- Supply Voltage -- V 3.5 4.0 Figure 15. Calibrated 8 MHz Frequency vs. VCC 46 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MSP430x23x, MSP430x24x(1), MSP430x2410 MIXED SIGNAL MICROCONTROLLER SLAS547A -- JUNE 2007 -- REVISED NOVEMBER 2007 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) typical characteristics -- calibrated 12-MHz DCO frequency 12.5 Frequency -- MHz 12.3 TA = --40 °C 12.1 TA = 25 °C TA = 85 °C 11.9 TA = 105 °C 11.7 11.5 1.5 2.0 2.5 3.0 3.5 4.0 VCC -- Supply Voltage -- V Figure 16. Calibrated 12-MHz Frequency vs VCC typical characteristics -- calibrated 16-MHz DCO frequency 16.1 Frequency -- MHz 16.0 TA = --40 °C TA = 25 °C 15.9 15.8 TA = 85 °C 15.7 TA = 105 °C 15.6 15.5 1.5 2.0 2.5 3.0 3.5 4.0 VCC -- Supply Voltage -- V Figure 17. Calibrated 16-MHz Frequency vs VCC POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 47 MSP430x23x, MSP430x24x(1), MSP430x2410 MIXED SIGNAL MICROCONTROLLER SLAS547A -- JUNE 2007 -- REVISED NOVEMBER 2007 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) wake-up from lower power modes (LPM3/4) PARAMETER tDCO,LPM3/4 tCPU,LPM3/4 TEST CONDITIONS DCO clock wake--up time from LPM3/4 (see Note 1) VCC MIN TYP MAX BCSCTL1= CALBC1_1MHz, DCOCTL = CALDCO_1MHz 2.2 V/3 V 2 BCSCTL1= CALBC1_8MHz, DCOCTL = CALDCO_8MHz 2.2 V/3 V 1.5 BCSCTL1= CALBC1_12MHz, DCOCTL = CALDCO_12MHz 2.2 V/3 V 1 BCSCTL1= CALBC1_16MHz, DCOCTL = CALDCO_16MHz 3V 1 UNIT μs s CPU wake--up time from LPM3/4 (see Note 2) 1/fMCLK + tClock,LPM3/4 NOTES: 1. The DCO clock wake-up time is measured from the edge of an external wake-up signal (e.g., port interrupt) to the first clock edge observable externally on a clock pin (MCLK or SMCLK). 2. Parameter applicable only if DCOCLK is used for MCLK. typical characteristics -- DCO clock wake-up time from LPM3/4 DCO Wake Time -- μs 10.00 1.00 0.10 0.10 RSELx = 0...11 RSELx = 12...15 1.00 10.00 DCO Frequency -- MHz Figure 18. Clock Wake-Up Time From LPM3 vs DCO Frequency 48 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MSP430x23x, MSP430x24x(1), MSP430x2410 MIXED SIGNAL MICROCONTROLLER SLAS547A -- JUNE 2007 -- REVISED NOVEMBER 2007 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) DCO with external resistor ROSC (see Note 1) PARAMETER TEST CONDITIONS VCC TYP 2.2 V 1.8 3V 1.95 UNIT fDCO,ROSC DCO output frequency with ROSC DCOR = 1, RSELx = 4, 4 DCOx = 3, 3 MODx = 0 0, TA = 25°C Dt Temperature drift DCOR = 1, RSELx = 4, DCOx = 3, MODx = 0 2.2 V/3 V ±0.1 %/°C DV Drift with VCC DCOR = 1, RSELx = 4, DCOx = 3, MODx = 0 2.2 V/3 V 10 %/V MHz NOTE 1. ROSC = 100 kΩ, metal film resistor, type 0257. 0.6 W with 1% tolerance, and TK = ±50 ppm/°C. typical characteristics -- DCO with external resistor ROSC 10.00 DCO Frequency -- MHz DCO Frequency -- MHz 10.00 1.00 0.10 RSELx = 4 0.01 10.00 100.00 1000.00 1.00 0.10 RSELx = 4 0.01 10.00 10000.00 ROSC -- External Resistor -- kΩ 10000.00 Figure 20. DCO Frequency vs ROSC, VCC = 3 V, TA = 25°C 2.50 2.50 ROSC = 100k 2.00 1.75 1.50 1.25 1.00 ROSC = 270k 0.75 0.50 ROSC = 1M 0.25 --25.0 0.0 25.0 50.0 75.0 100.0 2.25 DCO Frequency -- MHz 2.25 DCO Frequency -- MHz 1000.00 ROSC -- External Resistor -- kΩ Figure 19. DCO Frequency vs ROSC, VCC = 2.2 V, TA = 25°C 0.00 --50.0 100.00 ROSC = 100k 2.00 1.75 1.50 1.25 1.00 ROSC = 270k 0.75 0.50 ROSC = 1M 0.25 0.00 2.0 Figure 21. DCO Frequency vs Temperature, VCC = 3 V POST OFFICE BOX 655303 2.5 3.0 3.5 4.0 VCC -- Supply Voltage -- V TA -- Temperature -- °C Figure 22. DCO Frequency vs VCC, TA = 25°C • DALLAS, TEXAS 75265 49 MSP430x23x, MSP430x24x(1), MSP430x2410 MIXED SIGNAL MICROCONTROLLER SLAS547A -- JUNE 2007 -- REVISED NOVEMBER 2007 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) crystal oscillator, LFXT1, low frequency modes (see Note 4) PARAMETER TEST CONDITIONS VCC fLFXT1,LF LFXT1 oscillator crystal frequency, LF mode 0, 1 XTS = 0, LFXT1Sx = 0 or 1 1.8 V to 3.6 V fLFXT1,LF,logic LFXT1 oscillator logic level square wave input frequency, LF mode XTS = 0, LFXT1Sx = 3, XCAPx = 0 1.8 V to 3.6 V Oscillation allowance for LF crystals OALF Integrated effective load capacitance LF mode capacitance, (see Note 1) CL,eff MIN TYP MAX 32,768 10,000 32,768 UNIT Hz 50,000 Hz XTS = 0, LFXT1Sx = 0, fLFXT1,LF = 32,768 kHz, CL,eff = 6 pF 500 kΩ XTS = 0, LFXT1Sx = 0, fLFXT1,LF = 32,768 kHz, CL,eff = 12 pF 200 kΩ XTS = 0, XCAPx = 0 1 pF XTS = 0, XCAPx = 1 5.5 pF XTS = 0, XCAPx = 2 8.5 pF XTS = 0, XCAPx = 3 11 pF Duty cycle LF mode XTS = 0, Measured at P1.4/ACLK, fLFXT1,LF = 32,768 Hz fFault,LF Oscillator fault frequency, LF mode (see Note 3) XTS = 0, LFXT1Sx = 3, XCAPx = 0 (see Notes 2) 2.2 V/3 V 30 2.2 V/3 V 10 50 70 % 10,000 Hz NOTES: 1. Includes parasitic bond and package capacitance (approximately 2 pF per pin). Since the PCB adds additional capacitance it is recommended to verify the correct load by measuring the ACLK frequency. For a correct setup the effective load capacitance should always match the specification of the used crystal. 2. Measured with logic level input frequency but also applies to operation with crystals. 3. Frequencies below the MIN specification will set the fault flag, frequencies above the MAX specification will not set the fault flag. Frequencies in between might set the flag. 4. To improve EMI on the LFXT1 oscillator the following guidelines should be observed. -- Keep the trace between the device and the crystal as short as possible. -- Design a good ground plane around the oscillator pins. -- Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT. -- Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins. ---- Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins. If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins. Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation. This signal is no longer required for the serial programming adapter. 5. Applies only if using an external logic-level clock source. Not applicable when using a crystal or resonator. internal very low power, low frequency oscillator (VLO) PARAMETER TEST CONDITIONS VCC fVLO VLO frequency dfVLO/dT VLO frequency temperature drift See Note 6 2.2 V/3 V 2.2 V/3 V dfVLO/dVCC VLO frequency supply voltage drift See Note 7 1.8 V to 3.6 V MIN 4 TYP MAX 12 20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 kHz 0.5 %/°C 4 %/V NOTES: 6. Calculated using the box method: I version: (MAX(--40 to 85_C) -- MIN(--40 to 85_C))/MIN(--40 to 85_C)/(85_C -- (--40_C)) T version: (MAX(--40 to 105_C) -- MIN(--40 to 105_C))/MIN(--40 to 105_C)/(105_C -- (--40_C)) 7. Calculated using the box method: (MAX(1.8 to 3.6 V) -- MIN(1.8 to 3.6 V))/MIN(1.8 to 3.6 V)/(3.6 V -- 1.8 V) 50 UNIT MSP430x23x, MSP430x24x(1), MSP430x2410 MIXED SIGNAL MICROCONTROLLER SLAS547A -- JUNE 2007 -- REVISED NOVEMBER 2007 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) crystal oscillator, LFXT1, high frequency modes (see Note 5) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT fLFXT1,HF0 LFXT1 oscillator crystal frequency, HF mode 0 XTS = 1, LFXT1Sx = 0, XCAPx = 0 1.8 V to 3.6 V 0.4 1 MHz fLFXT1,HF1 LFXT1 oscillator crystal frequency, HF mode 1 XTS = 1, LFXT1Sx = 1, XCAPx = 0 1.8 V to 3.6 V 1 4 MHz LFXT1 oscillator ill t crystal t l frequency, f HF mode 2 1.8 V to 3.6 V 2 10 fLFXT1,HF2 XTS = 1, LFXT1Sx = 2, XCAPx = 0 2.2 V to 3.6 V 2 12 LFXT1 oscillator ill t logic l i level l l square wave input frequency, frequency HF mode fLFXT1,HF,logic Oscillation Allowance for HF crystals (refer to Figure 23 and Figure 24) OAHF Integrated effective load capacitance, HF mode (see Note NO TAG) CL,eff Duty cycle HF mode Oscillator fault frequency, HF mode (see Note 4) fFault,HF 3 V to 3.6 V XTS = 1, LFXT1Sx = 3, XCAPx = 0 2 16 1.8 V to 3.6 V 0.4 10 2.2 V to 3.6 V 0.4 12 3 V to 3.6 V 0.4 16 XTS = 1, XCAPx = 0, LFXT1Sx = 0, fLFXT1,HF = 1 MHz, CL,eff = 15 pF 2700 XTS = 1, XCAPx = 0, LFXT1Sx = 1 fLFXT1,HF = 4 MHz, CL,eff = 15 pF 800 XTS = 1, XCAPx = 0, LFXT1Sx = 2 fLFXT1,HF = 16 MHz, CL,eff = 15 pF 300 XTS = 1, XCAPx = 0 (see Note 2) XTS = 1, XCAPx = 0, Measured at P1.4/SMCLK, fLFXT1,HF = 10 MHz XTS = 1, XCAPx = 0, Measured at P1.4/SMCLK, fLFXT1,HF = 16 MHz XTS = 1, LFXT1Sx = 3, XCAPx = 0 (see Notes 3) MHz Ω 1 pF 40 50 60 40 50 60 2 2 V/3 V 2.2 2.2 V/3 V MHz % 30 300 kHz NOTES: 1. Includes parasitic bond and package capacitance (approximately 2 pF per pin). Since the PCB adds additional capacitance it is recommended to verify the correct load by measuring the ACLK frequency. For a correct setup the effective load capacitance should always match the specification of the used crystal. 2. Requires external capacitors at both terminals. Values are specified by crystal manufacturers. 3. Measured with logic level input frequency but also applies to operation with crystals. 4. Frequencies below the MIN specification will set the fault flag, frequencies above the MAX specification will not set the fault flag. Frequencies in between might set the flag. 5. To improve EMI on the LFXT1 oscillator the following guidelines should be observed. -- Keep the trace between the device and the crystal as short as possible. -- Design a good ground plane around the oscillator pins. -- Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT. -- Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins. ---- Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins. If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins. Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation. This signal is no longer required for the serial programming adapter. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 51 MSP430x23x, MSP430x24x(1), MSP430x2410 MIXED SIGNAL MICROCONTROLLER SLAS547A -- JUNE 2007 -- REVISED NOVEMBER 2007 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) typical characteristics -- LFXT1 oscillator in HF mode (XTS = 1) Oscillation Allowance -- Ohms 100000.00 10000.00 1000.00 LFXT1Sx = 3 100.00 LFXT1Sx = 1 10.00 0.10 1.00 LFXT1Sx = 2 10.00 100.00 Crystal Frequency -- MHz XT Oscillator Supply Current -- uA Figure 23. Oscillation Allowance vs Crystal Frequency, CL,eff = 15 pF, TA = 25°C 1600.0 1500.0 1400.0 1300.0 1200.0 1100.0 1000.0 900.0 800.0 700.0 600.0 500.0 400.0 300.0 200.0 100.0 0.0 0.0 LFXT1Sx = 3 LFXT1Sx = 2 LFXT1Sx = 1 4.0 8.0 12.0 16.0 20.0 Crystal Frequency -- MHz Figure 24. XT Oscillator Supply Current vs Crystal Frequency, CL,eff = 15 pF, TA = 25°C 52 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MSP430x23x, MSP430x24x(1), MSP430x2410 MIXED SIGNAL MICROCONTROLLER SLAS547A -- JUNE 2007 -- REVISED NOVEMBER 2007 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) crystal oscillator, XT2 (see Note 5) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT fXT2 XT2 oscillator crystal frequency, mode 0 XT2Sx = 0 1.8 V to 3.6 V 0.4 1 MHz fXT2 XT2 oscillator crystal frequency, mode 1 XT2Sx = 1 1.8 V to 3.6 V 1 4 MHz XT2 oscillator ill t crystal t l frequency, f mode 2 1.8 V to 3.6 V 2 10 fXT2 XT2Sx = 2 2.2 V to 3.6 V 2 12 3 V to 3.6 V XT2 oscillator ill t logic l i level l l square wave input frequency fXT2 XT2Sx = 3 Oscillation allowance (see Figure 23 and Figure 24) OA Integrated effective load capacitance, HF mode (see Note 1) CL,eff 16 0.4 10 2.2 V to 3.6 V 0.4 12 3 V to 3.6 V 0.4 16 XT2Sx = 0, fXT2 = 1 MHz, CL,eff = 15 pF 2700 XT2Sx = 1, fXT2 = 4 MHz, CL,eff = 15 pF 800 XT2Sx = 2, fXT1,HF = 16 MHz, CL,eff = 15 pF 300 See Note 2 Duty cycle Measured at P1.4/SMCLK, fXT2 = 16 MHz Oscillator fault frequency, HF mode (see Note 4) XT2Sx = 3 (see Note 3) pF 40 50 60 40 50 60 2 2 V/3 V 2.2 2.2 V/3 V MHz Ω 1 Measured at P1.4/SMCLK, fXT2 = 10 MHz fFault 2 1.8 V to 3.6 V MHz % 30 300 kHz NOTES: 1. Includes parasitic bond and package capacitance (approximately 2 pF per pin). Since the PCB adds additional capacitance it is recommended to verify the correct load by measuring the ACLK frequency. For a correct setup the effective load capacitance should always match the specification of the used crystal. 2. Requires external capacitors at both terminals. Values are specified by crystal manufacturers. 3. Measured with logic level input frequency but also applies to operation with crystals. 4. Frequencies below the MIN specification will set the fault flag, frequencies above the MAX specification will not set the fault flag. Frequencies in between might set the flag. 5. To improve EMI on the LFXT1 oscillator the following guidelines should be observed. -- Keep the trace between the device and the crystal as short as possible. -- Design a good ground plane around the oscillator pins. -- Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT. -- Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins. ---- Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins. If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins. Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation. This signal is no longer required for the serial programming adapter. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 53 MSP430x23x, MSP430x24x(1), MSP430x2410 MIXED SIGNAL MICROCONTROLLER SLAS547A -- JUNE 2007 -- REVISED NOVEMBER 2007 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) typical characteristics -- XT2 oscillator Oscillation Allowance -- Ohms 100000.00 10000.00 1000.00 XT2Sx = 3 100.00 XT2Sx = 2 XT2Sx = 1 10.00 0.10 1.00 10.00 100.00 Crystal Frequency -- MHz XT Oscillator Supply Current -- uA Figure 25. Oscillation Allowance vs Crystal Frequency, CL,eff = 15 pF, TA = 25°C 1600.0 1500.0 1400.0 1300.0 1200.0 1100.0 1000.0 900.0 800.0 700.0 600.0 500.0 400.0 300.0 200.0 100.0 0.0 0.0 XT2Sx = 3 XT2Sx = 2 XT2Sx = 1 4.0 8.0 12.0 16.0 20.0 Crystal Frequency -- MHz Figure 26. XT2 Oscillator Supply Current vs Crystal Frequency, CL,eff = 15 pF, TA = 25°C 54 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MSP430x23x, MSP430x24x(1), MSP430x2410 MIXED SIGNAL MICROCONTROLLER SLAS547A -- JUNE 2007 -- REVISED NOVEMBER 2007 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) Timer_A PARAMETER TEST CONDITIONS fTA Timer A clock frequency Timer_A Internal: SMCLK, ACLK, External: TACLK, TACLK INCLK INCLK, Duty cycle = 50% ± 10% tTA,cap Timer_A, capture timing TA0, TA1, TA2 VCC MIN MAX 2.2 V 7.5 3.3 V 16 2.2 V/3 V 20 UNIT MHz ns Timer_B PARAMETER TEST CONDITIONS fTB Timer B clock frequency Timer_B Internal: SMCLK, ACLK, External: TBCLK TBCLK, Duty cycle = 50% ± 10% tTB,cap Timer_B, capture timing TBx POST OFFICE BOX 655303 VCC MAX 7.5 3.3 V 16 2.2 V/3 V • DALLAS, TEXAS 75265 MIN 2.2 V 20 UNIT MHz ns 55 MSP430x23x, MSP430x24x(1), MSP430x2410 MIXED SIGNAL MICROCONTROLLER SLAS547A -- JUNE 2007 -- REVISED NOVEMBER 2007 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) USCI (UART mode) PARAMETER fUSCI USCI input clock frequency fBITCLK BITCLK clock frequency (equals Baudrate in MBaud) tτ UART receive deglitch time (see Note 1) TEST CONDITIONS VCC MIN TYP Internal: SMCLK, ACLK External: UCLK Duty cycle = 50% ± 10% 2.2V /3 V MAX UNIT fSYSTEM MHz 1 MHz 2.2 V 50 150 600 3V 50 100 600 ns NOTE 1. Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are correctly recognized their width should exceed the maximum specification of the deglitch time. USCI (SPI master mode) (see Figure 27 and Figure 28) PARAMETER fUSCI USCI input clock frequency tSU,MI SOMI input data setup time tHD,MI SOMI input data hold time tVALID,MO SIMO output data valid time TEST CONDITIONS VCC MIN SMCLK, ACLK Duty cycle = 50% ± 10% 2.2 V 110 3V 75 MAX UNIT fSYSTEM MHz ns 2.2 V ns 3V UCLK edge to SIMO valid; CL = 20 pF 2.2 V 30 3V 20 ns 1 with t LO∕HI ≥ max(t VALID,MO(USCI) + t SU,SI(Slave), t SU,MI(USCI) + t VALID,SO(Slave)). 2t LO∕HI For the slave’s parameters tSU,SI(Slave) and tVALID,SO(Slave), see the SPI parameters of the attached slave. NOTE: f UCxCLK = USCI (SPI slave mode) (see Figure 29 and Figure 30) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT tSTE,LEAD STE lead time STE low to clock 2.2 V/3 V tSTE,LAG STE lag time Last clock to STE high 2.2 V/3 V tSTE,ACC STE access time STE low to SOMI data out 2.2 V/3 V 50 ns tSTE,DIS STE disable time STE high to SOMI high impedance 2.2 V/3 V 50 ns tSU,SI SIMO input inp t data setup set p time tHD,SI SIMO inp inputt data hold time tVALID,SO SOMI o output tp t data valid alid time UCLK edge to SOMI valid; CL = 20 pF 50 10 2.2 V 20 3V 15 2.2 V 10 3V 10 ns ns ns 2.2 V 75 110 3V 50 75 1 with t LO∕HI ≥ max(t VALID,MO(Master) + t SU,SI(USCI), t SU,MI(Master) + t VALID,SO(USCI)). 2t LO∕HI For the master’s parameters tSU,MI(Master) and tVALID,MO(Master) refer to the SPI parameters of the attached master. NOTE: f UCxCLK = 56 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 ns ns MSP430x23x, MSP430x24x(1), MSP430x2410 MIXED SIGNAL MICROCONTROLLER SLAS547A -- JUNE 2007 -- REVISED NOVEMBER 2007 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) 1/fUCxCLK CKPL=0 UCLK CKPL=1 tLO/HI tLO/HI tSU,MI tHD,MI SOMI tVALID,MO SIMO Figure 27. SPI Master Mode, CKPH = 0 1/fUCxCLK CKPL=0 UCLK CKPL=1 tLO/HI tLO/HI tSU,MI tHD,MI SOMI tVALID,MO SIMO Figure 28. SPI Master Mode, CKPH = 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 57 MSP430x23x, MSP430x24x(1), MSP430x2410 MIXED SIGNAL MICROCONTROLLER SLAS547A -- JUNE 2007 -- REVISED NOVEMBER 2007 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) tSTE,LEAD tSTE,LAG STE 1/fUCxCLK CKPL=0 UCLK CKPL=1 tLO/HI tLO/HI tSU,SI tHD,SI SIMO tSTE,ACC tVALID,SO tSTE,DIS SOMI Figure 29. SPI Slave Mode, CKPH = 0 tSTE,LEAD tSTE,LAG STE 1/fUCxCLK CKPL=0 UCLK CKPL=1 tLO/HI tLO/HI tSU,SI tHD,SI SIMO tSTE,ACC tVALID,SO SOMI Figure 30. SPI Slave Mode, CKPH = 1 58 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 tSTE,DIS MSP430x23x, MSP430x24x(1), MSP430x2410 MIXED SIGNAL MICROCONTROLLER SLAS547A -- JUNE 2007 -- REVISED NOVEMBER 2007 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) USCI (I2C mode) (see Figure 31) PARAMETER fUSCI USCI input clock frequency fSCL SCL clock frequency TEST CONDITIONS VCC MIN TYP Internal: SMCLK, ACLK External: UCLK Duty cycle = 50% ± 10% 2.2 V/3 V fSCL ≤ 100kHz 0 MAX UNIT fSYSTEM MHz 400 kHz 4.0 tHD,STA Hold time (repeated) START 2 2 V/3 V 2.2 tSU,STA Set p time for a repeated START Setup tHD,DAT Data hold time 2.2 V/3 V 0 tSU,DAT Data setup time 2.2 V/3 V 250 ns tSU,STO Setup time for STOP 2.2 V/3 V 4.0 μs tSP Pulse width of spikes suppressed by input filter 2.2 V 50 150 600 3V 50 100 600 fSCL > 100kHz fSCL ≤ 100kHz tHD,STA 4.7 2 2 V/3 V 2.2 fSCL > 100kHz μs s 0.6 μs s 0.6 ns ns tSU,STA tHD,STA SDA 1/fSCL tSP SCL tSU,DAT tSU,STO tHD,DAT Figure 31. I2C Mode Timing POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 59 MSP430x23x, MSP430x24x(1), MSP430x2410 MIXED SIGNAL MICROCONTROLLER SLAS547A -- JUNE 2007 -- REVISED NOVEMBER 2007 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) Comparator_A+ (see Note 1) PARAMETER TEST CONDITIONS I(DD) CAON = 1, 1 CARSEL = 0 0, CAREF = 0 I(Refladder/Refdiode) CAON = 1, CARSEL = 0, CAREF = 1/2/3, 1/2/3 no load at P2.3/CA0/TA1 and P2.4/CA1/TA2 V(IC) V(Ref025) V(Ref050) Common-mode input voltage Voltage @ 0.25 V V node CC CC Voltage @ 0.5V V CC node CC VCC MIN TYP MAX 2.2 V 25 40 3V 45 60 2.2 V 30 50 3V 45 71 CAON = 1 2.2 V/3 V 0 VCC --1 PCA0 = 1, CARSEL = 1, CAREF = 1, no load at P2.3/CA0/TA1 and P2.4/CA1/TA2 2.2 V/3 V 0.23 0.24 0.25 PCA0 = 1, CARSEL = 1, CAREF = 2, no load at P2.3/CA0/TA1 and P2.4/CA1/TA2 2.2 V/3 V 0.47 0.48 0.5 2.2 V 390 480 540 3V 400 490 550 --30 V(RefVT) (see Figure 35 and Figure 36) PCA0 = 1, CARSEL = 1, CAREF = 3, no load at P2.3/CA0/TA1 P2 3/CA0/TA1 and P2.4/CA1/TA2 TA = 85°C V(offset) Offset voltage See Note 2 2.2 V/3 V Vhys Input hysteresis CAON = 1 2.2 V/3 V 0 TA = 25 25°C, C, Overdrive 10 mV, Without filter: CAF=0 2.2 V 80 3V 70 120 240 TA = 25 25°C, C, Overdrive 10 mV, With filter: CAF = 1 2.2 V 1.4 1.9 2.8 3V 0.9 1.5 2.2 t(response) Low to high and high to low (see Note 3) UNIT μA μA V mV 30 mV 0.7 1.4 mV 165 300 ns μs NOTES: 1. The leakage current for the Comparator_A terminals is identical to Ilkg(Px.x) specification. 2. The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A inputs on successive measurements. The two successive measurements are then summed together. 3. The response time is measured at P2.2/CAOUT/TA0/CA4 with an input voltage step, with Comparator_A+ already enabled (CAON = 1). If CAON is set at the same time, a settling time of up to 300 ns is added to the response time. 60 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MSP430x23x, MSP430x24x(1), MSP430x2410 MIXED SIGNAL MICROCONTROLLER SLAS547A -- JUNE 2007 -- REVISED NOVEMBER 2007 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) 0V 0 VCC 1 CAF CAON To Internal Modules Low Pass Filter + _ V+ V-- 0 0 1 1 CAOUT Set CAIFG Flag τ ≈ 2.0 μs Figure 32. Block Diagram of Comparator_A Module VCAOUT Overdrive V-400 mV t(response) V+ Figure 33. Overdrive Definition CASHORT CA0 CA1 1 VIN + -- IOUT = 10μA Comparator_A+ CASHORT = 1 Figure 34. Comparator_A+ Short Resistance Test Condition POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 61 MSP430x23x, MSP430x24x(1), MSP430x2410 MIXED SIGNAL MICROCONTROLLER SLAS547A -- JUNE 2007 -- REVISED NOVEMBER 2007 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) 650 650 VCC = 2.2 V 600 V(REFVT) -- Reference Volts --mV V(REFVT) -- Reference Volts --mV VCC = 3 V Typical 550 500 450 400 --45 --25 --5 15 35 55 75 600 Typical 550 500 450 400 --45 95 --25 --5 15 TA -- Free-Air Temperature -- °C Short Resistance -- kOhms 100.00 VCC = 1.8 V VCC = 2.2V VCC = 3 V VCC = 3.6 V 1.00 0.0 0.2 0.4 0.6 0.8 VIN/VCC -- Normalized Input Voltage -- V/V 1.0 Figure 37. Short Resistance vs VIN/VCC 62 55 75 95 Figure 36. V(RefVT) vs Temperature, VCC = 2.2 V Figure 35. V(RefVT) vs Temperature, VCC = 3 V 10.00 35 TA -- Free-Air Temperature -- °C POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MSP430x23x, MSP430x24x(1), MSP430x2410 MIXED SIGNAL MICROCONTROLLER SLAS547A -- JUNE 2007 -- REVISED NOVEMBER 2007 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) 12-bit ADC, power supply and input range conditions PARAMETER TEST CONDITIONS AVCC Analog supply voltage AVCC and DVCC are connected together AVSS and DVSS are connected together V(AVSS) = V(DVSS) = 0 V V(P6.x/Ax) Analog input voltage range (see Note 2) All P6.0/A0 to P6.7/A7 terminals. Analog inputs selected in ADC12MCTLx register, P6Sel.x = 1, 0 ≤ x ≤ 7, V(AVSS) ≤ VP6.x/Ax ≤ V(AVCC) IADC12 Operating supply current into AVCC terminal (see Note 3) fADC12CLK = 5 MHz, ADC12ON = 1, REFON = 0 0, SHT0 = 0, 0 SHT1 = 0, 0 ADC12DIV = 0 IREF+ Operating p g supply pp y current i into AVCC terminal i l (see Note 4) fADC12CLK = 5 MHz, ADC12ON = 0, REFON = 1, REF2_5V = 1 fADC12CLK = 5 MHz, ADC12ON = 0, REFON = 1, REF2_5V = 0 CI † Input capacitance Only one terminal can be selected at one time, P6.x/Ax RI† Input MUX ON resistance 0V ≤ VAx ≤ VAVCC VCC MIN TYP MAX UNIT 2.2 3.6 V 0 VAVCC V 2.2 V 0.65 0.8 3V 0.8 1.0 3V 0.5 0.7 2.2 V 0.5 0.7 3V 0.5 0.7 2.2 V 3V mA mA mA 40 pF 2000 Ω † Not production tested, limits verified by design NOTES: 1. The leakage current is defined in the leakage current table with P6.x/Ax parameter. 2. The analog input voltage range must be within the selected reference voltage range VR+ to VR-- for valid conversion results. 3. The internal reference supply current is not included in current consumption parameter IADC12. 4. The internal reference current is supplied via terminal AVCC. Consumption is independent of the ADC12ON control bit, unless a conversion is active. The REFON bit enables to settle the built-in reference before starting an A/D conversion. 12-bit ADC, external reference (see Note 1) PARAMETER MIN MAX UNIT VeREF+ > VREF-- /VeREF-- (see Note 2) 1.4 VAVCC V Negative external reference voltage input VeREF+ > VREF-- /VeREF-- (see Note 3) 0 1.2 V (VeREF+ -VREF--/VeREF-- ) Differential external reference voltage input VeREF+ > VREF-- /VeREF-- (see Note 4) 1.4 VAVCC V IVeREF+ Static input current 0V ≤ VeREF+ ≤ VAVCC 2.2 V/3 V ±1 μA IVREF--/VeREF-- Static input current 0V ≤ VeREF-- ≤ VAVCC 2.2 V/3 V ±1 μA VeREF+ Positive external reference voltage input VREF-- /VeREF-- TEST CONDITIONS VCC NOTES: 1. The external reference is used during conversion to charge and discharge the capacitance array. The input capacitance, Ci, is also the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy. 2. The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced accuracy requirements. 3. The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced accuracy requirements. 4. The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with reduced accuracy requirements. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 63 MSP430x23x, MSP430x24x(1), MSP430x2410 MIXED SIGNAL MICROCONTROLLER SLAS547A -- JUNE 2007 -- REVISED NOVEMBER 2007 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) 12-bit ADC, built-in reference PARAMETER VREF+ AVCC(min) IVREF+ IL(VREF)+ † Positive built-in reference voltage output AVCC minimum voltage, Positive built-in built in reference active TEST CONDITIONS TA VCC MIN TYP REF2_5V = 1 (2.5 V), IVREF+max ≤ IVREF+≤ IVREF+min --40°C to 85°C 105°C REF2_5V = 0 (1.5 V), IVREF+max ≤ IVREF+≤ IVREF+min 3V 2.4 2.5 2.6 3V 2.37 2.5 2.64 --40°C to 85°C 2.2 V/3 V 1.44 1.5 1.56 105°C 2.2V / 3 V 1.42 1.5 1.57 REF2_5V = 0, IVREF+max ≤ IVREF+≤ IVREF+min 2.2 REF2_5V = 1, --0.5mA ≤ IVREF+≤ IVREF+min 2.8 REF2_5V = 1, --1mA ≤ IVREF+≤ IVREF+min 2.9 Load current out of VREF+ terminal Load-current regulation VREF+ terminal IVREF+ = 500 μA ± 100 μA Analog input voltage ~0.75 0 75 V; REF2_5V = 0 MAX 0.01 --0.5 3V 0.01 --1 2.2 V ±2 3V ±2 IVREF+ = 500 μA ± 100 μA, Analog input voltage ~1.25 V, REF2_5V = 1 3V ±2 3V 20 Load current regulation VREF+ terminal IVREF+ =100 μA → 900 μA, CVREF+=5 5 μF, F ax ~0.5 0 5 × VREF+ Error of conversion result ≤ 1 LSB CVREF+ Capacitance at pin VREF+ (see Note 1) REFON =1, 0 mA ≤ IVREF+ ≤ IVREF+max 2.2 V/3 V TREF+† Temperature coefficient of built-in reference IVREF+ is a constant in the range of 0 mA ≤ IVREF+ ≤ 1 mA 2.2 V/3 V tREFON† Settle time of internal reference voltage (see Figure 38 and Note 2) IVREF+ = 0.5 mA, CVREF+ = 10 μF, VREF+ = 1.5 V, VAVCC = 2.2 V † 5 V V 2.2 V IDL(VREF) +‡ UNIT 10 mA LSB ns μF ±100 17 ppm/°C ms Not production tested, limits characterized Not production tested, limits verified by design NOTES: 1. The internal buffer operational amplifier and the accuracy specifications require an external capacitor. All INL and DNL tests uses two capacitors between pins VREF+ and AVSS and VREF-- /VeREF-- and AVSS: 10-μF tantalum and 100-nF ceramic. 2. The condition is that the error in a conversion started after tREFON is less than ±0.5 LSB. The settling time depends on the external capacitive load. ‡ 64 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MSP430x23x, MSP430x24x(1), MSP430x2410 MIXED SIGNAL MICROCONTROLLER SLAS547A -- JUNE 2007 -- REVISED NOVEMBER 2007 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) CVREF+ 100 μF tREFON ≈ .66 x CVREF+ [ms] with CVREF+ in μF 10 μF 1 μF 0 1 ms 10 ms 100 ms tREFON Figure 38. Typical Settling Time of Internal Reference tREFON vs External Capacitor on VREF+ POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 65 MSP430x23x, MSP430x24x(1), MSP430x2410 MIXED SIGNAL MICROCONTROLLER SLAS547A -- JUNE 2007 -- REVISED NOVEMBER 2007 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) From Power Supply DVCC + -10 μ F 100 nF AVCC + -10 μ F Apply External Reference [VeREF+] or Use Internal Reference [VREF+] 100 nF 10 μ F MSP430F261x MSP430F241x 100 nF VREF --/VeREF-- + -10 μ F AVSS VREF+ or VeREF+ + -- Apply External Reference DVSS 100 nF Figure 39. Supply Voltage and Reference Voltage Design VREF--/VeREF-- External Supply From Power Supply DVCC + -10 μ F 100 nF AVCC + -10 μ F Apply External Reference [VeREF+] or Use Internal Reference [VREF+] 100 nF AVSS MSP430F261x MSP430F241x VREF+ or VeREF+ + -10 μ F DVSS 100 nF Reference Is Internally Switched to AVSS VREF-- /VeREF-- Figure 40. Supply Voltage and Reference Voltage Design VREF--/VeREF-- = AVSS, Internally Connected 66 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MSP430x23x, MSP430x24x(1), MSP430x2410 MIXED SIGNAL MICROCONTROLLER SLAS547A -- JUNE 2007 -- REVISED NOVEMBER 2007 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) 12-bit ADC, timing parameters PARAMETER fADC12CLK fADC12OSC Internal ADC12 oscillator TEST CONDITIONS VCC MIN TYP MAX UNIT For specified performance of ADC12 linearity parameters 2.2V/3 V 0.45 5 6.3 MHz ADC12DIV=0, fADC12CLK=fADC12OSC 2.2 V/ 3 V 3.7 5 6.3 MHz CVREF+ ≥ 5 μF, Internal oscillator, fADC12OSC = 3.7 MHz to 6.3 MHz 2.2 V/ 3 V 2.06 tCONVERT Conversion time tADC12ON† Turn-on settling time of the ADC See Note 1 tSample† Sampling time RS = 400 Ω, RI = 1000 Ω, CI = 30 pF τ = [RS + RI] × CI;(see Note 2) External fADC12CLK from ACLK, MCLK, or SMCLK: ADC12SSEL ≠ 0 3.51 μs s 13 × ADC12DIV × 1 /fADC12CLK 100 3V 1220 2.2 V 1400 ns ns † Limits verified by design NOTES: 1. The condition is that the error in a conversion started after tADC12ON is less than ±0.5 LSB. The reference and input signal are already settled. 2. Approximately ten Tau (τ) are needed to get an error of less than ±0.5 LSB: tSample = ln(2n+1) x (RS + RI) x CI+ 800 ns where n = ADC resolution = 12, RS = external source resistance. 12-bit ADC, linearity parameters PARAMETER TEST CONDITIONS 1.4 V ≤ (VeREF+ -- VREF-- /VeREF-- ) min ≤ 1.6 V VCC EI Integral linearit linearity error ED Differential linearity error EO Offset error (VeREF+ -- VREF-- /VeREF-- )min ≤ (VeREF+ -- VREF-- /VeREF-- ), Internal impedance of source RS < 100 Ω, CVREF+ = 10 μF (tantalum) and 100 nF (ceramic) 2.2 V/3 V EG Gain error (VeREF+ -- VREF-- /VeREF-- )min ≤ (VeREF+ -- VREF-- /VeREF-- ), CVREF+ = 10 μF (tantalum) and 100 nF (ceramic) ET Total unadjusted error (VeREF+ -- VREF-- /VeREF-- )min ≤ (VeREF+ -- VREF-- /VeREF-- ), CVREF+ = 10 μF (tantalum) and 100 nF (ceramic) 1.6 V < (VeREF+ -- VREF-- /VeREF-- ) min ≤ [VAVCC] (VeREF+ -- VREF-- /VeREF-- )min ≤ (VeREF+ -- VREF-- /VeREF-- ), CVREF+ = 10 μF (tantalum) and 100 nF (ceramic) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MIN TYP MAX ±2 2 2 V/3 V 2.2 ±1.7 2.2 V/3 V UNIT LSB ±1 LSB ±2 ±4 LSB 2.2 V/3 V ±1.1 ±2 LSB 2.2 V/3 V ±2 ±5 LSB 67 MSP430x23x, MSP430x24x(1), MSP430x2410 MIXED SIGNAL MICROCONTROLLER SLAS547A -- JUNE 2007 -- REVISED NOVEMBER 2007 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) 12-bit ADC, temperature sensor and built-in VMID PARAMETER TEST CONDITIONS VCC MIN TYP MAX ISENSOR Operating supply current into AVCC terminal (see Note 1) REFON = 0, INCH = 0Ah, ADC12ON = 1, TA = 25_C 2.2 V 40 120 3V 60 160 VSENSOR† See Note 2 ADC12ON = 1, INCH = 0Ah, TA = 0°C 2.2 V 986 3V 986 2.2 V 3.55 3.55±3% 3V 3.55 3.55±3% TCSENSOR† ADC12ON = 1 1, INCH = 0Ah 2.2 V 30 3V 30 UNIT μA A mV tSENSOR(sample)† Sample time required if channel 10 is selected (see Note 3) ADC12ON = 1, INCH = 0Ah, Error of conversion result ≤ 1 LSB IVMID Current into divider at channel 11 (see Note 4) ADC12ON = 1 1, INCH = 0Bh 0Bh, VMID AVCC divider di ider at channel 11 ADC12ON = 1, INCH = 0Bh, VMID is ~0.5 × VAVCC 2.2 V 1.1 1.1±0.04 3V 1.5 1.50±0.04 tVMID(sample) Sample time required if channel 11 is selected (see Note 5) ADC12ON = 1, INCH = 0Bh, Error of conversion result ≤ 1 LSB 2.2 V 1400 3V 1220 mV/°C μs s 2.2 V NA 3V NA μA A V ns † Limits characterized NOTES: 1. The sensor current ISENSOR is consumed if (ADC12ON = 1 and REFON=1) or (ADC12ON=1 and INCH = 0Ah and sample signal is high). When REFON = 1, ISENSOR is already included in IREF+. 2. The temperature sensor offset can be as much as ±20_C. A single-point calibration is recommended in order to minimize the offset error of the built-in temperature sensor. 3. The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time tSENSOR(on). 4. No additional current is needed. The VMID is used during sampling. 5. The on-time tVMID(on) is included in the sampling time tVMID(sample); no additional on time is needed. 68 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MSP430x23x, MSP430x24x(1), MSP430x2410 MIXED SIGNAL MICROCONTROLLER SLAS547A -- JUNE 2007 -- REVISED NOVEMBER 2007 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) flash memory TEST CONDITIONS PARAMETER VCC(PGM/ VCC MIN TYP MAX UNIT ERASE) Program and erase supply voltage 2.2 3.6 V fFTG Flash timing generator frequency 257 476 kHz IPGM Supply current from DVCC during program 2.7 V/ 3.6 V 3 5 mA IERASE Supply current from DVCC during erase 2.7 V/ 3.6 V 3 7 mA tCPT Cumulative program time See Note 1 2.7 V/ 3.6 V 4 ms tCMErase Cumulative mass erase time See Note 2 2.7 V/ 3.6 V 200 104 Program/erase endurance TJ = 25°C ms 105 tRetention Data retention duration tWord Word or byte program time 35 tBlock, 0 Block program time for first byte or word 30 tBlock, 1-63 Block program time for each additional byte or word tBlock, End Block program end-sequence wait time tMass Erase Mass erase time (see Note 4) tSeg Erase Segment erase time cycles 100 years 21 See Note 3 tFTG 6 10593 4819 NOTES: 1. The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming methods: individual word/byte write and block write modes. 2. The mass erase duration generated by the flash timing generator is at least 11.1ms ( = 5297×1/fFTG,max = 5297×1/476kHz). To achieve the required cumulative mass erase time the Flash Controller’s mass erase operation can be repeated until this time is met. (A worst case minimum of 19 cycles are required). 3. These values are hardwired into the Flash Controller’s state machine (tFTG = 1/fFTG). 4. To erase the complete code area the mass erase has to be performed once with a dummy address in the range of the lower 64kB Flash addresses and once with the dummy address in the upper 64kB Flash addresses. RAM PARAMETER VRAMh TEST CONDITIONS See Note 1 MIN CPU halted MAX 1.6 UNIT V NOTE 1. This parameter defines the minimum supply voltage when the data in program memory RAM remain unchanged. No program execution should take place during this supply voltage condition. JTAG interface TEST CONDITIONS PARAMETER fTCK TCK input frequency See Note 1 RInternal Internal pullup resistance on TMS, TCK, TDI/TCLK See Note 2 VCC MIN TYP 2.2 V 0 5 3V 0 10 2.2 V/ 3 V 25 60 MAX 90 UNIT MHz kΩ NOTES: 1. fTCK may be restricted to meet the timing requirements of the module selected. 2. TMS, TDI/TCLK, and TCK pullup resistors are implemented in all versions. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 69 MSP430x23x, MSP430x24x(1), MSP430x2410 MIXED SIGNAL MICROCONTROLLER SLAS547A -- JUNE 2007 -- REVISED NOVEMBER 2007 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) JTAG fuse (see Note 1) PARAMETER TEST CONDITIONS VCC(FB) Supply voltage during fuse-blow condition VFB Voltage level on TDI/TCLK for fuse blow: F versions IFB Supply current into TDI/TCLK during fuse blow tFB Time to blow fuse TA = 25°C MIN MAX 2.5 6 UNIT V 7 V 100 mA 1 ms NOTE 1. Once the fuse is blown, no further access to the MSP430 JTAG/Test and emulation features is possible. The JTAG block is switched to bypass mode. 70 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MSP430x23x, MSP430x24x(1), MSP430x2410 MIXED SIGNAL MICROCONTROLLER SLAS547A -- JUNE 2007 -- REVISED NOVEMBER 2007 APPLICATION INFORMATION Port P1 pin schematic: P1.0 to P1.7, input/output with Schmitt trigger Pad Logic P1REN.x P1DIR.x 0 0 Module X OUT 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 P1OUT.x DVSS P1.0/TACLK P1.1/TA0 P1.2/TA1 P1.3/TA2 P1.4/SMCLK P1.5/TA0 P1.6/TA1 P1.7/TA2 P1SEL.x P1IN.x EN Module X IN D P1IE.x P1IRQ.x EN Q Set P1IFG.x P1SEL.x P1IES.x Interrupt Edge Select POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 71 MSP430x23x, MSP430x24x(1), MSP430x2410 MIXED SIGNAL MICROCONTROLLER SLAS547A -- JUNE 2007 -- REVISED NOVEMBER 2007 Port P1.0 to P1.7 pin functions PIN NAME (P1.X) (P1 X) P1.0/TACLK / X 0 FUNCTION P1.0 (I/O) Timer_A3.TACLK CAOUT P1.1/TA0 / P1.2/TA1 / P1.3/TA2 / 1 2 3 P1.4/SMCLK / 4 P1.5/TA0 / 5 P1.7/TA2 / 72 6 7 P1DIR.x P1SEL.x I: 0; O: 1 0 0 1 1 1 I: 0; O: 1 0 Timer_A3.CCI0A 0 1 Timer_A3.TA0 1 1 I: 0; O: 1 0 Timer_A3.CCI0A 0 1 Timer_A3.TA0 1 1 I: 0; O: 1 0 Timer_A3.CCI0A 0 1 Timer_A3.TA0 1 1 I: 0; O: 1 0 P1.1 (I/O) P1.2 (I/O) P1.3 (I/O) P1.4 (I/O) SMCLK P1.6/TA1 / CONTROL BITS / SIGNALS 1 1 I: 0; O: 1 0 Timer_A3.CCI0A 0 1 Timer_A3.TA0 1 1 I: 0; O: 1 0 Timer_A3.CCI0A 0 1 Timer_A3.TA1 1 1 I: 0; O: 1 0 Timer_A3.CCI0A 0 1 Timer_A3.TA2 1 1 P1.5 (I/O) P1.6 (I/O) P1.7 (I/O) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MSP430x23x, MSP430x24x(1), MSP430x2410 MIXED SIGNAL MICROCONTROLLER SLAS547A -- JUNE 2007 -- REVISED NOVEMBER 2007 Port P2 pin schematic: P2.0 to P2.4, P2.6, and P2.7, input/output with Schmitt trigger Pad Logic To Comparator_A From Comparator_A CAPD.x P2REN.x P2DIR.x 0 0 Module X OUT 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 P2OUT.x DVSS Bus Keeper EN P2SEL.x P2IN.x EN Module X IN P2.0/ACLK/CA2 P2.1/TAINCLK/CA3 P2.2/CAOUT/TA0/CA4 P2.3/CA0/TA1 P2.4/CA1/TA2 P2.6/ADC12CLK/CA6 P2.7/TA0/CA7 D P2IE.x P2IRQ.x EN Q Set P2IFG.x P2SEL.x P2IES.x Interrupt Edge Select POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 73 MSP430x23x, MSP430x24x(1), MSP430x2410 MIXED SIGNAL MICROCONTROLLER SLAS547A -- JUNE 2007 -- REVISED NOVEMBER 2007 Port P2.0 to P2.4, P2.6, and P2.7 pin functions PIN NAME (P2.X) (P2 X) P2.0/ACLK/CA2 / / P2.1/TAINCLK/CA3 / / P2.2/CAOUT/TA0/ / / / CA4 P2.3/CA0/TA1 / / P2.4/CA1/TA2 / / P2.6/ADC12CLK†/ / †/ CA6 P2.7/TA0/CA7 / / X 0 1 2 3 4 6 7 CONTROL BITS / SIGNALS FUNCTION CAPD.x P2DIR.x P2SEL.x P2.0 (I/O) 0 I: 0; O: 1 0 ACLK 0 1 1 CA2 1 X X P2.1 (I/O) 0 I: 0; O: 1 0 Timer_A3.INCLK 0 0 1 DVSS 0 1 1 CA3 1 X X P2.2 (I/O) 0 I: 0; O: 1 0 CAOUT 0 1 1 TA0 0 0 1 CA4 1 X X P2.3 (I/O) 0 I: 0; O: 1 0 Timer_A3.TA1 0 1 1 CA0 1 X X P2.4 (I/O) 0 I: 0; O: 1 0 Timer_A3.TA2 0 1 X CA1 1 X 1 P2.6 (I/O) 0 I: 0; O: 1 0 ADC12CLK† 0 1 1 CA6 1 X X P2.7 (I/O) 0 I: 0; O: 1 0 Timer_A3.TA0 0 1 1 CA7 1 X X † MSP430F24x and MSP430F23x devices only NOTE: X: Don’t care. 74 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MSP430x23x, MSP430x24x(1), MSP430x2410 MIXED SIGNAL MICROCONTROLLER SLAS547A -- JUNE 2007 -- REVISED NOVEMBER 2007 Port P2 pin schematic: P2.5, input/output with Schmitt trigger Pad Logic To Comparator From Comparator CAPD.5 To DCO in DCO DCOR P2REN.5 P2DIR.5 0 0 Module X OUT 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 P2OUT.5 DVSS P2.5/ROSC/CA5 Bus Keeper EN P2SEL.5 P2IN.5 EN Module X IN D P2IE.5 P2IRQ.5 EN Q Set P2IFG.5 P2SEL.5 P2IES.5 Interrupt Edge Select Port P2.5 pin functions PIN NAME (P2.X) (P2 X) P2.5/R / OSC//CA5 X 5 FUNCTION CONTROL BITS / SIGNALS CAPD DCOR P2DIR.5 P2SEL.5 P2.5 (I/O) 0 0 I: 0; O: 1 0 ROSC 0 1 X X DVSS 0 0 1 1 CA5 1 or selected 0 X X NOTE: X: Don’t care. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 75 MSP430x23x, MSP430x24x(1), MSP430x2410 MIXED SIGNAL MICROCONTROLLER SLAS547A -- JUNE 2007 -- REVISED NOVEMBER 2007 Port P3 pin schematic: P3.0 to P3.7, input/output with Schmitt trigger Pad Logic P3REN.x P3DIR.x Module direction P3OUT.x Module X OUT 0 DVSS 0 DVCC 1 1 Direction 0: Input 1: Output 1 0 1 P3.0/UCB0STE/UCA0CLK P3.1/UCB0SIMO/UCB0SDA P3.2/UCB0SOMI/UCB0SCL P3.3/UCB0CLK/UCA0STE P3.4/UCA0TXD/UCA0SIMO P3.5/UCA0RXD/UCA0SOMI P3.6/UCA1TXD/UCA1SIMO P3.7/UCA1RXD/UCA1SOMI P3SEL.x P3IN.x EN Module X IN D Port P3.0 to P3.7 pin functions PIN NAME (P3.X) (P3 X) X P3.0/UCB0STE/ / / UCA0CLK 0 P3.1/UCB0SIMO/ / / UCB0SDA 1 P3.2/UCB0SOMI/ / / UCB0SCL 2 P3.3/UCB0CLK/ / / UCA0STE 3 P3.4/UCA0TXD/ / / UCA0SIMO 4 P3.5/UCA0RXD/ / / UCA0SOMI 5 †/ P3.6/UCA1TXD / 6 UCA1SIMO† †/ P3.7/UCA1RXD / UCA1SOMI† FUNCTION P3.0 (I/O) UCB0STE/UCA0CLK (see Notes 2 and 4) P3.1 (I/O) UCB0SIMO/UCB0SDA (see Notes 2 and 3) P3.2 (I/O) UCB0SOMI/UCB0SCL (see Notes 2 and 3) P3.3 (I/O) UCB0CLK/UCA0STE (see Note 2) P3.4 (I/O) UCA0TXD/UCA0SIMO (see Note 2) P3.5 (I/O) UCA0RXD/UCA0SOMI (see Note 2) P3.6 (I/O) UCA1TXD†/UCA1SIMO† (see Note 2) 7 P3.7 (I/O) UCA1RXD†/UCA1SOMI† (see Note 2) † CONTROL BITS / SIGNALS P3DIR.x P3SEL.x I: 0; O: 1 0 X 1 I: 0; O: 1 0 X 1 I: 0; O: 1 0 X 1 I: 0; O: 1 0 X 1 I: 0; O: 1 0 X 1 I: 0; O: 1 0 X 1 I: 0; O: 1 0 X 1 I: 0; O: 1 0 X 1 MSP430F24x and MSP430F24x1 devices only NOTES: 1. X: Don’t care. 2. The pin direction is controlled by the USCI module. 3. In case the I2C functionality is selected the output drives only the logical 0 to VSS level. 4. UCA0CLK function takes precedence over UCB0STE function. If the pin is required as UCA0CLK input or output USCI A/B0 will be forced to 3--wire SPI mode if 4--wire SPI mode is selected. 76 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MSP430x23x, MSP430x24x(1), MSP430x2410 MIXED SIGNAL MICROCONTROLLER SLAS547A -- JUNE 2007 -- REVISED NOVEMBER 2007 Port P4 pin schematic: P4.0 to P4.7, input/output with Schmitt trigger Pad Logic P4REN.x P4DIR.x 0 0 Module X OUT 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 P4OUT.x DVSS P4.0/TB0 P4.1/TB1 P4.2/TB2 P4.3/TB3 P4.4/TB4 P4.5/TB5 P4.6/TB6 P4.7/TBCLK P4SEL.x P4IN.x EN Module X IN D Port P4.0 to P4.7 pin functions PIN NAME (P4.X) (P4 X) P4.0/TB0 / P4.1/TB1 / X 0 1 FUNCTION P4.0 (I/O) 0 0 1 Timer_B7.TB0 1 1 I: 0; O: 1 0 0 1 P4.1 (I/O) P4.2 (I/O) Timer_B7.CCI2A and Timer_B7.CCI2B Timer_B7.TB2 † P4.3/TB3 / 3 P4.3 (I/O) Timer_B7.CCI3A and Timer_B7.CCI3B† Timer_B7.TB3† † P4.4/TB4 / 4 P4.4 (I/O) Timer_B7.CCI4A and Timer_B7.CCI4B† Timer_B7.TB4† † P4.5/TB5 / 5 P4.5 (I/O) Timer_B7.CCI5A and Timer_B7.CCI5B† Timer_B7.TB5† † P4.6/TB6 / 6 P4.6 (I/O) Timer_B7.CCI6A and Timer_B7.CCI6B† Timer_B7.TB6† P4.7/TBCLK / 7 P4.7 (I/O) Timer_B7.TBCLK † P4SEL.x I: 0; O: 1 Timer_B7.TB1 2 P4DIR.x Timer_B7.CCI0A and Timer_B7.CCI0B Timer_B7.CCI1A and Timer_B7.CCI1B P4.2/TB2 / CONTROL BITS / SIGNALS 1 1 I: 0; O: 1 0 0 1 1 1 I: 0; O: 1 0 0 1 1 1 I: 0; O: 1 0 0 1 1 1 I: 0; O: 1 0 0 1 1 1 I: 0; O: 1 0 0 1 1 1 I: 0; O: 1 0 0 1 MSP430F24x and MSP430F24x1 devices only POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 77 MSP430x23x, MSP430x24x(1), MSP430x2410 MIXED SIGNAL MICROCONTROLLER SLAS547A -- JUNE 2007 -- REVISED NOVEMBER 2007 Port P5 pin schematic: P5.0 to P5.3, input/output with Schmitt trigger Pad Logic P5REN.x P5DIR.x 0 Module Direction 1 P5OUT.x 0 Module X OUT DVSS 0 DVCC 1 1 Direction 0: Input 1: Output 1 P5.0/UCB1STE/UCA1CLK P5.1/UCB1SIMO/UCB1SDA P5.2/UCB1SOMI/UCB1SCL P5.3/UCB1CLK/UCA1STE P5SEL.x P5IN.x EN Module X IN D Port P5.0 to P5.3 pin functions PIN NAME (P5.X) (P5 X) †/ P5.0/UCB1STE / UCA1CLK† X 0 FUNCTION P5.0 (I/O) UCB1STE†/UCA1CLK† (see Notes 2 and 4) †/ P5.1/UCB1SIMO / UCB1SDA† 1 †/ P5.2/UCB1SOMI / UCB1SCL† 2 †/ P5.3/UCB1CLK / UCA1STE† 3 P5.1 (I/O) UCB1SIMO†/UCB1SDA† (see Notes 2 and 3) P5.2 (I/O) UCB1SOMI†/UCB1SCL† (see Notes 2 and 3) P5.3 (I/O) UCB1CLK†/UCA1STE† (see Note 2) †† CONTROL BITS / SIGNALS P5DIR.x P5SEL.x I: 0; O: 1 0 X 1 I: 0; O: 1 0 X 1 I: 0; O: 1 0 X 1 I: 0; O: 1 0 X 1 MSP430F24x and MSP430F24x1 devices only NOTES: 1. X: Don’t care. 2. The pin direction is controlled by the USCI module. 3. In case the I2C functionality is selected the output drives only the logical 0 to VSS level. 4. UCA01CLK function takes precedence over UCB1STE function. If the pin is required as UCA1CLK input or output USCI A/B1 will be forced to 3--wire SPI mode if 4--wire SPI mode is selected. 78 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MSP430x23x, MSP430x24x(1), MSP430x2410 MIXED SIGNAL MICROCONTROLLER SLAS547A -- JUNE 2007 -- REVISED NOVEMBER 2007 Port P5 pin schematic: P5.4 to P5.7, input/output with Schmitt trigger Pad Logic P5REN.x P5DIR.x 0 Module X OUT 0 DVCC 1 1 Direction 0: Input 1: Output 1 P5OUT.x DVSS 0 1 P5.4/MCLK P5.5/SMCLK P5.6/ACLK P5.7/TBOUTH/SVSOUT P5SEL.x P5IN.x EN Module X IN D Port P5.4 to P5.7 pin functions PIN NAME (P5.X) (P5 X) P5.4/MCLK / X 4 FUNCTION P5.4 (I/O) MCLK P5.5/SMCLK / 5 P5.6/ACLK / 6 P5.7/TBOUTH/ / / SVSOUT 7 P5.5 (I/O) SMCLK P5.6 (I/O) ACLK CONTROL BITS / SIGNALS P5DIR.x P5SEL.x I: 0; O: 1 0 1 1 I: 0; O: 1 0 1 1 I: 0; O: 1 0 1 1 I: 0; O: 1 0 Timer_B7.TBOUTH 0 1 SVSOUT 1 1 P5.7 (I/O) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 79 MSP430x23x, MSP430x24x(1), MSP430x2410 MIXED SIGNAL MICROCONTROLLER SLAS547A -- JUNE 2007 -- REVISED NOVEMBER 2007 Port P6 pin schematic: P6.0 to P6.6, input/output with Schmitt trigger Pad Logic ADC12 Ax from ADC12 P6REN.x P6DIR.x 0 0 Module X OUT 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 P6OUT.x DVSS P6.0/A0 P6.1/A1 P6.2/A2 P6.3/A3 P6.4/A4 P6.5/A5 P6.6/A6 Bus Keeper EN P6SEL.x P6IN.x EN Module X IN D Port P6.0 to P6.6 pin functions PIN NAME (P6.X) (P6 X) P6.0/A0 / † X 0 CONTROL BITS / SIGNALS FUNCTION P5.0 (I/O) A0† P6.1/A1 / † 1 P5.1 (I/O) A1† P6.2/A2 / † 2 P5.2 (I/O) A2† P6.3/A3 / † 3 P5.3 (I/O) A3† P6.4/A4 / † 4 P5.4 (I/O) A4† P6.5/A5 / † 5 P5.5 (I/O) A5† P6.6/A6 / † 6 P6.6 (I/O) A6† † MSP430F24x and MSP430F23x devices only 80 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 P6DIR.x P6SEL.x CAPD.x I: 0; O: 1 0 0 X X 1 I: 0; O: 1 0 0 X X 1 I: 0; O: 1 0 0 X X 1 I: 0; O: 1 0 0 X X 1 I: 0; O: 1 0 0 X X 1 I: 0; O: 1 0 0 X X 1 I: 0; O: 1 0 0 X X 1 MSP430x23x, MSP430x24x(1), MSP430x2410 MIXED SIGNAL MICROCONTROLLER SLAS547A -- JUNE 2007 -- REVISED NOVEMBER 2007 Port P6 pin schematic: P6.7, input/output with Schmitt trigger Pad Logic to SVS Mux VLD = 15 ADC12 A7 from ADC12 P6REN.7 P6DIR.7 0 0 Module X OUT 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 P6OUT.7 DVSS P6.7/A7/SVSIN Bus Keeper EN P6SEL.7 P6IN.7 EN Module X IN D Port P6.7 pin functions PIN NAME (P6.X) (P6 X) P6.7/A7/SVSIN / / X 7 CONTROL BITS / SIGNALS FUNCTION P6.7 (I/O) P6DIR.x P6SEL.x CAPD.x I: 0; O: 1 0 0 DVSS 1 1 0 A7 X X 1 SVSIN (VLD = 15) X X 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 81 MSP430x23x, MSP430x24x(1), MSP430x2410 MIXED SIGNAL MICROCONTROLLER SLAS547A -- JUNE 2007 -- REVISED NOVEMBER 2007 APPLICATION INFORMATION JTAG pins (TMS, TCK, TDI/TCLK, TDO/TDI), input/output with Schmitt trigger TDO Controlled by JTAG Controlled by JTAG JTAG TDO/TDI Controlled by JTAG DVCC DVCC TDI Fuse Burn & Test Fuse Test TDI/TCLK and DVCC Emulation Module TMS TMS DVCC During Programming Activity and During Blowing of the Fuse, Pin TDO/TDI Is Used to Apply the Test Input Data for JTAG Circuitry TCK TCK 82 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MSP430x23x, MSP430x24x(1), MSP430x2410 MIXED SIGNAL MICROCONTROLLER SLAS547A -- JUNE 2007 -- REVISED NOVEMBER 2007 APPLICATION INFORMATION JTAG fuse check mode MSP430 devices that have the fuse on the TDI/TCLK terminal have a fuse check mode that tests the continuity of the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check current, ITF, of 1 mA at 3 V, 2.5 mA at 5 V can flow from the TDI/TCLK pin to ground if the fuse is not burned. Care must be taken to avoid accidentally activating the fuse check mode and increasing overall system power consumption. Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if the TMS is being held low during power up. The second positive edge on the TMS pin deactivates the fuse check mode. After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR the fuse check mode has the potential to be activated. The fuse check current will only flow when the fuse check mode is active and the TMS pin is in a low state (see Figure 41). Therefore, the additional current flow can be prevented by holding the TMS pin high (default condition). Time TMS Goes Low After POR TMS ITDI/TCLK ITF Figure 41. Fuse Check Mode Current POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 83 MSP430x23x, MSP430x24x(1), MSP430x2410 MIXED SIGNAL MICROCONTROLLER SLAS547A -- JUNE 2007 -- REVISED NOVEMBER 2007 Data Sheet Revision History LITERATURE NUMBER SLAS547 SLAS547A 84 SUMMARY Product Preview release Production Data release POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 31-Jan-2008 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty MSP430F233TPM ACTIVE LQFP PM 64 160 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR MSP430F233TPMR ACTIVE LQFP PM 64 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR MSP430F233TRGC PREVIEW QFN RGC 64 250 MSP430F233TRGCR ACTIVE QFN RGC 64 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR MSP430F233TRGCT ACTIVE QFN RGC 64 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR MSP430F235TPM ACTIVE LQFP PM 64 160 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR MSP430F235TPMR ACTIVE LQFP PM 64 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TBD TBD Lead/Ball Finish Call TI Call TI MSP430F235TRGC PREVIEW QFN RGC 64 250 MSP430F235TRGCR ACTIVE QFN RGC 64 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR MSP430F235TRGCT ACTIVE QFN RGC 64 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR MSP430F2410TPM ACTIVE LQFP PM 64 160 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR MSP430F2410TPMR ACTIVE LQFP PM 64 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TBD Call TI MSL Peak Temp (3) MSP430F2410TRGC PREVIEW QFN RGC 64 250 MSP430F2410TRGCR ACTIVE QFN RGC 64 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR MSP430F2410TRGCT ACTIVE QFN RGC 64 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR MSP430F2471TPM ACTIVE LQFP PM 64 160 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR MSP430F2471TPMR ACTIVE LQFP PM 64 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TBD Call TI Call TI MSP430F2471TRGC PREVIEW QFN RGC 64 250 MSP430F2471TRGCR ACTIVE QFN RGC 64 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR MSP430F2471TRGCT ACTIVE QFN RGC 64 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR MSP430F247TPM ACTIVE LQFP PM 64 160 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR MSP430F247TPMR ACTIVE LQFP PM 64 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR Call TI Call TI MSP430F247TRGC PREVIEW QFN RGC 64 250 MSP430F247TRGCR ACTIVE QFN RGC 64 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR MSP430F247TRGCT ACTIVE QFN RGC 64 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR MSP430F2481TPM ACTIVE LQFP PM 64 160 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR MSP430F2481TPMR ACTIVE LQFP PM 64 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR Addendum-Page 1 TBD Call TI Call TI Call TI PACKAGE OPTION ADDENDUM www.ti.com 31-Jan-2008 Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TBD Lead/Ball Finish MSP430F2481TRGC PREVIEW QFN RGC 64 250 MSP430F2481TRGCR ACTIVE QFN RGC 64 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR MSP430F2481TRGCT ACTIVE QFN RGC 64 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR MSP430F248TPM ACTIVE LQFP PM 64 160 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR MSP430F248TPMR ACTIVE LQFP PM 64 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TBD Call TI MSL Peak Temp (3) MSP430F248TRGC PREVIEW QFN RGC 64 250 MSP430F248TRGCR ACTIVE QFN RGC 64 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR MSP430F248TRGCT ACTIVE QFN RGC 64 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR MSP430F2491TPM ACTIVE LQFP PM 64 160 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR MSP430F2491TPMR ACTIVE LQFP PM 64 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TBD Call TI Call TI MSP430F2491TRGC PREVIEW QFN RGC 64 250 MSP430F2491TRGCR ACTIVE QFN RGC 64 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR MSP430F2491TRGCT ACTIVE QFN RGC 64 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR MSP430F249TPM ACTIVE LQFP PM 64 160 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR MSP430F249TPMR ACTIVE LQFP PM 64 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TBD Call TI Call TI MSP430F249TRGC PREVIEW QFN RGC 64 250 MSP430F249TRGCR ACTIVE QFN RGC 64 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR MSP430F249TRGCT ACTIVE QFN RGC 64 250 CU NIPDAU Level-3-260C-168 HR Green (RoHS & no Sb/Br) Call TI Call TI Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder Addendum-Page 2 PACKAGE OPTION ADDENDUM www.ti.com 31-Jan-2008 temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 3 MECHANICAL DATA MTQF008A – JANUARY 1995 – REVISED DECEMBER 1996 PM (S-PQFP-G64) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 0,08 M 33 48 49 32 64 17 0,13 NOM 1 16 7,50 TYP Gage Plane 10,20 SQ 9,80 12,20 SQ 11,80 0,25 0,05 MIN 0°– 7° 0,75 0,45 1,45 1,35 Seating Plane 0,08 1,60 MAX 4040152 / C 11/96 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Falls within JEDEC MS-026 May also be thermally enhanced plastic with leads connected to the die pads. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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