MICRON MT48V8M16LFFF

ADVANCE‡
128Mb: x16, x32
MOBILE SDRAM
SYNCHRONOUS
DRAM
MT48LC8M16LFFF, MT48V8M16LFFF – 2 Meg x 16 x 4 banks
MT48LC4M32LFFC , MT48V4M32LFFC – 1 Meg x 32 x 4 banks
For the latest data sheet revisions, please refer to the Micron Web
site: www.micron.com/dramds
FEATURES
• Temperature Compensated Self Refresh (TCSR)
• Fully synchronous; all signals registered on positive
edge of system clock
• Internal pipelined operation; column address can be
changed every clock cycle
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto Precharge, includes CONCURRENT AUTO
PRECHARGE, and Auto Refresh Modes
• Self Refresh Mode; standard and low power
• 64ms, 4,096-cycle refresh
• LVTTL-compatible inputs and outputs
• Low voltage power supply
• Partial Array Self Refresh power-saving mode
• Operating Temperature Range
Industrial (-40oC to +85oC)
OPTIONS
PIN ASSIGNMENT (Top View)
54-Ball VFBGA
MARKING
• VDD/VDDQ
3.3V/3.3V
2.5V/2.5V or 1.8V
• Configurations
8 Meg x 16 (2 Meg x 16 x 4 banks)
4 Meg x 32 (1 Meg x 32 x 4 banks)
• Package/Ball out
Plastic Package
54-ball FBGA (8mm x 9mm)(x16 only)
90-ball FBGA (11mm x 13mm)
• Timing (Cycle Time)
8ns @ CL = 3 (125 MHz)
10ns @ CL = 3 (100 MHz)
LC
V
1
2
3
7
8
9
A
VSS
DQ15
VSSQ
VDDQ
DQ0
VDD
B
DQ14
DQ13
VDDQ
VSSQ
DQ2
DQ1
C
DQ12
DQ11
VSSQ
VDDQ
DQ4
DQ3
D
DQ10
DQ9
VDDQ
VSSQ
DQ6
DQ5
E
DQ8
NC
VSS
VDD
LDQM
DQ7
F
UDQM
CLK
CKE
CAS#
RAS#
WE#
G
NC/A12
A11
A9
BA0
BA1
CS#
H
A8
A7
A6
A0
A1
A10
J
VSS
A5
A4
A3
A2
VDD
8M16
4M32
4
5
6
Top View
(Ball Down)
FF1
FC 1
Configuration
Refresh Count
Row Addressing
Bank Addressing
Column Addressing
-8
-10
Part Number Example:
8 Meg x 16
4 Meg x 32
2 Meg x 16 x 4 banks 1 Meg x 32 x 4 banks
4K
4K
4K (A0–A11)
4K (A0–A11)
4 (BA0, BA1)
4 (BA0, BA1)
512 (A0–A8)
256 (A0–A7)
KEY TIMING PARAMETERS
MT48V8M16LFFC-8
NOTE: 1. See page 61 for FBGA/VFBGA Device Marking
Table.
SPEED
CLOCK
ACCESS TIME
GRADE FREQUENCY CL=1* CL=2* CL=3*
–
–
–
–
7ns
7ns
tRCD
tRP
20ns
20ns
20ns
20ns
-8
-10
125 MHz
100 MHz
-8
100 MHz
–
8ns
–
20ns
20ns
-10
83 MHz
–
8ns
–
20ns
20ns
-8
50 MHz
19ns
–
–
20ns
20ns
-10
40 MHz
22ns
–
–
20ns
20ns
*CL = CAS (READ) latency
128Mb: x16, x32 Mobile SDRAM
MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02
‡
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PUROPOSES ONLY AND ARE SUBJECT TO CHANGE BY
MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON'S PRODUCTION AND DATA SHEET SPECIFICATIONS.
ADVANCE
128Mb: x16, x32
MOBILE SDRAM
90-Ball FBGA PIN ASSIGNMENT
(Top View)
1
2
3
DQ26
DQ24
DQ28
4
5
6
7
8
9
VSS
VDD
DQ23
DQ21
VDDQ
VSSQ
VDDQ
VSSQ
DQ19
VSSQ
DQ27
DQ25
DQ22
DQ20
VDDQ
VSSQ
DQ29
DQ30
DQ17
DQ18
VDDQ
VDDQ
DQ31
NC
NC
DQ16
VSSQ
VSS
DQM3
A3
A2
DQM2
VDD
A4
A5
A6
A10
A0
A1
A7
A8
NC
NC
BA1
A11
CLK
CKE
A9
BA0
CS#
RAS#
DQM1
NC
NC
CAS#
WE#
DQM0
VDDQ
DQ8
VSS
VDD
DQ7
VSSQ
VSSQ
DQ10
DQ9
DQ6
DQ5
VDDQ
VSSQ
DQ12
DQ14
DQ1
DQ3
VDDQ
DQ11
VDDQ
VSSQ
VDDQ
VSSQ
DQ4
DQ13
DQ15
VSS
VDD
DQ0
DQ2
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
Ball and Array
128Mb: x16, x32 Mobile SDRAM
MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
ADVANCE
128Mb: x16, x32
MOBILE SDRAM
128Mb SDRAM PART NUMBERS
PART NUMBER
VDD/V DDQ
ARCHITECTURE
PACKAGE
MT48LC8M16LFFF-xx
3.3V / 3.3V
8 Meg x 16
54-BALL VFBGA
MT48V8M16LFFF-xx
2.5V / 2.5V-1.8V
8 Meg x 16
54-BALL VFBGA
MT48LC4M32LFFC-xx
3.3V / 3.3V
4 Meg x 32
90-BALL FBGA
MT48V4M32LFFC-xx
2.5V / 2.5V-1.8V
4 Meg x 32
90-BALL FBGA
GENERAL DESCRIPTION
The Micron® 128Mb SDRAM is a high-speed CMOS,
dynamic random-access memory containing 134,217,728
bits. It is internally configured as a quad-bank DRAM
with a synchronous interface (all signals are registered on
the positive edge of the clock signal, CLK). Each of the
x16’s 33,554,432-bit banks is organized as 4,096 rows by
512 columns by 16 bits. Each of the x32’s 33,554,432-bit
banks is organized as 4,096 rows by 256 columns by 32
bits.
Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue
for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or
WRITE command. The address bits registered coincident with the ACTIVE command are used to select the
bank and row to be accessed (BA0, BA1 select the bank;
A0-A11 select the row). The address bits registered coincident with the READ or WRITE command are used to
select the starting column location for the burst access.
The SDRAM provides for programmable READ or
WRITE burst lengths of 1, 2, 4, or 8 locations, or the full
page, with a burst terminate option. An auto precharge
function may be enabled to provide a self-timed row
128Mb: x16, x32 Mobile SDRAM
MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02
precharge that is initiated at the end of the burst sequence.
The 128Mb SDRAM uses an internal pipelined
architecture to achieve high-speed operation. This
architecture is compatible with the 2n rule of prefetch
architectures, but it also allows the column address to be
changed on every clock cycle to achieve a high-speed,
fully random access. Precharging one bank while accessing one of the other three banks will hide the precharge
cycles and provide seamless high-speed, random-access
operation.
The 128Mb SDRAM is designed to operate in 3.3V or
2.5V, low-power memory systems. An auto refresh mode
is provided, along with a power-saving, power-down
mode. All inputs and outputs are LVTTL-compatible.
SDRAMs offer substantial advances in DRAM operating performance, including the ability to synchronously
burst data at a high data rate with automatic columnaddress generation, the ability to interleave between internal banks in order to hide precharge time and the
capability to randomly change column addresses on each
clock cycle during a burst access.
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
ADVANCE
128Mb: x16, x32
MOBILE SDRAM
TABLE OF CONTENTS
Functional Block Diagram – 8 Meg x 16 ................
Functional Block Diagram – 4 Meg x 32 ................
54-Ball Pin Descriptions .........................................
90-Ball Pin Descriptions .........................................
5
6
7
8
Functional Description .........................................
Initialization ......................................................
Register Definition ............................................
mode register ................................................
Burst Length ............................................
Burst Type ...............................................
CAS Latency ............................................
Operating Mode ......................................
Extended Mode Register .........................
Temperature Compensated Self Refresh .
Partial Array Self Refresh .........................
Commands .............................................................
Truth Table 1 (Commands and DQM Operation) ............
Command Inhibit .............................................
No Operation (NOP) ..........................................
Load mode register ............................................
Active ................................................................
Read ................................................................
Write ................................................................
Precharge ...........................................................
Auto Precharge ..................................................
Burst Terminate .................................................
Auto Refresh ......................................................
Self Refresh ........................................................
Operation ................................................................
Bank/Row Activation ........................................
Reads ................................................................
Writes ................................................................
Precharge ...........................................................
Concurrent Auto Precharge ..............................
Power-Down ......................................................
Clock Suspend ...................................................
Burst Read/Single Write ....................................
9
9
9
9
9
10
11
11
12
12
13
14
14
15
15
15
15
15
15
15
15
15
16
16
17
17
18
24
26
28
26
27
27
128Mb: x16, x32 Mobile SDRAM
MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02
Truth Table 2 (CKE) ................................................
Truth Table 3 (Current State, Same Bank) .....................
Truth Table 4 (Current State, Different Bank) .................
30
31
33
Absolute Maximum Ratings ................................... 35
DC Electrical Characteristics
and Operating Conditions ................................... 35
AC Electrical Characteristics and Recommended
Operating Conditions (Timing Table) .............
AC Functional Characteristics ................................
IDD Specifications and Conditions .........................
Capacitance ............................................................
Timing Waveforms
Initialize and Load mode register ......................
Power-Down Mode ............................................
Clock Suspend Mode .........................................
Auto Refresh Mode ............................................
Self Refresh Mode ..............................................
Reads
Read – Without Auto Precharge ...................
Read – With Auto Precharge ........................
Single Read – Without Auto Precharge ........
Single Read – With Auto Precharge .............
Alternating Bank Read Accesses ...................
Read – Full-Page Burst ..................................
Read – DQM Operation ................................
Writes
Write – Without Auto Precharge .................
Write – With Auto Precharge .......................
Single Write – Without Auto Precharge .......
Single Write – With Auto Precharge ............
Alternating Bank Write Accesses .................
Write – Full-Page Burst .................................
Write – DQM Operation ..............................
54-Ball VFBGA Drawing ...............................
90-Ball FBGA Drawing .................................
FBGA/VFBGA Device Marking .....................
4
36
37
37
38
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
ADVANCE
128Mb: x16, x32
MOBILE SDRAM
FUNCTIONAL BLOCK DIAGRAM
8 Meg x16 SDRAM
BA1
0
0
1
1
CKE
BA0
0
1
0
1
Bank
0
1
2
3
CLK
COMMAND
DECODE
CS#
WE#
CAS#
RAS#
CONTROL
LOGIC
BANK3
BANK2
BANK1
MODE REGISTER
REFRESH 12
COUNTER
12
ROWADDRESS
MUX
12
12
BANK0
ROWADDRESS
LATCH
&
DECODER
4096
BANK0
MEMORY
ARRAY
(4,096 x 512 x 16)
2
DQML,
DQMH
SENSE AMPLIFIERS
16
4096
14
ADDRESS
REGISTER
2
DATA
OUTPUT
REGISTER
I/O GATING
DQM MASK LOGIC
READ DATA LATCH
WRITE DRIVERS
2
A0-A11,
BA0, BA1
2
BANK
CONTROL
LOGIC
16
16
512
(x16)
DQ0DQ15
DATA
INPUT
REGISTER
COLUMN
DECODER
9
128Mb: x16, x32 Mobile SDRAM
MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02
COLUMNADDRESS
COUNTER/
LATCH
9
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
ADVANCE
128Mb: x16, x32
MOBILE SDRAM
FUNCTIONAL BLOCK DIAGRAM
4 Meg x 32 SDRAM
BA1
0
0
1
1
CKE
BA0
0
1
0
1
Bank
0
1
2
3
CLK
COMMAND
DECODE
CS#
WE#
CAS#
RAS#
CONTROL
LOGIC
BANK3
BANK2
BANK1
BANK0
MODE REGISTER
REFRESH 12
COUNTER
12
ROWADDRESS
MUX
12
12
BANK0
ROWADDRESS
LATCH
&
DECODER
4096
BANK0
MEMORY
ARRAY
(4,096 x 256 x 32)
4
DQM0–
DQM3
SENSE AMPLIFIERS
32
8192
14
ADDRESS
REGISTER
2
DATA
OUTPUT
REGISTER
I/O GATING
DQM MASK LOGIC
READ DATA LATCH
WRITE DRIVERS
2
A0–A11,
BA0, BA1
4
BANK
CONTROL
LOGIC
32
32
256
(x32)
DQ0–
DQ31
DATA
INPUT
REGISTER
COLUMN
DECODER
8
128Mb: x16, x32 Mobile SDRAM
MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02
COLUMNADDRESS
COUNTER/
LATCH
8
6
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
ADVANCE
128Mb: x16, x32
MOBILE SDRAM
BALL DESCRIPTIONS
54-BALL VFBGA
SYMBOL
TYPE
F2
CLK
Input
Clock: CLK is driven by the system clock. All SDRAM input signals are sampled
on the positive edge of CLK. CLK also increments the internal burst counter
and controls the output registers.
DESCRIPTION
F3
CKE
Input
Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal.
Deactivating the clock provides PRECHARGE POWER-DOWN and SELF REFRESH
operation (all banks idle), ACTIVE POWER-DOWN (row active in any bank) or
CLOCK SUSPEND operation (burst/access in progress). CKE is synchronous
except after the device enters power-down and self refresh modes, where
CKE becomes asynchronous until after exiting the same mode. The input
buffers, including CLK, are disabled during power-down and self refresh
modes, providing low standby power. CKE may be tied HIGH.
G9
CS#
Input
Chip Select: CS# enables (registered LOW) and disables (registered HIGH) the
command decoder. All commands are masked when CS# is registered HIGH.
CS# provides for external bank selection on systems with multiple banks. CS#
is considered part of the command code.
F7, F8, F9
CAS#, RAS#,
WE#
Input
Command Inputs: CAS#, RAS#, and WE# (along with CS#) define the
command being entered.
E8, F1
LDQM,
UDQM
Input
Input/Output Mask: DQM is sampled HIGH and is an input mask signal for
write accesses and an output enable signal for read accesses. Input data is
masked during a WRITE cycle. The output buffers are placed in a High-Z state
(two-clock latency) when during a READ cycle. LDQM corresponds to DQ0–
DQ7, UDQM corresponds to DQ8–DQ15. LDQM and UDQM are considered
same state when referenced as DQM.
G7, G8
BA0, BA1
Input
Bank Address Input(s): BA0 and BA1 define to which bank the ACTIVE, READ,
WRITE or PRECHARGE command is being applied. These pins also provide the
op-code during a LOAD MODE REGISTER command
H7, H8, J8, J7, J3, J2,
H3, H2, H1, G3, H9, G2,
A0–A11
Input
Address Inputs: A0–A11 are sampled during the ACTIVE command (rowaddress A0–A11) and READ/WRITE command (column-address A0–A8; with
A10 defining auto precharge) to select one location out of the memory array
in the respective bank. A10 is sampled during a PRECHARGE command to
determine if all banks are to be precharged (A10 HIGH) or bank selected by
BA0, BA1 (LOW). The address inputs also provide the op-code during a LOAD
MODE REGISTER command.
A8, B9, B8, C9, C8, D9,
D8, E9, E1, D2, D1, C2,
C1, B2, B1, A2
DQ0–DQ15
I/O
E2, G1
NC
–
Data Input/Output: Data bus
No Connect: These pins should be left unconnected.
G1 is a no connect for this part but may be used as A12 in future designs.
A7, B3, C7, D3
VDDQ
Supply
DQ Power: Isolated power on the die to improve noise immunity.
A3, B7, C3, D7,
VSSQ
Supply
DQ Ground: Isolated power on the die to improve noise immunity.
A9, E7, J9
VDD
Supply
Power Supply: Voltage dependant on option.
A1, E3, J1
VSS
Supply
Ground.
128Mb: x16, x32 Mobile SDRAM
MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02
7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
ADVANCE
128Mb: x16, x32
MOBILE SDRAM
BALL DESCRIPTIONS
90-BALL FBGA
SYMBOL
TYPE
J1
CLK
Input
Clock: CLK is driven by the system clock. All SDRAM input signals are sampled
on the positive edge of CLK. CLK also increments the internal burst counter
and controls the output registers.
J2
CKE
Input
Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal.
Deactivating the clock provides PRECHARGE POWER-DOWN and SELF REFRESH
operation (all banks idle), ACTIVE POWER-DOWN (row active in any bank) or
CLOCK SUSPEND operation (burst/access in progress). CKE is synchronous
except after the device enters power-down and self refresh modes, where
CKE becomes asynchronous until after exiting the same mode. The input
buffers, including CLK, are disabled during power-down and self refresh
modes, providing low standby power. CKE may be tied HIGH.
J8
CS#
Input
Chip Select: CS# enables (registered LOW) and disables (registered HIGH) the
command decoder. All commands are masked when CS# is registered HIGH.
CS# provides for external bank selection on systems with multiple banks. CS#
is considered part of the command code.
J9, K7, K8
RAS#, CAS#
WE#
Input
Command Inputs: RAS#, CAS#, and WE# (along with CS#) define the
command being entered.
K9, K1, F8, F2
DQM0–3
Input
Input/Output Mask: DQM is sampled HIGH and is an input mask signal for
write accesses and an output enable signal for read accesses. Input data is
masked during a WRITE cycle. The output buffers are placed in a High-Z state
(two-clock latency) when during a READ cycle. DQM0 corresponds to DQ0–
DQ7, DQM1 corresponds to DQ8–DQ15, DQM2 corresponds to DQ16–DQ23
and DQM3 corresponds to DQ24–DQ31. DQM0-3 are considered same state
when referenced as DQM.
J7, H8
BA0, BA1
Input
Bank Address Input(s): BA0 and BA1 define to which bank the ACTIVE, READ,
WRITE or PRECHARGE command is being applied. These pins also provide the
op-code during a LOAD MODE REGISTER command
G8, G9, F7, F3, G1, G2,
G3, H1, H2, J3, G7, H9
A0–A11
Input
Address Inputs: A0–A11 are sampled during the ACTIVE command (rowaddress A0–A11) and READ/WRITE command (column-address A0–A7; with
A10 defining auto precharge) to select one location out of the memory array
in the respective bank. A10 is sampled during a PRECHARGE command to
determine if all banks are to be precharged (A10 HIGH) or bank selected by
BA0, BA1 (LOW). The address inputs also provide the op-code during a LOAD
MODE REGISTER command.
R8, N7, R9, N8, P9, M8,
M7, L8, L2, M3, M2, P1, N2,
R1, N3, R2, E8, D7, D8, B9,
C8, A9, C7, A8, A2, C3, A1,
C2, B1, D2, D3, E2
DQ0–DQ31
I/O
E3, E7, H3, H7, K2, K3
NC
–
B2, B7, C9, D9, E1,
L1, M9, N9, P2, P7
VDDQ
Supply
DQ Power: Isolated power on the die to improve noise immunity.
B8, B3, C1, D1, E9,
L9, M1, N1, P3, P8
VSSQ
Supply
DQ Ground: Isolated power on the die to improve noise immunity.
A7, F9, L7, R7
VDD
Supply
Power Supply: Voltage dependant on option.
A3, F1, L3, R3
VSS
Supply
Ground.
128Mb: x16, x32 Mobile SDRAM
MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02
DESCRIPTION
Data Input/Output: Data bus
No Connect: These pins should be left unconnected.
H7 and H9 are not connects for this part but may be used as A12 and A11 in
future designs.
8
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
ADVANCE
128Mb: x16, x32
MOBILE SDRAM
FUNCTIONAL DESCRIPTION
Register Definition
In general, the 128Mb SDRAMs (2 Meg x16 x 4 banks
and 1 Meg x 32 x 4 banks) are quad-bank DRAMs that
operate at 3.3V or 2.5V and include a synchronous interface (all signals are registered on the positive edge of the
clock signal, CLK). Each of the x16’s 33,554,432-bit banks
is organized as 4,096 rows by 512 columns by 16 bits.
Each of the x32’s 33,554,432-bit banks is organized as
4,096 rows by 256 columns by 32bits.
Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue
for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or
WRITE command. The address bits registered coincident
with the ACTIVE command are used to select the bank
and row to be accessed (BA0 and BA1 select the bank, A0A11 select the row). The address bits ( x16: A0-A8; x32: A0A7; ) registered coincident with the READ or WRITE command are used to select the starting column location for
the burst access.
Prior to normal operation, the SDRAM must be initialized. The following sections provide detailed information covering device initialization, register definition,
command descriptions and device operation.
MODE REGISTER
In order to achieve low power consumption, there are
two mode registers in the Mobile component, Mode Register and Extended Mode Register. For this section, Mode
Register is referred to. Extended Mode register is discussed on page 12. The mode register is used to define the
specific mode of operation of the SDRAM. This definition
includes the selection of a burst length, a burst type, a
CAS latency, an operating mode and a write burst mode,
as shown in Figure 1. The mode register is programmed
via the LOAD MODE REGISTER command and will retain
the stored information until it is programmed again or
the device loses power.
Mode Register bits M0-M2 specify the burst length,
M3 specifies the type of burst (sequential or interleaved),
M4-M6 specify the CAS latency, M7 and M8 specify the
operating mode, M9, M10, and M11 should be set to zero.
M12 and M13 should be set to zero to prevent extended
mode register.
The mode register must be loaded when all banks are
idle, and the controller must wait the specified time
before initiating the subsequent operation. Violating either of these requirements will result in unspecified operation.
Initialization
Burst Length
Read and write accesses to the SDRAM are burst oriented, with the burst length being programmable, as
shown in Figure 1. The burst length determines the maximum number of column locations that can be accessed
for a given READ or WRITE command. Burst lengths of 1,
2, 4, or 8 locations are available for both the sequential
and the interleaved burst types, and a full-page burst is
available for the sequential type. The full-page burst is
used in conjunction with the BURST TERMINATE command to generate arbitrary burst lengths.
Reserved states should not be used, as unknown operation or incompatibility with future versions may result.
When a READ or WRITE command is issued, a block of
columns equal to the burst length is effectively selected.
All accesses for that burst take place within this block,
meaning that the burst will wrap within the block if a
boundary is reached. The block is uniquely selected by
A1-A8 (x16) or A1-A7 (x32) when the burst length is set to
two; by A2-A8 (x16) or A2-A7 (x32) when the burst length
is set to four; and by A3-A8 (x16) or A3-A7 (x32) when the
burst length is set to eight. The remaining (least significant) address bit(s) is (are) used to select the starting
location within the block. Full-page bursts wrap within
the page if the boundary is reached.
SDRAMs must be powered up and initialized in a
predefined manner. Operational procedures other than
those specified may result in undefined operation. Once
power is applied to VDD and V DDQ (simultaneously) and
the clock is stable (stable clock is defined as a signal
cycling within timing constraints specified for the clock
pin), the SDRAM requires a 100µs delay prior to issuing
any command other than a COMMAND INHIBIT or NOP.
Starting at some point during this 100µs period and continuing at least through the end of this period, COMMAND INHIBIT or NOP commands should be applied.
Once the 100µs delay has been satisfied with at least
one COMMAND INHIBIT or NOP command having been
applied, a PRECHARGE command should be applied. All
banks must then be precharged, thereby placing the
device in the all banks idle state.
Once in the idle state, two AUTO REFRESH cycles
must be performed. After the AUTO REFRESH cycles are
complete, the SDRAM is ready for mode register programming. Because the mode register will power up in an
unknown state, it should be loaded prior to applying any
operational command.
128Mb: x16, x32 Mobile SDRAM
MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02
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MOBILE SDRAM
Burst Type
Accesses within a given burst may be programmed to
be either sequential or interleaved; this is referred to as
the burst type and is selected via bit M3.
The ordering of accesses within a burst is determined
by the burst length, the burst type and the starting column address, as shown in Table 1.
Table 1
Burst Definition
Burst
Length
A0
0
1
A1 A0
0
0
0
1
1
0
1
1
A2 A1 A0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
2
Figure 1
Mode Register Definition
4
BA1 BA0
A9
A11 A10
A8
M13 M12 M11 M10 M9 M8
13
12
11
10
9
Reserved** Reserved* WB
8
A7
A6
M7 M6
6
7
Op Mode
A5
A4
A3
M5
M4
5
4
CAS Latency
A2
M3
M2
3
Address Bus
A0
M1
1
2
BT
A1
M0
0
Mode Register (Mx)
Burst Length
8
Burst Length
*Should program
M10 = “0, 0”
to ensure compatibility
with future devices.
M2 M1 M0
** BA1, BA0 = “0, 0”
to prevent Extended
Mode Register.
M3 = 0
M3 = 1
0
0
0
1
1
0
0
1
2
2
0
1
0
4
4
0
1
1
8
8
1
0
0
Reserved
Reserved
1
0
1
Reserved
Reserved
1
1
0
Reserved
Reserved
1
1
1
Full Page
Reserved
M3
Burst Type
0
Sequential
1
Interleaved
M6 M5 M4
0
0
Reserved
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
Reserved
1
0
1
Reserved
1
1
0
Reserved
1
1
1
Reserved
M8
M7
M6-M0
Operating Mode
0
0
Defined
Standard Operation
-
-
-
M9
Write Burst Mode
0
Programmed Burst Length
1
Single Location Access
128Mb: x16, x32 Mobile SDRAM
MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02
Full
Page
(y)
n = A0-A11
(location 0-y)
0-1
1-0
0-1
1-0
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
Cn, Cn + 1, Cn + 2
Cn + 3, Cn + 4...
…Cn - 1,
Cn…
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
Not Supported
NOTE: 1. For full-page accesses: y = 512 (x16), y = 256
(x32).
2. For a burst length of two, A1-A8 (x16) or A1-A7
(x32) select the block-of-two burst; A0 selects
the starting column within the block.
3. For a burst length of four, A2-A8 (x16) or A2-A7
(x32) select the block-of-four burst; A0-A1 select
the starting column within the block.
4. For a burst length of eight, A3-A8 (x16) or A3A7 (x32) select the block-of-eight burst; A0-A2
select the starting column within the block.
5. For a full-page burst, the full row is selected
and A0-A8 (x16) or A0-A7 (x32) select the
starting column.
6. Whenever a boundary of the block is reached
within a given sequence above, the following
access wraps within the block.
7. For a burst length of one, A0-A8 (x16) or A0-A7
(x32) select the unique column to be accessed,
and mode register bit M3 is ignored.
CAS Latency
0
Starting Column Order of Accesses Within a Burst
Address
Type = Sequential Type = Interleaved
All other states reserved
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MOBILE SDRAM
CAS Latency
The CAS latency is the delay, in clock cycles, between
the registration of a READ command and the availability
of the first piece of output data. The latency can be set to
one, two, or three clocks.
If a READ command is registered at clock edge n, and
the latency is m clocks, the data will be available by clock
edge n + m. The DQs will start driving as a result of the
clock edge one cycle earlier (n + m - 1), and provided that
the relevant access times are met, the data will be valid by
clock edge n + m. For example, assuming that the clock
cycle time is such that all relevant access times are met,
if a READ command is registered at T0 and the latency is
programmed to two clocks, the DQs will start driving
after T1 and the data will be valid by T2, as shown in
Figure 2. Table 2 indicates the operating frequencies at
which each CAS latency setting can be used.
Reserved states should not be used as unknown operation or incompatibility with future versions
may result.
Operating Mode
The normal operating mode is selected by setting M7
and M8 to zero; the other combinations of values for M7
and M8 are reserved for future use and/or test modes.
The programmed burst length applies to both READ and
WRITE bursts.
Test modes and reserved states should not be used
because unknown operation or incompatibility with future versions may result.
Figure 2
CAS Latency
T0
T1
Table 2
CAS Latency
T2
ALLOWABLE OPERATING
FREQUENCY (MHz)
CLK
COMMAND
READ
NOP
tLZ
tOH
DOUT
DQ
tAC
CAS Latency = 1
T0
T1
T2
NOP
NOP
SPEED
CAS
LATENCY = 1
CAS
LATENCY = 2
CAS
LATENCY = 3
-8
≤ 50
≤ 100
≤ 125
- 10
≤ 40
≤ 83
≤ 100
T3
CLK
COMMAND
READ
tLZ
tOH
DOUT
DQ
tAC
CAS Latency = 2
T0
T1
T2
T3
T4
NOP
NOP
NOP
CLK
COMMAND
READ
tLZ
tOH
DOUT
DQ
tAC
CAS Latency = 3
DON’T CARE
UNDEFINED
128Mb: x16, x32 Mobile SDRAM
MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02
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MOBILE SDRAM
EXTENDED MODE REGISTER TABLE
BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Address Bus
M13 M12 M11 M10 M9 M8 M7 M6 M5 M4 M3 M2 M1 M0
13 12 11 10
1
0
9
8
7
6
5
All must be set to "0"
A4
4
3
2
TCSR
1
0
PASR
Extended Mode
Register (Ex)
A3 Maximum Case Temp
1
0
1
0
85˚C
70˚C
0
1
45˚C
1
0
15˚C
Self Refresh Coverage
A2
A1
A0
0
0
0
Four Banks
0
0
1
Two Banks (Bank 0,1)
0
1
0
One Bank (Bank 0)
0
1
1
RFU
1
0
0
RFU
1
0
1
RFU
1
1
0
RFU
1
1
1
RFU
Notes: 1. E13 and E12 (BA1 and BA0) must be “1, 0” to select the
Extended Mode Register (vs. the base Mode Register).
2. RFU: Reserved for Future Use
TEMPERATURE COMPENSATED SELF REFRESH
Temperature Compensated Self Refresh (TCSR) allows the controller to program the Refresh interval during SELF REFRESH mode, according to the case temperature of the Mobile device. This allows great power savings
during SELF REFRESH during most operating temperature ranges. Only during extreme temperatures would
the controller have to select a TCSR level that will guarantee data during SELF REFRESH.
Every cell in the DRAM requires refreshing due to the
capacitor losing its charge over time. The refresh rate is
dependent on temperature. At higher temperatures a
capacitor loses charge quicker than at lower temperatures, requiring the cells to be refreshed more often.
Historically, during Self Refresh, the refresh rate has
been set to accomodate the worst case, or highest temperature range expected.
EXTENDED MODE REGISTER
The Extended Mode Register controls the functions
beyond those controlled by the Mode Register. These
additional functions are special features of the Mobile
device. They include Temperature Compensated Self Refresh (TCSR) Control, and Partial Array Self Refresh
(PASR).
The Extended Mode Register is programmed via the
Mode Register Set command (BA1=1,BA0=0) and retains
the stored information until it is programmed again or
the device loses power.
The Extended Mode Register must be programmed
with M5 through M11 set to “0”. The Extended Mode
Register must be loaded when all banks are idle and no
bursts are in progress, and the controller must wait the
specified time before before initiating any subsequent
operation. Violating either of these requirements results
in unspecified operation.
128Mb: x16, x32 Mobile SDRAM
MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02
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MOBILE SDRAM
Thus, during ambient temperatures, the power
consumed during refresh was unnecessarily high,
because the refresh rate was set to accommodate the
higher temperatures. Setting M4 and M3, allow the
DRAM to accomodate more specific temperature
regions during SELF REFRESH. There are four
temperature settings, which will vary the SELF
REFRESH current according to the selected temperature. This selectable refresh rate will save power when
the DRAM is operating at normal temperatures.
128Mb: x16, x32 Mobile SDRAM
MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02
PARTIAL ARRAY SELF REFRESH
For further power savings during SELF REFRESH, the
Partial Array Self Refresh (PASR) feature allows the controller to select the amount of memory that will be refreshed during SELF REFRESH. The refresh options are
all banks (banks 0, 1, 2, and 3); two banks(banks 0 and 1);
and one bank (bank 0). WRITE and READ commands
occur to any bank selected during standard operation,
but only the selected banks in PASR will be refreshed
during SELF REFRESH. It’s important to note that data
in banks 2 and 3 will be lost when the two bank option is
used. Data will be lost in banks 1, 2, and 3 when the one
bank option is used.
13
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MOBILE SDRAM
Commands
Truth Table 1 provides a quick reference of available
commands. This is followed by a written description of
each command. Three additional Truth Tables appear
following the Operation section; these tables provide
current state/next state information.
TRUTH TABLE 1 – COMMANDS AND DQM OPERATION
(Note: 1)
NAME (FUNCTION)
COMMAND INHIBIT (NOP)
CS# RAS# CAS# WE# DQM
X
X
X
ADDR
DQs
X
X
NOTES
H
X
NO OPERATION (NOP)
L
H
H
H
X
X
X
ACTIVE (Select bank and activate row)
L
L
H
H
X
Bank/Row
X
3
READ (Select bank and column, and start READ burst)
L
H
L
H
L/H8
Bank/Col
X
4
4
WRITE (Select bank and column, and start WRITE burst)
L
H
L
L
L/H8
Bank/Col
Valid
BURST TERMINATE
L
H
H
L
X
X
Active
PRECHARGE (Deactivate row in bank or banks)
L
L
H
L
X
Code
X
5
AUTO REFRESH or SELF REFRESH
(Enter self refresh mode)
L
L
L
H
X
X
X
6, 7
LOAD MODE REGISTER
L
L
L
L
X
Op-Code
X
2
Write Enable/Output Enable
–
–
–
–
L
–
Active
8
Write Inhibit/Output High-Z
–
–
–
–
H
–
High-Z
8
NOTE: 1.
2.
3.
4.
5.
6.
7.
8.
CKE is HIGH for all commands shown except SELF REFRESH.
A0-A10 define the op-code written to the mode register.
A0-A11 provide row address, and BA0, BA1 determine which bank is made active.
A0-A8 (x16) or A0-A7 (x32) provide column address; A10 HIGH enables the auto precharge feature (nonpersistent),
while A10 LOW disables the auto precharge feature; BA0, BA1 determine which bank is being read from or written to.
A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged and BA0, BA1 are “Don’t
Care.”
This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.
Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay). DQM0 controls DQ07, DQM1 controls DQ8-15, DQM2 controls DQ16-23, and DQM3 controls DQ24-31.
128Mb: x16, x32 Mobile SDRAM
MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02
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MOBILE SDRAM
COMMAND INHIBIT
The COMMAND INHIBIT function prevents new commands from being executed by the SDRAM, regardless of
whether the CLK signal is enabled. The SDRAM is effectively deselected. Operations already in progress are not
affected.
auto precharge is used. If auto precharge is selected, the
row being accessed will be precharged at the end of the
WRITE burst; if auto precharge is not selected, the row
will remain open for subsequent accesses. Input data
appearing on the DQs is written to the memory array
subject to the DQM input logic level appearing coincident with the data. If a given DQM signal is registered
LOW, the corresponding data will be written to memory;
if the DQM signal is registered HIGH, the corresponding
data inputs will be ignored, and a WRITE will not be
executed to that byte/column location.
NO OPERATION (NOP)
The NO OPERATION (NOP) command is used to perform a NOP to an SDRAM which is selected (CS# is LOW).
This prevents unwanted commands from being registered during idle or wait states. Operations already in
progress are not affected.
PRECHARGE
The PRECHARGE command is used to deactivate the
open row in a particular bank or the open row in all banks.
The bank(s) will be available for a subsequent row access
a specified time (tRP) after the PRECHARGE command is
issued. Input A10 determines whether one or all banks
are to be precharged, and in the case where only one bank
is to be precharged, inputs BA0, BA1 select the bank.
Otherwise BA0, BA1 are treated as “Don’t Care.” Once a
bank has been precharged, it is in the idle state and must
be activated prior to any READ or WRITE commands
being issued to that bank.
LOAD MODE REGISTER
The mode register is loaded via inputs A0, BA0, BA1.
See mode register heading in the Register Definition
section. The LOAD MODE REGISTER and LOAD EXTENDED MODE REGISTER commands can only be issued when all banks are idle, and a subsequent executable command cannot be issued until tMRD is met.
ACTIVE
The ACTIVE command is used to open (or activate) a
row in a particular bank for a subsequent access. The
value on the BA0, BA1 inputs selects the bank, and the
address provided on inputs A0-A11 selects the row. This
row remains active (or open) for accesses until a
PRECHARGE command is issued to that bank. A
PRECHARGE command must be issued before opening a
different row in the same bank.
AUTO PRECHARGE
Auto precharge is a feature which performs the same
individual-bank PRECHARGE function described above,
without requiring an explicit command. This is accomplished by using A10 to enable auto precharge in conjunction with a specific READ or WRITE command. A
PRECHARGE of the bank/row that is addressed with the
READ or WRITE command is automatically performed
upon completion of the READ or WRITE burst, except in
the full-page burst mode, where auto precharge does not
apply. Auto precharge is nonpersistent in that it is either
enabled or disabled for each individual READ or WRITE
command.
Auto precharge ensures that the precharge is initiated
at the earliest valid stage within a burst. The user must
not issue another command to the same bank until the
precharge time (tRP) is completed. This is determined as
if an explicit PRECHARGE command was issued at the
earliest possible time, as described for each burst type in
the Operation section of this data sheet.
READ
The READ command is used to initiate a burst read
access to an active row. The value on the BA0, BA1 inputs
selects the bank, and the address provided on inputs A0A8 (x16) or A0-A7 (x32) selects the starting column location. The value on input A10 determines whether or not
auto precharge is used. If auto precharge is selected, the
row being accessed will be precharged at the end of the
READ burst; if auto precharge is not selected, the row will
remain open for subsequent accesses. Read data appears
on the DQs subject to the logic level on the DQM inputs
two clocks earlier. If a given DQM signal was registered
HIGH, the corresponding DQs will be High-Z two clocks
later; if the DQM signal was registered LOW, the DQs will
provide valid data.
BURST TERMINATE
The BURST TERMINATE command is used to truncate either fixed-length or full-page bursts. The most
recently registered READ or WRITE command prior to
the BURST TERMINATE command will be truncated, as
shown in the Operation section of this data sheet.
WRITE
The WRITE command is used to initiate a burst write
access to an active row. The value on the BA0, BA1 inputs
selects the bank, and the address provided on inputs A0A8 (x16) or A0-A7 (x32) selects the starting column location. The value on input A10 determines whether or not
128Mb: x16, x32 Mobile SDRAM
MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02
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MOBILE SDRAM
SELF REFRESH
The SELF REFRESH command can be used to retain
data in the SDRAM, even if the rest of the system is
powered down. When in the self refresh mode, the SDRAM
retains data without external clocking. The SELF REFRESH command is initiated like an AUTO REFRESH
command except CKE is disabled (LOW). Once the SELF
REFRESH command is registered, all the inputs to the
SDRAM become “Don’t Care” with the exception of CKE,
which must remain LOW.
Once self refresh mode is engaged, the SDRAM provides its own internal clocking, causing it to perform its
own AUTO REFRESH cycles. The SDRAM must remain in
self refresh mode for a minimum period equal to tRAS
and may remain in self refresh mode for an indefinite
period beyond that.
The procedure for exiting self refresh requires a sequence of commands. First, CLK must be stable (stable
clock is defined as a signal cycling within timing constraints specified for the clock pin) prior to CKE going
back HIGH. Once CKE is HIGH, the SDRAM must have
NOP commands issued (a minimum of two clocks) for
tXSR because time is required for the completion of any
internal refresh in progress.
Upon exiting the self refresh mode, AUTO REFRESH
commands must be issued every 15.625µs or less as both
SELF REFRESH and AUTO REFRESH utilize the row refresh counter.
AUTO REFRESH
AUTO REFRESH is used during normal operation of
the SDRAM and is analogous to CAS#-BEFORE-RAS#
(CBR) REFRESH in conventional DRAMs. This
command is nonpersistent, so it must be issued each
time a refresh is required. All active banks must be
PRECHARGED prior to issuing an AUTO REFRESH
command. The AUTO REFRESH command should not
be issued until the minimum tRP has been met after the
PRECHARGE command as shown in the operation section.
The addressing is generated by the internal refresh
controller. This makes the address bits “Don’t Care”
during an AUTO REFRESH command. The 128Mb SDRAM
requires 4,096 AUTO REFRESH cycles every 64ms (tREF),
regardless of width option. Providing a distributed AUTO
REFRESH command every 15.625µs will meet the refresh
requirement and ensure that each row is refreshed. Alternatively, 4,096 AUTO REFRESH commands can be issued
in a burst at the minimum cycle rate (tRFC), once every
64ms.
128Mb: x16, x32 Mobile SDRAM
MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02
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128Mb: x16, x32
MOBILE SDRAM
Operation
Figure 3
Activating a Specific Row in a
Specific Bank
BANK/ROW ACTIVATION
Before any READ or WRITE commands can be issued
to a bank within the SDRAM, a row in that bank must be
“opened.” This is accomplished via the ACTIVE command, which selects both the bank and the row to be
activated (see Figure 3).
After opening a row (issuing an ACTIVE command), a
READ or WRITE command may be issued to that row,
subject to the tRCD specification. tRCD (MIN) should be
divided by the clock period and rounded up to the next
whole number to determine the earliest clock edge after
the ACTIVE command on which a READ or WRITE command can be entered. For example, a tRCD specification
of 20ns with a 125 MHz clock (8ns period) results in 2.5
clocks, rounded to 3. This is reflected in Figure 4, which
covers any case where 2 < tRCD (MIN)/tCK ≤ 3. (The same
procedure is used to convert other specification limits
from time units to clock cycles.)
A subsequent ACTIVE command to a different row in
the same bank can only be issued after the previous
active row has been “closed” (precharged). The minimum time interval between successive ACTIVE commands to the same bank is defined by tRC.
A subsequent ACTIVE command to another bank can
be issued while the first bank is being accessed, which
results in a reduction of total row-access overhead. The
minimum time interval between successive ACTIVE commands to different banks is defined by tRRD.
CLK
CKE
HIGH
CS#
RAS#
CAS#
WE#
ROW
ADDRESS
A0–A10, A11
BANK
ADDRESS
BA0, BA1
Figure 4
Example: Meeting tRCD (MIN) When 2 < tRCD (MIN)/tCK ≤ 3
T0
T1
T2
T3
NOP
NOP
T4
CLK
COMMAND
ACTIVE
READ or
WRITE
tRCD
DON’T CARE
128Mb: x16, x32 Mobile SDRAM
MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02
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MOBILE SDRAM
READs
READ bursts are initiated with a READ command, as
shown in Figure 5.
The starting column and bank addresses are provided
with the READ command, and auto precharge is either
enabled or disabled for that burst access. If auto precharge
is enabled, the row being accessed is precharged at the
completion of the burst. For the generic READ commands used in the following illustrations, auto precharge
is disabled.
During READ bursts, the valid data-out element from
the starting column address will be available following
the CAS latency after the READ command. Each subsequent data-out element will be valid by the next positive
clock edge. Figure 6 shows general timing for each possible CAS latency setting.
Upon completion of a burst, assuming no other commands have been initiated, the DQs will go High-Z. A fullpage burst will continue until terminated. (At the end of
the page, it will wrap to column 0 and continue.)
Data from any READ burst may be truncated with a
subsequent READ command, and data from a fixed-length
READ burst may be immediately followed by data from a
READ command. In either case, a continuous flow of data
can be maintained. The first data element from the new
burst follows either the last element of a completed burst
or the last desired data element of a longer burst that is
being truncated. The new READ command should be
issued x cycles before the clock edge at which the last
desired data element is valid, where x equals the CAS
latency minus one.
Figure 5
READ Command
Figure 6
CAS Latency
CLK
CKE
T0
T1
T2
READ
NOP
CLK
HIGH
COMMAND
tLZ
CS#
tOH
DOUT
DQ
tAC
CAS Latency = 1
RAS#
CAS#
T0
T1
T2
WE#
COMMAND
READ
NOP
NOP
tLZ
A0-A8
T3
CLK
DOUT
DQ
COLUMN
ADDRESS
tOH
tAC
CAS Latency = 2
A9, A11
ENABLE AUTO PRECHARGE
A10
DISABLE AUTO PRECHARGE
BA0,1
T0
T1
T2
T3
T4
READ
NOP
NOP
NOP
CLK
COMMAND
BANK
ADDRESS
tLZ
DQ
DON’T CARE
tOH
DOUT
tAC
CAS Latency = 3
DON’T CARE
UNDEFINED
128Mb: x16, x32 Mobile SDRAM
MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02
18
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
ADVANCE
128Mb: x16, x32
MOBILE SDRAM
This is shown in Figure 7 for CAS latencies of two and
three; data element n + 3 is either the last of a burst of four
or the last desired of a longer burst. The 128Mb SDRAM
uses a pipelined architecture and therefore does not
require the 2n rule associated with a prefetch architec-
ture. A READ command can be initiated on any clock
cycle following a previous READ command. Full-speed
random read accesses can be performed to the same
bank, as shown in Figure 8, or each subsequent READ
may be performed to a different bank.
Figure 7
Consecutive READ Bursts
T0
T1
T2
T3
T4
T5
CLK
COMMAND
READ
NOP
NOP
NOP
NOP
READ
X = 0 cycles
ADDRESS
BANK,
COL n
BANK,
COL b
DOUT
n+2
DOUT
n+1
DOUT
n
DQ
DOUT
n+3
DOUT
b
CAS Latency = 1
T0
T1
T2
T3
T4
T5
T6
CLK
COMMAND
READ
ADDRESS
BANK,
COL n
NOP
NOP
NOP
NOP
READ
NOP
X = 1 cycle
BANK,
COL b
DOUT
n+2
DOUT
n+1
DOUT
n
DQ
DOUT
n+3
DOUT
b
CAS Latency = 2
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
READ
ADDRESS
BANK,
COL n
NOP
NOP
NOP
NOP
READ
NOP
NOP
X = 2 cycles
BANK,
COL b
DOUT
n
DQ
DOUT
n+1
DOUT
n+2
DOUT
n+3
DOUT
b
CAS Latency = 3
NOTE: Each READ command may be to either bank. DQM is LOW.
DON’T CARE
128Mb: x16, x32 Mobile SDRAM
MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02
19
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
ADVANCE
128Mb: x16, x32
MOBILE SDRAM
Figure 8
Random READ Accesses
T0
T1
T2
T3
T4
CLK
COMMAND
READ
READ
READ
READ
ADDRESS
BANK,
COL n
BANK,
COL a
BANK,
COL x
BANK,
COL m
DOUT
n
DQ
NOP
DOUT
x
DOUT
a
DOUT
m
CAS Latency = 1
T0
T1
T2
T3
T4
T5
CLK
COMMAND
READ
READ
READ
READ
ADDRESS
BANK,
COL n
BANK,
COL a
BANK,
COL x
BANK,
COL m
DOUT
n
DQ
NOP
NOP
DOUT
x
DOUT
a
DOUT
m
CAS Latency = 2
T0
T1
T2
T3
T4
T5
T6
CLK
COMMAND
READ
READ
READ
READ
ADDRESS
BANK,
COL n
BANK,
COL a
BANK,
COL x
BANK,
COL m
NOP
DOUT
a
DOUT
n
DQ
NOP
DOUT
x
NOP
DOUT
m
CAS Latency = 3
NOTE: Each READ command may be to either bank. DQM is LOW.
DON’T CARE
128Mb: x16, x32 Mobile SDRAM
MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02
20
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
ADVANCE
128Mb: x16, x32
MOBILE SDRAM
Data from any READ burst may be truncated with a
subsequent WRITE command, and data from a fixedlength READ burst may be immediately followed by data
from a WRITE command (subject to bus turnaround
limitations). The WRITE burst may be initiated on the
clock edge immediately following the last (or last desired) data element from the READ burst, provided that I/
O contention can be avoided. In a given system design,
there may be a possibility that the device driving the
input data will go Low-Z before the SDRAM DQs go HighZ. In this case, at least a single-cycle delay should occur
between the last read data and the WRITE command.
The DQM input is used to avoid I/O contention, as
shown in Figures 9 and 10. The DQM signal must be
asserted (HIGH) at least two clocks prior to the WRITE
command (DQM latency is two clocks for output buffers)
to suppress data-out from the READ. Once the WRITE
command is registered, the DQs will go High-Z (or remain High-Z), regardless of the state of the DQM signal,
provided the DQM was active on the clock just prior to
the WRITE command that truncated the READ command. If not, the second WRITE will be an invalid WRITE.
For example, if DQM was LOW during T4 in Figure 10,
then the WRITEs at T5 and T7 would be valid, while the
WRITE at T6 would be invalid.
The DQM signal must be de-asserted prior to the
WRITE command (DQM latency is zero clocks for input
buffers) to ensure that the written data is not masked.
Figure 9 shows the case where the clock frequency allows
for bus contention to be avoided without adding a NOP
cycle, and Figure 10 shows the case where the additional
NOP is needed.
Figure 9
READ to WRITE
Figure 10
READ to WRITE With
Extra Clock Cycle
T0
T1
T2
T3
T4
T0
CLK
T1
T2
T3
T4
T5
CLK
DQM
DQM
COMMAND
READ
ADDRESS
BANK,
COL n
NOP
NOP
NOP
WRITE
BANK,
COL b
COMMAND
READ
ADDRESS
BANK,
COL n
tCK
DOUT n
NOP
NOP
NOP
WRITE
BANK,
COL b
tHZ
tHZ
DQ
NOP
DQ
DOUT n
DIN b
tDS
DIN b
tDS
DON’T CARE
DON’T CARE
NOTE:
NOTE:
A CAS latency of three is used for illustration. The READ
command may be to any bank, and the WRITE command
128Mb: x16, x32 Mobile SDRAM
MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02
21
A CAS latency of three is used for illustration. The READ command
may be to any bank, and the WRITE command may be to any bank.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
ADVANCE
128Mb: x16, x32
MOBILE SDRAM
A fixed-length READ burst may be followed by, or
truncated with, a PRECHARGE command to the same
bank (provided that auto precharge was not activated),
and a full-page burst may be truncated with a
PRECHARGE command to the same bank. The
PRECHARGE command should be issued x cycles before
the clock edge at which the last desired data element is
valid, where x equals the CAS latency minus one. This is
shown in Figure 11 for each possible CAS latency; data
element n + 3 is either the last of a burst of four or the last
desired of a longer burst. Following the PRECHARGE
command, a subsequent command to the same bank
cannot be issued until tRP is met. Note that part of the row
precharge time is hidden during the access of the last
data element(s).
In the case of a fixed-length burst being executed to
completion, a PRECHARGE command issued at the optimum time (as described above) provides the same operation that would result from the same fixed-length
burst with auto precharge. The disadvantage of the
Figure 11
READ to PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
t RP
COMMAND
READ
NOP
NOP
NOP
PRECHARGE
NOP
NOP
ACTIVE
X = 0 cycles
ADDRESS
BANK
(a or all)
BANK a,
COL n
DOUT
n
DQ
DOUT
n+2
DOUT
n+1
BANK a,
ROW
DOUT
n+3
CAS Latency = 1
T0
T1
T2
T3
T4
T5
T6
T7
CLK
t RP
COMMAND
READ
NOP
NOP
NOP
PRECHARGE
NOP
NOP
ACTIVE
X = 1 cycle
ADDRESS
BANK
(a or all)
BANK a,
COL n
DOUT
n
DQ
BANK a,
ROW
DOUT
n+2
DOUT
n+1
DOUT
n+3
CAS Latency = 2
T0
T1
T2
T3
T4
T5
T6
T7
CLK
t RP
COMMAND
READ
NOP
NOP
NOP
PRECHARGE
NOP
NOP
ACTIVE
X = 2 cycles
ADDRESS
BANK
(a or all)
BANK a,
COL n
DOUT
n
DQ
DOUT
n+1
BANK a,
ROW
DOUT
n+2
DOUT
n+3
CAS Latency = 3
NOTE: DQM is LOW.
128Mb: x16, x32 Mobile SDRAM
MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02
DON’T CARE
22
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
ADVANCE
128Mb: x16, x32
MOBILE SDRAM
PRECHARGE command is that it requires that the command and address buses be available at the appropriate
time to issue the command; the advantage of the
PRECHARGE command is that it can be used to truncate
fixed-length or full-page bursts.
Full-page READ bursts can be truncated with the
BURST TERMINATE command, and fixed-length READ
bursts may be truncated with a BURST TERMINATE com-
mand, provided that auto precharge was not activated.
The BURST TERMINATE command should be issued x
cycles before the clock edge at which the last desired data
element is valid, where x equals the CAS latency minus
one. This is shown in Figure 12 for each possible CAS
latency; data element n + 3 is the last desired data element of a longer burst.
Figure 12
Terminating a READ Burst
T0
T1
T2
T3
T4
T5
T6
CLK
COMMAND
READ
NOP
NOP
NOP
BURST
TERMINATE
NOP
NOP
X = 0 cycles
ADDRESS
BANK,
COL n
DOUT
n
DQ
DOUT
n+2
DOUT
n+1
DOUT
n+3
CAS Latency = 1
T0
T1
T2
T3
T4
T5
T6
CLK
COMMAND
READ
ADDRESS
BANK,
COL n
NOP
NOP
NOP
BURST
TERMINATE
NOP
NOP
X = 1 cycle
DOUT
n
DQ
DOUT
n+2
DOUT
n+1
DOUT
n+3
CAS Latency = 2
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
READ
NOP
NOP
NOP
BURST
TERMINATE
NOP
NOP
NOP
X = 2 cycles
ADDRESS
BANK,
COL n
DOUT
n
DQ
DOUT
n+1
DOUT
n+2
DOUT
n+3
CAS Latency = 3
NOTE: DQM is LOW.
128Mb: x16, x32 Mobile SDRAM
MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02
DON’T CARE
23
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
ADVANCE
128Mb: x16, x32
MOBILE SDRAM
WRITEs
WRITE bursts are initiated with a WRITE command,
as shown in Figure 13.
The starting column and bank addresses are provided with the WRITE command, and auto precharge is
either enabled or disabled for that access. If auto
precharge is enabled, the row being accessed is
precharged at the completion of the burst. For the generic WRITE commands used in the following illustrations, auto precharge is disabled.
During WRITE bursts, the first valid data-in element
will be registered coincident with the WRITE command.
Subsequent data elements will be registered on each
successive positive clock edge. Upon completion of a
fixed-length burst, assuming no other commands have
been initiated, the DQs will remain High-Z and any additional input data will be ignored (see Figure 14). A fullpage burst will continue until terminated. (At the end of
the page, it will wrap to column 0 and continue.)
Data for any WRITE burst may be truncated with a
subsequent WRITE command, and data for a fixed-length
WRITE burst may be immediately followed by data for a
WRITE command. The new WRITE command can be
issued on any clock following the previous WRITE command, and the data provided coincident with the new
command applies to the new command. An example is
shown in Figure 15. Data n + 1 is either the last of a burst
of two or the last desired of a longer burst. The 128Mb
SDRAM uses a pipelined architecture and therefore does
not require the 2n rule associated with a prefetch architecture. A WRITE command can be initiated on any clock
cycle following a previous WRITE command. Full-speed
random write accesses within a page can be performed to
the same bank, as shown in Figure 16, or each subsequent
WRITE may be performed to a different bank.
Figure 14
WRITE Burst
T0
T1
T2
T3
COMMAND
WRITE
NOP
NOP
NOP
ADDRESS
BANK,
COL n
CLK
NOTE:
DIN
n+1
DIN
n
DQ
Figure 13
WRITE Command
Burst length = 2. DQM is LOW.
CLK
CKE
Figure 15
WRITE to WRITE
HIGH
CS#
T0
T1
T2
COMMAND
WRITE
NOP
WRITE
ADDRESS
BANK,
COL n
RAS#
CLK
CAS#
WE#
COLUMN
ADDRESS
A0-A8
BANK,
COL b
A9, A11
DQ
ENABLE AUTO PRECHARGE
A10
DIN
n
DIN
n+1
DIN
b
DISABLE AUTO PRECHARGE
NOTE:
BANK
ADDRESS
BA0,1
VALID ADDRESS
128Mb: x16, x32 Mobile SDRAM
MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02
DQM is LOW. Each WRITE
command may be to any bank.
DON’T CARE
DON’T CARE
24
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©2002, Micron Technology, Inc.
ADVANCE
128Mb: x16, x32
MOBILE SDRAM
Data for any WRITE burst may be truncated with a
subsequent READ command, and data for a fixed-length
WRITE burst may be immediately followed by a READ
command. Once the READ command is registered, the
data inputs will be ignored, and WRITEs will not be
executed. An example is shown in Figure 17. Data n + 1 is
either the last of a burst of two or the last desired of a
longer burst.
Data for a fixed-length WRITE burst may be followed
by, or truncated with, a PRECHARGE command to the
same bank (provided that auto precharge was not activated), and a full-page WRITE burst may be truncated
with a PRECHARGE command to the same bank. The
PRECHARGE command should be issued tWR after the
clock edge at which the last desired input data element is
registered. The auto precharge mode requires a tWR of at
least one clock plus time, regardless of frequency.
In addition, when truncating a WRITE burst, the DQM
signal must be used to mask input data for the clock edge
prior to, and the clock edge coincident with, the
PRECHARGE command. An example is shown in Figure
18. Data n + 1 is either the last of a burst of two or the last
desired of a longer burst. Following the PRECHARGE
command, a subsequent command to the same bank
cannot be issued until tRP is met.
In the case of a fixed-length burst being executed to
completion, a PRECHARGE command issued at the optimum time (as described above) provides the same operation that would result from the same fixed-length
burst with auto precharge. The disadvantage of the
PRECHARGE command is that it requires that the command and address buses be available at the appropriate
time to issue the command; the advantage of the
PRECHARGE command is that it can be used to truncate
fixed-length or full-page bursts.
Figure 16
Random WRITE Cycles
T0
T1
T2
T3
CLK
COMMAND
Figure 18
WRITE to PRECHARGE
WRITE
WRITE
WRITE
WRITE
T0
T1
T2
T3
WRITE
NOP
PRECHARGE
NOP
T4
T5
T6
NOP
ACTIVE
NOP
CLK
ADDRESS
BANK,
COL n
BANK,
COL a
BANK,
COL x
BANK,
COL m
DIN
n
DIN
a
DIN
x
DIN
m
tWR@ tCK 15ns
DQM
t RP
DQ
COMMAND
ADDRESS
NOTE:
Each WRITE command may be to any bank.
DQM is LOW.
BANK
(a or all)
BANK a,
COL n
BANK a,
ROW
t WR
DQ
DIN
n
DIN
n+1
tWR@ tCK < 15ns
Figure 17
WRITE to READ
DQM
t RP
T0
T1
T2
T3
T4
T5
COMMAND
WRITE
NOP
NOP
PRECHARGE
NOP
NOP
ACTIVE
CLK
ADDRESS
BANK
(a or all)
BANK a,
COL n
BANK a,
ROW
t WR
COMMAND
WRITE
ADDRESS
BANK,
COL n
NOP
READ
NOP
NOP
NOP
DQ
BANK,
COL b
NOTE:
DIN
n
DIN
n+1
DQM could remain LOW in this example if the WRITE burst is a fixed length
of two.
DON’T CARE
DQ
NOTE:
DIN
n
DIN
n+1
DOUT
b
DOUT
b+1
The WRITE command may be to any bank, and the READ command may
be to any bank. DQM is LOW. CAS latency = 2 for illustration.
128Mb: x16, x32 Mobile SDRAM
MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02
25
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
ADVANCE
128Mb: x16, x32
MOBILE SDRAM
PRECHARGE
The PRECHARGE command (see Figure 20) is used to
deactivate the open row in a particular bank or the open
row in all banks. The bank(s) will be available for a subsequent row access some specified time (tRP) after the
PRECHARGE command is issued. Input A10 determines
whether one or all banks are to be precharged, and in the
case where only one bank is to be precharged, inputs
BA0, BA1 select the bank. When all banks are to be
precharged, inputs BA0, BA1 are treated as “Don’t Care.”
Once a bank has been precharged, it is in the idle state
and must be activated prior to any READ or WRITE commands being issued to that bank.
Fixed-length or full-page WRITE bursts can be truncated with the BURST TERMINATE command. When
truncating a WRITE burst, the input data applied coincident with the BURST TERMINATE command will be
ignored. The last data written (provided that DQM is
LOW at that time) will be the input data applied one clock
previous to the BURST TERMINATE command. This is
shown in Figure 19, where data n is the last desired data
element of a longer burst.
Figure 19
Terminating a WRITE Burst
T0
T1
T2
COMMAND
WRITE
BURST
TERMINATE
ADDRESS
BANK,
COL n
(ADDRESS)
DIN
n
(DATA)
POWER-DOWN
Power-down occurs if CKE is registered LOW coincident with a NOP or COMMAND INHIBIT when no accesses are in progress. If power-down occurs when all
banks are idle, this mode is referred to as precharge
power-down; if power-down occurs when there is a row
active in any bank, this mode is referred to as active
power-down. Entering power-down deactivates the input and output buffers, excluding CKE, for maximum
power savings while in standby. The device may not
remain in the power-down state longer than the refresh
period (64ms) since no refresh operations are performed
in this mode.
The power-down state is exited by registering a NOP
or COMMAND INHIBIT and CKE HIGH at the desired
clock edge (meeting tCKS). See Figure 21.
CLK
DQ
NEXT
COMMAND
Figure 20
PRECHARGE Command
Figure 21
Power-Down
CLK
CKE
HIGH
((
))
((
))
CLK
tCKS
CS#
CKE
RAS#
> tCKS
((
))
COMMAND
((
))
((
))
NOP
NOP
All banks idle
Input buffers gated off
CAS#
Enter power-down mode.
WE#
Exit power-down mode.
ACTIVE
tRCD
tRAS
tRC
DON’T CARE
A0-A9
All Banks
A10
Bank Selected
BA0,1
128Mb: x16, x32 Mobile SDRAM
MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02
BANK
ADDRESS
26
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©2002, Micron Technology, Inc.
ADVANCE
128Mb: x16, x32
MOBILE SDRAM
CLOCK SUSPEND
The clock suspend mode occurs when a column access/burst is in progress and CKE is registered LOW. In
the clock suspend mode, the internal clock is deactivated, “freezing” the synchronous logic.
For each positive clock edge on which CKE is sampled
LOW, the next internal positive clock edge is suspended.
Any command or data present on the input pins at the
time of a suspended internal clock edge is ignored; any
data present on the DQ pins remains driven; and burst
counters are not incremented, as long as the clock is
suspended. (See examples in Figures 22 and 23.)
Clock suspend mode is exited by registering CKE
HIGH; the internal clock and related operation will resume on the subsequent positive clock edge.
BURST READ/SINGLE WRITE
The burst read/single write mode is entered by programming the write burst mode bit (M9) in the mode
register to a logic 1. In this mode, all WRITE commands
result in the access of a single column location (burst of
one), regardless of the programmed burst length. READ
commands access columns according to the programmed
burst length and sequence, just as in the normal mode of
operation (M9 = 0).
Figure 22
Clock Suspend During WRITE Burst
T0
T1
T2
T3
T4
Figure 23
Clock Suspend During READ Burst
T5
T0
CLK
CLK
CKE
CKE
ADDRESS
NOP
WRITE
NOP
T3
T4
T5
T6
COMMAND
READ
ADDRESS
BANK,
COL n
NOP
NOP
NOP
NOP
NOP
NOP
BANK,
COL n
DQ
DIN
T2
INTERNAL
CLOCK
INTERNAL
CLOCK
COMMAND
T1
DIN
n
DIN
n+1
DOUT
n
DOUT
n+1
DOUT
n+2
DOUT
n+3
DIN
n+2
DON’T CARE
NOTE: For this example, CAS latency = 2, burst length = 4 or greater, and
DQM is LOW.
DON’T CARE
128Mb: x16, x32 Mobile SDRAM
MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02
27
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
ADVANCE
128Mb: x16, x32
MOBILE SDRAM
CONCURRENT AUTO PRECHARGE
An access command (READ or WRITE) to another
bank while an access command with auto precharge
enabled is executing is not allowed by SDRAMs, unless
the SDRAM supports CONCURRENT AUTO PRECHARGE.
Micron SDRAMs support CONCURRENT AUTO
PRECHARGE. Four cases where CONCURRENT AUTO
PRECHARGE occurs are defined below.
on bank n, CAS latency later. The PRECHARGE to
bank n will begin when the READ to bank m is registered (Figure 24).
2. Interrupted by a WRITE (with or without auto
precharge): A WRITE to bank m will interrupt a READ
on bank n when registered. DQM should be used two
clocks prior to the WRITE command to prevent bus
contention. The PRECHARGE to bank n will begin
when the WRITE to bank m is registered (Figure 25).
READ with Auto Precharge
1. Interrupted by a READ (with or without auto
precharge): A READ to bank m will interrupt a READ
Figure 24
READ With Auto Precharge Interrupted by a READ
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
BANK n
Internal
States
READ - AP
BANK n
NOP
Page Active
READ - AP
BANK m
NOP
READ with Burst of 4
NOP
NOP
NOP
NOP
Idle
Interrupt Burst, Precharge
tRP - BANK m
t RP - BANK n
Page Active
BANK m
BANK n,
COL a
ADDRESS
Precharge
READ with Burst of 4
BANK m,
COL d
DOUT
a+1
DOUT
a
DQ
DOUT
d
DOUT
d+1
CAS Latency = 3 (BANK n)
CAS Latency = 3 (BANK m)
NOTE: DQM is LOW.
Figure 25
READ With Auto Precharge Interrupted by a WRITE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
BANK n
Internal
States
READ - AP
BANK n
Page
Active
NOP
NOP
NOP
READ with Burst of 4
WRITE - AP
BANK m
NOP
NOP
Interrupt Burst, Precharge
Idle
tRP - BANK n
Page Active
BANK m
ADDRESS
NOP
Write-Back
WRITE with Burst of 4
BANK n,
COL a
t WR - BANK m
BANK m,
COL d
1
DQM
DOUT
a
DQ
DIN
d
DIN
d+1
DIN
d+2
DIN
d+3
CAS Latency = 3 (BANK n)
NOTE: 1. DQM is HIGH at T2 to prevent DOUT-a+1 from contending with DIN-d at T4.
DON’T CARE
128Mb: x16, x32 Mobile SDRAM
MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02
28
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©2002, Micron Technology, Inc.
ADVANCE
128Mb: x16, x32
MOBILE SDRAM
WRITE with Auto Precharge
3. Interrupted by a READ (with or without auto
precharge): A READ to bank m will interrupt a WRITE
on bank n when registered, with the data-out appearing CAS latency later. The PRECHARGE to bank n will
begin after tWR is met, where tWR begins when the
READ to bank m is registered. The last valid WRITE to
bank n will be data-in registered one clock prior to the
READ to bank m (Figure 26).
4. Interrupted by a WRITE (with or without auto
precharge): A WRITE to bank m will interrupt a WRITE
on bank n when registered. The PRECHARGE to bank
n will begin after tWR is met, where tWR begins when
the WRITE to bank m is registered.
The last valid data WRITE to bank n will be data
registered one clock prior to a WRITE to bank m
(Figure 27).
Figure 26
WRITE With Auto Precharge Interrupted by a READ
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
BANK n
Internal
States
NOP
WRITE - AP
BANK n
Page Active
READ - AP
BANK m
NOP
WRITE with Burst of 4
DIN
a
DQ
NOP
Precharge
tWR - BANK n
tRP - BANK n
NOP
tRP - BANK m
READ with Burst of 4
BANK n,
COL a
ADDRESS
NOP
Interrupt Burst, Write-Back
Page Active
BANK m
NOP
BANK m,
COL d
DOUT
d+1
DOUT
d
DIN
a+1
CAS Latency = 3 (BANK m)
NOTE: 1. DQM is LOW.
Figure 27
WRITE With Auto Precharge Interrupted by a WRITE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
BANK n
Internal
States
NOP
WRITE - AP
BANK n
Page Active
NOP
NOP
WRITE with Burst of 4
NOP
Interrupt Burst, Write-Back
tWR - BANK n
BANK m
ADDRESS
DQ
Page Active
BANK n,
COL a
DIN
a
NOP
NOP
Precharge
tRP - BANK n
t WR - BANK m
Write-Back
WRITE with Burst of 4
BANK m,
COL d
DIN
a+1
DIN
a+2
NOTE: 1. DQM is LOW.
128Mb: x16, x32 Mobile SDRAM
MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02
WRITE - AP
BANK m
DIN
d
DIN
d+1
DIN
d+2
DIN
d+3
DON’T CARE
29
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MOBILE SDRAM
TRUTH TABLE 2 – CKE
(Notes: 1-4)
CKEn-1 CKEn
L
L
L
H
H
L
CURRENT STATE
COMMANDn
Power-Down
X
Self Refresh
X
Maintain Self Refresh
Clock Suspend
X
Maintain Clock Suspend
Power-Down
COMMAND INHIBIT or NOP
Exit Power-Down
Self Refresh
COMMAND INHIBIT or NOP
Exit Self Refresh
6
Clock Suspend
X
Exit Clock Suspend
7
All Banks Idle
COMMAND INHIBIT or NOP
Power-Down Entry
All Banks Idle
AUTO REFRESH
Self Refresh Entry
Reading or Writing
H
H
VALID
ACTIONn
NOTES
Maintain Power-Down
5
Clock Suspend Entry
See Truth Table 3
NOTE: 1.
2.
3.
4.
5.
CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous clock edge.
Current state is the state of the SDRAM immediately prior to clock edge n.
COMMANDn is the command registered at clock edge n, and ACTIONn is a result of COMMANDn.
All states and sequences not shown are illegal or reserved.
Exiting power-down at clock edge n will put the device in the all banks idle state in time for clock edge n + 1
(provided that tCKS is met).
6. Exiting self refresh at clock edge n will put the device in the all banks idle state once tXSR is met. COMMAND INHIBIT
or NOP commands should be issued on any clock edges occurring during the tXSR period. A minimum of two NOP
commands must be provided during tXSR period.
7. After exiting clock suspend at clock edge n, the device will resume operation and recognize the next command at
clock edge n + 1.
128Mb: x16, x32 Mobile SDRAM
MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02
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MOBILE SDRAM
TRUTH TABLE 3 – CURRENT STATE BANK n, COMMAND TO BANK n
(Notes: 1-6; notes appear below and on next page)
CURRENT STATE CS# RAS# CAS# WE#
Any
Idle
Row Active
COMMAND (ACTION)
NOTES
H
X
X
X
COMMAND INHIBIT (NOP/Continue previous operation)
L
H
H
H
NO OPERATION (NOP/Continue previous operation)
L
L
H
H
ACTIVE (Select and activate row)
L
L
L
H
AUTO REFRESH
7
L
L
L
L
LOAD MODE REGISTER
7
L
L
H
L
PRECHARGE
11
L
H
L
H
READ (Select column and start READ burst)
10
L
H
L
L
WRITE (Select column and start WRITE burst)
10
L
L
H
L
PRECHARGE (Deactivate row in bank or banks)
8
Read
L
H
L
H
READ (Select column and start new READ burst)
10
(Auto
L
H
L
L
WRITE (Select column and start WRITE burst)
10
Precharge
L
L
H
L
PRECHARGE (Truncate READ burst, start PRECHARGE)
8
Disabled)
L
H
H
L
BURST TERMINATE
9
Write
L
H
L
H
READ (Select column and start READ burst)
10
(Auto
L
H
L
L
WRITE (Select column and start new WRITE burst)
10
Precharge
L
L
H
L
PRECHARGE (Truncate WRITE burst, start PRECHARGE)
8
Disabled)
L
H
H
L
BURST TERMINATE
9
NOTE: 1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Truth Table 2) and after tXSR has been
met (if the previous state was self refresh).
2. This table is bank-specific, except where noted; i.e., the current state is for a specific bank and the commands shown
are those allowed to be issued to that bank when in that state. Exceptions are covered in the notes below.
3. Current state definitions:
Idle: The bank has been precharged, and tRP has been met.
Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and
no register accesses are in progress.
Read: A READ burst has been initiated, with auto precharge disabled, and has not yet
terminated or been terminated.
Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated
or been terminated.
4. The following states must not be interrupted by a command issued to the same bank. COMMAND INHIBIT or NOP
commands, or allowable commands to the other bank should be issued on any clock edge occurring during these
states. Allowable commands to the other bank are determined by its current state and Truth Table 3, and according to
Truth Table 4.
Precharging: Starts with registration of a PRECHARGE command and ends when tRP is met. Once tRP is
met, the bank will be in the idle state.
Row Activating: Starts with registration of an ACTIVE command and ends when tRCD is met. Once tRCD is
met, the bank will be in the row active state.
Read w/Auto
Precharge Enabled: Starts with registration of a READ command with auto precharge enabled and ends when tRP
has been met. Once tRP is met, the bank will be in the idle state.
Write w/Auto
Precharge Enabled: Starts with registration of a WRITE command with auto precharge enabled and ends when
t
RP has been met. Once tRP is met, the bank will be in the idle state.
(Continued on next page)
128Mb: x16, x32 Mobile SDRAM
MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02
31
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MOBILE SDRAM
NOTE (continued):
5. The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP commands
must be applied on each positive clock edge during these states.
Refreshing: Starts with registration of an AUTO REFRESH command and ends when tRC is met. Once tRC is
met, the SDRAM will be in the all banks idle state.
Accessing Mode
Register: Starts with registration of a LOAD MODE REGISTER command and ends when tMRD has been
met. Once tMRD is met, the SDRAM will be in the all banks idle state.
Precharging All: Starts with registration of a PRECHARGE ALL command and ends when tRP is met. Once tRP is
met, all banks will be in the idle state.
6. All states and sequences not shown are illegal or reserved.
7. Not bank-specific; requires that all banks are idle.
8. May or may not be bank-specific; if all banks are to be precharged, all must be in a valid state for precharging.
9. Not bank-specific; BURST TERMINATE affects the most recent READ or WRITE burst, regardless of bank.
10. READs or WRITEs listed in the Command (Action) column include READs or WRITEs with auto precharge enabled and
READs or WRITEs with auto precharge disabled.
11. Does not affect the state of the bank and acts as a NOP to that bank.
128Mb: x16, x32 Mobile SDRAM
MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02
32
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MOBILE SDRAM
TRUTH TABLE 4 – CURRENT STATE BANK n, COMMAND TO BANK m
(Notes: 1-6; notes appear below and on next page)
CURRENT STATE CS# RAS# CAS# WE#
COMMAND (ACTION)
NOTES
Any
H
X
X
X
COMMAND INHIBIT (NOP/Continue previous operation)
L
H
H
H
NO OPERATION (NOP/Continue previous operation)
Idle
X
X
X
X
Any Command Otherwise Allowed to Bank m
Row
L
L
H
H
ACTIVE (Select and activate row)
Activating,
L
H
L
H
READ (Select column and start READ burst)
7
Active, or
L
H
L
L
WRITE (Select column and start WRITE burst)
7
Precharging
L
L
H
L
PRECHARGE
Read
L
L
H
H
ACTIVE (Select and activate row)
(Auto
L
H
L
H
READ (Select column and start new READ burst)
7, 10
Precharge
L
H
L
L
WRITE (Select column and start WRITE burst)
7, 11
Disabled)
L
L
H
L
PRECHARGE
Write
L
L
H
H
ACTIVE (Select and activate row)
9
(Auto
L
H
L
H
READ (Select column and start READ burst)
7, 12
Precharge
L
H
L
L
WRITE (Select column and start new WRITE burst)
7, 13
Disabled)
L
L
H
L
PRECHARGE
Read
L
L
H
H
ACTIVE (Select and activate row)
9
(With Auto
L
H
L
H
READ (Select column and start new READ burst)
7, 8, 14
Precharge)
L
H
L
L
WRITE (Select column and start WRITE burst)
7, 8, 15
L
L
H
L
PRECHARGE
L
L
H
H
ACTIVE (Select and activate row)
Write
9
(With Auto
L
H
L
H
READ (Select column and start READ burst)
7, 8, 16
Precharge)
L
H
L
L
WRITE (Select column and start new WRITE burst)
7, 8, 17
L
L
H
L
PRECHARGE
9
NOTE: 1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Truth Table 2) and after tXSR has been met (if the
previous state was self refresh).
2. This table describes alternate bank operation, except where noted; i.e., the current state is for bank n and the
commands shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given
command is allowable). Exceptions are covered in the notes below.
3. Current state definitions:
Idle: The bank has been precharged, and tRP has been met.
Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and
no register accesses are in progress.
Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated
or been terminated.
Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated
or been terminated.
Read w/Auto
Precharge Enabled: Starts with registration of a READ command with auto precharge enabled, and ends when
t
RP has been met. Once tRP is met, the bank will be in the idle state.
Write w/Auto
Precharge Enabled: Starts with registration of a WRITE command with auto precharge enabled, and ends when
t
RP has been met. Once tRP is met, the bank will be in the idle state.
(Continued on next page)
128Mb: x16, x32 Mobile SDRAM
MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02
33
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©2002, Micron Technology, Inc.
ADVANCE
128Mb: x16, x32
MOBILE SDRAM
NOTE (continued):
4. AUTO REFRESH, SELF REFRESH and LOAD MODE REGISTER commands may only be issued when all banks are idle.
5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current
state only.
6. All states and sequences not shown are illegal or reserved.
7. READs or WRITEs to bank m listed in the Command (Action) column include READs or WRITEs with auto precharge
enabled and READs or WRITEs with auto precharge disabled.
8. CONCURRENT AUTO PRECHARGE: Bank n will initiate the auto precharge command when its burst has been
interrupted by bank m’s burst.
9. Burst in bank n continues as initiated.
10. For a READ without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m
will interrupt the READ on bank n, CAS latency later (Figure 7).
11. For a READ without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m
will interrupt the READ on bank n when registered (Figures 9 and 10). DQM should be used one clock prior to the
WRITE command to prevent bus contention.
12. For a WRITE without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m
will interrupt the WRITE on bank n when registered (Figure 17), with the data-out appearing CAS latency later. The
last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m.
13. For a WRITE without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m
will interrupt the WRITE on bank n when registered (Figure 15). The last valid WRITE to bank n will be data-in
registered one clock prior to the READ to bank m.
14. For a READ with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will
interrupt the READ on bank n, CAS latency later. The PRECHARGE to bank n will begin when the READ to bank m is
registered (Figure 24).
15. For a READ with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will
interrupt the READ on bank n when registered. DQM should be used two clocks prior to the WRITE command to
prevent bus contention. The PRECHARGE to bank n will begin when the WRITE to bank m is registered (Figure 25).
16. For a WRITE with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will
interrupt the WRITE on bank n when registered, with the data-out appearing CAS latency later. The PRECHARGE to
bank n will begin after tWR is met, where tWR begins when the READ to bank m is registered. The last valid WRITE to
bank n will be data-in registered one clock prior to the READ to bank m (Figure 26).
17. For a WRITE with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will
interrupt the WRITE on bank n when registered. The PRECHARGE to bank n will begin after tWR is met, where tWR
begins when the WRITE to bank m is registered. The last valid WRITE to bank n will be data registered one clock prior
to the WRITE to bank m (Figure 27).
128Mb: x16, x32 Mobile SDRAM
MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02
34
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
ADVANCE
128Mb: x16, x32
MOBILE SDRAM
ABSOLUTE MAXIMUM RATINGS*
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation
of the device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
Voltage on VDD/VDDQ Supply
Relative to VSS(3.3V) ............................. -1V to +4.6V
Relative to VSS(2.5V) ......................... -0.5V to +3.6V
Voltage on Inputs, NC or I/O Pins
Relative to VSS(3.3V) ............................. -1V to +4.6V
Relative to VSS(2.5V) ......................... -0.5V to +3.6V
Operating Temperature,
TA (Industrial) ....................................... -40°C to +85°C
Storage Temperature (plastic) ................ -55°C to +150°C
Power Dissipation .......................................................... 1W
DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS - LC VERSION
(Notes: 1, 5, 6; notes appear on page 39; VDD = +3.3V ±0.3V, VDDQ = +3.3V ±0.3V
PARAMETER/CONDITION
SYMBOL
MIN
MAX
VDD
3
3.6
V
Supply Voltage
I/O Supply Voltage
UNITS NOTES
VDDQ
3
3.6
V
VIH
2
VDD + 0.3
V
22
22
Input High Voltage: Logic 1; All inputs
Input Low Voltage: Logic 0; All inputs
VIL
-0.3
0.8
V
Data Output High Voltage: Logic 1; All inputs
VOH
2.4
–
V
Data Output LOW Voltage: LOGIC 0; All inputs
VOL
–
0.4
V
II
-5
5
µA
IOZ
-5
5
µA
Input Leakage Current:
Any Input 0V ≤ VIN ≤ VDD
(All other pins not under test = 0V)
Output Leakage Current: DQs are disabled; 0V ≤ VOUT ≤ VDDQ
DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS - V VERSION
(Notes: 1, 5, 6; notes appear on page 39; VDD = 2.5 ±0.2V, VDDQ = +2.5V ±0.2V or +1.8V ±0.15V )
PARAMETER/CONDITION
Supply Voltage
I/O Supply Voltage
SYMBOL
MIN
MAX
VDD
2.3
2.7
UNITS NOTES
V
VDDQ(2.5V)
2.3
2.7
V
V
VDDQ(1.8V)
1.65
1.95
Input High Voltage: Logic 1; All inputs
VIH
1.25
VDD + 0.3
V
22
Input Low Voltage: Logic 0; All inputs
VIL
-0.3
+0.55
V
22
Data Output High Voltage: Logic 1; All inputs
VOH
VDDQ - 0.2
–
V
Data Output Low Voltage: LOGIC 0; All inputs
VOL
–
0.2
V
II
-2
2
µA
-5
5
µA
Input Leakage Current:
Any input 0V ≤ VIN ≤ VDD (All other pins not under test = 0V)
Output Leakage Current: DQs are disabled; 0V ≤ VOUT ≤ VDDQ
128Mb: x16, x32 Mobile SDRAM
MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02
35
IOZ
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
ADVANCE
128Mb: x16, x32
MOBILE SDRAM
AC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
(VDD = +3.3V ±0.3V or 2.5 ±0.2V, VDDQ = +3.3V ±0.3V or +2.5V ±0.2V or +1.8V ±0.15V )
PARAMETER/CONDITION
SYMBOL
MIN
MAX
Input High Voltage: Logic 1; All inputs
VIH
1.4
–
UNITS NOTES
V
Input Low Voltage: Logic 0; All inputs
VIL
–
0.4
V
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 5, 6, 8, 9, 11; notes appear on page 39)
AC CHARACTERISTICS
PARAMETER
Access time from CLK (pos. edge)
Address hold time
Address setup time
CLK high-level width
CLK low-level width
Clock cycle time
CKE hold time
CKE setup time
CS#, RAS#, CAS#, WE#, DQM hold time
CS#, RAS#, CAS#, WE#, DQM setup time
Data-in hold time
Data-in setup time
Data-out high-impedance time
CL = 3
CL = 2
CL = 1
CL = 3
CL = 2
CL = 1
CL = 3
CL = 2
CL = 1
Data-out low-impedance time
Data-out hold time (load)
Data-out hold time (no load)
ACTIVE to PRECHARGE command
ACTIVE to ACTIVE command period
ACTIVE to READ or WRITE delay
Refresh period (4,096 rows)
AUTO REFRESH period
PRECHARGE command period
ACTIVE bank a to ACTIVE bank b command
Transition time
WRITE recovery time
tXSR
Exit SELF REFRESH to ACTIVE command
128Mb: x16, x32 Mobile SDRAM
MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02
-8
-10
SYMBOL MIN
MAX
MIN MAX UNITS NOTES
tAC (3)
7
7
ns
27
tAC (2)
8
8
ns
tAC (1)
19
22
ns
tAH
1
1
ns
tAS
2.5
2.5
ns
tCH
3
3
ns
tCL
3
3
ns
tCK (3)
8
10
ns
23
tCK (2)
10
12
ns
23
tCK (1)
20
25
ns
23
tCKH
1
1
ns
tCKS
2.5
2.5
ns
tCMH
1
1
ns
tCMS
2.5
2.5
ns
tDH
1
1
ns
tDS
2.5
2.5
ns
tHZ (3)
7
7
ns
10
tHZ (2)
8
8
ns
10
tHZ (1)
19
22
ns
10
tLZ
1
1
ns
tOH
2.5
2.5
ns
tOH
1.8
1.8
ns
28
N
tRAS
48
120,000
50
120,000
ns
tRC
80
100
ns
tRCD
20
20
ns
tREF
64
64
ms
tRFC
80
100
ns
tRP
20
20
ns
tRRD
20
20
ns
tT
0.5
1.2
0.5
1.2
ns
7
tWR
1 CLK +
1 CLK +
–
24
7ns
5ns
36
15
80
15
100
ns
ns
25
20
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MOBILE SDRAM
AC FUNCTIONAL CHARACTERISTICS
(Notes: 5, 6, 7, 8, 9, 11; notes appear on page 39)
PARAMETER
READ/WRITE command to READ/WRITE command
CKE to clock disable or power-down entry mode
CKE to clock enable or power-down exit setup mode
DQM to input data delay
DQM to data mask during WRITEs
DQM to data high-impedance during READs
WRITE command to input data delay
Data-in to ACTIVE command
Data-in to PRECHARGE command
Last data-in to burst STOP command
Last data-in to new READ/WRITE command
Last data-in to PRECHARGE command
LOAD MODE REGISTER command to ACTIVE or REFRESH command
Data-out to high-impedance from PRECHARGE command
SYMBOL
tCCD
tCKED
tPED
tDQD
tDQM
tDQZ
tDWD
tDAL
tDPL
tBDL
tCDL
tRDL
tMRD
tROH(3)
tROH(2)
tROH(1)
CL = 3
CL = 2
CL = 1
-8
1
1
1
0
0
2
0
5
2
1
1
2
2
3
2
1
-10 UNITS NOTES
tCK
1
17
tCK
1
14
tCK
1
14
tCK
0
17
tCK
0
17
tCK
2
17
tCK
0
17
tCK
5
15, 21
tCK
2
16, 21
tCK
1
17
tCK
1
17
tCK
2
16, 21
tCK
2
26
tCK
3
17
tCK
2
17
tCK
1
17
IDD SPECIFICATIONS AND CONDITIONS (x16)
(Notes: 1, 5, 6, 11, 13; notes appear on page 39; VDD = +3.3V ±0.3V or 2.5 ±0.2V, VDDQ = +3.3V ±0.3V or +2.5V
±0.2V or +1.8V ±0.15V )
MAX
PARAMETER/CONDITION
Operating Current: Active Mode;
Burst = 2; READ or WRITE; tRC = tRC (MIN)
Standby Current: Power-Down Mode; All banks idle; CKE = LOW
Standby Current: Active Mode;
CKE = HIGH; CS# = HIGH; All banks active after tRCD met;
No accesses in progress
Operating Current: Burst Mode; Page burst;
READ or WRITE; All banks active
tRFC = tRFC (MIN)
Auto Refresh Current
CKE = HIGH; CS# = HIGH
tRFC = 15.625µs
SYMBOL
IDD1
-8
130
-10
100
UNITS NOTES
mA
3, 18,
19, 32
µA
32
mA
3, 12,
19, 32
IDD2
IDD3
350
35
350
30
IDD4
100
95
mA
IDD5
210
170
mA
IDD6
3
3
mA
3, 18,
19, 32
3, 12,
18, 19,
32, 33
IDD7 - SELF REFRESH CURRENT OPTIONS (x16)
(Notes: Note 4 appears on page 39) (VDD = +3.3V ±0.3V or 2.5 ±0.2V, VDDQ) = +3.3V ±0.3V or +2.5V ±0.2V or
+1.8V ±0.15V)
Temperature Compensated Self Refresh
Parameter/Condition
Max
Temperature
-8 and -10
UNITS
NOTES
Self Refresh Current:
85ºC
800
µA
4
CKE < 0.2V
70ºC
500
µA
4
45ºC
350
µA
4
15ºC
300
µA
4
128Mb: x16, x32 Mobile SDRAM
MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02
37
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
ADVANCE
128Mb: x16, x32
MOBILE SDRAM
IDD SPECIFICATIONS AND CONDITIONS (x32)
(Notes: 1, 5, 6, 11, 13; notes appear on page 39; VDD = +3.3V ±0.3V or 2.5 ±0.2V, VDDQ = +3.3V ±0.3V or +2.5V
±0.2V or +1.8V ±0.15V )
MAX
PARAMETER/CONDITION
SYMBOL
-8
-10
Operating Current: Active Mode;
Burst = 2; READ or WRITE; tRC = tRC (MIN)
IDD1
150
120
mA
3, 18,
19, 32
Standby Current: Power-Down Mode;
All banks idle; CKE = LOW
IDD2
350
350
µA
32
Standby Current: Active Mode;
CKE = HIGH; CS# = HIGH; All banks active after tRCD met;
No accesses in progress
IDD3
40
35
mA
3, 12,
19, 32
Operating Current: Burst Mode; Page burst;
READ or WRITE; All banks active
Auto Refresh Current
CKE = HIGH; CS# = HIGH
IDD4
115
110
mA
IDD5
IDD6
220
3
180
3
mA
mA
3, 18,
19, 32
3, 12,
18, 19,
32, 33
tRFC
tRFC
= tRFC (MIN)
= 15.625µs
UNITS NOTES
IDD7 - SELF REFRESH CURRENT OPTIONS (x32)
(Notes: Note 4 appears on page 39) (VDD = +3.3V ±0.3V or 2.5 ±0.2V, VDDQ) = +3.3V ±0.3V or +2.5V ±0.2V or
+1.8V ±0.15V)
Temperature Compensated Self Refresh
Parameter/Condition
Max
Temperature
-8 and -10
UNITS
NOTES
Self Refresh Current:
85ºC
1000
µA
4
CKE < 0.2V
70ºC
550
µA
4
45ºC
400
µA
4
15ºC
350
µA
4
CAPACITANCE
(Note: 2; notes appear on page 39)
PARAMETER
SYMBOL
MIN
MAX
Input Capacitance: CLK
C I1
2.5
3.5
pF
29
Input Capacitance: All other input-only pins
C I2
2.5
3.8
pF
30
Input/Output Capacitance: DQs
CIO
4.0
6.0
pF
31
128Mb: x16, x32 Mobile SDRAM
MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02
38
UNITS NOTES
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
ADVANCE
128Mb: x16, x32
MOBILE SDRAM
NOTES
1.
2.
3.
4.
5.
6.
7.
8.
9.
14. Timing actually specified by tCKS; clock(s) specified
as a reference only at minimum cycle rate.
15. Timing actually specified by tWR plus tRP; clock(s)
specified as a reference only at minimum cycle rate.
16. Timing actually specified by tWR.
17. Required clocks are specified by JEDEC functionality
and are not dependent on any timing parameter.
18. The IDD current will increase or decrease proportionally according to the amount of frequency alteration for the test condition.
19. Address transitions average one transition every two
clocks.
20. CLK must be toggled a minimum of two times during
this period.
21. Based on tCK =8ns for -8 and tCK =10ns for -10.
22. VIH overshoot: VIH (MAX) = VDDQ + 2V for a pulse width
≤ 3ns, and the pulse width cannot be greater than one
third of the cycle rate. VIL undershoot: VIL (MIN) = -2V
for a pulse width ≤ 3ns.
23. The clock frequency must remain constant (stable
clock is defined as a signal cycling within timing
constraints specified for the clock pin) during access
or precharge states (READ, WRITE, including tWR,
and PRECHARGE commands). CKE may be used to
reduce the data rate.
24. Auto precharge mode only. The precharge timing
budget (tRP) begins at 7ns for -8 after the first clock
delay, after the last WRITE is executed. May not exceed limit set for precharge mode.
25. Precharge mode only.
26. JEDEC and PC100 specify three clocks.
27. tAC for -8 at CL = 3 with no load is 7ns and is guaranteed by design.
28. Parameter guaranteed by design.
29. PC100 specifies a maximum of 4pF.
30. PC100 specifies a maximum of 5pF.
31. PC100 specifies a maximum of 6.5pF.
32. For -8, CL = 2 and tCK = 10ns; for -10, CL = 3 and
tCK =10ns.
33. CKE is HIGH during refresh command period
tRFC (MIN) else CKE is LOW. The IDD6 limit is actually a nominal value and does not result in a fail
value.
All voltages referenced to VSS.
This parameter is sampled. VDD, V DDQ = +3.3V;
f = 1 MHz, TA = 25°C; pin under test biased at 1.4V.
IDD is dependent on output loading and cycle rates.
Specified values are obtained with minimum cycle
time and the outputs open.
Enables on-chip refresh and address counters.
The minimum specifications are used only to
indicate cycle time at which proper operation over
the full temperature range (-40°C ≤ TA ≤ +85°C for
IT parts) is ensured.
An initial pause of 100µs is required after power-up,
followed by two AUTO REFRESH commands, before
proper device operation is ensured. (VDD and VDDQ
must be powered up simultaneously. VSS and VSSQ
must be at same potential.) The two AUTO REFRESH
command wake-ups should be repeated any time
the tREF refresh requirement is exceeded.
AC characteristics assume tT = 1ns.
In addition to meeting the transition rate specification, the clock and CKE must transit between VIH and
VIL (or between VIL and VIH) in a monotonic manner.
Outputs measured for 3.3V at1.5V or 2.5V at 1.25V
with equivalent load:
Q
30pF
10. tHZ defines the time at which the output achieves the
open circuit condition; it is not a reference to V OH or
VOL. The last valid data element will meet tOH before
going High-Z.
11. AC timing and I DD tests have VIL and VIH, with timing
referenced to VIH/2 = crossover point. If the input
transition time is longer than t T (MAX), then the
timing is referenced at VIL (MAX) and VIH (MIN) and
no longer at the VIH/2 crossover point.
12. Other input signals are allowed to transition no more
than once every two clocks and are otherwise at valid
VIH or VIL levels.
13. IDD specifications are tested after the device is properly initialized.
128Mb: x16, x32 Mobile SDRAM
MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02
39
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
ADVANCE
128Mb: x16, x32
MOBILE SDRAM
INITIALIZE AND LOAD MODE REGISTER
T1
T0
T3
T5
CLK
((
))
((
))
CKE
((
))
((
))
COMMAND5
((
))
((
))
DQML, DQMU
((
))
((
))
((
))
((
))
A0-A9, A11
((
))
((
))
((
))
((
))
CODE
((
))
((
))
A10
((
))
((
))
((
))
((
))
CODE
((
))
((
))
T7
1,2
T9
T19
T29
((
))
((
tCK ) )
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
tCKS tCKH
tCMS tCMH
NOP
((
))
((
))
PRE
((
))
((
))
LMR4
((
))
((
))
LMR4
((
))
((
))
PRE3
((
))
((
))
AR4
((
))
((
))
((
))
((
))
AR4
ACT4
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
CODE
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
RA
CODE
( ( ALL BANKS
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
RA
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
BA
((
))
((
))
((
))
((
))
tMRD
tRP
tAS tAH
BA0, BA1
((
))
((
))
DQ
((
))
ALL BANKS
tAS tAH
tAS
((
))
((
))
High-Z
tAH
tAS
((
))
((
))
BA0 = L,
BA1 = H
BA0 = L,
BA1 = L
((
))
((
))
tRP
tMRD
tAH
T = 100µs
Power-up:
VDD and
CLK stable
Load Extended
Mode Register
tRFC
tRFC
Load Mode
Register
DON’T CARE
NOTE:
1. The two AUTO REFRESH commands at T9 and T19 may be applied before either LOAD MODE REGISTER (LMR) command.
2. PRE = PRECHARGE command, LMR = LOAD MODE REGISTER command, AR = AUTO REFRESH command, ACT = ACTIVE command, RA = Row Address,
BA = Bank Address
3. Optional refresh command.
4. The Load Mode Register for both MR/EMR and 2 Auto Refresh commands can be in any order. However, all must occur prior to an Active command.
5. Device timing is -10 with 100 MHz clock.
TIMING PARAMETERS
-8
SYMBOL*
tAH
tAS
tCH
tCL
tCK
(3)
(2)
tCK (1)
tCK
MIN
1
2.5
3
3
MAX
8
10
20
MIN
1
2.5
3
3
10
12
25
-10
MAX
-8
UNITS
ns
ns
ns
ns
SYMBOL*
tCKH
tCKS
tCMH
tCMS
tMRD3
ns
ns
ns
tRFC
tRP
MIN
1
2.5
1
2.5
2
80
20
MAX
MIN
1
2.5
1
2.5
2
100
20
-10
MAX
UNITS
ns
ns
ns
ns
tCK
ns
ns
*CAS latency indicated in parentheses.
128Mb: x16, x32 Mobile SDRAM
MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02
40
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
ADVANCE
128Mb: x16, x32
MOBILE SDRAM
POWER-DOWN MODE
T0
T1
T2
tCK
CLK
((
))
((
))
tCL
tCH
tCKS
CKE
tCKS
Tn + 1
Tn + 2
tCKS
((
))
tCKH
tCMS tCMH
COMMAND
1
PRECHARGE
NOP
((
))
((
))
NOP
NOP
ACTIVE
DQML, DQMU
((
))
((
))
A0-A9, A11
((
))
((
))
ROW
((
))
((
))
ROW
((
))
((
))
BANK
ALL BANKS
A10
SINGLE BANK
tAS
BA0, BA1
tAH
BANK(S)
High-Z
((
))
DQ
Two clock cycles
Input buffers gated off while in
power-down mode
Precharge all
active banks
All banks idle
All banks idle, enter
power-down mode
Exit power-down mode
DON’T CARE
TIMING PARAMETERS
-8
SYMBOL*
tAH
tAS
tCH
tCL
tCK (3)
tCK (2)
MIN
1
2.5
3
3
8
10
MAX
MIN
1
2.5
3
3
10
12
-10
MAX
-8
UNITS
ns
ns
ns
ns
ns
ns
SYMBOL*
tCK (1)
tCKH
tCKS
tCMH
tCMS
MIN
20
1
2.5
1
2.5
MAX
MIN
25
1
2.5
1
2.5
-10
MAX
UNITS
ns
ns
ns
ns
ns
*CAS latency indicated in parentheses.
NOTE: 1. Violating refresh requirements during power-down may result in a loss of data.
128Mb: x16, x32 Mobile SDRAM
MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02
41
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
ADVANCE
128Mb: x16, x32
MOBILE SDRAM
1
CLOCK SUSPEND MODE
T0
T1
T2
tCK
CLK
T3
T4
T5
T6
T7
T8
T9
tCL
tCH
tCKS
tCKH
CKE
tCKS
tCKH
tCMS tCMH
COMMAND
READ
NOP
NOP
NOP
NOP
NOP
WRITE
NOP
tCMS tCMH
DQMU, DQML
tAS
A0-A9, A11
tAH
COLUMN m 2
tAS
COLUMN e 2
tAH
A10
tAS
BA0, BA1
tAH
BANK
BANK
tAC
tOH
tAC
DQ
tHZ
DOUT m
tLZ
DOUT m + 1
tDS
tDH
DOUT e
DOUT e + 1
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-8
SYMBOL*
tAC (3)
tAC (2)
tAC (1)
tAH
tAS
tCH
tCL
tCK (3)
tCK (2)
tCK
(1)
MIN
MAX
7
8
19
MIN
-10
MAX
7
8
22
-8
1
2.5
3
3
8
10
1
2.5
3
3
10
12
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
25
ns
SYMBOL*
tCKH
tCKS
tCMH
tCMS
tDH
tDS
MIN
1
2.5
1
2.5
1
2.5
tHZ
(3)
(2)
tHZ (1)
tLZ
tOH
MAX
MIN
1
2.5
1
2.5
1
2.5
7
8
19
tHZ
1
2.5
-10
MAX
7
8
22
1
2.5
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 2, the CAS latency = 3, and auto precharge is disabled.
2. x16: A9 and A11 = “Don’t Care”
x32: A8, A9 and A11 = “Don’t Care”
128Mb: x16, x32 Mobile SDRAM
MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02
42
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
ADVANCE
128Mb: x16, x32
MOBILE SDRAM
AUTO REFRESH MODE
T0
CLK
T1
T2
tCK
tCH
tCKS
tCKH
tCMS
tCMH
PRECHARGE
AUTO
REFRESH
NOP
NOP
A0-A9, A11
ALL BANKS
A10
SINGLE BANK
tAS
BA0, BA1
DQ
((
))
((
))
( ( NOP
))
AUTO
REFRESH
NOP
((
))
((
))
DQMU, DQML
To + 1
((
))
((
))
tCL
((
))
CKE
COMMAND
Tn + 1
((
))
((
))
((
))
( ( NOP
))
ACTIVE
((
))
((
))
((
))
((
))
((
))
((
))
ROW
((
))
((
))
((
))
((
))
ROW
tAH
BANK(S)
High-Z
tRP
((
))
((
))
((
))
((
))
((
))
((
))
tRFC1
BANK
tRFC1
Precharge all
active banks
DON’T CARE
TIMING PARAMETERS
-8
SYMBOL*
tAH
tAS
tCH
tCL
tCK (3)
tCK (2)
MIN
1
2.5
3
3
8
10
MAX
MIN
1
2.5
3
3
10
12
-10
MAX
-8
UNITS
ns
ns
ns
ns
ns
ns
SYMBOL*
tCK (1)
tCKH
tCKS
tCMH
tCMS
tRFC
tRP
MIN
20
1
2.5
1
2.5
80
20
MAX
MIN
25
1
2.5
1
2.5
100
20
-10
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
*CAS latency indicated in parentheses.
NOTE: 1. Each AUTO REFRESH command performs a refresh cycle. Back-to-back commands are not required.
128Mb: x16, x32 Mobile SDRAM
MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02
43
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
ADVANCE
128Mb: x16, x32
MOBILE SDRAM
SELF REFRESH MODE
T0
CLK
T1
tCK
tCL
tCH
T2
tCKS
> tRAS
CKE
tCKS
tCMS
COMMAND
Tn + 1
((
))
((
))
tCMH
PRECHARGE
((
))
((
))
AUTO
REFRESH
NOP
((
))
((
))
((
))
A0-A9, A11
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
SINGLE BANK
tAS
BA0, BA1
DQ
AUTO
REFRESH
))
((
))
((
))
ALL BANKS
To + 2
NOP ( (
DQMU, DQML
A10
To + 1
((
))
((
))
((
))
tCKH
((
))
((
))
tAH
BANK(S)
High-Z
((
))
((
))
tRP
Precharge all
active banks
tXSR
Enter self refresh mode
Exit self refresh mode
(Restart refresh time base)
DON’T CARE
CLK stable prior to exiting
self refresh mode
TIMING PARAMETERS
-8
SYMBOL*
tAH
tAS
tCH
tCL
tCK (3)
tCK (2)
tCK (1)
MIN
1
2.5
3
3
8
10
20
MAX
MIN
1
2.5
3
3
10
12
25
-10
MAX
-8
UNITS
ns
ns
ns
ns
ns
ns
ns
SYMBOL*
tCKH
tCKS
tCMH
tCMS
tRAS
tRP
tXSR
MIN
1
2.5
1
2.5
48
20
80
MAX
120,000
MIN
1
2.5
1
2.5
50
20
100
-10
MAX
UNITS
ns
ns
ns
ns
120,000
ns
ns
ns
*CAS latency indicated in parentheses.
128Mb: x16, x32 Mobile SDRAM
MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02
44
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
ADVANCE
128Mb: x16, x32
MOBILE SDRAM
READ – WITHOUT AUTO PRECHARGE
T0
T1
T2
tCK
CLK
T3
T4
T5
NOP
NOP
1
T6
T7
T8
NOP
ACTIVE
tCL
tCH
tCKS
tCKH
CKE
tCMS tCMH
COMMAND
ACTIVE
NOP
READ
tCMS
NOP
PRECHARGE
tCMH
DQMU, DQML
tAS
A0-A9, A11
tAS
COLUMN m2
ROW
tAH
ALL BANKS
ROW
A10
tAS
BA0, BA1
tAH
ROW
ROW
SINGLE BANKS
DISABLE AUTO PRECHARGE
tAH
BANK
BANK
BANK(S)
tAC
tLZ
tRCD
BANK
tAC
tOH
tOH
tOH
tOH
DOUT m
DOUT m+1
DOUT m+2
DOUT m+3
tAC
DQ
tAC
tHZ
tRP
CAS Latency
tRAS
tRC
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-8
SYMBOL*
tAC (3)
tAC (2)
tAC (1)
tAH
tAS
tCH
tCL
tCK (3)
tCK (2)
tCK (1)
tCKH
tCKS
MIN
MAX
7
8
19
1
2.5
3
3
8
10
20
1
2.5
MIN
1
2.5
3
3
10
12
25
1
2.5
-10
MAX
7
8
22
-8
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SYMBOL*
tCMH
tCMS
tHZ (3)
tHZ (2)
tHZ (1)
tLZ
tOH
tRAS
tRC
tRCD
tRP
MIN
1
2.5
MAX
MIN
1
2.5
7
8
19
1
2.5
48
80
20
20
120,000
1
2.5
50
100
20
20
-10
MAX
UNITS
ns
ns
7
ns
8
ns
22
ns
ns
ns
120,000
ns
ns
ns
ns
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 4, the CAS latency = 2, and the READ burst is followed by a “manual”
PRECHARGE.
2. x16: A9 and A11 = “Don’t Care”
x32: A8, A9,and A11 = “Don’t Care”
128Mb: x16, x32 Mobile SDRAM
MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02
45
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
ADVANCE
128Mb: x16, x32
MOBILE SDRAM
READ – WITH AUTO PRECHARGE
T0
T1
T2
tCK
CLK
tCKS
T3
T4
T5
1
T6
T7
T8
NOP
ACTIVE
tCL
tCH
tCKH
CKE
tCMS tCMH
COMMAND
ACTIVE
NOP
READ
tCMS
NOP
NOP
NOP
NOP
tCMH
DQMU, DQML
tAS
A0-A9, A11
tAS
A10
COLUMN m 2
tAH
ROW
ENABLE AUTO PRECHARGE
ROW
tAS
BA0, BA1
tAH
ROW
ROW
tAH
BANK
BANK
BANK
tAC
tOH
tAC
DQ
tLZ
tRCD
DOUT m
tAC
tOH
DOUT m + 1
tAC
tOH
tOH
DOUT m + 2
DOUT m + 3
tHZ
tRP
CAS Latency
tRAS
tRC
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-8
SYMBOL*
tAC (3)
tAC (2)
tAC (1)
tAH
tAS
tCH
tCL
tCK (3)
tCK (2)
tCK (1)
tCKH
tCKS
MIN
MAX
7
8
19
1
2.5
3
3
8
10
20
1
2.5
MIN
1
2.5
3
3
10
12
25
1
2.5
-10
MAX
7
8
22
-8
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SYMBOL*
tCMH
tCMS
tHZ (3)
tHZ (2)
tHZ (1)
tLZ
tOH
tRAS
tRC
tRCD
tRP
MIN
1
2.5
MAX
MIN
1
2.5
7
8
19
1
2.5
48
80
20
20
120,000
1
2.5
50
70
20
20
-10
MAX
UNITS
ns
ns
7
ns
8
ns
22
ns
ns
ns
120,000
ns
ns
ns
ns
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 4, and the CAS latency = 2.
2. x16: A9 and A11 = “Don’t Care”
x32: A8, A9,and A11 = “Don’t Care”
128Mb: x16, x32 Mobile SDRAM
MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02
46
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
ADVANCE
128Mb: x16, x32
MOBILE SDRAM
SINGLE READ – WITHOUT AUTO PRECHARGE
T0
T1
T2
tCK
CLK
T3
T4
T5
NOP 3
NOP 3
1
T6
T7
T8
tCL
tCH
tCKS
tCKH
CKE
tCMS tCMH
COMMAND
ACTIVE
NOP
READ
tCMS
PRECHARGE
ACTIVE
NOP
NOP
tCMH
DQMU, DQML
tAS
A0-A9, A11
tAS
COLUMN m2
ROW
tAH
ALL BANKS
ROW
A10
tAS
BA0, BA1
tAH
ROW
ROW
DISABLE AUTO PRECHARGE
tAH
BANK
SINGLE BANKS
BANK
tOH
tAC
DQ
tLZ
tRCD
BANK
BANK(S)
DOUT m
tHZ
tRP
CAS Latency
tRAS
tRC
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-8
SYMBOL*
tAC (3)
tAC (2)
tAC (1)
tAH
tAS
tCH
tCL
tCK (3)
tCK (2)
tCK (1)
tCKH
tCKS
MIN
MAX
7
8
19
1
2.5
3
3
8
10
20
1
2.5
MIN
1
2.5
3
3
10
12
25
1
2.5
-10
MAX
7
8
22
-8
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SYMBOL*
tCMH
tCMS
tHZ (3)
tHZ (2)
tHZ (1)
tLZ
tOH
tRAS
tRC
tRCD
tRP
MIN
1
2.5
MAX
MIN
1
2.5
7
8
19
1
2.5
48
80
20
20
120,000
1
2.5
50
100
20
20
-10
MAX
UNITS
ns
ns
7
ns
8
ns
22
ns
ns
ns
120,000
ns
ns
ns
ns
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 1, the CAS latency = 2, and the READ burst is followed by a “manual”
PRECHARGE.
2. x16: A9 and A11 = “Don’t Care”
x32: A8, A9,and A11 = “Don’t Care”
3. PRECHARGE command not allowed or tRAS would be violated.
128Mb: x16, x32 Mobile SDRAM
MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02
47
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
ADVANCE
128Mb: x16, x32
MOBILE SDRAM
SINGLE READ – WITH AUTO PRECHARGE
T0
T1
T2
tCK
CLK
tCKS
T3
T4
T5
READ
NOP
1
T6
T7
T8
tCL
tCH
tCKH
CKE
tCMS tCMH
COMMAND
ACTIVE
NOP3
NOP
NOP3
tCMS
NOP
ACTIVE
NOP
tCMH
DQMU, DQML
tAS
A0-A9, A11
tAS
A10
COLUMN m2
tAH
ROW
ENABLE AUTO PRECHARGE
ROW
tAS
BA0, BA1
tAH
ROW
ROW
tAH
BANK
BANK
BANK
tAC
t OH
DOUT m
DQ
tRCD
CAS Latency
tHZ
tRP
tRAS
tRC
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-8
SYMBOL*
tAC (3)
tAC (2)
tAC (1)
tAH
tAS
tCH
tCL
tCK (3)
tCK (2)
tCK (1)
tCKH
tCKS
MIN
MAX
7
8
19
1
2.5
3
3
8
10
20
1
2.5
MIN
1
2.5
3
3
10
12
25
1
2.5
-10
MAX
7
8
22
-8
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SYMBOL*
tCMH
tCMS
tHZ (3)
tHZ (2)
tHZ (1)
tLZ
tOH
tRAS
tRC
tRCD
tRP
MIN
1
2.5
MAX
MIN
1
2.5
7
8
19
1
2.5
48
80
20
20
120,000
1
2.5
50
100
20
20
-10
MAX
UNITS
ns
ns
7
ns
8
ns
22
ns
ns
ns
120,000
ns
ns
ns
ns
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 1, and the CAS latency = 2.
2. x16: A9 and A11 = “Don’t Care”
x32: A8, A9,and A11 = “Don’t Care”
3. READ command not allowed else tRAS would be violated.
128Mb: x16, x32 Mobile SDRAM
MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02
48
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
ADVANCE
128Mb: x16, x32
MOBILE SDRAM
ALTERNATING BANK READ ACCESSES
T0
T1
T2
tCK
CLK
T3
T4
T5
1
T6
T7
T8
READ
NOP
ACTIVE
tCL
tCH
tCKS
tCKH
tCMS
tCMH
CKE
COMMAND
ACTIVE
NOP
READ
tCMS
ACTIVE
NOP
NOP
tCMH
DQMU, DQML
tAS
A0-A9, A11
tAH
COLUMN b 2
ROW
ENABLE AUTO PRECHARGE
ROW
ENABLE AUTO PRECHARGE
ROW
tAS
BA0, BA1
COLUMN m 2
ROW
tAS
A10
tAH
ROW
ROW
tAH
BANK 0
BANK 0
BANK 3
tAC
DQ
DOUT m
tLZ
tRCD - BANK 0
BANK 3
tAC
tOH
tAC
tOH
DOUT m + 1
BANK 0
tAC
tOH
tAC
tOH
DOUT m + 2
DOUT m + 3
DOUT b
tRP - BANK 0
CAS Latency - BANK 0
tAC
tOH
tRCD - BANK 0
tRAS - BANK 0
tRC - BANK 0
tRCD - BANK 3
tRRD
CAS Latency - BANK 3
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-8
SYMBOL*
tAC (3)
tAC (2)
tAC (1)
tAH
tAS
tCH
tCL
tCK (3)
tCK (2)
tCK (1)
tCKH
MIN
MAX
7
8
19
1
2.5
3
3
8
10
20
1
MIN
1
2.5
3
3
10
12
25
1
-10
MAX
7
8
22
-8
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SYMBOL*
tCKS
tCMH
tCMS
tLZ
tOH
tRAS
tRC
tRCD
tRP
tRRD
MIN
2.5
1
2.5
1
2.5
48
80
20
20
20
MAX
120,000
MIN
2.5
1
2.5
1
2.5
50
100
20
20
20
-10
MAX
UNITS
ns
ns
ns
ns
ns
120,000
ns
ns
ns
ns
ns
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 4, and the CAS latency = 2.
2. x16: A9 and A11 = “Don’t Care”
x32: A8, A9,and A11 = “Don’t Care”
128Mb: x16, x32 Mobile SDRAM
MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02
49
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
ADVANCE
128Mb: x16, x32
MOBILE SDRAM
READ – FULL-PAGE BURST
T0
T1
T2
tCL
CLK
T3
T4
T5
1
T6
((
))
((
))
tCK
tCH
tCKS
tCMH
ACTIVE
NOP
READ
tCMS
NOP
NOP
NOP
NOP
tCMH
tAS
tAH
tAH
NOP
BURST TERM
NOP
NOP
((
))
((
))
ROW
tAS
((
))
((
))
((
))
((
))
COLUMN m 2
ROW
tAS
BA0, BA1
Tn + 4
((
))
((
))
DQMU, DQML
A10
Tn + 3
((
))
((
))
tCMS
A0-A9, A11
Tn + 2
tCKH
CKE
COMMAND
Tn + 1
tAH
BANK
((
))
((
))
BANK
tAC
tAC
tOH
DOUT m
DQ
tAC
DOUT m+1
tLZ
tRCD
tAC ( (
tOH ) )
tOH
DOUT
((
))
m+2
((
))
tAC
tAC
tOH
tOH
tOH
DOUT m-1
DOUT m
DOUT m+1
tHZ
512 (x16) locations within same row
CAS Latency
Full page completed
DON’T CARE
Full-page burst does not self-terminate.
3
Can use BURST TERMINATE command.
UNDEFINED
TIMING PARAMETERS
-8
SYMBOL*
tAC (3)
tAC (2)
tAC (1)
tAH
tAS
tCH
tCL
tCK (3)
tCK (2)
tCK (1)
MIN
MAX
7
8
19
1
2.5
3
3
8
10
20
MIN
-10
MAX
7
8
22
1
2.5
3
3
10
12
25
-8
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
SYMBOL*
tCKH
tCKS
tCMH
tCMS
tHZ (3)
tHZ (2)
tHZ (1)
tLZ
tOH
tRCD
ns
MIN
1
2.5
1
2.5
MAX
MIN
1
2.5
1
2.5
7
8
19
1
2.5
20
-10
MAX
7
8
22
1
2.5
20
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the CAS latency = 2.
2. x16: A9 and A11 = “Don’t Care”
x32: A8, A9,and A11 = “Don’t Care”
3. Page left open; no tRP.
128Mb: x16, x32 Mobile SDRAM
MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02
50
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
ADVANCE
128Mb: x16, x32
MOBILE SDRAM
READ – DQM OPERATION
T0
T1
T2
tCK
CLK
tCKS
tCKH
tCMS
tCMH
T3
T4
NOP
NOP
1
T5
T6
T7
T8
NOP
NOP
NOP
tCL
tCH
CKE
COMMAND
ACTIVE
NOP
READ
tCMS
NOP
tCMH
DQMU, DQML
tAS
A0-A9, A11
tAS
A10
COLUMN m 2
tAH
ENABLE AUTO PRECHARGE
ROW
tAS
BA0, BA1
tAH
ROW
DISABLE AUTO PRECHARGE
tAH
BANK
BANK
tAC
DQ
DOUT m
tLZ
tRCD
tAC
tOH
tAC
tOH
tOH
DOUT m + 2
DOUT m + 3
tLZ
tHZ
tHZ
CAS Latency
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-8
SYMBOL*
tAC (3)
tAC (2)
tAC (1)
tAH
tAS
tCH
tCL
tCK (3)
tCK (2)
tCK (1)
MIN
MAX
7
8
19
1
2.5
3
3
8
10
20
MIN
1
2.5
3
3
10
12
25
-10
MAX
7
8
22
-8
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SYMBOL*
tCKH
tCKS
tCMH
tCMS
tHZ (3)
tHZ (2)
tHZ (1)
tLZ
tOH
tRCD
MIN
1
2.5
1
2.5
MAX
MIN
1
2.5
1
2.5
7
8
19
1
2.5
20
-10
MAX
7
8
22
1
2.5
20
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 4, and the CAS latency = 2.
2. x16: A9 and A11 = “Don’t Care”
x32: A8, A9,and A11 = “Don’t Care”
128Mb: x16, x32 Mobile SDRAM
MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02
51
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
ADVANCE
128Mb: x16, x32
MOBILE SDRAM
WRITE – WITHOUT AUTO PRECHARGE
T0
tCK
CLK
T1
T2
tCL
1
T3
T4
T5
T6
T7
T8
T9
NOP
NOP
NOP
NOP
PRECHARGE
NOP
ACTIVE
tCH
tCKS
tCKH
tCMS
tCMH
CKE
COMMAND
ACTIVE
NOP
WRITE
tCMS tCMH
DQMU, DQML
tAS
A0-A9, A11
tAS
A10
COLUMN m 3
ROW
tAH
ALL BANKS
ROW
tAS
BA0, BA1
tAH
ROW
ROW
DISABLE AUTO PRECHARGE
tAH
BANK
SINGLE BANK
BANK
tDS
tDH
DIN m
DQ
BANK
BANK
tDS
tDH
tDS
DIN m + 1
tDH
DIN m + 2
tDS
tDH
DIN m + 3
t WR 2
tRCD
tRAS
tRP
tRC
DON’T CARE
TIMING PARAMETERS
-8
SYMBOL*
tAH
tAS
tCH
tCL
tCK (3)
tCK (2)
tCK (1)
tCKH
tCKS
MAX
1
2.5
3
3
8
10
20
1
2.5
MIN
-10
MAX UNITS
1
2.5
3
3
10
12
25
1
2.5
-8
SYMBOL*
tCMH
tCMS
tDH
tDS
tRAS
tRC
tRCD
tRP
tWR
ns
ns
ns
ns
ns
ns
ns
ns
ns
MIN
1
2.5
1
2.5
48
80
20
20
15
MAX
120,000
MIN
1
2.5
1
2.5
50
100
20
20
15
-10
MAX
UNITS
ns
ns
ns
ns
120,000
ns
ns
ns
ns
ns
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 4, and the WRITE burst is followed by a “manual” PRECHARGE.
2. 15ns is required between <DIN m + 3> and the PRECHARGE command, regardless of frequency.
3. x16: A9 and A11 = “Don’t Care”
x32: A8, A9,and A11 = “Don’t Care”
128Mb: x16, x32 Mobile SDRAM
MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02
52
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
ADVANCE
128Mb: x16, x32
MOBILE SDRAM
WRITE – WITH AUTO PRECHARGE
T0
tCK
CLK
tCKS
tCKH
tCMS
tCMH
T1
T2
tCL
1
T3
T4
T5
T6
T7
T8
T9
NOP
NOP
NOP
NOP
NOP
NOP
ACTIVE
tCH
CKE
COMMAND
ACTIVE
NOP
WRITE
tCMS tCMH
DQMU, DQML
tAS
A0-A9, A11
tAS
A10
COLUMN m 2
tAH
ROW
ENABLE AUTO PRECHARGE
ROW
tAS
BA0, BA1
tAH
ROW
ROW
tAH
BANK
BANK
tDS
BANK
tDH
DIN m
DQ
tDS
tDH
DIN m + 1
tDS
tDH
DIN m + 2
tRCD
tRAS
tDS
tDH
DIN m + 3
tWR
tRP
tRC
DON’T CARE
TIMING PARAMETERS
-8
SYMBOL*
tAH
tAS
tCH
tCL
tCK (3)
tCK (2)
tCK (1)
tCKH
tCKS
tCMH
MIN
1
2.5
3
3
8
10
20
1
2.5
1
MAX
MIN
1
2.5
3
3
10
12
25
1
2.5
1
-10
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SYMBOL*
tCMS
tDH
tDS
tRAS
tRC
tRCD
tRP
tWR
-8
-10
MIN
MAX
MIN
MAX UNITS
2.5
2.5
ns
1
1
ns
2.5
2.5
ns
48
120,000
50
120,000
ns
80
100
ns
20
20
ns
20
20
ns
1 CLK +
1 CLK +
–
7ns
5ns
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 4.
2. x16: A9 and A11 = “Don’t Care”
x32: A8, A9,and A11 = “Don’t Care”
128Mb: x16, x32 Mobile SDRAM
MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02
53
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
ADVANCE
128Mb: x16, x32
MOBILE SDRAM
1
SINGLE WRITE – WITHOUT AUTO PRECHARGE
T0
tCK
CLK
T1
T2
tCL
T3
T4
NOP 4
NOP 4
T5
T6
T7
T8
ACTIVE
NOP
tCH
tCKS
tCKH
tCMS
tCMH
CKE
COMMAND
ACTIVE
NOP
WRITE
PRECHARGE
NOP
tCMS tCMH
DQMU, DQML
tAS
A0-A9, A11
tAH
ALL BANKS
ROW
tAS
BA0, BA1
COLUMN m 3
ROW
tAS
A10
tAH
ROW
tAH
DISABLE AUTO PRECHARGE
SINGLE BANK
BANK
BANK
BANK
tDS
BANK
tDH
DIN m
DQ
tRCD
tRAS
tRP
t WR 2
tRC
DON’T CARE
TIMING PARAMETERS
-8
SYMBOL*
tAH
tAS
tCH
tCL
tCK (3)
tCK (2)
tCK (1)
tCKH
tCKS
MIN
1
2.5
3
3
8
10
20
1
2.5
MAX
MIN
1
2.5
3
3
10
12
25
1
2.5
-10
MAX
-8
SYMBOL*
tCMH
tCMS
tDH
tDS
tRAS
tRC
tRCD
tRP
tWR
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
MIN
1
2.5
1
2.5
48
80
20
20
15
MAX
120,000
MIN
1
2.5
1
2.5
50
100
20
20
15
-10
MAX
UNITS
ns
ns
ns
ns
120,000
ns
ns
ns
ns
ns
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 1, and the WRITE burst is followed by a “manual” PRECHARGE.
2. 15ns is required between <DIN m> and the PRECHARGE command, regardless of frequency.
3. x16: A9 and A11 = “Don’t Care”
x32: A8, A9,and A11 = “Don’t Care”
4. PRECHARGE command not allowed else tRAS would be violated.
128Mb: x16, x32 Mobile SDRAM
MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02
54
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
ADVANCE
128Mb: x16, x32
MOBILE SDRAM
1
SINGLE WRITE – WITH AUTO PRECHARGE
T0
tCK
CLK
tCKS
tCKH
tCMS
tCMH
T1
tCL
T2
T3
T4
T5
T6
T7
NOP3
WRITE
NOP
NOP
NOP
T8
T9
tCH
CKE
COMMAND
NOP3
ACTIVE
NOP3
tCMS
ACTIVE
NOP
tCMH
DQMU, DQML
tAS
A0-A9, A11
tAS
A10
COLUMN m 2
tAH
ROW
ENABLE AUTO PRECHARGE
ROW
tAS
BA0, BA1
tAH
ROW
ROW
tAH
BANK
BANK
tDS
BANK
tDH
DIN m
DQ
tRCD
tRAS
tRP
tWR
tRC
DON’T CARE
TIMING PARAMETERS
-8
SYMBOL*
tAH
tAS
tCH
tCL
tCK (3)
tCK (2)
tCK (1)
tCKH
tCKS
tCMH
MIN
1
2.5
3
3
8
10
20
1
2.5
1
MAX
MIN
1
2.5
3
3
10
12
25
1
2.5
1
-10
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SYMBOL*
tCMS
tDH
tDS
tRAS
tRC
tRCD
tRP
tWR
-8
-10
MIN
MAX
MIN
MAX UNITS
2.5
2.5
ns
1
1
ns
2.5
2.5
ns
48
120,000
50
120,000
ns
80
100
ns
20
20
ns
20
20
ns
1 CLK +
1 CLK +
–
7ns
5ns
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 1.
2. x16: A9 and A11 = “Don’t Care”
x32: A8, A9,and A11 = “Don’t Care”
3. WRITE command not allowed else tRAS would be violated.
128Mb: x16, x32 Mobile SDRAM
MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02
55
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
ADVANCE
128Mb: x16, x32
MOBILE SDRAM
1
ALTERNATING BANK WRITE ACCESSES
T0
tCK
CLK
T1
T2
tCL
T3
T4
T5
T6
T7
T8
T9
NOP
NOP
ACTIVE
tCH
tCKS
tCKH
tCMS
tCMH
CKE
COMMAND
ACTIVE
NOP
WRITE
tCMS
NOP
ACTIVE
NOP
WRITE
tCMH
DQMU, DQML
tAS
A0-A9, A11
tAS
A10
COLUMN m 2
tAH
COLUMN b 2
ROW
ENABLE AUTO PRECHARGE
ROW
ENABLE AUTO PRECHARGE
ROW
tAS
BA0, BA1
tAH
ROW
ROW
ROW
tAH
BANK 0
BANK 0
tDS
tDH
DIN m
DQ
BANK 1
tDS
tDH
DIN m + 1
tDS
BANK 1
tDH
tDS
DIN m + 2
tDH
DIN m + 3
tDS
tDH
DIN b
tWR - BANK 0
tRCD - BANK 0
BANK 0
tDS
tDH
DIN b + 1
tRP - BANK 0
tDS
tDH
DIN b + 2
tDS
tDH
DIN b + 3
tRCD - BANK 0
tRAS - BANK 0
tRC - BANK 0
tRCD - BANK 1
tRRD
tWR - BANK 1
DON’T CARE
TIMING PARAMETERS
-8
SYMBOL*
tAH
tAS
tCH
tCL
tCK (3)
tCK (2)
tCK (1)
tCKH
tCKS
tCMH
MIN
1
2.5
3
3
8
10
20
1
2.5
1
MAX
MIN
1
2.5
3
3
10
12
25
1
2.5
1
-10
MAX
SYMBOL*
tCMS
tDH
tDS
tRAS
tRC
tRCD
tRP
tRRD
tWR
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
-8
-10
MIN
MAX
MIN
MAX UNITS
2.5
2.5
ns
1
1
ns
2.5
2.5
ns
48
120,000
50
120,000
ns
80
100
ns
20
20
ns
20
20
ns
20
20
ns
1 CLK +
1 CLK +
–
7ns
5ns
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 4.
2. x16: A9 and A11 = “Don’t Care”
x32: A8, A9,and A11 = “Don’t Care”
128Mb: x16, x32 Mobile SDRAM
MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02
56
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
ADVANCE
128Mb: x16, x32
MOBILE SDRAM
WRITE – FULL-PAGE BURST
T0
T1
T2
tCL
CLK
T3
T4
T5
((
))
((
))
tCK
tCH
tCKS
tCKH
tCMS
tCMH
ACTIVE
NOP
WRITE
NOP
NOP
NOP
tCMS tCMH
tAS
((
))
((
))
NOP
BURST TERM
NOP
((
))
((
))
COLUMN m 1
tAH
((
))
((
))
ROW
tAS
BA0, BA1
tAH
ROW
tAS
A10
Tn + 3
((
))
((
))
DQMU, DQML
A0-A9, A11
Tn + 2
((
))
((
))
CKE
COMMAND
Tn + 1
tAH
BANK
((
))
((
))
BANK
tDS
tDH
DIN m
DQ
tDS
tDH
DIN m + 1
tDS
tDH
DIN m + 2
tRCD
tDS
tDH
DIN m + 3
((
))
((
))
tDS
tDH
DIN m - 1
Full-page burst does not
self-terminate. Can use
BURST TERMINATE
command to stop.2, 3
512 (x16) locations within same row
Full page completed
DON’T CARE
TIMING PARAMETERS
-8
SYMBOL*
tAH
tAS
tCH
tCL
tCK (3)
tCK (2)
tCK (1)
MIN
1
2.5
3
3
8
10
20
MAX
MIN
1
2.5
3
3
10
12
25
-10
MAX
-8
UNITS
ns
ns
ns
ns
ns
ns
ns
SYMBOL*
tCKH
tCKS
tCMH
tCMS
tDH
tDS
tRCD
MIN
1
2.5
1
2.5
1
2.5
20
MAX
MIN
1
2.5
1
2.5
1
2.5
20
-10
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
*CAS latency indicated in parentheses.
NOTE: 1. x16: A9 and A11 = “Don’t Care”
x32: A8, A9,and A11 = “Don’t Care”
2. tWR must be satisfied prior to PRECHARGE command.
3. Page left open; no tRP.
128Mb: x16, x32 Mobile SDRAM
MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02
57
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
ADVANCE
128Mb: x16, x32
MOBILE SDRAM
WRITE – DQM OPERATION
T0
T1
tCK
CLK
T2
1
T3
T4
T5
NOP
NOP
NOP
T6
T7
NOP
NOP
tCL
tCH
tCKS
tCKH
tCMS
tCMH
CKE
COMMAND
ACTIVE
NOP
WRITE
tCMS tCMH
DQMU, DQML
tAS
A0-A9, A11
tAS
A10
COLUMN m 2
tAH
ENABLE AUTO PRECHARGE
ROW
tAS
BA0, BA1
tAH
ROW
tAH
DISABLE AUTO PRECHARGE
BANK
BANK
tDS
tDH
tDS
DIN m
DQ
tDH
DIN m + 2
tDS
tDH
DIN m + 3
tRCD
DON’T CARE
TIMING PARAMETERS
-8
SYMBOL*
tAH
tAS
tCH
tCL
tCK (3)
tCK (2)
tCK (1)
MIN
1
2.5
3
3
8
10
20
MAX
MIN
1
2.5
3
3
10
12
25
-10
MAX
-8
UNITS
ns
ns
ns
ns
ns
ns
ns
SYMBOL*
tCKH
tCKS
tCMH
tCMS
tDH
tDS
tRCD
MIN
1
2.5
1
2.5
1
2.5
20
MAX
MIN
1
2.5
1
2.5
1
2.5
20
-10
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 4.
2. x16: A9 and A11 = “Don’t Care”
x32: A8, A9,and A11 = “Don’t Care”
128Mb: x16, x32 Mobile SDRAM
MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02
58
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
ADVANCE
128Mb: x16, x32
MOBILE SDRAM
54-BALL VFBGA (8mm x 9mm)
0.70 ±0.075
SEATING PLANE
C
0.08 C
54X ∅0.35
SOLDER BALL DIAMETER
REFERS TO POST REFLOW
CONDITION. THE PREREFLOW DIAMETER IS Ø 0.33
BALL A9
6.40
0.80
TYP
BALL A1 ID
BALL A1
1.0 MAX
BALL A1 ID
0.80
TYP
6.40
9.00 ±0.10
CL
3.20 ±0.05
4.50 ±0.05
CL
3.20 ±0.05
4.00 ±0.05
MOLD COMPOUND: EPOXY NOVOLAC
SUBSTRATE: PLASTIC LAMINATE
8.00 ±0.10
SOLDER BALL MATERIAL: EUTECTIC 63% Sn, 37% Pb or
62% Sn, 36% Pb, 2%Ag
SOLDER BALL PAD: Ø .27mm
NOTE: 1. All dimensions in millimeters.
2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side.
128Mb: x16, x32 Mobile SDRAM
MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02
59
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
ADVANCE
128Mb: x16, x32
MOBILE SDRAM
90-BALL FBGA (11mm x 13mm)
.850 ±.075
.10
C
SEATING PLANE
C
SOLDER BALL MATERIAL: EUTECTIC 63% Sn, 37% Pb.
Or 62% Sn, 36% Pb, 2% Ag
SOLDER BALL PAD: Ø .33mm
11.00 ±.10
90X Ø 0.45
SOLDER BALL DIAMETER REFERS
TO POST REFLOW CONDITION.
THE PRE-REFLOW DIAMETER IS Ø 0.40mm
SUBSTRATE: PLASTIC LAMINATE
ENCAPSULATION MATERIAL: EPOXY NOVOLAC
BALL A1 ID
6.40
.80
TYP
BALL A1 ID
BALL A9
BALL A1
6.50 ±.05
13.00 ± .10
CL
11.20
.80
TYP
5.60 ±.05
CL
3.20 ±.05
1.20 MAX
5.50 ±.05
(Bottom View)
NOTE: 1. All dimensions in millimeters.
2. Recommended pad size for PCB is 0.33mm±0.025mm.
128Mb: x16, x32 Mobile SDRAM
MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02
60
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
ADVANCE
128Mb: x16, x32
MOBILE SDRAM
FBGA DEVICE MARKING
DBFCF
Due to the size of the package, Micron’s standard part
number is not printed on the top of each device. Instead,
an abbreviated device mark comprised of a five-digit
alphanumeric code is used. The abbreviated device marks
are cross referenced to Micron part numbers in Table 1.
Speed Grade
B = -10
C = -8
Width ( I/Os)
D = x16
G = x32
Device Density
F = 128Mb
Product Type
N = 2.5V SDR SDRAM, Low Power version (54-ball, 8 x 9)
P = 3.3V SDR SDRAM, Low Power version (54-ball, 8 x 9)
V = 2.5V SDR SDRAM, Low Power version (90-ball, 11 x 13)
Z = 3.3V SDR SDRAM, Low Power version (90-ball, 11 x 13)
Product Group
D = DRAM
Z = DRAM ENGINEERING SAMPLE
CROSS REFERENCE FOR FBGA OR VFBGA DEVICE MARKING
ENGINEERING
PART NUMBER
ARCHITECTURE
FBGA/VFBGA
MT48V4M32LFFC-8
MT48LC4M32LFFC-10
MT48V8M16LFFF-10
MT48LC8M16LFFF-8
4 Meg x 32
4 Meg x 32
8 Meg x 16
8 Meg x 16
90-pin, 11 x 13
90-pin, 11 x 13
54-ball, 8 x 9
54-ball, 8 x 9
PRODUCTION
SAMPLE
MARKING
ZVFGC
ZZFGB
ZNFDB
ZPFDC
DVFGC
DZFGB
DNFDB
DPFDC
DATA SHEET DESIGNATION
Advance: This data sheet contains initial descriptions of products still under development.
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
E-mail: [email protected], Internet: http://www.micron.com, Customer Comment Line: 800-932-4992
Micron and the M logo are registered trademarks and the Micron logo is a trademark of Micron Technology, Inc.
128Mb: x16, x32 Mobile SDRAM
MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02
61
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.