256Mb: x4, x8, x16 SDRAM SYNCHRONOUS DRAM MT48LC64M4A2 – 16 Meg x 4 x 4 banks MT48LC32M8A2 – 8 Meg x 8 x 4 banks MT48LC16M16A2 – 4 Meg x 16 x 4 banks For the latest data sheet, please refer to the Micron Web site: www.micron.com/dramds Features Figure 1: Pin Assignment (Top View) 54-Pin TSOP • PC66-, PC100-, and PC133-compliant • Fully synchronous; all signals registered on positive edge of system clock • Internal pipelined operation; column address can be changed every clock cycle • Internal banks for hiding row access/precharge • Programmable burst lengths: 1, 2, 4, 8, or full page • Auto Precharge, includes CONCURRENT AUTO PRECHARGE, and Auto Refresh Modes • Self Refresh Mode • 64ms, 8,192-cycle refresh • LVTTL-compatible inputs and outputs • Single +3.3V ±0.3V power supply Options - TG P FB4, 5 FG3 BB4, 5 BG3 • Timing (Cycle Time) 7.5ns @ CL = 2 (PC133) 7.5ns @ CL = 3 (PC133) -7E -75 • Die Revision :D • Self Refresh Standard Low power None L3 • Operating Temperature Commercial (0oC to +70oC) Industrial (-40oC to +85oC) None IT3 - NC NC NC DQ2 - - NC NC DQ1 DQ3 A2 • Package/Pinout 54-pin TSOP II OCPL2 (400 mil) (standard) 54-pin TSOP II OCPL2 (400 mil) (lead-free) 60-ball FBGA (x4, x8) 54-ball VFBGA (x16) 60-ball FBGA (x4, x8) (lead-free) 54-ball VFBGA (x16) (lead-free) - NC NC DQ0 DQ1 64M4 32M8 16M16 • WRITE Recovery (tWR) t WR = “2 CLK”1 - NC DQ0 Marking • Configurations 64 Meg x 4 (16 Meg x 4 x 4 banks) 32 Meg x 8 ( 8 Meg x 8 x 4 banks) 16 Meg x 16 ( 4 Meg x 16 x 4 banks) NOTE: 1. 2. 3. 4. 5. x4 x8 x16 - - NC NC - - NC NC - - Note: VDD DQ0 VDDQ DQ1 DQ2 VssQ DQ3 DQ4 VDDQ DQ5 DQ6 VssQ DQ7 VDD DQML WE# CAS# RAS# CS# BA0 BA1 A10 A0 A1 A2 A3 VDD x16 x8 x4 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 Vss DQ15 DQ7 VssQ DQ14 NC DQ13 DQ6 VDDQ DQ12 NC DQ11 DQ5 VssQ DQ10 NC DQ9 DQ4 VDDQ DQ8 NC Vss NC DQMH DQM CLK CKE A12 A11 A9 A8 A7 A6 A5 A4 Vss - NC NC DQ3 NC NC NC DQ2 NC DQM - The # symbol indicates signal is active LOW. A dash (–) indicates x8 and x4 pin function is same as x16 pin function. Table 1: Address Table 64 Meg x 4 32 Meg x 8 16 Meg x 16 Configuration 16 Meg x 4 x 4 banks 8 Meg x 8 x 4 banks 4 Meg x 16 x 4 banks Refresh Count 8K 8K 8K Row Addressing 8K (A0–A12) 8K (A0–A12) 8K (A0–A12) Bank Addressing 4 (BA0, BA1) 4 (BA0, BA1) 4 (BA0, BA1) Column Addressing 2K (A0–A9, A11) 1K (A0–A9) 512 (A0–A8) Table 2: Key Timing Parameters SPEED GRADE -7E -75 -7E -75 Refer to Micron Technical Note TN-48-05. Off-center parting line. Consult Micron for availability. Not available in x16 configuration. Actual FBGA part marking shown on page 60. CLOCK ACCESS TIME FREQUENCY CL = 2* CL = 3* 143 MHz 133 MHz 133 MHz 100 MHz – – 5.4ns 6ns 5.4ns 5.4ns – – SETUP TIME HOLD TIME 1.5ns 1.5ns 1.5ns 1.5ns 0.8ns 0.8ns 0.8ns 0.8ns *CL = CAS (READ) latency Part Number Example: MT48LC16M16A2TG-75 PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8 256MSDRAM.pmd – Rev. H; Pub. 2/05 1 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. 256Mb: x4, x8, x16 SDRAM Figure 2: 60-Ball FBGA Assignment (Top View) 64 Meg x 4 SDRAM 8mm x 16mm “FB” 32 Meg x 8 SDRAM 8mm x 16mm “FB” 7 8 Vss VDD DQ0 NC VssQ VDDQ NC C VDDQ DQ6 DQ1 VssQ NC D DQ5 NC NC DQ2 VDDQ NC E NC VssQ VDDQ NC DQ2 DQ1 VssQ F VDDQ DQ4 DQ3 VssQ NC NC NC NC G NC NC NC NC H NC Vss VDD NC H NC Vss VDD NC J NC DQM WE# CAS# J NC DQM WE# CAS# K NC CK RAS# NC K NC CK RAS# NC L A12 CKE NC CS# L A12 CKE NC CS# M A11 A9 BA1 BA0 M A11 A9 BA1 BA0 N A8 A7 A0 A10 N A8 A7 A0 A10 P A6 A5 A2 A1 P A6 A5 A2 A1 R A4 Vss VDD A3 R A4 Vss VDD A3 1 2 A DQ7 NC B DQ0 VssQ NC NC NC VssQ F VDDQ G 7 8 Vss VDD NC NC VssQ VDDQ C VDDQ DQ3 D NC E 1 2 A NC B 3 4 5 6 3 4 5 6 Depopulated Balls Depopulated Balls NOTE: FBGA pin Symbol, Type, and Descriptions are identical to the listing of the 54-pin TSOP table on page 9. PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8 256MSDRAM.pmd – Rev. H; Pub. 2/05 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 256Mb: x4, x8, x16 SDRAM Figure 3: 54-Ball FBGA Assignment (Top View) 16 Meg x 16 SDRAM 8mm x 14mm “FG” 7 8 9 VSSQ VDDQ DQ0 VDD DQ13 VDDQ VssQ DQ2 DQ1 DQ12 DQ11 VSSQ VDDQ DQ4 DQ3 DQ10 DQ9 VDDQ VSSQ DQ6 DQ5 1 2 3 A Vss DQ15 B DQ14 C D 4 5 6 E DQ8 NC Vss VDD LDQM DQ7 F UDQM CLK CKE CAS# RAS# WE# G A12 A11 A9 BA0 BA1 CS# H A8 A7 A6 A0 A1 A10 J Vss A5 A4 A3 A2 VDD Depopulated Balls PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8 256MSDRAM.pmd – Rev. H; Pub. 2/05 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 256Mb: x4, x8, x16 SDRAM tration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select the bank; A0–A12 select the row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. The SDRAM provides for programmable READ or WRITE burst lengths of 1, 2, 4, or 8 locations, or the full page, with a burst terminate option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. The 256Mb SDRAM uses an internal pipelined architecture to achieve high-speed operation. This architecture is compatible with the 2n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a highspeed, fully random access. Precharging one bank while accessing one of the other three banks will hide the precharge cycles and provide seamless, highspeed, random-access operation. The 256Mb SDRAM is designed to operate in 3.3V memory systems. An auto refresh mode is provided, along with a power-saving, power-down mode. All inputs and outputs are LVTTL-compatible. SDRAMs offer substantial advances in DRAM operating performance, including the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks to hide precharge time and the capability to randomly change column addresses on each clock cycle during a burst access. Table 3: 256 Mb SDRAM Part Numbers PART NUMBER MT48LC64M4A2TG MT48LC64M4A2P MT48LC64M4A2FB* MT48LC64M4A2BB* MT48LC32M8A2TG MT48LC32M8A2P MT48LC32M8A2FB* MT48LC32M8A2BB* MT48LC16M16A2TG MT48LC16M16A2P MT48LC16M16A2FG MT48LC16M16A2BG ARCHITECTURE 64 Meg x 4 64 Meg x 4 64 Meg x 4 64 Meg x 4 32 Meg x 8 32 Meg x 8 32 Meg x 8 32 Meg x 8 16 Meg x 16 16 Meg x 16 16 Meg x 16 16 Meg x 16 PACKAGE 54-pin TSOP II 54-pin TSOP II 60-ball FBGA 60-ball FBGA 54-pin TSOP II 54-pin TSOP II 60-ball FBGA 60-ball FBGA 54-pin TSOP II 54-pin TSOP II 54-ball FBGA 54-ball FBGA *Actual FBGA part marking shown on pages 60 and 61. General Description The 256Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 268,435,456 bits. It is internally configured as a quadbank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x4’s 67,108,864-bit banks is organized as 8,192 rows by 2,048 columns by 4 bits. Each of the x8’s 67,108,864-bit banks is organized as 8,192 rows by 1,024 columns by 8 bits. Each of the x16’s 67,108,864-bit banks is organized as 8,192 rows by 512 columns by 16 bits. Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the regis- PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8 256MSDRAM.pmd – Rev. H; Pub. 2/05 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 256Mb: x4, x8, x16 SDRAM Table of Contents Functional Block Diagram – 64 Meg x 4 .................... 6 Functional Block Diagram – 32 Meg x 8 .................... 7 Functional Block Diagram – 16 Meg x 16 .................. 8 Pin Descriptions .......................................................... 10 Ball Descriptions .......................................................... 10 Functional Description ............................................... Initialization ........................................................... Register Definition ................................................ Mode Register ................................................... Burst Length ................................................ Burst Type ................................................... CAS Latency ................................................ Operating Mode .......................................... Write Burst Mode ........................................ Commands ................................................................... Truth Table 1 (Commands and DQM Operation) .............. Command Inhibit .................................................. No Operation (NOP) .............................................. Load mode register ................................................ Active ....................................................................... Read ....................................................................... Write ....................................................................... Precharge ................................................................ Auto Precharge ....................................................... Burst Terminate ..................................................... Auto Refresh ........................................................... Self Refresh ............................................................. Operation ..................................................................... Bank/Row Activation ............................................. Reads ....................................................................... Writes ....................................................................... Precharge ................................................................ Power-Down ........................................................... Clock Suspend ........................................................ Burst Read/Single Write ....................................... PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8 256MSDRAM.pmd – Rev. H; Pub. 2/05 Concurrent Auto Precharge ................................. Truth Table 2 (CKE) ...................................................... Truth Table 3 (Current State, Same Bank) ........................ Truth Table 4 (Current State, Different Bank) .................. Absolute Maximum Ratings ....................................... DC Electrical Characteristics and Operating Conditions ....................................... IDD Specifications and Conditions ............................. Capacitance .................................................................. Electrical Characteristics and Recommended AC Operating Conditions ....... 12 12 12 12 12 13 14 14 14 15 15 16 16 16 16 16 16 16 16 17 17 17 18 18 19 25 27 27 28 28 29 31 32 34 36 36 36 37 37 AC Electrical Characteristics (Timing Table) ......... 38 Timing Waveforms Initialize and Load mode register ........................ Power-Down Mode ................................................ Clock Suspend Mode ............................................ Auto Refresh Mode ................................................ Self Refresh Mode .................................................. Reads Read – Without Auto Precharge ..................... Read – With Auto Precharge ........................... Single Read – Without Auto Precharge ......... Single Read – With Auto Precharge ............... Alternating Bank Read Accesses .................... Read – Full-Page Burst .................................... Read – DQM Operation ................................... Writes Write – Without Auto Precharge ..................... Write – With Auto Precharge ........................... Single Write - Without Auto Precharge ......... Single Write - With Auto Precharge ................ Alternating Bank Write Accesses ................... Write – Full-Page Burst .................................... Write – DQM Operation ................................... 5 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 256Mb: x4, x8, x16 SDRAM Figure 4: Functional Block Diagram 64 Meg x 4 SDRAM CKE CLK COMMAND DECODE CS# WE# CAS# RAS# CONTROL LOGIC BANK3 BANK2 BANK1 MODE REGISTER REFRESH 13 COUNTER 12 ROWADDRESS MUX 13 13 BANK0 ROWADDRESS LATCH & DECODER 8192 BANK0 MEMORY ARRAY (8,192 x 2,048 x 4) 1 DQM SENSE AMPLIFIERS 4 8192 I/O GATING DQM MASK LOGIC READ DATA LATCH WRITE DRIVERS 2 A0-A12, BA0, BA1 15 ADDRESS REGISTER 2 BANK CONTROL LOGIC DATA OUTPUT REGISTER 4 4 2048 (x4) 1 DQ0DQ3 DATA INPUT REGISTER COLUMN DECODER 11 PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8 256MSDRAM.pmd – Rev. H; Pub. 2/05 COLUMNADDRESS COUNTER/ LATCH 11 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 256Mb: x4, x8, x16 SDRAM Figure 5: Functional Block Diagram 32 Meg x 8 SDRAM CKE CLK COMMAND DECODE CS# WE# CAS# RAS# CONTROL LOGIC BANK3 BANK2 BANK1 MODE REGISTER REFRESH 13 COUNTER 12 ROWADDRESS MUX 13 13 BANK0 ROWADDRESS LATCH & DECODER 8192 BANK0 MEMORY ARRAY (8,192 x 1,024 x 8) 1 DQM SENSE AMPLIFIERS 8 8192 I/O GATING DQM MASK LOGIC READ DATA LATCH WRITE DRIVERS 2 A0-A12, BA0, BA1 15 ADDRESS REGISTER 2 BANK CONTROL LOGIC DATA OUTPUT REGISTER 8 8 1024 (x8) 1 DQ0DQ7 DATA INPUT REGISTER COLUMN DECODER 10 PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8 256MSDRAM.pmd – Rev. H; Pub. 2/05 COLUMNADDRESS COUNTER/ LATCH 10 7 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 256Mb: x4, x8, x16 SDRAM Figure 6: Functional Block Diagram 16 Meg x 16 SDRAM CKE CLK COMMAND DECODE CS# WE# CAS# RAS# CONTROL LOGIC BANK3 BANK2 BANK1 MODE REGISTER REFRESH 13 COUNTER 12 ROWADDRESS MUX 13 13 BANK0 ROWADDRESS LATCH & DECODER 8192 BANK0 MEMORY ARRAY (8,192 x 512 x 16) 2 DQML, DQMH SENSE AMPLIFIERS 16 8192 I/O GATING DQM MASK LOGIC READ DATA LATCH WRITE DRIVERS 2 A0-A12, BA0, BA1 15 ADDRESS REGISTER 2 BANK CONTROL LOGIC DATA OUTPUT REGISTER 16 16 512 (x16) 2 DQ0DQ15 DATA INPUT REGISTER COLUMN DECODER 9 PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8 256MSDRAM.pmd – Rev. H; Pub. 2/05 COLUMNADDRESS COUNTER/ LATCH 9 8 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 256Mb: x4, x8, x16 SDRAM Table 4: Pin Descriptions (54-pin TSOP) 54-PIN TSOP SYMBOL TYPE 38 CLK Input Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers. DESCRIPTION 37 CKE Input Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. Deactivating the clock provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all banks idle), ACTIVE POWER-DOWN (row active in any bank) or CLOCK SUSPEND operation (burst/access in progress). CKE is synchronous except after the device enters power-down and self refresh modes, where CKE becomes asynchronous until after exiting the same mode. The input buffers, including CLK, are disabled during power-down and self refresh modes, providing low standby power. CKE may be tied HIGH. 19 CS# Input Chip Select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when CS# is registered HIGH. CS# provides for external bank selection on systems with multiple banks. CS# is considered part of the command code. 16, 17, 18 WE#, CAS#, RAS# Input Command Inputs: WE#, CAS#, and RAS# (along with CS#) define the command being entered. 39 x4, x8: DQM Input 15, 39 x16: DQML, DQMU Input/Output Mask: DQM is an input mask signal for write accesses and an output enable signal for read accesses. Input data is masked when DQM is sampled HIGH during a WRITE cycle. The output buffers are placed in a High-Z state (two-clock latency) when DQM is sampled HIGH during a READ cycle. On the x4 and x8, DQML (Pin 15) is a NC and DQMH is DQM. On the x16, DQML corresponds to DQ0DQ7 and DQMH corresponds to DQ8-DQ15. DQML and DQMH are considered same state when referenced as DQM. 20, 21 BA0, BA1 Input Bank Address Inputs: BA0 and BA1 define to which bank the ACTIVE, READ, WRITE or PRECHARGE command is being applied. 23-26, 29-34, 22, 35, 36 A0-A12 Input Address Inputs: A0-A12 are sampled during the ACTIVE command (rowaddress A0-A12) and READ/WRITE command (column-address A0-A9, A11 [x4]; A0-A9 [x8]; A0-A8 [x16]; with A10 defining auto precharge) to select one location out of the memory array in the respective bank. A10 is sampled during a PRECHARGE command to determine if all banks are to be precharged (A10 [HIGH]) or bank selected by (A10 [LOW]). The address inputs also provide the op-code during a LOAD MODE REGISTER command. 2, 4, 5, 7, 8, 10, 11, 13, 42, DQ0-DQ15 x16: I/O Data Input/Output: Data bus for x16 (4, 7, 10, 13, 42, 45, 48, and 51 44, 45, 47, 48, 50, 51, 53 are NCs for x8; and 2, 4, 7, 8, 10, 13, 42, 45, 47, 48, 51, and 53 are NCs for x4). 2, 5, 8, 11, 44, 47, 50, 53 DQ0-DQ7 x8: I/O Data Input/Output: Data bus for x8 (2, 8, 47, 53 are NCs for x4). 5, 11, 44, 50 DQ0-DQ3 x4: I/O Data Input/Output: Data bus for x4. 40 NC – No Connect: This pin should be left unconnected. 3, 9, 43, 49 6, 12, 46, 52 V DD Q VSSQ 1, 14, 27 VDD Supply Power Supply: +3.3V ±0.3V. 28, 41, 54 VSS Supply Ground. PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8 256MSDRAM.pmd – Rev. H; Pub. 2/05 Supply DQ Power: DQ power to the die for improved noise immunity. Supply DQ Ground: DQ ground to the die for improved noise immunity. 9 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 256Mb: x4, x8, x16 SDRAM Table 5: Ball Descriptions (54-Ball FBGA) 54-BALL FBGA SYMBOL TYPE F2 CLK Input Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers. DESCRIPTION F3 CKE Input Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. Deactivating the clock provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all banks idle), ACTIVE POWER-DOWN (row active in any bank) or CLOCK SUSPEND operation (burst/access in progress). CKE is synchronous except after the device enters power-down and self refresh modes, where CKE becomes asynchronous until after exiting the same mode. The input buffers, including CLK, are disabled during power-down and self refresh modes, providing low standby power. CKE may be tied HIGH. G9 CS# Input Chip Select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when CS# is registered HIGH. CS# provides for external bank selection on systems with multiple banks. CS# is considered part of the command code. F7, F8, F9 CAS#, RAS#, WE# Input Command Inputs: CAS#, RAS#, and WE# (along with CS#) define the command being entered. E8, F1 LDQM, UDQM Input Input/Output Mask: DQM is sampled HIGH and is an input mask signal for write accesses and an output enable signal for read accesses. Input data is masked during a WRITE cycle. The output buffers are placed in a High-Z state (two-clock latency) when during a READ cycle. LDQM corresponds to DQ0–DQ7, UDQM corresponds to DQ8–DQ15. LDQM and UDQM are considered same state when referenced as DQM. G7, G8 BA0, BA1 Input Bank Address Input(s): BA0 and BA1 define to which bank the ACTIVE, READ, WRITE or PRECHARGE command is being applied. These pins also provide the op-code during a LOAD MODE REGISTER command H7, H8, J8, J7, J3, J2, H3, H2, H1, G3, H9, G2, G1 A0–A12 Input Address Inputs: A0–A12 are sampled during the ACTIVE command (rowaddress A0–A11) and READ/WRITE command (column-address A0–A8; with A10 defining auto precharge) to select one location out of the memory array in the respective bank. A10 is sampled during a PRECHARGE command to determine if all banks are to be precharged (A10 HIGH) or bank selected by BA0, BA1 (LOW). The address inputs also provide the op-code during a LOAD MODE REGISTER command. A8, B9, B8, C9, C8, D9, D8, E9, E1, D2, D1, C2, C1, B2, B1, A2 DQ0–DQ15 I/O Data Input/Output: Data bus E2 NC – A7, B3, C7, D3 VDDQ Supply DQ Power: DQ power to the die for improved noise immunity. A3, B7, C3, D7 V SS Q Supply DQ Ground: DQ ground to the die for improved noise immunity. A9, E7, J9 VDD Supply Power Supply: Voltage dependant on option. A1, E3, J1 VSS Supply Ground. PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8 256MSDRAM.pmd – Rev. H; Pub. 2/05 No Connect: These pins should be left unconnected. 10 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 256Mb: x4, x8, x16 SDRAM Table 6: Ball Descriptions (60-ball FBGA) 60-BALL FBGA SYMBOL TYPE K2 CLK Input Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers. L2 CKE Input Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. Deactivating the clock provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all banks idle), ACTIVE POWER-DOWN (row active in any bank) or CLOCK SUSPEND operation (burst/access in progress). CKE is synchronous except after the device enters power-down and self refresh modes, where CKE becomes asynchronous until after exiting the same mode. The input buffers, including CLK, are disabled during power-down and self refresh modes, providing low standby power. CKE may be tied HIGH. L8 CS# Input Chip Select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when CS# is registered HIGH. CS# provides for external bank selection on systems with multiple banks. CS# is considered part of the command code. J8, K7, J7 CAS#, RAS#, WE# Input Command Inputs: CAS#, RAS#, and WE# (along with CS#) define the command being entered. J2 DQM, Input Input/Output Mask: DQM is sampled HIGH and is an input mask signal for write accesses and an output enable signal for read accesses. Input data is masked during a WRITE cycle. The output buffers are placed in a High-Z state (two-clock latency) when during a READ cycle. M8, M7 BA0, BA1 Input Bank Address Input(s): BA0 and BA1 define to which bank the ACTIVE, READ, WRITE or PRECHARGE command is being applied. These pins also provide the op-code during a LOAD MODE REGISTER command A0–A12 Input Address Inputs: A0–A11 are sampled during the ACTIVE command (rowaddress A0–A11) and READ/WRITE command (column-address A0–A8; with A10 defining auto precharge) to select one location out of the memory array in the respective bank. A10 is sampled during a PRECHARGE command to determine if all banks are to be precharged (A10 HIGH) or bank selected by BA0, BA1 (LOW). The address inputs also provide the op-code during a LOAD MODE REGISTER command. N7, P8, P7, R8, R1, P2, P1, N2, N1, M2, N8, M1, L1 DESCRIPTION C7, F7, F2, C2 A8, C7, D8, F7, F2, D1, C2, A1 DQ0–DQ3 DQ0–DQ7 A1, A8, B1, B8, D1, D2, D7, D8, E1, E8, G1, G2, G7, G8, H1, H8, J1, K1, K8, L7 NC x4 No Connect: These pins should be left unconnected. G1 is a no connect for this part but may be used as A12 in future designs. B1, B8, D2, D7, E1, E8, G1, G2, G7, G8, H1, H8, J1, K1, K8, L7 NC x8 No Connect: These pins should be left unconnected. G1 is a no connect for this part but may be used as A12 in future designs. B7, C1, E7, F1 VDDQ Supply DQ Power: Isolated power to DQs for improved noise immunity. B2, C8, E2, F8 V SS Q Supply DQ Ground: Isolated ground to DQs for improved noise immunity. A7, R7 VDD Supply Power Supply: Voltage dependant on option. A2, H2, R2 VSS Supply Ground. PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8 256MSDRAM.pmd – Rev. H; Pub. 2/05 (x4) I/O Data Input/Output: Data bus (x8) I/O Data Input/Output: Data bus 11 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 256Mb: x4, x8, x16 SDRAM Functional Description Register Definition Mode Register In general, the 256Mb SDRAMs (16 Meg x 4 x 4 banks, 8 Meg x 8 x 4 banks and 4 Meg x 16 x 4 banks) are quadbank DRAMs that operate at 3.3V and include a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x4’s 67,108,864-bit banks is organized as 8,192 rows by 2,048 columns by 4 bits. Each of the x8’s 67,108,864-bit banks is organized as 8,192 rows by 1,024 columns by 8 bits. Each of the x16’s 67,108,864-bit banks is organized as 8,192 rows by 512 columns by 16 bits. Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0 and BA1 select the bank, A0–A12 select the row). The address bits (x4: A0–A9, A11; x8: A0–A9; x16: A0–A8) registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. Prior to normal operation, the SDRAM must be initialized. The following sections provide detailed information covering device initialization, register definition, command descriptions and device operation. The mode register is used to define the specific mode of operation of the SDRAM. This definition includes the selection of a burst length, a burst type, a CAS latency, an operating mode and a write burst mode, as shown in Figure 7. The mode register is programmed via the LOAD MODE REGISTER command and will retain the stored information until it is programmed again or the device loses power. Mode register bits M0–M2 specify the burst length, M3 specifies the type of burst (sequential or interleaved), M4–M6 specify the CAS latency, M7 and M8 specify the operating mode, M9 specifies the write burst mode, and M10 and M11 are reserved for future use. Address A12 (M12) is undefined but should be driven LOW during loading of the mode register. The mode register must be loaded when all banks are idle, and the controller must wait the specified time before initiating the subsequent operation. Violating either of these requirements will result in unspecified operation. Burst Length Read and write accesses to the SDRAM are burst oriented, with the burst length being programmable, as shown in Figure 1. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths of 1, 2, 4 or 8 locations are available for both the sequential and the interleaved burst types, and a fullpage burst is available for the sequential type. The full-page burst is used in conjunction with the BURST TERMINATE command to generate arbitrary burst lengths. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A1–A9, A11 (x4), A1–A9 (x8) or A1–A8 (x16) when the burst length is set to two; by A2–A9, A11 (x4), A2–A9 (x8) or A2–A8 (x16) when the burst length is set to four; and by A3–A9, A11 (x4), A3–A9 (x8) or A3–A8 (x16) when the burst length is set to eight. The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. Full-page bursts wrap within the page if the boundary is reached. Initialization SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. Once power is applied to VDD and VDDQ (simultaneously) and the clock is stable (stable clock is defined as a signal cycling within timing constraints specified for the clock pin), the SDRAM requires a 100µs delay prior to issuing any command other than a COMMAND INHIBIT or NOP. Starting at some point during this 100µs period and continuing at least through the end of this period, COMMAND INHIBIT or NOP commands should be applied. Once the 100µs delay has been satisfied with at least one COMMAND INHIBIT or NOP command having been applied, a PRECHARGE command should be applied. All banks must then be precharged, thereby placing the device in the all banks idle state. Once in the idle state, two AUTO REFRESH cycles must be performed. After the AUTO REFRESH cycles are complete, the SDRAM is ready for mode register programming. Because the mode register will power up in an unknown state, it should be loaded prior to applying any operational command. PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8 256MSDRAM.pmd – Rev. H; Pub. 2/05 12 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 256Mb: x4, x8, x16 SDRAM Burst Type Table 7: Burst Definition Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit M3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table 7. Burst Starting Column Order of Accesses Within a Burst Length Address Type = Sequential Type = Interleaved 2 Figure 7: Mode Register Definition A12 A11 A10 12 11 10 Reserved* A9 9 A8 8 A6 A7 6 7 WB Op Mode A5 5 A4 A3 4 CAS Latency 3 1 2 BT A1 A2 Address Bus A0 0 4 Mode Register (Mx) Burst Length 8 *Should program M12, M11, M10 = “0, 0, 0” to ensure compatibility with future devices. Burst Length M2 M1 M0 M3 = 0 M3 = 1 0 0 0 1 1 0 0 1 2 2 0 1 0 4 4 0 1 1 8 8 1 0 0 Reserved Reserved 1 0 1 Reserved Reserved 1 1 0 Reserved Reserved 1 1 1 Full Page Reserved 0 Sequential 1 Interleaved M6 M5 M4 CAS Latency 0 0 0 Reserved 0 0 1 Reserved 0 1 0 2 0 1 1 3 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 1 1 Reserved M8 M7 M6-M0 Operating Mode 0 0 Defined Standard Operation - - - M9 Write Burst Mode 0 Programmed Burst Length 1 Single Location Access 0-1 1-0 0-1 1-0 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 Cn, Cn + 1, Cn + 2 n = A0-A11/9/8 Cn + 3, Cn + 4... …Cn - 1, (location 0-y) Cn… 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 Not Supported NOTE: 1. For full-page accesses: y = 2,048 (x4); y = 1,024 (x8); y = 512 (x16). 2. For a burst length of two, A1-A9, A11 (x4); A1-A9 (x8); or A1-A8 (x16) select the block-of-two burst; A0 selects the starting column within the block. 3. For a burst length of four, A2-A9, A11 (x4); A2-A9 (x8); or A2-A8 (x16) select the block-of-four burst; A0-A1 select the starting column within the block. 4. For a burst length of eight, A3-A9, A11 (x4); A3-A9 (x8); or A3-A8 (x16) select the block-of-eight burst; A0-A2 select the starting column within the block. 5. For a full-page burst, the full row is selected and A0-A9, A11 (x4); A0-A9 (x8); or A0-A8 (x16) select the starting column. 6. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. 7. For a burst length of one, A0-A9, A11 (x4); A0-A9 (x8); or A0-A8 (x16) select the unique column to be accessed, and mode register bit M3 is ignored. Burst Type M3 PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8 256MSDRAM.pmd – Rev. H; Pub. 2/05 Full Page (y) A0 0 1 A1 A0 0 0 0 1 1 0 1 1 A2 A1 A0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 All other states reserved 13 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 256Mb: x4, x8, x16 SDRAM CAS Latency Operating Mode The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to two or three clocks. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge n + m. The DQs will start driving as a result of the clock edge one cycle earlier (n + m - 1), and provided that the relevant access times are met, the data will be valid by clock edge n + m. For example, assuming that the clock cycle time is such that all relevant access times are met, if a READ command is registered at T0 and the latency is programmed to two clocks, the DQs will start driving after T1 and the data will be valid by T2, as shown in Figure 8. Table 8 indicates the operating frequencies at which each CAS latency setting can be used. Reserved states should not be used as unknown operation or incompatibility with future versions may result. The normal operating mode is selected by setting M7 and M8 to zero; the other combinations of values for M7 and M8 are reserved for future use and/or test modes. The programmed burst length applies to both READ and WRITE bursts. Test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result. Write Burst Mode When M9 = 0, the burst length programmed via M0-M2 applies to both READ and WRITE bursts; when M9 = 1, the programmed burst length applies to READ bursts, but write accesses are single-location (nonburst) accesses. Table 8: CAS Latency ALLOWABLE OPERATING FREQUENCY (MHz) Figure 8: CAS Latency T0 T1 T2 T3 CLK COMMAND READ NOP NOP tLZ SPEED CAS LATENCY = 2 CAS LATENCY = 3 -7E -75 ≤ 133 ≤ 100 ≤ 143 ≤ 133 tOH DOUT DQ tAC CAS Latency = 2 T0 T1 T2 T3 T4 READ NOP NOP NOP CLK COMMAND tLZ tOH DOUT DQ tAC CAS Latency = 3 DON’T CARE UNDEFINED PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8 256MSDRAM.pmd – Rev. H; Pub. 2/05 14 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 256Mb: x4, x8, x16 SDRAM Commands Truth Tables appear following the Operation section; these tables provide current state/next state information. Truth Table 1 provides a quick reference of available commands. This is followed by a written description of each command. Three additional Table 9: Truth Table 1 – Commands and DQM Operation (Note: 1) NAME (FUNCTION) COMMAND INHIBIT (NOP) CS# RAS# CAS# WE# DQM X X X ADDR DQs X X NOTES H X NO OPERATION (NOP) L H H H X X X ACTIVE (Select bank and activate row) L L H H X Bank/Row X 3 READ (Select bank and column, and start READ burst) L H L H L/H8 Bank/Col X 4 4 WRITE (Select bank and column, and start WRITE burst) L H L L L/H8 Bank/Col Valid BURST TERMINATE L H H L X X Active PRECHARGE (Deactivate row in bank or banks) L L H L X Code X 5 AUTO REFRESH or SELF REFRESH (Enter self refresh mode) L L L H X X X 6, 7 LOAD MODE REGISTER L L L L X Op-Code X 2 Write Enable/Output Enable – – – – L – Active 8 Write Inhibit/Output High-Z – – – – H – High-Z 8 NOTE: 1. 2. 3. 4. 5. 6. 7. 8. CKE is HIGH for all commands shown except SELF REFRESH. A0-A11 define the op-code written to the mode register, and A12 should be driven LOW. A0-A12 provide row address, and BA0, BA1 determine which bank is made active. A0-A9, A11 (x4); A0-A9 (x8); or A0-A8 (x16) provide column address; A10 HIGH enables the auto precharge feature (nonpersistent), while A10 LOW disables the auto precharge feature; BA0, BA1 determine which bank is being read from or written to. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged and BA0, BA1 are “Don’t Care.” This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay). PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8 256MSDRAM.pmd – Rev. H; Pub. 2/05 15 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 256Mb: x4, x8, x16 SDRAM COMMAND INHIBIT inputs A0-A9; A11 (x4); A0-A9 (x8); or A0-A8 (x16) selects the starting column location. The value on input A10 determines whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the WRITE burst; if auto precharge is not selected, the row will remain open for subsequent accesses. Input data appearing on the DQs is written to the memory array subject to the DQM input logic level appearing coincident with the data. If a given DQM signal is registered LOW, the corresponding data will be written to memory; if the DQM signal is registered HIGH, the corresponding data inputs will be ignored, and a WRITE will not be executed to that byte/column location. The COMMAND INHIBIT function prevents new commands from being executed by the SDRAM, regardless of whether the CLK signal is enabled. The SDRAM is effectively deselected. Operations already in progress are not affected. NO OPERATION (NOP) The NO OPERATION (NOP) command is used to perform a NOP to an SDRAM which is selected (CS# is LOW). This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. LOAD MODE REGISTER PRECHARGE The mode register is loaded via inputs A0–A11 (A12 should be driven LOW.) See mode register heading in the Register Definition section. The LOAD MODE REGISTER command can only be issued when all banks are idle, and a subsequent executable command cannot be issued until tMRD is met. The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access a specified time (tRP) after the PRECHARGE command is issued. Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs BA0, BA1 select the bank. Otherwise BA0, BA1 are treated as “Don’t Care.” Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. ACTIVE The ACTIVE command is used to open (or activate) a row in a particular bank for a subsequent access. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-A12 selects the row. This row remains active (or open) for accesses until a PRECHARGE command is issued to that bank. A PRECHARGE command must be issued before opening a different row in the same bank. AUTO PRECHARGE Auto precharge is a feature which performs the same individual-bank PRECHARGE function described above, without requiring an explicit command. This is accomplished by using A10 to enable auto precharge in conjunction with a specific READ or WRITE command. A PRECHARGE of the bank/row that is addressed with the READ or WRITE command is automatically performed upon completion of the READ or WRITE burst, except in the full-page burst mode, where AUTO PRECHARGE does not apply. Auto precharge is nonpersistent in that it is either enabled or disabled for each individual READ or WRITE command. Auto precharge ensures that the precharge is initiated at the earliest valid stage within a burst. The user must not issue another command to the same bank until the precharge time (tRP) is completed. This is determined as if an explicit PRECHARGE command was issued at the earliest possible time, as described for each burst type in the Operation section of this data sheet. READ The READ command is used to initiate a burst read access to an active row. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-A9, A11 (x4), A0-A9 (x8), or A0-A8 (x16) selects the starting column location. The value on input A10 determines whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the READ burst; if auto precharge is not selected, the row will remain open for subsequent accesses. Read data appears on the DQs subject to the logic level on the DQM inputs two clocks earlier. If a given DQM signal was registered HIGH, the corresponding DQs will be High-Z two clocks later; if the DQM signal was registered LOW, the DQs will provide valid data. WRITE BURST TERMINATE The WRITE command is used to initiate a burst write access to an active row. The value on the BA0, BA1 inputs selects the bank, and the address provided on PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8 256MSDRAM.pmd – Rev. H; Pub. 2/05 The BURST TERMINATE command is used to truncate either fixed-length or full-page bursts. The most 16 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 256Mb: x4, x8, x16 SDRAM recently registered READ or WRITE command prior to the BURST TERMINATE command will be truncated, as shown in the Operation section of this data sheet. SELF REFRESH The SELF REFRESH command can be used to retain data in the SDRAM, even if the rest of the system is powered down. When in the self refresh mode, the SDRAM retains data without external clocking. The SELF REFRESH command is initiated like an AUTO REFRESH command except CKE is disabled (LOW). Once the SELF REFRESH command is registered, all the inputs to the SDRAM become “Don’t Care” with the exception of CKE, which must remain LOW. Once self refresh mode is engaged, the SDRAM provides its own internal clocking, causing it to perform its own AUTO REFRESH cycles. The SDRAM must remain in self refresh mode for a minimum period equal to tRAS and may remain in self refresh mode for an indefinite period beyond that. The procedure for exiting self refresh requires a sequence of commands. First, CLK must be stable (stable clock is defined as a signal cycling within timing constraints specified for the clock pin) prior to CKE going back HIGH. Once CKE is HIGH, the SDRAM must have NOP commands issued (a minimum of two clocks) for tXSR because time is required for the completion of any internal refresh in progress. Upon exiting the self refresh mode, AUTO REFRESH commands must be issued every 7.81µs or less as both SELF REFRESH and AUTO REFRESH utilize the row refresh counter. AUTO REFRESH AUTO REFRESH is used during normal operation of the SDRAM and is analogous to CAS#-BEFORE-RAS# (CBR) REFRESH in conventional DRAMs. This command is nonpersistent, so it must be issued each time a refresh is required. All active banks must be precharged prior to issuing an AUTO REFRESH command. The AUTO REFRESH command should not be issued until the minimum tRP has been met after the PRECHARGE command as shown in the operations section. The addressing is generated by the internal refresh controller. This makes the address bits “Don’t Care” during an AUTO REFRESH command. The 256Mb SDRAM requires 8,192 AUTO REFRESH cycles every 64ms (tREF), regardless of width option. Providing a distributed AUTO REFRESH command every 7.81µs will meet the refresh requirement and ensure that each row is refreshed. Alternatively, 8,192 AUTO REFRESH commands can be issued in a burst at the minimum cycle rate (tRFC), once every 64ms. PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8 256MSDRAM.pmd – Rev. H; Pub. 2/05 17 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 256Mb: x4, x8, x16 SDRAM Operation Bank/Row Activation Figure 9: Activating a Specific Row in a Specific Bank Before any READ or WRITE commands can be issued to a bank within the SDRAM, a row in that bank must be “opened.” This is accomplished via the ACTIVE command, which selects both the bank and the row to be activated (see Figure 9). After opening a row (issuing an ACTIVE command), a READ or WRITE command may be issued to that row, subject to the tRCD specification. tRCD (MIN) should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the ACTIVE command on which a READ or WRITE command can be entered. For example, a tRCD specification of 20ns with a 125 MHz clock (8ns period) results in 2.5 clocks, rounded to 3. This is reflected in Figure 10, which covers any case where 2 < tRCD (MIN)/tCK ≤ 3. (The same procedure is used to convert other specification limits from time units to clock cycles.) A subsequent ACTIVE command to a different row in the same bank can only be issued after the previous active row has been “closed” (precharged). The minimum time interval between successive ACTIVE commands to the same bank is defined by tRC. A subsequent ACTIVE command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access overhead. The minimum time interval between successive ACTIVE commands to different banks is defined by t RRD. CLK CKE HIGH CS# RAS# CAS# WE# ROW ADDRESS A0-A12 BANK ADDRESS BA0, BA1 Figure 10: Example: Meeting tRCD (MIN) When 2 < tRCD (MIN)/tCK < 3 T0 T1 T2 NOP NOP T3 T4 CLK COMMAND ACTIVE READ or WRITE tRCD DON’T CARE PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8 256MSDRAM.pmd – Rev. H; Pub. 2/05 18 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 256Mb: x4, x8, x16 SDRAM READs each possible CAS latency setting. Upon completion of a burst, assuming no other commands have been initiated, the DQs will go High-Z. A full-page burst will continue until terminated. (At the end of the page, it will wrap to the start address and continue.) Data from any READ burst may be truncated with a subsequent READ command, and data from a fixedlength READ burst may be immediately followed by data from a READ command. In either case, a continuous flow of data can be maintained. The first data element from the new burst follows either the last element of a completed burst or the last desired data element of a longer burst that is being truncated. The new READ command should be issued x cycles before the clock edge at which the last desired data element is READ bursts are initiated with a READ command, as shown in Figure 11. The starting column and bank addresses are provided with the READ command, and auto precharge is either enabled or disabled for that burst access. If auto precharge is enabled, the row being accessed is precharged at the completion of the burst. For the generic READ commands used in the following illustrations, auto precharge is disabled. During READ bursts, the valid data-out element from the starting column address will be available following the CAS latency after the READ command. Each subsequent data-out element will be valid by the next positive clock edge. Figure 12 shows general timing for Figure 11: READ Command Figure 12: CAS Latency CLK CKE T0 T1 T2 T3 READ NOP NOP CLK HIGH COMMAND CS# tLZ tOH DOUT DQ tAC RAS# CAS Latency = 2 CAS# A0–A9, A11: x4 A0–A9: x8 A0–A8: x16 T0 T1 T2 T3 T4 READ NOP NOP NOP CLK WE# COMMAND COLUMN ADDRESS tLZ tOH DOUT DQ tAC A12: x4 A11, A12: x8 A9, A11, A12: x16 CAS Latency = 3 DON’T CARE ENABLE AUTO PRECHARGE A10 UNDEFINED DISABLE AUTO PRECHARGE BA0,1 BANK ADDRESS DON’T CARE PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8 256MSDRAM.pmd – Rev. H; Pub. 2/05 19 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 256Mb: x4, x8, x16 SDRAM valid, where x equals the CAS latency minus one. This is shown in Figure 13 for CAS latencies of two and three; data element n + 3 is either the last of a burst of four or the last desired of a longer burst. The 256Mb SDRAM uses a pipelined architecture and therefore does not require the 2n rule associated with a prefetch architecture. A READ command can be initiated on any clock cycle following a previous READ command. Fullspeed random read accesses can be performed to the same bank, as shown in Figure 14, or each subsequent READ may be performed to a different bank. Figure 13: Consecutive READ Bursts T0 T1 T2 T3 T4 T5 T6 CLK COMMAND READ ADDRESS BANK, COL n NOP NOP NOP NOP READ NOP X = 1 cycle BANK, COL b DOUT n+2 DOUT n+1 DOUT n DQ DOUT n+3 DOUT b CAS Latency = 2 T0 T1 T2 T3 T4 T5 T6 T7 CLK COMMAND READ ADDRESS BANK, COL n NOP NOP NOP NOP READ NOP NOP X = 2 cycles BANK, COL b DOUT n DQ DOUT n+1 DOUT n+2 DOUT n+3 DOUT b CAS Latency = 3 TRANSITIONING DATA DON’T CARE NOTE: Each READ command may be to any bank. DQM is LOW. PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8 256MSDRAM.pmd – Rev. H; Pub. 2/05 20 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 256Mb: x4, x8, x16 SDRAM Figure 14: Random READ Accesses T0 T1 T2 T3 T4 T5 CLK COMMAND READ READ READ READ ADDRESS BANK, COL n BANK, COL a BANK, COL x BANK, COL m DOUT n DQ NOP NOP DOUT x DOUT a DOUT m CAS Latency = 2 T0 T1 T2 T3 T4 T5 T6 CLK COMMAND READ READ READ READ ADDRESS BANK, COL n BANK, COL a BANK, COL x BANK, COL m NOP DOUT a DOUT n DQ NOP DOUT x NOP DOUT m CAS Latency = 3 TRANSITIONING DATA DON’T CARE NOTE: Each READ command may be to any bank. DQM is LOW. PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8 256MSDRAM.pmd – Rev. H; Pub. 2/05 21 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 256Mb: x4, x8, x16 SDRAM Data from any READ burst may be truncated with a subsequent WRITE command, and data from a fixedlength READ burst may be immediately followed by data from a WRITE command (subject to bus turnaround limitations). The WRITE burst may be initiated on the clock edge immediately following the last (or last desired) data element from the READ burst, provided that I/O contention can be avoided. In a given system design, there may be a possibility that the device driving the input data will go Low-Z before the SDRAM DQs go High-Z. In this case, at least a single-cycle delay should occur between the last read data and the WRITE command. The DQM input is used to avoid I/O contention, as shown in Figures 15 and 16. The DQM signal must be asserted (HIGH) at least two clocks prior to the WRITE command (DQM latency is two clocks for output buffers) to suppress data-out from the READ. Once the WRITE command is registered, the DQs will go High-Z (or remain High-Z), regardless of the state of the DQM signal; provided the DQM was active on the clock just prior to the WRITE command that truncated the READ command. If not, the second WRITE will be an invalid WRITE. For example, if DQM was LOW during T4 in Figure 10, then the WRITEs at T5 and T7 would be valid, while the WRITE at T6 would be invalid. The DQM signal must be de-asserted prior to the WRITE command (DQM latency is zero clocks for input buffers) to ensure that the written data is not masked. Figure 9 shows the case where the clock frequency allows for bus contention to be avoided without adding a NOP cycle, and Figure 16 shows the case where the additional NOP is needed. Figure 15: READ to WRITE Figure 16: READ to WRITE with Extra Clock Cycle T0 T1 T2 T3 T0 T4 CLK CLK DQM DQM COMMAND READ ADDRESS BANK, COL n NOP NOP NOP WRITE COMMAND READ BANK, COL b ADDRESS BANK, COL n tHZ DOUT n NOP T2 NOP T3 T4 NOP NOP T5 WRITE BANK, COL b tHZ tCK DQ T1 DQ DOUT n DIN b tDS DIN b tDS TRANSITIONING DATA TRANSITIONING DATA NOTE: NOTE: A CAS latency of three is used for illustration. The READ command may be to any bank, and the WRITE command may be to any bank. If a burst of one is used, then DQM is not required. PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8 256MSDRAM.pmd – Rev. H; Pub. 2/05 DON’T CARE DON’T CARE 22 A CAS latency of three is used for illustration. The READ command may be to any bank, and the WRITE command may be to any bank. Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 256Mb: x4, x8, x16 SDRAM A fixed-length READ burst may be followed by, or truncated with, a PRECHARGE command to the same bank (provided that auto precharge was not activated), and a full-page burst may be truncated with a PRECHARGE command to the same bank. The PRECHARGE command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the CAS latency minus one. This is shown in Figure 17 for each possible CAS latency; data element n + 3 is either the last of a burst of four or the last desired of a longer burst. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until tRP is met. Note that part of the row precharge time is hidden during the access of the last data element(s). In the case of a fixed-length burst being executed to completion, a PRECHARGE command issued at the optimum time (as described above) provides the same operation that would result from the same fixed-length burst with auto precharge. The disadvantage of the Figure 17: READ to PRECHARGE T0 T1 T2 T3 T4 T5 T6 T7 CLK t RP COMMAND READ NOP NOP NOP PRECHARGE NOP NOP ACTIVE X = 1 cycle ADDRESS BANK (a or all) BANK a, COL n DOUT n DQ BANK a, ROW DOUT n+2 DOUT n+1 DOUT n+3 CAS Latency = 2 T0 T1 T2 T3 T4 T5 T6 T7 CLK t RP COMMAND READ NOP NOP NOP PRECHARGE NOP NOP ACTIVE X = 2 cycles ADDRESS BANK (a or all) BANK a, COL n DOUT n DQ BANK a, ROW DOUT n+1 DOUT n+2 DOUT n+3 CAS Latency = 3 TRANSITIONING DATA DON’T CARE NOTE: DQM is LOW. PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8 256MSDRAM.pmd – Rev. H; Pub. 2/05 23 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 256Mb: x4, x8, x16 SDRAM PRECHARGE command is that it requires that the command and address buses be available at the appropriate time to issue the command; the advantage of the PRECHARGE command is that it can be used to truncate fixed-length or full-page bursts. Full-page READ bursts can be truncated with the BURST TERMINATE command, and fixed-length READ bursts may be truncated with a BURST TERMINATE command, provided that auto precharge was not activated. The BURST TERMINATE command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the CAS latency minus one. This is shown in Figure 18 for each possible CAS latency; data element n + 3 is the last desired data element of a longer burst. Figure 18: Terminating a READ Burst T0 T1 T2 T3 T4 T5 T6 CLK COMMAND READ ADDRESS BANK, COL n NOP NOP NOP BURST TERMINATE NOP NOP X = 1 cycle DOUT n+2 DOUT n+1 DOUT n DQ DOUT n+3 CAS Latency = 2 T0 T1 T2 T3 T4 T5 T6 T7 CLK COMMAND READ ADDRESS BANK, COL n NOP NOP NOP BURST TERMINATE NOP NOP NOP X = 2 cycles DOUT n DQ DOUT n+1 DOUT n+2 DOUT n+3 CAS Latency = 3 TRANSITIONING DATA DON’T CARE NOTE: DQM is LOW. PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8 256MSDRAM.pmd – Rev. H; Pub. 2/05 24 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 256Mb: x4, x8, x16 SDRAM WRITEs new command applies to the new command. An example is shown in Figure 21. Data n + 1 is either the last of a burst of two or the last desired of a longer burst. The 256Mb SDRAM uses a pipelined architecture and therefore does not require the 2n rule associated with a prefetch architecture. A WRITE command can be initiated on any clock cycle following a previous WRITE command. Full-speed random write accesses within a page can be performed to the same bank, as shown in Figure 22, or each subsequent WRITE may be performed to a different bank. Data for any WRITE burst may be truncated with a subsequent READ command, and data for a fixedlength WRITE burst may be immediately followed by a READ command. Once the READ command is regis- WRITE bursts are initiated with a WRITE command, as shown in Figure 19. The starting column and bank addresses are provided with the WRITE command, and auto precharge is either enabled or disabled for that access. If auto precharge is enabled, the row being accessed is precharged at the completion of the burst. For the generic WRITE commands used in the following illustrations, auto precharge is disabled. During WRITE bursts, the first valid data-in element will be registered coincident with the WRITE command. Subsequent data elements will be registered on each successive positive clock edge. Upon completion of a fixed-length burst, assuming no other commands have been initiated, the DQs will remain High-Z and any additional input data will be ignored (see Figure 20). A full-page burst will continue until terminated. (At the end of the page, it will wrap to the start address and continue.) Data for any WRITE burst may be truncated with a subsequent WRITE command, and data for a fixedlength WRITE burst may be immediately followed by data for a WRITE command. The new WRITE command can be issued on any clock following the previous WRITE command, and the data provided coincident with the Figure 20: WRITE Burst T0 T1 T2 T3 COMMAND WRITE NOP NOP NOP ADDRESS BANK, COL n CLK Figure 19: WRITE Command DQ CLK CKE DIN n DIN n+1 TRANSITIONING DATA HIGH DON’T CARE NOTE: Burst length = 2. DQM is LOW. CS# RAS# Figure 21: WRITE to WRITE CAS# T1 T2 COMMAND WRITE NOP WRITE ADDRESS BANK, COL n CLK WE# A0-A9, A11: x4 A0-A9: x8 A0-A8: x16 T0 COLUMN ADDRESS A12: x4 A11, A12: x8 A9, A11, A12: x16 BANK, COL b ENABLE AUTO PRECHARGE A10 DISABLE AUTO PRECHARGE BA0,1 DQ BANK ADDRESS DIN n+1 TRANSITIONING DATA DIN b DON’T CARE NOTE: DQM is LOW. Each WRITE command may be to any bank. DON’T CARE PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8 256MSDRAM.pmd – Rev. H; Pub. 2/05 DIN n 25 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 256Mb: x4, x8, x16 SDRAM tered, the data inputs will be ignored, and WRITEs will not be executed. An example is shown in Figure 23. Data n + 1 is either the last of a burst of two or the last desired of a longer burst. Data for a fixed-length WRITE burst may be followed by, or truncated with, a PRECHARGE command to the same bank (provided that auto precharge was not activated), and a full-page WRITE burst may be truncated with a PRECHARGE command to the same bank. The PRECHARGE command should be issued tWR after the clock edge at which the last desired input data element is registered. The auto precharge mode requires a tWR of at least one clock plus time, regardless of frequency. In addition, when truncating a WRITE burst, the DQM signal must be used to mask input data for the clock edge prior to, and the clock edge coinci- dent with, the PRECHARGE command. An example is shown in Figure 24. Data n + 1 is either the last of a burst of two or the last desired of a longer burst. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until tRP is met. The precharge can be issued coincident with the first coincident clock edge (T2 in Figure 24) on an A1 Version and with the second clock on an A2 Version (Figure 24.) In the case of a fixed-length burst being executed to completion, a PRECHARGE command issued at the optimum time (as described above) provides the same operation that would result from the same fixed-length burst with auto precharge. The disadvantage of the PRECHARGE command is that it requires that the command and address buses be available at the appropriate time to issue the command; the advantage of the PRECHARGE command is that it can be used to truncate fixed-length or full-page bursts. Fixed-length or full-page WRITE bursts can be truncated with the BURST TERMINATE command. When truncating a WRITE burst, the input data applied coincident with the BURST TERMINATE command will be Figure 22: Random WRITE Cycles T0 T1 T2 T3 COMMAND WRITE WRITE WRITE WRITE ADDRESS BANK, COL n BANK, COL a BANK, COL x BANK, COL m CLK Figure 24: WRITE To PRECHARGE T0 T1 T2 T3 NOP PRECHARGE NOP T4 T5 T6 NOP ACTIVE NOP CLK DQ DIN n DIN a DIN x TRANSITIONING DATA DIN m tWR @ tCLK ≥ 15ns DQM DON’T CARE t RP COMMAND ADDRESS T1 T2 T3 T4 BANK (a or all) BANK a, COL n BANK a, ROW t WR Figure 23: WRITE To READ T0 WRITE DQ T5 DIN n DIN n+1 tWR = tCLK < 15ns CLK DQM COMMAND WRITE NOP READ NOP NOP t RP NOP COMMAND ADDRESS BANK, COL n ADDRESS BANK, COL b WRITE NOP NOP PRECHARGE NOP BANK (a or all) BANK a, COL n NOP ACTIVE BANK a, ROW t WR DQ DIN n DIN n+1 DOUT b DQ DOUT b+1 DIN n DIN n+1 TRANSITIONING DATA TRANSITIONING DATA DON’T CARE DON’T CARE NOTE: DQM could remain LOW in this example if the WRITE burst is a fixed length of two. PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8 256MSDRAM.pmd – Rev. H; Pub. 2/05 26 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 256Mb: x4, x8, x16 SDRAM ignored. The last data written (provided that DQM is LOW at that time) will be the input data applied one clock previous to the BURST TERMINATE command. This is shown in Figure 25, where data n is the last desired data element of a longer burst. open row in all banks. The bank(s) will be available for a subsequent row access some specified time (tRP) after the PRECHARGE command is issued. Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs BA0, BA1 select the bank. When all banks are to be precharged, inputs BA0, BA1 are treated as “Don’t Care.” Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. PRECHARGE The PRECHARGE command (see Figure 26) is used to deactivate the open row in a particular bank or the Figure 25: Terminating a WRITE Burst T0 T1 COMMAND WRITE BURST TERMINATE ADDRESS BANK, COL n (ADDRESS) DIN n (DATA) Power-Down Power-down occurs if CKE is registered LOW coincident with a NOP or COMMAND INHIBIT when no accesses are in progress. If power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in any bank, this mode is referred to as active power-down. Entering power-down deactivates the input and output buffers, excluding CKE, for maximum power savings while in standby. The device may not remain in the power-down state longer than the refresh period (64ms) since no refresh operations are performed in this mode. The power-down state is exited by registering a NOP or COMMAND INHIBIT and CKE HIGH at the desired clock edge (meeting tCKS). See Figure 27. T2 CLK DQ NEXT COMMAND TRANSITIONING DATA DON’T CARE NOTE: DQMs are LOW. Figure 26: PRECHARGE Command Figure 27: Power-Down CLK CKE HIGH (( )) (( )) CLK tCKS CS# CKE (( )) COMMAND RAS# > tCKS (( )) (( )) NOP NOP All banks idle Input buffers gated off CAS# Enter power-down mode. WE# Exit power-down mode. ACTIVE tRCD tRAS tRC DON’T CARE A0-A9, A11, A12 All Banks A10 Bank Selected BA0, BA1 PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8 256MSDRAM.pmd – Rev. H; Pub. 2/05 BANK ADDRESS 27 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 256Mb: x4, x8, x16 SDRAM CLOCK SUSPEND The clock suspend mode occurs when a column access/burst is in progress and CKE is registered LOW. In the clock suspend mode, the internal clock is deactivated, “freezing” the synchronous logic. For each positive clock edge on which CKE is sampled LOW, the next internal positive clock edge is suspended. Any command or data present on the input pins at the time of a suspended internal clock edge is ignored; any data present on the DQ pins remains driven; and burst counters are not incremented, as long as the clock is suspended. (See examples in Figures 28and 29.) Clock suspend mode is exited by registering CKE HIGH; the internal clock and related operation will resume on the subsequent positive clock edge. Figure 28: Clock Suspend During WRITE Burst Figure 29: Clock Suspend During READ Burst T0 T1 T2 T3 T4 BURST READ/SINGLE WRITE The burst read/single write mode is entered by programming the write burst mode bit (M9) in the mode register to a logic 1. In this mode, all WRITE commands result in the access of a single column location (burst of one), regardless of the programmed burst length. READ commands access columns according to the programmed burst length and sequence, just as in the normal mode of operation (M9 = 0). T0 T5 CLK CLK CKE CKE INTERNAL CLOCK INTERNAL CLOCK COMMAND ADDRESS DIN NOP WRITE NOP NOP BANK, COL n DIN n TRANSITIONING DATA DIN n+1 DIN n+2 COMMAND READ ADDRESS BANK, COL n DQ T1 NOP T2 T3 NOP DOUT n T4 NOP DOUT n+1 T5 T6 NOP DOUT n+2 NOP DOUT n+3 DON’T CARE TRANSITIONING DATA DON’T CARE NOTE: For this example, CAS latency = 2, burst length = 4 or greater, and DQM is LOW. PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8 256MSDRAM.pmd – Rev. H; Pub. 2/05 28 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 256Mb: x4, x8, x16 SDRAM CONCURRENT AUTO PRECHARGE on bank n, CAS latency later. The PRECHARGE to bank n will begin when the READ to bank m is registered (Figure 30). 2. Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will interrupt a READ on bank n when registered. DQM should be used two clocks prior to the WRITE command to prevent bus contention. The PRECHARGE to bank n will begin when the WRITE to bank m is registered (Figure 31). An access command (READ or WRITE) to another bank while an access command with auto precharge enabled is executing is not allowed by SDRAMs, unless the SDRAM supports CONCURRENT AUTO PRECHARGE. Micron SDRAMs support CONCURRENT AUTO PRECHARGE. Four cases where CONCURRENT AUTO PRECHARGE occurs are defined below. READ with Auto Precharge 1. Interrupted by a READ (with or without auto precharge): A READ to bank m will interrupt a READ Figure 30: READ With Auto Precharge Interrupted by a READ T0 T1 T2 T3 T4 T5 T6 T7 CLK COMMAND BANK n Internal States READ - AP BANK n NOP Page Active READ - AP BANK m NOP READ with Burst of 4 NOP NOP NOP NOP Idle Interrupt Burst, Precharge tRP - BANK m t RP - BANK n Page Active BANK m BANK n, COL a ADDRESS Precharge READ with Burst of 4 BANK m, COL d DOUT a+1 DOUT a DQ DOUT d DOUT d+1 CAS Latency = 3 (BANK n) CAS Latency = 3 (BANK m) NOTE: DQM is LOW. TRANSITIONING DATA DON’T CARE Figure 31: READ With Auto Precharge Interrupted by a WRITE T0 T1 T2 T3 T4 T5 T6 T7 CLK COMMAND BANK n Internal States READ - AP BANK n Page Active NOP NOP NOP READ with Burst of 4 WRITE - AP BANK m NOP NOP Interrupt Burst, Precharge Idle tRP - BANK n Page Active BANK m ADDRESS NOP Write-Back WRITE with Burst of 4 BANK n, COL a t WR - BANK m BANK m, COL d 1 DQM DOUT a DQ CAS Latency = 3 (BANK n) DIN d DIN d+1 DIN d+2 TRANSITIONING DATA DIN d+3 DON’T CARE NOTE: 1. DQM is HIGH at T2 to prevent DOUT-a+1 from contending with DIN-d at T4. PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8 256MSDRAM.pmd – Rev. H; Pub. 2/05 29 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 256Mb: x4, x8, x16 SDRAM WRITE with Auto Precharge 3. Interrupted by a READ (with or without auto precharge): A READ to bank m will interrupt a WRITE on bank n when registered, with the data-out appearing CAS latency later. The PRECHARGE to bank n will begin after tWR is met, where tWR begins when the READ to bank m is registered. The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m (Figure 32). 4. Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will interrupt a WRITE on bank n when registered. The PRECHARGE to bank n will begin after tWR is met, where tWR begins when the WRITE to bank m is registered. The last valid data WRITE to bank n will be data registered one clock prior to a WRITE to bank m (Figure 33). Figure 32: WRITE With Auto Precharge Interrupted by a READ T0 T1 T2 T3 T4 T5 T6 T7 CLK COMMAND BANK n Internal States NOP WRITE - AP BANK n Page Active READ - AP BANK m NOP WRITE with Burst of 4 DIN a DQ NOP Precharge tWR - BANK n tRP - BANK n NOP tRP - BANK m READ with Burst of 4 BANK n, COL a ADDRESS NOP Interrupt Burst, Write-Back Page Active BANK m NOP BANK m, COL d DOUT d+1 DOUT d DIN a+1 CAS Latency = 3 (BANK m) TRANSITIONING DATA NOTE: 1. DQM is LOW. DON’T CARE Figure 33: WRITE With Auto Precharge Interrupted by a WRITE T0 T1 T2 T3 T4 T5 T6 T7 CLK COMMAND BANK n Internal States NOP WRITE - AP BANK n Page Active NOP NOP WRITE with Burst of 4 WRITE - AP BANK m NOP NOP Interrupt Burst, Write-Back Precharge tRP - BANK n tWR - BANK n BANK m ADDRESS DQ Page Active DIN a t WR - BANK m Write-Back WRITE with Burst of 4 BANK n, COL a NOP BANK m, COL d DIN a+1 DIN a+2 DIN d DIN d+1 DIN d+2 TRANSITIONING DATA DIN d+3 DON’T CARE NOTE: 1. DQM is LOW. PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8 256MSDRAM.pmd – Rev. H; Pub. 2/05 30 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 256Mb: x4, x8, x16 SDRAM Table 10: Truth Table 2 – CKE (Notes: 1-4) CKEn-1 CKEn L L L H H L CURRENT STATE COMMANDn Power-Down X Self Refresh X Maintain Self Refresh Clock Suspend X Maintain Clock Suspend Power-Down COMMAND INHIBIT or NOP Exit Power-Down Self Refresh COMMAND INHIBIT or NOP Exit Self Refresh 6 Clock Suspend X Exit Clock Suspend 7 All Banks Idle COMMAND INHIBIT or NOP Power-Down Entry All Banks Idle AUTO REFRESH Self Refresh Entry Reading or Writing H H VALID ACTIONn NOTES Maintain Power-Down 5 Clock Suspend Entry See Truth Table 3 NOTE: 1. 2. 3. 4. 5. CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous clock edge. Current state is the state of the SDRAM immediately prior to clock edge n. COMMANDn is the command registered at clock edge n, and ACTIONn is a result of COMMANDn. All states and sequences not shown are illegal or reserved. Exiting power-down at clock edge n will put the device in the all banks idle state in time for clock edge n + 1 (provided that tCKS is met). 6. Exiting self refresh at clock edge n will put the device in the all banks idle state once tXSR is met. COMMAND INHIBIT or NOP commands should be issued on any clock edges occurring during the tXSR period. A minimum of two NOP commands must be provided during tXSR period. 7. After exiting clock suspend at clock edge n, the device will resume operation and recognize the next command at clock edge n + 1. PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8 256MSDRAM.pmd – Rev. H; Pub. 2/05 31 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 256Mb: x4, x8, x16 SDRAM Table 11: Truth Table 3 – Current State Bank n, Command to Bank n (Notes: 1-6; notes appear below and on next page) CURRENT STATE Any Idle Row Active CS# RAS# CAS# WE# COMMAND (ACTION) NOTES H X X X COMMAND INHIBIT (NOP/Continue previous operation) L H H H NO OPERATION (NOP/Continue previous operation) L L H H ACTIVE (Select and activate row) L L L H AUTO REFRESH 7 L L L L LOAD MODE REGISTER 7 L L H L PRECHARGE 11 L H L H READ (Select column and start READ burst) 10 L H L L WRITE (Select column and start WRITE burst) 10 L L H L PRECHARGE (Deactivate row in bank or banks) 8 Read L H L H READ (Select column and start new READ burst) 10 (Auto L H L L WRITE (Select column and start WRITE burst) 10 Precharge L L H L PRECHARGE (Truncate READ burst, start PRECHARGE) 8 Disabled) L H H L BURST TERMINATE 9 Write L H L H READ (Select column and start READ burst) 10 (Auto L H L L WRITE (Select column and start new WRITE burst) 10 Precharge L L H L PRECHARGE (Truncate WRITE burst, start PRECHARGE) 8 Disabled) L H H L BURST TERMINATE 9 NOTE: 1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Truth Table 2) and after tXSR has been met (if the previous state was self refresh). 2. This table is bank-specific, except where noted, i.e., the current state is for a specific bank and the commands shown are those allowed to be issued to that bank when in that state. Exceptions are covered in the notes below. 3. Current state definitions: Idle: The bank has been precharged, and tRP has been met. Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in progress. Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. 4. The following states must not be interrupted by a command issued to the same bank. COMMAND INHIBIT or NOP commands, or allowable commands to the other bank should be issued on any clock edge occurring during these states. Allowable commands to the other bank are determined by its current state and Truth Table 3, and according to Truth Table 4. Precharging: Starts with registration of a PRECHARGE command and ends when tRP is met. Once tRP is met, the bank will be in the idle state. Row Activating: Starts with registration of an ACTIVE command and ends when tRCD is met. Once tRCD is met, the bank will be in the row active state. Read w/Auto Precharge Enabled: Starts with registration of a READ command with auto precharge enabled and ends when tRP has been met. Once tRP is met, the bank will be in the idle state. Write w/Auto Precharge Enabled: Starts with registration of a WRITE command with auto precharge enabled and ends when tRP has been met. Once tRP is met, the bank will be in the idle state. PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8 256MSDRAM.pmd – Rev. H; Pub. 2/05 32 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 256Mb: x4, x8, x16 SDRAM NOTE (continued): 5. The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP commands must be applied on each positive clock edge during these states. Refreshing: Starts with registration of an AUTO REFRESH command and ends when tRC is met. Once tRC is met, the SDRAM will be in the all banks idle state. Accessing Mode Register: Starts with registration of a LOAD MODE REGISTER command and ends when tMRD has been met. Once tMRD is met, the SDRAM will be in the all banks idle state. Precharging All: Starts with registration of a PRECHARGE ALL command and ends when tRP is met. Once tRP is met, all banks will be in the idle state. 6. All states and sequences not shown are illegal or reserved. 7. Not bank-specific; requires that all banks are idle. 8. May or may not be bank-specific; if all banks are to be precharged, all must be in a valid state for precharging. 9. Not bank-specific; BURST TERMINATE affects the most recent READ or WRITE burst, regardless of bank. 10. READs or WRITEs listed in the Command (Action) column include READs or WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled. 11. Does not affect the state of the bank and acts as a NOP to that bank. PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8 256MSDRAM.pmd – Rev. H; Pub. 2/05 33 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 256Mb: x4, x8, x16 SDRAM Table 12: Truth Table 4 – Current State Bank n, Command to Bank m (Notes: 1-6; notes appear below and on next page) CURRENT STATE CS# RAS# CAS# WE# COMMAND (ACTION) NOTES Any H X X X COMMAND INHIBIT (NOP/Continue previous operation) L H H H NO OPERATION (NOP/Continue previous operation) Idle X X X X Any Command Otherwise Allowed to Bank m Row L L H H ACTIVE (Select and activate row) Activating, L H L H READ (Select column and start READ burst) 7 Active, or L H L L WRITE (Select column and start WRITE burst) 7 Precharging L L H L PRECHARGE Read L L H H ACTIVE (Select and activate row) (Auto L H L H READ (Select column and start new READ burst) 7, 10 Precharge L H L L WRITE (Select column and start WRITE burst) 7, 11 Disabled) L L H L PRECHARGE Write L L H H ACTIVE (Select and activate row) 9 (Auto L H L H READ (Select column and start READ burst) 7, 12 Precharge L H L L WRITE (Select column and start new WRITE burst) 7, 13 Disabled) L L H L PRECHARGE Read L L H H ACTIVE (Select and activate row) 9 (With Auto L H L H READ (Select column and start new READ burst) 7, 8, 14 Precharge) L H L L WRITE (Select column and start WRITE burst) 7, 8, 15 L L H L PRECHARGE L L H H ACTIVE (Select and activate row) Write 9 (With Auto L H L H READ (Select column and start READ burst) 7, 8, 16 Precharge) L H L L WRITE (Select column and start new WRITE burst) 7, 8, 17 L L H L PRECHARGE 9 NOTE: 1. This table applies when CKE n-1 was HIGH and CKEn is HIGH (see Truth Table 2) and after tXSR has been met (if the previous state was self refresh). 2. This table describes alternate bank operation, except where noted; i.e., the current state is for bank n and the commands shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). Exceptions are covered in the notes below. 3. Current state definitions: Idle: The bank has been precharged, and tRP has been met. Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in progress. Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. Read w/Auto Precharge Enabled: Starts with registration of a READ command with auto precharge enabled, and ends when tRP has been met. Once tRP is met, the bank will be in the idle state. Write w/Auto Precharge Enabled: Starts with registration of a WRITE command with auto precharge enabled, and ends when tRP has been met. Once tRP is met, the bank will be in the idle state. PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8 256MSDRAM.pmd – Rev. H; Pub. 2/05 34 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 256Mb: x4, x8, x16 SDRAM NOTE (continued): 4. AUTO REFRESH, SELF REFRESH and LOAD MODE REGISTER commands may only be issued when all banks are idle. 5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state only. 6. All states and sequences not shown are illegal or reserved. 7. READs or WRITEs to bank m listed in the Command (Action) column include READs or WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled. 8. CONCURRENT AUTO PRECHARGE: Bank n will initiate the auto precharge command when its burst has been interrupted by bank m’s burst. 9. Burst in bank n continues as initiated. 10. For a READ without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the READ on bank n, CAS latency later (Figure 7). 11. For a READ without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the READ on bank n when registered (Figures 9 and 10). DQM should be used one clock prior to the WRITE command to prevent bus contention. 12. For a WRITE without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the WRITE on bank n when registered (Figure 17), with the data-out appearing CAS latency later. The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m. 13. For a WRITE without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the WRITE on bank n when registered (Figure 15). The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m. 14. For a READ with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the READ on bank n, CAS latency later. The PRECHARGE to bank n will begin when the READ to bank m is registered (Figure 24). 15. For a READ with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the READ on bank n when registered. DQM should be used two clocks prior to the WRITE command to prevent bus contention. The PRECHARGE to bank n will begin when the WRITE to bank m is registered (Figure 25). 16. For a WRITE with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the WRITE on bank n when registered, with the data-out appearing CAS latency later. The PRECHARGE to bank n will begin after tWR is met, where tWR begins when the READ to bank m is registered. The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m (Figure 26). 17. For a WRITE with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the WRITE on bank n when registered. The PRECHARGE to bank n will begin after tWR is met, where tWR begins when the WRITE to bank m is registered. The last valid WRITE to bank n will be data registered one clock prior to the WRITE to bank m (Figure 27). PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8 256MSDRAM.pmd – Rev. H; Pub. 2/05 35 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 256Mb: x4, x8, x16 SDRAM Absolute Maximum Ratings Voltage on VDD, VDDQ Supply Relative to VSS ....................................... -1V to +4.6V Voltage on Inputs, NC or I/O Pins Relative to VSS ....................................... -1V to +4.6V Operating Temperature, TA (commercial) ....................................... 0°C to +70°C Operating Temperature, TA (industrial “IT”) ............................. -40°C to +85°C Storage Temperature (plastic) ............ -55°C to +150°C Power Dissipation ........................................................ 1W Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Table 13: DC Electrical Characteristics and Operating Conditions (Notes: 1, 5, 6; notes appear on page 39); (VDD, VDDQ = +3.3V ±0.3V) PARAMETER/CONDITION SYMBOL MIN MAX Supply Voltage VDD, VDDQ 3 3.6 V Input High Voltage: Logic 1; All inputs VIH 2 VDD + 0.3 V 22 Input Low Voltage: Logic 0; All inputs VIL -0.3 0.8 V 22 II -5 5 µA IOZ -5 5 µA VOH VOL 2.4 – – 0.4 V V Input Leakage Current: Any input 0V ≤ VIN ≤ VDD (All other pins not under test = 0V) Output Leakage Current: DQs are disabled; 0V ≤ VOUT ≤ VDDQ Output Levels: Output High Voltage (IOUT = -4mA) Output Low Voltage (IOUT = 4mA) UNITS NOTES Table 14: IDD Specifications and Conditions (Notes: 1, 5, 6, 11, 13; notes appear on page 39); (VDD, VDDQ = +3.3V ±0.3V) MAX PARAMETER/CONDITION SYMBOL -7E -75 UNITS NOTES Operating Current: Active Mode; Burst = 2; READ or WRITE; tRC = tRC (MIN) IDD1 135 125 mA 3, 18, 19, 32 Standby Current: Power-Down Mode; All banks idle; CKE = LOW IDD2 2 2 mA 32 Standby Current: Active Mode; CKE = HIGH; CS# = HIGH; All banks active after tRCD met; No accesses in progress IDD3 40 40 mA 3, 12, 19, 32 Operating Current: Burst Mode; Page burst; READ or WRITE; All banks active IDD4 135 135 mA 3, 18, 19, 32 3, 12, 18, 19, 32, 33 Auto Refresh Current tRFC = tRFC (MIN) IDD5 285 270 mA CS# = HIGH; CKE = HIGH tRFC = 7.81 µs IDD6 3.5 3.5 mA SELF REFRESH CURRENT: CKE ≤ 0.2V Standard Low power (L) IDD7 IDD7 2.5 1.5 2.5 1.5 mA mA PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8 256MSDRAM.pmd – Rev. H; Pub. 2/05 36 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 256Mb: x4, x8, x16 SDRAM Table 15: Capacitance (Note: 2; notes appear on page 39) PARAMETER - TSOP “TG” Package SYMBOL MIN MAX Input Capacitance: CLK CI1 2.5 3.5 pF 29 Input Capacitance: All other input-only pins CI2 2.5 3.8 pF 30 Input/Output Capacitance: DQs CIO 4.0 6.0 pF 31 PARAMETER - FBGA “FB” and “FG” Package UNITS NOTES SYMBOL MIN MAX Input Capacitance: CLK CI1 1.5 3.5 UNITS NOTES pF 34 Input Capacitance: All other input-only pins CI2 1.5 3.8 pF 35 Input/Output Capacitance: DQs CIO 3.0 6.0 pF 36 Table 16: Electrical Characteristics and Recommended AC Operating Conditions (Notes: 5, 6, 8, 9, 11; notes appear on page 39) AC CHARACTERISTICS PARAMETER Access time from CLK (pos. edge) Address hold time Address setup time CLK high-level width CLK low-level width Clock cycle time CKE hold time CKE setup time CS#, RAS#, CAS#, WE#, DQM hold time CS#, RAS#, CAS#, WE#, DQM setup time Data-in hold time Data-in setup time Data-out high-impedance time Data-out low-impedance time Data-out hold time (load) Data-out hold time (no load) ACTIVE to PRECHARGE command ACTIVE to ACTIVE command period ACTIVE to READ or WRITE delay Refresh period (8,192 rows) AUTO REFRESH period PRECHARGE command period ACTIVE bank a to ACTIVE bank b command Transition time WRITE recovery time CL = 3 CL = 2 CL = 3 CL = 2 CL = 3 CL = 2 tXSR Exit SELF REFRESH to ACTIVE command PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8 256MSDRAM.pmd – Rev. H; Pub. 2/05 -7E -75 SYMBOL MIN MAX MIN MAX tAC(3) 5.4 5.4 tAC(2) 5.4 6 tAH 0.8 0.8 tAS 1.5 1.5 tCH 2.5 2.5 tCL 2.5 2.5 tCK(3) 7 7.5 tCK(2) 7.5 10 tCKH 0.8 0.8 tCKS 1.5 1.5 tCMH 0.8 0.8 tCMS 1.5 1.5 tDH 0.8 0.8 tDS 1.5 1.5 tHZ(3) 5.4 5.4 tHZ(2) 5.4 6 t LZ 1 1 tOH 3 3 tOH 1.8 1.8 N tRAS 37 120,000 44 120,000 tRC 60 66 tRCD 15 20 tREF 64 64 tRFC 66 66 tRP 15 20 tRRD 14 15 tT 0.3 1.2 0.3 1.2 tWR 1 CLK+ 1 CLK+ 7ns 7.5ns 37 14 67 15 75 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns ns ns ns NOTES 27 ns ns 25 20 23 23 37 10 10 28 7 24 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 256Mb: x4, x8, x16 SDRAM Table 17: AC Functional Characteristics (Notes: 5, 6, 7, 8, 9, 11; notes appear on page 39) PARAMETER READ/WRITE command to READ/WRITE command CKE to clock disable or power-down entry mode CKE to clock enable or power-down exit setup mode DQM to input data delay DQM to data mask during WRITEs DQM to data high-impedance during READs WRITE command to input data delay Data-in to ACTIVE command Data-in to PRECHARGE command Last data-in to burst STOP command Last data-in to new READ/WRITE command Last data-in to PRECHARGE command LOAD MODE REGISTER command to ACTIVE or REFRESH command Data-out to high-impedance from PRECHARGE command PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8 256MSDRAM.pmd – Rev. H; Pub. 2/05 38 CL = 3 CL = 2 SYMBOL tCCD tCKED tPED tDQD tDQM tDQZ tDWD tDAL tDPL tBDL tCDL tRDL tMRD tROH(3) tROH(2) -7E 1 1 1 0 0 2 0 4 2 1 1 2 2 3 2 -75 1 1 1 0 0 2 0 5 2 1 1 2 2 3 2 UNITS tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK NOTES 17 14 14 17 17 17 17 15, 21 16, 21 17 17 16, 21 26 17 17 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 256Mb: x4, x8, x16 SDRAM Notes 1. 2. 3. 4. 5. 6. 7. 8. 9. 14. Timing actually specified by tCKS; clock(s) specified as a reference only at minimum cycle rate. 15. Timing actually specified by tWR plus tRP; clock(s) specified as a reference only at minimum cycle rate. 16. Timing actually specified by tWR. 17. Required clocks are specified by JEDEC functionality and are not dependent on any timing parameter. 18. The IDD current will increase or decrease proportionally according to the amount of frequency alteration for the test condition. 19. Address transitions average one transition every two clocks. 20. CLK must be toggled a minimum of two times during this period. 21.Based on tCK = 7.5ns for -75 and -7E. 22. VIH overshoot: VIH (MAX) = VDDQ + 2V for a pulse width ≤ 3ns, and the pulse width cannot be greater than one third of the cycle rate. VIL undershoot: VIL (MIN) = -2V for a pulse width ≤ 3ns. 23. The clock frequency must remain constant (stable clock is defined as a signal cycling within timing constraints specified for the clock pin) during access or precharge states (READ, WRITE, including tWR, and PRECHARGE commands). CKE may be used to reduce the data rate. 24. Auto precharge mode only. The precharge timing budget (tRP) begins 7ns for -7E and 7.5ns for -75 after the first clock delay, after the last WRITE is executed. 25. Precharge mode only. 26. JEDEC and PC100 specify three clocks. 27. tAC for -75/-7E at CL = 3 with no load is 4.6ns and is guaranteed by design. 28. Parameter guaranteed by design. 29. PC100 specifies a maximum of 4pF. 30. PC100 specifies a maximum of 5pF. 31. PC100 specifies a maximum of 6.5pF. 32. For -75, CL = 3 and tCK = 7.5ns; for -7E, CL = 2 and tCK = 7.5ns. 33. CKE is HIGH during refresh command period tRFC (MIN) else CKE is LOW. The IDD6 limit is actually a nominal value and does not result in a fail value. 34. PC133 specifies a minimum of 2.5pF. 35. PC133 specifies a minimum of 2.5pF. 36. PC133 specifies a minimum of 3.0pF. 37. For operating frequencies ≤ 45 MHz tCKS = 3.0ns. All voltages referenced to VSS. This parameter is sampled. VDD , V DDQ = +3.3V; f = 1 MHz, TA = 25°C; pin under test biased at 1.4V. IDD is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and the outputs open. Enables on-chip refresh and address counters. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range is ensured; (0°C ≤ TA ≤ +70°C for commercial) and (-40°C ≤ TA ≤ +85°C for IT). An initial pause of 100µs is required after powerup, followed by two AUTO REFRESH commands, before proper device operation is ensured. (VDD and VDDQ must be powered up simultaneously. VSS and VSSQ must be at same potential.) The two AUTO REFRESH command wake-ups should be repeated any time the tREF refresh requirement is exceeded. AC characteristics assume tT = 1ns. In addition to meeting the transition rate specification, the clock and CKE must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner. Outputs measured at 1.5V with equivalent load: Q 50pF 10. tHZ defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL. The last valid data element will meet tOH before going High-Z. 11. AC operating and IDD test conditions have VIL = 0V and VIH = 3.0V using a measurement reference level of 1.5V. If the input transition time is longer than 1ns, then the timing is measured from VIL (MAX) and VIH (MIN) and no longer from the 1.5V midpoint. CLK should always be 1.5V referenced to crossover. Refer to Micron Technical Note TN-4809. 12. Other input signals are allowed to transition no more than once every two clocks and are otherwise at valid VIH or VIL levels. 13. IDD specifications are tested after the device is properly initialized. PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8 256MSDRAM.pmd – Rev. H; Pub. 2/05 39 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 256Mb: x4, x8, x16 SDRAM Figure 34: Initialize and Load Mode Register 2 T0 CK (( )) CKE (( )) (( )) COMMAND (( )) (( )) tCK T1 (( )) (( )) tCKH tCKS Tn + 1 To + 1 tCL (( )) (( )) tCH (( )) (( )) (( )) Tp + 1 (( )) (( )) Tp + 2 Tp + 3 (( )) tCMS tCMH NOP PRECHARGE (( )) (( )) (( )) NOP NOP (( )) AUTO REFRESH (( )) NOP NOP (( )) AUTO REFRESH (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) A0-A9, A11, A12 (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) A10 (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) DQM/ DQML, DQMU BA0, BA1 DQ ALL BANKS SINGLE BANK (( )) (( )) ALL BANKS (( )) T = 100µs MIN High-Z tAS NOP ACTIVE tAH 5 ROW CODE tAS tAH ROW CODE BANK (( )) tRP Power-up: VDD and CLK stable LOAD MODE REGISTER tRFC tRFC Program Mode Register 1, 3, 4 AUTO REFRESH AUTO REFRESH Precharge all banks tMRD DON’T CARE UNDEFINED TIMING PARAMETERS -7E SYMBOL* tAH tAS tCH tCL tCK (3) tCK (2) tCKH MIN 0.8 1.5 2.5 2.5 7 7.5 0.8 -75 MAX MIN 0.8 1.5 2.5 2.5 7.5 10 0.8 -7E MAX UNITS ns ns ns ns ns ns ns SYMBOL* tCKS tCMH tCMS tMRD3 tRFC tRP MIN 1.5 0.8 1.5 2 66 15 -75 MAX MIN 1.5 0.8 1.5 2 66 20 MAX UNITS ns ns ns tCK ns ns *CAS latency indicated in parentheses. NOTE: 1. 2. 3. 4. 5. The mode register may be loaded prior to the AUTO REFRESH cycles if desired. If CS is HIGH at clock HIGH time, all commands applied are NOP. JEDEC and PC100 specify three clocks. Outputs are guaranteed High-Z after command is issued. A12 should be a LOW at tP + 1. PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8 256MSDRAM.pmd – Rev. H; Pub. 2/05 40 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 256Mb: x4, x8, x16 SDRAM Figure35: Power-Down Mode 1 T0 T1 T2 Tn + 1 Tn + 2 (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) DQM/ DQML, DQMU (( )) (( )) (( )) (( )) A0-A9, A11, A12 (( )) (( )) (( )) (( )) ROW (( )) (( )) (( )) (( )) ROW (( )) (( )) (( )) (( )) BANK (( )) (( )) tCK CLK tCL tCKS tCH CKE tCKS tCKH tCMS tCMH COMMAND PRECHARGE NOP NOP ALL BANKS A10 SINGLE BANK tAS BA0, BA1 tCKS NOP ACTIVE tAH BANK(S) High-Z DQ Two clock cycles Input buffers gated off while in power-down mode Precharge all active banks All banks idle All banks idle, enter power-down mode Exit power-down mode DON’T CARE TIMING PARAMETERS -7E SYMBOL* tAH tAS tCH tCL tCK (3) MIN 0.8 1.5 2.5 2.5 7 -75 MAX MIN 0.8 1.5 2.5 2.5 7.5 -7E MAX UNITS ns ns ns ns ns SYMBOL* tCK (2) tCKH tCKS tCMH tCMS MIN 7.5 0.8 1.5 0.8 1.5 -75 MAX MIN 10 0.8 1.5 0.8 1.5 MAX UNITS ns ns ns ns ns *CAS latency indicated in parentheses. NOTE: 1. Violating refresh requirements during power-down may result in a loss of data. PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8 256MSDRAM.pmd – Rev. H; Pub. 2/05 41 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 256Mb: x4, x8, x16 SDRAM Figure 36: Clock Suspend Mode1 T0 T1 tCK CLK T2 T3 T4 T5 T6 T7 T8 NOP WRITE T9 tCL tCH tCKS tCKH CKE tCKS tCKH tCMS tCMH COMMAND READ NOP NOP NOP NOP NOP tCMS tCMH DQM/ DQML, DQMU A0-A9, A11, A12 tAS tAH COLUMN m tAS 2 COLUMN e 2 tAH A10 tAS BA0, BA1 tAH BANK BANK tAC tOH tAC DQ DOUT m tLZ tHZ tDS DOUT m + 1 tDH DIN e DIN + 1 DON’T CARE UNDEFINED TIMING PARAMETERS -7E SYMBOL* tAC (3) tAC (2) tAH tAS tCH tCL tCK (3) tCK (2) tCKH MIN -75 MAX 5.4 5.4 0.8 1.5 2.5 2.5 7 7.5 0.8 MIN 0.8 1.5 2.5 2.5 7.5 10 0.8 -7E MAX 5.4 6 UNITS ns ns ns ns ns ns ns ns ns SYMBOL* tCKS tCMH tCMS tDH tDS tHZ (3) tHZ (2) tLZ tOH MIN 1.5 0.8 1.5 0.8 1.5 -75 MAX MIN 1.5 0.8 1.5 0.8 1.5 5.4 5.4 1 3 MAX 5.4 6 1 3 UNITS ns ns ns ns ns ns ns ns ns *CAS latency indicated in parentheses. NOTE: 1. For this example, the burst length = 2, the CAS latency = 3, and auto precharge is disabled. 2. x16: A9, A11 and A12 = “Don’t Care” x8: A11 and A12 = “Don’t Care” x4: A12 = “Don’t Care” PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8 256MSDRAM.pmd – Rev. H; Pub. 2/05 42 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 256Mb: x4, x8, x16 SDRAM Figure 37: Auto Refresh Mode T0 CLK T1 T2 tCK (( )) (( )) tCH tCKS tCKH tCMS tCMH COMMAND PRECHARGE AUTO REFRESH NOP NOP (( )) ( ( NOP )) (( )) AUTO REFRESH NOP (( )) (( )) DQM / DQML, DQMU A0-A9, A11, A12 ALL BANKS A10 SINGLE BANK tAS BA0, BA1 To + 1 (( )) (( )) (( )) CKE DQ Tn + 1 tCL (( )) ( ( NOP )) ACTIVE (( )) (( )) (( )) (( )) (( )) (( )) ROW (( )) (( )) (( )) (( )) ROW tAH BANK(S) High-Z tRP (( )) (( )) (( )) (( )) (( )) (( )) tRFC BANK tRFC Precharge all active banks DON’T CARE TIMING PARAMETERS -7E SYMBOL* tAH tAS tCH tCL tCK (3) tCK (2) MIN 0.8 1.5 2.5 2.5 7 7.5 -75 MAX MIN 0.8 1.5 2.5 2.5 7.5 10 -7E MAX UNITS ns ns ns ns ns ns SYMBOL* tCKH tCKS tCMH tCMS tRFC tRP MIN 0.8 1.5 0.8 1.5 66 15 -75 MAX MIN 0.8 1.5 0.8 1.5 66 20 MAX UNITS ns ns ns ns ns ns *CAS latency indicated in parentheses. PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8 256MSDRAM.pmd – Rev. H; Pub. 2/05 43 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 256Mb: x4, x8, x16 SDRAM Figure 38: Self Refresh Mode T0 CLK T1 tCK tCL tCH T2 tCKS ≥ tRAS(MIN)1 CKE tCKS tCKH tCMS tCMH COMMAND PRECHARGE Tn + 1 (( )) (( )) AUTO REFRESH (( )) (( )) (( )) (( )) A0-A9, A11,A12 (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) SINGLE BANK tAS BA0, BA1 DQ AUTO REFRESH INHIBIT )) (( )) (( )) ALL BANKS To + 2 (( ) ) or COMMAND NOP ( ( DQM/ DQML, DQMU A10 To + 1 (( )) (( )) (( )) NOP (( )) (( )) tAH BANK(S) High-Z (( )) (( )) tRP Precharge all active banks tXSR2 Enter self refresh mode Exit self refresh mode (Restart refresh time base) DON’T CARE CLK stable prior to exiting self refresh mode TIMING PARAMETERS -7E SYMBOL* tAH tAS tCH tCL tCK (3) tCK (2) tCKH MIN 0.8 1.5 2.5 2.5 7 7.5 0.8 -75 MAX MIN 0.8 1.5 2.5 2.5 7.5 10 0.8 -7E MAX UNITS ns ns ns ns ns ns ns SYMBOL* tCKS tCMH tCMS tRAS tRP tXSR MIN 1.5 0.8 1.5 37 15 67 -75 MAX 120,000 MIN 1.5 0.8 1.5 44 20 75 MAX 120,000 UNITS ns ns ns ns ns ns *CAS latency indicated in parentheses. NOTES: 1. No maximum time limit for Self Refresh. tRAS(MAX) applies to non-Self Refresh mode. 2. tXSR requires minimum of two clocks regardless of frequency or timing. 3. As a general rule, any time Self Refresh is exited, the DRAM may not reenter the Self Refresh mode until all rows have been refreshed by the Auto Refresh command at the distributed refresh rate, tREF, or faster. However, the following exceptions are allowed a. The DRAM has been in Self Refresh mode for a minimum of 64mS prior to exiting. b. TXSR is not violated c.. At least two Auto Refresh commands are preformed during each 7.81mS interval while the DRAM remains out of the Self Refresh mode. PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8 256MSDRAM.pmd – Rev. H; Pub. 2/05 44 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 256Mb: x4, x8, x16 SDRAM Figure 39: Read – Without Auto Precharge1 T0 T1 T2 tCK CLK T3 T4 T5 NOP NOP T6 T7 T8 NOP ACTIVE tCL tCH tCKS tCKH tCMS tCMH CKE COMMAND ACTIVE NOP READ tCMS NOP PRECHARGE tCMH DQM/ DQML, DQMU tAS A0-A9, A11, A12 tAH COLUMN m 2 ROW tAS ROW tAH ALL BANKS ROW A10 tAS BA0, BA1 ROW SINGLE BANK DISABLE AUTO PRECHARGE tAH BANK BANK BANK tAC tOH tAC DQ DOUT m tLZ tRCD BANK tAC tAC tOH DOUT m + 1 tOH tOH DOUT m + 2 DOUT m + 3 tHZ tRP CAS Latency tRAS tRC DON’T CARE UNDEFINED TIMING PARAMETERS -7E SYMBOL* tAC (3) tAC (2) tAH tAS tCH tCL tCK (3) tCK (2) tCKH tCKS MIN -75 MAX 5.4 5.4 0.8 1.5 2.5 2.5 7 7.5 0.8 1.5 MIN 0.8 1.5 2.5 2.5 7.5 10 0.8 1.5 -7E MAX 5.4 6 UNITS ns ns ns ns ns ns ns ns ns ns SYMBOL* tCMH tCMS tHZ (3) tHZ (2) tLZ tOH tRAS tRC tRCD tRP MIN 0.8 1.5 -75 MAX MIN 0.8 1.5 5.4 5.4 1 3 37 60 20 15 120,000 MAX 5.4 6 1 3 44 66 20 20 120,000 UNITS ns ns ns ns ns ns ns ns ns ns *CAS latency indicated in parentheses. NOTE: 1. For this example, the burst length = 4, the CAS latency = 2, and the READ burst is followed by a “manual” PRECHARGE. 2. x16: A9, A11, and A12 = “Don’t Care” x8: A11 and A12 = “Don’t Care” x4: A12 = “Don’t Care” PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8 256MSDRAM.pmd – Rev. H; Pub. 2/05 45 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 256Mb: x4, x8, x16 SDRAM Figure 40: Read – With Auto Precharge1 T0 T1 T2 tCK CLK tCKS T3 T4 T5 NOP NOP T6 T7 T8 NOP ACTIVE tCL tCH tCKH CKE tCMS tCMH COMMAND ACTIVE NOP READ tCMS NOP NOP tCMH DQM/ DQML, DQMU tAS A0-A9, A11, A12 tAH COLUMN m 2 ROW tAS tAH ROW ENABLE AUTO PRECHARGE ROW A10 tAS BA0, BA1 ROW tAH BANK BANK BANK tAC tOH tAC DQ DOUT m tLZ tRCD tAC tOH DOUT m + 1 tAC tOH DOUT m + 2 tOH DOUT m + 3 tHZ tRP CAS Latency tRAS tRC DON’T CARE UNDEFINED TIMING PARAMETERS -7E SYMBOL* tAC (3) tAC (2) tAH tAS tCH tCL tCK (3) tCK (2) tCKH tCKS MIN -75 MAX 5.4 5.4 0.8 1.5 2.5 2.5 7 7.5 0.8 1.5 MIN 0.8 1.5 2.5 2.5 7.5 10 0.8 1.5 -7E MAX 5.4 6 UNITS ns ns ns ns ns ns ns ns ns ns SYMBOL* tCMH tCMS tHZ (3) tHZ (2) tLZ tOH tRAS tRC tRCD tRP MIN 0.8 1.5 -75 MAX MIN 0.8 1.5 5.4 5.4 1 3 37 60 15 15 120,000 MAX 5.4 6 1 3 44 66 20 20 120,000 UNITS ns ns ns ns ns ns ns ns ns ns *CAS latency indicated in parentheses. NOTE: 1. For this example, the burst length = 4, and the CAS latency = 2. 2. x16: A9, A11, and A12 = “Don’t Care” x8: A11 and A12 = “Don’t Care” x4: A12 = “Don’t Care” PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8 256MSDRAM.pmd – Rev. H; Pub. 2/05 46 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 256Mb: x4, x8, x16 SDRAM Figure 41: Single Read – Without Autor Precharge1 T0 T1 T2 tCK CLK T3 T4 T5 NOP 2 NOP 2 T6 T7 T8 tCL tCH tCKS tCKH CKE tCMS tCMH COMMAND ACTIVE NOP READ PRECHARGE NOP ACTIVE NOP tCMS tCMH DQM / DQML, DQMU tAS A0-A9, A11,A12 tAH COLUMN m3 ROW tAS ROW tAH ALL BANKS ROW A10 tAS BA0, BA1 ROW DISABLE AUTO PRECHARGE tAH BANK SINGLE BANKS BANK tOH tAC DQ tLZ tRCD BANK BANK(S) DOUT m tHZ tRP CAS Latency tRAS tRC DON’T CARE UNDEFINED TIMING PARAMETERS -7E SYMBOL* tAC (3) tAC (2) tAH tAS tCH tCL tCK (3) tCK (2) tCKH tCKS MIN -75 MAX 5.4 5.4 0.8 1.5 2.5 2.5 7 7.5 0.8 1.5 MIN 0.8 1.5 2.5 2.5 7.5 10 0.8 1.5 -7E MAX 5.4 6 UNITS ns ns ns ns ns ns ns ns ns ns SYMBOL* tCMH tCMS tHZ (3) tHZ (2) tLZ tOH tRAS tRC tRCD tRP MIN 0.8 1.5 -75 MAX MIN 0.8 1.5 5.4 5.4 1 3 37 60 15 15 120,000 MAX 5.4 6 1 3 44 66 20 20 120,000 UNITS ns ns ns ns ns ns ns ns ns ns *CAS latency indicated in parentheses. NOTE: 1. For this example, the burst length = 1, the CAS latency = 2, and the READ burst is followed by a “manual” PRECHARGE. 2. PRECHARGE command not allowed else tRAS would be violated. 3. x16: A9, A11, and A12 = “Don’t Care” x8: A11 and A12 = “Don’t Care” x4: A12 = “Don’t Care” PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8 256MSDRAM.pmd – Rev. H; Pub. 2/05 47 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 256Mb: x4, x8, x16 SDRAM Figure 42: Single Read – With Auto Precharge1 T0 T1 T2 tCK CLK tCKS T3 T4 T5 T6 T7 T8 tCL tCH tCKH CKE tCMS tCMH COMMAND ACTIVE NOP2 NOP NOP2 READ tCMS NOP NOP ACTIVE NOP tCMH DQM / DQML, DQMU tAS A0-A9, A11 tAS A10 COLUMN m3 tAH ROW ENABLE AUTO PRECHARGE ROW tAS BA0, BA1 tAH ROW ROW tAH BANK BANK BANK tAC t OH DOUT m DQ tRCD CAS Latency tHZ tRP tRAS tRC DON’T CARE UNDEFINED TIMING PARAMETERS -7E SYMBOL* tAC (3) tAC (2) tAH tAS tCH tCL tCK (3) tCK (2) tCKH tCKS MIN -75 MAX 5.4 5.4 0.8 1.5 2.5 2.5 7 7.5 0.8 1.5 MIN 0.8 1.5 2.5 2.5 7.5 10 0.8 1.5 -7E MAX 5.4 6 UNITS ns ns ns ns ns ns ns ns ns ns SYMBOL* tCMH tCMS tHZ (3) tHZ (2) tLZ tOH tRAS tRC tRCD tRP MIN 0.8 1.5 -75 MAX MIN 0.8 1.5 5.4 5.4 1 3 37 60 15 15 120,000 MAX 5.4 6 1 3 44 66 20 20 120,000 UNITS ns ns ns ns ns ns ns ns ns ns *CAS latency indicated in parentheses. NOTE: 1. For this example, the burst length = 1, and the CAS latency = 2. 2. PRECHARGE command not allowed else tRAS would be violated. 3. x16: A9, A11, and A12 = “Don’t Care” x8: A11 and A12 = “Don’t Care” x4: A12 = “Don’t Care” PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8 256MSDRAM.pmd – Rev. H; Pub. 2/05 48 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 256Mb: x4, x8, x16 SDRAM Figure 43: Alternating Bank Read Accesses1 T0 T1 T2 tCK CLK T3 T4 T5 NOP ACTIVE T6 T7 T8 READ NOP ACTIVE tCL tCH tCKS tCKH tCMS tCMH CKE COMMAND ACTIVE NOP READ tCMS NOP tCMH DQM/ DQML, DQMU tAS A0-A9, A11, A12 tAS COLUMN m 2 tAH tAS COLUMN b 2 ROW ENABLE AUTO PRECHARGE ROW ENABLE AUTO PRECHARGE ROW A10 BA0, BA1 tAH ROW ROW ROW tAH BANK 0 BANK 0 BANK 3 tAC DQ DOUT m tLZ tRCD - BANK 0 BANK 3 tAC tOH tAC tOH DOUT m + 1 BANK 0 tAC tOH DOUT m + 2 tAC tOH tAC tOH DOUT m + 3 DOUT b tRCD - BANK 0 tRP - BANK 0 CAS Latency - BANK 0 tRAS - BANK 0 tRC - BANK 0 tRCD - BANK 3 tRRD CAS Latency - BANK 3 DON’T CARE UNDEFINED TIMING PARAMETERS -7E SYMBOL* tAC (3) tAC (2) tAH tAS tCH tCL tCK (3) tCK (2) tCKH tCKS MIN -75 MAX 5.4 5.4 0.8 1.5 2.5 2.5 7 7.5 0.8 1.5 MIN 0.8 1.5 2.5 2.5 7.5 10 0.8 1.5 -7E MAX 5.4 6 UNITS ns ns ns ns ns ns ns ns ns ns SYMBOL* tCMH tCMS tLZ tOH tRAS tRC tRCD tRP tRRD MIN 0.8 1.5 1 3 37 60 15 15 14 -75 MAX 120,000 MIN 0.8 1.5 1 3 44 66 20 20 15 MAX 120,000 UNITS ns ns ns ns ns ns ns ns ns *CAS latency indicated in parentheses. NOTE: 1. For this example, the burst length = 4, and the CAS latency = 2. 2. x16: A9, A11, and A12 = “Don’t Care” x8: A11 and A12 = “Don’t Care” x4: A12 = “Don’t Care” PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8 256MSDRAM.pmd – Rev. H; Pub. 2/05 49 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 256Mb: x4, x8, x16 SDRAM Figure 44: Read – Full-Page Burst1 T0 T1 T2 tCL CLK T3 T4 T5 T6 (( )) (( )) tCK tCH tCKS tCMH ACTIVE NOP READ tCMS NOP NOP NOP NOP tCMH tAS tAH tAH NOP BURST TERM NOP NOP (( )) (( )) ROW tAS (( )) (( )) (( )) (( )) COLUMN m 2 ROW tAS BA0, BA1 Tn + 4 (( )) (( )) DQM/ DQML, DQMU A10 Tn + 3 (( )) (( )) tCMS A0-A9, A11, A12 Tn + 2 tCKH CKE COMMAND Tn + 1 tAH BANK (( )) (( )) BANK tAC tAC tOH DOUT m DQ tAC DOUT m+1 tLZ tRCD tAC ( ( tOH ) ) tOH DOUT tAC (( )) m+2 (( )) tAC tOH tOH tOH DOUT m-1 Dout m DOUT m+1 tHZ 512 (x16) locations within same row 1,024 (x8) locations within same row 2,048 (x4) locations within same row CAS Latency Full page completed DON’T CARE Full-page burst does not self-terminate. 3 Can use BURST TERMINATE command. UNDEFINED TIMING PARAMETERS -7E SYMBOL* tAC (3) tAC (2) tAH tAS tCH tCL tCK (3) tCK (2) tCKH MIN -75 MAX 5.4 5.4 0.8 1.5 2.5 2.5 7 7.5 0.8 MIN -7E MAX 5.4 6 0.8 1.5 2.5 2.5 7.5 10 0.8 UNITS ns ns ns ns ns ns ns ns ns SYMBOL* tCKS tCMH tCMS tHZ (3) tHZ (2) tLZ tOH tRCD MIN 1.5 0.8 1.5 -75 MAX MIN 1.5 0.8 1.5 5.4 5.4 1 3 15 MAX 5.4 6 1 3 20 UNITS ns ns ns ns ns ns ns ns *CAS latency indicated in parentheses. NOTE: 1. For this example, the CAS latency = 2. 2. x16: A9, A11, and A12 = “Don’t Care” x8: A11 and A12 = “Don’t Care” x4: A12 = “Don’t Care” 3. Page left open; no tRP. PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8 256MSDRAM.pmd – Rev. H; Pub. 2/05 50 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 256Mb: x4, x8, x16 SDRAM Figure 45: Read – DQM Operation1 T0 T1 T2 tCK CLK tCKS tCKH tCMS tCMH T3 T4 T5 NOP NOP T6 T7 T8 NOP NOP NOP tCL tCH CKE COMMAND ACTIVE NOP READ tCMS NOP tCMH DQM/ DQML, DQMU tAS A0-A9, A11, A12 tAH COLUMN m 2 ROW tAS tAH ENABLE AUTO PRECHARGE ROW A10 tAS BA0, BA1 DISABLE AUTO PRECHARGE tAH BANK BANK tAC DQ tOH DOUT m tLZ tRCD tAC tOH tAC tHZ tOH DOUT m + 2 DOUT m + 3 tLZ tHZ CAS Latency DON’T CARE UNDEFINED TIMING PARAMETERS -7E SYMBOL* tAC (3) tAC (2) tAH tAS tCH tCL tCK (3) tCK (2) tCKH MIN -75 MAX 5.4 5.4 0.8 1.5 2.5 2.5 7 7.5 0.8 MIN 0.8 1.5 2.5 2.5 7.5 10 0.8 -7E MAX 5.4 6 UNITS ns ns ns ns ns ns ns ns ns SYMBOL* tCKS tCMH tCMS tHZ (3) tHZ (2) tLZ tOH tRCD MIN 1.5 0.8 1.5 -75 MAX MIN 1.5 0.8 1.5 5.4 5.4 1 3 15 MAX 5.4 6 1 3 20 UNITS ns ns ns ns ns ns ns ns *CAS latency indicated in parentheses. NOTE: 1. For this example, the burst length = 4, and the CAS latency = 2. 2. x16: A9, A11, and A12 = “Don’t Care” x8: A11 and A12 = “Don’t Care” x4: A12 = “Don’t Care” PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8 256MSDRAM.pmd – Rev. H; Pub. 2/05 51 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 256Mb: x4, x8, x16 SDRAM Figure 46: Write – Without Auto Precharge1 T0 tCK CLK T1 T2 tCL T3 T4 T5 T6 NOP NOP NOP NOP T7 T8 T9 tCH tCKS tCKH tCMS tCMH CKE COMMAND ACTIVE NOP WRITE NOP PRECHARGE ACTIVE tCMS tCMH DQM/ DQML, DQMU tAS A0-A9, A11, A12 tAS A10 COLUMN m 2 ROW tAH ALL BANKs ROW tAS BA0, BA1 tAH ROW ROW tAH DISABLE AUTO PRECHARGE SINGLE BANK BANK BANK BANK tDS tDH DIN m DQ tDS tDH DIN m + 1 tDS tDH DIN m + 2 tDS BANK tDH DIN m + 3 t WR 3 tRCD tRAS tRP tRC DON’T CARE TIMING PARAMETERS -7E SYMBOL* tAH tAS tCH tCL tCK (3) tCK (2) tCKH tCKS tCMH MIN 0.8 1.5 2.5 2.5 7 7.5 0.8 1.5 0.8 -7E -75 MAX MIN 0.8 1.5 2.5 2.5 7.5 10 0.8 1.5 0.8 MAX SYMBOL* tCMS tDH tDS tRAS tRC tRCD tRP tWR UNITS ns ns ns ns ns ns ns ns ns MIN 1.5 0.8 1.5 37 60 15 15 14 -75 MAX 120,000 MIN 1.5 0.8 1.5 44 66 20 20 15 MAX 120,000 UNITS ns ns ns ns ns ns ns ns *CAS latency indicated in parentheses. NOTE: 1. For this example, the burst length = 4, and the WRITE burst is followed by a “manual” PRECHARGE. 2. 14ns to 15ns is required between <DIN m+3> and the PRECHARGE command, regardless of frequency. 3. x16: A9, A11, and A12 = “Don’t Care” x8: A11 and A12 = “Don’t Care” x4: A12 = “Don’t Care” PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8 256MSDRAM.pmd – Rev. H; Pub. 2/05 52 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 256Mb: x4, x8, x16 SDRAM Figure 47: Write – With Auto Precharge1 T0 tCK CLK tCKS tCKH tCMS tCMH T1 T2 tCL T3 T4 T5 T6 T7 T8 T9 NOP NOP NOP NOP NOP NOP ACTIVE tCH CKE COMMAND ACTIVE NOP WRITE tCMS tCMH DQM/ DQML, DQMU tAS A0-A9, A11, A12 tAH COLUMN m 2 ROW tAS tAH ROW ENABLE AUTO PRECHARGE ROW A10 tAS BA0, BA1 ROW tAH BANK BANK tDS BANK tDH DIN m DQ tDS tDH DIN m + 1 tDS tDH DIN m + 2 tDS tDH DIN m + 3 tRCD tRAS tRP tWR tRC DON’T CARE TIMING PARAMETERS -7E SYMBOL* tAH tAS tCH tCL tCK (3) tCK (2) tCKH tCKS tCMH MIN 0.8 1.5 2.5 2.5 7 7.5 0.8 1.5 0.8 -75 MAX MIN 0.8 1.5 2.5 2.5 7.5 10 0.8 1.5 0.8 -7E MAX UNITS ns ns ns ns ns ns ns ns ns SYMBOL* tCMS tDH tDS tRAS tRC tRCD tRP tWR MIN 1.5 0.8 1.5 37 60 15 15 1 CLK + 7ns -75 MAX 120,000 MIN 1.5 0.8 1.5 44 66 20 20 1 CLK + 7.5ns MAX 120,000 UNITS ns ns ns ns ns ns ns – *CAS latency indicated in parentheses. NOTE: 1. For this example, the burst length = 4. 2. x16: A9, A11, and A12 = “Don’t Care” x8: A11 and A12 = “Don’t Care” x4: A12 = “Don’t Care” PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8 256MSDRAM.pmd – Rev. H; Pub. 2/05 53 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 256Mb: x4, x8, x16 SDRAM Figure 48: Single Write – Without Auto Precharge1 T0 tCK CLK T1 T2 tCL T3 T4 NOP 2 NOP 2 T5 T6 T7 T8 ACTIVE NOP tCH tCKS tCKH tCMS tCMH CKE COMMAND ACTIVE NOP WRITE PRECHARGE NOP tCMS tCMH DQM / DQML, DQMU tAS A0-A9, A11 tAS A10 COLUMN m 3 tAH ALL BANKS ROW tAS BA0, BA1 tAH ROW ROW tAH DISABLE AUTO PRECHARGE SINGLE BANK BANK BANK BANK tDS BANK tDH DIN m DQ tRCD tRAS tRP t WR 4 tRC DON’T CARE TIMING PARAMETERS -7E SYMBOL* tAH tAS tCH tCL tCK (3) tCK (2) tCKH tCKS tCMH MIN 0.8 1.5 2.5 2.5 7 7.5 0.8 1.5 0.8 -75 MAX MIN 0.8 1.5 2.5 2.5 7.5 10 0.8 1.5 0.8 -7E MAX UNITS ns ns ns ns ns ns ns ns ns SYMBOL* tCMS tDH tDS tRAS tRC tRCD tRP tWR MIN 1.5 0.8 1.5 37 60 15 15 14 -75 MAX 120,000 MIN 1.5 0.8 1.5 44 66 20 20 15 MAX 120,000 UNITS ns ns ns ns ns ns ns ns *CAS latency indicated in parentheses. NOTE: 1. For this example, the burst length = 1, and the WRITE burst is followed by a “manual” PRECHARGE. 2. 14ns to 15ns is required between <DIN m> and the PRECHARGE command, regardless of frequency. With a single write tWR has been increased to meet minimum tRAS requirement. 3. x16: A8, A9, and A11 = “Don’t Care” x8: A9 and A11 = “Don’t Care” x4: A11 = “Don’t Care” 4. PRECHARGE command not allowed else tRAS would be violated. PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8 256MSDRAM.pmd – Rev. H; Pub. 2/05 54 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 256Mb: x4, x8, x16 SDRAM Figure 49: Single Write – With Auto Precharge1 T0 tCK CK tCKS tCKH tCMS tCMH T1 T2 tCL T3 T4 T5 T6 T7 WRITE NOP NOP NOP T8 T9 tCH CKE COMMAND NOP2 ACTIVE NOP2 NOP2 tCMS NOP ACTIVE tCMH DQM/ DQML, DQMU tAS A0-A9, A11, A12 tAS A10 COLUMN m 3 tAH ROW ENABLE AUTO PRECHARGE ROW tAS BA0, BA1 tAH ROW ROW tAH BANK BANK tDS BANK tDH DIN m DQ tRCD tRAS tRP tWR4 tRC DON’T CARE TIMING PARAMETERS -7E SYMBOL* tAH tAS tCH tCL tCK (3) tCK (2) tCKH tCKS tCMH MIN 0.8 1.5 2.5 2.5 7 7.5 0.8 1.5 0.8 -75 MAX MIN 0.8 1.5 2.5 2.5 7.5 10 0.8 1.5 0.8 -7E MAX UNITS ns ns ns ns ns ns ns ns ns SYMBOL* tCMS tDH tDS tRAS tRC tRCD tRP tWR MIN 1.5 0.8 1.5 37 60 15 15 1 CLK + 7ns -75 MAX 120,000 MIN 1.5 0.8 1.5 44 66 20 20 1 CLK + 7.5ns MAX 120,000 UNITS ns ns ns ns ns ns ns – *CAS latency indicated in parentheses. NOTE: 1. For this example, the burst length = 1. 2. Requires one clock plus time (7ns to 7.5ns) with auto precharge or 14ns to 15ns with PRECHARGE. 3. x16: A9, A11, and A12 = “Don’t Care” x8: A11 and A12 = “Don’t Care” x4: A12 = “Don’t Care” 4. WRITE command not allowed else tRAS would be violated. PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8 256MSDRAM.pmd – Rev. H; Pub. 2/05 55 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 256Mb: x4, x8, x16 SDRAM Figure 50: Alternating Bank Write Accesses1 T0 tCK CLK T1 T2 tCL T3 T4 T5 T6 T7 T8 T9 NOP NOP ACTIVE tCH tCKS tCKH tCMS tCMH CKE COMMAND ACTIVE NOP WRITE tCMS NOP ACTIVE NOP WRITE tCMH DQM/ DQML, DQMU tAS A0-A9, A11, A12 tAS A10 COLUMN m 3 tAH COLUMN b 3 ROW ENABLE AUTO PRECHARGE ROW ENABLE AUTO PRECHARGE ROW tAS BA0, BA1 tAH ROW ROW ROW tAH BANK 0 BANK 0 tDS tDH DIN m DQ BANK 1 tDS tDH DIN m + 1 tDS tDH DIN m + 2 BANK 1 tDS tDH DIN m + 3 tDS BANK 0 tDH DIN b tDS DIN b + 1 tDS tDH tDS DIN b + 2 tDH DIN b + 3 tRP - BANK 0 tWR - BANK 0 tRCD - BANK 0 tDH tRCD - BANK 0 tRAS - BANK 0 tRC - BANK 0 tWR - BANK 1 tRCD - BANK 1 tRRD DON’T CARE TIMING PARAMETERS -7E SYMBOL* tAH tAS tCH tCL tCK (3) tCK (2) tCKH tCKS tCMH MIN 0.8 1.5 2.5 2.5 7 7.5 0.8 1.5 0.8 -7E -75 MAX MIN 0.8 1.5 2.5 2.5 7.5 10 0.8 1.5 0.8 MAX SYMBOL* tCMS tDH tDS tRAS tRC tRCD tRP tRRD tWR UNITS ns ns ns ns ns ns ns ns ns MIN 1.5 0.8 1.5 37 60 15 15 14 Note 2 -75 MAX 120,000 MIN 1.5 0.8 1.5 44 66 20 20 15 Note 2 MAX 120,000 UNITS ns ns ns ns ns ns ns ns ns *CAS latency indicated in parentheses. NOTE: 1. For this example, the burst length = 4. 2. Requires one clock plus time (7ns or 7.5ns) with auto precharge or 14ns to 15ns with PRECHARGE. 3. x16: A9, A11, and A12 = “Don’t Care” x8: A11 and A12 = “Don’t Care” x4: A12 = “Don’t Care” PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8 256MSDRAM.pmd – Rev. H; Pub. 2/05 56 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 256Mb: x4, x8, x16 SDRAM Figure 51: Write – Full-Page Burst T0 T1 T2 tCL CLK T3 T4 T5 tCKS tCKH tCMS tCMH ACTIVE NOP WRITE NOP NOP NOP tCMS tCMH A0-A9, A11, A12 tAH tAH tAS BA0, BA1 NOP BURST TERM NOP (( )) (( )) ROW A10 (( )) (( )) (( )) (( )) COLUMN m 1 ROW tAS Tn + 3 (( )) (( )) DQM/ DQML, DQMU tAS Tn + 2 (( )) (( )) CKE COMMAND Tn + 1 (( )) (( )) tCK tCH tAH BANK (( )) (( )) BANK tDS tDH tDS DIN m DQ tDH DIN m + 1 tDS tDH DIN m + 2 tDS tDH DIN m + 3 tRCD (( )) (( )) tDS tDH DIN m - 1 512 (x16) locations within same row 1,024 (x8) locations within same row 2,048 (x4) locations within same row Full-page burst does not self-terminate. Can use BURST TERMINATE command to stop.2, 3 Full page completed DON’T CARE TIMING PARAMETERS -7E SYMBOL* tAH tAS tCH tCL tCK (3) tCK (2) tCKH MIN 0.8 1.5 2.5 2.5 7 -75 MAX 7.5 0.8 MIN 0.8 1.5 2.5 2.5 7.5 10 0.8 -7E MAX UNITS ns ns ns ns ns SYMBOL* tCKS tCMH tCMS tDH tDS tRCD ns ns MIN 1.5 0.8 1.5 0.8 1.5 15 -75 MAX MIN 1.5 0.8 1.5 0.8 1.5 20 MAX UNITS ns ns ns ns ns ns *CAS latency indicated in parentheses. NOTE: 1. x16: A9, A11, and A12 = “Don’t Care” x8: A11 and A12 = “Don’t Care” x4: A12 = “Don’t Care” 2. tWR must be satisfied prior to PRECHARGE command. 3. Page left open; no tRP. PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8 256MSDRAM.pmd – Rev. H; Pub. 2/05 57 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 256Mb: x4, x8, x16 SDRAM Figure 52: Write – DQM Operation1 T0 T1 T2 tCK CLK T3 T4 T5 NOP NOP NOP T6 T7 NOP NOP tCL tCH tCKS tCKH tCMS tCMH CKE COMMAND ACTIVE NOP WRITE tCMS tCMH DQM/ DQML, DQMU tAS A0-A9, A11, A12 tAH COLUMN m 2 ROW tAS tAH ENABLE AUTO PRECHARGE ROW A10 tAS BA0, BA1 tAH DISABLE AUTO PRECHARGE BANK BANK tDS tDH tDS DIN m DQ tDS tDH DIN m + 2 tDH DIN m + 3 tRCD DON’T CARE TIMING PARAMETERS -7E SYMBOL* tAH tAS tCH tCL tCK (3) tCK (2) tCKH MIN 0.8 1.5 2.5 2.5 7 7.5 0.8 -75 MAX MIN 0.8 1.5 2.5 2.5 7.5 10 0.8 -7E MAX UNITS ns ns ns ns ns ns ns SYMBOL* tCKS tCMH tCMS tDH tDS tRCD MIN 1.5 0.8 1.5 0.8 1.5 15 -75 MAX MIN 1.5 0.8 1.5 0.8 1.5 20 MAX UNITS ns ns ns ns ns ns *CAS latency indicated in parentheses. NOTE: 1. For this example, the burst length = 4. 2. x16: A9, A11, and A12 = “Don’t Care” x8: A11 and A12 = “Don’t Care” x4: A12 = “Don’t Care” PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8 256MSDRAM.pmd – Rev. H; Pub. 2/05 58 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 256Mb: x4, x8, x16 SDRAM Figure 53: 54-PIN PLASTIC TSOP (400 mil) SEE DETAIL A 22.22 ±.08 .71 .80 TYP 2X 0.10 .375 ±.075 TYP 2.80 11.76 ±0.20 10.16 ±0.08 R 2X 0.75 0.15 PIN #1 ID +0.03 -0.02 GAGE PLANE R 2X 1.00 0.25 0.10 0.10 PLATED LEAD FINISH: 90% Sn, 10% Pb OR 100%Sn +0.10 -0.05 0.50 ±0.10 1.2 MAX 0.80 TYP PLASTIC PACKAGE MATERIAL: EPOXY NOVOLAC PACKAGE WIDTH AND LENGTH DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 PER SIDE. DETAIL A NOTE: 1. All dimensions in millimeters . 2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side. PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8 256MSDRAM.pmd – Rev. H; Pub. 2/05 59 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 256Mb: x4, x8, x16 SDRAM Figure 54: FBGA “FB” Package, 60-Ball, 8mm x 16mm x4, x8 .205 MAX .850 ±.075 .10 A SEATING PLANE SOLDER BALL MATERIAL: 62% Sn, 36% Pb, 2% Ag SOLDER BALL PAD: Ø 0.33mm A SUBSTRATE: PLASTIC LAMINATE ENCAPSULATION MATERIAL: EPOXY NOVOLAC 8.00 ±.10 5.60 .80 TYP 60X Ø .45 PIN #1 ID PIN #1 ID BALL A1 BALL A8 .80 TYP 8.00 ±.05 16.00 ±.10 11.20 5.60 ±.05 2.40 ±.05 CTR 2.80 ±.05 1.20 MAX 4.00 ±.05 (Bottom View) NOTE: 1. All dimensions in millimeters. 2. Recommended Pad size for PCB is 0.33mm±0.025mm. 3. Top side part marking decode can be found at: http://www.micron.com/products/fbga/FBGA.asp PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8 256MSDRAM.pmd – Rev. H; Pub. 2/05 60 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 256Mb: x4, x8, x16 SDRAM Figure 55: VFBGA “FG” Package, 54-ball, 8mm x 14mm x16 0.65 ±0.05 SEATING PLANE C 0.10 C 6.40 1.00 MAX BALL A1 ID 0.80 TYP 54X Ø0.45 SOLDER BALL DIAMETER REFERS TO POST REFLOW CONDITION. THE PREREFLOW DIAMETER IS Ø0.42 BALL A9 BALL A1 ID BALL A1 0.80 TYP CL 6.40 14.00 ±0.10 3.20 ±0.05 7.00 ±0.05 3.20 ±0.05 CL 4.00 ±0.05 MOLD COMPOUND: EPOXY NOVOLAC SUBSTRATE MATERIAL: PLASTIC LAMINATE 8.00 ±0.10 SOLDER BALL MATERIAL: 62% Sn, 36% Pb, 2% Ag OR 96.5% Sn, 3%Ag, 0.5% Cu SOLDER MASK DEFINED BALL PADS: Ø 0.40 (Bottom View) NOTE: 1. All dimensions in millimeters. 2. Recommended Pad size for PCB is 0.4mm±0.065mm. 3. Top side part marking decode can be found at: http://www.micron.com/products/fbga/FBGA.asp DATA SHEET DESIGNATION Production: This data sheet contains minimum and maximum limits specified over the complete power supply and temperature range for production devices. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: [email protected], Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8 256MSDRAM.pmd – Rev. H; Pub. 2/05 61 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved.