MYSON TECHNOLOGY MTU8B54E/55E/56E/57E EPROM-Based 8-Bit CMOS Microcontroller FEATURES • Total of 33 single word instructions . • The fast execution time may be 200ns for all single cycle instructions under 20MHz operating. • Operating voltage range: 2.3V ~ 6.5V • 8-bit data bus. • 14-bit instruction word. • Four-level stacks. • On chip EPROM size : 512x14 bits for MTU8B54E/55E, 1Kx14 bits for MTU8B56E, 2Kx14 bits for MTU8B57E. • Internal RAM size : 25 bytes for MTU8B54E/56E, 24 bytes for MTU8B55E, • 72 bytes for MTU8B57E. • Direct and indirect addressing modes for data accessing • 8-bit real time clock/counter with 8-bit programmable prescaler. • Internal power-on Reset. • Device Reset Timer. • Code protection. • Sleep mode for power saving. • On chip Watchdog Timer(WDT) based on internal RC oscillator. • Three I/O ports PA, PB nad PC with independent direction control. • 4 types of oscillator can be selected by code options: - RC : Low-cost RC oscillator - XTAL : Standard crystal oscillator - HFXTAL : High frequency crystal oscillator - LFXTAL : Low frequency crystal oscillator GENERAL DESCRIPTION MTU8B5X series is an EPROM based 8-bit microcontroller which employs a full CMOS technology enhanced with low-cost, high speed and high noise immunity. Watchdog Timer, RAM, EPROM, tri-state I/O port, power down mode, and real time programmable clock/counter are integrated into this chip. MTU8B5X contains 33 instructions, all are single cycle except for program branches which take two cycles. On chip memory is available with 512x14 bits of EPROM for MTU8B54E/55E, 1Kx14 bits of EPROM for MTU8B56E, 2Kx14 bits of EPROM for MTU8B57E and 24 to 72 bytes of static RAM. BLOCK DIAGRAM Vdd Vss Osc Mode 2 Select Enable /Disable Configuration Word 11 Four-level Stack 11 WatchDog Timer OSCI OSCO MCLR Program Counter EPROM 512 X 14 TO 2048 X 14 Oscillator Circuit Sleep 14 Instruction Register T0CKI WDT/Timer0 Prescaler WDT Time Out 14 Timer0 T0MODE Register 6 Data 6 Instruction Decoder 8 RAM PortA 24, 25 or 27 Bytes Accumulator PortB 4 8 PA3:PA0 PB7:PB0 FSR PortC Status ALU 8 PC7:PC0 Only in MTU8B55E/57E 8 This datasheet contains new product information. Myson Technology reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of this procuts. No rights under any patent accompany the sales of the product. Revision 1.2 -1 - 24 October 2000 MYSON TECHNOLOGY MTU8B54E/55E/56E/57E 1.0 PIN CONNECTION T0CKI Vdd PA2 PA3 T0CKI MCLR/Vpp Vss PB0 PB1 PB2 PB3 1 2 3 4 5 MTU8B54E 6 MTU8B56E 7 8 9 18 17 16 15 14 13 12 11 10 N/C PA1 PA0 OSCI OSCO Vdd PB7 PB6 PB5 PB4 Vss N/C PA0 PA1 PA2 PA3 PB0 PB1 PB2 PB3 PB4 1 2 3 4 5 6 7 MTU8B55E 8 MTU8B57E 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 MCLR/Vpp OSCI OSCO PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PB7 PB6 PB5 2.0 PIN DESCRIPTIONS Name I/O OSCI I OSCO O Descriptions RC type: Input pin of RC oscillator XTAL type: Input terminal of crystal oscillator RC type: OSCO outputs with 1/4 frequency of OSCI to denotes the cycle rate for instruction. XTAL type: Output terminal of crystal oscillator T0CKI/SCL I Input pin of real time counter/clock. Must be tied to Vss or Vdd if not in use. Input pin for device reset or high voltage programming input for EPROM. If this pin is low, the device is reset. MCLR/Vpp I PA0~PA3 I/O PA0~PA3 as bi-directional I/O port PB0~PB7 I/O PB0~PB7 as bi-directional I/O port PC0~PC7 I/O PC0~PC7 as bi-directional I/O port Vdd - Power supply Vss - Ground Revision 1.2 In programmimg mode, this pin is connected to 12V. In normal operating mode, this pin must not exceed Vdd to avoid entering unintended programming mode. -2- 24 October 2000 MYSON TECHNOLOGY MTU8B54E/55E/56E/57E 3.0 FUNCTIONAL DESCRIPTIONS 3.1 REGISTER MAP The register map of MTU8B5X is depicted as below:. The Register Map of MTU8B55E The Register Map of MTU8B54E/56E Address Description Address Description 00h Indirect Addressing Register 00h Indirect Addressing Register 01h Timer0 01h Timer0 02h PC 02h PC 03h STATUS 03h STATUS 04h FSR 04h FSR 05h PORTA 05h PORTA 06h PORTB 06h PORTB General Purpose Register 07h PORTC 07h-1Fh 08h-1Fh General Purpose Register The Register Map of MTU8B57E Address Description FSR<6:5> Bank 1 Bank 2 Bank 3 00 01 10 11 00h Indirect Addressing Register 01h Timer0 02h PC 03h STATUS 04h FSR 05h PORTA 06h PORTB 07h PORTC 08h~0Fh Revision 1.2 Bank 0 Map back to address in Bank 0 General Purpose Register 10h~1Fh 30h~3Fh 50h~5Fh 70h~7Fh General Purpose General Purpose General Purpose General Purpose Register Register Register Register -3- 24 October 2000 MYSON TECHNOLOGY MTU8B54E/55E/56E/57E 3.1.1 INAR(Indirect Address Register) : R0 R0 is not a physically implemented register. It is used as an indirect addressing pointer. Any instruction accessing this register can access data pointed by FSR(R4). 3.1.2 Timer0(8-bit real-time clock/timer) : R1 This register increases by an external signal edge applied to T0CKI pin, or by internal instruction cycle. It can be read or written as any other register. 3.1.3 PC(Program Counter) : R2 This register increases itself every instruction cycle, except the following condition shown in Figure 1: LCALL, LGOTO : from instruction word RETIA : from STACK LCALL A10~A0 RETIA Stack1 Stack2 Stack3 Stack4 FIGURE 1. Program Counter 3.1.4 STATUS(Status Register): The content of R3 is listed in Table 1. TABLE 1. STATUS Register Bit Symbol Carry/borrow bit 0 C Description ADDWF SUBWF = 1, a carry occurred = 1, a borrow did not occur = 0, a carry did not occur Half carry/half borrow bit = 0, a borrow occurred ADDWF = 1, a carry from the 4th low order bit of the result occurred 1 DC = 0, a carry from the 4th low order bit of the result did not occur SUBWF = 1, a borrow from the 4th low order bit of the result did not occur = 0, a borrow from the 4th low order bit of the result occurred Zero bit: 2 Z = 1, the result of a logic operation is zero = 0, the result of a logic operation is not zero Power down flag bit: 3 PD = 1, after power-up or by the CLRWDT instruction = 0, by the SLEEP instruction Time overflow flag bit: 4 TO 5, 6, 7 - Revision 1.2 = 1, after power-up or by the CLRWDT or SLEEP instruction = 0, a WDT time-overflow occurred Unused -4- 24 October 2000 MYSON TECHNOLOGY MTU8B54E/55E/56E/57E 3.1.5 FSR(File select register pointer): R4 Bit 0~4 are used to select up to 32 registers (address: 00h~1Fh) and Bit 5~6 are Bank Select (Bank0~3) in the indirect addressing mode shown in Figure 2. 3.1.6 PORT A: R5 PA3:PA0, bi-directional I/O Register 3.1.7 PORT B: R6 PB7:PB0, bi-directional I/O Register 3.1.8 PORT C: R7 PB7:PB0, bi-directional I/O Register, and for MTU8B55E/57E only 3.1.9 T0MODE REGISTER: T0MODE is a write-only register and the content is listed in Table 2. 3.1.10 IOST (Control Port I/O Mode Register) The IOST register is “write-only” = 0, I/O pin in output mode; = 1, I/O pin in input mode. Indirect Addressing Mode Location Select Bank Select B7 B6 B5 B4 B3 B2 B1 B0 Read 1 70h 50h Bank 3 Bank 2 30h Bank 1 Bank 0 10h 16 Bytes SRAM 7Fh 5Fh 3Fh 1Fh 00h 01h 02h 03h 04h 05h 06h 07h 08h 0Fh INAR Timer0 PC STATUS FSR PORT A PORT B PORT C 8 Bytes SRAM Bank 0 FIGURE 2. Data Memory Configuraion Revision 1.2 -5- 24 October 2000 MYSON TECHNOLOGY MTU8B54E/55E/56E/57E TABLE 2. T0MODE Register Bit Symbol Description Bit Value 2-0 PS2:PS0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 Timer Rate WDT Rate 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256 1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128 0 1 0 1 0 1 0 1 Prescaler assign bit: 3 PSC = 0, Timer0 = 1, WDT Timer0 source signal edge select bit: 4 TE = 0, increment when low-to-high transition on T0CKI pin = 1, increment when high-to-low transition on T0CKI pin Timer0 source signal select bit: 5 TS = 0, internal instruction clock cycle = 1, transition on T0CKI pin 6, 7 Revision 1.2 - Unused -6- 24 October 2000 MYSON TECHNOLOGY MTU8B54E/55E/56E/57E 3.2 INSTRUCTION SET Mnemonic Operands Description Cycles Instruction Code Status Affected BCR R, bit Clear bit in R 1 11 11bb brrr rrrr None BSR R, bit Set bit in R 1 11 10bb brrr rrrr None BTRSC R, bit Test bit in R and skip if clear 11 01bb brrr rrrr None BTRSS R, bit Test bit in R and skip if set 11 00bb brrr rrrr None CLRWDT Clear Watchdog Timer 1 01 0000 0000 0001 TO, PD T0MODE Load T0MODE Register 1 01 0000 0000 0010 None SLEEP Go into standby mode 1 01 0000 0000 0011 TO, PD IOST R Load IOST Register 1 01 0000 0000 0rrr None ANDIA I AND immediate with Acc 1 00 1001 iiii iiii Z XORIA I Exclusive OR immediate with Acc 1 00 1000 iiii iiii Z MOVIA I Move immediate to Acc 1 00 0001 iiii iiii None IORIA I Inclusive OR immediate with Acc 1 00 0011 iiii iiii Z RETIA I Return, place immediate in A 2 00 1100 iiii iiii None LCALL I Call subroutine 2 10 0iii iiii iiii None LGOTO I Unconditional branch 2 10 1iii iiii iiii None NOP No operation 1 01 0000 0000 0000 None MOVAR R Move Acc to R 1 01 0000 1rrr rrrr None COMR R, d Complement R 1 01 0010 drrr rrrr Z MOVR R Move R 1 01 0011 drrr rrrr Z RRR R, d Rotate right R 1 01 1110 drrr rrrr C RLR R, d Rotate left R 1 01 1100 drrr rrrr C SWAPR R, d Swap halves R 1 01 1101 drrr rrrr None CLRA Clear Acc 1 01 0001 0000 0000 Z CLRR R Clear R 1 01 0001 1rrr rrrr Z INCR R, d Increment R 1 01 1000 drrr rrrr Z INCRSZ R, d Increment R, Skip if 0 01 1001 drrr rrrr None Revision 1.2 1 or 2(skip) 1 or 2(skip) 1 or 2(skip) -7- 24 October 2000 MYSON TECHNOLOGY Mnemonic Operands DECR R, d Description Decrement R MTU8B54E/55E/56E/57E Cycles 1 1 or DECRSZ R, d Decrement R, Skip if 0 2(skip) Instruction Code Status Affected 01 0110 drrr rrrr Z 01 0111 drrr rrrr None SUBAR R, d Subtract Acc from R 1 01 1010 drrr rrrr C, DC, Z XORAR R, d Exclusive OR Acc with R 1 01 1011 drrr rrrr Z ANDAR R, d AND Acc with R 1 01 0100 drrr rrrr Z ADDAR R, d Add Acc and R 1 01 0101 drrr rrrr C, DC, Z IORAR R, d Inclusive OR Acc with R 1 01 1111 drrr rrrr Z Note: b : Bit position WDT : Watchdog Timer R : Register address i : Immediate data Acc : Accumulator T0MODE : T0MODE register PD : Power down flag TO : Time overflow bit IOST : I/O port status register Z : Zero flag C : Carry flag DC : Digital carry flag I : (i7i6i5i4i3i2i1i0) R : (r6r5r4r3r2r1r0) d ∈ [ 0, 1 ] :Destination If d is “0”, the result is stored in the Acc register. If d is “1”, the result is stored back in register R. 3.3 I/O PORTS EQUIVALENT CIRCUIT Acc Data D Q VDD IOST Latch CK IOST R Data Bus D I/O Pin QB QB VSS Data Latch WR Port CK Q RD Port Note : 1. The IOST registers are “write-only” and set upon RESET. 2. If the IOST latch is “0”, the corresponding I/O pin is in output mode; if the IOST latch is “1”, the corresponding I/O pin is in input mode. Revision 1.2 -8- 24 October 2000 MYSON TECHNOLOGY MTU8B54E/55E/56E/57E 3.4 RESET This device may be reset by one of the following ways: (1) Power-on Reset : At power-up, this device will be kept in a RESET condition for a period of 18ms after the voltage on MCLR/Vpp pin has reached a logic high level. (2) MCLR reset (normal operation). (3) WDT reset (normal operation). (4) MCLR wake-up (from sleep mode). (5) WDT wake-up (from sleep mode) : Executing the SLEEP instruction can force this device entering into sleep mode (power saving mode). While in sleep mode, the WDT is cleared but keeps running. This device can be awakened by WDT time-out or reset input on MCLR pin. The contents of registers after reset are listed below: Address Register Power-On Reset /MCLR or WDT Reset 00h INAR xxxx xxxx uuuu uuuu 01h Timer0 xxxx xxxx uuuu uuuu 02h PC 1111 1111 1111 1111 03h STATUS 0001 1xxx 000# #uuu 04h FSR 1xxx xxxx 1uuu uuuu 05h PORTA ---- xxxx ---- uuuu 06h PORTB xxxx xxxx uuuu uuuu 07h PORTC xxxx xxxx uuuu uuuu General Purpose Register xxxx xxxx uuuu uuuu N/A Acc xxxx xxxx uuuu uuuu N/A IOST 1111 1111 1111 1111 N/A T0MODE --11 1111 --11 1111 07h-1Fh Note: x = unknown, u = unchanged, - = unimplemented, read as “0”, # = refer to the following table Condition Status:bit 4 Status:bit 3 /MCLR Reset (not during SLEEP) u u /MCLR Reset during SLEEP 1 0 WDT Reset (not during SLEEP) 0 1 WDT Reset during SLEEP 0 0 Revision 1.2 -9- 24 October 2000 MYSON TECHNOLOGY MTU8B54E/55E/56E/57E 3.5 REAL TIME CLOCK (TIMER0) AND WATCHDOG TIMER T0CKI TE FOSC/4 WDT enable 1 0 M U X WDT 1 TS PSC 0 1 0 MUX MUX PSC Sync 2 cycles 8-bit prescaler 8 bits Timer0 PS2:PS0 8-to-1 MUX 8 bits Data Bus 0 1 PSC MUX WDT Time-Out 3.5.1 Timer0 Timer0 is an 8-bit timer/counter. The clock source of Timer0 can come from the internal clock or by an external clock source presented at the T0CKI pin. To select the internal clock source, bit 5 of the T0MODE register should be reset. In this mode, Timer0 will increase by 1 in every instruction cycle (without prescaler). To select the external clock source, bit 5 of the T0MODE register should be set. In this mode, Timer0 will increase by 1 on every falling or rising edge of T0CKI pin is controlled by bit 4 of T0MODE register. 3.5.2 Watchdog Timer(WDT) The Watchdog Timer is a free running on-chip RC oscillator. This RC oscillator is separated from the RC oscillator of the OSCI pin. That means the WDT will keep running even when the oscillator driver is turned off, such as in sleep mode. During normal operation or in sleep mode, a WDT time-out will cause the device reset and the TO bit (bit 4 of STATUS register) will be cleared. Without prescaler, the WDT time-out period is 18ms. This period can be increased by using the prescaler. The division ratio of prescaler is up to 1:128. Thus, the longest time-out period is approximately 2.3s. 3.5.3 Prescaler The 8-bit prescaler may be assigned to either the Timer0 or the WDT through the PSC bit (bit 3 of the T0MODE register). Setting this bit assigns the prescaler to the WDT. Resetting this bit assigns the prescaler to the Timer0. The PS2:PS0 bits determine the prescale ratio. When assigned to Timer0, the prescaler will be cleared by instructions which write to Timer0 Register. A CLRWDT instruction will clear the WDT and prescaler when assigned to WDT. The prescaler can not be assigned to both the Timer0 and WDT simultaneously. Revision 1.2 - 10 - 24 October 2000 MYSON TECHNOLOGY MTU8B54E/55E/56E/57E 3.6 OSCILLATOR CONFIGURATION This device supports four oscillator modes. Users can program two configuration bits to select the appropriate mode. These oscillator modes offered as: • RC: Low-cost crystal • XTAL: Standard crystal oscillator • HFXTAL: High frequency crystal oscillator • LFXTAL: Low frequency crystal oscillator 3.6.1 XTAL, HFXTAL or LFXTAL modes MTU8B54E/55E/56E/57E Internal Circuit MTU8B54E/55E/56E/57E SLEEP OSCI RF RS Open Clock from external system XTAL C2 C1 OSCO OSCI OSCO (a) Crystal Operation (or Ceramic Resonator) (b) External Clock Input Operation 3.6.2 RC Oscillator Mode R OSCI MTU8B54E/55E/56E/57E internal clock C 0÷4 OSCO 3.7 CONFIGURATION WORD Bit 3 Bit2 Bit1 Bit0 Code Protect WDT Enable Oscillator Type Oscillator Type 1 x x x 0 x x x x 1 x x x 0 x x x x 1 1 x x 1 0 x x 0 1 x x 0 0 Revision 1.2 - 11 - Function EPROM unprotected EPROM protected Watchdog Timer enable Watchdog Timer disable RC HFXTAL XTAL LFXTAL Remark Default Default Default 24 October 2000 MYSON TECHNOLOGY MTU8B54E/55E/56E/57E 4.0 ABSOLUTE MAXIMUM RATINGS -55oC to +125oC -65oC to +150oC 0V to +7.5V 0.6V to (Vdd + 0.6)V 0V to +12V Ambient Operating Temperature Store Temperature DC Supply Voltage(Vdd) Voltage with respect to Ground(Vss) Voltage on MCLR(Vpp) with respect to Ground(Vss) 5.0 OPERATING CONDITIONS DC Supply Voltage Operaing Temprature +2.3V to +6.5V -40oC to +85oC 6.0 ELECTRICAL CHARACTERISTICS (Under Operating Conditions) 6.1 ELECTRICAL CHARACTERISTICS of MTU8B54E/56E Parameter Sym Input High Voltage VIH Input Low Volatge VIL Output Voltage Sleep Current VOh Max. 4.2 Units Conditions I/O ports, Vdd=5V V MCLR, Vdd=5V V 1.1 V I/O ports, Vdd=5V 1.0 V MCLR, Vdd=5V V V I/O Ports, Vdd=4.5V, Ioh=-5.4mA, Iol=8.7mA in RC mode 3.8 0.6 IPD 3.0 uA WDT Enable, Vdd=3.0V IPD <1 uA WDT Disable, Vdd=3.0V 8.07 mA HFXTAL: 24MHz, WDT Disable Vdd=6.4V 5.16 mA Vdd=5.0V 3.98 mA Vdd=4.0V 2.05 mA Vdd=3.0v 2.8 mA LFXTAL: 32kHz, WDT Disable Vdd=6.4V 1.77 mA Vdd=5.0V 1.31 mA Vdd=4.0V 604 uA Vdd=3.0V 224 uA Vdd=2.4V 88 uA Vdd=2.1V ** 6.21 mA XTAL: 12MHz, WDT Disable Vdd=6.4V 3.91 mA Vdd=5.0V 2.71 mA Vdd=4.0V 1.39 mA Vdd=3.0V 685 uA Vdd=2.4V IDD IDD Revision 1.2 Typ. 2.2 VOL IDD Operating Current Min. - 12 - 24 October 2000 MYSON TECHNOLOGY Parameter Sym IDD Min. Typ. MTU8B54E/55E/56E/57E Typ. Units Conditions 5.01 mA XTAL: 4MHz, WDT Disable 3.03 mA Vdd=6.4V 2.05 mA Vdd=5.0V 916 uA Vdd=4.0V 391 uA Vdd=3.0V 195 uA Vdd=2.1V ** Vdd=5V, RC mode, WDT Disable, These values include current through Rext 6.32 mA R=900Ohm F=7.80MHz 3.11 mA R=4.7kOhm F=4.10MHz 2.46 mA R=10kOhm F=2.38MHz C=3P Operating Current 1.88 mA R=47kOhm F=617kHz 1.80 mA R=100kOhm F=311kHz 1.73 mA R=300kOhm F=103Hz 6.18 mA R=900Ohm F=6.76MHz 2.91 mA R=4.7kOhm F=2.98MHz 2.31 mA R=10kOhm F=1.67MHz C=20P IDD 1.84 mA R=47kOhm F=403kHz 1.77 mA R=100kOhm F=202kHz 1.72 mA R=300kOhm F=65.8kHz 5.72 mA R=900Ohm F=4.17MHz 2.60 mA R=4.7kOhm F=1.33MHz 2.13 mA R=10kOhm F=676kHz R=47kOhm F=154kHz C=101P 1.79 mA 1.75 mA R=100kOhm F=75.8kHz 1.71 mA R=300kOhm F=24.5kHz 5.32 mA R=900Ohm F=2.34MHz 2.45 mA R=4.7kOhm F=617kHz 2.06 mA R=10kOhm F=313kHz C=301P 1.78 mA R=47kOhm F=64.9kHz 1.74 mA R=100kOhm F=32.5kHz 1.71 mA R=300kOhm F=10.4kHz ** Operating at Vdd=2.1V is for reference only. Revision 1.2 - 13 - 24 October 2000 MYSON TECHNOLOGY MTU8B54E/55E/56E/57E 6.2 ELECTRICAL CHARACTERISTICS of MTU8B55E/57E Parameter Sym Input High Voltage VIH Input Low Volatge VIL Output Voltage Sleep Current VOh Min. Typ. Max. Units Conditions 2.2 V I/O ports, Vdd=5V 4.2 V MCLR, Vdd=5V 1.1 V I/O ports, Vdd=5V 1.0 V MCLR, Vdd=5V V V I/O Ports, Vdd=4.5V, Ioh=-5.4mA, Iol=8.7mA in RC mode 3.8 VOL 0.6 IPD 3.0 uA WDT Enable, Vdd=3.0V IPD <1 uA WDT Disable, Vdd=3.0V HFXTAL: 24MHz, WDT Disable IDD 8.87 mA Vdd=6.4V 5.84 mA Vdd=5.0V 4.09 mA Vdd=4.0V 1.88 mA Vdd=3.0v LFXTAL: 32kHz, WDT Disable IDD Operating Current mA Vdd=6.4V 1.96 mA Vdd=5.0V 1.42 mA Vdd=4.0V 675 uA Vdd=3.0V 279 uA Vdd=2.4V 116 uA Vdd=2.1V ** XTAL: 12MHz, WDT Disable IDD Revision 1.2 2.83 6.70 mA Vdd=6.4V 4.39 mA Vdd=5.0V 3.12 mA Vdd=4.0V 1.76 mA Vdd=3.0V 908 uA Vdd=2.4V mA XTAL: 4MHz, WDT Disable 3.11 mA Vdd=6.4V 2.22 mA Vdd=5.0V 1.17 mA Vdd=4.0V 578 uA Vdd=3.0V 377 uA Vdd=2.1V ** - 14 - 24 October 2000 MYSON TECHNOLOGY Parameter Sym Min. Typ. MTU8B54E/55E/56E/57E Typ. Units Conditions Vdd=5V, RC mode, WDT Disable, These values include current through Rext Operating Current IDD 6.58 mA R=900Ohm F=9.12MHz 3.18 mA R=4.7kOhm F=3.85MHz 2.55 mA R=10kOhm F=2.10MHz 2.05 mA R=47kOhm F=500kHz 1.98 mA R=100kOhm F=250kHz 1.93 mA R=300kOhm F=82.8Hz 6.40 mA R=900Ohm F=7.72MHz 3.03 mA R=4.7kOhm F=2.86MHz 2.46 mA R=10kOhm F=1.52MHz 2.04 mA R=47kOhm F=352kHz 1.97 mA R=100kOhm F=176kHz 1.93 mA R=300kOhm F=56.8kHz 5.90 mA R=900Ohm F=4.61MHz 2.79 mA R=4.7kOhm F=1.33MHz 2.34 mA R=10kOhm F=676kHz 2.02 mA R=47kOhm F=147kHz 1.97 mA R=100kOhm F=73.1kHz 1.93 mA R=300kOhm F=23.6kHz 5.48 mA R=900Ohm F=2.46MHz 2.60 mA R=4.7kOhm F=638kHz 2.28 mA R=10kOhm F=311kHz 2.02 mA R=47kOhm F=66.8kHz 1.98 mA R=100kOhm F=32.7kHz mA R=300kOhm F=10.5kHz 1.93 ** Operating at Vdd=2.1V is for reference only. Revision 1.2 - 15 - C=3P C=20P C=101P C=301P 24 October 2000 MYSON TECHNOLOGY MTU8B54E/55E/56E/57E 7.0 PACKAGE DIMENSION 7.1 18 Pin PDIP 300mil for MTU8B54EN and MTU8B56EN eB 15o (4x) E E1 D C 0.727 TOP E-PIN INDENT ∅0.079 L A A1 A2 BOTTOM E-PIN INDENT ∅0.118 e B B1 D1 Dimension In Millemeters Dimension In Inches Symbols Revision 1.2 Min Nom Max Min Nom Max A - - 4.57 - - 0.180 A1 0.13 - - 0.005 - - A2 - 3.30 3.56 - 0.130 0.140 B 0.36 0.46 0.56 0.014 0.018 0.022 B1 1.27 1.52 1.78 0.050 0.060 0.070 C 0.20 0.25 0.33 0.008 0.010 0.013 D 22.71 22.96 23.11 0.894 0.904 0.910 D1 0.43 0.56 0.69 0.017 0.022 0.027 E 7.62 - 8.26 0.300 - 0.325 E1 6.40 6.50 6.65 0.252 0.256 0.262 e - 2.54 - - 0.100 - L 3.18 - - 0.125 - - eB 8.38 - 9.65 0.330 - 0.380 - 16 - 24 October 2000 MYSON TECHNOLOGY MTU8B54E/55E/56E/57E view “A” C 0.020x45o 7o (4x) H E 7.2 18 Pin SOP for MTU8B54EP and MTU8B56EP D view “A” e B A θ A1 A2 7o (4x) L Dimension In Millimeters Dimension In Inches Symbols Revision 1.2 Min Nom Max Min Nom Max A 2.36 2.49 2.64 0.093 0.098 0.104 A1 0.10 - 0.30 0.04 - 0.012 A2 - 2.31 - - 0.091 - B 0.33 0.41 0.51 0.013 0.016 0.020 C 0.18 0.23 0.28 0.007 0.009 0.011 D 11.35 - 11.76 0.447 - 0.463 E 7.39 7.49 7.59 0.291 0.295 0.299 e - 1.27 - - 0.050 - H 10.01 10.31 10.64 0.394 0.406 0.419 L 0.38 0.81 1.27 0.015 0.032 0.050 θ 0o - 80 0o - 8o - 17 - 24 October 2000 MYSON TECHNOLOGY MTU8B54E/55E/56E/57E 7.3 28 Pin PDIP 300mil for MTU8B55EM and MTU8B57EM eB 15o (4x) E E1 D C 1.000” L A A1 A2 PIN 1 INDENT e B1 B2 B Dimension In Millimeters Dimension In Inches Symbols Revision 1.2 Min Nom Max Min Nom Max A - - 4.57 - - 0.180 A1 0.38 - - 0.015 - - A2 - 3.30 3.56 - 0.130 0.140 B 1.02 - 1.65 0.0040 - 0.065 B1 0.41 - 0.58 0.016 - 0.023 B2 0.71 - 1.12 0.028 - 0.044 C 0.20 0.25 0.33 0.008 0.010 0.013 D 35.13 35.18 35.43 1.383 1.385 1.395 E 7.87 8.31 8.38 0.310 0.327 0.330 E1 7.26 7.32 7.52 0.284 0.288 0.296 e - 2.54 - - 0.100 - L 3.18 - - 0.125 - - eB 8.64 - 9.65 0.340 - 0.380 - 18 - 24 October 2000 MYSON TECHNOLOGY MTU8B54E/55E/56E/57E 7.4 28 Pin PDIP 600mil for MTU8B55EN and MTU8B57EN eB L A A1 A2 E E1 15o (4x) D e B1 B Dimension In Millimeters Dimension In Inches Symbols Revision 1.2 Min Nom Max Min Nom Max A - - 5.59 - - 0.220 A1 0.38 - - 0.015 - - A2 3.81 3.94 4.06 0.150 0.155 0.160 B - 1.52 - - 0.06 - B1 - 0.46 - - 0.018 - D 36.96 37.08 37.34 1.455 1.460 1.470 E - 15.24 - - 0.600 - E1 13.72 13.84 13.97 0.540 0.545 0.550 e - 2.54 - - 0.100 - L 3.18 - - 0.125 - - eB 16.00 16.51 17.02 0.630 0.650 0.670 - 19 - 24 October 2000 MYSON TECHNOLOGY MTU8B54E/55E/56E/57E view “A” C E eB 0.020x45o 7o (4x) 7.5 28 Pin SOP for MTU8B55EP and MTU8B57EP D view “A” θ A1 e A A2 7o (4x) B D1 L Dimension In Millimeters Dimension In Inches Symbols Revision 1.2 Min Nom Max Min Nom Max A - 2.488 2.743 - 0.098 0.108 A1 0.152 - - 0.006 - - A2 2.21 2.336 2.464 0.087 0.091 0.097 B 0.305 0.406 0.508 0.012 0.016 0.020 C 0.204 0.254 0.304 0.008 0.010 0.012 D 17.78 17.91 18.42 0.700 0.705 0.725 E 7.366 7.493 7.62 0.290 0.295 0.300 e 1.219 1.270 1.321 0.048 0.050 0.052 eB 10.26 10.42 10.57 0.404 0.410 0.416 L 0.635 - - 0.025 - - θ 0o 4o 80 0o 4o 8o D1 0.356 0.508 - 0.014 0.020 - - 20 - 24 October 2000 MYSON TECHNOLOGY MTU8B54E/55E/56E/57E 8.0 PAD ASSIGNMENT Vss MCLR/Vpp TOCKI/SCL PA3/SDA PA2 PA1 PA0 OSCI OSCO 8.1 Pad Assignmemt for MTU8B54E and MTU8B56E 18 17 16 15 14 13 12 11 10 Pad of MTU8B54E/56E 8 9 Vdd 7 PB7 6 PB6 5 PB5 4 PB4 3 PB3 2 PB2 PB0 1 PB1 Chip size : 1710um x 1760um Pad size : 110um x 110um Pad No. Pad X Y Pad No. Pad X Y 1 PB0 145.45 153.05 10 OSCO 1598.95 1606.95 2 PB1 320.95 153.05 11 OSCI 1264.95 1606.95 3 PB2 496.45 153.05 12 PA0 1098.45 1606.95 4 PB3 671.95 153.05 13 PA1 922.95 1606.95 5 PB4 847.45 153.05 14 PA2 747.45 1606.95 6 PB5 1022.95 153.05 15 PA3/SDA 571.95 1606.95 7 PB6 1198.45 153.05 16 TOCKI/SCL 424.90 1606.95 8 PB7 1373.95 153.05 17 MCLR/Vpp 249.20 1606.95 9 Vdd 1557.45 153.05 18 Vss 124.20 1606.95 Revision 1.2 - 21 - 24 October 2000 MYSON TECHNOLOGY MTU8B54E/55E/56E/57E 14 13 PC5 12 PC4 11 PC3 10 PC2 PC1 MCLRB/Vpp OSCI OSCO PC7 Pad of MTU8B55E/57E Chip size : 2201um x 1822um Pad size : 110um x 110um PB1 1 2 3 4 8 5 6 7 PC0 26 PC6 9 T0CKI/SCL 15 PB7 25 PB0 16 PB6 24 PA3 17 PB5 23 PA2 18 PB4 22 PA1 19 PB3 21 PA0 20 PB2 Vss Vdd 8.2 Pad Assignment for MTU8B55E and MTU8B57E Pad No. Pad X Y Pad No. Pad X Y 1 PB1 217.01 93.20 14 PC6 2117.01 1627.80 2 PB2 476.09 93.20 15 PC7 1830.89 1738.75 3 PB3 720.67 93.20 16 OSCO 1595.29 1733.20 4 PB4 979.75 93.20 17 OSCI 1210.68 1733.20 5 PB5 1224.33 93.20 18 MCLR/Vpp 863.95 1738.79 6 PB6 1483.41 93.20 19 TOCKI/SCL 603.04 1738.75 7 PB7 1727.99 93.20 20 Vdd 344.41 1738.75 8 PC0 1987.07 93.20 21 Vss 101.98 1644.97 9 PC1 2117.01 361.40 22 PA0 93.21 1372.18 10 PC2 2117.01 620.48 23 PA1 93.21 1127.60 11 PC3 2117.01 865.06 24 PA2 93.21 868.52 12 PC4 2117.01 1124.14 25 PA3/SDA 93.21 623.94 13 PC5 2117.01 1386.72 26 PB0 93.21 364.86 Revision 1.2 - 22 - 24 October 2000 MYSON TECHNOLOGY MTU8B54E/55E/56E/57E 9.0 Order Information Type 300mil PDIP 600mil PDIP 300mil SOP Die Form 18pins MTU8B54EN - MTU8B54EP MTU8B54E 28pins MTU8B55EM MTU8B55EN MTU8B55EP MTU8B55E 18pins MTU8B56EN - MTU8B56EP MTU8B56E 28pins MTU8B57EM MTU8B57EN MTU8B57EP MTU8B57E Revision 1.2 - 23 - 24 October 2000