NCN6010 SIM Card Supply and Level Shifter The NCN6010 is a level shifter analog circuit designed to translate the voltages between a SIM Card and an external microcontroller. A built–in DC/DC converter makes the NCN6010 useable to drive any type of SIM card. The device fulfills the GSM 11.11 specification. The external MPU has an access to a dedicated input STOP pin, providing a way to switch off the power applied to the SIM card in case of failure or when the card is removed. http://onsemi.com MARKING DIAGRAM 14 Features • • • • • Supports 3.0 V or 5.0 V Operating SIM Card Built–in Pull Up Resistor for I/O Pin in Both Directions All Pins are Fully ESD Protected, According to GSM Specification Supports 10 MHz Clock 6.0 kV ESD Proof on SIM Card Pins NCN 6010 ALYW TSSOP–14 CASE 948G 14 1 1 A L Y W Typical Applications • Cellular Phone SIM Interface • Identification Module = Assembly Location = Wafer Lot = Year = Work Week PIN CONNECTIONS VDD 14 SIM_VCC VDD 1 SIM_VCC VDD 2 P2 6 P1 7 P0 C2 220 nF PWR_ON Ctb I/O CLOCK SIM_IO RESET GND SIM_RST 10 GND 9 SIM_CLK RESET 7 8 SIM_RST (Top View) 11 ORDERING INFORMATION 9 Device Package Shipping TSSOP–14 96 Units/Rail GND 8 NCN6010DTB 4 C8 C4 GND 11 SIM_IO CLOCK 6 12 10 SIM_CLK 12 Ctb 8 3 2 7 1 6 9 5 NCN6010DTBR2 TSSOP–14 2500 Tape & Reel DET 5 MOD_VCC 3 DET P3 MOD_VCC 13 Cta I/O 5 1 µF Cta STOP 2 PWR_ON 4 GND VCC 4 STOP RST 3 P4 13 Vpp MPU or GSM Controller VCC C3 14 CLK 1 I/O GND C4 4.7 µF 10 GND Figure 1. Typical Interface Application Semiconductor Components Industries, LLC, 2001 April, 2001 – Rev. 1 1 Publication Order Number: NCN6010/D NCN6010 STOP 2 ENABLE MOD_VCC 3 3 V/5 V CLOCK 6 RESET 7 13 Cta 12 Ctb 9 SIM_CLK 8 SIM_RST 11 SIM_IO 10 GROUND ENABLE 1 PWR_ON VDD SIM_VCC POWER UNIT & LOGIC MANAGEMENT 4 VCC PWR_ON 14 GND VDD VCC GND 20 k 20 k GND I/O I/O 5 DATA DATA I/O GND GND Figure 2. NCN6010 Block Diagram http://onsemi.com 2 NCN6010 PIN DESCRIPTIONS Pin Name Type Description 1 VDD POWER This pin is connected to the system controller power supply suitable to operate from a 3.6 V typical battery. A low ESR ceramic capacitor (4.7 F typical) shall be used to bypass the power supply voltage. 2 STOP INPUT A Low level on this pin resets the SIM interface, switching off the SIM_VCC, according to the ISO7816–3 Power Down procedure (See Table 1 and Figure 3). 3 MOD_VCC INPUT The signal present on this pin programs the SIM_VCC value (See Table 1): MOD_VCC = L → SIM_VCC = 5.0 V MOD_VCC = H → SIM_VCC = 3.0 V 4 PWR_ON INPUT The signal present on this pin controls the SIM_VCC state (See Table 1): PWR_ON = L → SIM_VCC = Open, no supply connected to the SIM card. PWR_ON = H → SIM_VCC = Active, the card is powered. 5 I/O INPUT This pin is connected to an external microcontroller or GSM management unit. A bi–directional level translator adapts the serial I/O signal between the smart card and the external controller. A built–in constant 20 kΩ (typical) resistor provides a high impedance state when not activated. 6 CLOCK INPUT The clock signal, coming from the external controller, must have a Duty Cycle within the Min/Max values defined by the specification (typically 50%). The built–in level shifter translates the input signal to the external SIM card CLK input. 7 RESET INPUT The RESET signal present at this pin is connected to the SIM card. The internal level shifter translates the level according to the voltages present at pin 1 and the SIM_VCC programmed value. 8 SIM_RST OUTPUT This pin is connected to the RESET pin of the card connector. A level translator adapts the external RESET signal to the SIM card. A built–in active pull down connects this pin to ground when the device is in a nonoperating mode. 9 SIM_CLK OUTPUT This pin is connected to the CLK pin of the card connector. The CLOCK signal comes from the external clock generator, the internal level shifter being used to adapt the voltage defined for the SIM_VCC. A built–in active pull down connects this pin to ground when the device is in a nonoperating mode. 10 GND GROUND This pin is the GROUND reference for the integrated circuit and associated signals. Cares must be observed to avoid voltage spikes when the device operates in a normal operation. 11 SIM_I/O 12 Cta POWER This pin is connected to the external capacitor used by the internal Charge Pump converter. Using Low ESR ceramic type is recommended (X5R or X7R). 13 Ctb POWER This pin is connected to the external capacitor used by the internal Charge Pump converter. Using Low ESR ceramic type is recommended (X5R or X7R). 14 SIM_VCC POWER This pin is connected to the SIM card power supply pin. An internal Charge Pump converter is programmable by the external MPU to supply either 3.0 V or 5.0 V output voltage. An external 1.0 µF minimum ceramic capacitor (ESR 100 m, X5R or X7R recommended) must be connected across SIM_VCC and GND. This pin handles the connection to the serial I/O of the card connector. A bi–directional level translator adapts the serial I/O signal between the card and the microcontroller. A 20 kΩ (typical) pull up resistor provides a High impedance state for the SIM card I/O link. During a normal operation, the SIM_VCC voltage can be set to 3.0 V followed by a 5.0 V value, or can start directly to any of these two values. When the voltage is adjusted downward (from 5.0 V to 3.0 V) cares must be observed as reverse peak current can flow from the external capacitors to the battery during a short amount of time (in the 1.0 µs range). When such a voltage adjustment is necessary, it is recommended to force SIM_VCC to zero, wait 350 µs minimum, then reprogram the chip to get SIM_VCC = 3.0 V. http://onsemi.com 3 NCN6010 MAXIMUM RATINGS (Note 1.) Symbol Value Unit VDD 7.0 V SIM_VCC 7.0 V Digital Input Voltage Digital Input Current STOP –0.3 V VDD 1.0 V mA Digital Input Voltage Digital Input Current RESET –0.3 V VDD 1.0 V mA Digital Input Voltage Digital Input Current CLOCK –0.3 V VDD 1.0 V mA Digital Input Voltage Digital Input Current I/O –0.3 V VDD 1.0 V mA SIM_RST –0.3 V SIM_VCC 25 V mA SIM_I/O –0.3 V SIM_VCC 25 V mA SIM_CLK –0.3 V SIM_VCC 50 V mA 6.0 2.0 kV kV PD RTHhja 275 145 mW °C/W Operating Ambient Temperature Range TA –25 to +85 °C Operating Junction Temperature Range TJ –25 to +125 °C TJmax +150 °C Tstg –65 to +150 °C Rating Power Supply External Card Power Supply and Level Shifter Digital Output Voltage Digital Output Current Digital Input/Output Voltage Digital Input/Output Current Digital Output Voltage Digital Output Current Human Body Model: R = 1500 Ω, C = 100 pF SIM card side, pins 8, 9, 11 & 14 All other pins ESD TSSOP–14 Package Power Dissipation @ TA = +85°C Thermal Resistance Junction to Air Maximum Junction Temperature Storage Temperature Range 1. Maximum electrical ratings are defined as those values beyond which damage to the device may occur at TA = +25°C. http://onsemi.com 4 NCN6010 POWER SUPPLY SECTION (–25C to +85C) Symbol Pin Min Typ Max Unit Power Supply VDD 1 2.7 – 3.6 V Standby Supply Current @ No Input Clock, All Input Logic to H, No Load Connected to the SIM Interface. I VDD 1 – 500 – nA Ground Current, @ VDD = 3.0 V, Operating Conditions: PWR_ON = 0 SIM_VCC = 5.0 V, ICC = 0 mA SIM_VCC = 5.0 V, ICC = 10 mA (Note 2.) SIM_VCC = 3.0 V, ICC = 0 mA SIM_VCC = 3.0 V, ICC = 6.0 mA (Note 2.) I VDD 1 – Rating External Card Power Supply at 5.0 V @ 2.7 V VDD 3.6 V, ICC = 10 mA External Card Power Supply at 3.0 V @ 2.7 V VDD 3.6 V, ICC = 10 mA µA 5.0 125 200 25 40 SIM_VCC 14 V 4.5 VDD – 50 mV Output SIM Card Supply Voltage Turn On Time Ct = 220 nF, Cout1 = 1.0 µF 20% VDD = 3.0 V, SIM_VCC = 5.0 V VDD = 3.0 V, SIM_VCC = 3.0 V VCCTON Output SIM Card Supply Voltage Turn Off Time Ct = 220 nF, Cout1 = 1.0 µF 20% (Note 3.) VDD = 2.7 V, SIM_VCC = 5.0 V, @ VLOW = 0.4 V VDD = 2.7 V, SIM_VCC = 3.0 V, @ VLOW = 0.4 V VCCTOFF 14 5.5 VDD VDD – 25 mV – ms 1.0 0.5 14 – µs – 300 300 Output Voltage Ripple (Note 4.) Ct = 220 nF, Cout1 = 1.0 µF, Cout2 = 100 nF VDD = 3.0 V, SIM_VCC = 5.0 V, ICC = 10 mA (Not Relevant at SIM_VCC = 3.0 V) VCCRIP 14 – – mV 200 Input Peak Current During DC/DC Startup @ VDD = 3.0 V, SIM_VCC = 5.0 V IDDpk 1 – 300 – mA Input Average Current During Normal Operation, @ VDD = 3.0 V, SIM_VCC = 5.0 V IDDavg 1 – 20 – mA Fosc – – 800 – kHz DC/DC Internal Oscillator 2. The IDD current represents the absolute difference between the current absorbed by the load and the one absorbed by the chip. 3. A 350 µs delay must be observed by the external MPU prior to reactivate the SIM_VCC output. 4. Using low ESR capacitors type (max 100 mΩ) is mandatory for Ct, Cout1 and Cout2 to reach the NCN6010 specifications. Ceramic type (X5R or X7R) are recommended. DIGITAL INPUT SECTION CLOCK, RESET, I/O, STOP, MOD_VCC, PWR_ON Rating High Level Input Voltage Low Level Input Voltage Input Rise Time Input Fall Time Input Capacitance Input @ 45% < Duty Cycle < 55% Clock Rise Time Clock Fall Time Input Clock Capacitance Input/Output Data Transfer Frequency I/O Rise Time I/O Fall Time Input I/O Capacitance Symbol Pin Min Typ Max Unit VIH VIL tr tf Cin 2, 3 4, 5 6, 7 0.7 * VDD – VDD 0.3 * VDD 50 50 10 V V ns ns pF CLOCK 6 – – 5.0 50 50 10 MHz ns ns pF I/O 5 – 15 160 0.8 0.8 10 kHz µs µs pF http://onsemi.com 5 NCN6010 SIM INTERFACE SECTION (Note 7.) Rating SIM_VCC = +5.0 V Output RESET VOH @ Isim_rst = +200 µA Output RESET VOL @ Isim_rst = –200 µA Output RESET Rise Time @ Cout = 50 pF Output RESET Fall Time @ Cout = 50 pF Symbol Pin SIM_RST Note 5. 8 SIM_VCC = +3.0 V Output RESET VOH @ Isim_rst = +200 µA Output RESET VOL @ Isim_rst = –200 µA Output RESET Rise Time @ Cout = 50 pF Output RESET Fall Time @ Cout = 50 pF SIM_VCC = +5.0 V Output Duty Cycle Output Frequency Output SIM_CLK Rise Time @ Cout = 50 pF Output SIM_CLK Fall Time @ Cout = 50 pF Output VOH @ Isim_clk = +20 µA Output VOL @ Isim_clk = –200 µA SIM_CLK Note 5. Note 6. Card I/O Pull Up Resistor Max Unit SIM_VCC – 0.7 0 SIM_VCC 0.6 400 400 V V ns ns 0.8 * SIM_VCC 0 SIM_VCC 0.2 * SIM_VCC 400 400 V V ns ns 60 5.0 18 18 SIM_VCC 0.5 % MHz ns ns V V 60 5.0 18 18 SIM_VCC 0.2 * SIM_VCC % MHz ns ns V V 15 160 0.8 0.8 SIM_VCC 0.4 kHz µs µs V V 15 160 0.8 0.8 SIM_VCC 0.4 kHz µs µs V V – 40 0.7 * SIM_VCC 0 40 0.7 * SIM_VCC 0 SIM_I/O 11 0.7 * SIM_VCC 0 SIM_VCC = +3.0 V SIM_I/O Data Transfer Frequency SIM_I/O Rise Time @ Cout = 50 pF SIM_I/O Fall Time @ Cout = 50 pF Output VOH @ ISIM_IO = +20 µA, VIH = VDD Output VOL @ ISIM_IO = –1.0 mA, VIL I/O = 0 V I/O Pull Up Resistor Typ – 9 SIM_VCC = +3.0 V Output Duty Cycle Output Frequency Output SIM_CLK Rise Time @ Cout = 50 pF Output SIM_CLK Fall Time @ Cout = 50 pF Output VOH @ Isim_clk = +20 µA Output VOL @ Isim_clk = –20 µA SIM_VCC = +5.0 V SIM_I/O Data Transfer Frequency SIM_I/O Rise Time @ Cout = 50 pF SIM_I/O Fall Time @ Cout = 50 pF Output VOH @ ISIM_IO = +20 µA, VIH = VDD Output VOL @ ISIM_IO = –1.0 mA, VIL I/O = 0 V Min 0.7 * SIM_VCC 0 I/O_RP 5 13 20 – kΩ SIM_I/O_RP 11 13 20 – kΩ 5. Internal NMOS device, biased to VDD, provides low impedance when SIM_VCC is disconnected to sustain GSM 11.11–200 µA input current test. 6. The SIM_CLK clock can operate up to 10 MHz, but the rise and fall time are not guaranteed to be fully within the ISO7816 specification over the temperature range. Typically, tr and tf are 12 ns @ CRD_CLK = 10 MHz. 7. Digital inputs undershoot –0.30 V, Digital inputs overshoot 0.30 V. http://onsemi.com 6 NCN6010 Card Supply Charge Pump Converter hand, although it is possible to change the SIM_VCC voltage from 5.0 V to 3.0 V, it is recommended to switch off the Charge Pump prior to reprogram the SIM_VCC voltage from the high 5.0 V to a low 3.0 V. The DC/DC converter operates under two modes as defined by the logic level present at MOD_VCC/pin 3: The NCN6010 device provides three pins to control the operation of the interface as depicted in Table 1. The built–in charge pump converter circuit provides either a 3.0 V or a 5.0 V output voltage as defined by the programming mode. The external capacitor connected across pins 12 and 13 is used to generate the step up voltage. Since the device operates at 800 kHz typically, one must use high quality, Low ESR type, ceramic capacitor (220 nF recommended). The second external capacitor, connected across pin 14 and GND, smooths the output voltage coming from the Charge Pump. A high quality, Low ESR capacitor is necessary to achieve the SIM_VCC ripple voltage (1.0 µF Ceramic type is recommended). The setting of the SIM_VCC voltage, using MOD_VCC = 0 or 1, can only be made when PWR_ON is Low. Consequently, a new supply voltage adjustment is performed by first deactivating the SIM card, followed by reactivating it with the new supply voltage. The SIM_VCC voltage can be reprogrammed straightforward when the output voltage increases from 3.0 V to 5.0 V. On the other MOD_VCC = 0 SIM_CC = 5.0 V, 10%. This is the default condition at start up. MOD_VCC = 1 The Charge Pump is not activated and the SIM_VCC voltage is equal to the VDD supply minus the internal maximum 50 mV drop. The NCN6010 provides a POWER DOWN sequence, according to the ISO7816–3 specification. Since a built–in active pull down MOS pull the SIM_VCC pin to ground when the smart card is deactivated, a 350 µs minimum delay must be observed prior to reactivate the power supply. This timing assumes a 1.0 µF external reservoir capacitor connected across SIM_VCC and Ground. Table 1. Programming Functions STOP MOD_VCC PWR_ON Operation Mode 0 X X The SIM card supply is disabled, the SIM_VCC pin is Open, SIM_RST = L, SIM_I/O = L, SIM_CLK = L 1 0 0 The NCN6010 is in the power down mode. The SIM card supply is disabled, SIM_VCC = Open, SIM_RST = L, SIM_CLK = L, SIM_IO = L. The SIM_VCC voltage is programmed to 5.0 V. 1 1 0 The NCN6010 is in the power down mode. The SIM card supply is disabled, SIM_VCC = Open, SIM_RST = L, SIM_CLK = L, SIM_IO = L. The SIM_VCC voltage is programmed to 3.0 V. 1 X 1 The NCN6010 is in normal operating mode. The SIM card supply is enabled, SIM_VCC voltage is the one previously programmed, all the SIM interface pins are active. Table 1: Programming Mode voltage. When the output voltage starts from zero, as depicted in Figure 3, a 50 s stabilization delay (typical) is necessary to make sure all the output signals are biased at the nominal 5.0 V voltage. To avoid a card transaction error, the user must take this delay into account and program the chip accordingly. When the card is removed, the STOP pin shall be asserted Low to disable the NCN6010. A mechanical switch, or equivalent, can be either sensed by the MPU, or directly connected to pin 2, to handle the procedure. Power Up Sequence When the charge pump is activated, MOD_VCC = Low, the SIM card related level shifter pins are biased to the 5.0 V http://onsemi.com 7 NCN6010 Figure 3. Power On Sequence Power Down Operation PWR_ON is Low, the SIM_IO, SIM_CLK and SIM_RST pins are forced to Low and the SIM_VCC pin is left floating. When the STOP signal is Low, the SIM_IO, SIM_CLK and SIM_RST are forced Low, the SIM_VCC being left floating, until the STOP pin is taken High again. When the card is extracted, the external MPU shall detect the operation and run the Power Down of the card by forcing PWR_ON input to Low. The NCN6010 fulfills the power sequence as defined by the ISO/CEI 7816–3 norm (see oscillogram given in Figure 5). The power down mode can be initiated by either the PWR_ON or by the STOP pin condition. In both cases, the communication I/O session is terminated immediately, according to the ISO7816–3 sequence as depicted in Figure 4. When the PWR_ON signal is set Low, the NCN6010 goes to the power down mode. According to the ISO7816–3 procedure defined to deactivate the SIM contacts, the input pins I/O, CLOCK and RESET must be Low before the PWR_ON is taken Low. When the SIM_RST SIM_CLK Force SIM_RST to Low Force SIM_CLK to Low, unless it is already in this state Force SIM_IO to Low Shut Off the SIM_VCC supply SIM_IO UNDEFINED SIM_VCC T T0 T1 Figure 4. ISO7816–3 Power Down Sequence http://onsemi.com 8 T2 T3 NCN6010 Figure 5. Power Down Sequence Oscillogram Level Shifters When the SIM card voltage is either higher or lower than the MPU VDD supply, the level shifters can be reprogrammed to cope with the expected output voltage. When the MPU and the SIM card operate under the same supply voltage, the DC/DC converter is not activated (SIM_VCC = VDD –50 mV) and the signals go directly through the level shifters. The bi–directional I/O line provides a way to automatically adapt the voltage difference between the µCU and the SIM card. In addition with the pull up resistor, an active pull up circuit (Figure 6 Q1 and Q2) provides a fast charge of the stray capacitance, yielding a rise time fully within the ISO/EMV specifications. VDD VCC Q1 Q2 20 k 20 k 200 ns 200 ns SIM_IO I/O GND Q3 IO/CONTROL LOGIC GND Figure 6. Basic I/O Line Interface crosses the Vgsth, the opposite one shot is activated, providing a low impedance to charge the capacitance, thus increasing the rise time as depicted in Figure 7. The same mechanism applies for the opposite side of the line to make sure the system is optimum. The typical waveform provided in Figure 7 shows how the accelerator operates. During the first 200 ns (typical), the slope of the rise time is solely a function of the pull up resistor associated with the stray capacitance. During this period, the PMOS devices are not activated since the input voltage is below their Vgs threshold. When the input slope http://onsemi.com 9 NCN6010 Figure 7. SIM_IO Rise and Fall Time Oscillogram Input Schmitt Triggers All the Logic Input pins have built–in Schmitt trigger circuits to prevent the NCN6010 against uncontrolled operation. The typical dynamic characteristics of the related pins are depicted in Figure 8. The output signal is guaranteed to go High when the input voltage is above 0.70*Vbat, and will go Low when the input voltage is below 0.30 * Vbat. this capacitor is series with the input voltage–output reservoir network. The voltage developed across the load is, theoretically, twice the battery voltage, but the system must takes into account the losses associated with the power switches and the internal ohmic drops. IS S3 S1 Output B Vbat C1 A S5 VCC ON S2 S4 OFF C2 VO LOAD Vbat 0.70 Vbat 0.30 Vbat Input Figure 9. Basic Charge Pump Converter When the output voltage is programmed to 3.0 V, the clocks are inactive and the load is directly connected to the battery by means of switch S5. The SIM_VCC voltage follows the input value, minus the drop coming from the internal resistance . The current is limited by the Ron of the power device S5 and t he output voltage will decrease as the load current increases above 20 mA (typical). Figure 10 illustrates the theoretical waveforms. Figure 8. Typical Schmitt Trigger Characteristic Charge Pump Converter The converter uses a switched capacitor technique to increase the SIM_VCC voltage up to 5.0 V from a 3.3 V typical battery. The concept, depicted in Figure 9, charges the transfer capacitor C1 up to the Vcc value, then connects http://onsemi.com 10 NCN6010 SIM_VCC = 5.0 V SIM_VCC = 3.0 V S1 S2 S3 S4 S5 MOD_VCC Figure 10. Basic Charge Pump Operating Timings design the chip. The third parameter is adjustable by the user and, beside the micro farad values, the type of capacitors plays a significant role. As a matter of fact, using a low cost electrolytic model will ruin the efficiency due to the high ESR of such a capacitor. It is highly recommended to use ceramic types, preferably from the X5R or X7R series, to achieve the efficiency and the SIM_VCC output voltage ripple. Table 2 summarizes the characteristics of the most common type of capacitors. When the NCN6010 is programmed in the 5.0 V output voltage, the clocks are activated, switch S5 is disconnected and the output voltage is the result of the C1 charge transfer into the output load. The current is limited by three mains parameters: – the Ron of the switching MOS (S1 through S4) – the operating frequency – the C1/C2 ratio and their ESR The first parameters are depending upon the internal structure and size of the NMOS/PMOS devices used to Table 2. Comparison of Capacitor Types Manufacturers Type/Serie Format Max Value Tolerance Typ. Z @ 500 kHz MURATA CERAMIC/GRM225 0805 10 F/6.3 V +80%/–20% 30 m VISHAY Tantalum/594C/593C 1206 10 F/16 V – 450 m VISHAY Electrolytic/94SV 1206 10 F/10 V –20%/+20% 400 m http://onsemi.com 11 NCN6010 represent the accurate internal structure of the NCN6010, it can be used for engineering purpose. The ABM devices S1, S2, S4 and S5 have been defined in the PSPICE model to represent the NMOS and PMOS used in the silicon. The ESR value of C2 and C3 can be adjusted, at PSPICE level, to cope with any type of external capacitors and are useful to double check the behavior of the system as a function of the external passives components. It is clear that, with nearly half an ohm of resistance is series with the pure capacitor, the tantalum or the electrolytic type will generate high voltage spikes and poor regulation in the high frequency operating charge pump built into the NCN6010. Moreover, with ESR in the 3.0 Ohm range, low cost capacitors are not suitable for this application. Figure 11 provides the schematic diagram of the simulated charge pump circuit. Although this schematic does not + IC = 0 R3 0.5 R + Battery Pack – V1 275 V C1 4.7 µF R1 0.1 R + S1 + S4 + + – – S VOFF = 0.0 V VON = 1.0 V C3 220 nF U2A 1 U1A 3 2 S5 + + – – S VOFF = 2.0 V VON = 0.0 V C2 1 µF 74HC14 74HC08 V2 U3A 2 LOAD V1 = 0 V2 = 3 TD = 10 ns + TR = 10 ns TF = 10 ns – PW = 600 ns PER = 1200 ns 2 E5 1 74HC14 R5 500 R OUT+ IN+ OUT– IN– EVALUE if (V (%IN+, %IN–) > 80 mV, 5, 0) + – V3 5.0 V Figure 11. Charge Pump Simulation Schematic Diagram http://onsemi.com 12 – – S VOFF = 2.0 V VON = 0.0 V Transfer Capacitor S2 + + 1 R4 0.05 R R2 0.1 R – – S VON = 1.0 V VOFF = 0.0 V NCN6010 The operating waveforms are given in Figure 12 to illustrate the high peak current flowing in the transfer capacitor. The real ripple voltage, coming from the engineering board, is given in Figure 13. 6.0 V SIM_VCC Output Voltage Load = 10 mA 4.0 V 2.0 V 0V V(C2:2) 2.0 A Charge Pump Transfer Capacitor Current 0A SEL>> –2.0 A 0 I(R4) 20 40 TIME (µs) Figure 12. Simulated Charge Pump Typical Waveforms Figure 13. SIM_VCC Output Voltage Ripple @ Iout = 10 mA http://onsemi.com 13 60 +3.3 V 470 R VDD ON +3.3 V J1 S2 +3.3 V POL. DET 25 24 23 22 21 20 19 18 17 16 15 14 11 10 9 8 7 POL. DET 1 U1 NCN6010 1 VDD MOD_VCC PWR_ON PWR_ON R3 5 I/O 6 1k D4 D3 MOD_VCC 4 I/O CLOCK 7 RST D2 D1 D0 4 Ctb SIM_IO GND RESET SIM_CLK SIM_RST +3.3 V +3.3 V R5 10 k R4 100 R GND R6 10 k 1 TP1 1 TP2 1 TP3 1 TP4 1 TP5 E RST I/O PWR MOD S3 C5 100 nF GND S4 MANUAL MOD_VCC MANUAL PWR_ON 3 13 2 12 1 C4 220 nF 5 7 11 GND Figure 14. Engineering Test Board Swa Swb C8 C4 CLK RST VCC GND I/O 10 VPP SMARTCARD 9 8 +3.3 V CLK IRQ 14 Cta STOP 3 8 GND J2 17 C2 1.0 µF SIM_VCC 2 Y7 D6 D5 E GND GND 6 5 4 3 2 C3 100 nF 18 B7 B6 B5 B4 B3 B2 B1 B0 C1 47 µF R2 10 k S1 GND 1 TP6 1 TP7 1 TP8 RST CLK S_IO 1 TP9 V CC 6 NCN6010 14 http://onsemi.com 13 12 GND ISO7816 26 NCN6010 Obviously, a GSM application will use much less area, but cares must be observed to locate the capacitors as close as possible to the integrated circuit associated pins. Capacitors C1, C2, C3, C4 and C5 are ceramic, X7R, 10 V, surface mount. The layout of the PCB is a key parameter to avoid the voltage spikes that could pollute the rest of the system. Figure 16 represents a typical printed circuit lay out, based on the schematic diagram given in Figure 14, highlighting the large ground plane used in this engineering tool. Figure 15. Engineering Test Board Silk Layer Figure 16. Engineering Test Board Top Layer http://onsemi.com 15 NCN6010 PACKAGE DIMENSIONS TSSOP–14 CASE 948G–01 ISSUE O NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. 14X K REF 0.10 (0.004) 0.15 (0.006) T U M T U V S S S N 2X 14 L/2 0.25 (0.010) 8 M B –U– L PIN 1 IDENT. F 7 1 0.15 (0.006) T U N S DETAIL E K A –V– ÉÉ ÇÇ ÇÇ ÉÉ K1 J J1 SECTION N–N –W– C 0.10 (0.004) –T– SEATING PLANE D G H DETAIL E DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.50 0.60 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0 8 INCHES MIN MAX 0.193 0.200 0.169 0.177 --0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.020 0.024 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0 8 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. 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