NCP370 Positive and Negative Overvoltage Protection with Internal Low RON N-MOSFETs and Reverse Charge Control Pin http://onsemi.com The NCP370 is an overvoltage, overcurrent and reverse control device. Two main modes are available by setting logic pins. First mode is Direct Mode from Wall−Adapter to the system. In this mode the system is both positive and negative over−voltage protected up to +28 V and down to −28 V. The wall adapter (or AC/DC charger) is disconnected from the system if the input voltage exceeds the overvoltage (OVLO) or undervoltage (UVLO) thresholds. At power up, the Vout turns on 30 ms after the Vin exceeds the undervoltage threshold. The second mode (see Tables 1 & 2), called the Reverse Mode, allows an external accessory to be powered by the system battery or boost converter. Here the external accessory would be connected to the device input (bottom connector of system) and the device battery would be at the device output. In this case overcurrent protection is activated to prevent accessory faults and battery discharge. Thanks to the NCP370 using an internal NMOS, the system cost and the PCB area of the application board are minimized. The NCP370 provides a negative going flag (FLAG) output which alerts the system that a fault has occurred. In addition, the device has ESD−protected input (15 kV Air) when bypassed with a 1 mF or larger capacitor. Features • • • • • • • • • • • • • • • Overvoltage Protection Up to 28 V Negative Voltage Protection Down to −28 V Reverse Charge Control: REV Direct Charge Control: DIR Overcurrent Protection Thermal Shutdown On−chip Low RDS(on) NMOS Transistors: Typical 130 mW Overvoltage Lockout (OVLO) Undervoltage Lockout (UVLO) Soft−Start Alert FLAG Output Compliance to IEC61000−4−2 (Level 4) 8 kV (Contact) 15 kV (Air) ESD Ratings: Machine Model = B Human Body Model = 2 12 Lead TLLGA 3x3 mm Package This is a Pb−Free Device © Semiconductor Components Industries, LLC, 2008 December, 2008 − Rev. 2 1 MARKING DIAGRAM NCAI 370 ALYWG G 1 12 PIN LLGA MU SUFFIX CASE 513AK A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package (Note: Microdot may be in either location) IN 1 12 NC IN 2 11 OUT GND 3 10 FLAG RES 4 RES RES NCP370 9 DIR 5 8 REV 6 7 Ilim (Top View) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 10 of this data sheet. Typical Applications • • • • • Cell Phones Camera Phones Digital Still Cameras Personal Digital Applications MP3 Players Publication Order Number: NCP370/D NCP370 10k Charger Wall Adapter 1mF 1 2 3 4 5 6 NCP370 12 IN NC 11 IN OUT 10 GND FLAG 9 RES DIR 8 RES REV 7 RES Ilim FLAG DIR REV System FLAG 4.7mF Rlimit LI+BATTERY DIR REV GND Figure 1. Typical Application Circuit FUNCTIONAL BLOCK DIAGRAM INPUT OUTPUT Gate Driver and Reverse OCP Logic REV Ilim VREF Charge Pump EN Block UVLO OVLO Control Logic and Timer FLAG Thermal Shutdown DIR Figure 2. Functional Block Diagram http://onsemi.com 2 GND NCP370 PIN FUNCTION DESCRIPTION Pin Name Type Description 1, 2 IN POWER Input voltage pins. These pins are connected to the power supply. A 1 mF low ESR ceramic capacitor, or larger, must be connected between these pins and GND. The two IN pins must be hardwired to common supply. 3 GND POWER Main Ground 4 RES INPUT Reserved pin. This pin must be connected to GND. 5 RES INPUT Reserved pin. This pin must be connected to GND. 6 RES INPUT Reserved pin. This pin must be connected to GND. 7 Ilim OUTPUT Current Limit Pin. This pin provides the reference, based on the internal band−gap voltage reference, to limit the over current, across internal N−MOSFETs, from battery to external accessory. A 1% tolerance, or better, resistor shall be used to get the highest accuracy of the overcurrent limit. 8 REV INPUT Reverse Charge Control Pin. In combination with DIR, the internal N−MOSFETs are turned on if Battery is applied on the OUT pin (See Tables 1 & 2). In reverse mode, the internal overcurrent protection is activated. When reverse mode is disabled, the NCP370 current consumption, into OUT pin, is drastically decreased to limit battery discharge. 9 DIR INPUT Direct Mode Pin. In combination with REV, the internal N−MOSFETs are turned on if a wall adapter AC−DC is applied on the IN pins (See Tables 1 & 2). The device enters in shutdown mode when this pin is tied to a high level and the REV pin is tied to high. In this case the output is disconnected from input. The state of this pin does not have an impact on the fault detect of the FLAG pin. 10 FLAG OUTPUT Fault Indication Pin. This pin allows an external system to detect fault condition. The pin goes low when input voltage exceeds OVLO threshold or drops below UVLO threshold, charge current from battery to accessory exceeds current limit or internal temperature exceeds thermal shutdown limit. Since the pin is open drain functionality, an external pull up resistor to VBat must be added (10 kW minimum value). 11 OUT OUTPUT Output Voltage Pin. This pin follows IN pins when “no input fault” is detected. The output is disconnected from the VIN power supply when the input voltage is under the UVLO threshold or above OVLO threshold or thermal shutdown limit is exceeded.In Reverse Mode, the device is supplied across OUT pin. 12 NC NC 13 PAD1 POWER Not Connected The PAD1 is used to dissipate the internal MOSFET thermal energy and must be soldered to an isolated PCB area. The area mustn’t be connected to any other potential than complete isolated one. See PCB recommendations on page 9. MAXIMUM RATINGS Rating Symbol Value Unit Vminin −30 V Vmin −0.3 V Maximum Voltage (IN to GND) Vmaxin 30 V Maximum Voltage (OUT to GND) Vmaxout 10 V Vmax 7 V RqJA 200 °C/W Minimum Voltage (IN to GND) Minimum Voltage (All others to GND) Maximum Voltage (All others to GND) Thermal Resistance, Junction−to−Air, (Note 1) Operating Ambient Temperature Range TA −40 to +85 °C TSTG −65 to +150 °C TJ 150 °C ESD Withstand Voltage (IEC 61000−4−2) Human Body Model (HBM), Model = 2, (Note 2) Machine Model (MM) Model = B, (Note 3) Vesd 15kV air, 8kV contact 2000V 200V kV V V Moisture Sensitivity MSL Level 1 Storage Temperature Range Junction Operating Temperature Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. The RqJA is highly dependent on the PCB heat sink area (connected to PAD1). See PCB recommendation paragraph. 2. Human Body Model, 100 pF discharged through a 1.5 kW resistor following specification JESD22/A114. 3. Machine Model, 200 pF discharged through all pins following specification JESD22/A115. http://onsemi.com 3 NCP370 ELECTRICAL CHARACTERISTICS (Vin = 5 V, Minimum/Maximum limits at −40°C < TA < +85°C unless otherwise noted. Typical values are at TA = +25°C) Symbols Conditions Min Vin Disable, Direct and Enhance Modes, Vout = 0 V −28 Vinmin Disable, Direct and Enhance Modes, Vout = 4.25V −24 Vout Reverse Mode 2.5 Undervoltage Lockout Threshold UVLO Vin falls below UVLO Threshold (Disable, Direct and Enhance Modes) 2.6 Undervoltage Lockout Hysteresis UVLOhyst Vin rises above UVLO Threshold + UVLOhyst Over voltage Lockout Threshold NCP370MUAITXG OVLO Overvoltage Lockout Hysteresis Over System Voltage Lockout Characteristics Input Voltage Range Input Voltage Output Voltage Range Overvoltage Lockout Hysteresis Vin to Vout Resistance Vout to Vin Resistance Input Standby Current Input Supply Quiescent Current Typ Max Unit 28 V V 5.5 V 2.7 2.8 V 45 60 75 mV Vin rises above OVLO threshold (Disable and Direct Modes) 6.3 6.6 6.9 V OVLOhyst Vin falls below to OVLO − OVLOhyst 60 80 100 mV OVLO00 Vin rises above OVLO00 Threshold Enhanced Mode @ 25°C 7.9 8.27 8.6 V OVLO00hyst Vin falls below to OVLO00 − OVLO00hyst @ 25°C 80 100 145 mV RDS(on) Vin = 5 V, Direct Mode, Load Connected to Vout Vin = 5 V, Direct Mode, Load Connected to Vout @ 25°C 130 220 mW 130 200 Vout = 5 V, Reverse Mode, Accessory Connected to Vin Vout = 5 V, Reverse Mode, Accessory Connected to Vin @ 25°C 130 220 130 200 No Load. Disable Mode, Vin connected 90 150 mA RDS(on) IddSTD mW IddIN No Load. Direct Mode 200 280 mA IddSTDOUT Rin = 10 kW, Vout = 5.5 V, Disable Mode 0.02 1.0 mA Reverse Mode current IddREV No Accessory, Vout = 4.2 V, Reverse Mode 200 315 mA Minimum DC Current ICHG Output Load, Vin = 5.5 V, Direct 1.3 IREV Accessory, Vout = 5.5 V, Reverse Modes 1.3 Overcurrent Threshold IOCP Vout = 4.2 V, Load on Vin, Reverse Mode, RILIM = 0 W, 1 A/1 ms 1.35 Overcurrent Response Iacc Direct Accessory Short, Reverse Mode, Vout = 4.2 V, Ilim = 1.6 A 7.0 Volflag 1.2 V < Vin < UVLO Sink 50 mA on FLAG Pin 30 Output Standby Current FLAG Output Low Voltage FLAG Leakage Current FLAGleak DIR Voltage High VihDIR DIR Voltage Low VilDIR DIR Leakage Current DIRleak REV Voltage High VihREV REV Voltage Low VilREV REV Leakage Current Thermal Shutdown Temperature Thermal Shutdown Hysteresis REVleak A 1.75 2.10 % 400 Vin > OVLO, Sink 1 mA on FLAG Pin 400 Ireverse > Ilim, Sink 1 mA on FLAG Pin 400 FLAG Level = 5.5 V 1.0 V 0.55 200 1.0 V nA 1.2 V 0.55 Vin or Vout connected Vin and Vout disconnected mV nA 1.2 Vin or Vout connected Vin and Vout disconnected A V 200 1.0 nA TSD 150 °C TSDHYST 30 °C http://onsemi.com 4 NCP370 Characteristics Symbols Conditions Min Typ Max Unit ton From Vin > UVLO to Vout w 0.3 V 20 30 40 ms tstart From Vout > 0.3 V to FLAG = 1.2 V 20 30 40 ms toff From Vin > OVLO to Vout v 0.3 V Vin Increasing from 5 V to 8 V at 3 V/ms 1.5 5.0 ms Alert Delay tstop From Vin > OVLO to FLAG v 0.4 V See Figure 3 and 9 Vin Increasing from 5 V to 8 V at 3 V/ms 1.5 ms Disable Time tdis REV = 1.2 V, From DIR = 0.4 V to 1.2 V to Vout v 0.3 V 2.5 ms tonREV Vout w 2.5 V, From REV = 1.2 to 0.55 to Vin w 0.3 V, Reverse Mode 0.6 1.2 1.8 ms tstartREV From Vin w 0.3 V FLAG = 1.2 V, Reverse Mode 0.6 1.2 1.8 ms Rearming Reverse Delay tRRD Vout > 2.5 V, Rin = 1 W, Reverse Mode 20 30 40 ms Over Current Regulation Time tREG Vout > 2.6, Vin > 0.3 V, Reverse Mode 0.5 1.2 1.8 ms OCP Delay Time tOCP From Ireverse > Ilim, 1 A/1 ms 5 ms tREVDIS From REV = 0.55 V to 1.2 V, to Vin < 0.3 V. Vout = 5 V 200 ms TIMINGS DIRECT MODE Start Up Delay FLAG Going Up Delay Turn Off Delay REVERSE MODE Reverse Start Up Delay Reverse FLAG Going Up Delay Reverse Disable Time NOTE: Electrical parameters are guaranteed by correlation across the full range of temperature. TYPICAL OPERATING CHARACTERISTICS Operation Overvoltage Lockout (OVLO) The NCP370 provides overvoltage protection for positive and negative voltages, up to 28 V or down to −28 V on IN pins. At powerup, with DIR pin = low, REV = high, the output rises 30 ms after the input rises above the UVLO. The NCP370 provides a FLAG output, which alerts the system that a fault has occurred. The FLAG signal rises 30 ms after the output signal rises. A Reverse Mode is available when an accessory is connected on IN pins and the internal battery is applied on the OUT pin, allowing the accessory to be powered. In this mode, no supply must be connected on IN pins and REV pin must be tied to low level. The NCP370 provides overcurrent protection for the battery from current faults in the accessory. To protect connected systems on Vout pin from overvoltage, the device has a built−in overvoltage lock out (OVLO) circuit. During overvoltage condition, the output is disabled as long as the input voltage exceeds OVLO. Additional OVLO thresholds can be manufactured (Please contact your ON Semiconductor representative for availability). FLAG output will be low since Vin is higher than OVLO. This circuit has a 80 mV hysteresis to provide noise immunity to transient conditions. Oversystem Voltage Lockout (OVLO00) A second overvoltage comparator is available for supplying the sytem (output) by the Wall Adaptor (input) by setting DIR = low and REV = low. The RDS(on) will be higher during this mode allowing to handle few 10 mA. This additional comparator allows to put higher input voltage (OVLO = 8.27 V typical) on the NCP370 during test production sequence (I.E: One Time Programming of the cell phone, PDA). This parameter is 25°C guaranteed only. Undervoltage Lockout (UVLO) To ensure proper turn−on operation from AC/DC (or Wall adapter charging) under any conditions, the device has a built−in undervoltage lock out (UVLO) circuit. During positive going slope on Vin, the output remains disconnected from input until Vin voltage is above UVLO. The FLAG output will be low as long as Vin has not reached UVLO threshold. This circuit has a 60 mV hysteresis to provide noise immunity to transient conditions. In Reverse Mode (REV pin v 0.55 V, DIR w 1.2 V), UVLO and OVLO comparators are inactivated. FLAG Output The NCP370 provides a FLAG output which alerts that a fault has occurred. As soon as a fault state is detected by the NCP370 (see Figure 3), the FLAG pin output goes low, alerting the micro−controller to take appropriate action. http://onsemi.com 5 NCP370 The FLAG pin goes low as soon the input voltage exceeds the OVLO threshold or falls below the UVLO threshold. When the Vin level recovers normal condition, FLAG goes high after a time delay, tstart (see Figure 3), following the Vout response. The FLAG pin is an open drain output and therefore a pull up resistor (typically 1 MW, minimum 10 kW) must be connected to Battery. The FLAG level will always reflect Vin status, even if the device is turned off (DIR = 0). Vin OVLO UVLO Vout FLAG DIR tdis REV > 1.2 V ton tstart toff tstop ton tstart Figure 3. FLAG Pin in AC/DC Charging Mode overvoltage condition, overcurrent condition or thermal shutdown condition. During over thermal condition (T°J>T°SD), output is disconnected from input, and FLAG pin goes low. In Reverse Mode, FLAG pin remains available, allowing the micro−controller to appropriately process the http://onsemi.com 6 NCP370 Vin tonrev Vout Battery Output FLAG DIR REV micro−controller micro−controller External Accessory ID = 1 Figure 4. FLAG status in Reverse Mode Table 1. FLAG TABLE DIR REV IN OUT FLAG Status Pass Element (Dual NMOS FET) 0 0 1.5 < Vin < UVLO or Vin > OVLOoo Hiz Low Open 0 0 UVLO < Vin < OVLOoo = Vin−DROPOUT High Close 0 1 1.5 < Vin < UVLO or Vin > OVLO Hiz Low Open 0 1 UVLO < Vin < OVLO = Vin−DROPOUT High Close 1 0 = Vout−DROPOUT Vout > 2.5 V High Close 1 1 1.5 < Vin < UVLO or Vin > OVLO Hiz Low Open 1 1 UVLO < Vin < OVLO Hiz High Open DIR Input Table 2. TABLE SELECTION OF CHARGE MODES To enable Direct Charge operation (Direct Mode), the DIR pin shall be forced to low and REV to high. A high level on the DIR pin disconnects OUT pin from IN pin. DIR does not over−ride an OVLO or UVLO fault (FLAG status is still available). DIR REV Mode 0 0 Enhance Mode 0 1 Direct Mode 1 0 Reverse Mode 1 1 Disable Mode http://onsemi.com 7 NCP370 Negative Voltage and Reverse Current. By adding external resistors in series from Ilim to GND, the OCP value is lowered. See below table: Typical Current clamp table: The device protects the downstream side from negative voltage occurring on the IN pin, down to −28 V. When a negative voltage occurs, the output is disconnected from the IN pins. Table 3. OVERCURRENT THRESHOLD SELECTION Reverse Mode In Reverse Mode, an external accessory plugged into the bottom connector can be powered by the internal battery of the system. To access to the reverse mode, DIR pin must be tied high (> 1.2) and REV must be tied high to low (< 0.55 V). In this case, the core of the NCP370 will be supplied by the battery, with a 2.5 V minimum voltage and 5.5 V maximum voltage. In this reverse state, both OCP and thermal modes are available. OCP RLIMIT (A) (kW) 1.6 0 1.0 14 0.5 70 During an overcurrent event, the N−MOSFETs turn off and FLAG output goes low, allowing the micro−controller to process the fault event and then disable reverse charge path. At power up (accessory is plugged on input pins), the current is limited up to Ilim for 1.2 ms (typical), to allow capacitor charge and limit inrush current. If the Ilim threshold is exceeded over 1.2 ms, the device enters OCP burst mode until the overcurrent event disappears. After 1 ms following the plug in of the accessory, the OCP mode is engaged. See Figure 5. Overcurrent Protection (OCP) This device integrates the reverse over current protection function, from battery to external accessory. That means the current across the internal NMOS is limited when the value, set by the external Rlimit resistor, exceeds IOCP. An internal resistor is placed in series with the Ilim pin allowing a maximum OCP value when Ilim pin is directly connected to GND. Vout Vin tonREV tstartREV FLAG tREG IREV Ilim REV tRRD ID Drive Current in Accessory DIR Figure 5. Overcurrent Protection Sequence http://onsemi.com 8 Accessory ID Detection NCP370 Thermal Shutdown protection PCB Recommendations In case of internal overheating, the integrated thermal shutdown protection turns off the internal MOSFETs in order to instantaneously decrease the device temperature. The thermal threshold has been set at 150°C FLAG then goes low to inform the MCU. As the thermal hysteresis is 30°C, the MOSFETs will turn on as soon the device temperature falls below 120°C. If the fault event is still present, the temperature increase engages the thermal shutdown again until the fault event disappears. Since the NCP370 integrates the 1. 3A N−MOSFETs, PCB rules must be respected to properly evacuate the heat out of the silicon. From an applications standpoint, PAD1 of the NCP370 package should be connected to an isolated PCB area to increase the heat transfer if necessary. In any case, PAD1 should be not connected to any other potential or GND other than the isolated extra copper surface. To assist in the design of the transfer plane connected to PAD1, Figure 6 shows the copper area required with respect to RqJA. MAXIMUM qTA (°C/W) 250 2.5 Power Curve with PCB cu thk 2 oz 200 150 2 Power Curve with PCB cu thk 1 oz 100 1 qJA Curve with PCB cu thk 2 oz 50 0 1.5 0 100 200 qJA Curve with PCB cu thk 1 oz 300 400 500 0.5 600 0 700 COPPER HEAT SPREAD AREA (mm2) Figure 6. Copper heat Spread Area ESD Tests The NCP370 conforms to the IEC61000−4−2, level 4 on the Input pin. A 1 mF (I.E Murata GRM188R61E105KA12D) must be placed close to the IN pins. If the IEC61000−4−2 is not a requirement, a 100 nF/25 V must be placed between IN and GND. The above configuration supports 15 kV (Air) and 8 kV (Contact) at the input per IEC61000−4−2 (level 4). Please refer to Figure 7 for the IEC61000−4−2 electrostatic discharge waveform. Figure 7. Ipeak = f(t)/IEC61000−4−2 http://onsemi.com 9 NCP370 RDS(on) and Dropout As example: Rload = 8 W, Vin= 5 V. RDS(on) = 155 mW. Iout = 800 mA. Vout = 4.905 V NMOS Losses = RDS(on) x Iout2 = 0.155 x 0.82 = 0.0992 W The NCP370 includes two internal low RDS(on) N−MOSFETs to protect the system, connected on OUT pin, from overvoltage, negative voltage and reverse current protection. During normal operation, the RDS(on) characteristics of the N−MOSFETs give rise to low losses on Vout pin. DEMO BOARD Figure 8. Evaluation Board Schematic ORDERING INFORMATION Device NCP370MUAITXG Marking Package Shipping† NCAI 370 LLGA12 (Pb−Free) 3000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 10 NCP370 PACKAGE DIMENSIONS LLGA12 3x3, 0.5P CASE 513AK−01 ISSUE O PIN ONE REFERENCE 2X 0.15 C 2X ÇÇÇ ÇÇÇ ÇÇÇ 0.15 C NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 MM FROM TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. A B D E DIM A A1 b D D2 E E2 e K L TOP VIEW 0.10 C A 12X 0.08 C MILLIMETERS MIN MAX 0.50 0.60 0.00 0.05 0.20 0.30 3.00 BSC 2.60 2.80 3.00 BSC 1.90 2.10 0.50 BSC 0.20 −−− 0.25 0.35 SOLDERING FOOTPRINT* A1 SIDE VIEW C SEATING PLANE 3.30 D2 1 6 e 12X 0.50 1 0.50 PITCH 0.43 2.75 12X K E2 11X 0.30 12X L 12 7 12X b BOTTOM VIEW 2.05 0.10 C A B 0.05 C DIMENSIONS: MILLIMETERS NOTE 3 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. The products described herein (NCP370), may be covered by one or more U.S. patents. There may be other patents pending. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 http://onsemi.com 11 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative NCP370/D