NCP5393 2/3/4-Phase Controller for CPU Applications The NCP5393 controls up to four VDD phases and one VDDNB phase to provide a buck regulator solution for current and next-generation AMD processors. The NCP5393 incorporates differential voltage sensing, differential phase current sensing, optional load-line voltage positioning, and programmable VDD and VDDNB offsets to provide accurately regulated power parallel- and serial-VID AMD processors. Dual-edge multiphase modulation provides the fastest initial response to dynamic load events. This reduces system cost by requiring less bulk and ceramic output capacitance to meet transient regulation specifications. High performance operational error amplifiers are provided to simplify compensation of the VDD and VDDNB regulators. Dynamic Reference Injection further simplifies loop compensation by eliminating the need to compromise between response to load transients and response to VID code changes. Features •Meets AMD's Parallel, Serial (SVI) and Hybrid VR Specifications •Up to Four VDD Phases •Single-Phase VDDNB Controller •Dual-Edge PWM for Fastest Initial Response to Transient Loading •High Performance Operational Error Amplifiers •Internal Soft Start and Slew Rate Limiting •Dynamic Reference Injection (Patent #US07057381) •DAC Range from 12.5 mV to 1.55 V •$0.5% DAC Accuracy fro 0.8 V to 1.55 V •VDD and VDD Offset Ranges 0 mV - 800 mV •True Differential Remote Voltage Sense Amplifiers •Phase-to-Phase IDD Current Balancing •Differential Current Sense Amplifiers for Each Phase of Each Output •“Lossless” Inductor Current Sensing for VDD and VDDNB Outputs •Supports Load Lines (Droop) for VDD and VDDNB Outputs •Oscillator Range of 100 kHz - 1 MHz •Tracking Over Voltage Protection •Output Inductor DCR-Based Over Current Protection for VDD and http://onsemi.com MARKING DIAGRAM 1 NCP5393 AWLYYWWG 1 48 QFN48, 7x7 CASE 485AJ A WL YY WW G = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package ORDERING INFORMATION Device NCP5393MNR2G Package Shipping† QFN48 (Pb-Free) 2500 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. VDDNB Outputs •Guaranteed Startup into Precharged Loads •Temperature Range: 0°C to 70°C •This is a Pb-Free Device* Applications •Desktop Processors •Server Processors •High-End Notebook PCs *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2008 February, 2008 - Rev. 0 1 Publication Order Number: NCP5393/D G1 G2 G3 G4 NB_G DRVON NB_DRVON PWRGOOD SVD/VID2 SVC/VID3 ENABLE PWROK NCP5393 48 1 VID1 VID0 NB_COMP NB_FB NB_DROOP NB_VS+ NB_VSNB_OFFSET NB_DIFFOUT ROSC VID5 VID4 CS1 CS1N CS2 CS2N CS3 CS3N CS4 CS4N ILIM VCCB NB_CS NB_CSN VCCA GND COMP FB DROOP VS+ VSOFFSET DIFFOUT VFIX 12VMON PSI_L Figure 1. Pinout http://onsemi.com 2 NCP5393 NB_VS+ + NB_VS- + - Diff Amp NB_DIFFOUT NB_G HI-Z PWM_NB MID OVP 1.3 V FAULT + - NB_FB ILIMIT_NB + - Error Amp NB_COMP ILIMIT_NB = ILIMIT_VDD/N (N = VDD phase count) NB_DROOP Gain = 1 Droop Amplifier NB_CS NB_CSN NB_SRL NB_DAC NB_VS+ NB_VS- VDD PSI_L NB_DRVON NB REGULATOR Fault Logic and Monitor Circuits 1.3 V + Gain =6 NB OFFSET SCALING X + NORMAL OPERATION BOOT_VID & VFIX MODES NB Oscillator NB_OFFSET NB_DAC OUT NB_SRL OUT + NB Slew Rate Lim‐ it fNB = 1.27 x fVDD PWRGOOD PWROK NB PVI/SVI HYBRID INTERFACE VDD Slew Rate Limit VSVS+ DIFFOUT VDD_DAC OUT + VDD_SRL OUT + Diff Amp NORMAL OPERATION BOOT_VID & VFIX MODES 1.3 V PSI_L X VDD OFFSET SCALING + Error Amp FB VDD VID0 VID1 VID2/SVD VID3/SVC VID4 VID5 OFFSET FLAG COMP GND DROOP Gain = 1 Droop Amplifier CS1 CS1N CS2 CS2N CS3 CS3N CS4 CS4N + Gain = 6 + Gain = 6 + Gain = 6 + Gain = 6 1.3 V VDD PSI_L + + PWM1 + G1 + PWM2 + PMW3 + PWM4 + + + VDD Oscillator ROSC + 5V UVLO 4.25V/4.05V 12VMON VDD_SRL VDD_DAC VS+ VS- + 12V UVLO 8.5V/7.5V HI-Z MID HI-Z MID G4 FAULT 4OFF VDD REGULATOR Fault Logic 3-Phase Detection and Monitor Circuits NCP5393 Figure 2. NCP5393 Block Diagram http://onsemi.com 3 MID + - ENABLE VCCA HI-Z G3 SHED ILIMIT_VDD MID G2 OVP ILIM HI-Z DRVON NCP5393 Figure 3. NCP5393 Configured for 3 + 1 Phases, with Optional Droop http://onsemi.com 4 NCP5393 NCP5393 PIN DESCRIPTIONS Pin No. Symbol 1 VCCA 5 V supply pin for the NCP5393. The VCC bypassing capacitance must be connected between this pin and GND (preferably returned to the package flag). Description 2 GND Small-signal power supply return. This pin should be tied directly to the package flag (exposed pad). 3 COMP Output of the voltage error amplifier for the VDD regulator. 4 FB Voltage error amplifier inverting input for the VDD regulator. 5 DROOP 6 VS+ Non-inverting input to the differential remote sense amplifier for the VDD regulator. 7 VS- Inverting input to the differential remote sense amplifier for the VDD regulator. 8 OFFSET Input for offset voltage to be added to the VDD DAC's output voltage. Ground this pin for zero VDD offset. 9 DIFFOUT Output of the differential remote sense amplifier for the VDD regulator. 10 VFIX 11 12VMON 12 PSI_L Power Saving Control. Low = single phase operation, High = normal operation. This pin is not used in SVI mode. 13 CS1 Non-inverting input to current sense amplifier #1 for the VDD regulator. See Table: “Pin Connections vs. Phase Count” 14 CS1N 15 CS2 16 CS2N 17 CS3 18 CS3N 19 CS4 20 CS4N 21 ILIM 22 VCCB 5 V supply pin. Tie this pin to VCCA (Pin 1). 23 NB_CS Non-inverting input to the current sense amplifier for the VDDNB regulator 24 NB_CSN 25 VID4 Parallel Voltage ID DAC Input 4. Not used in SVI mode. 26 VID5 Parallel Voltage ID DAC Input 5. Not used in SVI mode. 27 ROSC 28 NB_DIFFOUT Output of the differential remote sense amplifier for the VDDNB regulator. 29 NB_OFFSET Input for offset voltage to be added to the VDDNB DAC's output voltage. Ground this pin for zero VDDNB offset. 30 NB_VS- Inverting input to the differential remote sense amplifier for the VDDNB regulator. 31 NB_VS+ Non-inverting input to the differential remote sense amplifier for the VDDNB regulator. Voltage output signal proportional to total current drawn from the VDD regulator. Used when load line operation (“droop”) is desired. When pulled low, this pin causes the levels on the SVC (VID3) and SVD (VID2) pins to be decoded as a two-bit DAC code, which controls the VDD and VDDNB outputs. UVLO monitor input for the 12 V power rail. Inverting input to current sense amplifier #1 for the VDD regulator. See Table: “Pin Connections vs. Phase Count” Non-inverting input to current sense amplifier #2 for the VDD regulator. See Table: “Pin Connections vs. Phase Count” Inverting input to current sense amplifier #2 for the VDD regulator. See Table: “Pin Connections vs. Phase Count” Non-inverting input to current sense amplifier #3 for the VDD regulator. See Table: “Pin Connections vs. Phase Count” Inverting input to current sense amplifier #3 for the VDD regulator. See Table: “Pin Connections vs. Phase Count” Non-inverting input to current sense amplifier #4 for the VDD regulator. See Table: “Pin Connections vs. Phase Count” Inverting input to current sense amplifier #4 for the VDD regulator. See Table: “Pin Connections vs. Phase Count” Overcurrent shutdown threshold for VDD and VDDNB. A resistor divider from ROSC to GND is typic‐ ally used to develop an appropriate voltage on ILIM. Inverting input to the current sense amplifier for the VDDNB regulator A resistance from this pin to ground programs the VDD and VDDNB oscillator frequencies. This pin supplies a trimmed output voltage of 2 V. http://onsemi.com 5 NCP5393 NCP5393 PIN DESCRIPTIONS Pin No. Symbol 32 NB_DROOP Description Voltage output signal proportional to total current drawn from the VDDNB regulator. Used when load line operation (“droop”) is desired. 33 NB_FB Voltage error amplifier inverting input for the VDDNB regulator. 34 NB_COMP Output of the voltage error amplifier for the VDDNB regulator. 35 VID0 Parallel Voltage ID DAC Input 0. Not used in SVI mode. 36 VID1 Parallel Voltage ID DAC Input 1. Also used for PVI or SVI mode selection. 37 PWROK System power supplies status input. Used in SVI mode only. 38 ENABLE High = Run, Low = Standby/Reset. 39 VID3/SVC Parallel Voltage ID DAC Input 1. Also used in SVI mode. 40 VID2/SVD Parallel Voltage ID DAC Input 1. Also used in SVI mode. 41 PWRGOOD Open drain output. High indicates that the active output(s) are within specification. 42 NB_DRVON Bidirectional Gate Drive Enable to the gate driver for the VDDNB regulator. 43 DRVON 44 NB_G 45 G4 PWM output #4. See Table: “Pin Connections vs. Phase Count” 46 G3 PWM output #3. See Table: “Pin Connections vs. Phase Count” 47 G2 PWM output #2. See Table: “Pin Connections vs. Phase Count” 48 G1 PWM output #1. See Table: “Pin Connections vs. Phase Count” FLAG PGND Bidirectional Gate Drive Enable to gate drivers for the VDD regulator. PWM output to the VDDNB gate driver. High-current power supply return via metal pad (flag) underneath package. The package flag should be tied directly to Pin 2. PIN CONNECTIONS VS. PHASE COUNT Number of Phases G4 G3 G2 G1 CS4 & CS4N CS3 & CS3N CS2 & CS2N CS1 & CS1N 4 Phase 4 Out Phase 3 Out Phase 2 Out Phase 1 Out Phase 4 CS Input Phase 3 CS Input Phase 2 CS Input Phase 1 CS Input 3 Tie to GND Phase 3 Out Phase 2 Out Phase 1 Out Tie to GND Phase 3 CS Input Phase 2 CS Input Phase 1 CS Input 2 Tie to GND Phase 2 Out Tie to GND Phase 1 Out Tie to GND Phase 2 CS input Tie to GND Phase 1 CS Input http://onsemi.com 6 NCP5393 ABSOLUTE MAXIMUM RATINGS ELECTRICAL INFORMATION Pin Symbol VMAX VMIN ISOURCE ISINK 12VMON 13.2 V -0.3 V N/A 50 mA VCC 7.0 V -0.3 V N/A 10 mA COMP, NB_COMP 5.5 V -0.3 V 10 mA 10 mA DROOP, NB_DROOP 5.5 V -0.3 V 5 mA 5 mA DIFFOUT, NB_DIFFOUT 5.5 V -0.3 V 20 mA 20 mA DRVON, NB_DRVON 5.5 V -0.3 V 5 mA 10 mA PWRGOOD 5.5 V -0.3 V N/A 20 mA VS+, NB_VS+ 3V -0.3 V 1 mA 1 mA VS-, NB_VS- 0.3 V -0.3 V 1 mA 1 mA ROSC 5.5 V -0.3 V 1 mA N/A All Other Pins 5.5 V -0.3 V N/A N/A Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. NOTE: All signals are referenced to GND unless noted otherwise. THERMAL INFORMATION Rating Symbol Value Unit Thermal Characteristic, QFN Package (Note 1) RqJA 30.5 °C/W Operating Junction Temperature Range (Note 2) TJ 0 to 125 °C Operating Ambient Temperature Range TA 0 to 70 °C Maximum Storage Temperature Range TSTG -55 to +150 °C Moisture Sensitivity Level, QFN Package MSL 1 * The maximum package power dissipation must be observed. 1. JESD 51-5 (1S2P Direct-Attach Method) with 0 LFM. 2. JESD 51-7 (1S2P Direct-Attach Method) with 0 LFM. http://onsemi.com 7 NCP5393 ELECTRICAL CHARACTERISTICS (Unless otherwise stated: 0°CvTAv70°C; 4.75 VvVCCv5.25 V; All DAC Codes; CVCC = 0.1 mF) Parameter Test Conditions Min Typ Max Unit -200 - 200 nA -1.0 - 1.0 mV ERROR AMPLIFIERS (VDD & VDDNB) Input Bias Current Input Offset Voltage (Note 3) V+ = V- = 1.3V Open Loop DC Gain CL = 60 pF to GND, RL = 10 kW to GND - 80 - dB Open Loop Unity Gain Bandwidth CL = 60 pF to GND, RL = 10 kW to GND - 15 - MHz Open Loop Phase Margin CL = 60 pF to GND, RL = 10 kW to GND - 70 - Slew Rate DVIN = 100 mV, AV = -10 V/V, 1.5 V < VCOMP < 2.5 V, CL = 60 pF, DC Loading = $125 mA deg V/ms - 5 - 3.5 - - Maximum Output Voltage 10 mV of Overdrive, ISOURCE = 2.0 mA V Minimum Output Voltage 10 mV of Overdrive, ISINK = 2.0 mA - - 1.0 V Output Source Current (Note 3) 10 mV of Overdrive, VOUT = 3.5 V - 2 - mA Output Sink Current (Note 3) 10 mV of Overdrive, VOUT = 1.0 V - 2 - mA DIFFERENTIAL SUMMING AMPLIFIERS (VDD & VDDNB) VS- Input Bias Current VS- Voltage at 0 V 33 mA VS+ Input Resistance DRVON = Low 1.0 kW VS+ Input Bias Voltage DRVON = High 7 DRVON = Low 0.37 DRVON = High 0.05 V VS+ Input Voltage Range (Note 3) -0.3 - 3.0 V VS- Input Voltage Range (Note 3) -0.3 - 0.3 V -3dB Bandwidth (Note 3) CL = 80 pF to GND, RL = 10 kW to GND 15 MHz DC gain, VS+ to DIFFOUT VS+ to VS- = 0.5 V to 2.35 V 0.982 1.0 1.022 V/V DAC Accuracy (Measured at VS+) Closed Loop Measurement, Error Amplifier Inside the Loop. 1.0125 V v VDAC v 1.5500 V 0.8000 V v VDAC v 1.0000 V 12.5 mV v VDAC v 0.8000 V -0.5 -5 -8 - 0.5 5 8 % mV mV Slew Rate DVIN = 100 mV, DVOUT = 1.3 V-1.2 V Maximum Output Voltage ISOURCE = 2 mA Minimum Output Voltage ISINK = 2 mA Output source current (Note 3) VOUT = 3 V 2.0 mA Output sink current (Note 3) VOUT = 0.5 V 2.0 mA 10 V/ms 2.0 V 0.5 V DROOP AMPLIFIERS (VDD & VDDNB) Gain from Current Sense Input to Droop Amplifier Output 0 mV < (CSx - CSxN) < 60 mV Droop Amplifier DC Output Voltage CSx = CSxN = 1.3 V Slew Rate CL = 20 pF to GND, RL = 1 kW to GND Maximum Output Voltage ISOURCE = 4.0 mA Minimum Output Voltage 5.7 6.0 6.3 1.3 V/V V - 5.0 - V/ms 3.0 - - V ISINK = 1.0 mA - - 1.0 V Output Source Current (Note 3) VOUT = 3.0 V - 4.0 - mA Output Sink Current (Note 3) VOUT = 1.0 V 1.0 - mA 3. Guaranteed by design. Not production tested. http://onsemi.com 8 NCP5393 ELECTRICAL CHARACTERISTICS (Unless otherwise stated: 0°CvTAv70°C; 4.75 VvVCCv5.25 V; All DAC Codes; CVCC = 0.1 mF) Parameter Test Conditions Min Typ Max Unit -50 - 50 nA Common Mode Input Voltage Range -0.3 - 2.6 V Differential Mode Input Voltage Range (Note 3) -120 - 120 mV CURRENT SENSE AMPLIFIERS (VDD & VDDNB) Input Bias Current CSx = CSxN = 1.4 V Input Offset Voltage (Note 3) CSx = CSxN = 1.00 V -1.0 - 1.0 mV Gain from Current Sense Input to PWM Comparator 0 mV < (CSx - CSxN) < 60 mV 5.0 6.0 7.0 V/V - 1.3 - V 3.0 - - V INTERNAL OFFSET VOLTAGE Voltage at Error Amplifier Non-In‐ verting Inputs DRVON & NB_DRVON Output Voltage (High) Sourcing 500 mA Output Voltage (Low) Sinking 500 mA - - 0.7 V Delay Time Propagation Delays - 10 - ns Active Internal Pull-up Resistance Sourcing 500 mA - 2.0 - kW Active Internal Pull-down Resistance Sinking 500 mA - 150 - W Rise Time CL (PCB) = 20 pF, DVOUT = 10% to 90% - 130 - ns Fall Time CL (PCB) = 20 pF, DVOUT = 10% to 90% - 15 - ns 100 - 900 kHz VDD PWM OSCILLATOR Switching Frequency Range Switching Frequency Accuracy 2- or 4-phase ROSC = 49.9 kW ROSC = 24.9 kW ROSC = 10 kW 196 380 803 - 226 420 981 kHz Switching Frequency Accuracy 3-phase ROSC = 49.9 kW ROSC = 24.9 kW ROSC = 10 kW 196 380 803 - 226 420 981 kHz ROSC Output Voltage 10 mA ≤ IROSC ≤ 200 mA 1.94 2.0 2.06 V - 1.25 - x fVDD VDDNB PWM OSCILLATOR Switching Frequency PWM COMPARATORS (VDD & VDDNB) Minimum Pulse Width (Note 3) FSW = 800 kHz - 30 - ns Propagation Delay (Note 3) $20 mV of Overdrive - 10 - ns Magnitude of the PWM Ramp - 1.0 - V 0% Duty Cycle COMP Voltage at which the PWM Outputs Remain LOW - 0.2 - V 100% Duty Cycle COMP Voltage at which the PWM Outputs Remain HIGH - 1.2 - V PWM Phase Angle Error Between Adjacent Phases +15 ° -15 PWRGOOD OUTPUT PWRGOOD Output Voltage (Low) IPGD = 5 mA - - 0.4 V PWRGOOD Rise Time External Pullup of 1 kW to 5 V CTOTAL = 45 pF, DVOUT = 10% to 90% - 125 - ns PWRGOOD High-State Leakage VPWRGOOD = 5.25 V - - 1 mA 3. Guaranteed by design. Not production tested. http://onsemi.com 9 NCP5393 ELECTRICAL CHARACTERISTICS (Unless otherwise stated: 0°CvTAv70°C; 4.75 VvVCCv5.25 V; All DAC Codes; CVCC = 0.1 mF) Parameter Test Conditions Min Typ Max Unit PWRGOOD OUTPUT PWRGOOD Upper Threshold VOUT Increasing, DAC = 1.3 V (Wrt DAC) - 300 - mV PWRGOOD Lower Threshold VOUT Decreasing, DAC = 1.3 V - 350 - mV VCC V PWM OUTPUTS (VDD & VDDNB) Output Voltage (High) Sourcing 500 mA 3.0 - Output Voltage (Mid) RL = 4 kW to GND 1.3 1.5 1.7 V Output Voltage (Low) Sinking 500 mA - - 0.15 V Rise and Fall Times CL = 50 pF, 0.7 V to 3.0 V or 3.0 V to 0.7 V - 15 - ns Tri-State Output Leakage Gx = 2.5 V (x = 1-4 or NB) -1.5 - 1.5 mA Output Impedance - HIGH or LOW State Resistance to VCC or GND - 50 - W Gate Pin Source Current - 80 - mA Gate Pin Threshold Voltage - 250 - mV Phase Detect Timer - 20 - ms VDD REGULATOR 2/3/4 PHASE DETECTION SLEW RATE LIMITERS Soft Start Ramp Time DAC = 0 to DAC = BOOT_VID - 2 - ms Slew Rate Limit In Any Mode after Soft-Start Completes - 3.25 - mV/ms 0.9 - - V VID INPUTS (Note: In SVI Mode, VID[2] = Bidirectional “SVD' Line and VID[3] = “SVC” Clock Input) VID Input Voltage (High) VHIGH VID Input Voltage (Low) VLOW - - 0.6 V VID Hysteresis VHIGH - VLOW or VLOW - VHIGH - 100 - mV Input Pulldown Current VIN = 0.6 V - 1.9 V - 15 - mA SVD Output Voltage (Low) In SVI Mode, ISINK = 5 mA 0 - 0.25 V 2.0 - - V ENABLE INPUT ENABLE Input Voltage (High) VHIGH ENABLE Input Voltage (Low) VLOW - - 0.8 V Enable Hysteresis Low - High or High - Low - 200 - mV Enable Input Pull-Up Current Internal Pullup to VCC - 15 - mA VFIXEN INPUT (Active-Low Input) VFIXEN Input Voltage (High) VHIGH 0.9 - - V VFIXEN Input Voltage (Low) VLOW - - 0.6 V VFIXEN Hysteresis Low - High or High - Low VFIXEN Input Pull-Up Current Internal Pullup to VCC 100 - 3. Guaranteed by design. Not production tested. http://onsemi.com 10 15 mV - mA NCP5393 ELECTRICAL CHARACTERISTICS (Unless otherwise stated: 0°CvTAv70°C; 4.75 VvVCCv5.25 V; All DAC Codes; CVCC = 0.1 mF) Parameter Test Conditions Min Typ Max Unit PSI_L (Power Saving Control, Active Low) (This pin is used in PVI mode only) PSI_L Input Voltage (High) VHIGH 0.9 - - V PSI_L Input Voltage (Low) VLOW - - 0.6 V PSI_L Hysteresis VHIGH - VLOW or VLOW - VHIGH 100 mV CURRENT LIMIT Current Sense Amp to ILIM Gain 20 mV < (CSx - CSxN) < 60 mV (CS inputs tied) ILIM Pin Input Bias Current ILIM Pin Working Voltage Range (Note3) ILIM Offset Voltage Offset extrapolated to CSx-CSxN = 0 V, and referred to the ILIM pin Delay VDDNB Current Limit Coefficient 5.7 6.0 6.3 V/V - - 0.5 mA 0.2 - 2.0 V - 30 - mV - 600 - ns = N x VNBILIM /VILIM, where N = number of VDD phases, and VNBILIM is the equivalent voltage threshold for NB Current Limit resulting from VILIM. 1.0 V OFFSET INPUTS (VDD & VDDNB) Output Offset Voltage Above VDAC 0 - 800 mV VDAC + 250 mV OUTPUT OVERVOLTAGE PROTECTION (VDD & VDDNB) Over Voltage Threshold In normal operation, with no VID changes VCCA UNDERVOLTAGE PROTECTION VCCA UVLO Start Threshold 4.0 4.25 4.5 V VCCA UVLO Stop Threshold 3.8 4.05 4.3 V VCCA UVLO Hysteresis 200 mV INPUT SUPPLY CURRENT VCC Operating Current ENABLE held Low, No PWM operation - 25 35 mA 12VMON (High Threshold) 8 8.5 9 V 12VMON (Low Threshold) 7 7.5 8 V 12VMON 12VMON Hysteresis Low - High or High - Low 3. Guaranteed by design. Not production tested. http://onsemi.com 11 1.0 V NCP5393 TYPICAL CHARACTERISTICS 1.5 EN, ENABLE THRESHOLD VOLTAGE (V) 2.03 SS TIME (ms) 2.01 1.99 1.97 1.95 25 50 1.2 Enable Decreasing Voltage 1.1 75 0 25 50 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 1. SS Time vs. Temperature Figure 2. Enable Threshold Voltage vs. Temperature 26.1 231.1 25.8 230.8 DETECT THRESHOLD (mV) ICC CURRENT (mA) Enable Increasing Voltage 1.3 1.0 0 25.5 25.2 24.9 24.6 24.3 24.0 75 230.5 230.2 229.9 229.6 229.3 229.0 0 25 50 75 0 25 50 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 3. ICC Current vs. Temperature Figure 4. 2/3/4 Phase Detection Threshold vs. Temperature 4.5 75 2.009 2.008 VCCP Increasing Voltage ROSC VOLTAGE (V) VCCP UVLO THRESHOLD VOLTAGE (V) 1.4 4.0 VCCP Decreasing Voltage 3.5 2.007 2.006 2.005 2.004 3.0 2.003 0 25 50 75 0 25 50 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 5. VCCP Undervoltage Lockout Threshold Voltage vs. Temperature Figure 6. ROSC Voltage vs. Temperature http://onsemi.com 12 75 NCP5393 10 PWRGOOD THRESHOLD VOLTAGE (mV) VCC UVLO THRESHOLD VOLTAGE (V) TYPICAL CHARACTERISTICS 9.5 9.0 VCC Increasing Voltage 8.5 8.0 VCC Decreasing Voltage 7.5 7.0 0 25 50 75 370 PWRGOOD Upper Voltage 360 350 340 330 320 PWRGOOD Lower Voltage 310 0 25 50 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 7. 12VMON Undervoltage Lockout Threshold Voltage vs. Temperature Figure 8. PWRGOOD Voltage vs. Temperature 75 Functional Description General and the Vcore ground reference point to VSN. This configuration keeps ground potential differences between the local controller ground and the Vcore ground reference point from affecting regulation of Vcore between Vcore and Vcore ground reference points. The RSA also subtracts the DAC (minus VID offset) voltage, thereby producing an unamplified output error voltage at the DIFFOUT pin. This output also has a 1.3 V bias voltage as the floating ground to allow both positive and negative error voltages. NCP5393 is an universal CPU Power Supply Controller compatible with both Parallel (PVI) and Serial (SVI) protocols for AMD Processors. The device provides complete control logic and protections for a high-performance step-down DC-DC voltage regulator, optimized for advanced microprocessor power supply supporting both PVI and SVI communication. It embeds two independent controllers for CPU CORE and the integrated NB, each one with its set of protections. The Controller performs a single-phase control for the NB Section and a programmable 2- to-4 phase control for the CORE Section featuring Dual-Edge multiphase architecture. NCP5393 also supports V_FIX mode for board debug: in this particular configuration the SVI bus is used as a static bus configuring 4 operative voltages for both the sections and ignoring any serial-VID command. It can be used for the board debug before plugging-in the CPU. The NCP5393 incorporates differential voltage sensing, differential phase current sensing, optional load-line voltage positioning, and programmable VDD and VDDNB offsets to provide accurately regulated power parallel- and serial-VID AMD processors. Dual-edge multiphase modulation provides the fastest initial response to dynamic load events. NCP5393 is able to detect which kind of CPU is connected in order to configure itself to work as a Single-Plane PVI controller or Dual-Plane SVI controller. The NCP5393 manages On the Fly VID transitions and maintains the slew rates as defined when the transitions take place. NCP5393 is available in TQFN48 Package. Precision Programmable DAC A precision programmable DAC is provided and system trimmed. This DAC has 0.5% accuracy over the entire operating temperature range of the part. The DAC can be programmed to support both PVI and SVI VID code specifications. High Performance Voltage Error Amplifier The error amplifier is designed to provide high slew rate and bandwidth. Although not required when operating as the controller of a voltage regulator, a capacitor from COMP to VFB is required for stable unity gain test configurations. Gate Driver Outputs and 2/3/4 Phase Operation The part can be configured to run in 2-, 3-, or 4-phase mode. In 2-phase mode, phases 1 and 3 should be used to drive the external gate drivers, G2 and G4 must be grounded. In 3-phase mode, gate output G4 must be grounded. In 4-phase mode all 4 gate outputs are used as shown in the 4-phase Applications Schematic. The Current Sense inputs of unused channels should be connected to GND. Please refer to table “PIN CONNECTIONS vs. PHASE COUNTS” for details. Remote Output Sensing Amplifier (RSA) A true differential amplifier allows the NCP5393 to measure Vcore voltage feedback with respect to the Vcore ground reference point by connecting the Vcore reference point to VSP, http://onsemi.com 13 NCP5393 Differential Current Sense Amplifiers and Summing Amplifier oscillator generates up to 4 symmetrical triangle waveforms with amplitude between 1.3_V and 2.3_V. The triangle waves have a phase delay between them such that for 2-, 3and 4-phase operation the PWM outputs are separated by 180, 120, and 90 angular degrees, respectively. When the NB phase is enabled, in order to ensure that the VDDNB oscillator does not accidentally lock to the VDD oscillator, the VDDNB oscillator will free-run at a frequency which is nominally 1.25 ratio of fVDD. Four differential amplifiers are provided to sense the output current of each phase. The inputs of each current sense amplifier must be connected across the current sensing element of the phase controlled by the corresponding gate output (G1, G2, G3, or G4). If a phase is unused, the differential inputs to that phase's current sense amplifier must be shorted together and connected to the GND. The current signals sensed from inductor DCR are fed into a summing amplifier to have a summed-up output. The outputs of current sense amplifiers control three functions. First, the summing current signal of all phases will go through DROOP amplifier and join the voltage feedback loop for output voltage positioning. Second, the output signal from DROOP amplifier also goes to ILIM amplifier to monitor the output current limit. Finally, the individual phase current contributes to the current balance of all phases by offsetting their ramp signals of PWM comparators. CPU Support NCP5393 is able to detect the CPU it is going to supply and configure itself accordingly. At system Start-up, on the rising-edge of the EN signal, the device monitors the status of VID1 and switches in PVI mode (VID1 = 1) or SVI mode (VID1 = 0). When in PVI mode, NCP5393 uses the information available on the VID[0:5] bus to address the CORE Section output voltage. NB Section is kept in HiZ mode. When in SVI mode, NCP5393 discards the information available on VID0, VID4 and VID5 and uses VID2 and VID3 for SVC and SVD respectively. Oscillator and Triangle Wave Generator The controller embeds a programmable precision dual-Oscillator: one section is used for the CORE and it is a multiphase programmable oscillator managing equal phase-shift among all phases and the other section is used for the NB section. The oscillator's frequency is programmed by the resistance connected from the ROSC pin to ground. The user will usually form this resistance from two resistors in order to create a voltage divider that uses the ROSC output voltage as the reference for creating the current limit setpoint voltage. The oscillator frequency range is 100_kHz per phase to 1.0_MHz per phase. The PVI - Parallel Interface PVI is a 6-bit-wide parallel interface used to address the CORE Section reference. According to the selected code, the device sets the CORE Section reference and regulates its output voltage. NB Section is kept in HiZ; no activity is performed on this section. furthermore, PWROK information is ignored as well since the signal is propietary of the SVI protocol. Start-up sequences before soft start and after soft start are given in Figure 9. Voltage identifications for the 6Bit AMD mode is given in Table 1. Figure 9. Power Up Sequences Before and After Soft Start in PVI Mode http://onsemi.com 14 NCP5393 Table 1. SIX-BIT PARALLEL VID CODES in PVI Modes SVID[5:0] VOUT (V) SVID[5:0] VOUT (V) SVID[5:0] VOUT (V) SVID[5:0] VOUT (V) 00_0000 1.5500 01_0000 1.1500 10_0000 0.7625 11_0000 0.5625 00_0001 1.5250 01_0001 1.1250 10_0001 0.7500 11_0001 0.5500 00_0010 1.5000 01_0010 1.1000 10_0010 0.7375 11_0010 0.5375 00_0011 1.4750 01_0011 1.0750 10_0011 0.7250 11_0011 0.5250 00_0100 1.4500 01_0100 1.0500 10_0100 0.7125 11_0100 0.5125 00_0101 1.4250 01_0101 1.0250 10_0101 0.7000 11_0101 0.5000 00_0110 1.4000 01_0110 1.0000 10_0110 0.6875 11_0110 0.4875 10_0111 1.3750 01_0111 0.9750 10_0111 0.6750 11_0111 0.4750 00_1000 1.3500 01_1000 0.9500 10_1000 0.6625 11_1000 0.4625 00_1001 1.3250 01_1001 0.9250 10_1001 0.6500 11_1001 0.4500 00_1010 1.3000 01_1010 0.9000 10_1010 0.6325 11_1010 0.4375 00_1011 1.2750 01_1011 0.8750 10_1011 0.6250 11_1011 0.4250 00_1100 1.2500 01_1100 0.8500 10_1100 0.6125 11_1100 0.4125 00_1101 1.2250 10_1101 0.8250 10_1101 0.6000 11_1101 0.4000 00_1110 1.2000 01_1110 0.8000 10_1110 0.5875 11_1110 0.3875 00_1111 1.1750 01_1111 0.7750 10_1111 0.5750 11_1111 0.3750 SVI - Serial Interface SVI is a two wire, Clock and Data, bus that connects a single master (AMD processor) to one NCP5393. The master initiates and terminates SVI transactions and drives the clock, SVC, and the data SVD, during a transaction. The slave receives the SVI transactions and acts accordingly. SVI wire protocol is based on fast-mode I2C. The SVI communications are given in Figure 10. SVI interface also considers EN and PWROK signals for start-up. The device returns a PWRGOOD signal if the output voltages are in regulation. The VID codes for SVI are given in Table 2. The start-up sequences before and after soft start are given in Figure 11. Figure 10. SVI Communication - Send Byte http://onsemi.com 15 NCP5393 Table 2. SEVEN-BIT SERIAL VID CODES for SVI Mode SVID[6:0] VOUT (V) SVID[6:0] VOUT (V) SVID[6:0] VOUT (V) SVID[6:0] VOUT (V) 000_0000 1.5500 010_0000 1.1500 100_0000 0.7500 110_0000 0.3500 000_0001 1.5375 010_0001 1.1375 100_0001 0.7375 110_0001 0.3375 000_0010 1.5250 010_0010 1.1250 100_0010 0.7250 110_0010 0.3250 000_0011 1.5125 010_0011 1.1125 100_0011 0.7125 110_0011 0.3125 000_0100 1.5000 010_0100 1.1000 100_0100 0.7000 110_0100 0.3000 000_0101 1.4875 010_0101 1.0875 100_0101 0.6875 110_0101 0.2875 000_0110 1.4750 010_0110 1.0750 100_0110 0.6750 110_0110 0.2750 000_0111 1.4625 010_0111 1.0625 100_0111 0.6625 110_0111 0.2625 000_1000 1.4500 010_1000 1.0500 100_1000 0.6500 110_1000 0.2500 000_1001 1.4375 010_1001 1.0375 100_1001 0.6325 110_1001 0.2375 000_1010 1.4250 010_1010 1.0250 100_1010 0.6250 110_1010 0.2250 000_1011 1.4125 010_1011 1.0125 100_1011 0.6125 110_1011 0.2125 000_1100 1.4000 010_1100 1.0000 100_1100 0.6000 110_1100 0.2000 000_1101 1.3875 010_1101 0.9875 100_1101 0.5875 110_1101 0.1875 000_1110 1.3750 010_1110 0.9750 100_1110 0.5750 110_1110 0.1750 000_1111 1.3625 010_1111 0.9625 100_1111 0.5625 110_1111 0.1625 001_0000 1.3500 011_0000 0.9500 101_0000 0.5500 111_0000 0.1500 001_0001 1.3375 011_0001 0.9375 101_0001 0.5375 111_0001 0.1375 001_0010 1.3250 011_0010 0.9250 101_0010 0.5250 111_0010 0.1250 001_0011 1.3125 011_0011 0.9125 101_0011 0.5125 111_0011 0.1125 001_0100 1.3000 011_0100 0.9000 101_0100 0.5000 111_0100 0.1000 001_0101 1.2875 011_0101 0.8875 101_0101 0.4875 111_0101 0.0875 001_0110 1.2750 011_0110 0.8750 101_0110 0.4750 111_0110 0.0750 001_0111 1.2625 011_0111 0.8625 101_0111 0.4625 111_0111 0.0625 001_1000 1.2500 011_1000 0.8500 101_1000 0.4500 111_1000 0.0500 001_1001 1.2375 011_1001 0.8375 101_1001 0.4375 111_1001 0.0375 001_1010 1.2250 011_1010 0.8250 101_1010 0.4250 111_1010 0.0250 001_1011 1.2125 011_1011 0.8125 101_1011 0.4125 111_1011 0.0125 001_1100 1.2000 011_1100 0.8000 101_1100 0.4000 111_1100 OFF 001_1101 1.1875 011_1101 0.7875 110_1101 0.3875 111_1101 OFF 001_1110 1.1750 011_1110 0.7750 101_1110 0.3750 111_1110 OFF 001_1111 1.1625 011_1111 0.7625 101_1111 0.3625 111_1111 OFF http://onsemi.com 16 NCP5393 Figure 11. Power Up Sequences Before and After Soft Start in SVI Mode Hardware Jumper Override - V_FIX • This capture is INDEPENDENT of any other signal. VFIX is an active low pin and when it is pulled low, the controller enters V_FIX mode.The voltage regulator can be powered when an external SVI bus master is not present. When in VFIX mode, all of the voltage regulator's output voltages will be governed by the information shown in Table3, regardless of the state of PWROK. VFIX mode is for debug and bring-up only. If VFIX mode is necessary for processor bring-up, VFIXEN, SVC, and SVD should be connected with jumpers to either ground or VDDIO through suitable pull-up resistors. SVC and SVD are considered as static VID and the output voltage will change according to their status. • Table 3. SVI VFIX VID CODES (TWO-BIT PARALLEL) • SVC SVD VOUT (V) 0 0 1.4 0 1 1.2 1 0 1.0 1 1 0.8 • SVI/PVI is determined by sampling VID[1] during rising edge of ENABLE (SVI: VID[1]=0, PVI: VID[1]=1). Once SVI/PVI is determined, the VID controller is enabled and increments to the Boot VID at the Soft Start rate. VFIXEN mode is entered once VFIXEN is asserted. If VFIXEN is asserted prior to the VID controller reaching the Boot VID, the VID controller will move to the VFIXEN VID. Once the first VID value is reached (either BOOT VID or VFIXEN VID), the VID will now increment at the Normal rate. Once the VID controller is enabled, the VID controller can receive VFIXEN VIDs, independent of PWROK which is ignored in VFIXEN mode. If VFIXEN is de-asserted, the device PORs. This occurs independent of ENABLE PWROK De-assertion Anytime PWROK de-asserts while EN is asserted, the controller uses the previously stored BOOT VID and regulates all planes to that level performing an on-the-Fly transition to that level. PWRGOOD remains asserted in this process. Start-up sequences are presented below: Boot VID is captured from SVC and SVD pins on rising edge of ENABLE. http://onsemi.com 17 NCP5393 Protection Features: voltage, the PWRGOOD goes low, the DRVON signal remains high, the PWM outputs are set low. The outputs will remain disabled until the VCC voltage is removed and reapplied. Every time the OV is triggered it will increment the OV counter. If the counter reaches a count of 16 then the OV condition will latch into a permanent OV state. It will require POR or disable/enable to restart. Prior to latching if the OV condition goes away then normal operation will resume. An OV decrement counter is also incorporated. It consists of a free-running clock which runs at 8x the PWM frequency. So essentially every 4096 PWM cycles the OV counter will decrement. For example, for a max PWM frequency of 1 MHz, the counter decrements roughly every 4ms and for a PWM frequency of 400 kHz, it would be about every 10 ms. During normal operation, if the output voltage falls more than 350_mV below the DAC setting, the PWRGOOD pin will be set low until the output voltage rises. Undervoltage Lockout An undervoltage lockout (UVLO) senses the VCC and VCCP input. During powerup, the input voltage to the controller is monitored, and the PWM outputs and the soft-start circuit are disabled until the input voltage exceeds the threshold voltage of the UVLO comparator. The UVLO comparator incorporates hysteresis to avoid chattering, since VCC is likely to decrease as soon as the converter initiates soft-start. Overcurrent Shutdown A programmable overcurrent function is incorporated within the IC. A comparator and latch make up this function. The inverting input of the comparator is connected to the ILIM pin. The voltage at this pin sets the maximum output current the converter can produce. The ROSC pin provides a convenient and accurate reference voltage from which a resistor divider can create the overcurrent setpoint voltage. Although not actually disabled, tying the ILIM pin directly to the ROSC pin sets the limit above useful levels effectively disabling overcurrent shutdown. The comparator noninverting input is the summed current information from the VDRP minus offset voltage. The overcurrent latch is set when the current information exceeds the voltage at the ILIM pin. The outputs are pulled low, and the soft-start is pulled low. The outputs will remain disabled until the VCC voltage is removed and re-applied, or the ENABLE input is brought low and then high. Soft-Start The NCP5393 simply ramps Vcore to boot voltage at a fixed rate of 2 ms (0.8mV/uS), and then reads the VID pins to determine the DAC setting. Then ramps Vcore to the final DAC setting at the Dynamic VID slew rate of up to 3.25mV/mS. In SVI mode, SoftStart Time is intended as the time required by the device to set the output voltages to the Pre-PWROK Metal VID. In PVI mode, VID[0:5] or V_FIX VID in V_FIX mode are the set output voltages. Typical soft start sequence timing in SVI mode is given in Figure 12. Output Overvoltage and Undervoltage Protection and Power Good Monitor An output voltage monitor is incorporated. During normal operation, if the output voltage is 250 mV over the DAC Figure 12. Soft-Start Sequence to Vcore = 1.3 V http://onsemi.com 18 NCP5393 Programming the Current Limit and the Oscillator Frequency The demo board is set for an operating frequency of approximately 330 kHz. The ROSC pin provides a 2.0 V reference voltage which is divided down with a resistor divider and fed into the current limit pin ILIM. Calculate the total series resistance to set the frequency and then calculate the individual RLIM1 and RLIM2 values for the divider. The series resistors RLIM1 and RLIM2 sink current from the ILIM pin to ground. This current is internally mirrored into a capacitor to create an oscillator. The period is proportional to the resistance and frequency is inversely proportional to the total resistance. The total resistance may be estimated by Equation 2. This equation is valid for the individual phase frequency in both three and four phase mode. RTOTAL ^ 24686 Fsw-1.1549 30.5·kW ^ 24686 330-1.1549 (eq. 1) Figure 13. ROSC vs. Frequency The current limit function is based on the total sensed current of all phases multiplied by a gain of 6. DCR sensed inductor current is function of the winding temperature. The best approach is to set the maximum current limit based on the expected average maximum temperature of the inductor windings. DCRTmax + DCR25C· (eq. 2) (1 ) 0.00393(T max -25)) Calculate the current limit voltage: ǒ VILIMIT ^ 6· IMIN_OCP·DCRTmax ) ǒ DCRTmax·Vout · Vin-Vout * (N-1)· Vout L 2·Vin·Fsw L ǓǓ (eq. 3) Solve for the individual resistors: V ·RTOTAL RLIM2 + ILIMIT 2·V RLIM1 + RTOTAL-RLIM2 (eq. 4) (eq. 5) Final Equation for the Current Limit Threshold ILIMIT(Tinductor) ^ 2·V·RLIM2 Ǔ ǒRLIM1)RLIM2 6·(DCR25C·(1 ) 0.00393(TInductor-25))) The inductors on the demo board have a DCR at 25°C of 0.75 mW. Selecting the closest available values of 16.9 kW for RLIM1 and 13.7 kW for RLIM2 yield a nominal operating frequency of 330 kHz and an approximate current * ǒ Vout · Vin-Vout * (N-1)· Vout 2·Vin·Fsw L L Ǔ (eq. 6) limit of 152 A at 100°C. The total sensed current can be observed as a scaled voltage at the VDRP pin added to a positive, no-load offset of approximately 1.3 V. http://onsemi.com 19 NCP5393 OUTPUT OFFSET VOLTAGES External offset voltages from 0 mv to 800 mV `above the DAC' can be added for the VDD and VDD_NB independently. Offset is set by a resistor divider from VCC to GND. Output offsets are ratiometric to VCC. As VCC changes, the on-chip scaling factors change by the same amount: Offset = 0.8 V x VOFFSET/VCC For example: For 0 V offset: pin voltage = GND; For 800 mV offset: pin voltage = VCC Minimum Voffset_IN (as Vin/Vcc) Typical Voffset_IN (as Vin/Vcc) Maximum Voffset_IN (as Vin/Vcc) Resulting Output Offset Units 0 0 0.046875 0 mV 0.046875 0.06250 0.078125 25 mV 0.078125 0.09375 0.109375 50 mV 0.109375 0.12500 0.140625 75 mV 0.140625 0.15625 0.171875 100 mV 0.171875 0.18750 0.203125 125 mV 0.203125 0.21875 0.234375 150 mV 0.234375 0.25000 0.265625 175 mV 0.265625 0.28125 0.296875 200 mV 0.296875 0.31250 0.328125 225 mV 0.328125 0.34375 0.359375 250 mV 0.359375 0.37500 0.390625 275 mV 0.390625 0.40625 0.421875 300 mV 0.421875 0.43750 0.453125 325 mV 0.453125 0.46875 0.484375 350 mV 0.484375 0.50000 0.515625 375 mV 0.515625 0.53125 0.546875 400 mV 0.546875 0.56250 0.578125 425 mV 0.578125 0.59375 0.609375 450 mV 0.609375 0.62500 0.640625 475 mV 0.640625 0.65625 0.671875 500 mV 0.671875 0.68750 0.703125 525 mV 0.703125 0.71875 0.734375 550 mV 0.734375 0.75000 0.765625 575 mV 0.765625 0.78125 0.796875 600 mV 0.796875 0.81250 0.828125 625 mV 0.828125 0.84375 0.859375 650 mV 0.859375 0.87500 0.890625 675 mV 0.890625 0.90625 0.921875 700 mV 0.921875 0.93750 0.953125 725 mV 0.953125 0.96875 0.984375 750 mV 0.984375 1.00000 Vcc+0.3V 800 mV The input to the OFFSET pin for the VDD output is encoded by an internal ADC. The input to the NB_OFFSET pin for the VDDNB output is encoded by the same ADC. The reference for this ADC is VCC. The ADC's output is ratiometric to VCC. Voffset IN represents the voltage applied to the OFFSET or NB_OFFSET pin. It is intended that these voltages be derived by a resistive divider from Vcc. The recommended total driving impedance is <10 kilohms. http://onsemi.com 20 NCP5393 PACKAGE DIMENSIONS QFN48 7x7, 0.5P CASE 485AJ-01 ISSUE O ÈÈÈ ÈÈÈ ÈÈÈ PIN 1 LOCATION D NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO THE PLATED TERMINAL AND IS MEASURED ABETWEEN 0.15 AND 0.30 MM FROM TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. A B E 2X DIM A A1 A3 b D D2 E E2 e K L L 0.15 C DETAIL A OPTIONAL CONSTRUCTION 2X SCALE 2X 0.15 C TOP VIEW (A3) 0.05 C MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.20 0.30 7.00 BSC 5.00 5.20 7.00 BSC 5.00 5.20 0.50 BSC 0.20 --0.30 0.50 A 0.08 C SOLDERING FOOTPRINT* A1 NOTE 4 2X C SIDE VIEW SEATING PLANE 5.20 D2 DETAIL A 1 K 13 25 12 2X 7.30 48X 0.63 E2 48X 1 48 48X L 0.30 36 e e/2 BOTTOM VIEW 0.50 PITCH DIMENSIONS: MILLIMETERS 37 48X b 0.10 C A B 0.05 C *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. NOTE 3 The products described herein (NCP5393), may be covered by one or more of the following U.S. patents, #US07057381. There may be other patents pending. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. 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