SLUS578A − OCTOBER 2003 − REVISED JUNE 2004 FEATURES D Two-, Three-, or Four-Phase Operation D 5-V to 15-V Operating Range D Programmable Switching Frequency Up to D D D D D D D D D D DESCRIPTION 1-MHz/Phase Current Mode Control With Forced Current Sharing(1) 1% Internal 0.7-V Reference Resistive Divider Set Output Voltage True Remote Sensing Differential Amplifier Resistive or DCR Current Sensing Current Sense Fault Protection Programmable Load Line Compatible with UCC37222 Predictive Gate Drive Technology Drivers 24-Pin Space-Saving TSSOP Package TPS40090: Binary Output TPS40091: Tri−State Output APPLICATIONS D Internet Servers D Network Equipment D Telecommunications Equipment D DC Power Distributed Systems 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 Each phase can be operated at a switching frequency up to 1-MHz, resulting in an effective ripple frequency of up to 4-MHz at the input and the output in a four-phase application. A two phase design operates 180 degrees out-of- phase, a three-phase design operates 120 degrees out of phase, and a four-phase design operates 90 degrees out of phase as shown in Figure 1. The number of phases is programmed by con− necting the de-activated phase PWM output to the output of the internal 5-V LDO. In two-phase operation the even phase outputs should be de-activated. The TPS4009x uses fixed frequency, peak current mode control with forced phase current balancing. When compared to voltage mode control, current mode results in a simplified feedback network and reduced input line sensitivity. Phase current is sensed by using either current sense resistors installed in series with output inductors or, for improved efficiency, by using the DCR (direct current resistance) of the filter inductors. The latter method involves generation of a current proportional signal with an R-C circuit (shown in Figure 10. PW PACKAGE (TOP VIEW) CS1 CS2 CS3 CS4 CSCN ILIM DROOP REF COMP FB DIFFO VOUT The TPS4009x family are two-, three-, or four-phase programmable synchronous buck controllers, optimized for low-voltage, highcurrent applications powered by a 5-V to 15-V distributed supply. A multi-phase converter offers several advantages over a single power stage including lower current ripple on the input and output capacitors, faster transient response to load steps, improved power handling capabilities, and higher system efficiency. EN/SYNC VIN BP5 PWM1 PWM2 PWM3 PWM4 GND RT SS PGOOD GNDS (1) Patent pending Predictive Gate Drive is a trademark of Texas Instruments Incorporated. !" # $%&" !# '%()$!" *!"&+ *%$"# $ " #'&$$!"# '& ",& "&# &-!# #"%&"# #"!*!* .!!"/+ *%$" '$&##0 *&# " &$&##!)/ $)%*& "&#"0 !)) '!!&"&#+ The R-C values are selected by matching the time constants of the R-C circuit and the inductor; R-C = L/DCR. With either current sense method, the current signal is amplified and superimposed on the amplified voltage error signal to provide current mode PWM control. Copyright 1999 − 2003, Texas Instruments Incorporated www.ti.com 1 SLUS578A − OCTOBER 2003 − REVISED JUNE 2004 DESCRIPTION (continued) An output voltage droop can be programmed to improve the transient window and reduce size of the output filter. Other features include a single voltage operation, a true differential sense amplifier, a programmable current limit, soft-start and a power good indicator. SIMPLIFIED TWO-PHASE APPLICATION DIAGRAM TPS40090PW CBP5 2 CS2 4 CS4 14 PGOOD 22 BP5 6 ILIM 17 GND CS3 RCS3 3 CCS3 CSCN 5 CCS1 RCS1 CSS 15 CS1 1 VIN 23 VIN (4.5 V to 15 V) CIN SS RILIM2 L1 RRT 16 RT 7 DROOP RDROOP RILIM1 21 BP5 8 REF CREF RFB3 PWM1 TI Synchronous Buck Driver 24 EN/SYNC 9 COMP 10 FB CFB1 PWM2 20 PWM4 18 L2 RFB2 RFB1 PWM3 11 DIFFO 19 TI Synchronous Buck Driver VOUT (0.7 V to 3.5 V) COUT 13 GNDS 12 VOUT UDG−03104 2 www.ti.com SLUS578A − OCTOBER 2003 − REVISED JUNE 2004 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOSFET gates. ORDERING INFORMATION TA −40°C to 85°C PACKAGE Plastic TSSOP(PW)(1) OUTPUT PART NUMBER Binary TPS40090PW Tri−state TPS40091PW (1) The PW package is also available taped and reeled. Add an R suffix to the device type (i.e., TPS40090PWR). ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(2) TPS40090 TPS40091 EN/SYNC, VIN, Input voltage range, VIN Output voltage range, VOUT UNIT 16.5 CS1, CS2, CS3, CS4, CSCN, DROOP, FB, GNDS, ILIM, VOUT −0.3 to 6.0 REF, COMP, DIFFO, PGOOD, SS, RT, PWM1, PWM2, PWM3, PWM4, BP5 −0.3 to 6.0 Operating junction temperature range, TJ −40 to 125 Storage temperature, Tstg −55 to 150 V °C C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260 (2) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS MIN Input voltage, VIN 4.5 Operating free-air temperature, TA −40 www.ti.com NOM MAX 15 85 UNIT V °C 3 SLUS578A − OCTOBER 2003 − REVISED JUNE 2004 ELECTRICAL CHARACTERISTICS TA = −40°C to 85°C, VIN = 12 V, RRT = 64.9 kΩ, TJ = TA (unless otherwise noted) TEST CONDITIONS PARAMETER MIN TYP MAX UNIT INPUT SUPPLY VIN VIN Operating voltage range, VIN UVLO, UVLO(1) VIN IIN 4.5 15 Rising VIN 4.25 4.45 Falling VIN 4.1 4.35 Shutdown current, VIN IIN Quiescent current switching OSCILLATOR/SYNCHRONIZATION Four channels, 400 kHz each, no load RRT = 64.9 kΩ 370 V 2 10 µA 4.0 6.0 mA Phase frequency accuracy Four channels, Phase frequency set range(1) Four channels 100 415 1200 Synchronization frequency range(1) Synchronization input threshold(1) Four channels 800 9600 Four channels VBP5/2 4-phase operation 87.5% 2- and 3-phase operation 83.3% 455 kHz V PWM Maximum duty cycle per channel Minimum duty cycle per channel(1) Minimum controllable on-time(1) 0 50 100 ns 0.700 0.707 V 25 150 nA ERROR AMPLIFIER Feedback input voltage Feedback input bias current VOH VOL GBW High-level output voltage low-level output voltage Gain bandwidth(1) 0.693 VFB = 0.7 V ICOMP = −1 mA 2.5 ICOMP = 1 mA 0.5 Open loop gain(1) AVOL SOFT START ISS VSS 2.9 0.8 V 5 MHz 90 dB Soft-start source current 3.5 5.0 6.0 µA Soft-start clamp voltage 0.95 1.00 1.05 V Enable threshold voltage 0.8 2.0 ENABLE Enable voltage capability(1) 2.5 VIN(max) V PWM OUTPUT PWM pull-up resistance PWM pull-down resistance PWM output leakage(1)(2) IOH = 5 mA IOL = 10 mA Ω 27 45 27 45 Ω 1 µA 5.2 V 200 mV 30 mA Three-state 5V REGULATOR VBP5 Output voltage External ILOAD = 2 mA Pass device voltage drop VIN = 4.5 V, no external load on BP5 Short circuit current (1) (2) 4 4.8 10 Ensured by design. Not production tested. TPS40091 only. www.ti.com 5.0 SLUS578A − OCTOBER 2003 − REVISED JUNE 2004 ELECTRICAL CHARACTERISTICS TA = −40°C to 85°C, VIN = 12 V, RRT = 64.9 kΩ, TJ = TA (unless otherwise noted) TEST CONDITIONS PARAMETER MIN TYP MAX UNIT CURRENT SENSE AMPLIFIER Gain transfer −100 mV ≤ VCS ≤ 100 mV, Gain variance between phases VCS = 100 mV VCS = 0 V Input offset variance at zero current Input common mode(1) VCSRTN = 1.5 V 4.9 5.4 −4% −3.5 0 0 Bandwidth(1) 5.9 V/V 4% 3.5 4 18 mV V MHz DIFFERENTIAL AMPLIFIER Gain Gain tolerance CMRR Common mode rejection ratio(1) Bandwidth(1) 1 VOUT 4.0 V vs. 0.7 V, 0.7 V ≤ VOUT ≤ 4.0 V VGNDS = 0 V −0.5% V/V 0.5% 60 dB 5 MHz RAMP Ramp amplitude(1) 0.4 0.5 0.6 V POWER GOOD VOL ILEAK PGOOD high threshold wrt VREF 10% 14% PGOOD low threshold wrt VREF −14% −10% Low-level output voltage IPGOOD = 4 mA VPGOOD = 5.0 V PGOOD output leakage 0.35 0.60 V 50 80 µA OUTPUT OVERVOLTAGE/UNDERVOLTAGE FAULT VOV VUV Overvoltage threshold voltage Undervoltage threshold voltage VFBK relative to VREF VFBK relative to VREF 15% 19% −18% −14% LOAD LINE PROGRAMMING IDROOP Pull-down current on DROOP (1) Ensured by design. Not production tested. 4-phase, VCS = 100 mV www.ti.com 40 µA 5 SLUS578A − OCTOBER 2003 − REVISED JUNE 2004 TERMINAL FUNCTIONS TERMINAL NAME NO. I/O DESCRIPTION BP5 22 O Output of an internal 5V regulator. A 4.7-µF capacitor should be connected from this pin to ground. For 5V applications this pin should be connected to VDD. COMP 9 O Output of the error amplifier. The voltage at this pin determines the duty cycle for the PWM. CS1 1 I CS2 2 I CS3 3 I CS4 4 I CSCN 5 I Common point of current sense resistors or filter inductors DIFFO 11 O Output of the differential amplifier. The voltage at this pin represents the true output voltage without drops that result from high current in the PCB traces DROOP 7 I Used to program droop function. A resistor between this pin and the REF pin sets the desired droop value. EN/SYNC 24 I A logic high signal on this input enables the controller operation. A pulsing signal to this pin synchronizes the main oscillator to the rising edge of an external clock source. These pulses must be of higher frequency than the free running frequency of the main oscillator set by the resistor from the RT pin. FB 10 I Inverting input of the error amplifier. In closed loop operation, the voltage at this pin is the internal reference level of 700 mV. This pin is also used for the PGOOD and OVP comparators. GND 17 − Ground connection to the device. GNDS 13 I Inverting input of the differential amplifier. This pin should be connected to ground at the point of load. ILIM 6 I Used to set the cycle-by-cycle current limit threshold. If ILIM threshold is reached, the PWM cycle is terminated and the converter delivers limited current to the output. Under these conditions the undervoltage threshold is reached eventually and the controller enters the hiccup mode. The controller stays in hiccup mode for seven consecutive cycles. At the eighth cycle the controller attempts a full start-up sequence. PGOOD 14 O Power good indicator of the output voltage. This open-drain output connects to the supply via an external resistor. PWM1 21 O PWM2 20 O PWM3 19 O PWM4 18 O REF 8 O Output of an internal 0.7-V reference voltage. RT 16 I Connecting a resistor from this pin to ground sets the oscillator frequency. VIN 23 I Power input for the chip. De-coupling of this pin is required. VOUT 12 I Non-inverting input of the differential amplifier. This pin should be connected to VOUT at the point of load. 6 Used to sense the inductor current in the phases. Inductor current can be sensed with an external current sense resistor or by using an external circuit and the inductor’s DC resistance. They are also used for overcurrent protection and forced current sharing between the phases. Phase shifted PWM outputs which control the external drivers. The high output signal commands a PWM cycle. The low output signal commands controlled conduction of the synchronous rectifiers. These pins are also used to program various operating modes as follows: for three-phase mode, PWM4 is connected to 5 V; for two-phase mode, PWM2 and PWM4 are connected to 5 V. www.ti.com SLUS578A − OCTOBER 2003 − REVISED JUNE 2004 FUNCTIONAL BLOCK DIAGRAM RT 16 TPS40090 COMP 9 CLOCK FB 10 + 5 µA DROOP 7 REF 8 01 A = −(K +Y) B = +1 A SS 15 + 21 PWM1 IDROOP 02 B 1/N + 700 mV + 20 PWM2 PH2 PH4 A DIFFO 11 GNDS 13 VOUT 12 CSCN 1 CS2 2 CS3 CS4 3 4 + 19 PWM3 A + 04 B 5 CS1 03 B + 18 PWM4 A gM PHDET IPH1 + gM + IPH3 gM + PH2 IPH2 Σ IPH y K B PH2 gM + IPH1 IPH4 IPH2 POWER GOOD IPH3 CURRENT LIMIT 5V REG IPH4 23 VIN 22 BP5 17 GND PH4 14 6 24 PGOOD ILIM EN/SYNC www.ti.com PH4 UDG−03118 7 SLUS578A − OCTOBER 2003 − REVISED JUNE 2004 APPLICATION INFORMATION FUNCTIONAL DESCRIPTION The TPS4009x is a multiphase, synchronous, peak current mode, buck controller. The controller uses external gate drivers to operate N-channel power MOSFETs. The controller can be configured to operate in a two-, three-, or four-phase power supply. The controller accepts current feedback signals from either current sense resistors placed in series with the filter inductors or current proportional signals derived from the inductors’ DCR. Other features include an LDO regulator with UVLO to provide single voltage operation, a differential input amplifier for precise output regulation, user programmable operation frequency for design flexibility, external synchronization capability, programmable pulse-by-pulse overcurrent protection, output overvoltage protection, and output undervoltage shutdown. DIFFERENTIAL AMPLIFIER The unity gain differential amplifier with high bandwidth allows improved regulation at a user-defined point and eases layout constraints. The output voltage is sensed between the VOUT and GNDS pins. The output voltage programming divider is connected to the output of the amplifier (DIFFO). The differential amplifier can be used only for output voltages lower then 3.3 V. If there is no need for a differential amplifer, or if the output voltage required is higher than 3.3-V, the differential amplifier can be disabled by connecting the GNDS pin to the BP5 pin. The voltage programming divider in this case shoudl be connected directly to the output of the converter. CURRENT SENSING AND BALANCING The controller employs a peak current-mode control scheme, which naturally provides a certain degree of current balancing. With current mode, the level of current feedback should comply with certain guidelines depending on duty factor, known as slope compensation to avoid sub-harmonic instability. This requirement can prohibit achieving a higher degree of phase current balance. To avoid the controversy, a separate current loop that forces phase currents to match is added to the proprietary control scheme. This effectively provides high degree of current sharing independently of properties of controller’s small signal response. High-bandwidth current amplifiers can accept as an input voltage either voltage drop across dedicated precise current-sense resistors, or inductor’s DCR voltage derived by an R-C network, or thermally compensated voltage derived from the inductor’s DCR. The wide range of current-sense settings eases the cost and complexity constraints and provides performance superior to those found in controllers using low-side MOSFET current sensing. 8 www.ti.com SLUS578A − OCTOBER 2003 − REVISED JUNE 2004 APPLICATION INFORMATION SETTING CONTROLLER CONFIGURATION By default, the controller operates at four-phase configuration. The alternate number of active phases is programmed by connecting unused PWM outputs to BP5. (See Figure 1) For example, for three-phase operation, the unused fourth phase output, PWM4, should be connected to BP5. For two-phase operation, the second, PWM2, and the fourth, PWM4, outputs should be connected to BP5. POWER UP Capacitors connected to the BP5 pin and the soft-start pin set the power-up time. When EN is high, the capacitor connected to the BP5 pin gets charged by the internal LDO as shown in Figure 2. t BPS + 4.5 8 C BP5 10 *3 (1) 1 4−Phase Operation 2 EN 3 4 BP5 1 3−Phase Operation SS 2 1.0 0.7 3 4 BP5 VOUT 1 2−Phase Operation 2 PGOOD BP5 3 4 t − Time BP5 UDG−03119 UDG−03115 Figure 1. Programming Controller Configuration Figure 2. Power-Up Waveforms When the BP5 pin voltage crosses its lower undervoltage threshold and the power-on reset function is cleared, the calibrated current source starts charging the soft start capacitor. The PGOOD pin is held low during the start up. The rising voltage across the capacitor serves as a reference for the error amplifier assuring start−up in a closed loop manner. When the soft start pin voltage reaches the level of the reference voltage VREF = 0.7 V, the converter’s output reaches the regulation point and further rise of the soft start voltage has no effect on the output. www.ti.com 9 SLUS578A − OCTOBER 2003 − REVISED JUNE 2004 APPLICATION INFORMATION t SS + 0.7 5 C SS 10 *6 (2) When the soft-start voltage reaches level of 1.0 V, the power good (PGOOD) function is cleared and reported on the PGOOD pin. Normally, the PGOOD pin goes high at this moment. The time from when SS begins to rise to when PGOOD is reported is: t PG + 1.43 T SS (3) OUTPUT VOLTAGE PROGRAMMING The converter output voltage is programmed by the R1/R2 divider from the output of the differential amplifier. The center point of the divider is connected to the inverting output of the error amplifier (FB), as shown in Figure 5. V OUT + 0.7 V ǒR1 ) 1Ǔ R2 (4) CURRENT SENSE FAULT PROTECTION Multiphase controllers with forced current sharing are inherently sensitive to failure of a current sense component. In case of such failure the whole load current can be steered with catastrophic consequences into a single channel where the fault has happened. The dedicated circuit in the TPS4009x controller prevents it from starting up if any current sense pin is open or shorted to ground. The current-sense fault detection circuit is active only during device initialization and does not protect should a current-sense failure happen during normal operation. OVERVOLTAGE PROTECTION If the voltage at the FB pin (VFB) exceeds VREF by more than 16%, the TPS4009x enters into an overvoltage state. In this condition, the output signals from the controller to the external drivers is pulled low, causing the drivers to force all of the upper MOSFETs to the OFF position and all the lower MOSFETs to the ON position. As soon as VFB returns to regulation, the normal operaing state resumes. OVERCURRENT PROTECTION The overcurrent function monitors the voltage level separately on each current sense input and compares it to the voltage on the ILIM pin set by a divider from the controller’s reference. In case a threshold of VILIM/2.7 is exceeded the PWM cycle on the associated phase is terminated. The voltage level on the ILIM pin is determined by the following expression: V ILIM + 2.7 I PH(max) I PH(max) + I OUT ) R CS ǒVIN * VOUTǓ 2 L f SW (5) V OUT V IN (6) where D IPH(max) is a maximum value of the phase current allowed D RCS is a value of the current sense resistor used 10 www.ti.com SLUS578A − OCTOBER 2003 − REVISED JUNE 2004 APPLICATION INFORMATION If the overcurrent condition continues, each phase’s PWM cycle is terminated by the overcurrent signals. This puts a converter in a constant current mode with the output current programmed by the ILIM voltage. Eventually the supply and demand equilibrium on the converter output fails and the output voltage declines. When the undervoltage threshold is reached, the converter enters a hiccup mode. The controller is stopped and the output is not regulated any more, the softstart pin function changes. It serves now as a timing capacitor for a fault control circuit. The soft-start pin is periodically charged and discharged by the fault control circuit. After seven hiccup cycles expire, the controller attempts to restore normal operation. If the overload condition is not cleared, the controller stays in the hiccup mode indefinitely long. In such conditions the average current delivered to the load is roughly 1/8 of the set overcurrent value. UNDERVOLTAGE PROTECTION If the FB pin voltage falls lower than the undervoltage protection threshold (84.5%), the controller enters the hiccup mode as it is described in the Overcurrent Protection section. FAULT-FREE OPERATION If the SS pin voltage is externally prevented from rising above the 1-V threshold, the controller does not execute nor report most faults and the PGOOD output remains low. Only the overcurrent function and current-sense fault remain active. The overcurrent protection continues to terminate PWM cycle every time when the threshold is exceeded but the hiccup mode is not entered. www.ti.com 11 SLUS578A − OCTOBER 2003 − REVISED JUNE 2004 APPLICATION INFORMATION SETTING THE SWITCHING FREQUENCY The clock frequency is programmed by the value of the timing resistor connected from the RT pin to ground. R RT + K PH ǒ39.2 10 3 f *1.041 * 7Ǔ PH (7) where KPH is a coefficient that depends on the number of active phases. For two-phase and three-phase configurations KPH=1.333. For four-phase configurations, KPH=1.0. fPH is a single phase frequency, kHz. The RT resistor value is returned by the last expression in kΩ. To calculate the output ripple frequency, use the following equation: F RPL + N PH f PH (8) where D NPH is a number of phases used in the converter The switching frequency of the controller can be synchronized to an external clock applied to the EN/SYNC pin. The external frequency should be somewhat higher than the free-running clock frequency for synchronization to take place. SWITCHING FREQUENCY vs TIMING RESISTANCE fSW − Switching Frequency − kHz 10000 100 0 50 100 150 200 RT − Timing Resistance − kΩ Figure 3 12 www.ti.com 250 300 SLUS578A − OCTOBER 2003 − REVISED JUNE 2004 APPLICATION INFORMATION SETTING THE OUTPUT VOLTAGE DROOP In many applications the output voltage of the converter is intentionally allowed to droop as load current increases. This approach (sometimes referred to as active load line programming) allows for better use of the regulation window and reduces the amount of the output capacitors required to handle the same load current step. A resistor from the REF pin to the DROOP pin sets the desired value of the output voltage droop. R DROOP + 2500 N PH I OUT V DROOP R CS 2500 N PH V DROOP V REF + V OUT V CS1 ) V CS2 ) V CS3 ) V CS4 R2 R1 ) R2 (9) where D D D D D VDROOP is the value of droop at maximum load current IOUT NPH is number of phases RCS is the current-sense resistor value 2500 Ω is the inversed value of transconductance from the current sense pins to DROOP VCSx, are the average voltages on the current sense pins GNDS Differential Amplifier 13 OUTPUT VOLTAGE vs OUTPUT CURRENT VOUT + 12 DIFFO 11 VOUT VOUT − Output Voltage − V COMP 9 VDROOP R1 IDROOP C1 Error Amplifier R3 FB 10 + DROOP R2 7 IDROOP RDROOP REF + 8 IOUT(max) 0 700 mV IOUT − Output Current − A Figure 4 UDG−03116 www.ti.com Figure 5 UDG−03117 13 SLUS578A − OCTOBER 2003 − REVISED JUNE 2004 APPLICATION INFORMATION FEEDBACK LOOP COMPENSATION The TPS4009x operates in a peak current mode and the converter exhibits a single pole response with ESR zero for which Type II compensation network is usually adequate, as shown in Figure 7. The following equations show where the load pole and ESR zero calculations are situated. f OP + 2p 1 R OUT C OUT f ESRZ + 2p 1 R ESR C OUT (10) To achieve desired bandwidth the error amplifier must compensate for modulator gain loss on the crossover frequency and this is facilitated by placing the zero over the load pole. The ESR zero alters the modulator’s −1 slope at higher frequencies.To compensate for that alteration, the pole in-error amplifier transfer function should be added at frequency of the ESR zero as shown in Figure 6. Modulator LOUT 9 C1 C2 COUT R2 R1 10 ROUT + + RBIAS RERS UDG−03143 Figure 6 The following equations help in choosing components of the error amplifier compensation network. Fixing the value of the resistor R1 first is recommended as it simplifies further adjustments of the output voltage without altering the compensation network. R2 + R1 10 ǒ *G OMAG 20 Ǔ; C1 + ǒ2p 1 F OP R2Ǔ ; C2 + ǒ2p 1 F ESRZ R2Ǔ (11) Introduction of output voltage droop as a measure to reduce amount of filter capacitors changes the transfer function of the modulator as it is shown in the Figure 8. 14 www.ti.com SLUS578A − OCTOBER 2003 − REVISED JUNE 2004 APPLICATION INFORMATION GAIN AND PHASE vs FREQUENCY WITHOUT DROOP GAIN AND PHASE vs FREQUENCY WITH DROOP 80 80 Converter Overall G − Gain − dB 40 20 EA 60 Type II G − Gain − dB 60 Modulator 40 Droop Zero 20 0 0 Load Pole Load Pole −20 −40 −40 200 150 200 Phase 150 100 Phase − ° Phase − ° 100 50 50 0 0 −50 −100 10 ESR Zero −20 ESR Zero −50 100 1k 10 k f − Frequency − Hz 100 k 1M −100 10 100 1k 10 k f − Frequency − Hz 100 k 1M Figure 8 Figure 7 www.ti.com 15 SLUS578A − OCTOBER 2003 − REVISED JUNE 2004 APPLICATION INFORMATION The droop function, as well as the output capacitor ESR, introduces zero on some frequency left of the crossover point. F DROOPZ + 2p 1 ǒ Ǔ V DROOP I OUT(max) C OUT (12) To compensate for this zero, pole on the same frequency should be added to the error amplifier transfer function. With Type II compensation network a new value for the capacitor C2 is required compared to the case without droop. C2 + C1 2p R2 ǒF DROOPZ * 1Ǔ C1 (13) When attempting to close the feedback loop at frequency that is near the theoretical limit, use the above considerations as a first approximation and perform on bench measurements of closed loop parameters as effects of switching frequency proximity and finite bandwidth of voltage and current amplifiers may substantially alter them as it is shown in Figure 9. GAIN AND PHASE vs FREQUENCY 60 Phase 80 50 60 30 40 20 10 Gain Phase − ° G − Gain − dB 40 20 0 0 −10 −20 100 VIN = 12 V VOUT = 1.5 V IOUT= 100 A 1k 10 k 100 k f − Frequency − Hz Figure 9 16 www.ti.com −20 1M SLUS578A − OCTOBER 2003 − REVISED JUNE 2004 APPLICATION INFORMATION THERMAL COMPENSATION OF DCR CURRENT SENSING Inductor DCR current sensing is a known lossless technique to retrieve a current proportional signal. Equations (14) and (15) show the calculation used to determine the DCR voltage drop for any given frequency. (See Figure 10) V DCR + ǒV IN * V OUTǓ DCR DCR ) w V C + ǒV IN * V OUTǓ L (14) ǒR ) w 1 CǓ (15) 1 w C Voltage across the capacitor is equal to voltage drop across the inductor DCR, VC=VDCR when time constant of the inductor and the time constant of the R-C network are equal: VC + 1 w C ǒR ) w 1 CǓ + DCR DCR ) w L ; L +R DCR C; t DCRL + t RC (16) The output signal generated by the network shown in Figure 10 is temperature dependant due to positive thermal coefficient of copper specific resistance as determined using equation (17). The temperature variation of the inductor coil can easily exceed 100°C in a practical application leading to approximately 40% variation in the output signal and in turn, respectively move the overcurrent threshold and the load line. K(T) + 1 ) 0.0039 (T * 25) (17) The relatively simple network shown in Figure 11 (made of passive components including one NTC resistor) can provide almost complete compensation for copper thermal variations. L DCR VDCR L VIN C R DCR VOUT R2 C R R1 VC RNTC UDG−03142 Figure 10 RTHE UDG−03142 Figure 11 www.ti.com 17 SLUS578A − OCTOBER 2003 − REVISED JUNE 2004 APPLICATION INFORMATION The following algorithm and expressions help to determine components of the network. 1. Calculate the equivalent impedance of the network at 25°C that matches the inductor parameters in equation (18). It is recommended to use COG type capacitors for this application. For example, for L=0.4 µH, DCR=1.22 mΩ, C=10 nF; RE=33.3 kΩ. It is recommended to keep RE < 50 kΩ as higher values may produce false triggering of the current sense fault protection. L DCR RE + C (18) 2. It is necessary to set the network attenuation value KDIV(25) at 25°C. For example, KDIV(25)=0.85. The attenuation values KDIV(25)>0.9 produces higher values for NTC resistors that are harder to get from suppliers. Attenuation values lower 0.7 substantially reduce the network output signal. 3. Based on calculated RE and KDIV(25) values, calculate and pick the closest standard value for the resistor R=RE/KDIV(25). For the given example R=33kΩ/0.85=38.8kΩ. The closest standard value from 1% line is R=39.2kΩ. 4. Pick two temperature values at which curve fitting is made. For example T1=50°C and T2=90°C. 5. Find the relative values of RTHE required on each of these temperatures. R THE1 + RT + R THE(T1) R THE(25) R THE2 + K DIV(T) 1 * K DIV(T) R THE(T2) R THE(25) K DIV(25) 1 ) 0.0039 (t * 25) K DIV(T) + R (19) (20) For the given example RTHE1= 0.606, RTHE2=0.372. 6. From the NTC resistor datasheet get the relative resistance for resistors with desired curve. For the given example and curve 17 for NTHS NTC resistors from Vishay RNTC1=0.3507 and RNTC2=0.08652. 7. Calculate relative values for network resistors including the NTC resistor. R1 R + ǒRNTC1 * RNTC2Ǔ R NTC1 R E1 R E2 ǒ1 * RNTC2Ǔ * RNTC2 ƪ R NTC1 1 * 1 * R1 R R E1 * R1 R R2 R + ǒ1 * R NTC1Ǔ RNTC R R E2 * R NTC1 R E1 + ƪǒ1 * R1 Ǔ R *1 * ǒR2 RǓ ƫ *1 ǒ1 * RNTC2Ǔ ) RNTC2 RE1 ǒ1 * RNTC1Ǔ ; R E2 ǒ1 * R NTC1Ǔ * ǒR NTC1 * R NTC2Ǔ (21) ƫ *1 ; *1 (23) For the given example R1R= 0.281, R2R=2.079, and RNTCR = 1.1. 8. Calculate the absolute value of the NTC resistor as RTHE(25). In given example RNTC=244.3 kΩ. 18 (22) www.ti.com SLUS578A − OCTOBER 2003 − REVISED JUNE 2004 APPLICATION INFORMATION 9. Find a standard value for the NTC resistor with chosen curve type. In case the close value does not exist in a desired form factor or curve type. Chose a different type of the NTC resistor and repeat steps 6 to 9. In the example, the NTC resistor with the part number NTHS0402N17N2503J with RNTCS(25)=250 kΩ is close enough to the calculated value. 10. Calculate a scaling factor for the chosen NTC resistor as a ratio between selected and calculated NTC value and. In the example k=1.023. k+ RNTC S RNTC C (24) 11. Calculate values of the remaining network resistors. ƪǒ(1 * k) ) k R1 C + R THE(25) R1 RǓ ƫ (25) For the given example R1C=58.7 kΩ and R2C=472.8 kΩ. Pick the closest available 1% standard values: R1=39.2 kΩ, and R2=475 kΩ, thus completing the design of the thermally compensated network for the DCR current sensor. Figure 24 illustrates the fit of the designed network to the required function. CURRENT SENSE IMPEDANCE vs AMBIENT TEMPERATURE RTHE (T5C) − Current Sense Impedance − kΩ 40 r Measured Acquired 30 r 20 r 10 10 20 r 40 60 80 100 TA − Ambient Temperature − °C 120 Figure 12 www.ti.com 19 SLUS578A − OCTOBER 2003 − REVISED JUNE 2004 Operation with Output Voltages Higher Than 3.3 V The TPS40090/91 controllers are designed to operate in power supplies with output voltages ranging from 0.7 V to 3.3 V. To support higher output voltages, mainly in 12.0 V to 5.0 V power supplies, the BP5 voltage needs to be increased slightly to provide enough headroom to ensure linearity of current sense amplifiers. The simple circuit on Figure 13 shows a configuration that generates a 6.0-V voltage source to power the controller with increased bias voltage. Both the VIN and BP5 pins should be connected to this voltage source. The differential amplifier normally excessive for higher-output voltages can be disabled by connecting GNDS pin to the BP5 pin. 12 V TPS4009x 1.1 kΩ 1 CS1 2 CS2 VIN 23 3 CS3 BP5 22 4 CS4 PWM1 21 5 CSCN PWM2 20 EN/SYNC 24 13.7 kΩ 6.0 V 4.7 µF TLA431 10 kΩ UDG−04064 Figure 13. Biasing the TPS4009x with a 5.0-V Power Supply High-Impedance State of TPS40091 Outputs The TPS40091 controller has three-state enabled outputs to interface various gate drivers and DRMOS devices capable of turning all MOSFETs in the power supply into high-impedance state while remaining active. The common binary output commands the control MOSFET on when the PWM signal is high. Alternatively, the synchronous MOSFET is commanded on when the PWM signal is low. The three-state output can command both MOSFETs off when the PWM output is in the high-impedance state. This feature simplifies design of power supplies capable of starting into pre-charged output or allows in VR modules use of gate drivers that do not have the enable input to put VR module off line. Some DRMOS devices like Philips PIP202 also made compatible with three-state outputs of the multiphase controller. The TPS40091 outputs have high impedance when the EN pin is high but the soft-start sequence has not been initiated yet. The output impedance is also high when controller is in undervoltage fault condition or disabled. Figure 14 shows a 12-V, 80-A, all-ceramic power supply capable to start into pre-charged outputs. DESIGN EXAMPLE A design example is available. Please refer to the TPS40090EVM−001 user’s guide (SLUU175). 20 www.ti.com 12V + + + + + + 1.2V/100A SLUS578A − OCTOBER 2003 − REVISED JUNE 2004 Figure 14. 1.2-V, 80-A ASIC All-Ceramic, Power Supply www.ti.com 21 PACKAGE OPTION ADDENDUM www.ti.com 30-Mar-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) TPS40090PW ACTIVE TSSOP PW 24 60 TBD CU NIPDAU Level-1-220C-UNLIM TPS40090PWR ACTIVE TSSOP PW 24 2000 TBD CU NIPDAU Level-1-220C-UNLIM TPS40091PW ACTIVE TSSOP PW 24 60 TBD CU NIPDAU Level-1-220C-UNLIM TPS40091PWR ACTIVE TSSOP PW 24 2000 TBD CU NIPDAU Level-1-220C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. 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