PCA9548A 8-CHANNEL SWITCH WITH RESET I2C www.ti.com SCPS143B – OCTOBER 2006 – REVISED MARCH 2007 FEATURES • • • • 1-of-8 Bidirectional Translating Switches I2C Bus and SMBus Compatible Active-Low Reset Input Address by Three Hardware Address Pins for Use of up to Eight Devices Channel Selection Via I2C Bus Power-Up With All Switch Channels Deselected Low RON Switches Allows Voltage-Level Translation Between 2.5-V, 3.3-V, and 5-V Buses • • • • • • • • No Glitch on Power-Up Supports Hot Insertion Low Standby Current Operating Power-Supply Voltage Range of 2.3 V to 5.5 V 5-V Tolerant Inputs 400-kHz Fast I2C Bus Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) RGE PACKAGE (TOP VIEW) 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 VCC SDA SCL A2 SC7 SD7 SC6 SD6 SC5 SD5 SC4 SD4 24 23 22 21 20 19 SD0 SC0 SD1 SC1 SD2 SC2 18 A2 17 SC7 1 2 16 SD7 15 SC6 3 4 5 14 SD6 13 SC5 6 7 8 9 10 11 12 SD3 SC3 GND SD4 SC4 SD5 A0 A1 RESET SD0 SC0 SD1 SC1 SD2 SC2 SD3 SC3 GND RESET A1 A0 VCC DB, DGV, DW, OR PW PACKAGE (TOP VIEW) SDA SCL • • • • DESCRIPTION/ORDERING INFORMATION ORDERING INFORMATION PACKAGE (1) TA QFN – RGE SSOP – DB –40°C to 85°C TVSOP – DGV SOIC – DW TSSOP – PW (1) ORDERABLE PART NUMBER Reel of 3000 PCA9548ARGER Reel of 2000 PCA9548ADBR Reel of 250 PCA9548ADBT Reel of 2000 PCA9548ADGVR Reel of 2000 PCA9548ADWR Tube of 25 PCA9548ADW Reel of 2000 PCA9548APWR Tube of 60 PCA9548APW TOP-SIDE MARKING PD548A PD548A PD548A PCA9548A PD548A For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI Web site at www.ti.com. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006–2007, Texas Instruments Incorporated PCA9548A 8-CHANNEL I2C SWITCH WITH RESET www.ti.com SCPS143B – OCTOBER 2006 – REVISED MARCH 2007 DESCRIPTION/ORDERING INFORMATION (CONTINUED) The PCA9548A has eight bidirectional translating switches that can be controlled via the I2C bus. The SCL/SDA upstream pair fans out to eight downstream pairs, or channels. Any individual SCx/SDx channel or combination of channels can be selected, determined by the contents of the programmable control register. The system master can reset the PCA9548A in the event of a timeout or other improper operation by asserting a low in the RESET input. Similarly, the power-on reset deselects all channels and initializes the I2C/SMBus state machine. Asserting RESET causes the same reset/initialization to occur without depowering the part. The pass gates of the switches are constructed so that the VCC pin can be used to limit the maximum high voltage, which is passed by the PCA9548A. This allows the use of different bus voltages on each pair, so that 2.5-V or 3.3-V parts can communicate with 5-V parts, without any additional protection. External pullup resistors pull the bus up to the desired voltage level for each channel. All I/O pins are 5-V tolerant. 2 Submit Documentation Feedback PCA9548A 8-CHANNEL SWITCH WITH RESET I2C www.ti.com SCPS143B – OCTOBER 2006 – REVISED MARCH 2007 FUNCTIONAL BLOCK DIAGRAM PCA9548A SC0 SC1 SC2 SC3 SC4 SC5 SC6 SC7 SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 Switch Control Logic GND VCC RESET SCL SDA Reset Circuit A0 Input Filter 2 I C Bus Control A1 A2 Submit Documentation Feedback 3 PCA9548A 8-CHANNEL I2C SWITCH WITH RESET www.ti.com SCPS143B – OCTOBER 2006 – REVISED MARCH 2007 TERMINAL FUNCTIONS NO. SOIC (DW), SSOP (DB), TSSOP (PW), AND TVSOP (DGV) QFN (RGE) 1 22 A0 Address input 0. Connect directly to VCC or ground. 2 23 A1 Address input 1. Connect directly to VCC or ground. 3 24 RESET 4 1 SD0 Serial data 0. Connect to VCC through a pullup resistor. 5 2 SC0 Serial clock 0. Connect to VCC through a pullup resistor. 6 3 SD1 Serial data 1. Connect to VCC through a pullup resistor. 7 4 SC1 Serial clock 1. Connect to VCC through a pullup resistor. 8 5 SC2 Serial data 2. Connect to VCC through a pullup resistor. 9 6 SC2 Serial clock 2. Connect to VCC through a pullup resistor. 10 7 SD3 Serial data 3. Connect to VCC through a pullup resistor. 11 8 SC3 Serial clock 3. Connect to VCC through a pullup resistor. 12 9 GND Ground 13 10 SD4 Serial data 4. Connect to VCC through a pullup resistor. 14 11 SC4 Serial clock 4. Connect to VCC through a pullup resistor. 15 12 SD5 Serial data 5. Connect to VCC through a pullup resistor. 16 13 SC5 Serial clock 5. Connect to VCC through a pullup resistor. 17 14 SD6 Serial data 6. Connect to VCC through a pullup resistor. 18 15 SC6 Serial clock 6. Connect to VCC through a pullup resistor. 19 16 SD7 Serial data 7. Connect to VCC through a pullup resistor. 20 17 SC7 Serial clock 7. Connect to VCC through a pullup resistor. 21 18 A2 22 19 SCL Serial clock bus. Connect to VCC through a pullup resistor. 23 20 SDA Serial data bus. Connect to VCC through a pullup resistor. 24 21 VCC Supply voltage NAME DESCRIPTION Active-low reset input. Connect to VCC through a pullup resistor, if not used. Address input 2. Connect directly to VCC or ground. I2C Interface The bidirectional I2C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be connected to a positive supply through a pullup resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. I2C communication with this device is initiated by a master sending a start condition, a high-to-low transition on the SDA input/output while the SCL input is high (see Figure 1). After the start condition, the device address byte is sent, most significant bit (MSB) first, including the data direction bit (R/W). After receiving the valid address byte, this device responds with an acknowledge (ACK), a low on the SDA input/output during the high of the ACK-related clock pulse. The address inputs (A0–A2) of the slave device must not be changed between the start and the stop conditions. On the I2C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control commands (start or stop) (see Figure 2). A stop condition, a low-to-high transition on the SDA input/output while the SCL input is high, is sent by the master (see Figure 1). 4 Submit Documentation Feedback PCA9548A 8-CHANNEL SWITCH WITH RESET I2C www.ti.com SCPS143B – OCTOBER 2006 – REVISED MARCH 2007 Any number of data bytes can be transferred from the transmitter to receiver between the start and the stop conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before the receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACK clock pulse so that the SDA line is stable low during the high pulse of the ACK-related clock period (see Figure 3). When a slave receiver is addressed, it must generate an ACK after each byte is received. Similarly, the master must generate an ACK after each byte that it receives from the slave transmitter. Setup and hold times must be met to ensure proper operation. A master receiver signals an end of data to the slave transmitter by not generating an acknowledge (NACK) after the last byte has been clocked out of the slave. This is done by the master receiver by holding the SDA line high. In this event, the transmitter must release the data line to enable the master to generate a stop condition. SDA SCL S P Start Condition Stop Condition Figure 1. Definition of Start and Stop Conditions SDA SCL Data Line Stable; Data Valid Change of Data Allowed Figure 2. Bit Transfer Data Output by Transmitter NACK Data Output by Receiver ACK SCL From Master 1 2 8 9 S Clock Pulse for Acknowledgment Start Condition Figure 3. Acknowledgment on I2C Bus Submit Documentation Feedback 5 PCA9548A 8-CHANNEL I2C SWITCH WITH RESET www.ti.com SCPS143B – OCTOBER 2006 – REVISED MARCH 2007 Device Address Figure 4 shows the address byte of the PCA9548A. Slave Address 1 1 1 Fixed 0 A2 A1 A0 R/W Hardware Selectable Figure 4. PCA9548A Address Address Reference INPUTS A0 I2C BUS SLAVE ADDRESS A2 A1 L L L 112 (decimal), 70 (hexadecimal) L L H 113 (decimal), 71 (hexadecimal) L H L 114 (decimal), 72 (hexadecimal) L H H 115 (decimal), 73 (hexadecimal) H L L 116 (decimal), 74 (hexadecimal) H L H 117 (decimal), 75 (hexadecimal) H H L 118 (decimal), 76 (hexadecimal) H H H 119 (decimal), 77 (hexadecimal) The last bit of the slave address defines the operation (read or write) to be performed. When it is high (1), a read is selected, while a low (0) selects a write operation. Control Register Following the successful acknowledgment of the address byte, the bus master sends a command byte that is stored in the control register in the PCA9548A (see Figure 5). This register can be written and read via the I2C bus. Each bit in the command byte corresponds to a SCn/SDn channel and a high (or 1) selects this channel. Multiple SCn/SDn channels may be selected at the same time. When a channel is selected, the channel becomes active after a stop condition has been placed on the I2C bus. This ensures that all SCn/SDn lines are in a high state when the channel is made active, so that no false conditions are generated at the time of connection. A stop condition always must occur immediately after the acknowledge cycle. If multiple bytes are received by the PCA9548A, it saves the last byte received. 6 Submit Documentation Feedback PCA9548A 8-CHANNEL SWITCH WITH RESET I2C www.ti.com SCPS143B – OCTOBER 2006 – REVISED MARCH 2007 Channel Selection Bits (Read/Write) B7 B6 B5 B4 B3 B2 B1 B0 Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7 Figure 5. Control Register Command Byte Definition CONTROL REGISTER BITS B7 B6 B5 B4 B3 B2 B1 X X X X X X X X X X X X X X X X X X X X X X X X 0 1 0 1 Channel 0 disabled 1 Channel 0 enabled X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 0 0 0 0 0 0 X X 0 1 X 0 1 1 0 1 1 COMMAND 0 X 0 X 0 0 B0 Channel 1 disabled Channel 1 enabled Channel 2 disabled Channel 2 enabled Channel 3 disabled Channel 3 enabled Channel 4 disabled Channel 4 enabled Channel 5 disabled Channel 5 enabled Channel 6 disabled Channel 6 enabled Channel 7 disabled Channel 7 enabled No channel selected, power-up/reset default state RESET Input The RESET input is an active-low signal that may be used to recover from a bus-fault condition. When this signal is asserted low for a minimum of tWL, the PCA9548A resets its registers and I2C state machine and deselects all channels. The RESET input must be connected to VCC through a pullup resistor. Submit Documentation Feedback 7 PCA9548A 8-CHANNEL I2C SWITCH WITH RESET www.ti.com SCPS143B – OCTOBER 2006 – REVISED MARCH 2007 Power-On Reset When power (from 0 V) is applied to VCC, an internal power-on reset holds the PCA9548A in a reset condition until VCC has reached VPOR. At that point, the reset condition is released and the PCA9548A registers and I2C state machine initialize to their default states. After that, VCC must be lowered to below 0.2 V and then back up to the operating voltage for a power-reset cycle. Voltage Translation The pass-gate transistors of the PCA9548A are constructed such that the VCC voltage can be used to limit the maximum voltage that is passed from one I2C bus to another. Figure 6 shows the voltage characteristics of the pass-gate transistors (note that the graph was generated using the data specified in the Electrical Characteristics section of this data sheet). 5 4.5 ISWout = –100µA Maximum 4 Vpass (V) 3.5 Typical 3 2.5 2 Minimum 1.5 1 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 6. Pass-Gate Voltage vs Supply Voltage at Three Process Points For the PCA9548A to act as a voltage translator, the Vo(sw) voltage must be equal to, or lower than, the lowest bus voltage. For example, if the main bus is running at 5 V and the downstream buses are 3.3 V and 2.7 V, Vo(sw) should be equal to or below 2.7 V to effectively clamp the downstream bus voltages. As shown in Figure 6, Vo(sw)(max) is 2.7 V when the PCA9548A supply voltage is 3.5 V or lower, so the PCA9548A supply voltage can be set to 3.3 V. Pullup resistors then can be used to bring the bus voltages to their appropriate levels (see Figure 11). Bus Transactions Data is exchanged between the master and PCA9548A through write and read commands. Writes Data is transmitted to the PCA9548A by sending the device address and setting the least-significant bit (LSB) to a logic 0 (see Figure 4 for device address). The command byte is sent after the address and determines which SCn/SDn channel receives the data that follows the command byte (see Figure 7). There is no limitation on the number of data bytes sent in one write transmission. 8 Submit Documentation Feedback PCA9548A 8-CHANNEL SWITCH WITH RESET I2C www.ti.com SCPS143B – OCTOBER 2006 – REVISED MARCH 2007 Slave Address SDA S 1 1 1 0 Control Register A2 A1 A0 Start Condition 0 A B7 B6 B5 B4 B3 B2 B1 B0 R/W ACK From Slave A ACK From Slave P Stop Condition Figure 7. Write to Control Register Reads The bus master first must send the PCA9548A address with the LSB set to a logic 1 (see Figure 4 for device address). The command byte is sent after the address and determines which SCn/SDn channel is accessed. After a restart, the device address is sent again, but this time, the LSB is set to a logic 1. Data from the SCn/SDn channel defined by the command byte then is sent by the PCA9548A (see Figure 8). After a restart, the value of the SCn/SDn channel defined by the command byte matches the SCn/SDn channel being accessed when the restart occurred. Data is clocked into the SCn/SDn channel on the rising edge of the ACK clock pulse. There is no limitation on the number of data bytes received in one read transmission, but when the final byte is received, the bus master must not acknowledge the data. Slave Address SDA S 1 Start Condition 1 1 0 Control Register A2 A1 A0 1 R/W A B7 B6 B5 B4 B3 ACK From Slave B2 B1 B0 NA NACK From Master P Stop Condition Figure 8. Read From Control Register Submit Documentation Feedback 9 PCA9548A 8-CHANNEL I2C SWITCH WITH RESET www.ti.com SCPS143B – OCTOBER 2006 – REVISED MARCH 2007 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC Supply voltage range –0.5 7 V VI Input voltage range (2) –0.5 7 V II Input current ±20 mA IO Output current ±25 mA ICC Supply current ±100 mA θJA Package thermal impedance, junction to free air (3) DB package 63 DGV package 86 DW package 46 PW package 88 UNIT °C/W RGE package 45 RGE package 1.5 °C/W θJP Package thermal impedance, junction to pad Tstg Storage temperature range –65 150 °C TA Operating free-air temperature range –40 85 °C (1) (2) (3) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. The package thermal impedance is calculated in accordance with JESD 51-7. Recommended Operating Conditions (1) VCC VIH High-level input voltage VIL Low-level input voltage TA Operating free-air temperature (1) 10 MIN MAX 2.3 5.5 SCL, SDA 0.7 × VCC 6 A2–A0, RESET 0.7 × VCC VCC + 0.5 SCL, SDA –0.5 0.3 × VCC A2–A0, RESET –0.5 0.3 × VCC –40 85 Supply voltage UNIT V V V °C All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Submit Documentation Feedback PCA9548A 8-CHANNEL SWITCH WITH RESET I2C www.ti.com SCPS143B – OCTOBER 2006 – REVISED MARCH 2007 Electrical Characteristics VCC = 2.3 V to 3.6 V, over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VPOR Power-on reset voltage (2) TEST CONDITIONS No load, VI = VCC or GND VCC MIN TYP (1) MAX VPOR 1.6 2.1 5V 3.6 4.5 V to 5.5 V Vo(sw) Switch output voltage Vi(sw) = VCC, ISWout = –100 µA 2.6 3.3 V 3 V to 3.6 V IOL VOL = 0.4 V SDA VOL = 0.6 V 2.3 V to 5.5 V 1.6 2.8 2 3 6 6 9 A2–A0 VI = VCC or GND ±1 2.3 V to 5.5 V ±1 fSCL = 400 kHz VI = VCC or GND, IO = 0 Operating mode fSCL = 100 kHz VI = VCC or GND, IO = 0 ICC Low inputs VI = GND, IO = 0 Standby mode High inputs SCL, SDA A2–A0 Ci RESET SCL Cio(off) (3) ron SDA SC7–SC0, SD7–SD0 Switch-on resistance VI = VCC, IO = 0 SCL or SDA input at 0.6 V, Other inputs at VCC or GND SCL or SDA input at VCC – 0.6 V, Other inputs at VCC or GND VI = VCC or GND 5.5 V 50 80 3.6 V 20 35 2.7 V 11 20 5.5 V 9 30 3.6 V 6 15 2.7 V 4 8 5.5 V 0.2 1 3.6 V 0.1 1 2.7 V 0.1 1 5.5 V 0.2 1 3.6 V 0.1 1 2.7 V 0.1 1 3 20 3 20 4 5 VI = VCC or GND, Switch OFF VO = 0.4 V, IO = 15 mA µA µA 2.3 V to 5.5 V 2.3 V to 5.5 V VI = VCC or GND, Switch OFF VO = 0.4 V, IO = 10 mA (1) (2) (3) µA ±1 RESET ∆ICC mA ±1 SC7–SC0, SD7–SD0 Supply-current change V 1.5 1.1 SCL, SDA II V 4.5 1.9 2.5 V 2.3 V to 2.7 V UNIT 2.3 V to 5.5 V 4 5 20 28 20 28 5.5 7.5 4.5 V to 5.5 V 4 10 20 3 V to 3.6 V 5 12 30 2.3 V to 2.7 V 7 15 45 pF pF Ω All typical values are at nominal supply voltage (2.5-V, 3.3-V, or 5-V VCC), TA = 25°C. The power-on reset circuit resets the I2C bus logic with VCC < VPOR. VCC must be lowered to 0.2 V to reset the device. Cio(ON) depends on internal capacitance and external capacitance added to the SCn lines when channels(s) are ON. Submit Documentation Feedback 11 PCA9548A 8-CHANNEL I2C SWITCH WITH RESET www.ti.com SCPS143B – OCTOBER 2006 – REVISED MARCH 2007 I2C Interface Timing Requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 9) STANDARD MODE I2C BUS MIN MAX 100 FAST MODE I2C BUS UNIT MIN MAX 0 400 fscl I2C clock frequency 0 tsch I2C clock high time 4 0.6 µs tscl I2C clock low time 4.7 1.3 µs tsp I2C tsds I2C serial-data setup time 250 100 ns tsdh I2C serial-data hold time 0 (1) 0 (1) µs ticr I2C input rise time ticf I2C tocf I2C output (SDn) fall time (10-pF to 400-pF bus) tbuf I2C bus free time between stop and start 4.7 1.3 µs tsts I2C start or repeated start condition setup 4.7 0.6 µs tsth I2C start or repeated start condition hold 4 0.6 µs tsps I2C stop condition setup 4 0.6 µs spike time 50 input fall time low) (3) tvdL(Data) Valid-data time (high to tvdH(Data) Valid-data time (low to high) (3) SCL low to SDA output high valid tvd(ack) Valid-data time of ACK condition ACK signal from SCL low to SDA output low Cb I2C bus capacitive load (1) (2) (3) SCL low to SDA output low valid kHz 50 ns 1000 20 + 0.1Cb (2) 300 ns 300 20 + 0.1Cb (2) 300 ns 300 20 + 0.1Cb (2) 300 ns 1 1 µs 0.6 0.6 µs 1 1 µs 400 400 pF A device internally must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH min of the SCL signal), to bridge the undefined region of the falling edge of SCL. Cb = total bus capacitance of one bus line in pF Data taken using a 1-kΩ pullup resistor and 50-pF load (see Figure 10) Switching Characteristics over recommended operating free-air temperature range, CL ≤ 100 pF (unless otherwise noted) (see Figure 9) PARAMETER tpd (1) Propagation delay time trst (2) RESET time (SDA clear) (1) (2) RON = 20 Ω, CL = 15 pF RON = 20 Ω, CL = 50 pF FROM (INPUT) TO (OUTPUT) SDA or SCL SDn or SCn RESET SDA MIN MAX UNIT 0.3 ns 1 500 ns The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance). trst is the propagation delay measured from the time the RESET pin is first asserted low to the time the SDA pin is asserted high, signaling a stop condition. It must be a minimum of tWL. Reset Timing Requirements over recommended operating free-air temperature range (unless otherwise noted) PARAMETER MIN MAX UNIT tW(L) Pulse duration, RESET low 6 ns tREC(STA) Recovery time from RESET to start 0 ns 12 Submit Documentation Feedback PCA9548A 8-CHANNEL SWITCH WITH RESET I2C www.ti.com SCPS143B – OCTOBER 2006 – REVISED MARCH 2007 PARAMETER MEASUREMENT INFORMATION VCC R L = 1 kΩ DUT SDA CL = 50 pF (see Note A) SDA LOAD CONFIGURATION Three Bytes for Complete Device Programming Address Stop Start Bit 7 Address Condition Condition Bit 6 (MSB) (P) (S) Address Bit 1 tscl R/W Bit 0 (LSB) ACK (A) Data Bit 7 (MSB) Data Bit 0 (LSB) Stop Condition (P) tsch 0.7 × VCC SCL 0.3 × VCC ticr tvd(ack) ticf tbuf tsp tsts tvdH(Data) 0.7 × VCC SDA 0.3 × VCC ticr ticf tsth tvdL(Data) tsdh tsds tsps Repeat Start Condition Start or Repeat Start Condition Stop Condition VOLTAGE WAVEFORMS BYTE DESCRIPTION 1 I2C address 2, 3 P-port data A. CL includes probe and jig capacitance. B. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns. C. Not all parameters and waveforms are applicable to all devices. Figure 9. I2C Load Circuit and Voltage Waveforms Submit Documentation Feedback 13 PCA9548A 8-CHANNEL I2C SWITCH WITH RESET www.ti.com SCPS143B – OCTOBER 2006 – REVISED MARCH 2007 PARAMETER MEASUREMENT INFORMATION (continued) VCC RL = 1 kΩ DUT SDA CL = 50 pF (see Note A) SDA LOAD CONFIGURATION Start SCL ACK or Read Cycle SDA 0.3 y VCC tRESET RESET VCC/2 tREC tw SDn, SCn 0.3 y VCC tRESET A. CL includes probe and jig capacitance. B. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns. C. I/Os are configured as inputs. D. Not all parameters and waveforms are applicable to all devices. Figure 10. Reset Load Circuit and Voltage Waveforms 14 Submit Documentation Feedback PCA9548A 8-CHANNEL SWITCH WITH RESET I2C www.ti.com SCPS143B – OCTOBER 2006 – REVISED MARCH 2007 APPLICATION INFORMATION Figure 11 shows an application in which the PCA9548A can be used. VCC = 2.7 V to 5.5 V VCC = 3.3 V VCC = 2.7 V to 5.5 V 24 I2C/SMBus Master SDA SCL RESET 23 22 3 See Note A SDA SD0 SCL SC0 4 Channel 0 5 VCC = 2.7 V to 5.5 V RESET See Note A SD1 6 SC1 7 Channel 1 VCC = 2.7 V to 5.5 V See Note A SD2 SC2 8 Channel 2 9 VCC = 2.7 V to 5.5 V See Note A SD3 SC3 10 Channel 3 11 VCC = 2.7 V to 5.5 V PCA9548A See Note A SD4 SC4 13 Channel 4 14 VCC = 2.7 V to 5.5 V See Note A SD5 15 SC5 16 Channel 5 VCC = 2.7 V to 5.5 V See Note A SD6 SC6 21 2 1 12 A. 17 Channel 6 18 VCC = 2.7 V to 5.5 V A2 See Note A A1 A0 SD7 GND SC7 19 20 Channel 7 Pin numbers shown are for the DB, DW, PW, and DGV packages. Figure 11. Typical Application Submit Documentation Feedback 15 PACKAGE OPTION ADDENDUM www.ti.com 20-Mar-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty PCA9548ADB ACTIVE SSOP DB 24 PCA9548ADBR ACTIVE SSOP DB PCA9548ADGVR ACTIVE TVSOP PCA9548ADW ACTIVE PCA9548ADWR 60 Lead/Ball Finish MSL Peak Temp (3) Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM DGV 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SOIC DW 24 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM ACTIVE SOIC DW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCA9548APW ACTIVE TSSOP PW 24 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCA9548APWR ACTIVE TSSOP PW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCA9548ARGER ACTIVE QFN RGE 24 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1YEAR 25 60 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 1 MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0°–8° 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. Falls within JEDEC: 24/48 Pins – MO-153 14/16/20/56 Pins – MO-194 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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