PCA9546A 4-CHANNEL AND SMBus SWITCH WITH RESET FUNCTION I2C www.ti.com SCPS148D – OCTOBER 2005 – REVISED OCTOBER 2006 FEATURES • • • • • • • • • 1-of-4 Bidirectional Translating Switches I2C Bus and SMBus Compatible Active-Low Reset Input Three Address Pins, Allowing up to Eight Devices on the I2C Bus Channel Selection Via I2C Bus Power Up With All Switch Channels Deselected Low RON Switches Allows Voltage-Level Translation Between 1.8-V, 2.5-V, 3.3-V, and 5-V Buses No Glitch on Power Up • • • • • • • Supports Hot Insertion Low Standby Current Operating Power-Supply Voltage Range of 2.3 V to 5.5 V 5.5-V Tolerant Inputs 0 to 400-kHz Clock Frequency Latch-Up Performance Exceeds 100 mA Per JESD 78 ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) DESCRIPTION/ORDERING INFORMATION The PCA9546A is a quad bidirectional translating switch controlled via the I2C bus. The SCL/SDA upstream pair fans out to four downstream pairs, or channels. Any individual SCn/SDn channel or combination of channels can be selected, determined by the contents of the programmable control register. An active-low reset (RESET) input allows the PCA9546A to recover from a situation in which one of the downstream I2C buses is stuck in a low state. Pulling RESET low resets the I2C state machine and causes all the channels to be deselected, as does the internal power-on reset function. ORDERING INFORMATION PACKAGE (1) TA PCA9546ARVR PREVIEW QFN – RGY Reel of 1000 PCA9546ARGYR PD546A SOIC – D Reel of 2500 Reel of 250 SOIC – DW TSSOP – PW PCA9546ADG4 PCA9546ADR PCA9546ADT PCA9546ADTG4 Reel of 2000 PCA9546ADWR Reel of 250 PCA9546ADWT Reel of 2000 PCA9546A PCA9546ADRG4 PCA9546ADW Reel of 250 TVSOP – DGV PCA9546AD Tube of 40 Tube of 90 (1) TOP-SIDE MARKING Reel of 2500 Tube of 40 –40°C to 85°C ORDERABLE PART NUMBER QFN – RGV PCA9546A PREVIEW PCA9546APW PCA9546APWE4 PCA9546APWR PCA9546APWRE4 PD546A PCA9546APWT PCA9546APWTE4 Reel of 2000 PCA9546ADGVR PD546A Reel of 250 PCA9546ADGVT PREVIEW Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2005–2006, Texas Instruments Incorporated PCA9546A 4-CHANNEL I2C AND SMBus SWITCH WITH RESET FUNCTION www.ti.com SCPS148D – OCTOBER 2005 – REVISED OCTOBER 2006 DESCRIPTION/ORDERING INFORMATION (CONTINUED) The pass gates of the switches are constructed such that the VCC pin can be used to limit the maximum high voltage, which will be passed by the PCA9546A. This allows the use of different bus voltages on each pair, so that 1.8-V, 2.5-V, or 3.3-V parts can communicate with 5-V parts without any additional protection. External pullup resistors pull the bus up to the desired voltage level for each channel. All I/O pins are 5.5-V tolerant. 12 6 11 7 10 8 9 SDA 11 A2 SC0 3 10 SC3 SD1 4 9 5 6 7 8 SD3 VCC 5 SD0 2 A1 RESET SD0 SC0 SD1 SC1 1 16 15 14 13 12 11 10 2 3 4 5 6 7 8 9 SD2 13 16 15 14 13 12 SCL A0 4 RGY PACKAGE (TOP VIEW) GND 14 RESET 1 SC2 3 VCC SDA SCL A2 SC3 SD3 SC2 SD2 SD2 15 GND 16 2 VCC A1 1 SC1 A0 A1 RESET SD0 SC0 SD1 SC1 GND A0 RGV PACKAGE (TOP VIEW) D, DGV, DW, OR PW PACKAGE (TOP VIEW) SDA SCL A2 SC3 SD3 SC2 TERMINAL FUNCTIONS NO. 2 D, DGV, DW, PW, AND RGY RGV 1 15 2 3 NAME DESCRIPTION A0 Address input 0. Connect directly to VCC or ground. 16 A1 Address input 1. Connect directly to VCC or ground. 1 RESET 4 2 SD0 Serial data 0. Connect to VCC through a pullup resistor. 5 3 SC0 Serial clock 0. Connect to VCC through a pullup resistor. 6 4 SD1 Serial data 1. Connect to VCC through a pullup resistor. 7 5 SC1 Serial clock 1. Connect to VCC through a pullup resistor. 8 6 GND Ground 9 7 SD2 Serial data 2. Connect to VCC through a pullup resistor. 10 8 SC2 Serial clock 2. Connect to VCC through a pullup resistor. 11 9 SD3 Serial data 3. Connect to VCC through a pullup resistor. 12 10 SC3 Serial clock 3. Connect to VCC through a pullup resistor. 13 11 A2 14 12 SCL Serial clock line. Connect to VCC through a pullup resistor. 15 13 SDA Serial data line. Connect to VCC through a pullup resistor. 16 14 VCC Supply power Active low reset input. Connect to VCC through a pullup resistor, if not used. Address input 2. Connect directly to VCC or ground. Submit Documentation Feedback PCA9546A 4-CHANNEL AND SMBus SWITCH WITH RESET FUNCTION I2C www.ti.com SCPS148D – OCTOBER 2005 – REVISED OCTOBER 2006 BLOCK DIAGRAM SC0 PCA9546A 5 SC1 7 SC2 10 SC3 12 SD0 4 SD1 6 SD2 9 SD3 11 GND VCC RESET SCL SDA A. Switch Control Logic 8 16 3 Power-On Reset 14 15 Input Filter I2C Bus Control 1 A0 2 A1 13 A2 Pin numbers shown are for the D, DGV, DW, PW and RGY packages. Submit Documentation Feedback 3 PCA9546A 4-CHANNEL I2C AND SMBus SWITCH WITH RESET FUNCTION www.ti.com SCPS148D – OCTOBER 2005 – REVISED OCTOBER 2006 Device Address Following a start condition, the bus master must output the address of the slave it is accessing. The address of the PCA9546A is shown in Figure 1. To conserve power, no internal pullup resistors are incorporated on the hardware-selectable address pins, and they must be pulled high or low. Slave Address 1 1 0 1 A2 A1 A0 R/W Hardware Selectable Fixed Figure 1. PCA9546A Address The last bit of the slave address defines the operation to be performed. When set to a logic 1, a read is selected, while a logic 0 selects a write operation. Control Register Following the successful acknowledgment of the slave address, the bus master sends a byte to the PCA9546A, which is stored in the control register (see Figure 2). If multiple bytes are received by the PCA9546A, it will save the last byte received. This register can be written and read via the I2C bus. Channel Selection Bits (Read/Write) 7 6 5 4 3 2 1 0 X X X X B3 B2 B1 B0 Channel 0 Channel 1 Channel 2 Channel 3 Figure 2. Control Register Control Register Definition One or several SCn/SDn downstream pairs, or channels, are selected by the contents of the control register (see Table 1). This register is written after the PCA9546A has been addressed. The four LSBs of the control byte are used to determine which channel or channels are to be selected. When a channel is selected, the channel becomes active after a stop condition has been placed on the I2C bus. This ensures that all SCn/SDn lines are in a high state when the channel is made active, so that no false conditions are generated at the time of connection. A stop condition always must occur right after the acknowledge cycle. 4 Submit Documentation Feedback PCA9546A 4-CHANNEL AND SMBus SWITCH WITH RESET FUNCTION I2C www.ti.com SCPS148D – OCTOBER 2005 – REVISED OCTOBER 2006 Table 1. Control Register Write (Channel Selection), Control Register Read (Channel Status) (1) (1) B7 B6 B5 B4 B3 B2 B1 X X X X X X X X X X X X X X X X X X X X X 0 0 0 0 0 X 1 0 0 Channel 0 disabled 1 Channel 0 enabled X X X X X 0 0 0 1 COMMAND Channel 1 disabled X 1 0 0 B0 Channel 1 enabled Channel 2 disabled Channel 2 enabled Channel 3 disabled Channel 3 enabled No channel selected, power-up/reset default state Several channels can be enabled at the same time. For example, B3 =0, B2 = 1, B1 = 1, B0 = 0 means that channels 0 and 3 are disabled, and channels 1 and 2 are enabled. Care should be taken not to exceed the maximum bus capacity. RESET Input The RESET input is an active-low signal that may be used to recover from a bus-fault condition. When this signal is asserted low for a minimum of tWL, the PCA9446A resets its registers and I2C state machine and deselects all channels. The RESET input must be connected to VCC through a pullup resistor. Power-On Reset When power is applied to VCC, an internal power-on reset holds the PCA9546A in a reset condition until VCC has reached VPOR. At this point, the reset condition is released, and the PCA9546A registers and I2C state machine are initialized to their default states, all zeroes, causing all the channels to be deselected. Thereafter, VCC must be lowered below 0.2 V to reset the device. Voltage Translation The pass-gate transistors of the PCA9546A are constructed such that the VCC voltage can be used to limit the maximum voltage that will be passed from one I2C bus to another. Figure 3 shows the voltage characteristics of the pass-gate transistors (note that the graph was generated using the data specified in the electrical characteristics section of this data sheet). In order for the PCA9546A to act as a voltage translator, the Vpass voltage must be equal to or lower than the lowest bus voltage. For example, if the main bus is running at 5 V, and the downstream buses are 3.3 V and 2.7 V, then Vpass must be equal to or below 2.7 V to effectively clamp the downstream bus voltages. As shown in Figure 3, Vpass (max) is at 2.7 V when the PCA9546A supply voltage is 3.5 V or lower, so the PCA9546A supply voltage could be set to 3.3 V. Pullup resistors then can be used to bring the bus voltages to their appropriate levels (see Figure 12). 5 4.5 Maximum Vpass (V) 4 Typical 3.5 3 2.5 2 Minimum 1.5 1 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 3. Vpass Voltage vs VCC Submit Documentation Feedback 5 PCA9546A 4-CHANNEL I2C AND SMBus SWITCH WITH RESET FUNCTION www.ti.com SCPS148D – OCTOBER 2005 – REVISED OCTOBER 2006 I2C Interface The I2C bus is for two-way two-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pullup resistor when connected to the output stages of a device. Data transfer can be initiated only when the bus is not busy. One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the high period of the clock pulse, as changes in the data line at this time are interpreted as control signals (see Figure 4). SDA SCL Data Line Stable; Data Valid Change of Data Allowed Figure 4. Bit Transfer Both data and clock lines remain high when the bus is not busy. A high-to-low transition of the data line while the clock is high is defined as the start condition (S). A low-to-high transition of the data line while the clock is high is defined as the stop condition (P) (see Figure 5). SDA SCL S P Start Condition Stop Condition Figure 5. Definition of Start and Stop Conditions A device generating a message is a transmitter; a device receiving is the receiver. The device that controls the message is the master, and the devices that are controlled by the master are the slaves (see Figure 6). SDA SCL Master Transmitter/ Receiver Slave Receiver Slave Transmitter/ Receiver Master Transmitter Master Transmitter/ Receiver Slave Figure 6. System Configuration 6 Submit Documentation Feedback I2C Multiplexer PCA9546A 4-CHANNEL AND SMBus SWITCH WITH RESET FUNCTION I2C www.ti.com SCPS148D – OCTOBER 2005 – REVISED OCTOBER 2006 The number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge (ACK) bit. The transmitter must release the SDA line before the receiver can send an ACK bit. When a slave receiver is addressed, it must generate an ACK after the reception of each byte. Also, a master must generate an ACK after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges must pull down the SDA line during the ACK clock pulse so that the SDA line is stable low during the high pulse of the ACK-related clock period (see Figure 7). Setup and hold times must be taken into account. Data Output by Transmitter NACK Data Output by Receiver ACK SCL From Master 1 2 8 9 S Start Condition Clock Pulse for ACK Figure 7. Acknowledgment on the I2C Bus Data is transmitted to the PCA9546A control register using the write mode shown in Figure 8. Slave Address SDA S 1 1 1 0 Control Register A2 A1 A0 Start Condition 0 A X X X X B3 B2 B1 B0 R/W ACK From Slave A ACK From Slave P Stop Condition Figure 8. Write Control Register Data is read from the PCA9546A control register using the read mode shown in Figure 9. Slave Address SDA S 1 Start Condition 1 1 0 Control Register A2 A1 A0 1 R/W A 0 0 0 0 ACK From Slave B3 B2 B1 B0 NA NACK From Master P Stop Condition Figure 9. Read Control Register Submit Documentation Feedback 7 PCA9546A 4-CHANNEL I2C AND SMBus SWITCH WITH RESET FUNCTION www.ti.com SCPS148D – OCTOBER 2005 – REVISED OCTOBER 2006 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC Supply voltage range –0.5 7 V VI Input voltage range (2) –0.5 7 V II Input current ±20 mA IO Output current ±25 mA ±100 mA ±100 mA Continuous current through VCC Continuous current through GND D package 73 DGV package θJA Package thermal impedance (3) UNIT 120 DW package 57 PW package 108 RGV package TBD RGY package 50 °C/W Ptot Total power dissipation 400 mW Tstg Storage temperature range –65 150 °C TA Operating free-air temperature range –40 85 °C (1) (2) (3) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. The package thermal impedance is calculated in accordance with JESD 51-7. Recommended Operating Conditions (1) VCC Supply voltage VIH High-level input voltage VIL Low-level input voltage TA Operating free-air temperature (1) 8 MIN MAX 2.3 5.5 SCL, SDA 0.7 × VCC 6 A2–A0, RESET 0.7 × VCC VCC + 0.5 SCL, SDA –0.5 0.3 × VCC A2–A0, RESET –0.5 0.3 × VCC –40 85 UNIT All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Submit Documentation Feedback V V V °C PCA9546A 4-CHANNEL AND SMBus SWITCH WITH RESET FUNCTION I2C www.ti.com SCPS148D – OCTOBER 2005 – REVISED OCTOBER 2006 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VPOR TEST CONDITIONS Power-on reset voltage (2) No load, VI = VCC or GND VCC MIN TYP (1) MAX VPOR 1.6 2.1 5V 4.5 V to 5.5 V Vpass Switch output voltage VSWin = VCC, ISWout = –100 µA IOL VOL = 0.4 V SCL, SDA 2.3 V to 5.5 V VOL = 0.6 V 4.5 1.9 1.6 2.5 V 2.3 V to 2.7 V 2.8 2 3 7 6 10 A2–A0 VI = VCC or GND ±1 2.3 V to 5.5 V ±1 fSCL = 100 kHz Low inputs VI = VCC or GND, VI = GND, IO = 0 IO = 0 Standby mode High inputs ∆ICC RESET Cio(OFF) (3) (1) (2) (3) SCL, SDA A2–A0 Ci RON Supply-current change µA ±1 RESET ICC mA ±1 SC3–SC0, SD3–SD0 Operating mode V 1.5 1.1 SCL, SDA II V 3.6 2.6 3.3 V 3 V to 3.6 V UNIT SCL, SDA SC3–SC0, SD3–SD0 Switch on-state resistance VI = VCC, IO = 0 5.5 V 3 12 3.6 V 3 11 2.7 V 3 10 5.5 V 0.3 1 3.6 V 0.1 1 2.7 V 0.1 1 5.5 V 0.3 1 3.6 V 0.1 1 2.7 V 0.1 1 8 15 8 15 SCL or SDA input at 0.6 V, Other inputs at VCC or GND µA SCL or SDA input at VCC – 0.6 V, Other inputs at VCC or GND 2.3 V to 5.5 V VI = VCC or GND 2.3 V to 5.5 V VI = VCC or GND, Switch OFF VO = 0.4 V, IO = 15 mA VO = 0.4 V, IO = 10 mA µA 2.3 V to 5.5 V 4.5 6 4.5 5.5 15 19 6 8 4.5 V to 5.5 V 4 9 16 3 V to 3.6 V 5 11 20 2.3 V to 2.7 V 7 16 45 pF pF Ω All typical values are at nominal supply voltage (2.5-V, 3.3-V, or 5-V VCC), TA = 25°C. The power-on reset circuit resets the I2C bus logic with VCC < VPOR. VCC must be lowered to 0.2 V to reset the device. Cio(ON) depends on internal capacitance and external capacitance added to the SCn lines when channels(s) are ON. Submit Documentation Feedback 9 PCA9546A 4-CHANNEL I2C AND SMBus SWITCH WITH RESET FUNCTION www.ti.com SCPS148D – OCTOBER 2005 – REVISED OCTOBER 2006 I2C Interface Timing Requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 10) STANDARD MODE I2C BUS MIN MAX 100 FAST MODE I2C BUS UNIT MIN MAX 0 400 fscl I2C clock frequency 0 tsch I2C clock high time 4 0.6 µs tscl I2C clock low time 4.7 1.3 µs tsp I2C tsds I2C serial-data setup time 250 100 ns tsdh I2C serial-data hold time 0 (1) 0 (1) µs ticr I2C input rise time ticf I2C tocf I2C output fall time tbuf I2C bus free time between stop and start 4.7 1.3 µs tsts I2C start or repeated start condition setup 4.7 0.6 µs tsth I2C start or repeated start condition hold 4 0.6 µs tsps I2C stop condition setup 4 0.6 µs spike time 50 input fall time 10-pF to 400-pF bus low) (3) tvdL(Data) Valid-data time (high to tvdH(Data) Valid-data time (low to high) (3) SCL low to SDA output high valid tvd(ack) Valid-data time of ACK condition ACK signal from SCL low to SDA output low Cb I2C bus capacitive load (1) (2) (3) SCL low to SDA output low valid kHz 50 ns 1000 20 + 0.1Cb (2) 300 ns 300 20 + 0.1Cb (2) 300 ns 300 20 + 0.1Cb (2) 300 ns 1 1 µs 0.6 0.6 µs 1 1 µs 400 400 pF A device internally must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH min of the SCL signal), in order to bridge the undefined region of the falling edge of SCL. Cb = total bus capacitance of one bus line in pF Data taken using a 1-kΩ pullup resistor and 50-pF load (see Figure 10) Switching Characteristics over recommended operating free-air temperature range, CL ≤ 100 pF (unless otherwise noted) (see Figure 10) PARAMETER tpd (1) (1) Propagation delay time RON = 20 Ω, CL = 15 pF RON = 20 Ω, CL = 50 pF FROM (INPUT) TO (OUTPUT) SDA or SCL SDn or SCn MIN MAX UNIT 0.3 ns 1 The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance). Interrupt and Reset Timing Requirements over recommended operating free-air temperature range (unless otherwise noted) PARAMETER tWL Pulse duration, RESET low trst (1) RESET time (SDA clear) tREC(STA) Recovery time from RESET to start (1) 10 MIN MAX UNIT 6 ns 500 0 trst is the propagation delay measured from the time the RESET pin is first asserted low to the time the SDA pin is asserted high, signaling a stop condition. It must be a minimum of tWL. Submit Documentation Feedback ns ns PCA9546A 4-CHANNEL AND SMBus SWITCH WITH RESET FUNCTION I2C www.ti.com SCPS148D – OCTOBER 2005 – REVISED OCTOBER 2006 PARAMETER MEASUREMENT INFORMATION VCC RL = 1 kΩ SDn, SCn DUT CL = 50 pF (See Note A) I2C PORT LOAD CONFIGURATION Two Bytes for Complete Device Programming Address Start Stop Address Bit 7 Condition Condition Bit 6 (MSB) (S) (P) BYTE DESCRIPTION 1 I2C address + R/W 2 Control register data Address Bit 1 tscl R/W Bit 0 (LSB) ACK (A) Data Bit 7 (MSB) Data Bit 0 (LSB) ACK (A) Stop Condition (P) tsch 0.7 × VCC SCL tvd(ACK) or tvdL tvdH ticr ticf tbuf tsp 0.3 × VCC tsts 0.7 × VCC SDA 0.3 × VCC ticr ticf tsth tsdh tsds tsps Repeat Start Condition Start or Repeat Start Condition Stop Condition VOLTAGE WAVEFORMS A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns. C. The outputs are measured one at a time, with one transition per measurement. Figure 10. I2C Interface Load Circuit, Byte Descriptions, and Voltage Waveforms Submit Documentation Feedback 11 PCA9546A 4-CHANNEL I2C AND SMBus SWITCH WITH RESET FUNCTION www.ti.com SCPS148D – OCTOBER 2005 – REVISED OCTOBER 2006 PARAMETER MEASUREMENT INFORMATION (continued) Start ACK or Read Cycle SCL SDA 30% trst 50% RESET tREC tWL trst 50% LEDx LED OFF Figure 11. Reset Timing 12 Submit Documentation Feedback PCA9546A 4-CHANNEL AND SMBus SWITCH WITH RESET FUNCTION I2C www.ti.com SCPS148D – OCTOBER 2005 – REVISED OCTOBER 2006 APPLICATION INFORMATION Figure 12 shows an application in which the PCA9546A can be used. VCC = 2.7 V to 5.5 V VCC = 3.3 V VCC = 2.7 V to 5.5 V 16 I2C/SMBus Master SDA SCL 15 14 3 See Note A SDA SD0 SCL SC0 4 Channel 0 5 VCC = 2.7 V to 5.5 V RESET See Note A SD1 6 SC1 7 Channel 1 VCC = 2.7 V to 5.5 V PCA9546A See Note A SD2 SC2 13 2 1 8 A. 9 Channel 2 10 VCC = 2.7 V to 5.5 V A2 See Note A A1 A0 SD3 GND SC3 11 12 Channel 3 Pin numbers shown are for the D, DGV, DW, PW, and RGY packages. Figure 12. Typical Application Submit Documentation Feedback 13 PACKAGE OPTION ADDENDUM www.ti.com 30-Jan-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing PCA9546AD ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCA9546ADG4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCA9546ADGVR ACTIVE TVSOP DGV 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCA9546ADGVT PREVIEW TVSOP DGV 20 250 PCA9546ADR ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCA9546ADRG4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCA9546ADT ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCA9546ADTG4 ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCA9546ADW ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCA9546ADWR ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCA9546ADWT PREVIEW PCA9546AGQNR PREVIEW PCA9546APW ACTIVE PCA9546APWE4 SOIC Pins Package Eco Plan (2) Qty TBD Lead/Ball Finish Call TI MSL Peak Temp (3) Call TI DW 16 250 TBD Call TI Call TI GQN 20 1000 TBD Call TI Call TI TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCA9546APWR ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCA9546APWRE4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCA9546APWT ACTIVE TSSOP PW 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCA9546APWTE4 ACTIVE TSSOP PW 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCA9546ARGVR ACTIVE QFN RGV 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1YEAR PCA9546ARGYR ACTIVE QFN RGY 16 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1YEAR PCA9546ARGYRG4 ACTIVE QFN RGY 16 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1YEAR PCA9546AZQNR PREVIEW ZQN 20 1000 BGA MI CROSTA R JUNI OR BGA MI CROSTA R JUNI OR (1) TBD Call TI Call TI The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 30-Jan-2007 a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0°–8° 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. Falls within JEDEC: 24/48 Pins – MO-153 14/16/20/56 Pins – MO-194 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. 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