SPECIFICATIONS FOR LCD MODULE CUSTOMER CUSTOMER PART NO. PACER DISPLAY NO. PCM0802C` DESCRIPTION APPROVED BY DATE PREPARED BY Copyright © 2006 Pacer PLC CHECKED BY PAGE 1 OF 22 APPROVED BY DOCUMENT REVISION HISTORY: DATE PAGE 1999.8. 2005.3. .12 4 Copyright © 2006 Pacer PLC DESCRIPTION First release Modify the full specification Update the part number system PAGE 2 OF 22 1. Module Classification Information 2. Precautions in use of LCD Modules 3. General Specification 4. Absolute Maximum Ratings 5. Electrical Characteristics 6. Optical Characteristics 7. Interface Pin Function 8. Power Supply 9. Contour Drawing & Block Diagram 10. Function Description 11. Character Generator ROM Pattern 12. Instruction Table 13. Timing Characteristics 14. Initializing of LCM 15. Quality Assurance 16. Reliability Copyright © 2006 Pacer PLC PAGE 3 OF 22 1 2 3 5 4 6 7 8 9 10 11 12 1 Brand PACER DISPLAY 2 Display Type CM Character Type, GM Graphic Type, NONE Custom-made 3 Display Font Characters X Lines / Rows X Columns /Others 4 Model serials no. 5 RoHS compliant: R YES NONE NO M SMT Type 6 IC Package Type 7 LCD Mode 8 Viewing direction 9 Temperature range 10 LCD Polarizer Type 11 Backlight Type 12 Backlight Color 13 Internal Code Copyright © 2006 Pacer PLC B T G F S P N Y B G W T F S 6 N W S R T F S N D E F S Y B A W G R S COB Type TAB Type COG Type COF Type Special TN Positive TN Negative STN Positive, Yellow Green STN Negative, Blue STN Positive, Gray FSTN Positive FSTN Negative FFSTN Negative Special 6:00,12 12:00, S Special Normal Temperature Wide Temperature Special Reflective Transmissive Transflective Special None LED EL CCFL Special Yellow-green Blue Amber White Green Red Special PAGE 4 OF 22 13 ! (1)Avoid applying excessive shocks to the module or making any alterations or modifications to it. (2)Don’t make extra holes on the printed circuit board, modify its shape or change the components of LCD module. (3)Don’t disassemble the LCM. (4)Don’t operate it above the absolute maximum rating. (5)Don’t drop, bend or twist LCM. (6)Soldering: only to the I/O terminals. (7)Storage: please storage in anti-static electricity container and clean environment. " # $ Item Dimension Number of Characters Unit 8 characters x 2 Lines Module dimension(No Backlight ) 79.0 x 44.0 x 10.0 MAX mm Module dimension(With LED Backlight ) 79.0 x 44.0 x 14.0 MAX mm View area 63.0 x 25.0 mm Active area 57.17 x 23.00 mm Dot size 1.15 x 1.36 mm Dot pitch 1.23 x 1.44 mm Character size 6.07 x 11.44 mm Character pitch 7.30 x 11.56 mm LCD type STN Duty 1/16 View direction 6 o’clock or 12 o’clock Backlight Type None, YELLOW-GREEN Copyright © 2006 Pacer PLC PAGE 5 OF 22 % & ' ( Item Symbol Min Max Unit VI -0.3 VDD+0.3 V Supply Voltage For Logic VDD-VSS -0.3 7.0 V Supply Voltage For LCD VDD-V0 Vdd-13.5 0 V Input Voltage Standard Operating Temp. Top 0 50 Temperature LCM Storage Temp. Tstr -10 60 Wide Temperature Operating Temp. Top -20 70 LCM Storage Temp. Tstr -30 80 ) * + Item Symbol Supply Voltage For Logic VDD-VSS Supply Voltage For LCD VDD-V0 Condition Ta=25 Min Typ Max Unit 4.5 5.0 5.5 V 4.5 4.8 5.5 V Input High Volt. VIH 0.7 VDD VDD V Input Low Volt. VIL VSS 0.3 VDD V Supply Current IDD Supply Voltage of Yellow-green backlight Copyright © 2006 Pacer PLC VLED VDD=5V Forward current =150 mA Number of LED die 2x15= 30 PAGE 6 OF 22 0.8 1.2 2.0 mA 3.8 4.1 4.3 V ,$ + Item View Angle Symbol Condition Min (V) CR 2 (H) CR 2 Max Unit -20 35 deg -30 30 deg T rise 250 ms T fall 250 ms Contrast Ratio Typ CR Response Time 3 Definition of Operation Voltage (Vop) Definition of Response Time ( Tr , Tf ) Non-selected Conition Selected Wave Intensity 100 Non-selected Wave Non-selected Conition Selected Conition Intensity 10 Cr Max Cr = Lon / Loff Vop 100 90 Tr Driving Voltage(V) [positive type] Tf [positive type] Conditions : Operating Voltage : Vop Viewing Angle( Frame Frequency : 64 HZ Driving Waveform : 1/N duty , 1/a bias Definition of viewing angle(CR 2) Copyright © 2006 Pacer PLC PAGE 7 OF 22 ) : 0° 0° f l = 270 b = 180 r = 90 =0 - . Pin No. Symbol Level Description 1 VSS 0V Ground 2 VDD 5.0V 3 V0 4 RS H/L H: DATA, L: Instruction code 5 R/W H/L H: Read(MPU 6 E 7 DB0 H/L Data bit 0 8 DB1 H/L Data bit 1 9 DB2 H/L Data bit 2 10 DB3 H/L Data bit 3 11 DB4 H/L Data bit 4 12 DB5 H/L Data bit 5 13 DB6 H/L Data bit 6 14 DB7 H/L Data bit 7 15 LED(+) Anode of LED Backlight 16 LED(-) Cathode of LED Backlight Supply Voltage for logic (Variable) Operating voltage for LCD Copyright © 2006 Pacer PLC H,H L Module) L: Write(MPU Module) Chip enable signal PAGE 8 OF 22 / , * 0 !1 SINGLE SUPPLY VOLTAGE TYPE DUAL SUPPLY VOLTAGE TYPE Copyright © 2006 Pacer PLC PAGE 9 OF 22 5 ( 3.0 79.0 75.0 63.0[V.A.] 57.17[A.A.] NO B/L 10.0[MAX.] 5.0¡ À 0.5 2-R1.25 C L C L 76.0 84.0¡ À 0.5 8 8 1.6¡ À 0.1 1.6¡ À 0.1 40 *S6A0069 OR EQUIVALENT Copyright © 2006 Pacer PLC 14.0[MAX.] 9.0¡ À 0.5 7.30 6.07 1.15 LCD PANEL 8X2 CHARACTERS 8 LED B/L 11.56 11.44 1.36 CONTROLLER* Vdd V0 Vss E R/W RS 4.0 4.0 16- 1.0 P2.54X(16-1)=38.1 2.5 44.0¡ À 0.5 34.5 25.0[V.A.] 23.0[A.A.] C L 2- 2.5 10.2 DB0 DB7 (4 0.08 3 36.0 2 0.08 PAGE 10 OF 22 . $ The LCD display Module is built in a LSI controller, the controller has two 8-bit registers, an instruction register (IR) and a data register (DR). The IR stores instruction codes, such as display clear and cursor shift, and address information for display data RAM (DDRAM) and character generator (CGRAM). The IR can only be written from the MPU. The DR temporarily stores data to be written or read from DDRAM or CGRAM. When address information is written into the IR, then data is stored into the DR from DDRAM or CGRAM. By the register selector (RS) signal, these two registers can be selected. RS R/W 0 0 IR write as an internal operation (display clear, etc.) 0 1 Read busy flag (DB7) and address counter (DB0 to DB7) 1 0 Write data to DDRAM or CGRAM (DR to DDRAM or CGRAM) 1 1 Read data from DDRAM or CGRAM (DDRAM or CGRAM to DR) Operation Busy Flag (BF) When the busy flag is 1, the controller LSI is in the internal operation mode, and the next instruction will not be accepted. When RS=0 and R/W=1, the busy flag is output to DB7. next instruction must be written after ensuring that the busy flag is 0. The Address Counter (AC) The address counter (AC) assigns addresses to both DDRAM and CGRAM Display Data RAM (DDRAM) This DDRAM is used to store the display data represented in 8-bit character codes. Its extended capacity is 80×8 bits or 80 characters. Below figure is the relationships between DDRAM addresses and positions on the liquid crystal display. High bits Low bits Example: DDRAM addresses 4E AC (hexadecimal) AC6 AC5 AC4 AC3 AC2 AC1 AC0 Copyright © 2006 Pacer PLC PAGE 11 OF 22 1 0 0 1 1 1 0 Display position DDRAM address 1 2 3 4 5 6 00 01 02 03 04 05 08 09 10 11 12 13 7 8 06 07 14 15 -Line by 8 -Character Display Character Generator ROM (CGROM) The CGROM generate 5×8 dot or 5×10 dot character patterns from 8-bit character codes. See Table 2. Character Generator RAM (CGRAM) In CGRAM, the user can rewrite character by program. For 5×8 dots, eight character patterns can be written, and for 5×10 dots, four character patterns can be written. Write into DDRAM the character code at the addresses shown as the left column of table 1. To show the character patterns stored in CGRAM. Copyright © 2006 Pacer PLC PAGE 12 OF 22 Relationship between CGRAM Addresses, Character Codes (DDRAM) and Character patterns Table 1. F o r 5 * 8 d o t c h a ra c te r p a tte r n s C h a ra c te r C o d e s ( D D R A M d a ta ) 7 6 5 4 3 H ig h 0 0 0 0 0 0 0 0 0 2 1 0 Low 0 0 0 * 0 * 0 * 1 0 0 1 C h a r a c te r P a tte r n s ( C G R A M d a ta ) C G R A M A d d re ss 5 4 3 2 1 0 7 Low 0 0 0 0 0 1 0 1 0 0 0 1 0 1 0 1 1 1 1 0 0 0 0 0 1 0 1 1 0 0 0 1 1 0 1 1 1 1 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 * * * * * * * * * * * * * * * * * H ig h 0 1 1 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 * 6 5 H ig h * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 4 3 2 1 0 Low 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C h a r a c te r p a tte r n ( 1 ) 0 0 0 0 0 0 0 C u r s o r p a tte r n 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C h a r a c te r p a tte r n ( 2 ) C u r s o r p a tte r n * F o r 5 * 1 0 d o t c h a r a c te r p a tte rn s C h a ra c te r C o d e s ( D D R A M d a ta ) 7 6 5 4 H ig h 0 0 0 3 2 1 0 Low 0 * 0 0 C h a r a c te r P a tte r n s ( C G R A M d a ta ) C G R A M A d d re ss 5 4 3 H ig h 0 0 2 1 0 7 Low 0 6 5 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Low 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 * * * * * * * * * * * * * * * * * * * * * * * 0 * 0 * * * * * * * * * 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 * * * * * * * : " H ig h " Copyright © 2006 Pacer PLC 4 H ig h PAGE 13 OF 22 * C h a r a c te r p a tte r n C u r s o r p a tte r n + # , Table.2 Copyright © 2006 Pacer PLC PAGE 14 OF 22 & Instruction Code Instruction Execution time (fosc=270Khz) Description RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Clear Display 0 0 0 0 0 0 0 0 0 1 Return Home 0 0 0 0 0 0 0 0 1 Entry Mode Set 0 0 0 0 0 0 0 1 I/D SH Display ON/OFF Control 0 0 0 0 0 0 1 D C B Cursor or Display Shift 0 0 0 0 0 1 Function Set Set CGRAM Address Set DDRAM Address Write “00H” to DDRAM and set DDRAM address to “00H” from AC 1.53ms Set DDRAM address to “00H” from AC and return cursor to its original position if shifted. The contents of DDRAM are not changed. 1.53ms Assign cursor moving direction and enable the shift of entire display. 39 s Set display (D), cursor (C), and blinking of cursor (B) on/off control bit. 39 s Set cursor moving and display shift control bit, and the direction, without changing of DDRAM data. 39 s Set interface data length (DL:8-bit/4-bit), numbers of display line (N:2-line/1-line)and, display font type (F:5×11 dots/5×8 dots) 39 s AC5 AC4 AC3 AC2 AC1 AC0 Set CGRAM address in address counter. 39 s 1 DL S/C R/L 0 0 0 0 N F 0 0 0 1 0 0 1 AC6 AC5 AC4 AC3 AC2 AC1 AC0 Set DDRAM address in address counter. 39 s Whether during internal operation or not can be known by reading BF. The AC6 AC5 AC4 AC3 AC2 AC1 AC0 contents of address counter can also be read. 0 s Read Busy Flag and Address 0 1 BF Write Data to RAM 1 0 D7 D6 D5 D4 D3 D2 D1 D0 Write data into internal RAM (DDRAM/CGRAM). 43 s Read Data from RAM 1 1 D7 D6 D5 D4 D3 D2 D1 D0 Read data from internal RAM (DDRAM/CGRAM). 43 s ” Copyright © 2006 Pacer PLC PAGE 15 OF 22 ” don’t care " ( 13.1 + Write Operation RS VIH1 VIH1 VIL1 VIL1 tAS R/W tAH VIL1 PWEH VIH1 E VIH1 VIL1 tEr tDSW VIL1 VIL1 tH VIH1 DB0 to DB7 VIL1 tAH tEf VIH1 Valid data VIL1 VIL1 tcycE Ta=25 , VDD=5.0± 0.5V Item Symbol Min tcycE 1200 ns Enable pulse width (high level) PWEH 140 ns Enable rise/fall time tEr,tEf Enable cycle time Typ Max 25 Unit ns Address set-up time (RS, R/W to E) tAS 0 ns Address hold time tAH 10 ns Data set-up time tDSW 40 ns tH 10 ns Data hold time Copyright © 2006 Pacer PLC PAGE 16 OF 22 13.2 Read Operation RS VIH1 VIH1 VIL1 tAS tAH VIL1 VIH1 R/W VIH1 PWEH VIH1 E VIH1 VIL1 tEr VIL1 VOL1* VIL1 tDHR tDDR VOH1 DB0 to DB7 tAH tEf VOH1 Valid data *VOL1 tcycE NOTE: *VOL1 is assumed to be 0.8V at 2 MHZ operation. Ta=25 , VDD=5.0± 0.5V Item Symbol Min tcycE 1200 ns Enable pulse width (high level) PWEH 140 ns Enable rise/fall time tEr,tEf Enable cycle time Typ Max 25 Unit ns Address set-up time (RS, R/W to E) tAS 0 ns Address hold time tAH 10 ns Data delay time tDDR Data hold time tDHR Copyright © 2006 Pacer PLC PAGE 100 10 17 OF 22 ns ns 13.3 Timing Diagram of VDD Against V0. Power on sequence shall meet the requirement of Figure 4, the timing diagram of VDD against V0. VDD 95% LOGIC SUPPLY VOLTAGE V0 0V 50ms(typical) 0V LCD SUPPLY VOLTAGE Copyright © 2006 Pacer PLC PAGE 18 OF 22 % 6 ( ! Power on Wait for more than 40 ms after VDD rises to 4.5 V BF can not be checked before this instruction. RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Function set 0 0 0 0 1 1 * * * * Wait for more than 39us RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 0 * * * * 0 0 N F * * * * * * BF can not be checked before this instruction. Function set Wait for more than 39 µs BF can not be checked before this instruction. RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 0 * * * * Function set 0 0 N F * * * * * * Wait for more than 37us RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Display ON/OFF control 0 0 0 0 0 0 * * * * 0 0 1 D C B * * * * Wait for more than 37 µs RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Display Clear 0 0 0 0 0 0 * * * * * * * * 0 0 0 0 0 1 Wait for more than 1.53ms RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Entry Mode Set 0 0 0 0 0 0 * * * * 1 I/D SH * * * * 0 0 0 Initialization ends 4-Bit Ineterface Copyright © 2006 Pacer PLC PAGE 19 OF 22 Power on Wait for more than 40 ms after VDDrises to 4.5 V BF can not be checked before this instruction. RS R/WDB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Function set 0 0 0 0 1 1 N F * * Wait for more than 39us RS R/WDB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 1 N F * * BF can not be checked before this instruction. Function set Wait for more than 37us RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Display ON/OFF control 0 0 0 0 0 0 1 B C D Wait for more than 37 µs RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Display Clear 0 0 0 0 0 0 0 0 0 1 Wait for more than 1.53ms RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Entry Mode Set 0 0 0 0 0 0 0 1 I/D S Initialization ends 8-Bit Ineterface Copyright © 2006 Pacer PLC PAGE 20 OF 22 )7 8 Screen Cosmetic Criteria Item Defect 1 Spots 2 Bubbles in Polarizer 3 Scratch 4 Allowable Density 5 Coloration Copyright © 2006 Pacer PLC Judgment Criterion A)Clear Size: d mm Acceptable Qty in active area d 0.1 Disregard 0.1<d 0.2 6 0.2<d 0.3 2 0.3<d 0 Note: Including pin holes and defective dots which must be within one pixel size. B)Unclear Size: d mm Acceptable Qty in active area d 0.2 Disregard 0.2<d 0.5 6 0.5<d 0.7 2 0.7<d 0 Size: d mm Acceptable Qty in active area d 0.3 Disregard 3 0.3<d 1.0 1.0<d 1.5 1 1.5<d 0 In accordance with spots cosmetic criteria. When the light reflects on the panel surface, the scratches are not to be remarkable. Above defects should be separated more than 30mm each other. Not to be noticeable coloration in the viewing area of the LCD panels. Back-light type should be judged with back-light on state only. PAGE 21 OF 22 Partition Minor Minor Minor Minor Minor & 8 Content of Reliability Test Environmental Test Test Item High Temperature storage Low Temperature storage High Temperature Operation Low Temperature Operation High Temperature/ Humidity Storage High Temperature/ Humidity Operation Temperature Cycle Content of Test Test Condition Applicable Standard Endurance test applying the high storage temperature for a long time. 60 96hrs —— Endurance test applying the high storage temperature for a long time. -10 96hrs —— Endurance test applying the electric stress (Voltage & Current) and the thermal stress to the element for a long time. 50 96hrs —— Endurance test applying the electric stress under low temperature for a long time. 0 96hrs —— Endurance test applying the high 60 ,90%RH temperature and high humidity storage for a 96hrs long time. Endurance test applying the electric stress (Voltage & Current) and temperature / humidity stress to the element for a long time. Endurance test applying the low and high temperature cycle. -10 25 60 30min 5min 1 cycle 30min —— 50 ,90%RH 96hrs —— -10 /60 10 cycles —— Mechanical Test Vibration test Endurance test applying the vibration during transportation and using. Shock test Constructional and mechanical endurance test applying the shock during transportation. 10~22Hz 1.5mmp-p 22~500Hz 1.5G Total 0.5hrs 50G Half sign wave 11 msedc 3 times of each direction —— —— ***Supply voltage for logic system=5V. Supply voltage for LCD system =Operating voltage at 25 Copyright © 2006 Pacer PLC PAGE 22 OF 22