PCM5310 PC M5 310 Burr-Brown Audio www.ti.com ............................................................................................................................................................................................ SLES244 – FEBRUARY 2009 24-Bit, 96-/192-kHz, Asynchronous, 4-Channel/4-Channel Audio Codec with 2-VRMS Driver, Headphone Driver, and 6 Audio Interface Ports FEATURES 1 • 2- or 2.4-VRMS Output (Typ), 2-VRMS Input (Typ) • Asynchronous Operation for 2 Stereo DACs and 2 Stereo ADCs • 6 Audio Interface Ports with Mux and Bypass • Performance: – THD+N (fS = 48 kHz): 0.01% (ADC), 0.01% (DAC) – SNR/DR (fS = 48 kHz): 95 dB (ADC), 100 dB (DAC) – Line Input (Stereo x6): Available for 2-VRMS Input – Line Output (Stereo x2): Available for 2-VRMS or 2.4-VRMS Output – Headphone Output: > 20 mW into 32 Ω, > 30 mW into 16 Ω – Sampling Rate: 96 kHz (ADC), 192 kHz (DAC) – System Clock: 128 fS, 192 fS, 256 fS, 384 fS, 512 fS, 768 fS – Digital Filter Passband Ripple: ±0.05 dB (ADC), ±0.04 dB (DAC) – Digital Filter Stop Band Attenuation: –65 dB (ADC), –50 dB (DAC) 2 • I C™ Interface • Multifunctions: – Audio Interface: I2S™, Left-Justified, and Right-Justified – Digital Attenuation: 0 dB to –100 dB in 0.5-dB Steps (DAC), 20 dB to –100 dB in 0.5-dB Steps (ADC) – Digital Soft Mute: 1.0-dB Steps to Mute – Digital De-Emphasis Filter: 32, 44.1, 48 kHz – Digital Audio Interface Mux and Bypass – Line Input Level Control: 9, 6, 3, 0 dB – Line Output Level Control: 0, –0.5, –1.0 dB – Headphone Output Volume Control: 12 dB to –70 dB in 1-dB Steps – Oversampling Rate Control for DAC • 234 • • • • • • Power-Supply Voltage: – 9 V for 2-VRMS Driver – 3.3 V for Digital and Analog Power Consumption: – 360 mW at fS = 48-kHz Operation – 25.5 µW in Power-Down Mode Pop Noise Reduction at Clock Halt Short-Circuit Protection for Headphone Output Flexible GPIO Port: – Internal Mute Flag – Internal Zero Flag – Headphone Insertion Detection Status – Headphone Short-Circuit Protection Status – Logic Functions (AND, NAND, OR, NOR, BUF, INV) Package: 64-Pin HTQFP PowerPAD™ Operating Temperature Range:–25°C to +85°C APPLICATIONS • • • Digital TV DVD Recorder IP-STB (Set Top Box) DESCRIPTION The PCM5310 is a four-channel/four-channel audio codec with a 2-VRMS driver, headphone amplifier, analog multiplexer (mux), and six audio interface ports for digital TV applications. The PCM5310 accepts left-justified, right-justified, and I2S audio data formats with 16 or 24 bits. The PCM5310 also incorporates many functions through the I2C interface, such as an analog bypass mode, analog volume control, analog level control, analog multiplexer, GPIO, zero flag, short protection, de-emphasis filter, high-pass filter, and digital attenuator. The six audio interface ports each have a built-in digital mux and bypass functions to reduce the need for additional DSP ports or other devices. 1 2 3 4 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. I2C, I2S are trademarks of NXP Semiconductors. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2009, Texas Instruments Incorporated PCM5310 SLES244 – FEBRUARY 2009 ............................................................................................................................................................................................ www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGING/ORDERING INFORMATION For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) Over operating free-air temperature range (unless otherwise noted). PARAMETER Supply voltage PCM5310 UNIT VCCDA, VCCAD, VCCP, VDD –0.3 to 4.0 V VCCH –0.3 to 10 V ±0.1 V –0.3 to 4.0 V Ground voltage differences: AGNDAD, AGNDDA, PGND, HGND, DGND Input voltage Input current (all pins except supplies) ±10 mA Ambient temperature under bias –40 to +125 °C Storage temperature –55 to +150 °C Junction temperature +150 °C Lead temperature (soldering, 5s) +260 °C Package temperature (IR reflow, peak) +260 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Over operating free-air temperature range (unless otherwise noted). PARAMETER Analog supply voltage, VCCAD, VCCDA, VCCP Analog supply voltage, VCCH Digital supply voltage, VDD MIN NOM MAX 3.0 3.3 3.6 V 8.55 9 9.45 V 3.0 3.3 3.6 Analog input voltage, full-scale (–0 dB) 2 Analog output voltage, full-scale (–0 dB) 2 VRMS 4.096 36.864 MHz 32 96 kHz 4.096 36.864 MHz 32 192 kHz CMOS ADC system clock ADC sampling clock DAC system clock DAC sampling clock Analog output load resistance 10 Analog output load capacitance kΩ 30 Digital output load capacitance pF 10 Operating free-air temperature, TA 2 V VRMS 2.4 Digital input logic family Digital input clock frequency UNIT –25 Submit Documentation Feedback pF +85 °C Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM5310 PCM5310 www.ti.com ............................................................................................................................................................................................ SLES244 – FEBRUARY 2009 ELECTRICAL CHARACTERISTICS All specifications at TA = +25°C, VDD = VCCAD = VCCDA = VCCP = 3.3 V, VCCH = 9 V, fS (1) = 48 kHz, system clock = 256 fS, and 24-bit data, unless otherwise noted. PCM5310 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT AUDIO DATA Data Format Audio data bit length 16, 24 Audio data format Sampling frequency System clock Bit clock Bits I2S, left-justified, right-justified Audio data interface format MSB, twos complement ADC 108 DAC 216 kHz kHz ADC 256 fS, 384 fS, 512 fS, 768 fS MHz DAC 128 fS, 192 fS, 256 fS, 384 fS, 512 fS, 768 fS MHz ADC 48 fS, 64 fS MHz DAC 32 fS, 48 fS, 64 fS MHz DIGITAL INPUT/OUTPUT Logic family CMOS-compatible VIH Input logic high level 0.7 VDD VIL Input logic low level IIH IIL VOH Output logic high level IOH = 2 mA VOL Output logic low level IOH = –2 mA V 0.3 VDD V Input logic high current 10 µA Input logic low current –10 µA 0.75 VDD V 0.25 VDD V DAC LINE OUTPUT Dynamic Performance Full-scale output voltage SNR Digital input = 0 dB, G242, G241 = low 2 VRMS Digital input = 0 dB, G242, G241 = high 2.4 VRMS Dynamic range EIAJ, A-weighted 90 100 dB Signal-to-noise ratio EIAJ, A-weighted 90 100 dB 88 97 dB Channel separation THD+N Total harmonic distortion + noise Digital input = 0 dB, G242, G241 = low Load resistance AC load 0.01 0.02 % 10 kΩ DC Accuracy Gain error Digital input = 0 dB, G242, G241 = low Gain mismatch, channel-to-channel ±3 ±13 % of FSR ±3 ±13 % of FSR ±120 mV Bipolar zero error Zero data input ±40 Center voltage Zero data input 0.5 VCCDA V 0, –0.5, –1.0 dB ±0.5 dB Analog Gain Control Gain range Gain error (1) fS = sampling rate. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM5310 3 PCM5310 SLES244 – FEBRUARY 2009 ............................................................................................................................................................................................ www.ti.com ELECTRICAL CHARACTERISTICS (continued) All specifications at TA = +25°C, VDD = VCCAD = VCCDA = VCCP = 3.3 V, VCCH = 9 V, fS = 48 kHz, system clock = 256 fS, and 24-bit data, unless otherwise noted. PCM5310 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DAC HEADPHONE OUTPUT Dynamic Performance SNR THD+N Full-scale output voltage Digital input = 0 dB, VOL = 0dB 1 VRMS Dynamic range EIAJ, A-weighted 85 96 dB Signal-to-noise ratio EIAJ, A-weighted 85 96 dB Channel separation RL = 32 Ω 88 RL = 32 Ω, VOL = 0 dB 0.1 0.18 % RL = 16 Ω, VOL = 0 dB 1 3 % Total harmonic distortion + noise Load resistance dB Ω 16 DC Accuracy Gain error Digital input = 0 dB, VOL = 0dB Gain mismatch, channel-to-channel ±3 ±13 % of FSR ±3 ±13 % of FSR ±80 mV Bipolar zero error Zero data input ±27 Center voltage Zero data input 0.5 VCCDA V Analog Volume Gain range –70 12 dB Gain error 0.5 dB Gain step 1.0 dB ADC LINE INPUT Dynamic Performance SNR Full-scale input voltage Digital input = 0 dB, VOL = 0dB Dynamic range EIAJ, A-weighted Signal-to-noise ratio EIAJ, A-weighted 2 VRMS 85 95 dB 85 95 dB 93 dB Channel separation THD+N Total harmonic distortion + noise Analog input = –1 dB, VOL = 0dB 0.01 0.018 % ±3 ±13 % of FSR ±3 ±13 % of FSR ±50 mV DC Accuracy Gain error Analog input = 0 dB, VOL = 0dB Gain mismatch, channel-to-channel Bipolar zero error Zero data input ±17 Center voltage Zero data input 0.5 VCCAD V Analog Input Input impedance 37.6 47 56.4 kΩ Analog Gain Control Gain range Gain error 4 Submit Documentation Feedback 9, 6, 3, 0 dB ±0.5 dB Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM5310 PCM5310 www.ti.com ............................................................................................................................................................................................ SLES244 – FEBRUARY 2009 ELECTRICAL CHARACTERISTICS (continued) All specifications at TA = +25°C, VDD = VCCAD = VCCDA = VCCP = 3.3 V, VCCH = 9 V, fS = 48 kHz, system clock = 256 fS, and 24-bit data, unless otherwise noted. PCM5310 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG INPUT TO ANALOG OUTPUT PATH (BYPASS) Dynamic Performance SNR Full-scale input voltage Analog input = 0 dB, VOL = 0dB 2 VRMS Full-scale output voltage Analog input = 0 dB, G242, G241 = low 2 VRMS Dynamic range EIAJ, A-weighted 90 100 dB Signal-to-noise ratio EIAJ, A-weighted 90 100 dB 88 97 dB Channel separation THD+N Analog input = 0 dB, G242, G241 = low 0.003 0.006 Analog input = 0 dB, G242, G241 = low ±3 ±13 % of FSR 3 ±13 % of FSR Zero data input ±20 ±60 mV analog input Zero data input 0.5 VCCAD V analog output Zero data input 0.5 VCCDA V Total harmonic distortion + noise % DC Accuracy Gain error Gain mismatch, channel-to-channel Bipolar zero error Center voltage Analog Input Input impedance 37.6 47 56.4 kΩ 0.454 fS kHz FILTERS Interpolation Filters for DAC Passband Stop band 0.546 fS kHz Passband ripple ±0.04 Stop-band attenuation –50 dB dB Group delay 20/fS s De-emphasis error ±0.1 dB Analog Filter for DAC Frequency response fC = 20 kHz ±0.1 dB Cutoff frequency Gain = –3 dB 190 kHz Decimation Filter for ADC Passband 0.454 fS Stop band 0.583 fS kHz Passband ripple ±0.05 Stop-band attenuation –65 Group delay kHz dB dB 17.4/fS s ±0.01 dB Analog Filter for ADC Frequency response fC = 20 kHz Cutoff frequency Gain = –3 dB 500 kHz Gain = –3 dB 0.91 Hz High-Pass Filter for ADC Frequency response Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM5310 5 PCM5310 SLES244 – FEBRUARY 2009 ............................................................................................................................................................................................ www.ti.com ELECTRICAL CHARACTERISTICS (continued) All specifications at TA = +25°C, VDD = VCCAD = VCCDA = VCCP = 3.3 V, VCCH = 9 V, fS = 48 kHz, system clock = 256 fS, and 24-bit data, unless otherwise noted. PCM5310 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER-SUPPLY REQUIREMENTS VDD Digital voltage range 3 3.3 3.6 V VCCAD DAC voltage range 3 3.3 3.6 V VCCDA ADC voltage range 3 3.3 3.6 V VCCP Headphone driver voltage range 3 3.3 3.6 V VCCH 2-VRMS driver voltage range Supply current Power dissipation 8.55 9 9.45 V 98 120 mA 6 100 µA Zaro data input, all active 360 450 mW All power-down 25.5 350 µW +85 °C Zero data input, all active All power-down TEMPERATURE RANGE Operating temperature range θJA 6 Thermal resistance –25 HTQFP-64 Submit Documentation Feedback 21 °C/W Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM5310 PCM5310 www.ti.com ............................................................................................................................................................................................ SLES244 – FEBRUARY 2009 PIN ASSIGNMENTS VCOMAD VREFAD2 VREFAD1 AGNDAD VCCAD AMUTE RSTB GPIO3 GPIO2 GPIO1 DATA6 LRCK6 BCK6 SCK6 DATA5 LRCK5 PAP PACKAGE HTQFP-64 (TOP VIEW) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 AIN1L 1 48 BCK5 AIN1R 2 47 SCK5 AIN2L 3 46 DATA4 AIN2R 4 45 LRCK4 AIN3L 5 44 BCK4 AIN3R 6 43 SCK4 AIN4L 7 42 DGND AIN4R 8 AIN5L 9 PCM5310 PowerPAD 41 VDD 40 DATA3 19 20 21 22 23 24 25 26 27 28 29 30 31 32 DATA1 18 HPOR 17 LRCK1 33 SCK2 BCK1 LO2R 16 SCK1 34 BCK2 SCL LO2L 15 SDA 35 LRCK2 AGNDS LO1R 14 VCOMDA 36 DATA2 VCCDA LO1L 13 AGNDDA 37 SCK3 PGND AIN6R 12 VCCP 38 BCK3 HPOL AIN6L 11 VCCH 39 LRCK3 HGND AIN5R 10 PIN DESCRIPTIONS PIN NAME NO. I/O AIN1L 1 I Line input 1 L-channel DESCRIPTION AIN1R 2 I Line input 1 R-channel AIN2L 3 I Line input 2 L-channel AIN2R 4 I Line input 2 R-channel AIN3L 5 I Line input 3 L-channel AIN3R 6 I Line input 3 R-channel AIN4L 7 I Line input 4 L-channel AIN4R 8 I Line input 4 R-channel AIN5L 9 I Line input 5 L-channel AIN5R 10 I Line input 5 R-channel AIN6L 11 I Line input 6 L-channel AIN6R 12 I Line input 6 R-channel LO1L 13 O Line output 1 L-channel LO1R 14 O Line output 1 R-channel LO2L 15 O Line output 2 L-channel Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM5310 7 PCM5310 SLES244 – FEBRUARY 2009 ............................................................................................................................................................................................ www.ti.com PIN DESCRIPTIONS (continued) PIN NAME NO. I/O LO2R 16 O Line output 2 R-channel HPOL 19 O Headphone output L-channel HPOR 22 O Headphone output R-channel VCOMDA 25 — Common voltage for DAC VCOMAD 64 — Common voltage for ADC VREFAD1 62 — Reference voltage 1 for ADC VREFAD2 63 — Reference voltage 2 for ADC VCCAD 60 — Power supply for ADC (3.3-V typical) AGNDAD 61 — Ground for ADC VCCDA 23 — Power supply for DAC (3.3-V typical) AGNDDA 24 — Ground for DAC VCCP 20 — Power supply for headphone (3.3-V typical) PGND 21 — Ground for headphone VDD 41 — Power supply for digital (3.3-V typical) DGND 42 — Digital ground VCCH 18 — Power supply for 2-VRMS driver (9.0-V typical) HGND 17 — Ground for 2-VRMS driver AGNDS 26 — Analog ground SCK1 29 I/O PORT-1 system clock BCK1 30 I/O PORT-1 serial bit clock LRCK1 31 I/O PORT-1 left and right channel clock DATA1 32 I/O PORT-1 serial audio data SCK2 33 I/O PORT-2 system clock BCK2 34 I/O PORT-2 serial bit clock LRCK2 35 I/O PORT-2 left and right channel clock DATA2 36 I/O PORT-2 serial audio data SCK3 37 I/O PORT-3 system clock BCK3 38 I/O PORT-3 serial bit clock LRCK3 39 I/O PORT-3 left and right channel clock DATA3 40 I/O PORT-3 serial audio data SCK4 43 I/O PORT-4 system clock BCK4 44 I/O PORT-4 serial bit clock LRCK4 45 I/O PORT-4 left and right channel clock DATA4 46 I/O PORT-4 serial audio data SCK5 47 I/O PORT-5 system clock BCK5 48 I/O PORT-5 serial bit clock LRCK5 49 I/O PORT-5 left and right channel clock DATA5 50 I/O PORT-5 serial audio data SCK6 51 I/O PORT-6 system clock BCK6 52 I/O PORT-6 serial bit clock LRCK6 53 I/O PORT-6 left and right channel clock DATA6 54 I/O PORT-6 serial audio data SCL 28 I Clock for I2C interface SDA 27 I/O Data for I2C interface GPIO1 55 I/O General-purpose input and output 1 GPIO2 56 I/O General-purpose input and output 2 GPIO3 57 I/O General-purpose input and output 3 RSTB 58 I Reset (active low) AMUTE 59 I Analog mute control for all analog outputs (active high) 8 DESCRIPTION Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM5310 PCM5310 www.ti.com ............................................................................................................................................................................................ SLES244 – FEBRUARY 2009 GPIO1 GPIO2 GPIO3 SCL SDA SCK6 BCK6 LRCK6 DATA6 SCK5 BCK5 LRCK5 DATA5 SCK4 BCK4 LRCK4 DATA4 SCK3 BCK3 LRCK3 DATA3 SCK2 BCK2 LRCK2 DATA2 SCK1 BCK1 LRCK1 DATA1 RSTB AMUTE FUNCTIONAL BLOCK DIAGRAM I2C GPIO Digital Audio Interface with Mux and Bypass Interpolation Filter and De-Emphasis Decimation Filter and High-Pass Filter (HPF) AGNDS DGND Stereo ADC Stereo ADC Power Supply VDD Stereo DAC Stereo DAC PGND VCCP HGND VCCH AGNDDA VCCDA AGNDAD (VCCAD) Mux VCOMDA VCOMAD REFADN REFADP HP HPOR HPOL LO2R LO2L LO1R LO1L AIN6R AIN6L AIN5L AIN5R AIN4R AIN4L AIN3L AIN3R AIN2R AIN2L AIN1R AIN1L HP VCOM VREF Mux Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM5310 9 PCM5310 SLES244 – FEBRUARY 2009 ............................................................................................................................................................................................ www.ti.com TYPICAL CHARACTERISTICS: Digital Filter (DAC) Sharp, Slow All specifications at TA = +25°C, VDD = VCCAD = VCCDA = VCCP = 3.3 V, VCCH = 9 V, fS = 48 kHz, system clock = 256 fS, and 24-bit data, unless otherwise noted. FREQUENCY RESPONSE (0 fS to 4 fS) FREQUENCY RESPONSE, PASSBAND (0 fS to 0.5 fS) 0.1 0 -20 0 -40 Amplitude (dB) Amplitude (dB) -0.1 -60 -80 -0.2 -100 -0.3 -120 -0.4 -140 -0.5 -160 0 1 2 3 0 4 0.1 0.2 0.3 0.4 0.5 Normalized Frequency (x fS) Normalized Frequency (x fS) Figure 1. Figure 2. TYPICAL CHARACTERISTICS: Analog Filter (DAC) All specifications at TA = +25°C, VDD = VCCAD = VCCDA = VCCP = 3.3 V, VCCH = 9 V, fS = 48 kHz, system clock = 256 fS, and 24-bit data, unless otherwise noted. FREQUENCY RESPONSE (0 Hz to 10 MHz) FREQUENCY RESPONSE (0 Hz to 100 kHz) 2 0 -20 Amplitude (dB) Amplitude (dB) 1 -40 -60 0 -1 -80 -100 1 10 100 1k 10 k Frequency (Hz) 100 k 1M 10 M -2 1 10 100 1k 10 k 100 k Frequency (Hz) Figure 3. 10 Figure 4. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM5310 PCM5310 www.ti.com ............................................................................................................................................................................................ SLES244 – FEBRUARY 2009 TYPICAL CHARACTERISTICS: Digital Filter (ADC) All specifications at TA = +25°C, VDD = VCCAD = VCCDA = VCCP = 3.3 V, VCCH = 9 V, fS = 48 kHz, system clock = 256 fS, and 24-bit data, unless otherwise noted. FREQUENCY RESPONSE (0 fS to 32 fS) FREQUENCY RESPONSE, PASSBAND (0 fS to 0.5 fS) 0 0.1 -20 0 -40 Amplitude (dB) Amplitude (dB) -0.1 -60 -80 -100 -0.2 -0.3 -120 -0.4 -140 -0.5 -160 0 4 8 12 16 20 24 28 0 32 0.1 0.3 0.4 Figure 5. Figure 6. HIGH-PASS FILTER RESPONSE (0 fS to 0.4 fS) HIGH-PASS FILTER RESPONSE (0 fS to 0.1 fS) 0 0 -5 -5 -10 -10 -15 -15 Amplitude (dB) Amplitude (dB) 0.2 0.5 Normalized Frequency (x fS) Normalized Frequency (x fS) -20 -25 -30 -20 -25 -30 -35 -35 -40 -40 -45 -45 -50 -50 0 0.1 0.2 0.3 0.4 0 0.02 0.04 0.06 Normalized Frequency (x fS) Normalized Frequency (x fS) Figure 7. Figure 8. 0.08 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM5310 0.10 11 PCM5310 SLES244 – FEBRUARY 2009 ............................................................................................................................................................................................ www.ti.com TYPICAL CHARACTERISTICS: Analog Performance (DAC) All specifications at TA = +25°C, VDD = VCCAD = VCCDA = VCCP = 3.3 V, VCCH = 9 V, fS = 48 kHz, system clock = 256 fS, and 24-bit data, unless otherwise noted. TOTAL HARMONIC DISTORTION + NOISE vs VCC SUPPLY VOLTAGE SIGNAL-TO-NOISE RATIO AND DATA RATE vs VCC SUPPLY VOLTAGE 0.1 110 THD+N_48(%) THD+N_96(%) 105 SNR, DR (dB) THD+N (%) THD+N_192(%) 0.01 100 95 SNR_48(dB) SNR_96(dB) SNR_192(dB) 90 DR_48(dB) DR_96(dB) DR_192(dB) 0.001 85 3.0 3.3 3.6 3.0 3.3 VCC (V) VCC (V) 3.6 Figure 9. Figure 10. TOTAL HARMONIC DISTORTION + NOISE vs TEMPERATURE SIGNAL-TO-NOISE RATIO AND DATA RATE vs TEMPERATURE 0.1 110 THD+N_48(%) THD+N_96(%) 105 SNR, DR (dB) THD+N (%) THD+N_192(%) 0.01 100 95 SNR_48(dB) SNR_96(dB) 90 SNR_192(dB) DR_48(dB) DR_96(dB) DR_192(dB) 0.001 -25 12 85 0 25 50 75 100 -25 0 25 50 Temperature (°C) Temperature (°C) Figure 11. Figure 12. Submit Documentation Feedback 75 100 Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM5310 PCM5310 www.ti.com ............................................................................................................................................................................................ SLES244 – FEBRUARY 2009 TYPICAL CHARACTERISTICS: Analog Performance (ADC) All specifications at TA = +25°C, VDD = VCCAD = VCCDA = VCCP = 3.3 V, VCCH = 9 V, fS = 48 kHz, system clock = 256 fS, and 24-bit data, unless otherwise noted. TOTAL HARMONIC DISTORTION + NOISE vs VCC SUPPLY VOLTAGE SIGNAL-TO-NOISE RATIO AND DATA RATE vs VCC SUPPLY VOLTAGE 0.1 110 THD+N_48(%) SNR_48(dB) SNR_96(dB) THD+N_96(%) DR_48(dB) DR_96(dB) SNR, DR (dB) THD+N (%) 105 0.01 100 95 90 0.001 85 3.0 3.3 3.6 3.0 3.3 VCC (V) 3.6 VCC (V) Figure 13. Figure 14. TOTAL HARMONIC DISTORTION + NOISE vs TEMPERATURE SIGNAL-TO-NOISE RATIO AND DATA RATE vs TEMPERATURE 0.1 110 THD+N_48(%) THD+N_96(%) SNR, DR (dB) THD+N (%) 105 0.01 100 95 90 SNR_48(dB) SNR_96(dB) DR_48(dB) DR_96(dB) 0.001 85 -25 0 25 50 75 100 -25 0 25 50 Temperature (°C) Temperature (°C) Figure 15. Figure 16. 75 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM5310 100 13 PCM5310 SLES244 – FEBRUARY 2009 ............................................................................................................................................................................................ www.ti.com TYPICAL CHARACTERISTICS: Analog Performance (Headphone) All specifications at TA = +25°C, VDD = VCCAD = VCCDA = VCCP = 3.3 V, VCCH = 9 V, fS = 48 kHz, system clock = 256 fS, and 24-bit data, unless otherwise noted. TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER (48 kHz, 16 Ω) TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER (48 kHz, 32 Ω) 100 100 THD+N_3V(%) THD+N_3.3V(%) THD+N_3.6V(%) THD+N_3V(%) THD+N_3.3V(%) THD+N_3.6V(%) 10 THD+N (%) THD+N (%) 10 1 0.1 0.1 0.01 0.01 10 20 30 40 50 60 70 80 90 10 100 20 30 40 50 Output Power (mW) Output Power (mW) Figure 17. Figure 18. TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER (48 kHz, 0 dB, 6 dB, 12 dB, 16 Ω) TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER (48 kHz, 0 dB, 6 dB, 12 dB, 32 Ω) 10 60 10 THD+N_0dB(%) THD+N_0dB(%) THD+N_6dB(%) THD+N_6dB(%) THD+N_12dB(%) THD+N_12dB(%) 1 THD+N (%) THD+N (%) 1 0.1 0.1 0.01 0.01 10 14 1 20 30 40 50 60 70 10 15 20 25 30 Output Power (mW) Output Power (mW) Figure 19. Figure 20. Submit Documentation Feedback 35 40 Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM5310 PCM5310 www.ti.com ............................................................................................................................................................................................ SLES244 – FEBRUARY 2009 TYPICAL CHARACTERISTICS: Output Spectrum (DAC) All specifications at TA = +25°C, VDD = VCCAD = VCCDA = VCCP = 3.3 V, VCCH = 9 V, fS = 48 kHz, system clock = 256 fS, and 24-bit data, unless otherwise noted. AMPLITUDE vs FREQUENCY (–60 dB, 0 kHz to 20 kHz) 0 0 -20 -20 -40 -40 Amplitude (dB) Amplitude (dB) AMPLITUDE vs FREQUENCY (0 dB, 0 kHz to 20 kHz) -60 -80 -60 -80 -100 -100 -120 -120 -140 -140 0 5 10 15 20 0 5 10 Frequency (kHz) Frequency (kHz) 15 Figure 21. Figure 22. AMPLITUDE vs FREQUENCY (Zero Data Input, 0 kHz to 20 kHz) AMPLITUDE vs FREQUENCY (Zero Data Input, 0 kHz to 130 kHz) 0 20 20 0 -20 -20 Amplitude (dB) Amplitude (dB) -40 -60 -80 -40 -60 -80 -100 -100 -120 -120 -140 -140 0 5 10 15 20 0 Frequency (kHz) 20 40 60 80 100 120 Frequency (kHz) Figure 23. Figure 24. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM5310 15 PCM5310 SLES244 – FEBRUARY 2009 ............................................................................................................................................................................................ www.ti.com TYPICAL CHARACTERISTICS: Output Spectrum (ADC) All specifications at TA = +25°C, VDD = VCCAD = VCCDA = VCCP = 3.3 V, VCCH = 9 V, fS = 48 kHz, system clock = 256 fS, and 24-bit data, unless otherwise noted. AMPLITUDE vs FREQUENCY (–60 dB, 0 kHz to 20 kHz) 20 20 0 0 -20 -20 Amplitude (dB) Amplitude (dB) AMPLITUDE vs FREQUENCY (0 dB, 0 kHz to 20 kHz) -40 -60 -80 -40 -60 -80 -100 -100 -120 -120 -140 -140 0 5 10 Frequency (kHz) 15 0 20 5 10 15 20 Frequency (kHz) Figure 25. Figure 26. AMPLITUDE vs FREQUENCY (Zero Data Input, 0 kHz to 20 kHz) 20 0 Amplitude (dB) -20 -40 -60 -80 -100 -120 -140 0 5 10 Frequency (kHz) 15 20 Figure 27. 16 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM5310 PCM5310 www.ti.com ............................................................................................................................................................................................ SLES244 – FEBRUARY 2009 DETAILED DESCRIPTION ANALOG INPUTS The PCM5310 includes a four-channel analog-to-digital converter (ADC) with a programmable gain amplifier (PGA) and six stereo analog inputs with a 2-VRMS input. Pins AIN1L/1R to AIN6L/6R are connected to the ADC left (L) or right (R) channel through the analog multiplexer (mux) and PGA, as shown in Figure 28. If the analog input voltage level is less than 2 VRMS, it can be amplified by using the PGA. The gain level can be set to 9 dB, 6 dB, or 3 dB. The descriptions for the analog input registers are shown in Table 1. AIN1R AIN2R AIN3R AIN4R AIN5R AIN6R 1L-MUX PGA-AD1L ADC-1L PGA-AD1R 1R-MUX AIN1L AIN2L AIN3L AIN4L AIN5L AIN6L ADC-1R 2L-MUX PGA-AD2L ADC-2L 2R-MUX PGA-AD2R ADC-2R Figure 28. Analog Inputs Table 1. Analog Input Registers REGISTER DESCRIPTION REGISTER NUMBER REGISTER BITS Analog input mux selection for ADC1L/1R 20 AX1R[2:0], AX1L[2:0] Analog input mux selection for ADC2L/2R 21 AX2R[2:0], AX2L[2:0] Analog input gain control for ADC1L/1RW 22 AG1R[1:0], AG1L[1:0] Analog input gain control for ADC2L/2R 23 AG2R[1:0], AG2L[1:0] Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM5310 17 PCM5310 SLES244 – FEBRUARY 2009 ............................................................................................................................................................................................ www.ti.com ANALOG OUTPUTS The PCM5310 includes a four-channel digital-to-analog converter (DAC), two stereo line outputs with analog level control, a headphone output with analog volume control, and an analog multiplexer (mux) with analog direct input path. Line outputs (LO1L, LO1R, LO2L, LO2R) have a 2-VRMS capability without external amplifiers. If an audio application requires a higher output voltage level, the PCM5310 can achieve a 2.4-VRMS output. The headphone output (HPOL, HPOR) has a driving capability of more than 30 mW of output power into a 16-Ω load at 0.1% THD, and an analog volume with zero crossing that can be controlled from –70 dB to 12 dB. For audio applications that require it, the analog volume for the the L- and R-channels can be set simultaneously using the headphone output update control. The line outputs and headphone output can select analog input sources from all the analog inputs and each DAC channel, as shown in Figure 29. The descriptions for the analog output registers are shown in Table 2. AIN1L AIN2L AIN3L AIN4L AIN5L AIN6L PGA-L01R DAC-1L DAC-1R MUX-LO1R PGA-L01L MUX-LO1L AIN1R AIN2R AIN3R AIN4R AIN5R AIN6R HP PGA-HPOR HP MUX-LO2R MUX-HPOL PGA-HPOL DAC-2R MUX-HPOR PGA-L02R MUX-LO2L DAC-2L PGA-L02L Figure 29. Analog Outputs Table 2. Analog Output Registers REGISTER DESCRIPTION REGISTER NUMBER REGISTER BITS Gain level control for line outputs 27 GL2R[1:0], GL2L[1:0], GL1R[1:0], GL1L[1:0] 2.0 VRMS or 2.4 VRMS selection for line outputs 28 G242, G241 Headphone volume zero crossing update control 30 HUPE, HSUR, HSUL, HZRS Headphone output volume level setting 31, 32 HMUL, HMUR, HVOL[6:0], HVOR[6:0] Analog output mux selection for line output 1 24 AL1R[3:0], AL1L[3:0] Analog output mux selection for line output 2 25 AL2R[3:0], AL2L[3:0] Analog output mux selection for headphone output 26 AHPR[3:0], AHPL[3:0] 18 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM5310 PCM5310 www.ti.com ............................................................................................................................................................................................ SLES244 – FEBRUARY 2009 SYSTEM CLOCK INPUT, OUTPUT, AND fS AUTOMATIC DETECTION The PCM5310 has six system clock input ports: SCK1, SCK2, SCK3, SCK4, SCK5, and SCK6. Each input port can receive an independent clock at various frequencies. These ports are used for the internal clock of the digital filters and delta-sigma modulators, which are combined into a single common audio clock. The PCM5310 automatically detects the input clock rate at 128 fS, 192 fS, 256 fS, 384 fS, 512 fS or 768 fS (where fS is the audio sampling rate); if necessary, automatic clock rate detection can be disabled. The descriptions for the system clock input, output, and fS automatic detection registers are shown in Table 3. Table 4 shows the frequency of the common audio clock. Figure 30 and Table 5 shows the timing requirements for the system clock input. Table 3. System Clock Input, Output, and fS Automatic Detection Registers REGISTER NUMBER REGISTER BITS Master or slave with fS detection for DAC12 REGISTER DESCRIPTION 44 DMS12[3:0] Audio interface format for DAC12 44 DFM12[1:0] Master or slave with fS detection for DAC34 54 DMS34[3:0] Audio interface format for DAC34 54 DFM34[1:0] Master or slave with fS detection for ADC12 84 AMS12[3:0] Audio interface format for ADC12 84 AFM12[1:0] Master or slave with fS detection for ADC34 94 AMS34[3:0] Audio interface format for ADC34 94 AFM34[1:0] SCK6 clock output selection 07 PSC6[2:0] Table 4. System Clock Frequencies for the Common Audio Clock SAMPLING FREQUENCY (kHz) (1) SYSTEM CLOCK FREQUENCY (MHz) 128 fS (1) 192 fS (1) 256 fS 384 fS 512 fS 768 fS 32 4.0960 6.1440 8.1920 12.2880 16.3840 24.5760 44.1 5.6488 8.4672 11.2896 16.9344 22.5792 33.8688 48 6.1440 9.2160 12.2880 18.4320 24.5760 36.8640 88.2 11.2896 16.9344 22.5792 33.8688 Not supported Not supported 96 12.2880 18.4320 24.5760 36.8640 Not supported Not supported 176.4 (1) 22.5792 33.8688 Not supported Not supported Not supported Not supported 192 (1) 24.5760 36.8640 Not supported Not supported Not supported Not supported This sampling frequency and system clock frequency are supported only for the DAC. tSCH High 2.0 V SCK1 to 6 0.8 V Low tSCL tSCY Figure 30. System Clock Input Timing Table 5. Timing Characteristics for Figure 30 PARAMETER MIN MAX UNIT tSCY System clock cycle time 25 ns tSCH System clock high time 0.4 tSCY ns tSCL System clock low time 0.4 tSCY System clock duty cycle 40 ns 60 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM5310 % 19 PCM5310 SLES244 – FEBRUARY 2009 ............................................................................................................................................................................................ www.ti.com POWER ON/OFF RESET The power-on reset (POR) circuit generates a reset signal at typically 2.2 V; this circuit does not depend on the other power supplies: VCCDA, VCCAD, VCCH, and VCCP. The internal circuit is cleared to default status, then all analog and digital outputs have no signal. It is recommended to turn the device on and off as shown in Figure 31, in order to avoid loud, audible pop noises when powering the device on or off. 2.2 V Typical (1.6 V to 2.8 V) 1.6 V Typical (1.0 V to 2.0 V) VDD Power-On Reset RSTB 0 s (min) 2 I C Setting is Effective 2 I C Setting 1 ms (min) Power-Up for ADCs and DACs SCKx Internal Reset for ADCs and DACs (1) Clock Input Clock Input (1) Clock Input 1024 Clocks RSTB is active low. 100 ns (minimum) is needed for an effective reset to the internal circuit. Figure 31. Power On/Off Reset 20 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM5310 PCM5310 www.ti.com ............................................................................................................................................................................................ SLES244 – FEBRUARY 2009 REGISTER RESET AND SYSTEM RESET (Register 01) Register reset (MRST) clears all register data to the default setting. The MRST register is automatically set to '1' after the reset. System reset (SRST) clears all internal circuits, including all register data, to default status simultaneously. The SRST register is automatically set to '1' after the reset. Note that the PCM5310 may have audible pop noises on the analog and digital outputs when enabling MRST and SRST. The descriptions for the register reset and system reset registers are shown in Table 6. Table 6. Reset Registers REGISTER DESCRIPTION REGISTER NUMBER REGISTER BITS Reset register data only 01 MRST Reset for all circuits including register data 01 SRST RSTB Control Taking RSTB (pin 58) from high to low clears all internal circuits to default status. If an application does not require reset control, RSTB should be connected with an RC passive delay circuit to the digital power supply (VDD). Note that the PCM5310 may have audible pop noises on the analog and digital outputs when enabling RSTB. The RSTB control status descriptions are shown in Table 6. Table 7. RSTB Control RSTB (PIN 58) STATUS DESCRIPTION Low Reset all circuits including register data High Reset release Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM5310 21 PCM5310 SLES244 – FEBRUARY 2009 ............................................................................................................................................................................................ www.ti.com POWER-SUPPLY SEQUENCE AND POWER ON/OFF SEQUENCE In order to reduce audible pop noise, a register setting sequence is required after turning on all power supplies and before turning off all power supplies. Any modules that are not used in the application or system should be powered down after the recommended power-on sequence. Before the power-off sequence, all modules should be in a power-on state. The recommended power-supply sequence is shown in Figure 32. The recommended register settings are shown in Table 8 and Table 9. VDD, VCCP, VCCAD, VCCDA VCCH (9 V) Recommended Power-On Sequence 2 I C Register Setting Analog Output (1) Recommended Power-Off Sequence Half of Power-Supply Voltage 37.5 ms to 1000 ms 75 ms to 2000 ms (2) Digital Output (1) Ramp up/down time for the analog output can be changed through the register setting (see Register 18, PDTM[2:0]). (2) A 1.0-µF capacitor should be connected to the VCOMAD and VCOMDA pins. Figure 32. Recommended Power On/Off Sequence Table 8. Recommended Register Settings When Powered On REGISTER SETTING (1) 22 STEP ADDRESS DATA 1 — — Turn on all power supplies DESCRIPTION 2 11 00 Analog bias power up 3 1F 49 Headphone output L-channel mute disable and level (–42 dB) setting (1) 4 20 49 Headphone output R-channel mute disable and level (–42 dB) setting (1) 5 1E B0 Headphone volume update control 6 1B 00 Line output gain (0 dB) control from DAC (1) 7 1C 00 Line output 2 VRMS and 2.4 VRMS mode select 8 2A FF DAC12 L-channel digital attenuation level (0 dB) setting (1) 9 2B FF DAC12 R-channel digital attenuation level (0 dB) setting (1) 10 29 00 DAC12 digital mute setting and digital gain boost 11 28 B1 DAC12 digital attenuation/mute control and zero crossing enable 12 34 FF DAC34 L-channel digital attenuation level (0 dB) setting (1) 13 35 FF DAC34 R-channel digital attenuation level (0 dB) setting (1) 14 33 00 DAC34 digital mute setting and digital gain (0 dB) boost 15 32 B1 DAC34 digital attenuation/mute control and zero crossing enable 16 52 D5 ADC12 L-channel digital attenuation level (0 dB) setting (1) 17 53 D5 ADC12 R-channel digital attenuation level (0 dB) setting (1) Any level is acceptable for volume, gain, and attenuation. The level should be resumed by register data recorded when the system powers off. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM5310 PCM5310 www.ti.com ............................................................................................................................................................................................ SLES244 – FEBRUARY 2009 Table 8. Recommended Register Settings When Powered On (continued) REGISTER SETTING (2) (3) (4) (5) STEP ADDRESS DATA 18 51 00 ADC12 digital mute disable DESCRIPTION 19 50 01 ADC12 digital attenuation/mute control and zero crossing enable 20 5C D7 ADC34 L-channel digital attenuation level (0 dB) setting (1) 21 5D D7 ADC34 R-channel digital attenuation level (0 dB) setting (1) 22 5B 00 ADC34 digital mute disable 23 5A 01 ADC34 digital attenuation/mute control and zero crossing enable 24 18 77 Line output 1 L-/R-channel mux select 25 19 00 Line output 2 L-/R-channel mux select 26 1A 88 Headphone output L-/R-channel mux select 27 14 11 ADC12 analog input mux select (AIN1L/R) (2) 28 15 22 ADC34 analog input mux select (AIN2L/R) (2) 29 16 00 ADC12 analog input gain level (0 dB) setting (1) 30 17 00 ADC34 analog input gain level (0 dB) setting (1) 31 65 98 Audio interface (LRCKx/BCKx) PORT-1 and PORT-2 setting (ADC12/34, master) (3) 32 66 98 Audio interface (DATAx) PORT-1 and PORT-2 setting (DATA output of ADC12/34) (3) 33 67 10 Audio interface (SCKx) PORT-1 and PORT-2 setting (input of SCK1/2) (4) 34 68 32 Audio interface (LRCKx/BCKx) PORT-3 and PORT-4 setting (input of LRCK3/4, BCK3/4) (4) 35 69 32 Audio interface (DATAx) PORT-3 and PORT-4 setting (input of DATA3/4) (4) 36 6A 32 Audio interface (SCKx) PORT-3 and PORT-4 setting (input of SCK3/4) (4) 37 6B 54 Audio interface (LRCKx/BCKx) PORT-5 and PORT-6 setting (input of LRCK3/4, BCK3/4) (4) 38 6C 54 Audio interface (DATAx) PORT-5 and PORT-6 setting (input of DATA5/6) (4) 39 6D 54 Audio interface (SCKx) PORT-5 and PORT-6 setting (input of SCK5/6) (4) 40 6E 43 DAC12 and DAC34 LRCK/BCK select (4) 41 6F 43 DAC12 and DAC34 DATA select (4) 42 70 43 DAC12 and DAC34 SCK select (4) 43 74 89 ADC12 and ADC34 LRCK/BCK select (ADC12/34, master) (4) 44 75 10 ADC12 and ADC34 SCK select (4) 45 76 76 GPIO control or GPIO1 and GPIO2 audio data select 46 2C 80 DAC12 audio interface and master/slave select (5) 47 36 80 DAC34 audio interface and master/slave select (5) 48 54 40 ADC12 audio interface and master/slave select (master, 256 fS) (5) 49 5E 40 ADC34 audio interface and master/slave select (master, 256 fS) (5) 50 12 11 Analog back-end and front-end power-up 51 2E 00 DAC12 power-up 52 38 00 DAC34 power-up 53 55 00 ADC12 power-up 54 5F 00 ADC34 power-up 55 12 01 Common voltage (VCOM) power-up and ramp up/down time setting Any input terminals are acceptable for input of ADC12 and ADC34. These settings are not required if application does not use audio interface mux and bypass selection. These settings are not required if application does not use audio interface mux and bypass selection. These settings are not required if application uses slave mode for audio interface and SCK automatic fS detection. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM5310 23 PCM5310 SLES244 – FEBRUARY 2009 ............................................................................................................................................................................................ www.ti.com Table 9. Recommended Register Setting When Powered Off REGISTER SETTING 24 STEP ADDRESS DATA 1 18 00 Line output1 L- and R-channel mux select DESCRIPTION 2 19 00 Line output2 L- and R-channel mux select 3 1A 00 Headphone output L- and R-channel mux select 4 14 00 ADC12 analog input mux select 5 15 00 ADC34 analog input mux select 6 12 11 Common voltage (VCOM) power-down and ramp up/down time setting 7 55 80 ADC12 power-down 8 5F 80 ADC34 power-down 9 2E 80 DAC12 power-down 10 38 80 DAC34 power-down 11 12 71 Analog back-end and front-end power-down 12 11 80 Analog bias power-down 13 — — Turn off all power supplies Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM5310 PCM5310 www.ti.com ............................................................................................................................................................................................ SLES244 – FEBRUARY 2009 AUDIO SERIAL INTERFACE The PCM5310 has six audio interface ports: SCKx, BCKx, LRCKx, and DATAx (bidirectional). Each port or signal can be connected to any ADC or DAC. If an audio system application wants to bypass an audio signal, the PCM5310 can bypass from any port to any port. Refer to Figure 33 for a diagram of the of the audio inteface port and mux. See Figure 47 to Figure 52 for detailed diagrams of PORT-1 to PORT-6. The audio interface consists of LRCKs, BCKs, and DATAs. The sampling rate (fS), left channel and right channel data are present on the LRCKs. The DATAs receive the serial audio data from the interpolation filter for the DAC, and the DATAs transmit the serial data to the decimation filter. The BCKs are used to receive and transmit the serial audio data on the DATAs by high-to-low transition. The BCKs and LRCKs should be synchronized with the system clocks, SCKs. The PCM5310 operates with the LRCKs/BCKs synchronized with the SCKs; however, the PCM5310 does not need a specific phase between the BCKs/LRCKs and the SCKs. Each audio interface port can select either the master or slave mode, and generate the LRCKs and BCKs from the SCKs in master mode. The descriptions for the audio serial interface registers are shown in Table 6. Table 10. Audio Serial Interface Registers REGISTER NUMBER REGISTER BITS Master or slave with fS detection for DAC12 REGISTER DESCRIPTION 44 DMS12[3:0] Audio interface format for DAC12 44 DFM12[1:0] Master or slave with fS detection for DAC34 54 DMS34[3:0] Audio interface format for DAC34 54 DFM34[1:0] Master or slave with fS detection for ADC12 84 AMS12[3:0] Audio interface format for ADC12 84 AFM12[1:0] Master or slave with fS detection for ADC34 94 AMS34[3:0] Audio interface format for ADC34 94 AFM34[1:0] LRCK/BCK selection of PORT-1 and PORT-2 101 LBS2[3:0], LBS1[3:0] DATA selection of PORT-1 and PORT-2 102 DTS2[3:0], DTS1[3:0] SCK selection of PORT-1 and PORT-2 103 SCS2[2:0], SCS1[2:0] LRCK/BCK selection of PORT-3 and PORT-4 104 LBS4[3:0], LBS3[3:0] DATA selection of PORT-3 and PORT-4 105 DTS4[3:0], DTS3[3:0] SCK selection of PORT-3 and PORT-4 106 SCS4[2:0], SCS3[2:0] LRCK/BCK selection of PORT-5 and PORT-6 107 LBS6[3:0], LBS5[3:0] DATA selection of PORT-5 and PORT-6 108 DTS6[3:0], DTS5[3:0] SCK selection of PORT-5 and PORT-6 109 SCS6[2:0], SCS5[2:0] LRCK/BCK selection of DAC12 and DAC34 110 D34LB[3:0], D12LB[3:0] DATA selection of DAC12 and DAC34 111 D34DT[3:0], D12DT[3:0] SCK selection of DAC12 and DAC34 112 D34S[2:0], D12S[2:0] LRCK/BCK selection of ADC12 and ADC34 116 A34LB[3:0], A12LB[3:0] SCK selection of ADC12 and ADC34 117 A34SC[2:0], A12SC[2:0] GPIO-1 and GPIO-2 audio data selection 118 GP2S[3:0], GP1S[3:0] Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM5310 25 PCM5310 SLES244 – FEBRUARY 2009 ............................................................................................................................................................................................ www.ti.com LRCK1 DATA from ADC12 BCK1 LRCK, BCK at Master PORT-1 LRCK, BCK, DATA, SCK from PORT-1 LRCK, BCK, DATA, SCK from PORT-2 LRCK, BCK, DATA, SCK from PORT-3 LRCK, BCK, DATA, SCK from PORT-4 LRCK, BCK, DATA, SCK from PORT-5 LRCK, BCK, DATA, SCK from PORT-6 SCK1 LRCK2 BCK2 DATA2 MUX_AD12 DATA1 LRCK, BCK, SCK for ADC12 PORT-2 DATA from ADC34 LRCK, BCK at Master MUX_AD34 LRCK3 BCK3 ADC12 Reg 116 A12LB[3:0] Reg 117 A12S[2:0] SCK2 DATA3 BCK/LRCK Master PORT-3 SCK3 LRCK, BCK, SCK for ADC34 BCK/LRCK Master ADC34 Reg 116 A34LB[3:0] Reg 117 A34S[2:0] LRCK4 BCK4 DATA4 PORT-4 LRCK, BCK at Master MUX_DA12 SCK4 LRCK5 BCK5 DATA5 PORT-5 BCK/LRCK Master LRCK, BCK, SCK for DAC12 Reg 110 D12LB[3:0] Reg 111 D12DT[3:0] Reg 112 D12S[2:0] DAC12 SCK5 LRCK, BCK at Master BCK6 DATA6 MUX_DA34 LRCK6 PORT-6 SCK6 GPIO1 GPIO2 GPIO1 GPIO2 BCK/LRCK Master LRCK, BCK, SCK for DAC34 Reg 110 D34LB[3:0] Reg 111 D34DT[3:0] Reg 112 D34S[2:0] DATA for DAC12/34 from GPIO1 and GPIO2 DATA for ADC12/34 to GPIO1 and GPIO2 DAC34 To Register Mapping Figure 33. Audio Interface Port and Mux 26 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM5310 PCM5310 www.ti.com ............................................................................................................................................................................................ SLES244 – FEBRUARY 2009 AUDIO DATA FORMATS AND TIMING The PCM5310 supports I2S, left-justified, and right-justified data formats with 32 fS, 48 fS, or 64 fS BCK rates for digital input, and 48 fS or 64 fS BCK rates for the ADC. The data formats are shown in Figure 34 and can be selected through the I2C interface. All formats require binary twos complement, MSB first audio data. The default format is 16- to 24-bits I2S. Figure 35 and Figure 36 show detailed timing diagrams. The descriptions for the audio interface data format registers are shown in Table 11. Table 11. Audio Interface Data Format Registers REGISTER DESCRIPTION REGISTER NUMBER REGISTER BITS Audio interface format for DAC12 44 DFM12[1:0] Audio interface format for DAC34 54 DFM34[1:0] Audio interface format for ADC12 84 AFM12[1:0] Audio interface format for ADC34 94 AFM34[1:0] (a) Right-Justified Data Format; L-Channel = HIGH, R-Channel = LOW 1/fS LRCK R-Channel L-Channel BCK (= 32 fS, 48 fS, or 64 fS) DATA LSB MSB MSB LSB 2 (b) I S Data Format; L-Channel = LOW, R-Channel = HIGH 1/fS LRCK L-Channel R-Channel BCK (= 32 fS, 48 fS, or 64 fS) DATA MSB LSB MSB LSB (c) Left-Justified Data Format; L-Channel = HIGH, R-Channel = LOW 1/fS LRCK L-Channel R-Channel BCK (= 32 fS, 48 fS, or 64 fS) DATA MSB LSB MSB LSB Figure 34. Audio Data Input and Output Formats Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM5310 27 PCM5310 SLES244 – FEBRUARY 2009 ............................................................................................................................................................................................ www.ti.com tBCL tBCH BCKx (Input) 1. 4 V tBCY tLRH tLRS LRCKx (Input) 1. 4 V tDOD (1) DATAx (Output Mode) 0.5 VDD tDIS tDIH DATAx (Input Mode) (1) 1. 4 V Load capacitance of output is 20 pF. Figure 35. Audio Interface Timing (Slave Mode) Table 12. Timing Requirements for Figure 35 PARAMETER 28 MIN MAX UNIT tBCY BCKx cycle time 75 ns tBCH BCKx pulse width high 35 ns tBCL BCKx pulse width low 35 ns tLRS LRCKx set-up time to BCKx rising edge 15 ns tLRH LRCKx hold time to BCKx rising edge 10 ns tDIS DATAx setup time to BCKx rising edge 10 ns tDIH DATAx hold time to BCKx rising edge 10 tDOD DATAx delay time from BCKx falling edge 0 Submit Documentation Feedback ns 30 ns Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM5310 PCM5310 www.ti.com ............................................................................................................................................................................................ SLES244 – FEBRUARY 2009 tBCH tBCL BCKx (Output) 0.5 VDD tBCY tLRD LRCKx (Output) 0.5 VDD tDOD DATAx(1) (Output Mode) 0.5 VDD tDIS tDIH DATAx (Input Mode) (1) 1.4 V Load capacitance of output is 20 pF. Figure 36. Audio Interface Timing (Master Mode) Table 13. Timing Requirements for Figure 36 PARAMETER MIN TYP MAX tBCY BCKx cycle time tBCH BCKx pulse width high 0.4 tBCY 0.5 tBCY 0.6 tBCY tBCL BCKx pulse width low 0.4 tBCY 0.5 tBCY 0.6 tBCY tLRD LRCKx delay time from BCKx falling edge –15 UNIT 1/(64 fS) tDIS DATAx setup time to BCKx rising edge 10 tDIH DATAx hold time to BCKx rising edge 10 tDOD DATAx delay time from BCKx falling edge –10 20 ns ns 20 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM5310 ns ns 29 PCM5310 SLES244 – FEBRUARY 2009 ............................................................................................................................................................................................ www.ti.com ADC AND FILTER The analog-to-digital converter (ADC) and digital filter include a delta-sigma modulator, decimation filter, high-pass filter (HPF), digital gain control, digital attenuation control, and digital soft mute, as shown in Figure 37. The HPF eliminates dc offset of the ADC analog section with 0.91 Hz as the cutoff frequency at a 48-kHz sampling rate. The digital gain or attenuation control can be adjusted from 20 dB to –100 dB in 0.5-dB steps. The descriptions for the ADC and filter registers are shown in Table 14. PGA-AD1L ADC-1L Decimation Filter HPF ATT MUTE ADC-1R Decimation Filter HPF ATT MUTE ADC-2L Decimation Filter HPF ATT MUTE ADC-2R Decimation Filter HPF ATT MUTE PGA-AD1R PGA-AD2L PGA-AD2R Figure 37. ADCs and Filters Table 14. ADC and Filter Registers REGISTER DESCRIPTION REGISTER NUMBER REGISTER BITS Digital attenuation and gain update control for ADC12 80 A12E, AUC2, AUC1, AZ12 Digital soft mute setting for ADC12 81 AMU2, AMU1 82, 83 AAT2[7:0], AAT1[7:0] High-pass filter disable for ADC12 84 HF12 Digital attenuation and gain update control for ADC34 90 A34E, AUC4, AUC3, AZ34 Digital soft mute setting for ADC34 91 AMU4, AMU3 92, 93 AAT4[7:0], AAT3[7:0] 94 HF34 Digital attenuation and gain level setting for ADC12 Digital attenuation and gain level setting for ADC34 High-pass filter disable for ADC34 30 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM5310 PCM5310 www.ti.com ............................................................................................................................................................................................ SLES244 – FEBRUARY 2009 DAC AND FILTER The digital-to-analog converter (DAC) and digital filter include a delta-sigma modulator, interpolation filter, de-emphasis filter (DEM), digital gain control, digital attenuation control, digital soft mute, and digital gain boost, as shown in Figure 38. The digital gain or attenuation control can be adjusted from 20 dB to –100 dB in 0.5-dB steps. To play back low-volume recorded audio data, the digital gain can be used with a boost of either 6 dB, 12 dB, or 18 dB selected through the I2C interface. The descriptions for the DAC and filter registers are shown in Table 14. ATT MUTE GAIN DEM Interpolation Filter DAC-1L ATT MUTE GAIN DEM Interpolation Filter DAC-1R ATT MUTE GAIN DEM Interpolation Filter DAC-2L ATT MUTE GAIN DEM Interpolation Filter DAC-2R Figure 38. DACs and Filters Table 15. DAC and Filter Registers REGISTER DESCRIPTION Digital attenuation and gain update control for DAC12 Digital soft mute and boost setting for DAC12 Digital attenuation and gain level setting for DAC12 REGISTER NUMBER REGISTER BITS 40 D12E, DUC2, DUC1, DZ12 41 DMU2, DMU1, DB12[1:0] 42, 43 DAT2[7:0], DAT1[7:0] De-emphasis filter setting for DAC12 45 DM12, DF12[1:0] Digital attenuation and gain update control for DAC34 50 D34E, DUC4, DUC3, DZ34 Digital soft mute setting for DAC34 Digital attenuation and gain level setting for DAC34 De-emphasis filter setting for DAC34 51 DMU4, DMU3 52, 53 DAT4[7:0], DAT3[7:0] 55 DM34, DF34[1:0] Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM5310 31 PCM5310 SLES244 – FEBRUARY 2009 ............................................................................................................................................................................................ www.ti.com GPIO CONTROL The PCM5310 has three general-purpose input/output (GPIO) pins (pins 55, 56, and 57) that can be assigned to various functions and internal status reads shown in Table 16, Table 17, Table 18, and Figure 39. Table 16. GPIO Control Registers REGISTER NUMBER REGISTER BITS GPIO1 select, bypass PORT-4 REGISTER DESCRIPTION 09 GBP4, GSL1[4:0] GPIO2 select, bypass PORT-5 10 GBP5, GSL2[4:0] GPIO3 select 11 GSL3[4:0] Table 17. Register Data Read Through the GPIO Pins REGISTER NUMBER REGISTER BITS External device control REGISTER DESCRIPTION 08 GPO3, GPO2, GPO1 Headphone short-circuit protection status 16 SSHR, SSHL Headphone insertion detect status 35 RHPI Mute status for headphone 35 RHMUR, RHMUL System clock fS detect for DAC12, DAC34 35, 36 RD12FS[2:0], RD34[2:0] System clock fS detect for ADC12, ADC34 37, 38 RA12FS[2:0], RA34[2:0] Digital mute status for DAC12 and DAC34 36 RDM4, RDM3, RDM2, RDM1 Digital mute status for ADC12 and ADC34 37 RAM4, RAM3, RAM2, RAM1 Zero crossing timeout for DAC12 and DAC34 38 RDZ4, RDZ3, RDZ2, RDZ1 Zero crossing timeout for ADC12 and ADC34 39 RAZ4, RAZ3, RAZ2, RAZ1 Zero crossing timeout for headphone 39 RHZR, RHZL Table 18. Other GPIO Pin Functions GPIO PIN FUNCTION DESCRIPTION Zero flag for digital input Read the status for each DAC channel or all DAC channels Logic OR, AND, NOR, NAND, buffer, inverter Audio data Bypass audio data to PORT-4 and PORT-5 from GPIO pins GPIO1 GPIO2 Zero Flag Register Out GPIO Control GPIO1 GPIO2 GPIO3 Mux HP Insertion HP Protection Logic In/Out Connect to Port GPIO3 Figure 39. GPIO Control 32 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM5310 PCM5310 www.ti.com ............................................................................................................................................................................................ SLES244 – FEBRUARY 2009 HEADPHONE SHORT-CIRCUIT PROTECTION The PCM5310 has short-circuit protection for each headphone output. The short-circuit status can be read from the GPIO pins and the register data can be read through the I2C interface. The short-circuit detection time can be internally adjusted to avoid the headphone amplifier shutting down when inserting or removing the headphone jack. The descriptions for the headphone and short-circuit protection registers are shown in Table 19. The headphone short-circuit protection sequence is shown in Figure 40. Table 19. Headphone Short-Circuit Protection Registers REGISTER DESCRIPTION REGISTER NUMBER REGISTER BITS Headphone short-circuit protection enable/disable 13 SRCR, SHCR, SPDR, SRCL, SHCL, SPDL Headphone short-cicuit protection detect time 14 SDTR[1:0], SDTL[1:0] Headphone short-circuit protection release time 15 SRTR[1:0], SRTL[1:0] Headphone short-circuit protection status read 16 SSHR, SSHL Headphone Amplifier HPOL or HPOR Headphone Jack Protection Resistor Enable/Disable Current Monitor Internal Clock Increment or Decrement Counter Detect/Release Time 4096 fS: 85.2 ms at fS = 48 kHz 8192 fS: 1704 ms at fS = 48 kHz 16384 fS: 340.8 ms at fS = 48 kHz 32768 fS: 681.6 ms at fS = 48 kHz Headphone 16W or 32W Short or Not Internal Resistor GPIO Control GPIO1, GPIO2, or GPIO3 Figure 40. Headphone Short-Circuit Protection Sequence When the short-circuit protection is enabled, it is recommended to insert a small protection resistor to limit over-current flow. Table 20 shows the headphone output power with a small resistor. Table 20. Headphone Amplifier Output Power Load RL = 32 Ω + PROTECTION RESISTOR 32 Ω + 4 Ω 32 Ω + 8 Ω 32 Ω + 16 Ω 0.1% THD 28 mW 22 mW 16 mW 10% THD 37 mW 31 mW 22 mW Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM5310 33 PCM5310 SLES244 – FEBRUARY 2009 ............................................................................................................................................................................................ www.ti.com HEADPHONE INSERTION DETECTION The descriptions for the headphone insertion detection registers are shown in Table 21. The PCM5310 detects the insertion status of a headphone plug using the GPIO pins through the register setting and writes the status to the register, which can be read by the I2C interface. The status can also output to the GPIO pins, as shown in Figure 41. Table 21. Headphone Insertion Detection Registers REGISTER DESCRIPTION REGISTER NUMBER REGISTER BITS GPIO1 selection 09 GSL1[4:0] GPIO2 selection 10 GSL2[4:0] GPIO3 selection 11 GSL3[4:0] Read status for headphone insertion 35 RIPI SDA 2 IC Register SCL DSP VDD GPIO Control GPIO1, GPIO2, or GPIO3 Headphone Jack Headphone Amplifier HPOR HPOL PGND Figure 41. Headphone Insertion Detection 34 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM5310 PCM5310 www.ti.com ............................................................................................................................................................................................ SLES244 – FEBRUARY 2009 ZERO FLAG DETECTION The PCM5310 detects continuous zero data input to either DAC12, DAC34, or both DAC12 and DAC34. The GPIO pins can output the status to an external device by the register setting. The flag changes from low to high when the L-and R-channel data are zero after 1024 fS. The descriptions for the zero flag detection registers are shown in Table 22. Figure 42 shows the zero flag detection operation. Table 22. Zero Flag Registers REGISTER DESCRIPTION REGISTER NUMBER REGISTER BITS GPIO1 selection 09 GSL1[4:0] GPIO2 selection 10 GSL2[4:0] GPIO3 selection 11 GSL3[4:0] LRCK4 BCK4 DATA4 PORT-4 DAC12 LRCK5 BCK5 DATA5 PORT-5 DAC34 Zero Data or Not Zero Data or Not Increment Counter Increment Counter GPIO Control GPIO1 GPIO2 GPIO3 Figure 42. Zero Flag Detection AMUTE Control The PCM5310 has an AMUTE pin (pin 59) that controls the digital and analog mute function linked to Register 19 (13h). If these settings are disabled and the AMUTE pin goes from low to high, the PCM5310 holds the digital and analog mute disabled. If these settings are enabled and the AMUTE pin goes from low to high, the PCM5310 enables digital and analog mute. The mute function set by the AMUTE pin is effective, regardless of the setting in Register 19. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM5310 35 PCM5310 SLES244 – FEBRUARY 2009 ............................................................................................................................................................................................ www.ti.com MUTE CONTROL TIMING DURING CLOCK CHANGES The PCM5310 has six audio interface ports and can change from the current source to another source. However, the analog output or digital output may have an audible pop noise when changing or stopping clocks. It is recommend to use the mute control with zero data input and waiting time to avoid pop noise and clean up the internal circuit via I2C. Figure 43 illustrates the details. Note that the digital and analog inputs should be zero data initially. After that, use the following steps: 1. Disable zero crossing detection. 2. Enable the analog or digital output mute. 3. Change the clock source. 4. Disable the analog or digital mute. Clock Source A Clock Source B (1) 241 8 fS(ADC) 1 fS (DAC) 35 fS(ADC) 25 fS (DAC) I2C Setting NOTE: The digital and analog inputs should be zero data at first. Then use the following setting procedure: a) Disable zero crossing detection. b) Enable analog or digital output mute. c) Change the clock source. d) Disable the analog or digital mute. (1) Value depends on attenuation level setting in Registers 82, 83, 92, and 93. Figure 43. Mute Control Timing During Clock Changes 36 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM5310 PCM5310 www.ti.com ............................................................................................................................................................................................ SLES244 – FEBRUARY 2009 ANALOG MUX CHANGING TO REDUCE AUDIBLE NOISE The PCM5310 has an analog multiplexer (mux) that can select six stereo analog inputs. The ADC output may have audible noise when selecting without mute control via I2C. It is recommend to use digital soft mute before changing the analog input, as shown in Figure 44. AIN1L AIN2L I2C Setting (2) (1) (3) ADC Output (4) (4) (1) Enable digital soft mute of ADC. (2) Change analog input source. (3) Disable digital soft mute of ADC. (4) Maximum mute time is [241 × 8 fS] seconds; however, this time depends on the wave form if zero crossing is enabled. It is recommended to read the status of this mute from Register 35 to 39 via I2C. Then if the status is high, disable mute. Figure 44. Analog Mux Changing to Reduce Audible Noise Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM5310 37 PCM5310 SLES244 – FEBRUARY 2009 ............................................................................................................................................................................................ www.ti.com TWO-WIRE INTERFACE (I2C) The PCM5310 supports the I2C serial bus and the data transmission protocol for the I2C standard as a slave device. This protocol is explained in the I2C specification 2.0. In I2C mode, the control terminals are changed as shown in Table 23. Table 23. Control Pins PIN NAME INPUT/OUTPUT DESCRIPTION SDA Input/Output I2C data SCL Input I2C clock Slave Address The PCM5310 has its own 7-bit slave address, as shown in Table 24. The first six bits (MSBs) of the slave address are factory preset to '1000110'. The last bit of the address byte is the device select bit, which can be user-defined by the ADR terminal. A maximum of two PCM5310s can be connected on the same bus simultaneously. Each PCM5310 responds when it receives its own slave address. Table 24. Slave Address MSB LSB 1 0 0 0 1 1 0 R/W Packet Protocol The master device must control packet protocol, which consists of a start condition, a slave address with read/write (R/W) bit, data (if write) or acknowledgement (if read), and a stop condition, as shown in Figure 45. The PCM5310 supports only a slave receiver and slave transmitter. Table 25 shows a basic I2C write operation. Table 26 shows a basic I2C read operation. Start Condition Stop Condition SDA SCL St 1-7 8 9 1-8 9 1-8 9 Slave Address R/W ACK DATA ACK DATA ACK Sp R/W: Read operation if ‘1’; otherwise, write operation. ACK: Acknowledgement of a byte if ‘0’. DATA: 8 bits (1 byte). Figure 45. Basic I2C Framework Table 25. Basic I2C Write Operation TRANSMITTER M DATA TYPE St M Slave address M S M S M S M R/W ACK DATA ACK DATA ACK Sp LEGEND: M = master device, S = slave device, St = START condition, Sp = STOP condition, R/W = read/write, ACK = acknowledge. Table 26. Basic I2C Read Operation TRANSMITTER M DATA TYPE St M Slave address M S M S M S M R/W ACK DATA NACK DATA NACK Sp LEGEND: M = master device, S = slave device, St = START condition, Sp = STOP condition, R/W = read/write, ACK = acknowledge, NACK = not acknowledge. 38 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM5310 PCM5310 www.ti.com ............................................................................................................................................................................................ SLES244 – FEBRUARY 2009 Write Operation The master can write to any PCM5310 register in a single access. The master sends a PCM5310 slave address with a write bit, a register address, and data. When undefined registers are accessed, the PCM5310 does not send any acknowledgement. Table 27 shows the framework for a write operation. Table 27. Framework for Write Operation TRANSMITTER M DATA TYPE St M Slave address M S W ACK M Register address S M S M ACK Write data ACK Sp LEGEND: M = master device, S = slave device, St = start condition, Sp = stop condition, W = write, ACK = acknowledge. Read Operation The master can read any PCM5310 register. The value of the register address is stored in an indirect index register in advance. The master sends the PCM5310 slave address with a read bit after storing the register address. The PCM5310 then transfers the data to the address specified by the index register. Table 28 shows the framework for a read operation. Table 28. Framework for Read Operation TRANSMITTER M DATA TYPE St LEGEND: M Slave address M S W ACK M Register address S M ACK Sr M Slave address M S R ACK S Read data M M NACK Sp M = master device, S = slave device, St = START condition, Sr = repeated START condition, Sp = STOP condition, W = write, R = read, ACK = acknowledge, NACK = not acknowledge. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM5310 39 PCM5310 SLES244 – FEBRUARY 2009 ............................................................................................................................................................................................ www.ti.com I2CTiming Diagram Stop Condition Start Condition t(BUF) t(D-SU) t(D-HD) t(SDA-R) t(SDA-F) t(P-SU) SDA t(LOW) t(SCL-R) t(SP) t(RS-HD) SCL t(S-HD) t(SCL-F) t(HI) t(RS-SU) Figure 46. I2C Timing Table 29. Timing Characteristics for Figure 46 I2C SPECIFICATION PARAMETER 40 MIN MAX UNIT 100 kHz fSCL SCL clock frequency Standard t(BUF) Bus free time between STOP and START condition Standard 4.7 µs t(LOW) SCL clock low period Standard 4.7 µs t(HI) SCL clock high period Standard 4 µs t(RS-SU) START condition setup time Standard 4.7 µs t(S-HD) START condition hold time Standard 4 µs t(D-SU) Data setup time Standard 250 t(D-HD) Data hold time Standard 0 900 ns ns t(SCL-R) SCL signal rise time Standard 20 + 0.1 CB 1000 ns t(SCL-R1) Rise time of SCL signal after a repeated START condition and after an acknowledge bit Standard 20 + 0.1 CB 1000 ns t(SCL-F) SCL signal fall time Standard 20 + 0.1 CB 1000 ns t(SDA-R) SDA signal rise time Standard 20 + 0.1 CB 1000 ns t(SDA-F) SDA signal fall time Standard 20 + 0.1 CB 1000 t(P-SU) STOP condition setup time Standard 4 ns µs CB Capacitive load for SDA and SCL line 400 pF t(SP) Suppressed spike pulse duration 25 ns Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM5310 PCM5310 www.ti.com ............................................................................................................................................................................................ SLES244 – FEBRUARY 2009 REGISTER MAP The mode control register map is shown in Table 30. Each register includes an index (or address) indicated by the IDX[6:0] bits. Table 30. Mode Control Register Map REG HEX DESCRIPTION B7 B6 B5 B4 B3 B2 B1 B0 01 01h Reset function MRST SRST RSV (1) RSV RSV RSV RSV RSV 08 08h GPIO pin output control RSV RSV RSV RSV RSV 09 09h GPIO PORT-1 selection RSV RSV RSV GSL1[4:0] 10 0Ah GPIO PORT-2 selection RSV RSV RSV GSL2[4:0] 11 0Bh GPIO PORT-3 selection RSV RSV RSV GSL3[4:0] 12 0Ch Not assigned RSV RSV RSV RSV RSV RSV RSV RSV 13 0Dh Headphone short-circuit protection enable/disable RSV SRCR SHCR SPDR RSV SRCL SHCL SPDL 14 0Eh Headphone short-circuit protection detect time RSV RSV SDTR[1:0] RSV RSV SDTL[1:0] 15 0Fh Headphone short-circuit protection release time, auto control RSV SADR SRTR[1:0] RSV SADL SRTL[1:0] 16 10h Headphone short-circuit protection status read RSV RSV SSHR RSV RSV 17 11h Power up/down (bias) PBIS RSV RSV RSV RSV 18 12h Power up/down (analog), power up/down time RSV PABE PAFE PCOM RSV 19 13h Mute control linked to AMUTE pin MD12 MD34 MHPR MHPL ML2R 20 14h Analog input mux selection for ADC12 RSV 21 15h Analog input mux selection for ADC34 RSV 22 16h Analog input gain control for ADC12 RSV RSV AG1R[1:0] RSV RSV AG1L[1:0] 23 17h Analog input gain control for ADC12 RSV RSV AG2R[1:0] RSV RSV AG2L[1:0] 24 18h Analog output mux selection for line output 1 AL1R[3:0] 25 19h Analog output mux selection for line output 2 AL2R[3:0] AL2L[3:0] 26 1Ah Analog output mux selection for headphone output AHPR[3:0] AHPL[3:0] AX1R[2:0] RSV AX2R[2:0] RSV GPO2 GPO1 RSV PDCF[1:0] SSHL PDCS PDTM[2:0] ML2L ML1R ML1L AX1L[2:0] AX2L[2:0] AL1L[3:0] 27 1Bh Gain control for line output 28 1Ch 2.0 VRMS and 2.4 VRMS selection for line output RSV RSV RSV G242 RSV RSV 29 1Dh Clock halt detection control RSV RSV RSV RSV RSV RSV 30 1Eh Headphone output volume control HUPE RSV HSUR HSUL RSV RSV RSV HZRS 31 1Fh Headphone mute and volume level setting for R-channel HMUL HVOL[6:0] 32 20h Headphone mute and volume level setting for L-channel HMUR HVOR[6:0] 33 21h System clock output disable RSV RSV SC6D SC5D SC4D RSV SC2D SC1D 34 22h LRCK and BCK output disable at master mode RSV RSV LB6D LB5D LB4D LB3D LB2D LB1D 35 23h Read internal flag RSV RD12FS[2:0] RHMR RHML RSV RHPI 36 24h Read internal flag RSV RD34FS[2:0] RDM4 RDM3 RDM2 RDM1 37 25h Read internal flag RSV RA12FS[2:0] RAM4 RAM3 RAM2 RAM1 38 26h Read internal flag RSV RA34FS[2:0] RDZ4 RDZ3 RDZ2 RDZ1 39 27h Read internal flag CGLD RSV RHZR RHZL RAZ4 RAZ3 RAZ2 RAZ1 40 28h Digital attenuation and mute control for DAC12 D12E RSV DUC2 DUC1 RSV RSV RSV DZ12 41 29h Digital gain boost and digital soft mute for DAC12 RSV RSV RSV RSV 42 2Ah Digital attenuation level setting for DAC12 L-channel 43 2Bh Digital attenuation level setting for DAC12 R-channel 44 2Ch Master/slave interface format for DAC12 45 2Dh De-emphasis filter control for DAC12 RSV RSV 46 2Eh Power up/down, oversampling rate control for DAC12 PD12 RSV (1) GL2R[1:0] RSV GPO3 GL2L[1:0] GL1R[1:0] DB12[1:0] GL1L[1:0] RSV G241 ACTH CHDE DMU2 DMU1 DAT1[7:0] DAT2[7:0] DMS12[3:0] RSV RSV OV12[1:0] RSV RSV DFM12[1:0] DM12 RSV DF12[1:0] ZR12 RSV RSV RSV RSV = reserved (write '0' data). Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM5310 41 PCM5310 SLES244 – FEBRUARY 2009 ............................................................................................................................................................................................ www.ti.com Table 30. Mode Control Register Map (continued) REG HEX DESCRIPTION B7 B6 B5 B4 B3 B2 50 51 32h Digital attenuation and mute control for DAC34 D34E RSV DUC4 DUC3 RSV RSV 33h Digital gain boost and digital soft mute for DAC34 RSV RSV RSV RSV 52 34h Digital attenuation level setting for DAC34 L-channel 53 35h Digital attenuation level setting for DAC34 R-channel 54 36h Master/slave interface format for DAC34 55 37h De-emphasis filter control for DAC34 RSV RSV 56 38h Power up/down, oversampling rate control for DAC34 PD34 RSV 80 50h Digital attenuation and mute control for ADC12 A12E RSV AUC2 AUC1 81 51h Digital soft mute for ADC12 RSV FS12 RSV RSV 82 52h Digital attenuation level setting for ADC12 L-channel 83 53h Digital attenuation level setting for ADC12 R-channel 84 54h Master/slave interface format for ADC12 85 55h Power up/down for ADC12 PA12 90 5Ah Digital attenuation and mute control for ADC34 91 5Bh Digital soft mute for ADC34 92 5Ch Digital attenuation level setting for ADC34 L-channel 93 5Dh Digital attenuation level setting for ADC34 R-channel 94 5Eh Master/slave, interface format for ADC34 95 5Fh Power up/down for ADC34 101 65h LRCK/BCK selection of PORT-1 and PORT-2 102 66h DATA selection of PORT-1 and PORT-2 103 67h SCK selection of PORT-1 and PORT-2 104 68h LRCK/BCK selection of PORT-3 and PORT-4 105 69h DATA selection of PORT-3 and PORT-4 106 6Ah SCK selection of PORT-3 and PORT-4 107 6Bh LRCK/BCK selection of PORT-5 and PORT-6 108 6Ch DATA selection of PORT-5 and PORT-6 109 6Dh SCK selection of PORT-5 and PORT-6 110 6Eh LRCK/BCK selection of DAC12 and DAC34 D34LB[3:0] D12LB[3:0] 111 6Fh DATA selection of DAC12 and DAC34 D34DT[3:0] D12DT[3:0] 112 70h SCK selection of DAC12 and DAC34 RSV 113 71h Not assigned RSV RSV RSV RSV RSV RSV RSV RSV 114 72h Not assigned RSV RSV RSV RSV RSV RSV RSV RSV 115 73h Not assigned RSV RSV RSV RSV RSV RSV RSV RSV 116 74h LRCK/BCK selection of ADC12 and ADC34 117 75h SCK selection of ADC12 and ADC34 118 76h GPIO1 and GPIO2 audio data selection 42 DB34[1:0] B1 B0 RSV DZ34 DMU4 DMU3 DAT3[7:0] DAT4[7:0] DMS34[3:0] RSV RSV OV34[1:0] RSV RSV DFM34[1:0] DM34 RSV DF34[1:0] ZR34 RSV RSV RSV RSV RSV RSV AZ12 RSV RSV AMU2 AMU1 AAT1[7:0] AAT2[7:0] AMS12[3:0] HF12 RSV RSV RSV RSV RSV RSV A34E RSV AUC4 AUC3 RSV RSV RSV FS34 RSV RSV RSV RSV AFM12[1:0] RSV RSV RSV AZ34 AMU4 AMU3 AAT3[7:0] AAT4[7:0] AMS34[3:0] PA34 RSV RSV RSV HF34 RSV RSV RSV LBS2[3:0] DTS1[3:0] SCS2[2:0] RSV LBS4[3:0] DTS3[3:0] SCS4[2:0] RSV LBS6[3:0] DTS5[3:0] SCS6[2:0] RSV D34S[2:0] Submit Documentation Feedback D12S[2:0] A12LB[3:0] A34SC[2:0] GP2S[3:0] SCS5[2:0] RSV A34LB[3:0] RSV SCS3[2:0] LBS5[3:0] DTS6[3:0] RSV SCS1[2:0] LBS3[3:0] DTS4[3:0] RSV RSV LBS1[3:0] DTS2[3:0] RSV AFM34[1:0] RSV RSV A12SC[2:0] GP1S[3:0] Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM5310 PCM5310 www.ti.com ............................................................................................................................................................................................ SLES244 – FEBRUARY 2009 REGISTER DESCRIPTIONS Register 01 (01h) REG HEX DESCRIPTION B7 B6 B5 B4 B3 B2 B1 B0 01 01h Reset function MRST SRST RSV RSV RSV RSV RSV RSV MRST: Reset of All Registers Except for Other Internal Circuit This bit enables the reset signal for register data only. All registers are initialized to default data by setting MRST = '0'. After the reset sequence completes, MRST is automatically set to '1'. Defalut value: 1 0 Reset (set to '0' automatically after set to '1') 1 Not reset (default) SRST: Reset of All Internal Circuits Including All Registers This bit enables the internal system reset. All circuits including the registers are initialized by setting SRST = '0'. After completing the reset sequence, SRST is automatically set to '1'. Defalut value: 1 0 Reset (set to '0' automatically after set to '1') 1 Not reset (default) Register 08 (08h) REG HEX DESCRIPTION B7 B6 B5 B4 B3 B2 B1 B0 08 08h GPIO pin output control RSV RSV RSV RSV RSV GPO3 GPO2 GPO1 42 2Ah Digital attenuation level setting for DAC12 L-channel DAT1[7:0] GPO1: General-Purpose Output (pin 55) GPO2: General-Purpose Output (pin 56) GPO3: General-Purpose Output (pin 57) These three bits control the three GPIO pins that control external devices. These register data are effective by setting '01000', '01001', or '01010' to bits GSL1[4:0], GSL2[4:0] and GSL[4:0] of registers 9 to 11. Default value: 0 0 Low level output (default) 1 High level output Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM5310 43 PCM5310 SLES244 – FEBRUARY 2009 ............................................................................................................................................................................................ www.ti.com Registers 09-12 (09h-0Ch) REG HEX DESCRIPTION B7 B6 B5 B4 B3 B2 09 09h GPIO PORT-1 selection RSV RSV RSV GSL1[4:0] 10 0Ah GPIO PORT-2 selection RSV RSV RSV GSL2[4:0] 11 0Bh GPIO PORT-3 selection RSV RSV RSV 12 0Ch Not assigned RSV RSV RSV B1 B0 RSV RSV GSL3[4:0] RSV RSV RSV GSL1[4:0]: GPO1 Function Selection (pin 55) GSL2[4:0]: GPO2 Function Selection (pin 56) GSL3[4:0]: GPO3 Function Selection (pin 57) The three GPIO pins can be used as an input flag, output flag, and logic function, as shown in Table 31. Default value: 00000 Table 31. GPIO Functions GSL1-3[4:0] 44 GSL1[4:0]/GPIO1 GSL2[4:0]/GPIO2 GSL3[4:0]/GPIO3 00000 No assigned and input mode (default) No assigned and input mode (default) No assigned and input mode (default) 00001 Headphone insertion detection input Headphone insertion detection input Headphone insertion detection input 00010 Headphone insertion detection output Headphone insertion detection output Headphone insertion detection output 00011 Headphone short detection status L-channel Headphone short detection status L-channel Headphone short detection status L-channel 00100 Headphone short detection status R-channel Headphone short detection status R-channel Headphone short detection status R-channel 00101 Zero flag output for digital input (DAC12) Zero flag output for digital input (DAC12) Zero flag output for digital input (DAC12) 00110 Zero flag output for digital input (DAC34) Zero flag output for digital input (DAC34) Zero flag output for digital input (DAC34) 00111 Zero flag output for digital input (DAC12 and DAC34) Zero flag output for digital input (DAC12 and DAC34) Zero flag output for digital input (DAC12 and DAC34) 01000 Output register data to GPIO1 pin Output register data to GPIO1 pin Output register data to GPIO1 pin 01001 Output register data to GPIO2 pin Output register data to GPIO2 pin Output register data to GPIO2 pin 01010 Output register data to GPIO3 pin Output register data to GPIO3 pin Output register data to GPIO3 pin 01011 AND logic (GPIO1 = output, GPIO2,3 = input) AND logic (GPIO2 = output, GPIO1,3 = input) AND logic (GPIO2 = output, GPIO1,3 = input) 01100 NAND logic (GPIO1 = output, GPIO2,3 = input) NAND logic (GPIO2 = output, GPIO1,3 = input) NAND logic (GPIO2 = output, GPIO1,3 = input) 01101 OR logic (GPIO1 = output, GPIO2,3 = input) OR logic (GPIO2 = output, GPIO1,3 = input) OR logic (GPIO2 = output, GPIO1,3 = input) 01110 NOR logic (GPIO1 = output, GPIO2,3 = input) NOR logic (GPIO2 = output, GPIO1,3 = input) NOR logic (GPIO2 = output, GPIO1,3 = input) 01111 Buffer logic (GPIO1 = output, GPIO2 = input) Buffer logic (GPIO2 = output, GPIO1 = input) Buffer logic (GPIO2 = output, GPIO1 = input) 10000 Buffer logic (GPIO1 = output, GPIO3 = input) Buffer logic (GPIO2 = output, GPIO3 = input) Buffer logic (GPIO2 = output, GPIO3 = input) 10001 Inverter logic (GPIO1 = output, GPIO2 = input) Inverter logic (GPIO2 = output, GPIO1 = input) Inverter logic (GPIO2 = output, GPIO1 = input) 10010 Inverter logic (GPIO1 = output, GPIO3 = input) Inverter logic (GPIO2 = output, GPIO3 = input) Inverter logic (GPIO2 = output, GPIO3 = input) Others Reserved Reserved Reserved Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM5310 PCM5310 www.ti.com ............................................................................................................................................................................................ SLES244 – FEBRUARY 2009 Registers 13-16 (0Dh-10h) REG HEX DESCRIPTION B7 B6 B5 13 0Dh Headphone short-circuit protection enable/disable RSV 14 0Eh Headphone short-circuit protection detect time RSV RSV SDTR[1:0] 15 0Fh Headphone short-circuit protection release time, auto control RSV SADR SRTR[1:0] 16 10h Headphone short-circuit protection status read RSV RSV SRCR SHCR RSV B4 B3 B2 B1 B0 SPDR RSV SRCL SHCL SPDL RSV RSV SDTL[1:0] RSV SADL SRTL[1:0] RSV RSV SSHR RSV SSHL SRCR: Reset Short-Circuit Protection for Headphone Output R-Channel SRCL: Reset Short-Circuit Protection for Headphone Output L-Channel These bits initialize the short-circuit protection for the headphone outputs by setting SRCR = SRCL = '1'. After completing the initialization, the data of both registers are automatically set to '1'. Default value: 1 0 Reset (set to '1' automatically after set to '0') 1 Normal operation (default) SPDR: Short-Circuit Protection Disable for Headphone Output R-Channel SPDL: Short-Circuit Protection Disable for Headphone Output L-Channel These bits disable the short-circuit protection for the headphone outputs. Default value: 0 0 Enable (default) 1 Disable SDTR[1:0]: Short-Circuit Protection Detect Time Control for Headphone Output R-Channel SDTL[1:0]: Short-Circuit Protection Detect Time Control for Headphone Output L-Channel These bits define the continuous time until a short-circuit is detected on the headphone outputs. If the short-circuit time does not reach the defined time, the PCM5310 does not enable short-circuit protection. Default value: 11 00 4096 fS, 85.2 ms at fS = 48 kHz 01 8192 fS, 170.4 ms at fS = 48 kHz 10 16384 fS, 340.8 ms at fS = 48 kHz 11 32768 fS, 681.6 ms at fS = 48 kHz (default) SRTR[1:0]: Short-Circuit Protection Release Time Control for Headphone Output R-Channel SRTL[1:0]: Short-Circuit Protection Release Time Control for Headphone Output L-Channel These bits define the time until the short-circuit protection is released after detecting a short-circuit. Default value: 11 00 4096 fS, 85.2 ms at fS = 48 kHz 01 8192 fS, 170.4 ms at fS = 48 kHz 10 16384 fS, 340.8 ms at fS = 48 kHz 11 32768 fS, 681.6 ms at fS = 48 kHz (default) Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM5310 45 PCM5310 SLES244 – FEBRUARY 2009 ............................................................................................................................................................................................ www.ti.com SADR: Short-Circuit Protection Automatic Release Disable for Headphone Output R-Channel SADL: Short-Circuit Protection Automatic Release Disable for Headphone Output L-Channel These bits disable the automatic power down when a short-circuit is detected. Default value: 0 0 Enable (default) 1 Disable SSHR: Short-Circuit Status Read for Headphone Output R-Channel SSHL: Short-Circuit Status Read for Headphone Output L-Channel These bits are used to read the short-circuit status on the headphone through the I2C interface. If the status is '1', then the headphone output is in short-circuit. Default value: 0 0 Not shorted (default) 1 Short-circuit Registers 17 and 18 (11h and 12h) REG HEX DESCRIPTION B7 B6 B5 B4 B3 17 11h Power up/down (bias) PBIS RSV RSV RSV RSV 18 12h Power up/down (analog), power up/down time RSV PABE PAFE PCOM RSV B2 B1 PDCF[1:0] B0 PDCS PDTM[2:0] PBIS: Power Up/Down Control for Analog Bias Circuit This bit is used to power up/down the analog bias circuit. Default value: 1 0 Power up 1 Power down (default) PDCF[1:0]: Power Up/Down Time Control These bits set the power up/down time for each sampling rate. Set this register when the sampling rate is greater than 48 kHz at power up/down. Default value: 00 00 x1 (default) 01 x1/2 10 x1/4 11 Reserved PDCS: Power Up/Down Clock Selection The PCM5310 has six clock inputs for the four DAC and four ADC channels. The power on/off sequence starts using the DAC12 clock or the DAC34 clock. The appropriate clock source must be selected for the power up/down sequence. Default value: 0 46 0 Use the DAC12 clock for power up/down (default) 1 Use the DAC34 clock for power up/down Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM5310 PCM5310 www.ti.com ............................................................................................................................................................................................ SLES244 – FEBRUARY 2009 PAFE: Power Up/Down Control for Input Mux and Gain Amplifier This bit powers up/down the input mux and the gain amplifier. Default value: 1 0 Power up 1 Power down (default) PABE: Power Up/Down Control for Output Mux, Line Amp, and Headphone Amplifier This bit powers up/down the output mux, the line amplifiers, and the headphone amplifier. Default value: 1 0 Power up 1 Power down (default) PCOM: Power Up/Down Control for Common Voltage Circuit This bit powers up/down the common voltage circuit for the ADC and DAC channels. Default value: 1 0 Power up 1 Power down (default) PDTM[2:0]: Power Up/Down Time Control The power-up time selection for the PCM5310 can be from ground level to common voltage for analog outputs. The power-down time selection can be from the common voltage to ground level for analog outputs at the power on/off sequence. The time described in Figure 32 is defined for a 48-kHz sampling rate. Set bits PDCF[1:0] in Register 17 when the sampling rate is more than 48 kHz at the power up/down sequence. Default value: 001 PDTM[2:0] POWER-UP TIME 000 37.5 ms POWER-DOWN TIME 75 ms 001 75 ms (default) 150 ms 010 150 ms 300 ms 011 300 ms 600 ms 100 1000 ms 2000 ms 101 Reserved Reserved 110 Reserved Reserved 111 Reserved Reserved Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM5310 47 PCM5310 SLES244 – FEBRUARY 2009 ............................................................................................................................................................................................ www.ti.com Register 19 (13h) REG HEX DESCRIPTION B7 B6 19 13h Mute control linked to the AMUTE pin MD12 MD34 B5 B4 MHPR MHPL B3 B2 B1 B0 ML2R ML2L ML1R ML1L MD12: Mute Enable/Disable Linked to the AMUTE Pin for Digital Input (DAC12) MD34: Mute Enable/Disable Linked to the AMUTE Pin for Digital Input (DAC34) The PCM5310 has a mute control pin (AMUTE, 59 pin). When AMUTE = '1' and MD12 = '1' or MD34 = '1', the digital soft mute of digital input data is enabled. When AMUTE = '0', mute is disabled. Default value: 0 0 Mute disabled if the AMUTE pin is at a high or lo2w level (default) 1 Mute enabled if the AMUTE pin is at a high level MHPR: Mute Enable/Disable Linked AMUTE Pin for Headphone Output, R-Channel MHPL: Mute Enable/Disable Linked AMUTE Pin for Headphone Output, L-Channel The PCM5310 has a mute control pin (AMUTE, 59 pin). When AMUTE = '1' and MHPR = '1' or MHPL = '1', the analog mute for headphone outputs HPOL and HPOR is enabled. When AMUTE = '0', mute is disabled. Default value: 1 0 Mute disabled if the AMUTE pin is at a high or low level 1 Mute enabled if the AMUTE pin is at a high level (default) ML1R: Mute Enable/Disable Linked AMUTE Pin for Line Output 1, R-Channel ML1L: Mute Enable/Disable Linked AMUTE Pin for Line Output 1, L-Channel The PCM5310 has a mute control pin (AMUTE, 59 pin). When AMUTE = '1' and ML1R = '1' or ML1L = '1', the analog mute for line outputs LO1L and LO1R are enabled. When AMUTE = '0', mute is disabled. Default value: 1 0 Mute disabled if AMUTE pin is high or low level 1 Mute enabled if AMUTE pin is high level (default) MML2R: Mute Enable/Disable Linked AMUTE Pin for Line Output 2, R-Channel MML2L: Mute Enable/Disable Linked AMUTE Pin for Line Output 2, L-Channel The PCM5310 has a mute control pin (AMUTE, 59 pin). When AMUTE = '1' and ML2R = '1' or ML2L = '1', the analog mute for line outputs LO2L and LO2R are enabled. When AMUTE = '0', mute is disabled. Default value: 1 48 0 Mute disabled if AMUTE pin is high or low level 1 Mute enabled if AMUTE pin is high level (default) Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM5310 PCM5310 www.ti.com ............................................................................................................................................................................................ SLES244 – FEBRUARY 2009 Registers 20 and 21 (14h and 15h) REG HEX DESCRIPTION B7 B6 B5 B4 B3 B2 B1 20 14h Analog input mux selection for ADC12 RSV AX1R[2:0] RSV AX1L[2:0] 21 15h Analog input mux selection for ADC34 RSV AX2R[2:0] RSV AX2L[2:0] B0 AX1R[2:0]: Analog Input Mux Selection for ADC12, R-Channel AX1L[2:0]: Analog Input Mux Selection for ADC12, L-Channel AX2R[2:0]: Analog Input Mux Selection for ADC34, R-Channel AX2L[2:0]: Analog Input Mux Selection for ADC34, L-Channel The PCM5310 has six stereo inputs that can select one stereo input for each ADC. It is recommended to use the digital soft mute to reduce audible noise when the analog inputs are changed; see Figure 44 for details. Default value: 000 000 No connection (default) 001 AIN1L or AIN1R 010 AIN2L or AIN2R 011 AIN3L or AIN3R 100 AIN4L or AIN4R 101 AIN5L or AIN5R 110 AIN6L or AIN6R Others Reserved Registers 22 and 23 (16h and 17h) REG HEX DESCRIPTION B7 B6 B3 B2 22 16h Analog input gain control for ADC12 RSV RSV B5 AG1R[1:0] B4 RSV RSV B1 AG1L[1:0] B0 23 17h Analog input gain control for ADC34 RSV RSV AG2R[1:0] RSV RSV AG2L[1:0] AG1R[1:0]: Analog Input Gain Control for ADC12, R-Channel AG1L[1:0]: Analog Input Gain Control for ADC12, L-Channel AG2R[1:0]: Analog Input Gain Control for ADC34, R-Channel AG2L[1:0]: Analog Input Gain Control for ADC34, L-Channel The PCM5310 has analog gain amplifiers in front of each ADC input that can be programmed to between 0 dB to +9 dB in 3-dB steps; refer to Figure 28 for details. Default value: 00 00 0 dB (default) 01 3 dB 10 6 dB 11 9 dB Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM5310 49 PCM5310 SLES244 – FEBRUARY 2009 ............................................................................................................................................................................................ www.ti.com Registers 24-26 (18h-1Ah) REG HEX DESCRIPTION B7 B6 B5 B4 B3 B2 B1 24 18h Analog output mux selection for line output 1 AL1R[3:0] 25 19h Analog output mux selection for line output 2 AL2R[3:0] AL2L[3:0] 26 1Ah Analog output mux selection for headphone output AHPR[3:0] AHPL[3:0] B0 AL1L[3:0] AL1R[3:0]: Analog Output Mux Selection for Line Output 1, R-Channel AL1L[3:0]: Analog Output Mux Selection for Line Output 1, L-Channel AL2R[3:0]: Analog Output Mux Selection for Line Output 2, R-Channel AL2L[3:0]: Analog Output Mux Selection for Line Output 2, L-Channel AHPR[3:0]: Analog Output Mux Selection for Headphone Output, R-Channel AHPL[3:0]: Analog Output Mux Selection for Headphone Output, L-Channel Analog outputs LO1L/LO1R, LO2L/LO2R, and HPOL/HPOR can be selected as one of all the analog inputs and DAC outputs; see Figure 29 for details. Default value: 0000 0000 No connection (default) 0001 AIN1L or AIN1R 0010 AIN2L or AIN2R 0011 AIN3L or AIN3R 0100 AIN4L or AIN4R 0101 AIN5L or AIN5R 0110 AIN6L or AIN6R 0111 DAC12-L-channel or DAC12-R-channel 1000 DAC34-L-channel or DAC34-R-channel Others Reserved Register 27 (1Bh) REG HEX DESCRIPTION 27 1Bh Gain control for line output B7 B6 GL2R[1:0] B5 B4 GL2L[1:0] B3 B2 GL1R[1:0] B1 B0 GL1L[1:0] GL2R[1:0]: Gain Control for Line Output 2, R-Channel GL2L[1:0]: Gain Control for Line Output 2, L-Channel GL1R[1:0]: Gain Control for Line Output 1, R-Channelt GL1L[1:0]: Gain Control for Line Output 1, L-Channel The gain level for line outputs LO1L, LO1R, LO2L, and LO2R can be each be selected as 0 dB, –0.5 dB, or –1.0 dB. Default value: 00 50 00 0 dB (default) 01 –0.5 dB 10 –1.0 dB 11 0 dB when selecting analog input to line output Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM5310 PCM5310 www.ti.com ............................................................................................................................................................................................ SLES244 – FEBRUARY 2009 Register 28 (1Ch) REG HEX DESCRIPTION B7 B6 B5 B4 B3 B2 B1 B0 28 1Ch 2.0 Vrms and 2.4 Vrms selection for line output RSV RSV RSV G242 RSV RSV RSV G241 G242: 2-VRMS or 2.4-VRMS Output Mode Selection for Line Output 2 G241: 2-VRMS or 2.4-VRMS Output Mode Selection for Line Output 1 The line outputs can drive a 2-VRMS or 2.4-VRMS output with 10 kΩ. The 2.4-VRMS setting is recommend for use when the equipment requires greater than 2-VRMS output. Default value: 0 0 2 VRMS (default) 1 2.4 VRMS Register 29 (1Dh) REG HEX DESCRIPTION B7 B6 B5 B4 B3 B2 B1 B0 29 1Dh Clock halt detection control RSV RSV RSV RSV RSV RSV ACTH CHDE ACTH: Activate Control for Clock Halt Detection CHDE: Enable Clock Halt Detection ACTH is used to control the power up/down for clock halt detection and CHDE is used to enable it. Setting ACTH = CHDE = '1' activates and enables clock halt detection. Clock halt detection can reduce audible noise. The analog outputs are muted when the clock input to DAC12 and DAC34 is suddenly stopped. Default value: 0 ACTH = 0 Deactivate clock halt detection (default) ACTH = 1 Activate clock halt detection CHDE = 0 Clock halt detection disabled (default) CHDE = 1 Clock halt detection enabled Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM5310 51 PCM5310 SLES244 – FEBRUARY 2009 ............................................................................................................................................................................................ www.ti.com Register 30 (1Eh) REG HEX DESCRIPTION B7 B6 B5 B4 B3 B2 B1 B0 30 1Eh Headphone output volume control HUPE RSV HSUR HSUL RSV RSV RSV HZRS HUPE: Headphone Volume Update Control Enable HSUR: Headphone Volume Setting Update for Headphone Output, R-Channel HSUL: Headphone Volume Setting Update for Headphone Output, L-Channel HZRS: Headphone Volume Zero Cross Enable The volume level of the headphone output can be changed independently to any level by setting HMUL/HMUR and HVOL[6:0]/HVOR[6:0] when HUPE = '0'. When HUPE = '1', the volume level is changed to any level at the same time when HSUR = '1' or HSUL = '1'. Both bits are automatically set to '0' after being set to '1'. HSUR and HSUL must be set to '1' for every volume level setting during HUPE = '1'. Default value of HUPE and HZRS: 1. Default value of HSUR and HSUL: 0 HUPE = 0 Headphone volume update control disable HUPE = 1 Headphone volume update control enable (default) HSUR, HSUL = 0 No update volume setting data (default) HSUR, HSUL = 1 Update volume setting data (set to '0' automatically after setting to '1') HZRS = 0 Headphone volume zero crossing disable HZRS = 1 Headphone volume zero crossing enable (default) Register 31 and 32 (1Fh and 20h) REG HEX DESCRIPTION B7 31 1Fh Headphone mute and volume level setting for R-channel B6 B5 B4 B3 HMUL HVOL[6:0] 32 20h Headphone mute and volume level setting for L-channel HMUR HVOR[6:0] B2 B1 B0 HMUL: Headphone Volume Mute Control for L-Channel HMUR: Headphone Volume Mute Control for R-Channel The headphone output can be independently muted to zero level when HMUL and HMUR = '1'. These settings take precedence over volume level settings by HVOL and HVOR. The headphone output may have audible zipper noise while changing levels. This noise can be reduced by selecting zero-crossing detection (Register 30, HZRS). Default value: 0 0 Mute disabled (default) 1 Mute enabled HVOL[6:0]: Headphone Volume Level Control for L-Channel HVOR[6:0]: Headphone Volume Level Control for R-Channel The headphone output can be independently programmed to between 12 dB to –70 dB in 1-dB steps. The headphone output may have audible zipper noise while changing levels. This noise can be reduced by selecting zero-crossing detection (Register 30, HZRS). Default value: 010 1101 52 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM5310 PCM5310 www.ti.com ............................................................................................................................................................................................ SLES244 – FEBRUARY 2009 Table 32. Headphone Volume Level Control HP VOLUME LEVEL CONTROL HVOL[6:0] HVOR[6:0] HP VOLUME LEVEL CONTROL HVOL[6:0] HVOR[6:0] HP VOLUME LEVEL CONTROL HVOL[6:0] HVOR[6:0] 111 1111 7F 12 dB 110 0010 62 –17 dB 100 0101 45 –46 dB 111 1110 7E 11 dB 110 0001 61 –18 dB 100 0100 44 –47 dB 111 1101 7D 10 dB 110 0000 60 –19 dB 100 0011 43 –48 dB 111 1100 7C 9 dB 101 1111 5F –20 dB 100 0010 42 –49 dB 111 1011 7B 8 dB 101 1110 5E –21 dB 100 0001 41 –50 dB 111 1010 7A 7 dB 101 1101 5D –22 dB 100 0000 40 –51 dB 111 1001 79 6 dB 101 1100 5C –23 dB 011 1111 3F –52 dB 111 1000 78 5 dB 101 1011 5B –24 dB 011 1110 3E –53 dB 111 0111 77 4 dB 101 1010 5A –25 dB 011 1101 3D –54 dB 111 0110 76 3 dB 101 1001 59 –26 dB 011 1100 3C –55 dB 111 0101 75 2 dB 101 1000 58 –27 dB 011 1011 3B –56 dB 111 0100 74 1 dB 101 0111 57 –28 dB 011 1010 3A –57 dB 111 0011 73 0 dB 101 0110 56 –29 dB 011 1001 39 –58 dB 1110010 72 –1 dB 101 0101 55 –30 dB 011 1000 38 –59 dB 111 0001 71 –2 dB 101 0100 54 –31 dB 011 0111 37 –60 dB 111 0000 70 –3 dB 101 0011 53 –32 dB 011 0110 36 –61 dB 110 1111 6F –4 dB 101 0010 52 –33 dB 011 0101 35 –62 dB 110 1110 6E –5 dB 101 0001 51 –34 dB 011 0100 34 –63 dB 110 1101 6D –6 dB 101 0000 50 –35 dB 011 0011 33 –64 dB 110 1100 6C –7 dB 100 1111 4F –36 dB 011 0010 32 –65 dB 110 1011 6B –8 dB 100 1110 4E –37 dB 011 0001 31 –66 dB 110 1010 6A –9 dB 100 1101 4D –38 dB 011 0000 30 –67 dB 110 1001 69 –10 dB 100 1100 4C –39 dB 010 1111 2F –68 dB 110 1000 68 –11 dB 100 1011 4B –40 dB 010 1110 2E –69 dB 110 0111 67 –12 dB 100 1010 4A –41 dB 010 1101 2D –70 dB (default) 110 0110 66 –13 dB 100 1001 49 –42 dB 110 0101 65 –14 dB 100 1000 48 –43 dB 110 0100 64 –15 dB 100 0111 47 –44 dB 010 1100 ⋮ 000 0000 2C ⋮ 00 Mute 110 0011 63 –16 dB 100 0110 46 –45 dB Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM5310 53 PCM5310 SLES244 – FEBRUARY 2009 ............................................................................................................................................................................................ www.ti.com Register 33 (21h) REG HEX DESCRIPTION B7 B6 B5 B4 B3 B2 B1 B0 33 21h System clock output disable RSV RSV SC6D SC5D SC4D SC3D SC2D SC1D SC6D: SCK6 Output Disable SC5D: SCK5 Output Disable SC4D: SCK4 Output Disable SC3D: SCK3 Output Disable SC2D: SCK2 Output Disable SC1D: SCK1 Output Disable These bits are used to disable (low-level output) the clock ports (SCK1, SCK2, SCK3, SCK4, SCK5 and SCK6) in output mode. It is necessary to use these bits with Register 103 (SCS2[2:0], SCS1[2:0]), Register 106 (SCS4[2:0], SCS3[2:0]), and Register 109 (SCS6[2:0], SCS5[2:0]). Each clock port is set to input mode at the default setting. Default value: 1 0 Normal output 1 Disable, low-level output (default) Register 34 (22h) REG HEX DESCRIPTION B7 B6 B5 B4 B3 B2 B1 B0 34 22h LRCK and BCK output disable at master mode RSV RSV LB6D LB5D LB4D LB3D LB2D LB1D LB6D: LRCK6 and BCK6 Output Disable LB5D: LRCK5 and BCK5 Output Disable LB4D: LRCK4 and BCK4 Output Disable LB3D: LRCK3 and BCK3 Output Disable LB2D: LRCK2 and BCK2 Output Disable LB1D: LRCK1 and BCK1 Output Disable These bits are used to disable (low-level output) the LRCK/BCK ports (LRCK1/BCK1, LRCK2/BCK2, LRCK3/BCK3, LRCK4/BCK4, LRCK5/BCK5 and LRCK6/BCK6) in output mode. It is necessary to use these bits with Register 101 (LBS2[3:0], LBS1[3:0]), Register 104 (LBS4[3:0], LBS3[3:0]), and Register 107 (LBS6[3:0], LBS5[3:0]). Each LRCK/BCK port is set to input mode at the default setting. Default value: 1 54 0 Normal output 1 Disable, low-level output (default) Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM5310 PCM5310 www.ti.com ............................................................................................................................................................................................ SLES244 – FEBRUARY 2009 Registers 35-39 (23h-27h) REG HEX DESCRIPTION B7 B6 B5 35 23h Read internal flag RSV RD12FS[2:0] RHMR RHML 36 24h Read internal flag RSV RD34FS[2:0] RDM4 RDM3 RDM2 RDM1 37 25h Read internal flag RSV RA12FS[2:0] RAM4 RAM3 RAM2 RAM1 38 26h Read internal flag RSV RA34FS[2:0] RDZ4 RDZ3 RDZ2 RDZ1 39 27h Read internal flag CGLD RAZ4 RAZ3 RAZ2 RAZ1 RSV RHZR B4 RHZL B3 B2 B1 B0 RSV RHPI RD12FS[2:0]: Read System Clock fS Rate Detection Status for DAC12 RD34FS[2:0]: Read System Clock fS Rate Detection Status for DAC34 RA12FS[2:0]: Read System Clock fS Rate Detection Status for ADC12 RA34FS[2:0]: Read System Clock fS Rate Detection Status for ADC34 The PCM5310 includes automatic clock rate detection, which provides a divided clock to the ADC and DAC channels. The result of the detected clock rate can be read through the I2C port. Default value: 111 000 Reserved 001 128 fS (default) 010 192 fS 011 256 fS 100 384 fS 101 512 fS 110 768 fS 111 Reserved (default) RHMR: Read Mute Status for Headphone Output R-Channel RHML: Read Mute Status for Headphone Output L-Channel These bits are used to read the mute status of the headphone output. The results can be read through the I2C port. Default value: 0 0 Mute disabled (default) 1 Mute enabled RHPI: Read Headphone Insertion Detection Status for Headphone Output This bit is used to read the headphone output insertion detection status through the I2C port. Headphone insertion is set by Register 09 to Register 11 (GSL1[4:0], GSL2[4:0], GSL3[4:0]) with the GPIO port. Default value: 0 0 Headphone not inserted (default) 1 Headphone inserted Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM5310 55 PCM5310 SLES244 – FEBRUARY 2009 ............................................................................................................................................................................................ www.ti.com RDM4: Read Digital Mute Status for DAC34, R-Channel RDM3: Read Digital Mute Status for DAC34, L-Channel RDM2: Read Digital Mute Status for DAC12, R-Channel RDM1: Read Digital Mute Status for DAC12, L-Channel These bits are used to read the digital soft mute status for each DAC channel through the I2C port. Default value: 1 0 Mute disabled 1 Mute enabled (default) RAM4: Read Digital Mute Status for ADC34, R-Channel RAM3: Read Digital Mute Status for ADC34, L-Channel RAM2: Read Digital Mute Status for ADC12, R-Channel RAM1: Read Digital Mute Status for ADC12, L-Channel These bits are used to read the digital soft mute status for each ADC channel through the I2C port. Default value: 1 0 Mute disabled 1 Mute enabled (default) RRHZR: Read Volume Zero Cross Time Out Status for Headphone, R-Channel RHZL: Read Volume Zero Cross Time Out Status for Headphone, L-Channel RDZ4: Read Digital Attenuation/Mute Zero Cross Timeout Status for DAC34, R-Channel RDZ3: Read Digital Attenuation/Mute Zero Cross Timeout Status for DAC34, L-Channel RDZ2: Read Digital Attenuation/Mute Zero Cross Timeout Status for DAC12, R-Channel RDZ1: Read Digital Attenuation/Mute Zero Cross Timeout Status for DAC12, L-Channel RAZ4: Read Digital Attenuation/Mute Zero Cross Timeout Status for ADC34, R-Channel RAZ3: Read Digital Attenuation/Mute Zero Cross Timeout Status for ADC34, L-Channel RAZ2: Read Digital Attenuation/Mute Zero Cross Timeout Status for ADC12, R-Channel RAZ1: Read Digital Attenuation/Mute Zero Cross Timeout Status for ADC12, L-Channel These bits are used to read the zero-crossing timeout status of digital soft mute and digital attenuation for each ADCs and DACs channel and for headphone output volume through the I2C port. Default value: 0 0 not timed out (default) 1 Timed out CGLD: Glitch Reduction Disable when Changing Clock Source This bit disables the glitch reduction circuit, which reduces audible pop noise when changing the clock input from any SCKx to SCKx. Default value: 0 56 0 Enabled (default) 1 Disabled Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM5310 PCM5310 www.ti.com ............................................................................................................................................................................................ SLES244 – FEBRUARY 2009 Registers 40 and 41 (28h and 29h) REG HEX DESCRIPTION B7 B6 B5 B4 B3 B2 40 41 28h Digital attenuation and mute control for DAC12 D12E RSV DUC2 DUC1 RSV RSV 29h Digital gain boost and digital soft mute for DAC12 RSV RSV RSV RSV DB12[1:0] B1 B0 RSV DZ12 DMU2 DMU1 D12E: Digital Attenuation and Mute Update Control Enable for DAC12 DUC2: Digital Attenuation and Mute Setting Update for DAC12, R-Channel DUC1: Digital Attenuation and Mute Setting Update for DAC12, L-Channel The digital attenuation and mute levels of DAC12 can be changed independently to any level by setting bits DMU2 and DMU1 of Register 41, bits DAT1[7:0] of Register 42, and bits DAT2[7:0] of Register 43 when D12E = '0'. When D12E = '1', the level is changed to any level at the same time when DUC2 = '1' or DUC1 = '1'. Both bits are automatically set to '0' after being set to '1'. DUC2 and DUC1 must be set to '1' for every volume level setting while HUPE = '1'. Default value of D12E: 1. Default value of DUC2 and DUC1: 0 D12E = 0 Digital attenuation and mute update control disabled D12E = 1 Digital attenuation and mute update control enabled (default) DUC2, DUC1 = 0 No update level (default) DUC2, DUC1 = 1 Update level (set to '0' automatically after setting to '1') DZ12: Digital Attenuation and Mute Zero Crossing Enable for DAC12 This bit enables zero-crossing detection, which reduces zipper noise while the DAC digital attenuator and mute settings are being changed. If no zero-crossing data are input for a 512/fS period (10.6 ms at a 48-kHz sampling rate), then a timeout occurs and the PCM5310 volume level changes. Zero-crossing detection cannot be used with continuous zero and dc data. Default value: 1 0 Disabled 1 Enabled (default) DB12[1:0]: Digital Gain Boost for DAC12 These bits boost the gain for the digital data input to the DAC12 channels before the digital attenuation. Default value: 00 00 0dB (default) 01 6 dB 10 12 dB 11 18 dB DMU2: Digital Mute Control for DAC12, R-Channel DMU1: Digital Mute Control for DAC12, L-Channel The PCM5310 can independently mute the DACs digital input data to zero level when DMU2 and DMU1 = '1'. These settings take precedence over the attenuation level settings set by bits DAT1[7:0] and DAT2[7:0] in regsiter 42. The analog outputs may have audible zipper noise while changing levels. This noise can be reduced by selecting zero-crossing detection (Register 40, DZ12). Default value: 0 0 Mute disabled (default) 1 Mute enabled Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM5310 57 PCM5310 SLES244 – FEBRUARY 2009 ............................................................................................................................................................................................ www.ti.com Registers 42 and 43 (2Ah and 2Bh) REG HEX DESCRIPTION B7 B6 B5 B4 B3 42 2Ah Digital attenuation level setting for DAC12 L-channel DAT1[7:0] 43 2Bh Digital attenuation level setting for DAC12 R-channel DAT2[7:0] B2 B1 B0 DAT1[7:0]: Digital Attenuation Setting for DAC12, L-Channel DAT2[7:0]: Digital Attenuation Setting for DAC12, R-Channel The digital attenuator of DAC12 can be independently set from 0 dB to –100 dB in 0.5-dB steps. The DAC12 output may have audible zipper noise while changing levels. This noise can be reduced by selecting zero crossing detection (Register 40, DZ12). Default value : 1111 1111 Table 33. Digital Attenuation Level Setting for DAC12 DAT1[7:0] DAT2[7:0] DIGITAL ATT LEVEL SETTING DAT1[7:0] DAT2[7:0] DIGITAL ATT LEVEL SETTING DAT1[7:0] DAT2[7:0] DIGITAL ATT LEVEL SETTING DAT1[7:0] DAT2[7:0] DIGITAL ATT LEVEL SETTING 1111 1111 FF 0 dB (default) 1100 1100 CC –25.5 dB 1001 1001 99 – 51 dB 0110 0110 66 1111 1110 FE –0.5 dB 1100 1011 CB –26 dB 1001 1000 98 –51.5 dB 0110 0101 65 –77 dB 1111 1101 FD –1 dB 1100 1010 CA –26.5 dB 1001 0111 97 –52 dB 0110 0100 64 –77.5 dB 1111 1100 FC –1.5 dB 1100 1001 C9 –27 dB 1001 0110 96 –52.5 dB 0110 0011 63 –78 dB 1111 1011 FB –2 dB 1100 1000 C8 –27.5 dB 1001 0101 95 –53 dB 0110 0010 62 –78.8 dB 1111 1010 FA –2.5 dB 1100 0111 C7 –28 dB 1001 0100 94 –53.5 dB 0110 0001 61 –79 dB 1111 1001 F9 –3 dB 1100 0110 C6 –28.5 dB 1001 0011 93 –54 dB 0110 0000 60 –79.5 dB 1111 1000 F8 –3.5 dB 1100 0101 C5 –29 dB 1001 0010 92 –54.5 dB 0101 1111 5F –80 dB 1111 0111 F7 –4 dB 1100 0100 C4 –29.5 dB 1001 0001 91 –55 dB 0101 1110 5E –80.5 dB 1111 0110 F6 –4.5 dB 1100 0011 C3 –30 dB 1001 0000 90 –55.5 dB 0101 1101 5D –81 dB 1111 0101 F5 –5 dB 1100 0010 C2 –30.5 dB 1000 1111 8F –56 dB 0101 1100 5C –81.5 dB 1111 0100 F4 –5.5 dB 1100 0001 C1 –31 dB 1000 1110 8E –56.5 dB 0101 1011 5B –82 dB 1111 0011 F3 –6 dB 1100 0000 C0 –31.5 dB 1000 1101 8D –57 dB 0101 1010 5A –82.5 dB 1111 0010 F2 –6.5 dB 1011 1111 BF –32 dB 1000 1100 8C –57.5 dB 0101 1001 59 –83 dB 1111 0001 F1 –7 dB 1011 1110 BE –32.5 dB 1000 1011 8B –58 dB 0101 1000 58 –83.5 dB 1111 0000 F0 –7.5 dB 1011 1101 BD –33 dB 1000 1010 8A –58.5 dB 0101 0111 57 –84 dB 1110 1111 EF –8 dB 1011 1100 BC –33.5 dB 1000 1001 89 –59 dB 0101 0110 56 –84.5 dB 1110 1110 EE –8.5 dB 1011 1011 BB –34 dB 1000 1000 88 –59.5 dB 0101 0101 55 –85 dB 1110 1101 ED –9 dB 1011 1010 BA –34.5 dB 1000 0111 87 –60 dB 0101 0100 54 –85.5 dB 1110 1100 EC –9.5 dB 1011 1001 B9 –35 dB 1000 0110 86 –60.5 dB 0101 0011 53 –86 dB 1110 1011 EB –10 dB 1011 1000 B8 –35.5 dB 1000 0101 85 –61 dB 0101 0010 52 –86.5 dB 1110 1010 EA –10.5 dB 1011 0111 B7 –36 dB 1000 0100 84 –61.5 dB 0101 0001 51 –87 dB 1110 1001 E9 –11 dB 1011 0110 B6 –36.5 dB 1000 0011 83 –62 dB 0101 0000 50 –87.5 dB 1110 1000 E8 –11.5 dB 1011 0101 B5 –37 dB 1000 0010 82 –62.5 dB 0100 1111 4F –88 dB 1110 0111 E7 –12 dB 1011 0100 B4 –37.5 dB 1000 0001 81 –63 dB 0100 1110 4E –88.5 dB 1110 0110 E6 –12.5 dB 1011 0011 B3 –38 dB 1000 0000 80 –63.5 dB 0100 1101 4D –89 dB 1110 0101 E5 –13 dB 1011 0010 B2 –38.5 dB 0111 1111 7F –64 dB 0100 1100 4C –89.5 dB 1110 0100 E4 –13.5 dB 1011 0001 B1 –39 dB 0111 1110 7E –64.5 dB 0100 1011 4B –90 dB 1110 0011 E3 –14 dB 1011 0000 B0 –39.5 dB 0111 1101 7D –65 dB 0100 1010 4A –90.5 dB 1110 0010 E2 –14.5 dB 1010 1111 AF –40 dB 0111 1100 7C –65.5 dB 0100 1001 49 –91 dB 1110 0001 E1 –15 dB 1010 1110 AE –40.5 dB 0111 1011 7B –66 dB 0100 1000 48 –91.5 dB 1110 0000 E0 –15.5 dB 1010 1101 AD –41 dB 0111 1010 7A –66.5 dB 0100 0111 47 –92 dB 1101 1111 DF –16 dB 1010 1100 AC –41.5 dB 0111 1001 79 –67 dB 0100 0110 46 –92.5 dB 58 Submit Documentation Feedback –76.5 dB Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM5310 PCM5310 www.ti.com ............................................................................................................................................................................................ SLES244 – FEBRUARY 2009 Table 33. Digital Attenuation Level Setting for DAC12 (continued) DIGITAL ATT LEVEL SETTING DAT1[7:0] DAT2[7:0] 1101 1110 DE 1101 1101 1101 1100 DAT1[7:0] DAT2[7:0] DIGITAL ATT LEVEL SETTING DAT1[7:0] DAT2[7:0] –16.5 dB 1010 1011 AB –42 dB 0111 1000 78 DD –17 dB 1010 1010 AA –42.5 dB 0111 0111 DC –17.5 dB 1010 1001 A9 –43 dB 0111 0110 1101 1011 DB –18 dB 1010 1000 A8 –43.5 dB 1101 1010 DA –18.5 dB 1010 0111 A7 1101 1001 D9 –19 dB 1010 0110 1101 1000 D8 –19.5 dB 1010 0101 1101 0111 D7 –20 dB 1101 0110 D6 1101 0101 D5 1101 0100 D4 1101 0011 1101 0010 DIGITAL ATT LEVEL SETTING DAT1[7:0] DAT2[7:0] DIGITAL ATT LEVEL SETTING –67.5 dB 0100 0101 45 –93 dB 77 –68 dB 0100 0100 44 –93.5 dB 76 –68.5 dB 0100 0011 43 –94 dB 0111 0101 75 –69 dB 0100 0010 42 –94.5 dB –44 dB 0111 0100 74 –69.5 dB 0100 0001 41 –95 dB A6 –44.5 dB 0111 0011 73 –70 dB 0100 0000 40 –95.5 dB A5 –45 dB 0111 0010 72 –70.5 dB 0011 1111 3F –96 dB 1010 0100 A4 –45.5 dB 0111 0001 71 –71 dB 0011 1110 3E –96.5 dB –20.5 dB 1010 0011 A3 –46 dB 0111 0000 70 –71.5 dB 0011 1101 3D –97 dB –21 dB 1010 0010 A2 –46.5 dB 0110 1111 6F –72 dB 0011 1100 3C –97.5 dB –21.5 dB 1010 0001 A1 –47 dB 0110 1110 6E –72.5 dB 0011 1011 3B –98 dB D3 –22 dB 1010 0000 A0 –47.5 dB 0110 1101 6D –73 dB 0011 1010 3A –98.5 dB D2 –22.5 dB 1001 1111 9F –48 dB 0110 1100 6C –73.5 dB 0011 1001 39 –99 dB 1101 0001 D1 –23 dB 1001 1110 9E –48.5 dB 0110 1011 6B –74 dB 0011 1000 38 –99.5 dB 1101 0000 D0 –23.5 dB 1001 1101 9D –49 dB 0110 1010 6A –74.5 dB 0011 0111 37 –100 dB 0011 0110 ⋮ 0000 0000 36 ⋮ 00 Mute 1100 1111 CF –24 dB 1001 1100 9C –49.5 dB 0110 1001 69 –75 dB 1100 1110 CE –24.5 dB 1001 1011 9B –50 dB 0110 1000 68 –75.5 dB 1100 1101 CD –25 dB 1001 1010 9A –50.5 dB 0110 0111 67 –76 dB Registers 44 and 45 (2Ch and 2Dh) REG HEX DESCRIPTION 44 2Ch Master/slave interface format for DAC12 B7 45 2Dh De-emphasis filter control for DAC12 B6 B5 B4 DMS12[3:0] RSV RSV RSV RSV B3 B2 RSV RSV DFM12[1:0] B1 B0 DM12 RSV DF12[1:0] DMS12[3:0]: Master/Slave Audio Interface Setting for DAC12 These bits set the master or slave mode. DAC12 receives LRCK and BCK from PORT-1, PORT-2, PORT-3, PORT-4, PORT-5 or PORT-6 in slave mode, and generates LRCK and BCK from SCK in master mode. Default value: 1000 DMS12[3:0] MASTER/SLAVE AUDIO INTERFACE SETTING FOR MASTER/SLAVE AUDIO INTERFACE SETTING FOR DAC12 DMS12[3:0] DAC12 0000 Reserved 1000 Slave and system clock fS auto-detect mode (default) 0001 Master and system clock 768 fS 1001 Slave and system clock 768 fS 0010 Master and system clock 512 fS 1010 Slave and system clock 512 fS 0011 Master and system clock 384 fS 1011 Slave and system clock 384 fS 0100 Master and system clock 256 fS 1100 Slave and system clock 256 fS 0101 Master and system clock 192 fS 1101 Slave and system clock 192 fS 0110 Master and system clock 128 fS 1110 Slave and system clock 128 fS 0111 Reserved 1111 Reserved Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM5310 59 PCM5310 SLES244 – FEBRUARY 2009 ............................................................................................................................................................................................ www.ti.com DFM12[1:0]: Audio Interface Format for DAC12 These bits select the DAC12 audio data format as I2S, right-justified, or left-justified. Default value: 00 00 16 to 24 bits, I2S (default) 01 16 to 24 bits, left-justified 10 24 bits, right-justified 11 16 bits, right-justified DM12: De-Emphasis Filter Enable for DAC12 This bit enables the DAC12 de-emphasis filter. The frequency can be selected by setting bits DF12[1:0] of Register 45. Default value: 0 0 Disable (default) 1 Enable DF12[1:0]: De-Emphasis Filter Sampling Rate Selection for DAC12 A digital de-emphasis filter is in front of the interpolation filter. One of three de-emphasis filters can be selected corresponding to the sampling rate: 32 kHz, 44.1 kHz, or 48 kHz. Default value: 00 00 44.1 kHz (default) 01 48 kHz 10 32 kHz 11 Reserved Register 46 (2Eh) REG HEX DESCRIPTION B7 B6 46 2Eh Power up/down, oversampling rate control for DAC12 PD12 RSV B5 B4 OV12[1:0] B3 B2 B1 B0 ZR12 RSV RSV RSV PD12: Power Up/Down Control for DAC12 This bit controls the power up/down for DAC12, including the interpolation filter. Default value: 1 0 Power up 1 Power down (default) OV12[1:0]: Oversampling Rate Control for DAC12 These bits are used to control the oversampling rate of the DAC12 delta-sigma modulator. Default value: 01 SYSTEM CLOCK RATE OV12 128 fS, 192 fS 256 fS, 384 fS 00 16 fS 32 fS 64 fS 01 (default) 32 fS 64 fS 128 fS — — 32 fS 128 fS (1) 128 fS (1) 10 11 (1) 60 128 fS, 192 fS Less than fS = 48 kHz Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM5310 PCM5310 www.ti.com ............................................................................................................................................................................................ SLES244 – FEBRUARY 2009 ZR12: Zero Flag Reverse This bit reverses the polarity of the zero flag output. The zero flag goes from low to high after the digital input data are continuously zero during 1024 fS when ZR12 = '0'. The zero flag can output from the GPIO pins by setting Registers 9 to 11 (GSL1[4:0], GSL2[4:0], GSL3[4:0]). Default value: 0 0 Buffered output (default) 1 Inverted output Registers 50 and 51 (32h and 33h) REG HEX DESCRIPTION B7 B6 B5 B4 B3 B2 B1 B0 50 32h Digital attenuation and mute control for DAC34 D34E RSV DUC4 DUC3 RSV RSV RSV DZ34 51 33h Digital gain boost and digital soft mute for DAC34 RSV RSV RSV RSV DB34[1:0] DMU4 DMU3 D34E: Digital Attenuation and Mute Update Control Enable for DAC34 DUC4: Digital Attenuation and Mute Setting Update for DAC34, R-Channel DUC3: Digital Attenuation and Mute Setting Update for DAC34, L-Channel The digital attenuation and mute levels of DAC34 can be changed independently to any level by setting bits DMU4 and DMU3 in Register 51, bits DAT3[7:0] in Register 52, and bits DAT4[7:0] in Register 53 when D34E = '0'. When D34E = '1', the level is changed to any level at the same time when DUC4 = '1' or DUC3 = '1'. Both bits are automatically set to '0' after they are set to '1'. DUC4 and DUC3 must be set to '1' for every volume level setting while D34E = '1'. Default value of D34E: 1. Default value of DUC4 and DUC3: 0 D34E = 0 Digital attenuation and mute update control disabled D34E = 1 Digital attenuation and mute update control enabled (default) DUC4, DUC3 = 0 No update level (default) DUC4, DUC3 = 1 Update level (set to '0' automatically after setting to '1') DZ34: Digital Attenuation and Mute Zero Cross Enable for DAC34 This bit enables zero-crossing detection, which reduces zipper noise while the DAC digital attenuator and mute settings are being changed. If no zero-crossing data are input for a 512/fS period (10.6 ms at a 48-kHz sampling rate), then a timeout occurs and the PCM5310 volume level changes. Zero-crossing detection cannot be used with continuous zero and dc data. Default value: 1 0 Disable 1 Enable (default) DB34[1:0]: Digital Gain Boost for DAC34 These bits are used to boost the gain of digital data input to the DACs in front of the digital attenuator. Default value: 00 00 0 dB (default) 01 6 dB 10 12 dB 11 18 dB Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM5310 61 PCM5310 SLES244 – FEBRUARY 2009 ............................................................................................................................................................................................ www.ti.com DMU4: Digital Mute Control for DAC34, R-Channel DMU3: Digital Mute Control for DAC34, L-Channel The PCM5310 can independently mute the DAC digital input data to a zero level when DMU4 and DMU3 = '1'. These settings take precedence over the attenuation level settings of bits DAT3[7:0] and DAT4[7:0] in registers 52 and 53. The analog outputs may have audible zipper noise while changing levels. This noise can be reduced by selecting zero-crossing detection (Register 50, DZ34). Default value: 0 0 Mute disabled (default) 1 Mute enabled Registers 52 and 53 (34h and 35h) REG HEX DESCRIPTION B7 B6 B5 B4 B3 52 34h Digital attenuation level setting for DAC34 L-channel DAT3[7:0] 53 35h Digital attenuation level setting for DAC34 R-channel DAT4[7:0] B2 B1 B0 DAT3[7:0]: Digital Attenuation Setting for DAC34, L-Channel DAT4[7:0]: Digital Attenuation Setting for DAC34, R-Channel The digital attenuator of DAC34 can be independently set from 0 dB to –100 dB in 0.5-dB steps. The DAC34 output may have audible zipper noise while changing levels. This noise can be reduced by selecting zero crossing detection (Register 50, DZ34). Default value : 1111 1111 Table 34. Digital Attenuation Level Setting for DAC34 DAT3[7:0] DAT4[7:0] DIGITAL ATT LEVEL SETTING DAT3[7:0] DAT4[7:0] DIGITAL ATT LEVEL SETTING DAT3[7:0] DAT4[7:0] DIGITAL ATT LEVEL SETTING DAT3[7:0] DAT4[7:0] DIGITAL ATT LEVEL SETTING 1111 1111 FF 0 dB (default) 1100 1100 CC –25.5 dB 1001 1001 99 – 51 dB 0110 0110 66 1111 1110 FE –0.5 dB 1100 1011 CB –26 dB 1001 1000 98 –51.5 dB 0110 0101 65 –77 dB 1111 1101 FD –1 dB 1100 1010 CA –26.5 dB 1001 0111 97 –52 dB 0110 0100 64 –77.5 dB 1111 1100 FC –1.5 dB 1100 1001 C9 –27 dB 1001 0110 96 –52.5 dB 0110 0011 63 –78 dB 1111 1011 FB –2 dB 1100 1000 C8 –27.5 dB 1001 0101 95 –53 dB 0110 0010 62 –78.8 dB 1111 1010 FA –2.5 dB 1100 0111 C7 –28 dB 1001 0100 94 –53.5 dB 0110 0001 61 –79 dB 1111 1001 F9 –3 dB 1100 0110 C6 –28.5 dB 1001 0011 93 –54 dB 0110 0000 60 –79.5 dB 1111 1000 F8 –3.5 dB 1100 0101 C5 –29 dB 1001 0010 92 –54.5 dB 0101 1111 5F –80 dB 1111 0111 F7 –4 dB 1100 0100 C4 –29.5 dB 1001 0001 91 –55 dB 0101 1110 5E –80.5 dB 1111 0110 F6 –4.5 dB 1100 0011 C3 –30 dB 1001 0000 90 –55.5 dB 0101 1101 5D –81 dB 1111 0101 F5 –5 dB 1100 0010 C2 –30.5 dB 1000 1111 8F –56 dB 0101 1100 5C –81.5 dB 1111 0100 F4 –5.5 dB 1100 0001 C1 –31 dB 1000 1110 8E –56.5 dB 0101 1011 5B –82 dB 1111 0011 F3 –6 dB 1100 0000 C0 –31.5 dB 1000 1101 8D –57 dB 0101 1010 5A –82.5 dB 1111 0010 F2 –6.5 dB 1011 1111 BF –32 dB 1000 1100 8C –57.5 dB 0101 1001 59 –83 dB 1111 0001 F1 –7 dB 1011 1110 BE –32.5 dB 1000 1011 8B –58 dB 0101 1000 58 –83.5 dB 1111 0000 F0 –7.5 dB 1011 1101 BD –33 dB 1000 1010 8A –58.5 dB 0101 0111 57 –84 dB 1110 1111 EF –8 dB 1011 1100 BC –33.5 dB 1000 1001 89 –59 dB 0101 0110 56 –84.5 dB 1110 1110 EE –8.5 dB 1011 1011 BB –34 dB 1000 1000 88 –59.5 dB 0101 0101 55 –85 dB 1110 1101 ED –9 dB 1011 1010 BA –34.5 dB 1000 0111 87 –60 dB 0101 0100 54 –85.5 dB 1110 1100 EC –9.5 dB 1011 1001 B9 –35 dB 1000 0110 86 –60.5 dB 0101 0011 53 –86 dB 1110 1011 EB –10 dB 1011 1000 B8 –35.5 dB 1000 0101 85 –61 dB 0101 0010 52 –86.5 dB 1110 1010 EA –10.5 dB 1011 0111 B7 –36 dB 1000 0100 84 –61.5 dB 0101 0001 51 –87 dB 1110 1001 E9 –11 dB 1011 0110 B6 –36.5 dB 1000 0011 83 –62 dB 0101 0000 50 –87.5 dB 62 Submit Documentation Feedback –76.5 dB Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM5310 PCM5310 www.ti.com ............................................................................................................................................................................................ SLES244 – FEBRUARY 2009 Table 34. Digital Attenuation Level Setting for DAC34 (continued) DAT3[7:0] DAT4[7:0] 1110 1000 E8 1110 0111 1110 0110 DIGITAL ATT LEVEL SETTING DAT3[7:0] DAT4[7:0] DIGITAL ATT LEVEL SETTING DAT3[7:0] DAT4[7:0] –11.5 dB 1011 0101 B5 –37 dB 1000 0010 82 E7 –12 dB 1011 0100 B4 –37.5 dB 1000 0001 E6 –12.5 dB 1011 0011 B3 –38 dB 1000 0000 1110 0101 E5 –13 dB 1011 0010 B2 –38.5 dB 1110 0100 E4 –13.5 dB 1011 0001 B1 1110 0011 E3 –14 dB 1011 0000 1110 0010 E2 –14.5 dB 1010 1111 1110 0001 E1 –15 dB 1010 1110 AE 1110 0000 E0 –15.5 dB 1010 1101 1101 1111 DF –16 dB 1010 1100 1101 1110 DE –16.5 dB 1101 1101 DD 1101 1100 DC 1101 1011 DB 1101 1010 DA 1101 1001 1101 1000 DIGITAL ATT LEVEL SETTING DAT3[7:0] DAT4[7:0] –62.5 dB 0100 1111 81 –63 dB 80 –63.5 dB 0111 1111 7F –39 dB 0111 1110 7E B0 –39.5 dB 0111 1101 AF –40 dB 0111 1100 –40.5 dB AD AC 1010 1011 AB –17 dB 1010 1010 –17.5 dB 1010 1001 –18 dB DIGITAL ATT LEVEL SETTING 4F –88 dB 0100 1110 4E –88.5 dB 0100 1101 4D –89 dB –64 dB 0100 1100 4C –89.5 dB –64.5 dB 0100 1011 4B –90 dB 7D –65 dB 0100 1010 4A –90.5 dB 7C –65.5 dB 0100 1001 49 –91 dB 0111 1011 7B –66 dB 0100 1000 48 –91.5 dB –41 dB 0111 1010 7A –66.5 dB 0100 0111 47 –92 dB –41.5 dB 0111 1001 79 –67 dB 0100 0110 46 –92.5 dB –42 dB 0111 1000 78 –67.5 dB 0100 0101 45 –93 dB AA –42.5 dB 0111 0111 77 –68 dB 0100 0100 44 –93.5 dB A9 –43 dB 0111 0110 76 –68.5 dB 0100 0011 43 –94 dB 1010 1000 A8 –43.5 dB 0111 0101 75 –69 dB 0100 0010 42 –94.5 dB –18.5 dB 1010 0111 A7 –44 dB 0111 0100 74 –69.5 dB 0100 0001 41 –95 dB D9 –19 dB 1010 0110 A6 –44.5 dB 0111 0011 73 –70 dB 0100 0000 40 –95.5 dB D8 –19.5 dB 1010 0101 A5 –45 dB 0111 0010 72 –70.5 dB 0011 1111 3F –96 dB 1101 0111 D7 –20 dB 1010 0100 A4 –45.5 dB 0111 0001 71 –71 dB 0011 1110 3E –96.5 dB 1101 0110 D6 –20.5 dB 1010 0011 A3 –46 dB 0111 0000 70 –71.5 dB 0011 1101 3D –97 dB 1101 0101 D5 –21 dB 1010 0010 A2 –46.5 dB 0110 1111 6F –72 dB 0011 1100 3C –97.5 dB 1101 0100 D4 –21.5 dB 1010 0001 A1 –47 dB 0110 1110 6E –72.5 dB 0011 1011 3B –98 dB 1101 0011 D3 –22 dB 1010 0000 A0 –47.5 dB 0110 1101 6D –73 dB 0011 1010 3A –98.5 dB 1101 0010 D2 –22.5 dB 1001 1111 9F –48 dB 0110 1100 6C –73.5 dB 0011 1001 39 –99 dB 1101 0001 D1 –23 dB 1001 1110 9E –48.5 dB 0110 1011 6B –74 dB 0011 1000 38 –99.5 dB 1101 0000 D0 –23.5 dB 1001 1101 9D –49 dB 0110 1010 6A –74.5 dB 0011 0111 37 –100 dB 0011 0110 ⋮ 0000 0000 36 ⋮ 00 Mute 1100 1111 CF –24 dB 1001 1100 9C –49.5 dB 0110 1001 69 –75 dB 1100 1110 CE –24.5 dB 1001 1011 9B –50 dB 0110 1000 68 –75.5 dB 1100 1101 CD –25 dB 1001 1010 9A –50.5 dB 0110 0111 67 –76 dB Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM5310 63 PCM5310 SLES244 – FEBRUARY 2009 ............................................................................................................................................................................................ www.ti.com Registers 54 and 55 (36h and 37h) REG HEX DESCRIPTION 54 36h Master/slave interface format for DAC34 55 37h De-emphasis filter control for DAC34 B7 B6 RSV RSV B5 B4 B3 B2 RSV RSV DFM34[1:0] RSV DM34 RSV DF34[1:0] DMS34[3:0] RSV B1 B0 DMS34[3:0]: Master/Slave Audio Interface Setting for DAC34 These bits set the master or slave mode. DAC34 receives LRCK and BCK from PORT-1, PORT-2, PORT-3, PORT-4, PORT-5 or PORT-6 in slave mode, and generates LRCK and BCK from SCK in master mode. Default value: 1000 DMS34[3:0] MASTER/SLAVE AUDIO INTERFACE SETTING FOR MASTER/SLAVE AUDIO INTERFACE SETTING FOR DAC34 DMS34[3:0] DAC34 0000 Reserved 1000 Slave and system clock fS auto-detect mode (default) 0001 Master and system clock 768 fS 1001 Slave and system clock 768 fS 0010 Master and system clock 512 fS 1010 Slave and system clock 512 fS 0011 Master and system clock 384 fS 1011 Slave and system clock 384 fS 0100 Master and system clock 256 fS 1100 Slave and system clock 256 fS 0101 Master and system clock 192 fS 1101 Slave and system clock 192 fS 0110 Master and system clock 128 fS 1110 Slave and system clock 128 fS 0111 Reserved 1111 Reserved DFM34[1:0]: Audio Interface Format for DAC34 These bits select the DAC34 audio data format as I2S, right-justified, or left-justified. Default value: 00 00 16 to 24 bits, I2S (default) 01 16 to 24 bits, left-justified 10 24 bits, right-justified 11 16 bits, right-justified DM34: De-Emphasis Filter Enable for DAC34 This bit enables the DAC34 de-emphasis filter. The frequency can be selected by setting bits DF34[1:0] of Register 55. Default value: 0 0 Disable (default) 1 Enable DF34[1:0]: De-Emphasis Filter Sampling Rate Selection for DAC34 A digital de-emphasis filter is in front of the interpolation filter. One of three de-emphasis filters can be selected corresponding to the sampling rate: 32 kHz, 44.1 kHz, or 48 kHz. Default value: 00 64 00 44.1 kHz (default) 01 48 kHz 10 32 kHz 11 Reserved Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM5310 PCM5310 www.ti.com ............................................................................................................................................................................................ SLES244 – FEBRUARY 2009 Register 56 (38h) REG HEX DESCRIPTION B7 B6 56 38h Power up/down, oversampling rate control for DAC34 PD34 RSV B5 B4 OV34[1:0] B3 B2 B1 B0 ZR34 RSV RSV RSV PD34: Power Up/Down Control for DAC34 This bit controls the power up/down for DAC34, including the interpolation filter. Default value: 1 0 Power up 1 Power down (default) OV34[1:0]: Oversampling Rate Control for DAC34 These bits control the oversampling rate of the DAC34 delta-sigma modulator. Default value: 01 SYSTEM CLOCK RATE OV34 128 fS, 192 fS 256 fS, 384 fS 00 16 fS 32 fS 64 fS 01 (default) 32 fS 64 fS 128 fS — — 32 fS 128 fS (1) 128 fS (1) 10 11 (1) 128 fS, 192 fS Less than fS = 48 kHz ZR34: Zero Flag Reverse This bit reverses the polarity of the zero flag output. The zero flag is high after input data are zero during 1024 fS when ZR34 = '0', and is set with the GPIO port by bits GSL1[4:0], GSL2[4:0], GSL3[4:0] in registers 09 to 11. Default value: 0 0 Buffered output (default) 1 Inverted output Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM5310 65 PCM5310 SLES244 – FEBRUARY 2009 ............................................................................................................................................................................................ www.ti.com Registers 80 and 81 (50h and 51h) REG HEX DESCRIPTION B7 B6 B5 B4 B3 B2 80 50h Digital attenuation and mute control for ADC12 81 51h Digital soft mute for ADC12 B1 B0 A12E RSV AUC2 AUC1 RSV RSV RSV AZ12 RSV FS12 RSV RSV RSV RSV AMU2 AMU1 A12E: Digital Attenuation and Mute Update Control Enable for ADC12 AUC2: Digital Attenuation and Mute Setting Update for ADC12, R-Channel AUC1: Digital Attenuation and Mute Setting Update for ADC12, L-Channel The digital attenuation and mute levels of ADC12 can be changed independently to any level by setting bits AMU2 and AMU1 in Register 81, bits AAT1[7:0] in Register 82, and bits AAT2[7:0] in Register 83 when A12E = '0'. When A12E = '1', the level is changed to any level at the same time when AUC2 = '1' or AUC1 = '1'. Both bits are automatically set to '0' after they are set to '1'. AUC2 and AUC1 must be set to '1' for every volume level setting while A12E = '1'. Default value of A12E: 1. Default value of AUC2 and AUC1: 0 A12E = 0 Digital attenuation and mute update control disabled A12E = 1 Digital attenuation and mute update control enabled (default) AUC2, AUC1 = 0 No update level (default) AUC2, AUC1 = 1 Update level (set to '1' automatically after setting to '0') AZ12: Digital Attenuation and Mute Zero Crossing Enable for ADC12 This bit enables zero-crossing detection, which reduces zipper noise while the ADC digital attenuator and mute settings are being changed. If no zero-crossing data are input for a 512/fS period (10.6 ms at a 48-kHz sampling rate), then a timeout occurs and the PCM5310 volume level changes. Zero-crossing detection cannot be used with continuous zero and dc data. Default value: 1 0 Disable 1 Enable (default) FS12: Sampling Rate Selection for ADC12 This bit is used to select the ADS12 sampling rate. FS12 must be set to '1' when the sampling rate is greater than 48 kHz. Default value: 0 0 fS ≤ 48 kHz (default) 1 fS > 48 kHz AMU2: Digital Mute Control for ADC12, R-Channel AMU1: Digital Mute Control for ADC12, L-Channel The PCM5310 can independently mute the DAC digital input data to a zero level when AMU2 and AMU1 = '1'. These settings take precedence over the attenuation level settings of bits AAT1[7:0] and AAT2[7:0] in registers 82 and 83. The analog outputs may have audible zipper noise while changing levels. This noise can be reduced by selecting zero-crossing detection (Register 80, AZ12). Default value: 0 66 0 Mute disabled (default) 1 Mute enabled Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM5310 PCM5310 www.ti.com ............................................................................................................................................................................................ SLES244 – FEBRUARY 2009 Registers 82 and 83 (52h and 53h) REG HEX DESCRIPTION B7 B6 B5 B4 B3 82 52h Digital attenuation level setting for ADC12 L-channel AAT1[7:0] 83 53h Digital attenuation level setting for ADC12 R-channel AAT2[7:0] B2 B1 B0 AAT1[7:0]: Digital Attenuation Setting for ADC12, L-Channel AAT2[7:0]: Digital Attenuation Setting for ADC12, R-Channel The digital attenuator of ADC12 can be independently set from 20 dB to –100 dB in 0.5-dB steps. The ADC12 output may have audible zipper noise while changing levels. This noise can be reduced by selecting zero crossing detection (Register 80, AZ12). Default value : 1101 0111 Table 35. Digital Attenuation Level Setting for ADC12 AAT1[7:0] AAT2[7:0] DIGITAL ATT LEVEL SETTING AAT1[7:0] AAT2[7:0] DIGITAL ATT LEVEL SETTING AAT1[7:0] AAT2[7:0] DIGITAL ATT LEVEL SETTING AAT1[7:0] AAT2[7:0] DIGITAL ATT LEVEL SETTING 1111 1111 FF 20 dB 1100 0010 C2 –10.5 dB 1000 0101 85 –41 dB 0100 1000 48 1111 1110 FE 19.5 dB 1100 0001 C1 –11 dB 1000 0100 84 –41.5 dB 0100 0111 47 –71.5 dB –72 dB 1111 1101 FD 19 dB 1100 0000 C0 –11.5 dB 1000 0011 83 –42 dB 0100 0110 46 –72.5 dB 1111 1100 FC 18.5 dB 1011 1111 BF –12 dB 1000 0010 82 –42.5 dB 0100 0101 45 –73 dB 1111 1011 FB 18 dB 1011 1110 BE –12.5 dB 1000 0001 81 –43 dB 0100 0100 44 –73.5 dB 1111 1010 FA 17.5 dB 1011 1101 BD –13 dB 1000 0000 80 –43.5 dB 0100 0011 43 –74 dB 1111 1001 F9 17 dB 1011 1100 BC –13.5 dB 0111 1111 7F –44 dB 0100 0010 42 –74.5 dB 1111 1000 F8 16.5 dB 1011 1011 BB –14 dB 0111 1110 7E –44.5 dB 0100 0001 41 –75 dB 1111 0111 F7 16 dB 1011 1010 BA –14.5 dB 0111 1101 7D –45 dB 0100 0000 40 –75.5 dB 1111 0110 F6 15.5 dB 1011 1001 B9 –15 dB 0111 1100 7C –45.5 dB 0011 1111 3F –76 dB 1111 0101 F5 15 dB 1011 1000 B8 –15.5 dB 0111 1011 7B –46 dB 0011 1110 3E –76.5 dB 1111 0100 F4 14.5 dB 1011 0111 B7 –16 dB 0111 1010 7A –46.5 dB 0011 1101 3D –77 dB 1111 0011 F3 14 dB 1011 0110 B6 –16.5 dB 0111 1001 79 –47 dB 0011 1100 3C –77.5 dB 1111 0010 F2 13.5 dB 1011 0101 B5 –17 dB 0111 1000 78 –47.5 dB 0011 1011 3B –78 dB 1111 0001 F1 13 dB 1011 0100 B4 –17.5 dB 0111 0111 77 –48 dB 0011 1010 3A –78.8 dB 1111 0000 F0 12.5 dB 1011 0011 B3 –18 dB 0111 0110 76 –48.5 dB 0011 1001 39 –79 dB 1110 1111 EF 12 dB 1011 0010 B2 –18.5 dB 0111 0101 75 –49 dB 0011 1000 38 –79.5 dB 1110 1110 EE 11.5 dB 1011 0001 B1 –19 dB 0111 0100 74 –49.5 dB 0011 0111 37 –80 dB 1110 1101 ED 11 dB 1011 0000 B0 –19.5 dB 0111 0011 73 –50 dB 0011 0110 36 –80.5 dB 1110 1100 EC 10.5 dB 1010 1111 AF –20 dB 0111 0010 72 –50.5 dB 0011 0101 35 –81 dB 1110 1011 EB 10 dB 1010 1110 AE –20.5 dB 0111 0001 71 – 51 dB 0011 0100 34 –81.5 dB 1110 1010 EA 9.5 dB 1010 1101 AD –21 dB 0111 0000 70 –51.5 dB 0011 0011 33 –82 dB 1110 1001 E9 9 dB 1010 1100 AC –21.5 dB 0110 1111 6F –52 dB 0011 0010 32 –82.5 dB 1110 1000 E8 8.5 dB 1010 1011 AB –22 dB 0110 1110 6E –52.5 dB 0011 0001 31 –83 dB 1110 0111 E7 8 dB 1010 1010 AA –22.5 dB 0110 1101 6D –53 dB 0011 0000 30 –83.5 dB 1110 0110 E6 7.5 dB 1010 1001 A9 –23 dB 0110 1100 6C –53.5 dB 0010 1111 2F –84 dB 1110 0101 E5 7 dB 1010 1000 A8 –23.5 dB 0110 1011 6B –54 dB 0010 1110 2E –84.5 dB 1110 0100 E4 6.5 dB 1010 0111 A7 –24 dB 0110 1010 6A –54.5 dB 0010 1101 2D –85 dB 1110 0011 E3 6 dB 1010 0110 A6 –24.5 dB 0110 1001 69 –55 dB 0010 1100 2C –85.5 dB 1110 0010 E2 5.5 dB 1010 0101 A5 –25 dB 0110 1000 68 –55.5 dB 0010 1011 2B –86 dB 1110 0001 E1 5 dB dB 1010 0100 A4 –25.5 dB 0110 0111 67 –56 dB 0010 1010 2A –86.5 dB 1110 0000 E0 4.5 dB 1010 0011 A3 –26 dB 0110 0110 66 –56.5 dB 0010 1001 29 –87 dB 1101 1111 DF 4 dB 1010 0010 A2 –26.5 dB 0110 0101 65 –57 dB 0010 1000 28 –87.5 dB Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM5310 67 PCM5310 SLES244 – FEBRUARY 2009 ............................................................................................................................................................................................ www.ti.com Table 35. Digital Attenuation Level Setting for ADC12 (continued) AAT1[7:0] AAT2[7:0] 1101 1110 DE 1101 1101 1101 1100 DIGITAL ATT LEVEL SETTING AAT1[7:0] AAT2[7:0] DIGITAL ATT LEVEL SETTING AAT1[7:0] AAT2[7:0] 3.5 dB 1010 0001 A1 –27 dB 0110 0100 64 DD 3 dB 1010 0000 A0 –27.5 dB 0110 0011 DC 2.5 dB 1001 1111 9F –28 dB 0110 0010 1101 1011 DB 2 dB 1001 1110 9E –28.5 dB 1101 1010 DA 1.5 dB 1001 1101 9D 1101 1001 D9 1 dB 1001 1100 1101 1000 D8 0.5 dB 1001 1011 1101 0111 D7 0 dB (default) 1101 0110 D6 1101 0101 D5 1101 0100 D4 1101 0011 1101 0010 DIGITAL ATT LEVEL SETTING AAT1[7:0] AAT2[7:0] DIGITAL ATT LEVEL SETTING –57.5 dB 0010 0111 27 –88 dB 63 –58 dB 0010 0110 26 –88.5 dB 62 –58.5 dB 0010 0101 25 –89 dB 0110 0001 61 –59 dB 0010 0100 24 –89.5 dB –29 dB 0110 0000 60 –59.5 dB 0010 0011 23 –90 dB 9C –29.5 dB 0101 1111 5F –60 dB 0010 0010 22 –90.5 dB 9B –30 dB 0101 1110 5E –60.5 dB 0010 0001 21 –91 dB 1001 1010 9A –30.5 dB 0101 1101 5D –61 dB 0010 0000 20 –91.5 dB –0.5 dB 1001 1001 99 –31 dB 0101 1100 5C –61.5 dB 0001 1111 1F –92 dB –1 dB 1001 1000 98 –31.5 dB 0101 1011 5B –62 dB 0001 1110 1E –92.5 dB –1.5 dB 1001 0111 97 –32 dB 0101 1010 5A –62.5 dB 0001 1101 1D –93 dB D3 –2 dB 1001 0110 96 –32.5 dB 0101 1001 59 –63 dB 0001 1100 1C –93.5 dB D2 –2.5 dB 1001 0101 95 –33 dB 0101 1000 58 –63.5 dB 0001 1011 1B –94 dB 1101 0001 D1 –3 dB 1001 0100 94 –33.5 dB 0101 0111 57 –64 dB 0001 1010 1A –94.5 dB 1101 0000 D0 –3.5 dB 1001 0011 93 –34 dB 0101 0110 56 –64.5 dB 0001 1001 19 –95 dB –95.5 dB 1100 1111 CF –4 dB 1001 0010 92 –34.5 dB 0101 0101 55 –65 dB 0001 1000 18 1100 1110 CE –4.5 dB 1001 0001 91 –35 dB 0101 0100 54 –65.5 dB 0001 0111 17 –96 dB 1100 1101 CD –5 dB 1001 0000 90 –35.5 dB 0101 0011 53 –66 dB 0001 0110 16 –96.5 dB 1100 1100 CC –5.5 dB 1000 1111 8F –36 dB 0101 0010 52 –66.5 dB 0001 0101 15 –97 dB 1100 1011 CB –6 dB 1000 1110 8E –36.5 dB 0101 0001 51 –67 dB 0001 0100 14 –97.5 dB 1100 1010 CA –6.5 dB 1000 1101 8D –37 dB 0101 0000 50 –67.5 dB 0001 0011 13 –98 dB 1100 1001 C9 –7 dB 1000 1100 8C –37.5 dB 0100 1111 4F –68 dB 0001 0010 12 –98.5 dB 1100 1000 C8 –7.5 dB 1000 1011 8B –38 dB 0100 1110 4E –68.5 dB 0001 0001 11 –99 dB 1100 0111 C7 –8 dB 1000 1010 8A –38.5 dB 0100 1101 4D –69 dB 0001 0000 10 –99.5 dB 1100 0110 C6 –8.5 dB 1000 1001 89 –39 dB 0100 1100 4C –69.5 dB 0000 1111 0F –100 dB 1100 0101 C5 –9 dB 1000 1000 88 –39.5 dB 0100 1011 4B –70 dB 1100 0100 C4 –9.5 dB 1000 0111 87 –40 dB 0100 1010 4A –70.5 dB C3 –10 dB 1000 0110 86 –40.5 dB 0100 1001 49 –71 dB 0E ⋮ 00 Mute 1100 0011 0000 1110 ⋮ 0000 0000 68 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM5310 PCM5310 www.ti.com ............................................................................................................................................................................................ SLES244 – FEBRUARY 2009 Register 84 (54h) REG HEX DESCRIPTION B7 84 54h Master/slave interface format for ADC12 B6 B5 B4 AMS12[3:0] B3 B2 HF12 RSV B1 B0 AFM12[1:0] AMS12[3:0]: Master/Slave Audio Interface Setting for ADC12 These bits set the master or slave mode. ADC12 receives LRCK and BCK from PORT-1, PORT-2, PORT-3, PORT-4, PORT-5 or PORT-6 in slave mode, and generates LRCK and BCK from SCK in master mode. Default value: 1000 AMS12[3:0] MASTER/SLAVE AUDIO INTERFACE SETTING FOR MASTER/SLAVE AUDIO INTERFACE SETTING FOR ADC12 AMS12[3:0] ADC12 0000 Reserved 1000 Slave and system clock fS auto-detect mode (default) 0001 Master and system clock 768 fS 1001 Slave and system clock 768 fS 0010 Master and system clock 512 fS 1010 Slave and system clock 512 fS 0011 Master and system clock 384 fS 1011 Slave and system clock 384 fS 0100 Master and system clock 256 fS 1100 Slave and system clock 256 fS 0101 Reserved 1101 Reserved 0110 Reserved 1110 Reserved 0111 Reserved 1111 Reserved HF12: High-Pass Filter Disable for ADC12 This bit disables the digital high-pass filter of ADC12. Default value: 0 0 (0.019 fS/1000) Hz (default) 1 Off AFM12[1:0]: Audio Interface Format for ADC12 These bits select the ADC12 audio data format as I2S, right-justified, or left-justified. Default value: 00 00 16 to 24 bits, I2S (default) 01 16 to 24 bits, left-justified 10 24 bits, right-justified 11 16 bits, right-justified Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM5310 69 PCM5310 SLES244 – FEBRUARY 2009 ............................................................................................................................................................................................ www.ti.com Register 85 (55h) REG HEX DESCRIPTION B7 B6 B5 B4 B3 B2 B1 B0 85 55h Power up/down for ADC12 PA12 RSV RSV RSV RSV RSV RSV RSV PA12: Power Up/Down Control for ADC12 This bit controls the power up/down for ADC12, including the decimation filter. Default value: 1 0 Power up 1 Power down (default) Register 90 (5Ah) REG HEX DESCRIPTION B7 B6 B5 B4 B3 B2 B1 B0 90 5Ah Digital attenuation and mute control for ADC34 A34E RSV AUC4 AUC3 RSV RSV RSV AZ34 A34E: Digital Attenuation and Mute Update Control Enable for ADC34 AUC4: Digital Attenuation and Mute Setting Update for ADC34, R-Channel AUC3: Digital Attenuation and Mute Setting Update for ADC34, L-Channel The digital attenuation and mute levels of ADC12 can be changed independently to any level by setting bits AMU4 and AMU3 in Register 91, bits AAT3[7:0] in Register 92, and bits AAT4[7:0] in Register 93 when A34E = '0'. When A34E = '1', the level is changed to any level at the same time when AUC4 = '1' or AUC3 = '1'. Both bits are automatically set to '0' after they are to '1'. AUC4 and AUC3 must be set to '1' for every volume level setting while A34E = '1'. Default value of A34E: 1. Default value of AUC4 and AUC3: 0 A34E = 0 Digital attenuation and mute update control disabled A34E = 1 Digital attenuation and mute update control enabled (default) AUC4, AUC3 = 0 No update level (default) AUC4, AUC3 = 1 Update level (set to '0' automatically after setting to '1') AZ34: Digital Attenuation and Mute Zero Cross Enable for ADC34 This bit enables zero-crossing detection, which reduces zipper noise while the ADC digital attenuator and mute settings are being changed. If no zero-crossing data are input for a 512/fS period (10.6 ms at a 48-kHz sampling rate), then a timeout occurs and the PCM5310 volume level changes. Zero-crossing detection cannot be used with continuous zero and dc data. Default value: 1 70 0 Disable 1 Enable (default) Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM5310 PCM5310 www.ti.com ............................................................................................................................................................................................ SLES244 – FEBRUARY 2009 Register 91 (5Bh) REG HEX DESCRIPTION B7 B6 B5 B4 B3 B2 B1 B0 91 5Bh Digital soft mute for ADC34 RSV FS34 RSV RSV RSV RSV AMU4 AMU3 FS34: Sampling Rate Selection for ADC34 This bit sets the ADS34 sampling rate. FS34 must be set to '1' when the sampling rate is greater than 48 kHz. Default value: 0 0 fS ≤ 48 kHz (default) 1 fS > 48 kHz AMU4: Digital Mute Control for ADC34, R-Channel AMU3: Digital Mute Control for ADC34, L-Channel The PCM5310 can independently mute the DAC digital input data to a zero level when AMU4 and AMU3 = '1'. These settings take precedence over the attenuation level settings of bits AAT3[7:0] and AAT4[7:0] in registers 92 and 93. The analog outputs may have audible zipper noise while changing levels. This noise can be reduced by selecting zero-crossing detection (Register 90, AZ34). Default value: 0 0 Mute disabled (default) 1 Mute enabled Registers 92 and 93 (5Ch and 5Dh) REG HEX DESCRIPTION B7 B6 B5 B4 B3 92 5Ch Digital attenuation level setting for ADC34 L-channel AAT3[7:0] 93 5Dh Digital attenuation level setting for ADC34 R-channel AAT4[7:0] B2 B1 B0 AAT3[7:0]: Digital Attenuation Setting for ADC34, L-Channel AAT4[7:0]: Digital Attenuation Setting for ADC34, R-Channel The digital attenuator of ADC34 can be independently set from 20 dB to –100 dB in 0.5-dB steps. The ADC34 output may have audible zipper noise while changing levels. This noise can be reduced by selecting zero crossing detection (Register 90, AZ34). Default value : 1101 0111 Table 36. Digital Attenuation Level Setting for ADC34 DIGITAL ATT LEVEL SETTING AAT1[7:0] AAT2[7:0] 1111 1111 DIGITAL ATT LEVEL SETTING AAT1[7:0] AAT2[7:0] FF 20 dB 1100 0010 C2 1111 1110 FE 19.5 dB 1100 0001 1111 1101 FD 19 dB 1100 0000 1111 1100 FC 18.5 dB 1011 1111 1111 1011 FB 18 dB 1011 1110 1111 1010 FA 17.5 dB 1011 1101 1111 1001 F9 17 dB 1011 1100 1111 1000 F8 16.5 dB 1011 1011 1111 0111 F7 16 dB 1011 1010 1111 0110 F6 15.5 dB 1011 1001 1111 0101 F5 15 dB 1011 1000 1111 0100 F4 14.5 dB 1011 0111 1111 0011 F3 14 dB 1011 0110 1111 0010 F2 13.5 dB 1011 0101 1111 0001 F1 13 dB 1011 0100 DIGITAL ATT LEVEL SETTING AAT1[7:0] AAT2[7:0] DIGITAL ATT LEVEL SETTING AAT1[7:0] AAT2[7:0] –10.5 dB 1000 0101 85 –41 dB 0100 1000 48 –71.5 dB C1 –11 dB 1000 0100 84 –41.5 dB 0100 0111 47 –72 dB C0 –11.5 dB 1000 0011 83 –42 dB 0100 0110 46 –72.5 dB BF –12 dB 1000 0010 82 –42.5 dB 0100 0101 45 –73 dB BE –12.5 dB 1000 0001 81 –43 dB 0100 0100 44 –73.5 dB BD –13 dB 1000 0000 80 –43.5 dB 0100 0011 43 –74 dB BC –13.5 dB 0111 1111 7F –44 dB 0100 0010 42 –74.5 dB BB –14 dB 0111 1110 7E –44.5 dB 0100 0001 41 –75 dB BA –14.5 dB 0111 1101 7D –45 dB 0100 0000 40 –75.5 dB B9 –15 dB 0111 1100 7C –45.5 dB 0011 1111 3F –76 dB B8 –15.5 dB 0111 1011 7B –46 dB 0011 1110 3E –76.5 dB B7 –16 dB 0111 1010 7A –46.5 dB 0011 1101 3D –77 dB B6 –16.5 dB 0111 1001 79 –47 dB 0011 1100 3C –77.5 dB B5 –17 dB 0111 1000 78 –47.5 dB 0011 1011 3B –78 dB B4 –17.5 dB 0111 0111 77 –48 dB 0011 1010 3A –78.8 dB Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM5310 71 PCM5310 SLES244 – FEBRUARY 2009 ............................................................................................................................................................................................ www.ti.com Table 36. Digital Attenuation Level Setting for ADC34 (continued) DIGITAL ATT LEVEL SETTING AAT1[7:0] AAT2[7:0] DIGITAL ATT LEVEL SETTING AAT1[7:0] AAT2[7:0] DIGITAL ATT LEVEL SETTING AAT1[7:0] AAT2[7:0] DIGITAL ATT LEVEL SETTING AAT1[7:0] AAT2[7:0] 1111 0000 F0 12.5 dB 1011 0011 B3 –18 dB 0111 0110 76 –48.5 dB 0011 1001 39 –79 dB 1110 1111 EF 12 dB 1011 0010 B2 –18.5 dB 0111 0101 75 –49 dB 0011 1000 38 –79.5 dB 1110 1110 EE 11.5 dB 1011 0001 B1 –19 dB 0111 0100 74 –49.5 dB 0011 0111 37 –80 dB 1110 1101 ED 11 dB 1011 0000 B0 –19.5 dB 0111 0011 73 –50 dB 0011 0110 36 –80.5 dB 1110 1100 EC 10.5 dB 1010 1111 AF –20 dB 0111 0010 72 –50.5 dB 0011 0101 35 –81 dB 1110 1011 EB 10 dB 1010 1110 AE –20.5 dB 0111 0001 71 – 51 dB 0011 0100 34 –81.5 dB 1110 1010 EA 9.5 dB 1010 1101 AD –21 dB 0111 0000 70 –51.5 dB 0011 0011 33 –82 dB 1110 1001 E9 9 dB 1010 1100 AC –21.5 dB 0110 1111 6F –52 dB 0011 0010 32 –82.5 dB 1110 1000 E8 8.5 dB 1010 1011 AB –22 dB 0110 1110 6E –52.5 dB 0011 0001 31 –83 dB 1110 0111 E7 8 dB 1010 1010 AA –22.5 dB 0110 1101 6D –53 dB 0011 0000 30 –83.5 dB 1110 0110 E6 7.5 dB 1010 1001 A9 –23 dB 0110 1100 6C –53.5 dB 0010 1111 2F –84 dB 1110 0101 E5 7 dB 1010 1000 A8 –23.5 dB 0110 1011 6B –54 dB 0010 1110 2E –84.5 dB 1110 0100 E4 6.5 dB 1010 0111 A7 –24 dB 0110 1010 6A –54.5 dB 0010 1101 2D –85 dB 1110 0011 E3 6 dB 1010 0110 A6 –24.5 dB 0110 1001 69 –55 dB 0010 1100 2C –85.5 dB 1110 0010 E2 5.5 dB 1010 0101 A5 –25 dB 0110 1000 68 –55.5 dB 0010 1011 2B –86 dB 1110 0001 E1 5 dB dB 1010 0100 A4 –25.5 dB 0110 0111 67 –56 dB 0010 1010 2A –86.5 dB 1110 0000 E0 4.5 dB 1010 0011 A3 –26 dB 0110 0110 66 –56.5 dB 0010 1001 29 –87 dB 1101 1111 DF 4 dB 1010 0010 A2 –26.5 dB 0110 0101 65 –57 dB 0010 1000 28 –87.5 dB 1101 1110 DE 3.5 dB 1010 0001 A1 –27 dB 0110 0100 64 –57.5 dB 0010 0111 27 –88 dB 1101 1101 DD 3 dB 1010 0000 A0 –27.5 dB 0110 0011 63 –58 dB 0010 0110 26 –88.5 dB 1101 1100 DC 2.5 dB 1001 1111 9F –28 dB 0110 0010 62 –58.5 dB 0010 0101 25 –89 dB 1101 1011 DB 2 dB 1001 1110 9E –28.5 dB 0110 0001 61 –59 dB 0010 0100 24 –89.5 dB 1101 1010 DA 1.5 dB 1001 1101 9D –29 dB 0110 0000 60 –59.5 dB 0010 0011 23 –90 dB 1101 1001 D9 1 dB 1001 1100 9C –29.5 dB 0101 1111 5F –60 dB 0010 0010 22 –90.5 dB 1101 1000 D8 0.5 dB 1001 1011 9B –30 dB 0101 1110 5E –60.5 dB 0010 0001 21 –91 dB 1101 0111 D7 0 dB (default) 1001 1010 9A –30.5 dB 0101 1101 5D –61 dB 0010 0000 20 –91.5 dB 1101 0110 D6 –0.5 dB 1001 1001 99 –31 dB 0101 1100 5C –61.5 dB 0001 1111 1F –92 dB 1101 0101 D5 –1 dB 1001 1000 98 –31.5 dB 0101 1011 5B –62 dB 0001 1110 1E –92.5 dB 1101 0100 D4 –1.5 dB 1001 0111 97 –32 dB 0101 1010 5A –62.5 dB 0001 1101 1D –93 dB 1101 0011 D3 –2 dB 1001 0110 96 –32.5 dB 0101 1001 59 –63 dB 0001 1100 1C –93.5 dB 1101 0010 D2 –2.5 dB 1001 0101 95 –33 dB 0101 1000 58 –63.5 dB 0001 1011 1B –94 dB 1101 0001 D1 –3 dB 1001 0100 94 –33.5 dB 0101 0111 57 –64 dB 0001 1010 1A –94.5 dB 1101 0000 D0 –3.5 dB 1001 0011 93 –34 dB 0101 0110 56 –64.5 dB 0001 1001 19 –95 dB 1100 1111 CF –4 dB 1001 0010 92 –34.5 dB 0101 0101 55 –65 dB 0001 1000 18 –95.5 dB 1100 1110 CE –4.5 dB 1001 0001 91 –35 dB 0101 0100 54 –65.5 dB 0001 0111 17 –96 dB 1100 1101 CD –5 dB 1001 0000 90 –35.5 dB 0101 0011 53 –66 dB 0001 0110 16 –96.5 dB 1100 1100 CC –5.5 dB 1000 1111 8F –36 dB 0101 0010 52 –66.5 dB 0001 0101 15 –97 dB 1100 1011 CB –6 dB 1000 1110 8E –36.5 dB 0101 0001 51 –67 dB 0001 0100 14 –97.5 dB 1100 1010 CA –6.5 dB 1000 1101 8D –37 dB 0101 0000 50 –67.5 dB 0001 0011 13 –98 dB 1100 1001 C9 –7 dB 1000 1100 8C –37.5 dB 0100 1111 4F –68 dB 0001 0010 12 –98.5 dB 1100 1000 C8 –7.5 dB 1000 1011 8B –38 dB 0100 1110 4E –68.5 dB 0001 0001 11 –99 dB 1100 0111 C7 –8 dB 1000 1010 8A –38.5 dB 0100 1101 4D –69 dB 0001 0000 10 –99.5 dB 1100 0110 C6 –8.5 dB 1000 1001 89 –39 dB 0100 1100 4C –69.5 dB 0000 1111 0F –100 dB 1100 0101 C5 –9 dB 1000 1000 88 –39.5 dB 0100 1011 4B –70 dB 1100 0100 C4 –9.5 dB 1000 0111 87 –40 dB 0100 1010 4A –70.5 dB C3 –10 dB 1000 0110 86 –40.5 dB 0100 1001 49 –71 dB 0E ⋮ 00 Mute 1100 0011 0000 1110 ⋮ 0000 0000 72 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM5310 PCM5310 www.ti.com ............................................................................................................................................................................................ SLES244 – FEBRUARY 2009 Register 94 (5Eh) REG HEX DESCRIPTION B7 94 5Eh Master/slave interface format for ADC34 B6 B5 B4 AMS34[3:0] B3 B2 HF34 RSV B1 B0 AFM34[1:0] AMS34[3:0]: Master/Slave Audio Interface Setting for ADC34 These bits set the master or slave mode. ADC34 receives LRCK and BCK from PORT-1, PORT-2, PORT-3, PORT-4, PORT-5 or PORT-6 in slave mode, and generates LRCK and BCK from SCK in master mode. Default value: 1000 AMS34[3:0] MASTER/SLAVE AUDIO INTERFACE SETTING FOR MASTER/SLAVE AUDIO INTERFACE SETTING FOR ADC34 AMS34[3:0] ADC34 0000 Reserved 1000 Slave and system clock fS auto-detect mode (default) 0001 Master and system clock 768 fS 1001 Slave and system clock 768 fS 0010 Master and system clock 512 fS 1010 Slave and system clock 512 fS 0011 Master and system clock 384 fS 1011 Slave and system clock 384 fS 0100 Master and system clock 256 fS 1100 Slave and system clock 256 fS 0101 Reserved 1101 Reserved 0110 Reserved 1110 Reserved 0111 Reserved 1111 Reserved HF34: High-Pass Filter Disable for ADC34 This bit disables the digital high-pass filter of ADC34. Default value: 0 0 (0.019 fS/1000) Hz (default) 1 Off AFM34[1:0]: Audio Interface Format for ADC34 These bits select the ADC34 audio data format as I2S, right-justified, or left-justified. Default value: 00 00 16 to 24 bits, I2S (default) 01 16 to 24 bits, left-justified 10 24 bits, right-justified 11 16 bits, right-justified Register 95 (5Fh) REG HEX DESCRIPTION B7 B6 B5 B4 B3 B2 B1 B0 95 5Fh Power up/down for ADC34 PA34 RSV RSV RSV RSV RSV RSV RSV B4 B3 B2 B1 B0 PA34: Power Up/Down Control for ADC34 This bit controls the power up/down for ADC34, including the decimation filter. Default value: 1 0 Power up 1 Power down (default) Register 101 (65h) REG HEX DESCRIPTION B7 101 65h LRCK/BCK selection of PORT-1 and PORT-2 B6 B5 LBS2[3:0] LBS1[3:0] Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM5310 73 PCM5310 SLES244 – FEBRUARY 2009 ............................................................................................................................................................................................ www.ti.com LBS2[3:0]: LRCK/BCK Selection of PORT-2 (MUX_P2BL) These bits are used for routing LRCK and BCK of PORT-2. Any combination of LRCK1/BCK1 to LRCK6/BCK6 and LRCK/BCK of ADCs/DACs in master mode can be connected to PORT-2. Figure 47 shows a detailed diagram of PORT-2. Default value: 0001 0000 Output LRCK1 and BCK1 0001 Input LRCK2 and BCK2 (default) 0010 Output LRCK3 and BCK3 0011 Output LRCK4 and BCK4 0100 Output LRCK5 and BCK5 0101 Output LRCK6 and BCK6 0110 Output LRCK and BCK from DAC12 in master mode 0111 Output LRCK and BCK from DAC34 in master mode 1000 Output LRCK and BCK from ADC12 in master mode 1001 Output LRCK and BCK from ADC34 in master mode Others Reserved PORT-2 MUX-P2BL LRCK/BCK to MUX_ADCxx and MUXDACxx LRCK2 BCK2 LRCK1 BCK1 LRCK3 BCK3 LRCK4 BCK4 LRCK5 BCK5 LRCK6 BCK6 Register 101 LBS2[3:0] LRCK, BCK from ADC12 at Master LRCK, BCK from ADC34 at Master LRCK, BCK from DAC12 at Master LRCK, BCK from DAC34 at Master SCK to MUX_ADCxx and MUXDACxx MUX-P2SC SCK2 SCK1 SCK3 SCK4 SCK5 SCK6 Register 103 SCS2[2:0] DATA to MUXDACxx DATA1 DATA3 DATA4 DATA5 DATA6 DATA from ADC12 DATA from ADC34 DATA from GPIO1 DATA from GPIO2 MUX-P2DT DATA2 Register 102 DTS2[3:0] Figure 47. Detailed Diagram of PORT-2 74 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM5310 PCM5310 www.ti.com ............................................................................................................................................................................................ SLES244 – FEBRUARY 2009 LBS1[3:0]: LRCK/BCK Selection of PORT-1 (MUX_P2BL) These bits are used for routing LRCK and BCK of PORT-1. Any combination of LRCK1/BCK1 to LRCK6/BCK6 and LRCK/BCK of ADCs/DACs in master mode can be connected to PORT-1. Figure 48 shows a detailed diagram of PORT-1. Default value: 0000 0000 Input LRCK1 and BCK1 (default) 0001 Output LRCK2 and BCK2 0010 Output LRCK3 and BCK3 0011 Output LRCK4 and BCK4 0100 Output LRCK5 and BCK5 0101 Output LRCK6 and BCK6 0110 Output LRCK and BCK from DAC12 in master mode 0111 Output LRCK and BCK from DAC34 in master mode 1000 Output LRCK and BCK from ADC12 in master mode 1001 Output LRCK and BCK from ADC34 in master mode Others Reserved PORT-1 MUX-P1BL LRCK/BCK to MUX_ADCxx and MUXDACxx LRCK1 BCK1 LRCK2 BCK2 LRCK3 BCK3 LRCK4 BCK4 LRCK5 BCK5 LRCK6 BCK6 LRCK, BCK from ADC12 at Master Register 101 LRCK, BCK from ADC34 at Master LBS1[3:0] LRCK, BCK from DAC12 at Master LRCK, BCK from DAC34 at Master SCK to MUX_ADCxx and MUXDACxx SCK1 MUX-P1SC SCK2 SCK3 SCK4 SCK5 SCK6 Register 103 SCS1[2:0] DATA to MUXDACxx DATA2 DATA3 DATA4 DATA5 DATA6 DATA from ADC12 DATA from ADC34 MUX-P1DT DATA1 Register 102 DTS1[3:0] DAT A from GPIO1 DAT A from GPIO2 Figure 48. Detailed Diagram of PORT-1 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM5310 75 PCM5310 SLES244 – FEBRUARY 2009 ............................................................................................................................................................................................ www.ti.com Register 102 (66h) REG HEX DESCRIPTION B7 102 66h DATA selection of PORT-1 and PORT-2 B6 B5 DTS2[3:0] B4 B3 B2 B1 B0 DTS1[3:0] DTS2[3:0]: DATA Selection of PORT-2 (MUX_P2DT) These bits are used for routing DATA of PORT-2. Any combination of DATA1 to DATA6 and DATA of ADCs in master mode can be connected to PORT-2. Refer to Figure 47 for more details. Default value: 0001 0000 Output DATA1 0001 Input DATA2 (default) 0010 Output DATA3 0011 Output DATA4 0100 Output DATA5 0101 Output DATA6 0110 Output GPIO1 0111 Output GPIO2 1000 Output DATA from ADC12 1001 Output DATA from ADC34 Others Reserved DTS1[3:0]: DATA Selection of PORT-1 (MUX_P1DT) These bits are used for routing DATA of PORT-1. Any combination of DATA1 to DATA6 and DATA of ADCs in master mode can be connected to PORT-1. Refer to Figure 48 for more details. Default value: 0000 0000 Input DATA1 (default) 0001 Output DATA2 0010 Output DATA3 0011 Output DATA4 0100 Output DATA5 0101 Output DATA6 0110 Output GPIO1 0111 Output GPIO2 1000 Output DATA from ADC12 1001 Output DATA from ADC34 Others 76 Reserved Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM5310 PCM5310 www.ti.com ............................................................................................................................................................................................ SLES244 – FEBRUARY 2009 Register 103 (67h) REG HEX DESCRIPTION B7 103 67h SCK selection of PORT-1 and PORT-2 RSV B6 B5 B4 SCS2[3:0] B3 RSV B2 B1 B0 SCS1[3:0] SCS2[3:0]: SCK Selection of PORT-2 (MUX_P2SC) These bits are used for routing SCK of PORT-2. Any combination of SCK1 to SCK6 and SCK can be connected to PORT-2. Refer to Figure 47 for more details. Default value: 001 000 Output SCK1 001 Input SCK2 (default) 010 Output SCK3 011 Output SCK4 100 Output SCK5 101 Output SCK6 Others Reserved SCS1[3:0]: SCK Selection of PORT-1 (MUX_P1SC) These bits are used for routing SCK of PORT-2. Any combination of SCK1 to SCK6 and SCK can be connected to PORT-1. Refer to Figure 48 for more details. Default value: 000 000 Input SCK1 (default) 001 Output SCK2 010 Output SCK3 011 Output SCK4 100 Output SCK5 101 Output SCK6 Others Reserved Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM5310 77 PCM5310 SLES244 – FEBRUARY 2009 ............................................................................................................................................................................................ www.ti.com Register 104 (68h) REG HEX DESCRIPTION B7 104 68h LRCK/BCK selection of PORT-3 and PORT-4 B6 B5 B4 B3 LBS4[3:0] B2 B1 B0 LBS3[3:0] LBS4[3:0]: LRCK/BCK Selection of PORT-4 (MUX_P4BL) These bits are used for routing LRCK and BCK of PORT-4. Any combination of LRCK1/BCK1 to LRCK6/BCK6 and LRCK/BCK of ADCs/DACs in master mode can be connected to PORT-4. Figure 49 shows a detailed diagram of PORT-4. Default value: 0011 0000 Output LRCK1 and BCK1 0001 Output LRCK2 and BCK2 0010 Output LRCK3 and BCK3 0011 Input LRCK4 and BCK4 (default) 0100 Output LRCK5 and BCK5 0101 Output LRCK6 and BCK6 0110 Output LRCK and BCK from DAC12 in master mode 0111 Output LRCK and BCK from DAC34 in master mode 1000 Output LRCK and BCK from ADC12 in master mode 1001 Output LRCK and BCK from ADC34 in master mode Others Reserved PORT-4 MUX-P4BL LRCK/BCK to MUX_ADCxx and MUXDACxx LRCK4 BCK4 LRCK1 BCK1 LRCK2 BCK2 LRCK3 BCK3 LRCK5 BCK5 LRCK6 BCK6 Register 104 LBS4[3:0] LRCK, BCK from ADC12 at Master LRCK, BCK from ADC34 at Master LRCK, BCK from DAC12 at Master LRCK, BCK from DAC34 at Master SCK to MUX_ADCxx and MUXDACxx MUX-P4SC SCK4 SCK1 SCK2 SCK3 SCK5 SCK6 Register 106 SCS1[2:0] DATA to MUXDACxx DATA1 DATA2 DATA3 DATA5 DATA6 DATA from ADC12 DATA from ADC34 DATA from GPIO1 DATA from GPIO2 MUX-P4DT DATA4 Register 105 DTS4[3:0] Figure 49. Detailed Diagram of PORT-4 78 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM5310 PCM5310 www.ti.com ............................................................................................................................................................................................ SLES244 – FEBRUARY 2009 LBS3[3:0]: LRCK/BCK Selection of PORT-3 (MUX_P3BL) These bits are used for routing LRCK and BCK of PORT-3. Any combination of LRCK1/BCK1 to LRCK6/BCK6 and LRCK/BCK of ADCs/DACs in master mode can be connected to PORT-3. Figure 50 shows a detailed diagram of PORT-3. Default value: 0010 0000 Output LRCK1 and BCK1 0001 Output LRCK2 and BCK2 0010 Input LRCK3 and BCK3 (default) 0011 Output LRCK4 and BCK4 0100 Output LRCK5 and BCK5 0101 Output LRCK6 and BCK6 0110 Output LRCK and BCK from DAC12 in master mode 0111 Output LRCK and BCK from DAC34 in master mode 1000 Output LRCK and BCK from ADC12 in master mode 1001 Output LRCK and BCK from ADC34 in master mode Others Reserved PORT-3 MUX-P4BL LRCK/BCK to MUX_ADCxx and MUXDACxx LRCK3 BCK3 LRCK1 BCK1 LRCK2 BCK2 LRCK4 BCK4 LRCK5 BCK5 LRCK6 BCK6 Register 104 LBS3[3:0] LRCK, BCK from ADC12 at Master LRCK, BCK from ADC34 at Master LRCK, BCK from DAC12 at Master LRCK, BCK from DAC34 at Master SCK to MUX_ADCxx and MUXDACxx MUX-P3SC SCK3 SCK1 SCK2 SCK4 SCK5 SCK6 Register 106 SCS3[2:0] DATA to MUXDACxx DATA1 DATA2 DATA4 DATA5 DATA6 DATA from ADC12 DATA from ADC34 DATA from GPIO1 DATA from GPIO2 MUX-P3DT DATA3 Register 105 DTS3[3:0] Figure 50. Detailed Diagram of PORT-3 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM5310 79 PCM5310 SLES244 – FEBRUARY 2009 ............................................................................................................................................................................................ www.ti.com Register 105 (69h) REG HEX DESCRIPTION B7 105 69h DATA selection of PORT-3 and PORT-4 B6 B5 DTS4[3:0] B4 B3 B2 B1 B0 DTS3[3:0] DTS4[3:0]: DATA Selection of PORT-4 (MUX_P4DT) These bits are used for routing DATA of PORT-4. Any combination of DATA1 to DATA6 and DATA of ADCs in master mode can be connected to PORT-4. Refer to Figure 49 for more details. Default value: 0011 0000 Output DATA1 0001 Output DATA2 0010 Output DATA3 0011 Input DATA4 (default) 0100 Output DATA5 0101 Output DATA6 0110 Output GPIO1 0111 Output GPIO2 1000 Output DATA from ADC12 1001 Output DATA from ADC34 Others Reserved DTS3[3:0]: DATA Selection of PORT-3 (MUX_P3DT) These bits are used for routing DATA of PORT-3. Any combination of DATA1 to DATA6 and DATA of ADCs in master mode can be connected to PORT-3. Refer to Figure 50 for more details. Default value: 0010 0000 Output DATA1 0001 Output DATA2 0010 Input DATA3 (default) 0011 Output DATA4 0100 Output DATA5 0101 Output DATA6 0110 Output GPIO1 0111 Output GPIO2 1000 Output DATA from ADC12 1001 Output DATA from ADC34 Others 80 Reserved Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM5310 PCM5310 www.ti.com ............................................................................................................................................................................................ SLES244 – FEBRUARY 2009 Register 106 (6Ah) REG HEX DESCRIPTION B7 106 6Ah SCK selection of PORT-3 and PORT-4 RSV B6 B5 B4 SCS4[3:0] B3 RSV B2 B1 B0 SCS3[3:0] SCS4[3:0]: SCK Selection of PORT-4 (MUX_P4SC) These bits are used for routing SCK of PORT-4. Any combination of SCK1 to SCK6 and SCK can be connected to PORT-4. Refer to Figure 49 for more details. Default value: 011 000 Output SCK1 001 Output SCK2 010 Output SCK3 011 Input SCK4 (default) 100 Output SCK5 101 Output SCK6 Others Reserved SCS3[3:0]: SCK Selection of PORT-3 (MUX_P3SC) These bits are used for routing SCK of PORT-3. Any combination of SCK1 to SCK6 and SCK can be connected to PORT-3. Refer to Figure 50 for more details. Default value: 010 000 Output SCK1 001 Output SCK2 010 Input SCK3 (default) 011 Output SCK4 100 Output SCK5 101 Output SCK6 Others Reserved Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM5310 81 PCM5310 SLES244 – FEBRUARY 2009 ............................................................................................................................................................................................ www.ti.com Register 107 (6Bh) REG HEX DESCRIPTION B7 107 6Bh LRCK/BCK selection of PORT-5 and PORT-6 B6 B5 B4 B3 LBS6[3:0] B2 B1 B0 LBS5[3:0] LBS6[3:0]: LRCK/BCK Selection of PORT-6 (MUX_P6BL) These bits are used for routing LRCK and BCK of PORT-6. Any combination of LRCK1/BCK1 to LRCK6/BCK6 and LRCK/BCK of ADCs/DACs in master mode can be connected to PORT-6. Figure 51 shows a detailed diagram of PORT-6. Default value: 0101 0000 Output LRCK1 and BCK1 0001 Output LRCK2 and BCK2 0010 Output LRCK3 and BCK3 0011 Output LRCK4 and BCK4 0100 Output LRCK5 and BCK5 0101 Input LRCK6 and BCK6 (default) 0110 Output LRCK and BCK from DAC12 in master mode 0111 Output LRCK and BCK from DAC34 in master mode 1000 Output LRCK and BCK from ADC12 in master mode 1001 Output LRCK and BCK from ADC34 in master mode Others Reserved PORT-6 MUX-P6BL LRCK/BCK to MUX_ADCxx and MUXDACxx LRCK6 BCK6 LRCK1 BCK1 LRCK2 BCK2 LRCK3 BCK3 LRCK4 BCK4 LRCK5 BCK5 Register 107 LBS6[3:0] LRCK, BCK from ADC12 at Master LRCK, BCK from ADC34 at Master LRCK, BCK from DAC12 at Master LRCK, BCK from DAC34 at Master SCK to MUX_ADCxx and MUXDACxx MUX-P6SC SCK6 SCK1 SCK2 SCK3 SCK4 SCK5 Register 109 SCS6[2:0] DATA to MUXDACxx DATA1 DATA2 DATA3 DATA4 DATA5 DATA from ADC12 DATA from ADC34 DATA from GPIO1 DATA from GPIO2 MUX-P6DT DATA6 Register 108 DTS6[3:0] Figure 51. Detailed Diagram of PORT-6 82 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM5310 PCM5310 www.ti.com ............................................................................................................................................................................................ SLES244 – FEBRUARY 2009 LBS5[3:0]: LRCK/BCK Selection of PORT-5 (MUX_P5BL) These bits are used for routing LRCK and BCK of PORT-5. Any combination of LRCK1/BCK1 to LRCK6/BCK6 and LRCK/BCK of ADCs/DACs in master mode can be connected to PORT-5. Figure 52 shows a detailed diagram of PORT-5. Default value: 0100 0000 Output LRCK1 and BCK1 0001 Output LRCK2 and BCK2 0010 Output LRCK3 and BCK3 0011 Output LRCK4 and BCK4 0100 Input LRCK5 and BCK5 (default) 0101 Output LRCK6 and BCK6 0110 Output LRCK and BCK from DAC12 in master mode 0111 Output LRCK and BCK from DAC34 in master mode 1000 Output LRCK and BCK from ADC12 in master mode 1001 Output LRCK and BCK from ADC34 in master mode Others Reserved PORT-5 MUX-P5BL LRCK/BCK to MUX_ADCxx and MUXDACxx LRCK5 BCK5 LRCK1 BCK1 LRCK2 BCK2 LRCK3 BCK3 LRCK4 BCK4 LRCK6 BCK6 Register 107 LBS5[3:0] LRCK, BCK from ADC12 at Master LRCK, BCK from ADC34 at Master LRCK, BCK from DAC12 at Master LRCK, BCK from DAC34 at Master SCK to MUX_ADCxx and MUXDACxx MUX-P5SC SCK5 SCK1 SCK2 SCK3 SCK4 SCK6 Register 109 SCS5[2:0] DATA to MUXDACxx DATA1 DATA2 DATA3 DATA4 DATA6 DATA from ADC12 DATA from ADC34 DATA from GPIO1 DATA from GPIO2 MUX-P5DT DATA5 Register 108 DTS5[3:0] Figure 52. Detailed Diagram of PORT-5 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM5310 83 PCM5310 SLES244 – FEBRUARY 2009 ............................................................................................................................................................................................ www.ti.com Register 108 (6Ch) REG HEX DESCRIPTION B7 108 6Ch DATA selection of PORT-5 and PORT-6 B6 B5 DTS6[3:0] B4 B3 B2 B1 B0 DTS5[3:0] DTS6[3:0]: DATA Selection of PORT-6 (MUX_P6DT) These bits are used for routing DATA of PORT-6. Any combination of DATA1 to DATA6 and DATA of ADCs in master mode can be connected to PORT-6. Refer to Figure 51 for more details. Default value: 0101 0000 Output DATA1 0001 Output DATA2 0010 Output DATA3 0011 Output DATA4 0100 Output DATA5 0101 Input DATA6 (default) 0110 Output GPIO1 0111 Output GPIO2 1000 Output DATA from ADC12 1001 Output DATA from ADC34 Others Reserved DTS5[3:0]: DATA Selection of PORT-5 (MUX_P5DT) These bits are used for routing DATA of PORT-5. Any combination of DATA1 to DATA6 and DATA of ADCs in master mode can be connected to PORT-5. Refer to Figure 52 for more details. Default value: 0100 0000 Output DATA1 0001 Output DATA2 0010 Output DATA3 0011 Output DATA4 0100 Input DATA5 (default) 0101 Output DATA6 0110 Output GPIO1 0111 Output GPIO2 1000 Output DATA from ADC12 1001 Output DATA from ADC34 Others 84 Reserved Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM5310 PCM5310 www.ti.com ............................................................................................................................................................................................ SLES244 – FEBRUARY 2009 Register 109 (6Dh) REG HEX DESCRIPTION B7 109 6Dh SCK selection of PORT-5 and PORT-6 RSV B6 B5 B4 SCS6[3:0] B3 RSV B2 B1 B0 SCS5[3:0] SCS6[3:0]: SCK Selection of PORT-6 (MUX_P6SC) These bits are used for routing SCK of PORT-6. Any combination of SCK1 to SCK6 and SCK can be connected to PORT-6. Refer to Figure 51 for more details. Default value: 101 000 Output SCK1 001 Output SCK2 010 Output SCK3 011 Output SCK4 100 Output SCK5 101 Input SCK6 (default) Others Reserved SCS5[3:0]: SCK Selection of PORT-5 (MUX_P5SC) These bits are used for routing SCK of PORT-5. Any combination of SCK1 to SCK6 and SCK can be connected to PORT-5. Refer to Figure 52 for more details. Default value: 100 000 Output SCK1 001 Output SCK2 010 Output SCK3 011 Output SCK4 100 Input SCK5 (default) 101 Output SCK6 Others Reserved Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM5310 85 PCM5310 SLES244 – FEBRUARY 2009 ............................................................................................................................................................................................ www.ti.com Register 110 (6Eh) REG HEX DESCRIPTION B7 110 6Eh LRCK/BCK selection of DAC12 and DAC34 B6 B5 D34LB[3:0] B4 B3 B2 B1 B0 D12LB[3:0] D34LB[3:0]: LRCK/BCK Selection of DAC34 (MUX_DA34) These bits are used for routing LRCK and BCK from each audio interface port to DAC34, or routing LRCK and BCK from DACs/ADCs to each audio interface port in master mode. Refer to Figure 33 for more details. Default value: 0100 0000 Select LRCK and BCK from PORT-1 0001 Select LRCK and BCK from PORT-2 0010 Select LRCK and BCK from PORT-3 0011 Select LRCK and BCK from PORT-4 0100 Select LRCK and BCK from PORT-5 (default) 0101 Select LRCK and BCK from PORT-6 0110 Select LRCK and BCK from DAC12 in master mode 0111 Select LRCK and BCK from DAC34 in master mode 1000 Select LRCK and BCK from ADC12 in master mode 1001 Select LRCK and BCK from ADC34 in master mode Others Reserved D12LB[3:0] LRCK/BCK Selection of DAC12 (MUX_DA12) These bits are used for routing LRCK and BCK from each audio interface port to DAC12, or routing LRCK and BCK from DACs/ADCs to each audio interface port in master mode. Refer to Figure 33 for more details. Default value: 0011 0000 Select LRCK and BCK from PORT-1 0001 Select LRCK and BCK from PORT-2 0010 Select LRCK and BCK from PORT-3 0011 Select LRCK and BCK from PORT-4 (default) 0100 Select LRCK and BCK from PORT-5 0101 Select LRCK and BCK from PORT-6 0110 Select LRCK and BCK from DAC12 in master mode 0111 Select LRCK and BCK from DAC34 in master mode 1000 Select LRCK and BCK from ADC12 in master mode 1001 Select LRCK and BCK from ADC34 in master mode Others 86 Reserved Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM5310 PCM5310 www.ti.com ............................................................................................................................................................................................ SLES244 – FEBRUARY 2009 Register 111 (6Fh) REG HEX DESCRIPTION B7 111 6Fh DATA selection of DAC12 and DAC34 B6 B5 D34DT[3:0] B4 B3 B2 B1 B0 D12DT[3:0] D34DT[3:0] DATA Selection of DAC34 (MUX_DA34) These bits are used for routing DATA from each audio interface port to DAC34, or routing DATA from ADCs to each audio interface port in master mode. Refer to Figure 33 for more details. Default value: 0100 0000 Select DATA from PORT-1 0001 Select DATA from PORT-2 0010 Select DATA from PORT-3 0011 Select DATA from PORT-4 0100 Select DATA from PORT-5 (default) 0101 Select DATA from PORT-6 0110 Select DATA from GPIO1 0111 Select DATA from GPIO2 1000 Select DATA from ADC12 1001 Select DATA from ADC34 Others Reserved D12DT[3:0] DATA Selection of DAC12 (MUX_DA12) These bits are used for routing DATA from each audio interface port to DAC12, or routing DATA from ADCs to each audio interface port in master mode. Refer to Figure 33 for more details. Default value: 0011 0000 Select DATA from PORT-1 0001 Select DATA from PORT-2 0010 Select DATA from PORT-3 0011 Select DATA from PORT-4 (default) 0100 Select DATA from PORT-5 0101 Select DATA from PORT-6 0110 Select DATA from GPIO1 0111 Select DATA from GPIO2 1000 Select DATA from ADC12 1001 Select DATA from ADC34 Others Reserved Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM5310 87 PCM5310 SLES244 – FEBRUARY 2009 ............................................................................................................................................................................................ www.ti.com Register 112 (70h) REG HEX DESCRIPTION B7 112 70h SCK selection of DAC12 and DAC34 RSV B6 B5 B4 D34SC[3:0] B3 RSV B2 B1 B0 D12SC[3:0] D34SC[2:0] SCK Selection of DAC34 (MUX_DA34) These bits are used for routing SCK from each audio interface port to DAC34. Refer to Figure 33 for more details. Default value: 100 000 Select SCK from PORT-1 001 Select SCK from PORT-2 010 Select SCK from PORT-3 011 Select SCK from PORT-4 100 Select SCK from PORT-5 (default) 101 Select SCK from PORT-6 Others Reserved D12SC[2:0] SCK Selection of DAC12 (MUX_DA12) These bits are used for routing SCK from each audio interface port to DAC12. Refer to Figure 33 for more details. Default value: 011 000 Select SCK from PORT-1 001 Select SCK from PORT-2 010 Select SCK from PORT-3 011 Select SCK from PORT-4 (default) 100 Select SCK from PORT-5 101 Select SCK from PORT-6 Others 88 Reserved Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM5310 PCM5310 www.ti.com ............................................................................................................................................................................................ SLES244 – FEBRUARY 2009 Register 116 (74h) REG HEX DESCRIPTION B7 116 74h LRCK/BCK selection of ADC12 and ADC34 B6 B5 A34LB[3:0] B4 B3 B2 B1 B0 A12LB[3:0] A34LB[3:0]: LRCK/BCK Selection of ADC34 (MUX_AD34) These bits are used for routing LRCK and BCK from each audio interface port to ADC34, or routing LRCK and BCK from DACs/ADCs to each audio interface port in master mode. Refer to Figure 33 for more details. Default value: 0001 0000 Select LRCK and BCK from PORT-1 0001 Select LRCK and BCK from PORT-2 (default) 0010 Select LRCK and BCK from PORT-3 0011 Select LRCK and BCK from PORT-4 0100 Select LRCK and BCK from PORT-5 0101 Select LRCK and BCK from PORT-6 0110 Select LRCK and BCK from DAC12 in master mode 0111 Select LRCK and BCK from DAC34 in master mode 1000 Select LRCK and BCK from ADC12 in master mode 1001 Select LRCK and BCK from ADC34 in master mode Others Reserved A12LB[3:0] LRCK/BCK Selection of ADC12 (MUX_AD12) These bits are used for routing LRCK and BCK from each audio interface port to ADC12, or routing LRCK and BCK from DACs/ADCs to each audio interface port in master mode. Refer to Figure 33 for more details. Default value: 0000 0000 Select LRCK and BCK from PORT-1 (default) 0001 Select LRCK and BCK from PORT-2 0010 Select LRCK and BCK from PORT-3 0011 Select LRCK and BCK from PORT-4 0100 Select LRCK and BCK from PORT-5 0101 Select LRCK and BCK from PORT-6 0110 Select LRCK and BCK from DAC12 in master mode 0111 Select LRCK and BCK from DAC34 in master mode 1000 Select LRCK and BCK from ADC12 in master mode 1001 Select LRCK and BCK from ADC34 in master mode Others Reserved Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM5310 89 PCM5310 SLES244 – FEBRUARY 2009 ............................................................................................................................................................................................ www.ti.com Register 117 (75h) REG HEX DESCRIPTION B7 117 75h SCK selection of ADC12 and ADC34 RSV B6 B5 B4 A34SC[3:0] B3 RSV B2 B1 B0 A12SC[3:0] A34SC[2:0] SCK Selection of ADC34 (MUX_AD34) These bits are used for routing SCK from each audio interface port to ADC34. Refer to Figure 33 for more details. Default value: 001 000 Select SCK from PORT-1 001 Select SCK from PORT-2 (default) 010 Select SCK from PORT-3 011 Select SCK from PORT-4 100 Select SCK from PORT-5 101 Select SCK from PORT-6 Others Reserved A12SC[2:0] SCK Selection of ADC12 (MUX_AD12) These bits are used for routing SCK from each audio interface port to ADC12. Refer to Figure 33 for more details. Default value: 000 000 Select SCK from PORT-1 (default) 001 Select SCK from PORT-2 010 Select SCK from PORT-3 011 Select SCK from PORT-4 100 Select SCK from PORT-5 101 Select SCK from PORT-6 Others 90 Reserved Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM5310 PCM5310 www.ti.com ............................................................................................................................................................................................ SLES244 – FEBRUARY 2009 Register 118 (76h) REG HEX DESCRIPTION B7 118 76h GPIO1 and GPIO2 audio data selection B6 B5 GP2S[3:0] B4 B3 B2 B1 B0 GP1S[3:0] GP2S[3:0] GPIO2 Audio Data Selection Default value: 0111 0000 Output DATA1 0001 Output DATA2 0010 Output DATA3 0011 Output DATA4 0100 Output DATA5 0101 Output DATA6 0110 Output GPIO1 0111 Input GPIO2 (default) 1000 Output DATA from ADC12 1001 Output DATA from ADC34 1010 Use GPIO function Others Reserved GP1S[3:0] GPIO1 Audio Data Selection Default value: 0110 0000 Output DATA1 0001 Output DATA2 0010 Output DATA3 0011 Output DATA4 0100 Output DATA5 0101 Output DATA6 0110 Input GPIO1 (default) 0111 Output GPIO2 1000 Output DATA from ADC12 1001 Output DATA from ADC34 1010 Use GPIO function Others Reserved Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM5310 91 PCM5310 SLES244 – FEBRUARY 2009 ............................................................................................................................................................................................ www.ti.com BASIC CONNECTION DIAGRAMS (1) (2) Line Input Line Output (19) HPOL External Circuit External Circuit Headphone Output (22) HPOR (3) (25) VCOMDA (64) VCOMAD (62) VREFAD1 1.0 mF 1.0 mF 1.0 mF Reference Voltage (63) VREFAD2 22W to 100W Audio Interface and Clocks External Circuit External Circuit External Circuit + AIN6R (12) External Circuit External Circuit External Circuit + External Circuit External Circuit External Circuit External Circuit External Circuit External Circuit External Circuit External Circuit (13) LO1L (14) LO1R (15) LO2L (16) LO2R + External Circuit External Circuit AIN1L (1) AIN1R (2) AIN2L (3) AIN2R (4) AIN3L (5) AIN3R (6) AIN4L (7) AIN4R (8) AIN5L (9) AIN5R (10) AIN6L (11) SCK1 (29) BCK1 (30) LRCK1 (31) DATA1 (32) SCK2 (33) BCK2 (34) LRCK2 (35) DATA2 (36) SCK3 (37) BCK3 (38) LRCK3 (39) DATA3 (40) SCK4 (43) BCK4 (44) LRCK4 (45) DATA4 (46) SCK5 (47) BCK5 (48) LRCK5 (49) DATA5 (50) SCK6 (51) BCK6 (52) LRCK6 (53) DATA6 (54) (1) See Figure 54 for the line input. (2) See Figure 55 for the line output. (3) See Figure 56 for the headphone output. (41) VDD > 4.7 mF (42) DGND (23) VCCDA + > 4.7 mF (24) AGNDDA (60) VCCAD + > 4.7 mF (61) AGNDAD (20) VCCP (17) HGND Power Supply + > 4.7 mF (21) PGND (18) VCCH 3.3 V + 9.0 V + > 4.7 mF (26) AGNDS (58) RSTB (59) AMUTE (27) SDA (28) SCL (55) GPIO1 (26) GPIO2 Control Interface (27) GPIO3 Figure 53. Basic Connections 92 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM5310 PCM5310 www.ti.com ............................................................................................................................................................................................ SLES244 – FEBRUARY 2009 47 kW (typ) C1 R1 C5 AINL (1) AINL (1) + + R3 47 kW (typ) C3 47 kW (typ) 47 kW (typ) To ADC 47 kW (typ) C2 47 kW (typ) C6 AINR (2) AINR (2) + + R2 R4 To ADC C4 47 kW (typ) 47 kW (typ) To ADC (a) External Circuit for Line Input with Low-Pass Filter To ADC (b) External Circuit for Line Input without Low-Pass Filter 47 kW (typ) C7 AINL (1) 47 kW (typ) To ADC 47 kW (typ) AINR (2) 47 kW (typ) To ADC (c) External Circuit for not using Analog Input R1, R2: Greater than 100 kΩ R3, R4: 100 Ω to 1 kΩ C1, C2, C5, C6: 1 µF to 47 µF C3, C4: 0.01 µF to 0.001 µF C7: Less than 0.1 µF Figure 54. External Circuit for the Line Input Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM5310 93 PCM5310 SLES244 – FEBRUARY 2009 ............................................................................................................................................................................................ www.ti.com fC = 85 kHz From DAC From DAC C1 LO1L (13) R3 C5 + R1 + LO1L (13) fC = 85 kHz R5 R7 C3 C7 Mute Circuit From DAC From DAC C2 LO1R (14) R4 C6 + R2 + LO1R (14) Mute Circuit R6 R8 C4 C8 Mute Circuit Mute Circuit (a) External Circuit for Line Output with Low-Pass Filter R1, R2, R5, R3, R4, R7: C1, C2, C5, C3, C4, C7, (b) External Circuit for Line Output with Low-Pass Filter R6: 270 Ω > 100 kΩ C6: 1 µF to 47 µF C8: 6800 pF Figure 55. External Circuit for the Line Output From DAC C1 From DAC R1 HPOL (19) R3 R5 Mute Circuit C3 From DAC C2 C7 From DAC R2 HPOR (20) R4 Mute Circuit C6 + + HPOR (20) C5 + + HPOL (19) R6 Mute Circuit C4 (a) External Circuit with Short-Circuit protection Resistor C8 Mute Circuit (b) External Circuit without Short-Circuit Protection Resistor R1, R2 : 4 Ω to 16 Ω R3, R4, R5, R6 : 22 Ω C1, C2, C5, C6: 47 µF to 220 µF C3, C4, C7, C8 : 0.022 µF Figure 56. External Circuit for the Headphone Output 94 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM5310 PCM5310 www.ti.com ............................................................................................................................................................................................ SLES244 – FEBRUARY 2009 BOARD DESIGN AND LAYOUT CONSIDERATIONS POWER-SUPPLY PINS The digital and analog power supplies (VCC, VCCDA, VCCAD, VCCP, and VCCH) to the PCM5310 should be bypassed to the corresponding ground pins with a 1-µF to 4.7-µF electrolytic or ceramic capacitor, placed as close to the pins as possible to maximize the dynamic performance of ADC, DAC, and other analog circuits. If the power supply includes high-frequency noise, it is recommended to add a 0.1 µF ceramic capacitor as close as possible to the power-supply lines to improve the dynamic performance. To maximize the dynamic performance of the ADC, DAC, and other analog circuits, the analog and ground pins (DGND, AGNDDA, AGNDAD, PGND, HGND and AGNDS) are not connected internally. These grounds should have a low impedance to avoid digital noise feeding to the analog ground. Therefore, they should be connected directly to each other under the device to reduce the potential of a noise problem. ANALOG INPUT PINS All analog input pins (AIN1L/AIN1R to AIN6L/AIN6R) are single-ended inputs with an analog multiplexer. Antialiasing low-pass filters are included on the these inputs to remove the out-of-band nose from the audio. If the performance of these filters is not sufficient for a given application, appropriate external antialiasing filters are required. The passive RC filter (see Figure 54) is used in general. Any pins that are not used in a given application should be left open or connected to ground with a small, 0.1-µF ceramic capacitor. LINE OUTPUT PINS All line output pins (LO1L, LO1R, LO2L and LO2R) are single-ended outputs with a 2-VRMS driver. An amplifier with a low-pass filter is not required as in a conventional DAC; however, the delta-sigma modulator generates out-of-band noise. The passive RC filter (see Figure 55) is used to remove this noise in general. If any line output pins are not used within a given application, they should be left open. HEADPHONE OUTPUT PINS The headphone output pins (HPOL and HPOR) are single-ended outputs with more than 30-mW output power into either a 16-Ω or 32-Ω load. If the headphone output pins are not used within a given application, they should be left open. Adding a small resistor to these outputs is recommended (see Figure 56). in order to protect the application and device from short-circuiting. COMMON VOLTAGE PINS A 1µF ceramic capacitor should be connected between the common voltage pins (VCOMAD and VCOMDA) for the analog circuit and ground to ensure low source impedance of the ADC and DAC common voltages. This capacitor should be located as close as possible to these pins. REFERENCE VOLTAGE PINS A 1-µF ceramic capacitor should be connected between the VREFAD1 pin and ground to ensure low source impedance of ADC reference voltage. This capacitor should be located as close as possible to these pins. VREFAD2 pin should be connected to directly ground. DIGITAL OUTPUT PINS The audio interface pins (LRCKx, BCKx, SCKx), clock pins (SCKx) and general-purpose input/output (GPIOx) pins change from input mode to output mode through register settings. In output mode, these pins have adequate load drive capability (see the Electrical Characteristics); however, if the signal lines are long, placing a buffer near the PCM5310 and minimizing the load capacitor is recommended in order to optimize crosstalk between the digital and analog circuits, maximize the dynamic performance of the ADC and DAC, and reduce overall power consumption. The digital output pins should be open if they are not used in a given application. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM5310 95 PCM5310 SLES244 – FEBRUARY 2009 ............................................................................................................................................................................................ www.ti.com DIGITAL INPUT PINS Series resistors (ranging from 22 Ω to 100 Ω) are recommended for the SCKx, LRCKx, BCKx, and DATAx pins. These series resistors combine with the stray printed circuit board (PCB) and device input capacitance to form a low-pass filter that removes high-frequency noise from the digital signal, thus reducing high-frequency emissions. All digital input pins should be connected to ground if they are not used in a given application. PowerPAD (THERMAL PAD) The PCM5310 is available in an HTQFP-64 PowerPAD package. The PowerPAD is a heatsink, which is exposed metal at the bottom of the package. The PowerPAD works to conduct heat away from the silicon through thermal vias located at the bottom of the PowerPAD. The PowerPAD does not need to be soldered onto an exposed metal area of the PCB because the device works within the absolute maximum rating (junction temperature = +150°C) without soldering the PowerPAD. Refer to application note SLMA002, PowerPAD Thermally Enhanced Package, when considering whether to solder the PowerPAD in order to reduce more heat from the device. 96 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM5310 PACKAGE OPTION ADDENDUM www.ti.com 16-Apr-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty PCM5310PAP ACTIVE HTQFP PAP 64 160 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR PCM5310PAPR ACTIVE HTQFP PAP 64 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 5-Mar-2009 TAPE AND REEL INFORMATION *All dimensions are nominal Device PCM5310PAPR Package Package Pins Type Drawing HTQFP PAP 64 SPQ Reel Reel Diameter Width (mm) W1 (mm) 1000 330.0 24.4 Pack Materials-Page 1 A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 13.0 13.0 1.4 16.0 24.0 Q2 PACKAGE MATERIALS INFORMATION www.ti.com 5-Mar-2009 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) PCM5310PAPR HTQFP PAP 64 1000 346.0 346.0 41.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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