PDU16F
data 3
delay
devices, inc.
6-BIT PROGRAMMABLE
DELAY LINE
(SERIES PDU16F)
FEATURES
•
•
•
•
•
•
•
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PACKAGES
Digitally programmable in 64 delay steps
Monotonic delay-versus-address variation
Two separate outputs: inverting & non-inverting
Precise and stable delays
Input & outputs fully TTL interfaced & buffered
10 T2L fan-out capability
Fits standard 24-pin DIP socket
Auto-insertable
OUT/
1
24
VCC
OUT
2
23
A0
EN/
3
22
A1
GND
4
21
A2
N/C
5
20
VCC
IN
6
19
N/C
N/C
7
18
N/C
GND
8
17
N/C
N/C
9
16
VCC
N/C
10
15
A3
EN/
11
14
A4
GND
12
13
A5
PDU16F-xx
DIP
PDU16F-xxA4
Gull-Wing
PDU16F-xxB4
J-Lead
PDU16F-xxM
Military DIP
PDU16F-xxMC4
Military Gull-Wing
FUNCTIONAL DESCRIPTION
PIN DESCRIPTIONS
The PDU16F-series device is a 6-bit digitally programmable delay line.
The delay, TDA, from the input pin (IN) to the output pins (OUT, OUT/)
depends on the address code (A5-A0) according to the following formula:
IN
OUT
OUT/
A0-A5
EN/
VCC
GND
TDA = TD0 + TINC * A
Delay Line Input
Non-inverted Output
Inverted Output
Address Bits
Output Enable
+5 Volts
Ground
where A is the address code, TINC is the incremental delay of the device,
and TD0 is the inherent delay of the device. The incremental delay is
specified by the dash number of the device and can range from 0.5ns through 10ns, inclusively. The
enable pins (EN/) are held LOW during normal operation. These pins must always be in the same state
and may be tied together externally. When these signals are brought HIGH, OUT and OUT/ are forced
into LOW and HIGH states, respectively. The address is not latched and must remain asserted during
normal operation.
SERIES SPECIFICATIONS
DASH NUMBER SPECIFICATIONS
•
Part
Number
PDU16F-.5
PDU16F-1
PDU16F-2
PDU16F-3
PDU16F-4
PDU16F-5
PDU16F-6
PDU16F-8
PDU16F-10
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Programmed delay tolerance: 5% or 1ns,
whichever is greater
Inherent delay (TD0): 9ns typical (OUT)
8ns typical (OUT/)
Setup time and propagation delay:
Address to input setup (TAIS): 5ns
Disable to output delay (TDISO): 6ns typ. (OUT)
Operating temperature: 0° to 70° C
Temperature coefficient: 100PPM/°C (excludes TD0)
Supply voltage VCC: 5VDC ± 5%
Supply current: ICCH = 74ma
ICCL = 30ma
Minimum pulse width: 10% of total delay
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Incremental Delay
Per Step (ns)
.5 ± .3
1 ± .5
2 ± .5
3 ± 1.0
4 ± 1.0
5 ± 1.0
6 ± 1.0
8 ± 1.0
10 ± 1.5
Total Delay
Change (ns)
31.5 ± 1.6
63 ± 3.2
126 ± 6.3
189 ± 9.5
252 ± 12.6
315 ± 15.8
378 ± 18.9
504 ± 25.2
630 ± 31.5
NOTE: Any dash number between .5 and 10 not
shown is also available.
1997 Data Delay Devices
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
1
PDU16F
APPLICATION NOTES
possibility of spurious signals persists until the
required TDISH has elapsed.
ADDRESS UPDATE
The PDU16F is a memory device. As such,
special precautions must be taken when
changing the delay address in order to prevent
spurious output signals. The timing restrictions
are shown in Figure 1.
INPUT RESTRICTIONS
There are three types of restrictions on input
pulse width and period listed in the AC
Characteristics table. The recommended
conditions are those for which the delay
tolerance specifications and monotonicity are
guaranteed. The suggested conditions are
those for which signals will propagate through the
unit without significant distortion. The absolute
conditions are those for which the unit will
produce some type of output for a given input.
After the last signal edge to be delayed has
appeared on the OUT pin, a minimum time,
TOAX, is required before the address lines can
change. This time is given by the following
relation:
TOAX = max { (Ai - A i-1) * TINC , 0 }
where A i-1 and Ai are the old and new address
codes, respectively. Violation of this constraint
may, depending on the history of the input signal,
cause spurious signals to appear on the OUT
pin. The possibility of spurious signals persists
until the required TOAX has elapsed.
When operating the unit between the
recommended and absolute conditions, the
delays may deviate from their values at low
frequency. However, these deviations will
remain constant from pulse to pulse if the input
pulse width and period remain fixed. In other
words, the delay of the unit exhibits frequency
and pulse width dependence when operated
beyond the recommended conditions. Please
consult the technical staff at Data Delay Devices
if your application has specific high-frequency
requirements.
A similar situation occurs when using the EN/
signal to disable the output while IN is active. In
this case, the unit must be held in the disabled
state until the device is able to “clear” itself. This
is achieved by holding the EN/ signal high and
the IN signal low for a time given by:
Please note that the increment tolerances listed
represent a design goal. Although most delay
increments will fall within tolerance, they are not
guaranteed throughout the address range of the
unit. Monotonicity is, however, guaranteed over
all addresses.
TDISH = Ai * TINC
Violation of this constraint may, depending on
the history of the input signal, cause spurious
signals to appear on the OUT pin. The
A5-A0
A i-1
Ai
TOAX
TAENS
TAIS
EN/
TENIS
PWIN
TDISH
IN
TDA
PWOUT
TDISO
OUT
TSKEW
OUT/
Figure 1: Timing Diagram
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DATA DELAY DEVICES, INC.
Tel: 973-773-2299 Fax: 973-773-9672
Electronic-Library Service CopyRight 2003
http://www.datadelay.com
2
PDU16F
DEVICE SPECIFICATIONS
TABLE 1: AC CHARACTERISTICS
PARAMETER
Total Programmable Delay
Inherent Delay
Output Skew
Disable to Output Low Delay
Address to Enable Setup Time
Address to Input Setup Time
Enable to Input Setup Time
Output to Address Change
Disable Hold Time
Absolute
Input Period
Suggested
Recommended
Absolute
Input Pulse Width
Suggested
Recommended
SYMBOL
TDT
TD0
TSKEW
TDISO
TAENS
TAIS
TENIS
TOAX
TDISH
PERIN
PERIN
PERIN
PWIN
PWIN
PWIN
MIN
TYP
63
9.0
1.5
6.0
UNITS
TINC
ns
ns
ns
ns
ns
ns
2.0
5.0
2.5
See Text
See Text
20
40
200
10
20
100
% of TDT
% of TDT
% of TDT
% of TDT
% of TDT
% of TDT
TABLE 2: ABSOLUTE MAXIMUM RATINGS
PARAMETER
DC Supply Voltage
Input Pin Voltage
Storage Temperature
Lead Temperature
SYMBOL
VCC
VIN
TSTRG
TLEAD
MIN
-0.3
-0.3
-55
MAX
7.0
VDD+0.3
150
300
UNITS
V
V
C
C
NOTES
10 sec
TABLE 3: DC ELECTRICAL CHARACTERISTICS
(0C to 70C, 4.75V to 5.25V)
PARAMETER
High Level Output Voltage
SYMBOL
VOH
Low Level Output Voltage
VOL
High Level Output Current
Low Level Output Current
High Level Input Voltage
Low Level Input Voltage
Input Clamp Voltage
Input Current at Maximum
Input Voltage
High Level Input Current
Low Level Input Current
Short-circuit Output Current
Output High Fan-out
Output Low Fan-out
IOH
IOL
VIH
VIL
VIK
IIHH
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IIH
IIL
IOS
MIN
2.5
TYP
3.4
MAX
UNITS
V
0.35
0.5
V
-1.0
20.0
0.8
-1.2
0.1
mA
mA
V
V
V
mA
20
-0.6
-150
25
12.5
µA
mA
mA
Unit
Load
2.0
-60
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
NOTES
VCC = MIN, IOH = MAX
VIH = MIN, VIL = MAX
VCC = MIN, IOL = MAX
VIH = MIN, VIL = MAX
VCC = MIN, II = IIK
VCC = MAX, VI = 7.0V
VCC = MAX, VI = 2.7V
VCC = MAX, VI = 0.5V
VCC = MAX
3
PDU16F
PACKAGE DIMENSIONS
.020 TYP.
.040 TYP.
.010 TYP.
24 23 22 21 20 19 18 17 16 15 14 13
.270
TYP.
1
24 23 22 21 20 19 18 17 16 15 14 13
Lead Material:
Nickel-Iron alloy 42
TIN PLATE
1
2
3
4
5
6
7
8
2
3
4
5
6
7
8
9
.430
TYP.
10 11 12
.110
.100
.300
MAX.
1.100
1.290 MAX.
9 10 11 12
Commercial Gull-Wing (PDU16F-xxA4)
.280
MAX.
1.270
.020 TYP.
.290
MAX.
.040 TYP.
.050 TYP.
24 23 22 21 20 19 18 17 16 15 14 13
.320
TYP.
.270
TYP.
1
.015 TYP.
2
3
5
6
7
8
9
.110
10 11 12
.100
.350
MAX.
1.100
.350
MAX.
1.100
1.290 MAX.
Commercial DIP (PDU16F-xx)
24 23 22 21 20
4
.010±.002
.070 MAX.
.018 TYP.
.050
TYP.
.110
TYP.
Commercial J-Lead (PDU16F-xxB4)
16 15 14 13
.410
MAX.
1
2
3
4
6
8
11 12
.020 TYP.
.040 TYP.
1.300 TYP.
.130
MIN.
.100 TYP.
1.100 TYP.
1
2
.300
TYP.
Military DIP (PDU16F-xxM)
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3
4
5
6
7
8
9
.007
±.005
10 11 12
.012 TYP.
.090
.100
.882
±.005
.710 .590
±.005 MAX.
.300
MAX.
.018 TYP.
.010±.002
24 23 22 21 20 19 18 17 16 15 14 13
.100
1.100
1.280±.020
.280
MAX.
.050
±.010
Military Gull-Wing (PDU16F-xxMC4)
DATA DELAY DEVICES, INC.
Tel: 973-773-2299 Fax: 973-773-9672
Electronic-Library Service CopyRight 2003
http://www.datadelay.com
4
PDU16F
DELAY LINE AUTOMATED TESTING
TEST CONDITIONS
INPUT:
Ambient Temperature: 25oC ± 3oC
Supply Voltage (Vcc): 5.0V ± 0.1V
Input Pulse:
High = 3.0V ± 0.1V
Low = 0.0V ± 0.1V
Source Impedance:
50Ω Max.
Rise/Fall Time:
3.0 ns Max. (measured
between 0.6V and 2.4V )
Pulse Width:
PWIN = 1.5 x Total Delay
Period:
PERIN = 4.5 x Total Delay
OUTPUT:
Load:
Cload:
Threshold:
1 FAST-TTL Gate
5pf ± 10%
1.5V (Rising & Falling)
NOTE: The above conditions are for test only and do not in any way restrict the operation of the device.
PRINTER
COMPUTER
SYSTEM
REF
PULSE
GENERATOR
OUT
IN
DEVICE UNDER
TEST (DUT)
TRIG
OUT
IN
TRIG
TIME INTERVAL
COUNTER
Test Setup
PERIN
PWIN
TRISE
INPUT
SIGNAL
TFALL
VIH
2.4V
1.5V
0.6V
2.4V
1.5V
0.6V
TDAR
OUTPUT
SIGNAL
VIL
TDAF
VOH
1.5V
1.5V
VOL
Timing Diagram For Testing
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DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
5