M
PIC16CR54C
ROM-Based 8-Bit CMOS Microcontroller Series
Pin Diagrams
Devices Included in this Data Sheet:
• PIC16CR54C
PDIP and SOIC
High-Performance RISC CPU:
Device
Pins
I/O
ROM
•1
2
3
4
5
6
7
8
9
PIC16CR54C
• Only 33 single word instructions to learn
• All instructions are single cycle (200 ns) except for
program branches which are two-cycle
• Operating speed: DC - 20 MHz clock input
DC - 200 ns instruction cycle
RA2
RA3
T0CKI
MCLRVPP
VSS
RB0
RB1
RB2
RB3
18
17
16
15
14
13
12
11
10
RA1
RA0
OSC1/CLKIN
OSC2/CLKOUT
VDD
RB7
RB6
RB5
RB4
RAM
PIC16CR54C
18
12
512
25
• 12-bit wide instructions
• 8-bit wide data path
• Seven or eight special function hardware registers
• Two-level deep hardware stack
• Direct, indirect and relative addressing modes for
data and instructions
Peripheral Features:
RA2
RA3
T0CKI
MCLRVPP
VSS
VSS
RB0
RB1
RB2
RB3
•1
2
3
4
5
6
7
8
9
10
PIC16CR54C
• 8-bit real time clock/counter (TMR0) with 8-bit
programmable prescaler
• Power-On Reset (POR)
• Device Reset Timer (DRT)
• Watchdog Timer (WDT) with its own on-chip
RC oscillator for reliable operation
• Programmable code-protection
• Power saving SLEEP mode
• Selectable oscillator options:
- RC:
Low-cost RC oscillator
- XT:
Standard crystal/resonator
- HS:
High-speed crystal/resonator
- LP:
Power saving, low-frequency crystal
SSOP
20
19
18
17
16
15
14
13
12
11
RA1
RA0
OSC1/CLKIN
OSC2/CLKOUT
VDD
VDD
RB7
RB6
RB5
RB4
CMOS Technology:
• Low-power, high-speed CMOS ROM technology
• Fully static design
• Wide-operating voltage and temperature range:
- ROM Commercial/Industrial 3.0V to 5.5V
• Low-power consumption
- < 2 mA typical @ 5V, 4 MHz
- 15 µA typical @ 3V, 32 kHz
- < 0.6 µA typical standby current
(with WDT disabled) @ 3V, 0°C to 70°C
1998 Microchip Technology Inc.
Preliminary
DS40191A-page 1
PIC16CR54C
Device Differences
Oscillator
Selection
(Program)
Oscillator
Process
Technology
(Microns)
3.0-6.25
User
See Note 1
2.5-6.25
Factory
See Note 1
PIC16C54A
2.0-6.25
User
See Note 1
0.9
—
No
PIC16C54B
3.0-5.5
User
See Note 1
0.7
PIC16CR54B
or
PIC16CR54C
Yes
PIC16C55
2.5-6.25
Factory
See Note 1
1.7
—
No
Device
Voltage
Range
PIC16C52
PIC16C54
ROM
Equivalent
MCLR
Filter
0.9
—
No
1.2
PIC16CR54A
No
PIC16C55A
3.0-5.5
User
See Note 1
0.7
—
Yes
PIC16C56
2.5-6.25
Factory
See Note 1
1.7
—
No
PIC16C56A
3.0-5.5
User
See Note 1
0.7
PIC16CR56A
Yes
PIC16C57
2.5-6.25
Factory
See Note 1
1.2
—
No
PIC16C57C
3.0-5.5
User
See Note 1
0.7
PIC16CR57C
Yes
PIC16CR57C
2.5-5.5
Factory
See Note 1
0.7
NA
Yes
PIC16C58A
2.0-6.25
User
See Note 1
0.9
PIC16CR58A
No(2)
PIC16C58B
3.0-5.5
User
See Note 1
0.7
PIC16CR58B
Yes
PIC16CR54A
2.5-6.25
Factory
See Note 1
1.2
NA
Yes
PIC16CR54B
2.5-5.5
Factory
See Note 1
0.7
NA
Yes
PIC16CR54C
3.0-5.5
Factory
See Note 1
0.7
NA
Yes
PIC16CR56A
2.5-5.5
Factory
See Note 1
0.7
NA
Yes
PIC16CR57B
2.5-6.25
Factory
See Note 1
0.9
NA
Yes
PIC16CR58A
2.5-6.25
Factory
See Note 1
0.9
NA
Yes
PIC16CR58B
2.5-5.5
Factory
See Note 1
0.7
NA
Yes
Note 1: If you change from this device to another device, please verify oscillator characteristics in your application.
Note 2: In PIC16LV58A, MCLR Filter = Yes
DS40191A-page 2
Preliminary
1998 Microchip Technology Inc.
PIC16CR54C
Table of Contents
1.0
General Description............................................................................................................................................. 5
2.0
PIC16C5X Device Varieties................................................................................................................................. 7
3.0
Architectural Overview......................................................................................................................................... 9
4.0
Memory Organization ........................................................................................................................................ 13
5.0
I/O Ports ............................................................................................................................................................ 19
6.0
Timer0 Module and TMR0 Register .................................................................................................................. 21
7.0
Special Features of the CPU ............................................................................................................................. 25
8.0
Instruction Set Summary ................................................................................................................................... 37
9.0
Development Support........................................................................................................................................ 49
10.0 Electrical Characteristics - PIC16CR54C .......................................................................................................... 53
11.0 DC and AC Characteristics - PIC16CR54C....................................................................................................... 63
12.0 Packaging Information....................................................................................................................................... 73
Appendix A: Compatibility ............................................................................................................................................. 77
Index ............................................................................................................................................................................ 79
On-Line Support............................................................................................................................................................ 81
Reader Response ......................................................................................................................................................... 82
PIC16CR54C Product Identification System................................................................................................................. 83
1998 Microchip Technology Inc.
Preliminary
DS40191A-page 3
PIC16CR54C
NOTES:
DS40191A-page 4
Preliminary
1998 Microchip Technology Inc.
PIC16CR54C
1.0
GENERAL DESCRIPTION
1.1
The PIC16C5X from Microchip Technology is a family
of low-cost, high performance, 8-bit, fully static,
EPROM/ ROM-based CMOS microcontrollers. It
employs a RISC architecture with only 33 single
word/single cycle instructions. All instructions are single cycle (200 ns) except for program branches which
take two cycles. The PIC16C5X delivers performance
an order of magnitude higher than its competitors in the
same price category. The 12-bit wide instructions are
highly symmetrical resulting in 2:1 code compression
over other 8-bit microcontrollers in its class. The easy
to use and easy to remember instruction set reduces
development time significantly.
The PIC16C5X products are equipped with special features that reduce system cost and power requirements.
The Power-On Reset (POR) and Device Reset Timer
(DRT) eliminate the need for external reset circuitry.
There are four oscillator configurations to choose from,
including the power-saving LP (Low Power) oscillator
and cost saving RC oscillator. Power saving SLEEP
mode, Watchdog Timer and code protection features
improve system cost, power and reliability.
Applications
The PIC16C5X series fits perfectly in applications ranging from high-speed automotive and appliance motor
control to low-power remote transmitters/receivers,
pointing devices and telecom processors. The EPROM
technology makes customizing application programs
(transmitter codes, motor speeds, receiver frequencies, etc.) extremely fast and convenient. The small
footprint packages, for through hole or surface mounting, make this microcontroller series perfect for applications with space limitations. Low-cost, low-power, high
performance, ease of use and I/O flexibility make the
PIC16C5X series very versatile even in areas where no
microcontroller use has been considered before (e.g.,
timer functions, replacement of “glue” logic in larger
systems, coprocessor applications).
The UV erasable CERDIP packaged versions are ideal
for code development, while the cost-effective One
Time Programmable (OTP) versions are suitable for
production in any volume. The customer can take full
advantage of Microchip’s price leadership in OTP
microcontrollers while benefiting from the OTP’s
flexibility.
The PIC16C5X products are supported by a
full-featured macro assembler, a software simulator, an
in-circuit emulator, a ‘C’ compiler, fuzzy logic support
tools, a low-cost development programmer, and a full
featured programmer. All the tools are supported on
IBM PC and compatible machines.
1998 Microchip Technology Inc.
Preliminary
DS40191A-page 5
PIC16CR54C
TABLE 1-1:
PIC16C5X FAMILY OF DEVICES
PIC16C52
Clock
Memory
Peripherals
Features
PIC16C54s
PIC16CR54s
PIC16C55s
PIC16C56s
Maximum Frequency
of Operation (MHz)
4
20
20
20
20
EPROM Program Memory
(x12 words)
384
512
—
512
1K
ROM Program Memory
(x12 words)
—
—
512
—
—
RAM Data Memory (bytes)
25
25
25
24
25
Timer Module(s)
TMR0
TMR0
TMR0
TMR0
TMR0
I/O Pins
12
12
12
20
12
Number of Instructions
33
33
33
33
33
Packages
18-pin DIP,
SOIC
18-pin DIP,
SOIC;
20-pin SSOP
18-pin DIP,
SOIC;
20-pin SSOP
28-pin DIP,
SOIC;
28-pin SSOP
18-pin DIP,
SOIC;
20-pin SSOP
All PICmicro™ Family devices have Power-on Reset, selectable Watchdog Timer (except PIC16C52), selectable code
protect and high I/O current capability.
PIC16CR56s
Clock
Memory
Peripherals
Features
PIC16C57s
PIC16CR57s
PIC16C58s
PIC16CR58s
Maximum Frequency
of Operation (MHz)
20
20
20
20
20
EPROM Program Memory
(x12 words)
—
2K
—
2K
—
ROM Program Memory
(x12 words)
1K
—
2K
—
2K
RAM Data Memory (bytes)
25
72
72
73
73
Timer Module(s)
TMR0
TMR0
TMR0
TMR0
TMR0
I/O Pins
12
20
20
12
12
Number of Instructions
33
33
33
33
33
Packages
18-pin DIP,
SOIC;
20-pin SSOP
28-pin DIP,
SOIC;
28-pin SSOP
28-pin DIP,
SOIC;
28-pin SSOP
18-pin DIP,
SOIC;
20-pin SSOP
18-pin DIP,
SOIC;
20-pin SSOP
All PICmicro™ Family devices have Power-on Reset, selectable Watchdog Timer (except PIC16C52), selectable code
protect and high I/O current capability.
DS40191A-page 6
Preliminary
1998 Microchip Technology Inc.
PIC16CR54C
2.0
PIC16C5X DEVICE VARIETIES
A variety of frequency ranges and packaging options
are available. Depending on application and
production requirements, the proper device option can
be selected using the information in this section. When
placing orders, please use the PIC16CR54C Product
Identification System at the back of this data sheet to
specify the correct part number.
For the PIC16C5X family of devices, there are four
device types, as indicated in the device number:
1.
2.
3.
4.
5.
2.1
C, as in PIC16C54. These devices have
EPROM program memory and operate over the
standard voltage range.
LC, as in PIC16LC54A. These devices have
EPROM program memory and operate over an
extended voltage range.
LV, as in PIC16LV54A. These devices have
EPROM program memory and operate over a
2.0V to 3.8V range.
CR, as in PIC16CR54A. These devices have
ROM program memory and operate over the
standard voltage range.
LCR, as in PIC16LCR54B. These devices have
ROM program memory and operate over an
extended voltage range.
UV Erasable Devices (EPROM)
The UV erasable versions, offered in CERDIP
packages, are optimal for prototype development and
pilot programs
UV erasable devices can be programmed for any of
the four oscillator configurations. Microchip's
PICSTART and PRO MATE programmers both
support programming of the PIC16CR54C. Third party
programmers also are available; refer to the Third
Party Guide for a list of sources.
2.2
2.3
Quick-Turnaround-Production (QTP)
Devices
Microchip offers a QTP Programming Service for
factory production orders. This service is made
available for users who choose not to program a
medium to high quantity of units and whose code
patterns have stabilized. The devices are identical to
the OTP devices but with all EPROM locations and
configuration bit options already programmed by the
factory. Certain code and prototype verification
procedures apply before production shipments are
available. Please contact your Microchip Technology
sales office for more details.
2.4
Serialized
Quick-Turnaround-Production
(SQTP SM) Devices
Microchip offers the unique programming service
where a few user-defined locations in each device are
programmed with different serial numbers. The serial
numbers may be random, pseudo-random or
sequential. The devices are identical to the OTP
devices but with all EPROM locations and
configuration bit options already programmed by the
factory.
Serial programming allows each device to have a
unique number which can serve as an entry code,
password or ID number.
2.5
Read Only Memory (ROM) Devices
Microchip offers masked ROM versions of several of
the highest volume parts, giving the customer a low
cost option for high volume, mature products.
One-Time-Programmable (OTP)
Devices
The availability of OTP devices is especially useful for
customers expecting frequent code changes and
updates.
The OTP devices, packaged in plastic packages,
permit the user to program them once. In addition to
the program memory, the configuration bits must be
programmed.
1998 Microchip Technology Inc.
Preliminary
DS40191A-page 7
PIC16CR54C
NOTES:
DS40191A-page 8
Preliminary
1998 Microchip Technology Inc.
PIC16CR54C
3.0
ARCHITECTURAL OVERVIEW
The high performance of the PIC16CR54C can be
attributed to a number of architectural features
commonly found in RISC microprocessors. To begin
with, the PIC16CR54C uses a Harvard architecture in
which program and data are accessed on separate
buses. This improves bandwidth over traditional von
Neumann architecture where program and data are
fetched on the same bus. Separating program and data
memory further allows instructions to be sized
differently than the 8-bit wide data word. Instruction
opcodes are 12-bits wide making it possible to have all
single word instructions. A 12-bit wide program
memory access bus fetches a 12-bit instruction in a
single cycle. A two-stage pipeline overlaps fetch and
execution of instructions. Consequently, all instructions
(33) execute in a single cycle (200ns @ 20MHz) except
for program branches.
The PIC16CR54C address 512 x 12 of program
memory. All program memory is internal.
The PIC16CR54C can directly or indirectly address its
register files and data memory. All special function
registers including the program counter are mapped in
the data memory. The PIC16CR54C has a highly
orthogonal (symmetrical) instruction set that makes it
possible to carry out any operation on any register
using any addressing mode. This symmetrical nature
and lack of ‘special optimal situations’ make
programming with the PIC16CR54C simple yet
efficient. In addition, the learning curve is reduced
significantly.
1998 Microchip Technology Inc.
The PIC16CR54C device contains an 8-bit ALU and
working register. The ALU is a general purpose
arithmetic unit. It performs arithmetic and Boolean
functions between data in the working register and any
register file.
The ALU is 8-bits wide and capable of addition,
subtraction, shift and logical operations. Unless
otherwise mentioned, arithmetic operations are two's
complement in nature. In two-operand instructions,
typically one operand is the W (working) register. The
other operand is either a file register or an immediate
constant. In single operand instructions, the operand
is either the W register or a file register.
The W register is an 8-bit working register used for
ALU operations. It is not an addressable register.
Depending on the instruction executed, the ALU may
affect the values of the Carry (C), Digit Carry (DC),
and Zero (Z) bits in the STATUS register. The C and
DC bits operate as a borrow and digit borrow out bit,
respectively, in subtraction. See the SUBWF and ADDWF
instructions for examples.
A simplified block diagram is shown in Figure 3-1, with
the corresponding device pins described in Table 3-1.
Preliminary
DS40191A-page 9
PIC16CR54C
FIGURE 3-1:
PIC16CR54C SERIES BLOCK DIAGRAM
9-11
9-11
ROM
512 X 12
T0CKI
PIN
STACK 1
STACK 2
CONFIGURATION WORD
“DISABLE”
PC
WATCHDOG
TIMER
12
“CODE
PROTECT”
2
INSTRUCTION
REGISTER
WDT TIME
OUT
9
12
OSCILLATOR/
TIMING &
CONTROL
CLKOUT
WDT/TMR0
PRESCALER
8
“SLEEP”
INSTRUCTION
DECODER
6
“OPTION”
OPTION REG.
DIRECT ADDRESS
DIRECT RAM
ADDRESS
GENERAL
PURPOSE
REGISTER
FILE
(SRAM)
25 Bytes
FROM W
5
8
LITERALS
OSC1 OSC2 MCLR
“OSC
SELECT”
STATUS
TMR0
FSR
8
W
DATA BUS
ALU
8
FROM W
4
4
“TRIS 5”
8
“TRIS 6”
TRISA
PORTA
4
RA3:RA0
DS40191A-page 10
FROM W
Preliminary
TRISB
8
PORTB
8
RB7:RB0
1998 Microchip Technology Inc.
PIC16CR54C
TABLE 3-1:
Name
PINOUT DESCRIPTION - PIC16CR54C
DIP, SOIC SSOP I/O/P Input
No.
No. Type Levels
RA0
RA1
RA2
RA3
RB0
RB1
RB2
RB3
RB4
RB5
RB6
RB7
T0CKI
17
18
1
2
6
7
8
9
10
11
12
13
3
19
20
1
2
7
8
9
10
11
12
13
14
3
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
ST
MCLR/VPP
4
4
I
ST
OSC1/CLKIN
OSC2/CLKOUT
16
15
18
17
I
O
ST(1)
—
VDD
14
15,16
P
—
5
5,6
P
—
VSS
Legend: I = input, O = output, I/O = input/output,
P = power, — = Not Used, TTL = TTL input,
ST = Schmitt Trigger input
Description
Bi-directional I/O port
Bi-directional I/O port
Clock input to Timer0. Must be tied to VSS or VDD, if not in
use, to reduce current consumption.
Master clear (reset) input/verify voltage input. This pin is an
active low reset to the device.
Oscillator crystal input/external clock source input.
Oscillator crystal output. Connects to crystal or resonator in
crystal oscillator mode. In RC mode, OSC2 pin outputs
CLKOUT which has 1/4 the frequency of OSC1, and denotes
the instruction cycle rate.
Positive supply for logic and I/O pins.
Ground reference for logic and I/O pins.
Note 1: Schmitt Trigger input only when in RC mode.
1998 Microchip Technology Inc.
Preliminary
DS40191A-page 11
PIC16CR54C
Clocking Scheme/Instruction Cycle
3.1
3.2
The clock input (OSC1/CLKIN pin) is internally divided
by four to generate four non-overlapping quadrature
clocks namely Q1, Q2, Q3 and Q4. Internally, the
program counter is incremented every Q1, and the
instruction is fetched from program memory and
latched into instruction register in Q4. It is decoded
and executed during the following Q1 through Q4. The
clocks and instruction execution flow is shown in
Figure 3-2 and Example 3-1.
Instruction Flow/Pipelining
An Instruction Cycle consists of four Q cycles (Q1, Q2,
Q3 and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle
while decode and execute takes another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (e.g., GOTO)
then two cycles are required to complete the
instruction (Example 3-1).
A fetch cycle begins with the program counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is
latched into the Instruction Register (IR) in cycle Q1.
This instruction is then decoded and executed during
the Q2, Q3, and Q4 cycles. Data memory is read
during Q2 (operand read) and written during Q4
(destination write).
FIGURE 3-2:
CLOCK/INSTRUCTION CYCLE
Q1
Q2
Q3
Q4
Q2
Q1
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
Q1
Q2
Internal
phase
clock
Q3
Q4
PC
PC
OSC2/CLKOUT
(RC mode)
EXAMPLE 3-1:
PC+1
Fetch INST (PC)
Execute INST (PC-1)
PC+2
Fetch INST (PC+1)
Execute INST (PC)
Fetch INST (PC+2)
Execute INST (PC+1)
INSTRUCTION PIPELINE FLOW
1. MOVLW 55H
2. MOVWF PORTB
3. CALL
SUB_1
4. BSF
PORTA, BIT3
Fetch 1
Execute 1
Fetch 2
Execute 2
Fetch 3
Execute 3
Fetch 4
Flush
Fetch SUB_1 Execute SUB_1
All instructions are single cycle, except for any program branches. These take two cycles since the fetch
instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed.
DS40191A-page 12
Preliminary
1998 Microchip Technology Inc.
PIC16CR54C
4.0
MEMORY ORGANIZATION
4.2.1
PIC16CR54C memory is organized into program
memory and data memory. For devices with more than
512 bytes of program memory, a paging scheme is
used. Program memory pages are accessed using
one or two STATUS register bits. For devices with a
data memory register file of more than 32 registers, a
banking scheme is used. Data memory banks are
accessed using the File Selection Register (FSR).
GENERAL PURPOSE REGISTER FILE
The register file is accessed either directly or indirectly
through the file select register FSR (Section 4.7).
FIGURE 4-2:
File Address
Program Memory Organization
4.1
The PIC16CR54C has a 9-bit Program Counter (PC)
capable of addressing a 512 x 12 program memory
space (Figure 4-1). Accessing a location above the
physically implemented address will cause a
wraparound.
The reset vector for the PIC16CR54C is at 1FFh. A
NOP at the reset vector location will cause a restart at
location 000h.
FIGURE 4-1:
PIC16CR54C REGISTER FILE
MAP
00h
INDF(1)
01h
TMR0
02h
PCL
03h
STATUS
04h
FSR
05h
PORTA
06h
PORTB
07h
PIC16CR54C PROGRAM
MEMORY MAP AND STACK
0Fh
10h
General
Purpose
Registers
PC<8:0>
9
CALL, RETLW
Stack Level 1
Stack Level 2
1Fh
Note 1:
User Memory
Space
000h
On-chip
Program
Memory
Reset Vector
4.2
Not a physical register. See Section 4.7
0FFh
100h
4.2.2
1FFh
The Special Function Registers are registers used by
the CPU and peripheral functions to control the
operation of the device (Table 4-1).
Data Memory Organization
Data memory is composed of registers, or bytes of
RAM. Therefore, data memory for a device is specified
by its register file. The register file is divided into two
functional groups: special function registers and
general purpose registers.
SPECIAL FUNCTION REGISTERS
The special registers can be classified into two sets.
The special function registers associated with the
“core” functions are described in this section. Those
related to the operation of the peripheral features are
described in the section for each peripheral feature.
The special function registers include the TMR0
register, the Program Counter (PC), the Status
Register, the I/O registers (ports), and the File Select
Register (FSR). In addition, special purpose registers
are used to control the I/O port configuration and
prescaler options.
The general purpose registers are used for data and
control information under command of the instructions.
For the PIC16CR54C, the register file is composed of
7 special function registers and 25 general purpose
registers (Figure 4-2).
1998 Microchip Technology Inc.
Preliminary
DS40191A-page 13
PIC16CR54C
TABLE 4-1:
Address
SPECIAL FUNCTION REGISTER SUMMARY
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-On
Reset
Value on
MCLR and
WDT Reset
N/A
TRIS
I/O control registers (TRISA, TRISB)
1111 1111
1111 1111
N/A
OPTION
Contains control bits to configure Timer0 and Timer0/WDT prescaler
--11 1111
--11 1111
00h
INDF
Uses contents of FSR to address data memory (not a physical register)
xxxx xxxx
uuuu uuuu
01h
TMR0
8-bit real-time clock/counter
xxxx xxxx
uuuu uuuu
02h(1)
PCL
Low order 8 bits of PC
1111 1111
1111 1111
03h
STATUS
04h
FSR
05h
PORTA
—
—
—
—
RA3
RA2
RA1
06h
PORTB
RB7
RB6
RB5
RB4
RB3
RB2
RB1
PA2
PA1
PA0
TO
PD
Z
DC
C
0001 1xxx
000q quuu
1xxx xxxx
1uuu uuuu
RA0
---- xxxx
---- uuuu
RB0
xxxx xxxx
uuuu uuuu
Indirect data memory address pointer
Legend: Shaded boxes = unimplemented or unused, – = unimplemented, read as '0' (if applicable)
x = unknown, u = unchanged, q = see the tables in Section 7.7 for possible values.
Note 1: The upper byte of the Program Counter is not directly accessible. See Section 4.5
for an explanation of how to access these bits.
DS40191A-page 14
Preliminary
1998 Microchip Technology Inc.
PIC16CR54C
4.3
STATUS Register
This register contains the arithmetic status of the ALU,
the RESET status, and the page preselect bits for
program memories larger than 512 words.
The STATUS register can be the destination for any
instruction, as with any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to
the device logic. Furthermore, the TO and PD bits are
not writable. Therefore, the result of an instruction with
the STATUS register as destination may be different
than intended.
FIGURE 4-3:
R/W-0
PA2
bit7
For example, CLRF STATUS will clear the upper three
bits and set the Z bit. This leaves the STATUS register
as 000u u1uu (where u = unchanged).
It is recommended, therefore, that only BCF, BSF and
MOVWF instructions be used to alter the STATUS
register because these instructions do not affect the Z,
DC or C bits from the STATUS register. For other
instructions, which do affect STATUS bits, see
Section 8.0, Instruction Set Summary.
STATUS REGISTER (ADDRESS:03h)
R/W-0
PA1
6
R/W-0
PA0
5
R-1
TO
4
R-1
PD
3
R/W-x
Z
2
R/W-x
DC
1
R/W-x
C
bit0
R = Readable bit
W = Writable bit
- n = Value at POR reset
bit 7:
PA2: This bit unused at this time.
Use of the PA2 bit as a general purpose read/write bit is not recommended, since this may affect upward
compatibility with future products.
bit 6-5:
Not Applicable
bit 4:
TO: Time-out bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time-out occurred
bit 3:
PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2:
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1:
DC: Digit carry/borrow bit (for ADDWF and SUBWF instructions)
ADDWF
1 = A carry from the 4th low order bit of the result occurred
0 = A carry from the 4th low order bit of the result did not occur
SUBWF
1 = A borrow from the 4th low order bit of the result did not occur
0 = A borrow from the 4th low order bit of the result occurred
bit 0:
C: Carry/borrow bit (for ADDWF, SUBWF and RRF, RLF instructions)
ADDWF
SUBWF
1 = A carry occurred
1 = A borrow did not occur
0 = A carry did not occur
0 = A borrow occurred
1998 Microchip Technology Inc.
Preliminary
RRF or RLF
Load bit with LSb or MSb, respectively
DS40191A-page 15
PIC16CR54C
4.4
OPTION Register
By executing the OPTION instruction, the contents of
the W register will be transferred to the OPTION
register. A RESET sets the OPTION<5:0> bits.
The OPTION register is a 6-bit wide, write-only
register which contains various control bits to
configure the Timer0/WDT prescaler and Timer0.
FIGURE 4-4:
OPTION REGISTER
U-0
U-0
W-1
W-1
W-1
W-1
W-1
W-1
—
—
T0CS
T0SE
PSA
PS2
PS1
PS0
6
5
4
3
2
1
bit7
bit 7-6:
Unimplemented.
bit 5:
T0CS: Timer0 clock source select bit
1 = Transition on T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)
bit 4:
T0SE: Timer0 source edge select bit
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
bit 3:
PSA: Prescaler assignment bit
1 = Prescaler assigned to the WDT (not implemented on PIC16C52)
0 = Prescaler assigned to Timer0
bit 2-0:
PS2:PS0: Prescaler rate select bits
Bit Value
Timer0 Rate
000
001
010
011
100
101
110
111
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
DS40191A-page 16
bit0
W = Writable bit
U = Unimplemented bit
- n = Value at POR reset
WDT Rate (not implemented on PIC16C52)
1:1
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
Preliminary
1998 Microchip Technology Inc.
PIC16CR54C
4.5
Program Counter
FIGURE 4-5:
As a program instruction is executed, the Program
Counter (PC) will contain the address of the next
program instruction to be executed. The PC value is
increased by one every instruction cycle, unless an
instruction changes the PC.
LOADING OF PC
BRANCH INSTRUCTIONS PIC16CR54C
GOTO Instruction
8
Instruction Word
CALL or Modify PCL Instruction
8
PC
Instructions where the PCL is the destination, or
Modify PCL instructions, include MOVWF PC, ADDWF
PC, and BSF PC, 5.
Reset to '0'
4.5.1
.
Note:
Because PC<8> is cleared in the CALL
instruction, or any Modify PCL instruction,
all subroutine calls or computed jumps are
limited to the first 256 locations of any program memory page (512 words long).
0
PCL
For a GOTO instruction, bits 8:0 of the PC are provided
by the GOTO instruction word. The PC Latch (PCL) is
mapped to PC<7:0> (Figure 4-5 and Figure 4-6).
For a CALL instruction, or any instruction where the
PCL is the destination, bits 7:0 of the PC again are
provided by the instruction word. However, PC<8>
does not come from the instruction word, but is always
cleared (Figure 4-10 and Figure 4-11)/
7
PC
7
0
PCL
Instruction Word
EFFECTS OF RESET
The Program Counter is set upon a RESET, which
means that the PC addresses the last location in the
last page i.e., the reset vector.
The STATUS register page preselect bits are cleared
upon a RESET, which means that page 0 is
pre-selected.
Therefore, upon a RESET, a GOTO instruction at the
reset vector location will automatically cause the
program to jump to page 0.
4.6
Stack
PIC16CR54C device has a 9-bit, two-level hardware
push/pop stack (Figure 4-1).
A CALL instruction will push the current value of stack
1 into stack 2 and then push the current program
counter value, incremented by one, into stack level 1. If
more than two sequential CALL’s are executed, only
the most recent two return addresses are stored.
A RETLW instruction will pop the contents of stack level
1 into the program counter and then copy stack level 2
contents into level 1. If more than two sequential
RETLW’s are executed, the stack will be filled with the
address previously stored in level 2. Note that the
W register will be loaded with the literal value specified
in the instruction. This is particularly useful for the
implementation of data look-up tables within the
program memory.
1998 Microchip Technology Inc.
Preliminary
DS40191A-page 17
PIC16CR54C
4.7
Indirect Data Addressing; INDF and
FSR Registers
EXAMPLE 4-2:
The INDF register is not a physical register.
Addressing INDF actually addresses the register
whose address is contained in the FSR register (FSR
is a pointer). This is indirect addressing.
EXAMPLE 4-1:
INDIRECT ADDRESSING
movlw
movwf
clrf
incf
btfsc
goto
NEXT
HOW TO CLEAR RAM
USING INDIRECT
ADDRESSING
0x10
FSR
INDF
FSR,F
FSR,4
NEXT
;initialize pointer
; to RAM
;clear INDF register
;inc pointer
;all done?
;NO, clear next
CONTINUE
•
•
•
•
Register file 05 contains the value 10h
Register file 06 contains the value 0Ah
Load the value 05 into the FSR register
A read of the INDF register will return the value
of 10h
• Increment the value of the FSR register by one
(FSR = 06)
• A read of the INDR register now will return the
value of 0Ah.
:
;YES, continue
The FSR is a 5-bit ( PIC16CR54C) wide register. It is
used in conjunction with the INDF register to indirectly
address the data memory area.
The FSR<4:0> bits are used to select data memory
addresses 00h to 1Fh.
PIC16CR54C: Do not use banking. FSR<6:5> are
unimplemented and read as '1's.
Reading INDF itself indirectly (FSR = 0) will produce
00h. Writing to the INDF register indirectly results in a
no-operation (although STATUS bits may be affected).
A simple program to clear RAM locations 10h-1Fh
using indirect addressing is shown in Example 4-2.
FIGURE 4-6:
DIRECT/INDIRECT ADDRESSING
Direct Addressing
(FSR)
6 5
4
bank select
location select
Indirect Addressing
(opcode)
6
0
5
4
bank
(FSR)
0
location select
00
00h
Data
Memory(1)
0Fh
10h
1Fh
Bank 0
Note 1: For register map detail see Section 4.2.
DS40191A-page 18
Preliminary
1998 Microchip Technology Inc.
PIC16CR54C
5.0
I/O PORTS
As with any other register, the I/O registers can be
written and read under program control. However, read
instructions (e.g., MOVF PORTB,W) always read the I/O
pins independent of the pin’s input/output modes. On
RESET, all I/O ports are defined as input (inputs are at
hi-impedance) since the I/O control registers (TRISA,
TRISB, TRISC) are all set.
5.1
outputs are latched and remain unchanged until the
output latch is rewritten. To use a port pin as output,
the corresponding direction control bit (in TRISA,
TRISB) must be cleared (= 0). For use as an input, the
corresponding TRIS bit must be set. Any I/O pin can
be programmed individually as input or output.
FIGURE 5-1:
Data
Bus
PORTA
D
PORTA is a 4-bit I/O register. Only the low order 4 bits
are used (RA3:RA0). Bits 7-4 are unimplemented and
read as '0's.
5.2
WR
Port
Q
Data
Latch
CK
VDD
Q
P
PORTB
PORTB is an 8-bit I/O register (PORTB<7:0>).
5.3
EQUIVALENT CIRCUIT
FOR A SINGLE I/O PIN
W
Reg
TRIS Registers
D
TRIS ‘f’
I/O
pin(1)
Q
TRIS
Latch
The output driver control registers are loaded with the
contents of the W register by executing the TRIS f
instruction. A '1' from a TRIS register bit puts the
corresponding output driver in a hi-impedance mode.
A '0' puts the contents of the output data latch on the
selected pins, enabling the output buffer.
Note:
N
CK
VSS
Q
Reset
A read of the ports reads the pins, not the
output data latches. That is, if an output
driver on a pin is enabled and driven high,
but the external system is holding it low, a
read of the port will indicate that the pin is
low.
RD Port
Note 1: I/O pins have protection diodes to VDD and VSS.
The TRIS registers are “write-only” and are set (output
drivers disabled) upon RESET.
5.4
I/O Interfacing
The equivalent circuit for an I/O port pin is shown in
Figure 5-1. All ports may be used for both input and
output operation. For input operations these ports are
non-latching. Any input must be present until read by
an input instruction (e.g., MOVF PORTB, W). The
TABLE 5-1:
Address
SUMMARY OF PORT REGISTERS
Name
Bit 7
Bit 6
Bit 5
N/A
TRIS
05h
PORTA
—
—
—
06h
PORTB
RB7
RB6
RB5
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-On
Reset
1111 1111
1111 1111
—
RA3
RA2
RA1
RA0
---- xxxx
---- uuuu
RB4
RB3
RB2
RB1
RB0
xxxx xxxx
uuuu uuuu
Bit 4
I/O control registers (TRISA, TRISB)
Value on
MCLR and
WDT Reset
Legend: Shaded boxes = unimplemented, read as ‘0’,
– = unimplemented, read as '0', x = unknown, u = unchanged
1998 Microchip Technology Inc.
Preliminary
DS40191A-page 19
PIC16CR54C
5.5
I/O Programming Considerations
5.5.1
BI-DIRECTIONAL I/O PORTS
EXAMPLE 5-1:
;Initial PORT Settings
; PORTB<7:4> Inputs
; PORTB<3:0> Outputs
;PORTB<7:6> have external pull-ups and are
;not connected to other circuitry
;
;
PORT latch PORT pins
;
---------- ---------BCF
PORTB, 7
;01pp pppp
11pp pppp
BCF
PORTB, 6
;10pp pppp
11pp pppp
MOVLW 03Fh
;
TRIS PORTB
;10pp pppp
10pp pppp
;
;Note that the user may have expected the pin
;values to be 00pp pppp. The 2nd BCF caused
;RB7 to be latched as the pin value (High).
Some instructions operate internally as read followed
by write operations. The BCF and BSF instructions, for
example, read the entire port into the CPU, execute
the bit operation and re-write the result. Caution must
be used when these instructions are applied to a port
where one or more pins are used as input/outputs. For
example, a BSF operation on bit5 of PORTB will cause
all eight bits of PORTB to be read into the CPU, bit5 to
be set and the PORTB value to be written to the output
latches. If another bit of PORTB is used as a
bi-directional I/O pin (say bit0) and it is defined as an
input at this time, the input signal present on the pin
itself would be read into the CPU and rewritten to the
data latch of this particular pin, overwriting the
previous content. As long as the pin stays in the input
mode, no problem occurs. However, if bit0 is switched
into output mode later on, the content of the data latch
may now be unknown.
5.5.2
SUCCESSIVE OPERATIONS ON I/O
PORTS
The actual write to an I/O port happens at the end of
an instruction cycle, whereas for reading, the data
must be valid at the beginning of the instruction cycle
(Figure 5-2). Therefore, care must be exercised if a
write followed by a read operation is carried out on the
same I/O port. The sequence of instructions should
allow the pin voltage to stabilize (load dependent)
before the next instruction, which causes that file to be
read into the CPU, is executed. Otherwise, the
previous state of that pin may be read into the CPU
rather than the new state. When in doubt, it is better to
separate these instructions with a NOP or another
instruction not accessing this I/O port.
Example 5-1 shows the effect of two sequential
read-modify-write instructions (e.g., BCF, BSF, etc.) on
an I/O port.
A pin actively outputting a high or a low should not be
driven from external devices at the same time in order
to change the level on this pin (“wired-or”, “wired-and”).
The resulting high output currents may damage the
chip.
FIGURE 5-2:
READ-MODIFY-WRITE
INSTRUCTIONS ON AN
I/O PORT
SUCCESSIVE I/O OPERATION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC
Instruction
fetched
MOVWF PORTB
PC + 1
MOVF PORTB,W
PC + 2
PC + 3
NOP
NOP
This example shows a write
to PORTB followed by a read
from PORTB.
RB7:RB0
Port pin
written here
Instruction
executed
DS40191A-page 20
MOVWF PORTB
(Write to
PORTB)
Port pin
sampled here
MOVF PORTB,W
(Read
PORTB)
Preliminary
NOP
1998 Microchip Technology Inc.
PIC16CR54C
6.0
TIMER0 MODULE AND
TMR0 REGISTER
Counter mode is selected by setting the T0CS bit
(OPTION<5>). In this mode, Timer0 will increment
either on every rising or falling edge of pin T0CKI. The
incrementing edge is determined by the source edge
select bit T0SE (OPTION<4>). Clearing the T0SE bit
selects the rising edge. Restrictions on the external
clock input are discussed in detail in Section 6.1.
The Timer0 module has the following features:
• 8-bit timer/counter register, TMR0
- Readable and writable
• 8-bit software programmable prescaler
• Internal or external clock select
- Edge select for external clock
The prescaler may be used by either the Timer0
module or the Watchdog Timer, but not both. The
prescaler assignment is controlled in software by the
control bit PSA (OPTION<3>). Clearing the PSA bit
will assign the prescaler to Timer0. The prescaler is
not readable or writable. When the prescaler is
assigned to the Timer0 module, prescale values of 1:2,
1:4,..., 1:256 are selectable. Section 6.2 details the
operation of the prescaler.
Figure 6-1 is a simplified block diagram of the Timer0
module, while Figure 6-2 shows the electrical structure
of the Timer0 input.
Timer mode is selected by clearing the T0CS bit
(OPTION<5>). In timer mode, the Timer0 module will
increment every instruction cycle (without prescaler). If
TMR0 register is written, the increment is inhibited for
the following two cycles (Figure 6-3 and Figure 6-4).
The user can work around this by writing an adjusted
value to the TMR0 register.
FIGURE 6-1:
A summary of registers associated with the Timer0
module is found in Table 6-1.
TIMER0 BLOCK DIAGRAM
Data bus
FOSC/4
0
PSout
1
1
T0CKI
pin
Programmable
Prescaler(2)
T0SE(1)
0
8
Sync with
Internal
Clocks
TMR0 reg
PSout
(2 cycle delay) Sync
3
T0CS(1)
PSA(1)
PS2, PS1, PS0(1)
Note 1: Bits T0CS, T0SE, PSA, PS2, PS1 and PS0 are located in the OPTION register.
2: The prescaler is shared with the Watchdog Timer (Figure 6-6).
FIGURE 6-2:
ELECTRICAL STRUCTURE OF T0CKI PIN
RIN
T0CKI
pin
(1)
VSS
N
(1)
Schmitt Trigger
Input Buffer
VSS
Note 1: ESD protection circuits
1998 Microchip Technology Inc.
Preliminary
DS40191A-page 21
PIC16CR54C
FIGURE 6-3:
TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC
(Program
Counter)
PC-1
Instruction
Fetch
T0
Timer0
PC
PC+1
MOVWF TMR0
MOVF TMR0,W
T0+1
Instruction
Executed
FIGURE 6-4:
PC+3
MOVF TMR0,W
T0+2
NT0
NT0
Write TMR0
executed
Read TMR0
reads NT0
Read TMR0
reads NT0
PC+4
PC+5
MOVF TMR0,W
NT0
NT0+1
Read TMR0
reads NT0 + 1
Read TMR0
reads NT0
PC+6
MOVF TMR0,W
NT0+2
Read TMR0
reads NT0 + 2
TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC
(Program
Counter)
PC-1
Instruction
Fetch
PC
PC+1
MOVWF TMR0
MOVF TMR0,W
Instruction
Execute
PC+3
MOVF TMR0,W
PC+4
PC+5
MOVF TMR0,W
Read TMR0
reads NT0
Read TMR0
reads NT0
PC+6
MOVF TMR0,W
NT0+1
NT0
Write TMR0
executed
TABLE 6-1:
PC+2
MOVF TMR0,W
T0+1
T0
Timer0
Address
PC+2
MOVF TMR0,W
Read TMR0
reads NT0
Read TMR0
reads NT0
T0
Read TMR0
reads NT0 + 1
REGISTERS ASSOCIATED WITH TIMER0
Name
01h
TMR0
N/A
OPTION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PS2
PS1
PS0
Timer0 - 8-bit real-time clock/counter
—
—
T0CS
T0SE
PSA
Value on
Power-On
Reset
Value on
MCLR and
WDT Reset
xxxx xxxx uuuu uuuu
--11 1111 --11 1111
Legend: Shaded cells: Unimplemented bits,
- = unimplemented, x = unknown, u = unchanged,
DS40191A-page 22
Preliminary
1998 Microchip Technology Inc.
PIC16CR54C
6.1
Using Timer0 with an External Clock
When a prescaler is used, the external clock input is
divided by the asynchronous ripple counter-type
prescaler so that the prescaler output is symmetrical.
For the external clock to meet the sampling
requirement, the ripple counter must be taken into
account. Therefore, it is necessary for T0CKI to have a
period of at least 4TOSC (and a small RC delay of
40 ns) divided by the prescaler value. The only
requirement on T0CKI high and low time is that they
do not violate the minimum pulse width requirement of
10 ns. Refer to parameters 40, 41 and 42 in the
electrical specification of the desired device.
When an external clock input is used for Timer0, it
must meet certain requirements. The external clock
requirement is due to internal phase clock (TOSC)
synchronization. Also, there is a delay in the actual
incrementing of Timer0 after synchronization.
6.1.1
EXTERNAL CLOCK SYNCHRONIZATION
When no prescaler is used, the external clock input is
the same as the prescaler output. The synchronization
of T0CKI with the internal phase clocks is
accomplished by sampling the prescaler output on the
Q2 and Q4 cycles of the internal phase clocks
(Figure 6-5). Therefore, it is necessary for T0CKI to be
high for at least 2TOSC (and a small RC delay of 20 ns)
and low for at least 2TOSC (and a small RC delay of
20 ns). Refer to the electrical specification of the
desired device.
FIGURE 6-5:
6.1.2
TIMER0 INCREMENT DELAY
Since the prescaler output is synchronized with the
internal clocks, there is a small delay from the time the
external clock edge occurs to the time the Timer0
module is actually incremented. Figure 6-5 shows the
delay from the external clock edge to the timer
incrementing.
TIMER0 TIMING WITH EXTERNAL CLOCK
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
External Clock Input or
Prescaler Output (2)
Q1 Q2 Q3 Q4
Small pulse
misses sampling
(1)
External Clock/Prescaler
Output After Sampling
(3)
Increment Timer0 (Q4)
Timer0
T0
T0 + 1
T0 + 2
Note 1: Delay from clock input change to Timer0 increment is 3Tosc to 7Tosc. (Duration of Q = Tosc).
Therefore, the error in measuring the interval between two edges on Timer0 input = ± 4Tosc max.
2: External clock if no prescaler selected, Prescaler output otherwise.
3: The arrows indicate the points in time where sampling occurs.
1998 Microchip Technology Inc.
Preliminary
DS40191A-page 23
PIC16CR54C
6.2
Prescaler
following instruction sequence (Example 6-1) must be
executed when changing the prescaler assignment from
Timer0 to the WDT.
An 8-bit counter is available as a prescaler for the
Timer0 module, or as a postscaler for the Watchdog
Timer (WDT) (WDT postscaler not implemented on
PIC16C52), respectively (Section 6.1.2). For simplicity,
this counter is being referred to as “prescaler”
throughout this data sheet. Note that the prescaler
may be used by either the Timer0 module or the WDT,
but not both. Thus, a prescaler assignment for the
Timer0 module means that there is no prescaler for
the WDT, and vice-versa.
EXAMPLE 6-1:
1.CLRWDT
;Clear WDT
2.CLRF
TMR0
;Clear TMR0 & Prescaler
3.MOVLW '00xx1111’b ;These 3 lines (5, 6, 7)
4.OPTION
; are required only if
; desired
5.CLRWDT
;PS<2:0> are 000 or 001
6.MOVLW '00xx1xxx’b ;Set Postscaler to
7.OPTION
; desired WDT rate
The PSA and PS2:PS0 bits (OPTION<3:0>) determine
prescaler assignment and prescale ratio.
To change prescaler from the WDT to the Timer0
module, use the sequence shown in Example 6-2. This
sequence must be used even if the WDT is disabled. A
CLRWDT instruction should be executed before switching
the prescaler.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g., CLRF 1, MOVWF 1,
BSF 1,x, etc.) will clear the prescaler. When assigned
to WDT, a CLRWDT instruction will clear the prescaler
along with the WDT. The prescaler is neither readable
nor writable. On a RESET, the prescaler contains all
'0's.
6.2.1
CHANGING PRESCALER
(TIMER0→WDT)
EXAMPLE 6-2:
CHANGING PRESCALER
(WDT→TIMER0)
CLRWDT
SWITCHING PRESCALER ASSIGNMENT
The prescaler assignment is fully under software control
(i.e., it can be changed “on the fly” during program
execution). To avoid an unintended device RESET, the
MOVLW
'xxxx0xxx'
;Clear WDT and
;prescaler
;Select TMR0, new
;prescale value and
;clock source
OPTION
FIGURE 6-6:
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
TCY ( = Fosc/4)
Data Bus
0
T0CKI
pin
1
8
M
U
X
1
M
U
X
0
Sync
2
Cycles
TMR0 reg
T0SE
T0CS
0
Watchdog
Timer
1
M
U
X
PSA
8-bit Prescaler
8
8 - to - 1MUX
PS2:PS0
PSA
WDT Enable bit
1
0
MUX
PSA
WDT
Time-Out
Note: T0CS, T0SE, PSA, PS2:PS0 are bits in the OPTION register.
DS40191A-page 24
Preliminary
1998 Microchip Technology Inc.
PIC16CR54C
7.0
SPECIAL FEATURES OF THE
CPU
The SLEEP mode is designed to offer a very low
current power-down mode. The user can wake up from
SLEEP through external reset or through a Watchdog
Timer time-out. Several oscillator options are also
made available to allow the part to fit the application.
The RC oscillator option saves system cost while the
LP crystal option saves power. A set of configuration
bits are used to select various options.
What sets a microcontroller apart from other
processors are special circuits that deal with the
needs of real-time applications. The PIC16C5X family
of microcontrollers has a host of such features
intended to maximize system reliability, minimize cost
through elimination of external components, provide
power saving operating modes and offer code
protection. These features are:
•
•
•
•
•
•
•
7.1
Configuration bits can be programmed to select
various device configurations. Two bits are for the
selection of the oscillator type and one bit is the
Watchdog Timer enable bit. Nine bits are code
protection bits (Figure 7-1 and Figure 7-2) for the
PIC16CR54C devices.
Oscillator selection
Reset
Power-On Reset (POR)
Device Reset Timer (DRT)
Watchdog Timer (WDT)
SLEEP
Code protection
ROM devices have the oscillator configuration
programmed at the factory and these parts are tested
accordingly (see "Product Identification System"
diagrams in the back of this data sheet).
The PIC16CR54C Family has a Watchdog Timer
which can be shut off only through configuration bit
WDTE. It runs off of its own RC oscillator for added
reliability. There is an 18 ms delay provided by the
Device Reset Timer (DRT), intended to keep the chip
in reset until the crystal oscillator is stable. With this
timer on-chip, most applications need no external
reset circuitry.
FIGURE 7-1:
Configuration Bits
CONFIGURATION WORD FOR PIC16CR54C
CP
CP
CP
CP
CP
CP
CP
CP
CP
bit11
10
9
8
7
6
5
4
3
WDTE FOSC1 FOSC0
2
1
bit0
Register:
Address(1):
CONFIG
0FFFh
bit 11-3: CP: Code protection bits
1 = Code protection off
0 = Code protection on
bit 2:
WDTE: Watchdog timer enable bit
1 = WDT enabled
0 = WDT disabled
bit 1-0:
FOSC1:FOSC0: Oscillator selection bits
11 = RC oscillator
10 = HS oscillator
01 = XT oscillator
00 = LP oscillator
Note 1: Refer to the PIC16C5X Programming Specification (Literature number DS30190) to determine how to
access the configuration word.
1998 Microchip Technology Inc.
Preliminary
DS40191A-page 25
PIC16CR54C
7.2
Oscillator Configurations
7.2.1
OSCILLATOR TYPES
FIGURE 7-3:
PIC16CR54Cs can be operated in four different
oscillator modes. The user can program two
configuration bits (FOSC1:FOSC0) to select one of
these four modes:
•
•
•
•
LP:
XT:
HS:
RC:
7.2.2
TABLE 7-1:
CRYSTAL OSCILLATOR / CERAMIC
RESONATORS
In XT, LP or HS modes, a crystal or ceramic resonator
is connected to the OSC1/CLKIN and OSC2/CLKOUT
pins to establish oscillation (Figure 7-2). The
PIC16CR54C oscillator design requires the use of a
parallel cut crystal. Use of a series cut crystal may
give a frequency out of the crystal manufacturers
specifications. When in XT, LP or HS modes, the
device can have an external clock source drive the
OSC1/CLKIN pin (Figure 7-3).
CRYSTAL OPERATION
(OR CERAMIC RESONATOR)
(HS, XT OR LP OSC
CONFIGURATION)
C1(1)
OSC1
PIC16CR54C
SLEEP
XTAL
RS(2)
RF(3)
OSC2
To internal
logic
C2(1)
Note 1: See Capacitor Selection tables for
recommended values of C1 and C2.
2: A series resistor (RS) may be required for
AT strip cut crystals.
3: RF varies with the crystal chosen (approx.
value = 10 MΩ).
Osc
Type
Preliminary
OSC2
CAPACITOR SELECTION
FOR CERAMIC RESONATORS
- PIC16CR54C
Resonator
Freq
Cap. Range
C1
Cap. Range
C2
XT
455 kHz
68-100 pF
68-100 pF
2.0 MHz
15-33 pF
15-33 pF
4.0 MHz
10-22 pF
10-22 pF
HS
8.0 MHz
10-22 pF
10-22 pF
16.0 MHz
10 pF
10 pF
These values are for design guidance only. Since
each resonator has its own characteristics, the user
should consult the resonator manufacturer for
appropriate values of external components.
TABLE 7-2:
Osc
Type
CAPACITOR SELECTION
FOR CRYSTAL OSCILLATOR
- PIC16CR54C
Resonator
Freq
Cap.Range
C1
Cap. Range
C2
32 kHz(1)
15 pF
15 pF
200-300 pF
15-30 pF
100 kHz
100-200 pF
15-30 pF
200 kHz
15-100 pF
15-30 pF
455 kHz
15-30 pF
15-30 pF
1 MHz
15 pF
15 pF
2 MHz
15 pF
15 pF
4 MHz
HS
4 MHz
15 pF
15 pF
8 MHz
15 pF
15 pF
20 MHz
15 pF
15 pF
Note 1: For VDD > 4.5V, C1 = C2 ≈ 30 pF is
recommended.
These values are for design guidance only. Rs may
be required in HS mode as well as XT mode to avoid
overdriving crystals with low drive level specification.
Since each crystal has its own characteristics, the
user should consult the crystal manufacturer for
appropriate values of external components.
LP
XT
Note:
DS40191A-page 26
OSC1
PIC16CR54C
Clock from
ext. system
Open
Low Power Crystal
Crystal/Resonator
High Speed Crystal/Resonator
Resistor/Capacitor
FIGURE 7-2:
EXTERNAL CLOCK INPUT
OPERATION (HS, XT OR LP
OSC CONFIGURATION)
If you change from this device to
another device, please verify oscillator
characteristics in your application.
1998 Microchip Technology Inc.
PIC16CR54C
7.2.3
EXTERNAL CRYSTAL OSCILLATOR
CIRCUIT
Either a prepackaged oscillator or a simple oscillator
circuit with TTL gates can be used as an external
crystal oscillator circuit. Prepackaged oscillators
provide a wide operating range and better stability. A
well-designed crystal oscillator will provide good
performance with TTL gates. Two types of crystal
oscillator circuits can be used: one with parallel
resonance, or one with series resonance.
Figure 7-4 shows implementation of a parallel
resonant oscillator circuit. The circuit is designed to
use the fundamental frequency of the crystal. The
74AS04 inverter performs the 180-degree phase shift
that a parallel oscillator requires. The 4.7 kΩ resistor
provides the negative feedback for stability. The 10 kΩ
potentiometers bias the 74AS04 in the linear region.
This circuit could be used for external oscillator
designs.
FIGURE 7-4:
EXTERNAL PARALLEL
RESONANT CRYSTAL
OSCILLATOR CIRCUIT
(USING XT, HS OR LP
OSCILLATOR MODE)
+5V
To Other
Devices
10k
74AS04
4.7k
PIC16CR54C
CLKIN
74AS04
OSC2
10k
100k
XTAL
10k
20 pF
Note:
20 pF
If you change from this device to
another device, please verify oscillator
characteristics in your application.
Figure 7-5 shows a series resonant oscillator circuit.
This circuit is also designed to use the fundamental
frequency of the crystal. The inverter performs a
180-degree phase shift in a series resonant oscillator
circuit. The 330 Ω resistors provide the negative
feedback to bias the inverters in their linear region.
1998 Microchip Technology Inc.
FIGURE 7-5:
EXTERNAL SERIES
RESONANT CRYSTAL
OSCILLATOR CIRCUIT
(USING XT, HS OR LP
OSCILLATOR MODE)
330
To Other
Devices
330
74AS04
74AS04
74AS04
PIC16CR54C
CLKIN
0.1 µF
XTAL
OSC2
100k
Note:
7.2.4
If you change from this device to
another device, please verify oscillator
characteristics in your application.
RC OSCILLATOR
For timing insensitive applications, the RC device option
offers additional cost savings. The RC oscillator
frequency is a function of the supply voltage, the
resistor (Rext) and capacitor (Cext) values, and the
operating temperature. In addition to this, the oscillator
frequency will vary from unit to unit due to normal
process parameter variation. Furthermore, the
difference in lead frame capacitance between package
types will also affect the oscillation frequency, especially
for low Cext values. The user also needs to take into
account variation due to tolerance of external R and C
components used.
Figure 7-6 shows how the R/C combination is
connected to the PIC16CR54C. For Rext values below
2.2 kΩ, the oscillator operation may become unstable,
or stop completely. For very high Rext values
(e.g., 1 MΩ) the oscillator becomes sensitive to noise,
humidity and leakage. Thus, we recommend keeping
Rext between 3 kΩ and 100 kΩ.
Although the oscillator will operate with no external
capacitor (Cext = 0 pF), we recommend using values
above 20 pF for noise and stability reasons. With no or
small external capacitance, the oscillation frequency
can vary dramatically due to changes in external
capacitances, such as PCB trace capacitance or
package lead frame capacitance.
Preliminary
DS40191A-page 27
PIC16CR54C
The Electrical Specifications sections show RC
frequency variation from part to part due to normal
process variation. The variation is larger for larger R
(since leakage current variation will affect RC
frequency more for large R) and for smaller C (since
variation of input capacitance will affect RC frequency
more).
Also, see the Electrical Specifications sections for
variation of oscillator frequency due to VDD for given
Rext/Cext values as well as frequency variation due to
operating temperature for given R, C, and VDD values.
The oscillator frequency, divided by 4, is available on
the OSC2/CLKOUT pin, and can be used for test
purposes or to synchronize other logic.
FIGURE 7-6:
RC OSCILLATOR MODE
VDD
Rext
OSC1
Internal
clock
N
Cext
PIC16CR54C
VSS
Reset
PIC16CR54C devices may be reset in one of the
following ways:
•
•
•
•
•
Power-On Reset (POR)
MCLR reset (normal operation)
MCLR wake-up reset (from SLEEP)
WDT reset (normal operation)
WDT wake-up reset (from SLEEP)
Table 7-3 shows these reset conditions for the PCL
and STATUS registers.
Some registers are not affected in any reset condition.
Their status is unknown on POR and unchanged in
any other reset. Most other registers are reset to a
“reset state” on Power-On Reset (POR), MCLR or
WDT reset. A MCLR or WDT wake-up from SLEEP
also results in a device reset, and not a continuation of
operation before SLEEP.
The TO and PD bits (STATUS <4:3>) are set or
cleared depending on the different reset conditions
(Section 7.7). These bits may be used to determine
the nature of the reset.
Table 7-4 lists a full description of reset states of all
registers. Figure 7-7 shows a simplified block diagram
of the on-chip reset circuit.
Fosc/4
OSC2/CLKOUT
Note:
7.3
If you change from this device to
another device, please verify oscillator
characteristics in your application.
DS40191A-page 28
Preliminary
1998 Microchip Technology Inc.
PIC16CR54C
TABLE 7-3:
RESET CONDITIONS FOR SPECIAL REGISTERS
PCL
Addr: 02h
Condition
STATUS
Addr: 03h
Power-On Reset
1111 1111
0001 1xxx
MCLR reset (normal operation)
1111 1111
000u uuuu(1)
MCLR wake-up (from SLEEP)
1111 1111
0001 0uuu
WDT reset (normal operation)
1111 1111
0000 1uuu(2)
WDT wake-up (from SLEEP)
1111 1111
Legend: u = unchanged, x = unknown, - = unimplemented read as '0'.
Note 1: TO and PD bits retain their last value until one of the other reset conditions occur.
2: The CLRWDT instruction will set the TO and PD bits.
TABLE 7-4:
0000 0uuu
RESET CONDITIONS FOR ALL REGISTERS
Register
Address
Power-On Reset
MCLR or WDT Reset
W
N/A
xxxx xxxx
uuuu uuuu
TRIS
N/A
1111 1111
1111 1111
OPTION
N/A
--11 1111
--11 1111
INDF
00h
xxxx xxxx
uuuu uuuu
TMR0
01h
xxxx xxxx
uuuu uuuu
PCL(1)
02h
1111 1111
1111 1111
STATUS(1)
03h
0001 1xxx
000q quuu
FSR
04h
111x xxxx
111u uuuu
PORTA
05h
---- xxxx
---- uuuu
PORTB
06h
xxxx xxxx
uuuu uuuu
General Purpose Register Files
07-1Fh
xxxx xxxx
Legend: u = unchanged, x = unknown, - = unimplemented, read as '0',
q = see tables in Section 7.7 for possible values.
Note 1: See Table 7-3 for reset value for specific conditions.
uuuu uuuu
FIGURE 7-7:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
Power-Up
Detect
POR (Power-On Reset)
VDD
MCLR/VPP pin
WDT Time-out
RESET
WDT
On-Chip
RC OSC
8-bit Asynch
Ripple Counter
(Start-Up Timer)
S
Q
R
Q
CHIP RESET
DS40191A-page 29
Preliminary
1998 Microchip Technology Inc.
PIC16CR54C
7.4
Power-On Reset (POR)
FIGURE 7-8:
The PIC16CR54C incorporates on-chip Power-On
Reset (POR) circuitry which provides an internal chip
reset for most power-up situations. To use this feature,
the user merely ties the MCLR/VPP pin to VDD. A
simplified block diagram of the on-chip Power-On
Reset circuit is shown in Figure 7-7.
The Power-On Reset circuit and the Device Reset
Timer (Section 7.5) circuit are closely related. On
power-up, the reset latch is set and the DRT is reset.
The DRT timer begins counting once it detects MCLR
to be high. After the time-out period, which is typically
18 ms, it will reset the reset latch and thus end the
on-chip reset signal.
A power-up example where MCLR is not tied to VDD is
shown in Figure 7-9. VDD is allowed to rise and
stabilize before bringing MCLR high. The chip will
actually come out of reset TDRT msec after MCLR
goes high.
In Figure 7-10, the on-chip Power-On Reset feature is
being used (MCLR and VDD are tied together). The
VDD is stable before the start-up timer times out and
there is no problem in getting a proper reset. However,
Figure 7-11 depicts a problem situation where VDD
rises too slowly. The time between when the DRT
senses a high on the MCLR/VPP pin, and when the
MCLR/VPP pin (and VDD) actually reach their full value,
is too long. In this situation, when the start-up timer
times out, VDD has not reached the VDD (min) value
and the chip is, therefore, not guaranteed to function
correctly. For such situations, we recommend that
external RC circuits be used to achieve longer POR
delay times (Figure 7-8).
VDD
EXTERNAL POWER-ON
RESET CIRCUIT (FOR SLOW
VDD POWER-UP)
VDD
D
R
R1
MCLR
C
PIC16CR54C
• External Power-On Reset circuit is required
only if VDD power-up is too slow. The diode D
helps discharge the capacitor quickly when
VDD powers down.
• R < 40 kΩ is recommended to make sure that
voltage drop across R does not violate the
device electrical specification.
• R1 = 100Ω to 1 kΩ will limit any current
flowing into MCLR from external capacitor C
in the event of MCLR pin breakdown due to
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS).
Note:
When the device starts normal operation
(exits the reset condition), device operating parameters (voltage, frequency, temperature, etc.) must be meet to ensure
operation. If these conditions are not met,
the device must be held in reset until the
operating conditions are met.
For more information on PIC16CR54C POR, see
Power-Up Considerations - AN522 in the Embedded
Control Handbook.
The POR circuit does not produce an internal reset
when VDD declines.
DS40191A-page 30
Preliminary
1998 Microchip Technology Inc.
PIC16CR54C
FIGURE 7-9:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD)
VDD
MCLR
INTERNAL POR
TDRT
DRT TIME-OUT
INTERNAL RESET
FIGURE 7-10: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): FAST VDD RISE TIME
VDD
MCLR
INTERNAL POR
TDRT
DRT TIME-OUT
INTERNAL RESET
FIGURE 7-11: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): SLOW VDD RISE TIME
V1
VDD
MCLR
INTERNAL POR
TDRT
DRT TIME-OUT
INTERNAL RESET
When VDD rises slowly, the TDRT time-out expires long before VDD has reached its final value. In
this example, the chip will reset properly if, and only if, V1 ≥ VDD min
DS40191A-page 31
Preliminary
1998 Microchip Technology Inc.
PIC16CR54C
7.5
Device Reset Timer (DRT)
7.6
The Device Reset Timer (DRT) provides a fixed 18 ms
nominal time-out on reset. The DRT operates on an
internal RC oscillator. The processor is kept in RESET
as long as the DRT is active. The DRT delay allows
VDD to rise above VDD min., and for the oscillator to
stabilize.
Oscillator circuits based on crystals or ceramic
resonators require a certain time after power-up to
establish a stable oscillation. The on-chip DRT keeps
the device in a RESET condition for approximately 18
ms after the voltage on the MCLR/VPP pin has
reached a logic high (VIH) level. Thus, external RC
networks connected to the MCLR input are not
required in most cases, allowing for savings in
cost-sensitive and/or space restricted applications.
The Device Reset time delay will vary from chip to chip
due to VDD, temperature, and process variation. See
AC parameters for details.
The DRT will also be triggered upon a Watchdog Timer
time-out. This is particularly important for applications
using the WDT to wake the PIC16CR54C from SLEEP
mode automatically.
Watchdog Timer (WDT)
The Watchdog Timer (WDT) is a free running on-chip
RC oscillator which does not require any external
components. This RC oscillator is separate from the RC
oscillator of the OSC1/CLKIN pin. That means that the
WDT will run even if the clock on the OSC1/CLKIN and
OSC2/CLKOUT pins have been stopped, for example,
by execution of a SLEEP instruction. During normal
operation or SLEEP, a WDT reset or wake-up reset
generates a device RESET.
The TO bit (STATUS<4>) will be cleared upon a
Watchdog Timer reset.
The WDT can be permanently disabled by programming
the configuration bit WDTE as a '0' (Section 7.1). Refer
to the PIC16C5X Programming Specifications
(Literature Number DS30190) to determine how to
access the configuration word.
7.6.1
WDT PERIOD
The WDT has a nominal time-out period of 18 ms, (with
no prescaler). If a longer time-out period is desired, a
prescaler with a division ratio of up to 1:128 can be
assigned to the WDT (under software control) by writing
to the OPTION register. Thus, time-out a period of a
nominal 2.3 seconds can be realized. These periods
vary with temperature, VDD and part-to-part process
variations (see DC specs).
Under worst case conditions (VDD = Min., Temperature
= Max., max. WDT prescaler), it may take several
seconds before a WDT time-out occurs.
7.6.2
WDT PROGRAMMING CONSIDERATIONS
The CLRWDT instruction clears the WDT and the
postscaler, if assigned to the WDT, and prevents it from
timing out and generating a device RESET.
The SLEEP instruction resets the WDT and the
postscaler, if assigned to the WDT. This gives the
maximum SLEEP time before a WDT wake-up reset.
DS40191A-page 32
Preliminary
1998 Microchip Technology Inc.
PIC16CR54C
FIGURE 7-12: WATCHDOG TIMER BLOCK DIAGRAM
From TMR0 Clock Source
0
M
1
Watchdog
Postscaler
Postscaler
U
X
Timer
8 - to - 1 MUX
PS2:PS0
PSA
WDT Enable
EPROM Bit
To TMR0
1
0
MUX
PSA
Note: T0CS, T0SE, PSA, PS2:PS0
are bits in the OPTION register.
WDT
Time-out
TABLE 7-5:
Address
N/A
SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER
Name
OPTION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-On
Reset
—
—
T0CS
T0SE
PSA
PS2
PS1
PS0
--11 1111
Value on
MCLR and
WDT Reset
--11 1111
Legend: Shaded boxes = Not used by Watchdog Timer,
– = unimplemented, read as '0', u = unchanged
DS40191A-page 33
Preliminary
1998 Microchip Technology Inc.
PIC16CR54C
7.7
Time-Out Sequence and Power Down
Status Bits (TO/PD)
The TO and PD bits in the STATUS register can be
tested to determine if a RESET condition has been
caused by a power-up condition, a MCLR or Watchdog
Timer (WDT) reset, or a MCLR or WDT wake-up reset.
TABLE 7-6:
TO/PD STATUS AFTER
RESET
7.8
Reset on Brown-Out
A brown-out is a condition where device power (VDD)
dips below its minimum value, but not to zero, and then
recovers. The device should be reset in the event of a
brown-out.
To reset PIC16CR54C devices when a brown-out
occurs, external brown-out protection circuits may be
built, as shown in Figure 7-13 and Figure 7-14.
FIGURE 7-13: BROWN-OUT PROTECTION
CIRCUIT 1
TO
PD
RESET was caused by
1
1
Power-up (POR)
u
u
1
0
0
1
0
0
MCLR reset (normal operation)(1)
MCLR wake-up reset (from SLEEP)
WDT reset (normal operation)
WDT wake-up reset (from SLEEP)
VDD
VDD
33k
Legend: u = unchanged
Note 1: The TO and PD bits maintain their status (u) until
a reset occurs. A low-pulse on the MCLR input
does not change the TO and PD status bits.
10k
Q1
MCLR
40k
PIC16CR54C
These STATUS bits are only affected by events listed
in Table 7-7.
TABLE 7-7:
EVENTS AFFECTING TO/PD
STATUS BITS
Event
Power-up
WDT Time-out
SLEEP instruction
CLRWDT instruction
TO
PD
1
1
0
u
1
0
1
1
This circuit will activate reset when VDD goes below Vz +
0.7V (where Vz = Zener voltage).
Remarks
No effect on PD
FIGURE 7-14: BROWN-OUT PROTECTION
CIRCUIT 2
VDD
Legend: u = unchanged
A WDT time-out will occur regardless of the status of the TO
bit. A SLEEP instruction will be executed, regardless of the
status of the PD bit. Table 7-6 reflects the status of TO and
PD after the corresponding event.
VDD
R1
Q1
MCLR
R2
Table 7-3 lists the reset conditions for the special
function registers, while Table 7-4 lists the reset
conditions for all the registers.
40k
PIC16CR54C
This brown-out circuit is less expensive, although
less accurate. Transistor Q1 turns off when VDD
is below a certain level such that:
VDD •
DS40191A-page 34
Preliminary
R1
R1 + R2
= 0.7V
1998 Microchip Technology Inc.
PIC16CR54C
7.9
Power-Down Mode (SLEEP)
7.10
A device may be powered down (SLEEP) and later
powered up (Wake-up from SLEEP).
7.9.1
SLEEP
Program Verification/Code Protection
If the code protection bit(s) have not been
programmed, the on-chip program memory can be
read out for verification purposes.
Note:
The Power-Down mode is entered by executing a
SLEEP instruction.
Microchip does not recommend code protecting windowed devices.
If enabled, the Watchdog Timer will be cleared but
keeps running, the TO bit (STATUS<4>) is set, the PD
bit (STATUS<3>) is cleared and the oscillator driver is
turned off. The I/O ports maintain the status they had
before the SLEEP instruction was executed (driving
high, driving low, or hi-impedance).
It should be noted that a RESET generated by a WDT
time-out does not drive the MCLR/VPP pin low.
For lowest current consumption while powered down,
the T0CKI input should be at VDD or VSS and the
MCLR/VPP pin must be at a logic high level
(VIH MCLR).
7.9.2
WAKE-UP FROM SLEEP
The device can wake up from SLEEP through one of
the following events:
1.
2.
An external reset input on MCLR/VPP pin.
A Watchdog Timer time-out reset (if WDT was
enabled).
Both of these events cause a device reset. The TO and
PD bits can be used to determine the cause of device
reset.
The TO bit is cleared if a WDT time-out
occurred (and caused wake-up). The PD bit, which is
set on power-up, is cleared when SLEEP is invoked.
The WDT is cleared when the device wakes from
sleep, regardless of the wake-up source.
1998 Microchip Technology Inc.
Preliminary
DS40191A-page 35
PIC16CR54C
NOTES:
DS40191A-page 36
Preliminary
1998 Microchip Technology Inc.
PIC16CR54C
8.0
INSTRUCTION SET SUMMARY
Each PIC16CR54C instruction is a 12-bit word divided into
an OPCODE, which specifies the instruction type, and one
or more operands which further specify the operation of
the instruction. The PIC16CR54C instruction set summary
in Table 8-2 groups the instructions into byte-oriented,
bit-oriented, and literal and control operations. Table 8-1
shows the opcode field descriptions.
For byte-oriented instructions, 'f' represents a file register
designator and 'd' represents a destination designator. The
file register designator is used to specify which one of the
32 file registers is to be used by the instruction.
The destination designator specifies where the result
of the operation is to be placed. If 'd' is '0', the result is
placed in the W register. If 'd' is '1', the result is placed
in the file register specified in the instruction.
For bit-oriented instructions, 'b' represents a bit field
designator which selects the number of the bit affected
by the operation, while 'f' represents the number of the
file in which the bit is located.
All instructions are executed within one single
instruction cycle, unless a conditional test is true or the
program counter is changed as a result of an
instruction. In this case, the execution takes two
instruction cycles. One instruction cycle consists of
four oscillator periods. Thus, for an oscillator frequency
of 4 MHz, the normal instruction execution time is 1 µs.
If a conditional test is true or the program counter is
changed as a result of an instruction, the instruction
execution time is 2 µs.
Figure 8-1 shows the three general formats that the
instructions can have. All examples in the figure use the
following format to represent a hexadecimal number:
0xhhh
where 'h' signifies a hexadecimal digit.
FIGURE 8-1:
Byte-oriented file register operations
11
OPCODE FIELD
DESCRIPTIONS
Field
11
OPCODE
b
k
Bit address within an 8-bit file register
Literal field, constant data or label
x
Don't care location (= 0 or 1)
The assembler will generate code with x = 0. It is
the recommended form of use for compatibility
with all Microchip software tools.
d
Destination select;
d = 0 (store result in W)
d = 1 (store result in file register 'f')
Default is d = 1
dest
[ ]
( )
→
<>
∈
italics
4
0
f (FILE #)
d = 0 for destination W
d = 1 for destination f
f = 5-bit file register address
Description
Register file address (0x00 to 0x7F)
Working register (accumulator)
TOS
PC
WDT
TO
PD
5
d
Bit-oriented file register operations
f
W
label
6
OPCODE
For literal and control operations, 'k' represents an
8 or 9-bit constant or literal value.
TABLE 8-1:
GENERAL FORMAT FOR
INSTRUCTIONS
8 7
5 4
b (BIT #)
f (FILE #)
0
b = 3-bit bit address
f = 5-bit file register address
Literal and control operations (except GOTO)
11
8
7
OPCODE
0
k (literal)
k = 8-bit immediate value
Literal and control operations - GOTO instruction
11
9
8
OPCODE
Label name
Top of Stack
0
k (literal)
k = 9-bit immediate value
Program Counter
Watchdog Timer Counter
Time-Out bit
Power-Down bit
Destination, either the W register or the specified
register file location
Options
Contents
Assigned to
Register bit field
In the set of
User defined term (font is courier)
1998 Microchip Technology Inc.
Preliminary
DS40191A-page 37
PIC16CR54C
TABLE 8-2:
INSTRUCTION SET SUMMARY
Mnemonic,
Operands
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
DECFSZ
INCF
INCFSZ
IORWF
MOVF
MOVWF
NOP
RLF
RRF
SUBWF
SWAPF
XORWF
f,d
f,d
f
–
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
–
f, d
f, d
f, d
f, d
f, d
12-Bit Opcode
Description
Cycles MSb
Add W and f
AND W with f
Clear f
Clear W
Complement f
Decrement f
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
Move W to f
No Operation
Rotate left f through Carry
Rotate right f through Carry
Subtract W from f
Swap f
Exclusive OR W with f
LSb
Status
Affected Notes
1
1
1
1
1
1
1(2)
1
1(2)
1
1
1
1
1
1
1
1
1
0001
0001
0000
0000
0010
0000
0010
0010
0011
0001
0010
0000
0000
0011
0011
0000
0011
0001
11df
01df
011f
0100
01df
11df
11df
10df
11df
00df
00df
001f
0000
01df
00df
10df
10df
10df
ffff
ffff
ffff
0000
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
0000
ffff
ffff
ffff
ffff
ffff
C,DC,Z
Z
Z
Z
Z
Z
None
Z
None
Z
Z
None
None
C
C
C,DC,Z
None
Z
1,2,4
2,4
4
1
1
1 (2)
1 (2)
0100
0101
0110
0111
bbbf
bbbf
bbbf
bbbf
ffff
ffff
ffff
ffff
None
None
None
None
2,4
2,4
1
2
1
2
1
1
1
2
1
1
1
1110
1001
0000
101k
1101
1100
0000
1000
0000
0000
1111
kkkk
kkkk
0000
kkkk
kkkk
kkkk
0000
kkkk
0000
0000
kkkk
kkkk
kkkk
0100
kkkk
kkkk
kkkk
0010
kkkk
0011
0fff
kkkk
Z
None
TO, PD
None
Z
None
None
None
TO, PD
None
Z
2,4
2,4
2,4
2,4
2,4
2,4
1,4
2,4
2,4
1,2,4
2,4
2,4
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
f, b
f, b
f, b
f, b
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
LITERAL AND CONTROL OPERATIONS
ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLW
OPTION
RETLW
SLEEP
TRIS
XORLW
k
k
k
k
k
k
k
k
–
f
k
AND literal with W
Call subroutine
Clear Watchdog Timer
Unconditional branch
Inclusive OR Literal with W
Move Literal to W
Load OPTION register
Return, place Literal in W
Go into standby mode
Load TRIS register
Exclusive OR Literal to W
1
3
Note 1: The 9th bit of the program counter will be forced to a '0' by any instruction that writes to the PC except for GOTO.
(See individual device data sheets, Memory Section/Indirect Data Addressing, INDF and FSR Registers)
2: When an I/O register is modified as a function of itself (e.g. MOVF PORTB, 1), the value used will be that value
present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven
low by an external device, the data will be written back with a '0'.
3: The instruction TRIS f, where f = 5 or 6 causes the contents of the W register to be written to the tristate
latches of PORTA or B respectively. A '1' forces the pin to a hi-impedance state and disables the output buffers.
4: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared
(if assigned to TMR0).
DS40191A-page 38
Preliminary
1998 Microchip Technology Inc.
PIC16CR54C
ADDWF
Add W and f
Syntax:
[ label ] ADDWF
ANDWF
AND W with f
Syntax:
Operands:
[ label ] ANDWF
0 ≤ f ≤ 31
d ∈ [0,1]
Operands:
0 ≤ f ≤ 31
d ∈ [0,1]
Operation:
(W) + (f) → (dest)
Operation:
(W) .AND. (f) → (dest)
f,d
Status Affected: C, DC, Z
Encoding:
0001
f,d
Status Affected: Z
11df
Encoding:
ffff
0001
01df
ffff
Description:
Add the contents of the W register and
register 'f'. If 'd' is 0 the result is stored
in the W register. If 'd' is '1' the result is
stored back in register 'f'.
Description:
The contents of the W register are
AND’ed with register 'f'. If 'd' is 0 the
result is stored in the W register. If 'd' is
'1' the result is stored back in register 'f'.
Words:
1
Words:
1
Cycles:
1
Example:
ADDWF
FSR, 0
Cycles:
1
Example:
ANDWF
Before Instruction
W
=
FSR =
W =
FSR =
0x17
0xC2
After Instruction
After Instruction
W
=
FSR =
W
=
FSR =
0xD9
0xC2
ANDLW
And literal with W
Syntax:
[ label ] ANDLW
Operands:
0 ≤ k ≤ 255
Operation:
(W).AND. (k) → (W)
k
Status Affected: Z
Encoding:
Description:
kkkk
1
Cycles:
1
Example:
ANDLW
BCF
Bit Clear f
Syntax:
[ label ] BCF
Operands:
0 ≤ f ≤ 31
0≤b≤7
Operation:
0 → (f<b>)
=
Encoding:
=
0100
bbbf
ffff
Bit 'b' in register 'f' is cleared.
Words:
1
Cycles:
1
Example:
BCF
0x5F
FLAG_REG,
7
Before Instruction
FLAG_REG = 0xC7
0xA3
After Instruction
After Instruction
W
f,b
Description:
Before Instruction
W
0x17
0x02
Status Affected: None
kkkk
The contents of the W register are
AND’ed with the eight-bit literal 'k'. The
result is placed in the W register.
Words:
1
Before Instruction
0x17
0xC2
1110
FSR,
FLAG_REG = 0x47
0x03
1998 Microchip Technology Inc.
Preliminary
DS40191A-page 39
PIC16CR54C
BSF
Bit Set f
Syntax:
[ label ] BSF
BTFSS
Operands:
Operation:
Bit Test f, Skip if Set
Syntax:
[ label ] BTFSS f,b
0 ≤ f ≤ 31
0≤b≤7
Operands:
0 ≤ f ≤ 31
0≤b<7
1 → (f<b>)
Operation:
skip if (f<b>) = 1
f,b
Status Affected: None
Encoding:
Status Affected: None
0101
bbbf
Bit 'b' in register 'f' is set.
Words:
1
Cycles:
1
Example:
BSF
Encoding:
ffff
Description:
FLAG_REG,
FLAG_REG = 0x8A
1
Cycles:
1(2)
Example:
HERE
FALSE
TRUE
BTFSC
Bit Test f, Skip if Clear
Syntax:
[ label ] BTFSC f,b
Operands:
0 ≤ f ≤ 31
0≤b≤7
Before Instruction
Operation:
skip if (f<b>) = 0
After Instruction
•
•
PC
Status Affected: None
Encoding:
Description:
0110
bbbf
ffff
Words:
Before Instruction
FLAG_REG = 0x0A
bbbf
If bit 'b' in register 'f' is '1' then the next
instruction is skipped.
If bit 'b' is '1', then the next instruction
fetched during the current instruction
execution, is discarded and an NOP is
executed instead, making this a 2 cycle
instruction.
7
After Instruction
0111
Description:
ffff
If bit 'b' in register 'f' is 0 then the next
instruction is skipped.
If FLAG<1>
PC
if FLAG<1>
PC
BTFSS
GOTO
•
FLAG,1
PROCESS_CODE
=
address (HERE)
=
=
=
=
0,
address (FALSE);
1,
address (TRUE)
If bit 'b' is 0 then the next instruction
fetched during the current instruction
execution is discarded, and an NOP is
executed instead, making this a 2 cycle
instruction.
Words:
1
Cycles:
1(2)
Example:
HERE
FALSE
TRUE
BTFSC
GOTO
FLAG,1
PROCESS_CODE
•
•
•
Before Instruction
PC
=
address (HERE)
=
=
=
=
0,
address (TRUE);
1,
address(FALSE)
After Instruction
if FLAG<1>
PC
if FLAG<1>
PC
DS40191A-page 40
Preliminary
1998 Microchip Technology Inc.
PIC16CR54C
CALL
Subroutine Call
CLRW
Clear W
Syntax:
[ label ] CALL k
Syntax:
[ label ] CLRW
Operands:
0 ≤ k ≤ 255
Operands:
None
Operation:
(PC) + 1→ Top of Stack;
k → PC<7:0>;
(STATUS<6:5>) → PC<10:9>;
0 → PC<8>
Operation:
00h → (W);
1→Z
Status Affected: Z
Encoding:
Status Affected: None
Encoding:
Description:
1001
kkkk
kkkk
Subroutine call. First, return address
(PC+1) is pushed onto the stack. The
eight bit immediate address is loaded
into PC bits <7:0>. The upper bits
PC<10:9> are loaded from STATUS<6:5>, PC<8> is cleared. CALL is
a two cycle instruction.
1
Cycles:
2
Example:
HERE
CALL
1
Cycles:
1
Example:
CLRW
Before Instruction
W
CLRWDT
address (HERE)
address (THERE)
address (HERE + 1)
CLRF
Clear f
Syntax:
[ label ] CLRF
Operands:
0 ≤ f ≤ 31
Operation:
00h → (f);
1→Z
Words:
0x5A
0000
f
1
CLRF
[ label ] CLRWDT
Operands:
None
Operation:
00h → WDT;
0 → WDT prescaler (if assigned);
1 → TO;
1 → PD
011f
0x5A
=
=
0x00
1
1998 Microchip Technology Inc.
0100
Words:
1
ffff
Cycles:
1
Example:
CLRWDT
Before Instruction
WDT counter =
?
After Instruction
WDT counter
WDT prescale
TO
PD
After Instruction
FLAG_REG
Z
0000
The CLRWDT instruction resets the
WDT. It also resets the prescaler, if the
prescaler is assigned to the WDT and
not Timer0. Status bits TO and PD are
set.
FLAG_REG
=
0000
Description:
Before Instruction
FLAG_REG
Clear Watchdog Timer
Encoding:
1
Example:
0x00
1
Status Affected: TO, PD
The contents of register 'f' are cleared
and the Z bit is set.
Cycles:
=
=
Syntax:
Status Affected: Z
Encoding:
=
THERE
After Instruction
Description:
0000
Words:
W
Z
Before Instruction
PC =
TOS =
0100
The W register is cleared. Zero bit (Z)
is set.
After Instruction
Words:
PC =
0000
Description:
Preliminary
=
=
=
=
0x00
0
1
1
DS40191A-page 41
PIC16CR54C
COMF
Complement f
Syntax:
[ label ] COMF
DECFSZ
Decrement f, Skip if 0
Syntax:
Operands:
[ label ] DECFSZ f,d
0 ≤ f ≤ 31
d ∈ [0,1]
Operands:
0 ≤ f ≤ 31
d ∈ [0,1]
Operation:
(f) → (dest)
Operation:
(f) – 1 → d;
f,d
Status Affected: Z
Encoding:
0010
01df
Encoding:
ffff
Description:
The contents of register 'f' are complemented. If 'd' is 0 the result is stored in
the W register. If 'd' is 1 the result is
stored back in register 'f'.
Words:
1
Cycles:
1
Example:
COMF
=
REG1,0
Words:
0x13
After Instruction
REG1
W
=
=
Description:
Decrement f
Syntax:
[ label ] DECF f,d
0 ≤ f ≤ 31
d ∈ [0,1]
Operation:
1(2)
Example:
HERE
(f) – 1 → (dest)
Words:
PC
CNT
if CNT
PC
if CNT
PC
11df
1
1
Example:
DECF
Before Instruction
CNT
Z
=
=
=
=
=
address (HERE)
CNT,
=
=
=
≠
=
CNT - 1;
0,
address (CONTINUE);
0,
address (HERE+1)
GOTO
Unconditional Branch
Syntax:
[ label ]
Operands:
0 ≤ k ≤ 511
Operation:
k → PC<8:0>;
STATUS<6:5> → PC<10:9>
1
GOTO k
Status Affected: None
0x01
0
After Instruction
CNT
Z
CNT, 1
LOOP
ffff
Decrement register 'f'. If 'd' is 0 the
result is stored in the W register. If 'd' is
1 the result is stored back in register 'f'.
Cycles:
DECFSZ
GOTO
CONTINUE •
•
•
Before Instruction
Status Affected: Z
Description:
ffff
After Instruction
Operands:
0000
11df
1
Cycles:
0x13
0xEC
DECF
Encoding:
0010
The contents of register 'f' are decremented. If 'd' is 0 the result is placed in
the W register. If 'd' is 1 the result is
placed back in register 'f'.
If the result is 0, the next instruction,
which is already fetched, is discarded
and an NOP is executed instead making it a two cycle instruction.
Before Instruction
REG1
skip if result = 0
Status Affected: None
Encoding:
101k
kkkk
kkkk
Description:
GOTO is an unconditional branch. The
9-bit immediate value is loaded into PC
bits <8:0>. The upper bits of PC are
loaded from STATUS<6:5>. GOTO is a
two cycle instruction.
Words:
1
0x00
1
Cycles:
2
Example:
GOTO THERE
After Instruction
PC =
DS40191A-page 42
Preliminary
address (THERE)
1998 Microchip Technology Inc.
PIC16CR54C
INCF
Increment f
IORLW
Inclusive OR literal with W
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 ≤ f ≤ 31
d ∈ [0,1]
Operands:
0 ≤ k ≤ 255
Operation:
(f) + 1 → (dest)
(W) .OR. (k) → (W)
Operation:
INCF f,d
Status Affected: Z
Status Affected: Z
Encoding:
Description:
Words:
Encoding:
0010
10df
ffff
The contents of register 'f' are incremented. If 'd' is 0 the result is placed in
the W register. If 'd' is 1 the result is
placed back in register 'f'.
1
Cycles:
1
Example:
INCF
CNT,
=
=
1101
kkkk
kkkk
Description:
The contents of the W register are
OR’ed with the eight bit literal 'k'. The
result is placed in the W register.
Words:
1
Cycles:
1
Example:
IORLW
0x35
Before Instruction
1
W
Before Instruction
CNT
Z
IORLW k
=
0x9A
After Instruction
0xFF
0
W
Z
=
=
0xBF
0
After Instruction
CNT
Z
=
=
0x00
1
INCFSZ
Increment f, Skip if 0
Syntax:
[ label ]
Operands:
0 ≤ f ≤ 31
d ∈ [0,1]
Operation:
Description:
[ label ]
Operands:
0 ≤ f ≤ 31
d ∈ [0,1]
Operation:
(W).OR. (f) → (dest)
IORWF
f,d
Status Affected: Z
Encoding:
Status Affected: None
0011
Inclusive OR W with f
Syntax:
INCFSZ f,d
(f) + 1 → (dest), skip if result = 0
Encoding:
IORWF
11df
00df
ffff
Inclusive OR the W register with register 'f'. If 'd' is 0 the result is placed in
the W register. If 'd' is 1 the result is
placed back in register 'f'.
Words:
1
ffff
The contents of register 'f' are incremented. If 'd' is 0 the result is placed in
the W register. If 'd' is 1 the result is
placed back in register 'f'.
If the result is 0, then the next instruction, which is already fetched, is discarded and an NOP is executed
instead making it a two cycle instruction.
0001
Description:
Cycles:
1
Example:
IORWF
RESULT, 0
Before Instruction
RESULT =
W
=
0x13
0x91
After Instruction
Words:
1
Cycles:
1(2)
Example:
HERE
INCFSZ
GOTO
CONTINUE •
•
•
CNT,
LOOP
1
RESULT =
W
=
Z
=
0x13
0x93
0
Before Instruction
PC
=
address (HERE)
After Instruction
CNT
if CNT
PC
if CNT
PC
=
=
=
≠
=
CNT + 1;
0,
address (CONTINUE);
0,
address (HERE +1)
1998 Microchip Technology Inc.
Preliminary
DS40191A-page 43
PIC16CR54C
MOVF
Move f
Syntax:
[ label ]
Operands:
0 ≤ f ≤ 31
d ∈ [0,1]
Operation:
(f) → (dest)
MOVF f,d
0010
Description:
Move W to f
Syntax:
[ label ]
Operands:
0 ≤ f ≤ 31
Operation:
(W) → (f)
Encoding:
00df
ffff
The contents of register 'f' is moved to
destination 'd'. If 'd' is 0, destination is
the W register. If 'd' is 1, the destination
is file register 'f'. 'd' is 1 is useful to test
a file register since status flag Z is
affected.
1
Cycles:
1
Example:
MOVF
0000
001f
Move data from the W register to register 'f'.
Words:
1
Cycles:
1
Example:
MOVWF
TEMP_REG
W
FSR,
TEMP_REG
=
=
0xFF
0x4F
=
=
0x4F
0x4F
After Instruction
0
TEMP_REG
W
value in FSR register
NOP
No Operation
MOVLW
Move Literal to W
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
None
Operands:
0 ≤ k ≤ 255
Operation:
No operation
Operation:
k → (W)
Status Affected: None
MOVLW k
Status Affected: None
Words:
0000
0000
No operation.
The eight bit literal 'k' is loaded into the
W register. The don’t cares will assemble as 0s.
Words:
1
Cycles:
1
1
Example:
NOP
1100
Description:
Encoding:
NOP
Description:
Encoding:
ffff
Description:
After Instruction
=
f
Before Instruction
Words:
W
MOVWF
Status Affected: None
Status Affected: Z
Encoding:
MOVWF
Cycles:
1
Example:
MOVLW
kkkk
kkkk
0000
0x5A
After Instruction
W
=
DS40191A-page 44
0x5A
Preliminary
1998 Microchip Technology Inc.
PIC16CR54C
OPTION
Load OPTION Register
RLF
Rotate Left f through Carry
Syntax:
[ label ]
Syntax:
[ label ] RLF
Operands:
None
Operands:
Operation:
(W) → OPTION
0 ≤ f ≤ 31
d ∈ [0,1]
Operation:
See description below
OPTION
Status Affected: None
Encoding:
0000
Description:
0000
0010
Status Affected: C
The content of the W register is loaded
into the OPTION register.
Words:
1
Cycles:
1
Example
Encoding:
Description:
OPTION
0011
=
After Instruction
RETLW
Words:
0x07
Syntax:
[ label ]
Operands:
0 ≤ k ≤ 255
Operation:
k → (W);
TOS → PC
1
Example:
RLF
Encoding:
1000
RETLW k
kkkk
REG1
C
REG1
W
C
1
Cycles:
2
Example:
CALL TABLE ;W contains
;table offset
;value.
•
;W now has table
•
;value.
•
ADDWF PC
;W = offset
RETLW k1
;Begin table
RETLW k2
;
•
•
•
RETLW kn
; End of table
W
=
=
=
=
=
1110 0110
1100 1100
1
RRF
Rotate Right f through Carry
Syntax:
[ label ]
Operands:
0 ≤ f ≤ 31
d ∈ [0,1]
Operation:
See description below
RRF f,d
Status Affected: C
Encoding:
Description:
0011
Words:
00df
ffff
The contents of register 'f' are rotated
one bit to the right through the Carry
Flag. If 'd' is 0 the result is placed in the
W register. If 'd' is 1 the result is placed
back in register 'f'.
C
register 'f'
1
Cycles:
1
Example:
RRF
REG1,0
Before Instruction
0x07
REG1
C
After Instruction
W
1110 0110
0
kkkk
Words:
Before Instruction
=
=
After Instruction
The W register is loaded with the eight
bit literal 'k'. The program counter is
loaded from the top of the stack (the
return address). This is a two cycle
instruction.
TABLE
REG1,0
Before Instruction
Status Affected: None
Description:
1
Cycles:
Return with Literal in W
ffff
register 'f'
C
0x07
OPTION =
01df
The contents of register 'f' are rotated
one bit to the left through the Carry
Flag. If 'd' is 0 the result is placed in the
W register. If 'd' is 1 the result is stored
back in register 'f'.
Before Instruction
W
f,d
value of k8
=
=
1110 0110
0
After Instruction
REG1
W
C
1998 Microchip Technology Inc.
Preliminary
=
=
=
1110 0110
0111 0011
0
DS40191A-page 45
PIC16CR54C
SLEEP
Enter SLEEP Mode
SUBWF
Subtract W from f
Syntax:
[label]
Syntax:
[label]
Operands:
None
Operands:
Operation:
00h → WDT;
0 → WDT prescaler;
1 → TO;
0 → PD
0 ≤ f ≤ 31
d ∈ [0,1]
Operation:
(f) – (W) → (dest)
SLEEP
Status Affected: C, DC, Z
Encoding:
Status Affected: TO, PD
Encoding:
Description:
0000
0000
The processor is put into SLEEP mode
with the oscillator stopped. See section on SLEEP for more details.
1
Cycles:
1
Example:
SLEEP
0000
10df
ffff
Description:
Subtract (2’s complement method) the
W register from register 'f'. If 'd' is 0 the
result is stored in the W register. If 'd' is
1 the result is stored back in register 'f'.
Words:
1
0011
Time-out status bit (TO) is set. The
power down status bit (PD) is cleared.
The WDT and its prescaler are
cleared.
Words:
SUBWF f,d
Cycles:
1
Example 1:
SUBWF
REG1, 1
Before Instruction
REG1
W
C
=
=
=
3
2
?
After Instruction
REG1
W
C
=
=
=
1
2
1
; result is positive
Example 2:
Before Instruction
REG1
W
C
=
=
=
2
2
?
After Instruction
REG1
W
C
=
=
=
0
2
1
; result is zero
Example 3:
Before Instruction
REG1
W
C
=
=
=
1
2
?
After Instruction
REG1
W
C
DS40191A-page 46
Preliminary
=
=
=
FF
2
0
; result is negative
1998 Microchip Technology Inc.
PIC16CR54C
SWAPF
Swap Nibbles in f
XORLW
Exclusive OR literal with W
Syntax:
[ label ] SWAPF f,d
Syntax:
[label]
Operands:
0 ≤ f ≤ 31
d ∈ [0,1]
Operands:
0 ≤ k ≤ 255
(f<3:0>) → (dest<7:4>);
(f<7:4>) → (dest<3:0>)
Operation:
Operation:
(W) .XOR. k → (W)
Status Affected: Z
Encoding:
Status Affected: None
XORLW k
1111
kkkk
kkkk
Description:
The upper and lower nibbles of register
'f' are exchanged. If 'd' is 0 the result is
placed in W register. If 'd' is 1 the result
is placed in register 'f'.
The contents of the W register are
XOR’ed with the eight bit literal 'k'. The
result is placed in the W register.
Words:
1
Cycles:
1
Words:
1
Example:
XORLW
Cycles:
1
Example
SWAPF
Encoding:
Description:
0011
10df
ffff
REG1,
W
0
=
=
0xB5
After Instruction
Before Instruction
REG1
0xAF
Before Instruction
W
0xA5
=
0x1A
After Instruction
REG1
W
=
=
0xA5
0X5A
XORWF
Exclusive OR W with f
Syntax:
[ label ] XORWF
Operands:
0 ≤ f ≤ 31
d ∈ [0,1]
Operation:
(W) .XOR. (f) → (dest)
TRIS
Load TRIS Register
Syntax:
[ label ] TRIS
Operands:
f = 5, 6 or 7
Status Affected: Z
Operation:
(W) → TRIS register f
Encoding:
f
Status Affected: None
Encoding:
0000
0000
0001
Exclusive OR the contents of the W
register with register 'f'. If 'd' is 0 the
result is stored in the W register. If 'd' is
1 the result is stored back in register 'f'.
TRIS register 'f' (f = 5, 6, or 7) is loaded
with the contents of the W register
Words:
1
Words:
1
Cycles:
1
Cycles:
1
Example
XORWF
TRIS
PORTA
Before Instruction
W
=
=
REG,1
Before Instruction
0XA5
REG
W
After Instruction
TRISA
ffff
Description:
0fff
Description:
Example
10df
f,d
0xAF
0xB5
After Instruction
0XA5
REG
W
1998 Microchip Technology Inc.
=
=
Preliminary
=
=
0x1A
0xB5
DS40191A-page 47
PIC16CR54C
NOTES:
DS40191A-page 48
Preliminary
1998 Microchip Technology Inc.
PIC16CR54C
9.0
DEVELOPMENT SUPPORT
9.1
Development Tools
9.3
The PICmicrο microcontrollers are supported with a
full range of hardware and software development
tools:
• PICMASTER/PICMASTER CE Real-Time
In-Circuit Emulator
• ICEPIC Low-Cost PIC16C5X and PIC16CXXX
In-Circuit Emulator
• PRO MATE II Universal Programmer
• PICSTART Plus Entry-Level Prototype
Programmer
• PICDEM-1 Low-Cost Demonstration Board
• PICDEM-2 Low-Cost Demonstration Board
• PICDEM-3 Low-Cost Demonstration Board
• MPASM Assembler
• MPLAB SIM Software Simulator
• MPLAB-C17 (C Compiler)
• Fuzzy Logic Development System
(fuzzyTECH−MP)
9.2
ICEPIC is a low-cost in-circuit emulator solution for the
Microchip PIC12CXXX, PIC16C5X and PIC16CXXX
families of 8-bit OTP microcontrollers.
ICEPIC is designed to operate on PC-compatible
machines ranging from 286-AT through Pentium
based machines under Windows 3.x environment.
ICEPIC features real time, non-intrusive emulation.
9.4
PRO MATE II: Universal Programmer
The PRO MATE II Universal Programmer is a
full-featured programmer capable of operating in
stand-alone mode as well as PC-hosted mode. PRO
MATE II is CE compliant.
The PRO MATE II has programmable VDD and VPP
supplies which allows it to verify programmed memory
at VDD min and VDD max for maximum reliability. It has
an LCD display for displaying error messages, keys to
enter commands and a modular detachable socket
assembly to support various package types. In standalone mode the PRO MATE II can read, verify or
program PIC12CXXX, PIC14C000, PIC16C5X,
PIC16CXXX and PIC17CXX devices. It can also set
configuration and code-protect bits in this mode.
PICMASTER: High Performance
Universal In-Circuit Emulator with
MPLAB IDE
The PICMASTER Universal In-Circuit Emulator is
intended to provide the product development engineer
with a complete microcontroller design tool set for all
microcontrollers in the PIC14C000, PIC12CXXX,
PIC16C5X, PIC16CXXX and PIC17CXX families.
PICMASTER is supplied with the MPLAB Integrated
Development Environment (IDE), which allows editing,
“make” and download, and source debugging from a
single environment.
Interchangeable target probes allow the system to be
easily reconfigured for emulation of different
processors. The universal architecture of the
PICMASTER allows expansion to support all new
Microchip microcontrollers.
The PICMASTER Emulator System has been
designed as a real-time emulation system with
advanced features that are generally found on more
expensive development tools. The PC compatible 386
(and higher) machine platform and Microsoft Windows
3.x environment were chosen to best make these
features available to you, the end user.
A CE compliant version of PICMASTER is available for
European Union (EU) countries.
1998 Microchip Technology Inc.
ICEPIC: Low-Cost PICmicro™
In-Circuit Emulator
9.5
PICSTART Plus Entry Level
Development System
The PICSTART programmer is an easy-to-use,
low-cost prototype programmer. It connects to the PC
via one of the COM (RS-232) ports. MPLAB Integrated
Development Environment software makes using the
programmer simple and efficient. PICSTART Plus is
not recommended for production programming.
PICSTART
Plus
supports
all
PIC12CXXX,
PIC14C000, PIC16C5X, PIC16CXXX and PIC17CXX
devices with up to 40 pins. Larger pin count devices
such as the PIC16C923, PIC16C924 and PIC17C756
may be supported with an adapter socket. PICSTART
Plus is CE compliant.
9.6
PICDEM-1 Low-Cost PICmicro
Demonstration Board
The PICDEM-1 is a simple board which demonstrates
the
capabilities
of
several
of
Microchip’s
microcontrollers. The microcontrollers supported are:
PIC16C5X (PIC16C54 to PIC16C58A), PIC16C61,
PIC16C62X, PIC16C71, PIC16C8X, PIC17C42,
PIC17C43 and PIC17C44. All necessary hardware
and software is included to run basic demo programs.
The users can program the sample microcontrollers
provided with the PICDEM-1 board, on a
PRO MATE II or PICSTART-Plus programmer, and
easily test firmware. The user can also connect the
PICDEM-1 board to the PICMASTER emulator and
download the firmware to the emulator for testing.
Preliminary
DS40191A-page 49
PIC16CR54C
Additional prototype area is available for the user to
build some additional hardware and connect it to the
microcontroller socket(s). Some of the features include
an RS-232 interface, a potentiometer for simulated
analog input, push-button switches and eight LEDs
connected to PORTB.
9.7
PICDEM-2 Low-Cost PIC16CXX
Demonstration Board
The PICDEM-2 is a simple demonstration board that
supports the PIC16C62, PIC16C64, PIC16C65,
PIC16C73 and PIC16C74 microcontrollers. All the
necessary hardware and software is included to
run the basic demonstration programs. The user
can program the sample microcontrollers provided
with the PICDEM-2 board, on a PRO MATE II
programmer or PICSTART-Plus, and easily test
firmware. The PICMASTER emulator may also be
used with the PICDEM-2 board to test firmware.
Additional prototype area has been provided to the
user for adding additional hardware and connecting it
to the microcontroller socket(s). Some of the features
include a RS-232 interface, push-button switches, a
potentiometer for simulated analog input, a Serial
EEPROM to demonstrate usage of the I2C bus and
separate headers for connection to an LCD module
and a keypad.
9.8
PICDEM-3 Low-Cost PIC16CXXX
Demonstration Board
The PICDEM-3 is a simple demonstration board that
supports the PIC16C923 and PIC16C924 in the PLCC
package. It will also support future 44-pin PLCC
microcontrollers with a LCD Module. All the
necessary hardware and software is included to
run the basic demonstration programs. The user
can program the sample microcontrollers provided
with the PICDEM-3 board, on a PRO MATE II
programmer or PICSTART Plus with an adapter
socket, and easily test firmware. The PICMASTER
emulator may also be used with the PICDEM-3 board
to test firmware. Additional prototype area has been
provided to the user for adding hardware and
connecting it to the microcontroller socket(s). Some
of the features include an RS-232 interface,
push-button switches, a potentiometer for simulated
analog input, a thermistor and separate headers for
connection to an external LCD module and a keypad.
Also provided on the PICDEM-3 board is an LCD
panel, with 4 commons and 12 segments, that is
capable of displaying time, temperature and day of the
week. The PICDEM-3 provides an additional RS-232
interface and Windows 3.1 software for showing the
demultiplexed LCD signals on a PC. A simple serial
interface allows the user to construct a hardware
demultiplexer for the LCD signals.
DS40191A-page 50
9.9
MPLAB™ Integrated Development
Environment Software
The MPLAB IDE Software brings an ease of software
development previously unseen in the 8-bit
microcontroller market. MPLAB is a windows based
application which contains:
• A full featured editor
• Three operating modes
- editor
- emulator
- simulator
• A project manager
• Customizable tool bar and key mapping
• A status bar with project information
• Extensive on-line help
MPLAB allows you to:
• Edit your source files (either assembly or ‘C’)
• One touch assemble (or compile) and download
to PICmicro tools (automatically updates all
project information)
• Debug using:
- source files
- absolute listing file
• Transfer data dynamically via DDE (soon to be
replaced by OLE)
• Run up to four emulators on the same PC
The ability to use MPLAB with Microchip’s simulator
allows a consistent platform and the ability to easily
switch from the low cost simulator to the full featured
emulator with minimal retraining due to development
tools.
9.10
Assembler (MPASM)
The MPASM Universal Macro Assembler is a
PC-hosted symbolic assembler. It supports all
microcontroller series including the PIC12C5XX,
PIC14000, PIC16C5X, PIC16CXXX, and PIC17CXX
families.
MPASM offers full featured Macro capabilities,
conditional assembly, and several source and listing
formats. It generates various object code formats to
support Microchip's development tools as well as third
party programmers.
MPASM allows full symbolic debugging from
PICMASTER, Microchip’s Universal Emulator System.
MPASM has the following features to assist in
developing software for specific use applications.
• Provides translation of Assembler source code to
object code for all Microchip microcontrollers.
• Macro assembly capability.
• Produces all the files (Object, Listing, Symbol,
and special) required for symbolic debug with
Microchip’s emulator systems.
• Supports Hex (default), Decimal and Octal source
and listing formats.
Preliminary
1998 Microchip Technology Inc.
PIC16CR54C
MPASM provides a rich directive language to support
programming of the PICmicro. Directives are helpful in
making the development of your assemble source
code shorter and more maintainable.
9.11
9.15
Software Simulator (MPLAB-SIM)
The MPLAB-SIM Software Simulator allows code
development in a PC host environment. It allows the
user to simulate the PICmicro series microcontrollers
on an instruction level. On any given instruction, the
user may examine or modify any of the data areas or
provide external stimulus to any of the pins. The
input/output radix can be set by the user and the
execution can be performed in; single step, execute
until break, or in a trace mode.
MPLAB-SIM fully supports symbolic debugging using
MPLAB-C and MPASM. The Software Simulator offers
the low cost flexibility to develop and debug code
outside of the laboratory environment making it an
excellent multi-project software development tool.
9.12
own code. MP-DriveWay is intelligent enough to
maintain your code through subsequent code
generation.
C Compiler (MPLAB-C17)
The MPLAB-C Code Development System is a
complete ‘C’ compiler and integrated development
environment for Microchip’s PIC17CXXX family of
microcontrollers. The compiler provides powerful
integration capabilities and ease of use not found with
other compilers.
SEEVAL Evaluation and
Programming System
The SEEVAL SEEPROM Designer’s Kit supports all
Microchip 2-wire and 3-wire Serial EEPROMs. The kit
includes everything necessary to read, write, erase or
program special features of any Microchip SEEPROM
product including Smart Serials and secure serials.
The Total Endurance Disk is included to aid in
trade-off analysis and reliability calculations. The total
kit can significantly reduce time-to-market and result in
an optimized system.
9.16
KEELOQ Evaluation and
Programming Tools
KEELOQ evaluation and programming tools support
Microchips HCS Secure Data Products. The HCS
evaluation kit includes an LCD display to show
changing codes, a decoder to decode transmissions,
and a programming interface to program test
transmitters.
For easier source level debugging, the compiler
provides symbol information that is compatible with the
MPLAB IDE memory display.
9.13
Fuzzy Logic Development System
(fuzzyTECH-MP)
fuzzyTECH-MP fuzzy logic development tool is
available in two versions - a low cost introductory
version, MP Explorer, for designers to gain a
comprehensive working knowledge of fuzzy logic
system design; and a full-featured version,
fuzzyTECH-MP, Edition for implementing more
complex systems.
Both versions include Microchip’s fuzzyLAB
demonstration board for hands-on experience with
fuzzy logic systems implementation.
9.14
MP-DriveWay – Application Code
Generator
MP-DriveWay is an easy-to-use Windows-based
Application Code Generator. With MP-DriveWay you
can visually configure all the peripherals in a PICmicro
device and, with a click of the mouse, generate all the
initialization and many functional code modules in C
language. The output is fully compatible with
Microchip’s MPLAB-C C compiler. The code produced
is highly modular and allows easy integration of your
1998 Microchip Technology Inc.
Preliminary
DS40191A-page 51
PIC16C5X
PIC16CXXX
PIC16C6X PIC16C7XX PIC16C8X PIC16C9XX PIC17C4X
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
PIC17C75X
24CXX
25CXX
93CXX
HCS200
HCS300
HCS301
EMULATOR PRODUCTS
ü
ICEPIC Low-Cost
In-Circuit Emulator
ü
ü
ü
ü
ü
ü
ü
DEVELOPMENT TOOLS FROM MICROCHIP
PICMASTER/
PICMASTER-CE
In-Circuit Emulator
SOFTWARE PRODUCTS
MPLAB
Integrated
Development
Environment
ü
ü
MPLAB C17
Compiler
Preliminary
fuzzyTECH-MP
Explorer/Edition
Fuzzy Logic Dev. Tool
ü
ü
MP-DriveWay
Applications
Code Generator
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
Total Endurance
Software Model
ü
PROGRAMMERS
1998 Microchip Technology Inc.
PICSTARTPlus
Low-Cost
Universal Dev. Kit
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
PRO MATE II
Universal Programmer
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
KEELOQ Programmer
ü
ü
DEMO BOARDS
ü
SEEVAL Designers Kit
PICDEM-1
PICDEM-2
PICDEM-3
KEELOQ Evaluation Kit
ü
ü
ü
ü
ü
ü
ü
ü
PIC16CR54C
PIC14000
TABLE 9-1:
DS40191A-page 52
PIC12C5XX
PIC16CR54C
10.0
ELECTRICAL CHARACTERISTICS - PIC16CR54C
Absolute Maximum Ratings†
Ambient temperature under bias............................................................................................................–55°C to +125°C
Storage temperature ............................................................................................................................. –65°C to +150°C
Voltage on VDD with respect to VSS ..................................................................................................................0 to +7.5V
Voltage on MCLR with respect to VSS................................................................................................................0 to +14V
Voltage on all other pins with respect to VSS ................................................................................. –0.6V to (VDD + 0.6V)
Total power dissipation(1) .....................................................................................................................................800 mW
Max. current out of VSS pin....................................................................................................................................150 mA
Max. current into VDD pin ......................................................................................................................................100 mA
Max. current into an input pin (T0CKI only)......................................................................................................................±500 µA
Input clamp current, IIK (VI < 0 or VI > VDD) ....................................................................................................................±20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) ..............................................................................................................±20 mA
Max. output current sunk by any I/O pin..................................................................................................................15 mA
Max. output current sourced by any I/O pin ............................................................................................................15 mA
Max. output current sourced by a single I/O port A ................................................................................................45 mA
Max. output current sourced by a single I/O port B ................................................................................................45 mA
Max. output current sunk by a single I/O port A ......................................................................................................45 mA
Max. output current sunk by a single I/O port B .....................................................................................................45 mA
Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOL x IOL)
†
NOTICE: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
1998 Microchip Technology Inc.
Preliminary
DS40191A-page 53
PIC16CR54C
10.1
DC Characteristics:PIC16CR54C-04, 20 (Commercial)
PIC16CR54C-04I, 20I (Industrial)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0°C ≤ TA ≤ +70°C (commercial)
–40°C ≤ TA ≤ +85°C (industrial)
DC Characteristics
Power Supply Pins
Characteristic
Sym
Min
Typ(1) Max Units
3.0
4.5
5.5
5.5
Conditions
Supply Voltage
XT, RC and LP options
HS option
VDD
RAM Data Retention Voltage(2)
VDR
1.5*
V
Device in SLEEP mode
VDD start voltage to ensure
Power-On Reset
VPOR
VSS
V
See Section 7.4 for details on
Power-on Reset
VDD rise rate to ensure
Power-On Reset
SVDD
Supply Current(3)
XT and RC(4) options
HS option
LP option, Commercial
LP option, Industrial
IDD
Power Down Current(5)
Commercial
IPD
Industrial
0.05*
V
V
V/ms See Section 7.4 for details on
Power-on Reset
1.8
4.5
14
17
2.4
16
32
40
mA
mA
µA
µA
FOSC = 4.0 MHz, VDD = 5.5V
FOSC = 20 MHz, VDD = 5.5V
FOSC = 32 kHz, VDD = 3.0V, WDT disabled
FOSC = 32 kHz, VDD = 3.0V, WDT disabled
4.0
0.25
4.0
0.25
12
4.0
14
5.0
µA
µA
µA
µA
VDD = 3.0V, WDT enabled
VDD = 3.0V, WDT disabled
VDD = 3.0V, WDT enabled
VDD = 3.0V, WDT disabled
* These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design guidance
only and is not tested.
2: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus
loading, oscillator type, bus rate, internal code execution pattern, and temperature also have an impact on
the current consumption.
a) The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to
Vss, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified.
b) For standby current measurements, the conditions are the same, except that
the device is in SLEEP mode.
4: Does not include current through Rext. The current through the resistor can be estimated by the
formula: IR = VDD/2Rext (mA) with Rext in kΩ.
5: The power down current in SLEEP mode does not depend on the oscillator type. Power down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
DS40191A-page 54
Preliminary
1998 Microchip Technology Inc.
PIC16CR54C
10.2
DC Characteristics:PIC16CR54C-04, 20, PIC16CR54C-04I, 20I (Commercial, Industrial)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0°C ≤ TA ≤ +70°C (commercial)
–40°C ≤ TA ≤ +85°C (industrial)
Operating Voltage VDD range is described in Section 10.1
DC Characteristics
All Pins Except
Power Supply Pins
Characteristic
Sym
Input Low Voltage
I/O Ports
I/O Ports
MCLR (Schmitt Trigger)
T0CKI (Schmitt Trigger)
OSC1 (Schmitt Trigger)
OSC1
VIL
Input High Voltage
I/O ports
VIH
MCLR (Schmitt Trigger)
T0CKI (Schmitt Trigger)
OSC1 (Schmitt Trigger)
OSC1
Hysteresis of Schmitt
Trigger inputs
Input Leakage Current(3)
I/O ports
VHYS
Typ(1)
Max
Units
VSS
VSS
VSS
VSS
VSS
0.8 VDD
0.15 VDD
0.15 VDD
0.15 VDD
0.15 VDD
0.3 VDD
V
V
V
V
V
Pin at hi-impedance 4.5V , VDD ≤ 5.5V
Pin at hi-impedance 2.5V , VDD ≤ 4.5V
0.25 VDD+0.8V
2.0
0.85 VDD
0.85 VDD
0.85 VDD
0.7 VDD
VDD
VDD
VDD
VDD
VDD
VDD
V
V
V
V
V
V
For all VDD(5)
4.5V < VDD ≤ 5.5V(5)
Min
0.15VDD*
MCLR
0.5
-5.0
-3.0
-3.0
T0CKI
OSC1
Output Low Voltage
I/O ports
OSC2/CLKOUT
VOL
Output High Voltage
I/O ports(3)
OSC2/CLKOUT
VOH
RC option only(4)
XT, HS and LP options
RC option only(4)
XT, HS and LP options
V
IIL
-1.0
Conditions
0.5
0.5
0.5
For VDD ≤ 5.5V
VSS ≤ VPIN ≤ VDD,
Pin at hi-impedance
VPIN = VSS +0.25V(2)
VPIN = VDD(2)
VSS ≤ VPIN ≤ VDD
VSS ≤ VPIN ≤ VDD,
XT, HS and LP options
+1.0
µA
+5.0
+3.0
+3.0
µA
µA
µA
µA
0.6
0.6
V
V
IOL = 5.0 mA, VDD = 4.5V
IOL = 1.6 mA, VDD = 4.5V,
RC option only
V
V
IOH = -3.0 mA, VDD = 4.5V
IOH = -1.0 mA, VDD = 4.5V,
RC option only
VDD-0.7
VDD-0.7
* These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design guidance
only and is not tested.
2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltage.
3: Negative current is defined as coming out of the pin.
4: For the RC option, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16CR54C
be driven with external clock in RC mode.
5: The user may use the better of the two specifications.
1998 Microchip Technology Inc.
Preliminary
DS40191A-page 55
PIC16CR54C
10.3
Timing Parameter Symbology and Load Conditions
The timing parameter symbols have been created following one of the following formats:
1. TppS2ppS
2. TppS
T
F
Frequency
Lowercase subscripts (pp) and their meanings:
pp
2
to
ck
CLKOUT
cy
cycle time
drt
device reset timer
io
I/O port
Uppercase letters and their meanings:
S
F
Fall
H
High
I
Invalid (Hi-impedance)
L
Low
T
Time
mc
osc
os
t0
wdt
MCLR
oscillator
OSC1
T0CKI
watchdog timer
P
R
V
Z
Period
Rise
Valid
Hi-impedance
FIGURE 10-1: LOAD CONDITIONS - PIC16CR54C
Pin
CL = 50 pF for all pins except OSC2
CL
VSS
DS40191A-page 56
15 pF for OSC2 in XT, HS or LP
options when external clock
is used to drive OSC1
Preliminary
1998 Microchip Technology Inc.
PIC16CR54C
10.4
Timing Diagrams and Specifications
FIGURE 10-2: EXTERNAL CLOCK TIMING - PIC16CR54C
Q4
Q1
Q3
Q2
Q4
Q1
OSC1
1
3
3
4
4
2
CLKOUT
TABLE 10-1:
EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16CR54C
AC Characteristics
Parameter
No.
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0°C ≤ TA ≤ +70°C (commercial)
–40°C ≤ TA ≤ +85°C (industrial)
Operating Voltage VDD range is described in Section 10.1
Sym
FOSC
Characteristic
External CLKIN Frequency(2)
Oscillator Frequency(2)
1
TOSC
External CLKIN Period(2)
Oscillator Period(2)
Min
Typ(1)
Max
Units
DC
—
4.0
MHz
DC
—
4.0
MHz
HS osc mode (04)
DC
—
20
MHz
HS osc mode (20)
DC
—
200
kHz
LP osc mode
DC
—
4.0
MHz
RC osc mode
0.455
—
4.0
MHz
XT osc mode
4
—
4.0
MHz
HS osc mode (04)
4
—
20
MHz
HS osc mode (20)
5
—
200
kHz
LP osc mode
Conditions
XT osc mode
250
—
—
ns
XT osc mode
250
—
—
ns
HS osc mode (04)
50
—
—
ns
HS osc mode (20)
5.0
—
—
µs
LP osc mode
250
—
—
ns
RC osc mode
250
—
2,200
ns
XT osc mode
250
—
250
ns
HS osc mode (04)
50
—
250
ns
HS osc mode (20)
5.0
—
200
µs
LP osc mode
* These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
2: All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or
higher than expected current consumption.
When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.
3: Instruction cycle period (TCY) equals four times the input oscillator time base period.
1998 Microchip Technology Inc.
Preliminary
DS40191A-page 57
PIC16CR54C
TABLE 10-1:
EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16CR54C (CONTINUED)
AC Characteristics
Parameter
No.
Sym
2
TCY
3
4
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0°C ≤ TA ≤ +70°C (commercial)
–40°C ≤ TA ≤ +85°C (industrial)
Operating Voltage VDD range is described in Section 10.1
Characteristic
Instruction Cycle Time(3)
TosL, TosH Clock in (OSC1) Low or High Time
TosR, TosF Clock in (OSC1) Rise or Fall Time
Min
Typ(1)
Max
Units
—
4/FOSC
—
—
Conditions
50*
—
—
ns
XT oscillator
20*
—
—
ns
HS oscillator
2.0*
—
—
µs
LP oscillator
—
—
25*
ns
XT oscillator
—
—
25*
ns
HS oscillator
—
—
50*
ns
LP oscillator
* These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
2: All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or
higher than expected current consumption.
When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.
3: Instruction cycle period (TCY) equals four times the input oscillator time base period.
DS40191A-page 58
Preliminary
1998 Microchip Technology Inc.
PIC16CR54C
FIGURE 10-3: CLKOUT AND I/O TIMING - PIC16CR54C
Q1
Q4
Q2
Q3
OSC1
10
11
CLKOUT
13
19
14
12
18
16
I/O Pin
(input)
15
17
I/O Pin
(output)
New Value
Old Value
20, 21
Note: All tests must be done with specified capacitive loads (see data sheet) 50 pF on I/O pins and CLKOUT.
TABLE 10-2:
CLKOUT AND I/O TIMING REQUIREMENTS - PIC16CR54C
AC Characteristics
Parameter
No.
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0°C ≤ TA ≤ +70°C (commercial)
–40°C ≤ TA ≤ +85°C (industrial)
Operating Voltage VDD range is described in Section 10.1
Sym
Characteristic
Min
Typ(1)
Max
Units
10
TosH2ckL
OSC1↑ to CLKOUT↓(2)
—
15
30**
ns
11
TosH2ckH
OSC1↑ to CLKOUT↑(2)
—
15
30**
ns
12
TckR
CLKOUT rise time(2)
—
5.0
15**
ns
13
TckF
CLKOUT fall time(2)
—
5.0
15**
ns
14
TckL2ioV
CLKOUT↓ to Port out valid(2)
—
—
40**
ns
15
TioV2ckH
Port in valid before CLKOUT↑(2)
16
TckH2ioI
Port in hold after CLKOUT↑(2)
0.25 TCY+30*
—
—
ns
0*
—
—
ns
17
TosH2ioV
OSC1↑ (Q1 cycle) to Port out valid(3)
—
—
100*
ns
18
TosH2ioI
OSC1↑ (Q2 cycle) to Port input invalid
(I/O in hold time)
TBD
—
—
ns
19
TioV2osH
Port input valid to OSC1↑
(I/O in setup time)
TBD
—
—
ns
20
TioR
Port output rise time(3)
—
10
25**
ns
21
TioF
Port output fall time(3)
—
10
25**
ns
* These parameters are characterized but not tested.
** These parameters are design targets and are not tested. No characterization data available at this time.
Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
2: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC.
3: See Figure 10-1 for loading conditions.
1998 Microchip Technology Inc.
Preliminary
DS40191A-page 59
PIC16CR54C
FIGURE 10-4: RESET, WATCHDOG TIMER, AND
DEVICE RESET TIMER TIMING - PIC16CR54C
VDD
MCLR
30
Internal
POR
32
32
32
DRT
Time-out
Internal
RESET
Watchdog
Timer
RESET
31
34
34
I/O pin
(Note 1)
Note 1: I/O pins must be taken out of hi-impedance mode by enabling the output drivers in software.
TABLE 10-3:
RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER - PIC16CR54C
AC Characteristics Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0°C ≤ TA ≤ +70°C (commercial)
–40°C ≤ TA ≤ +85°C (industrial)
Operating Voltage VDD range is described in Section 10.1
Parameter
No.
Sym
30
TmcL
MCLR Pulse Width (low)
31
Twdt
Watchdog Timer Time-out Period
(No Prescaler)
32
TDRT
Device Reset Timer Period
9.0*
34
TioZ
I/O Hi-impedance from MCLR Low
100*
Characteristic
Min
Typ(1)
Max
Units
Conditions
1000*
—
—
ns
VDD = 5.0V
9.0*
18*
30*
ms
VDD = 5.0V (Commercial)
18*
30*
ms
VDD = 5.0V (Commercial)
300*
1000*
ns
* These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design
guidance only and are not tested.
DS40191A-page 60
Preliminary
1998 Microchip Technology Inc.
PIC16CR54C
FIGURE 10-5: TIMER0 CLOCK TIMINGS - PIC16CR54C
T0CKI
40
41
42
TABLE 10-4:
TIMER0 CLOCK REQUIREMENTS - PIC16CR54C
AC Characteristics
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0°C ≤ TA ≤ +70°C (commercial)
–40°C ≤ TA ≤ +85°C (industrial)
Operating Voltage VDD range is described in Section 10.1
Parameter
Sym Characteristic
No.
40
Min
Tt0H T0CKI High Pulse Width - No Prescaler
- With Prescaler
41
Tt0L
T0CKI Low Pulse Width - No Prescaler
- With Prescaler
42
Tt0P T0CKI Period
Typ(1) Max Units Conditions
0.5 TCY + 20*
—
—
ns
10*
—
—
ns
0.5 TCY + 20*
—
—
ns
10*
—
—
ns
20 or TCY + 40*
N
—
—
ns
Whichever is greater.
N = Prescale Value
(1, 2, 4,..., 256)
* These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
1998 Microchip Technology Inc.
Preliminary
DS40191A-page 61
PIC16CR54C
NOTES:
DS40191A-page 62
Preliminary
1998 Microchip Technology Inc.
PIC16CR54C
PIC16CR54C
11.0
DC AND AC CHARACTERISTICS - PIC16CR54C
The graphs and tables provided in this section are for design guidance and are not tested or guaranteed. In some
graphs or tables the data presented are outside specified operating range (e.g., outside specified VDD range). This is
for information only and devices will operate properly only within the specified range.
The data presented in this section is a statistical summary of data collected on units from different lots over a period of
time. “Typical” represents the mean of the distribution while “max” or “min” represents (mean + 3σ) and (mean – 3σ)
respectively, where σ is standard deviation.
FIGURE 11-1: TYPICAL RC OSCILLATOR FREQUENCY vs. TEMPERATURE
FOSC
FOSC (25°C)
Frequency normalized to +25°C
1.10
Rext ≥ 10 kΩ
Cext = 100 pF
1.08
1.06
1.04
1.02
1.00
0.98
VDD = 5.5 V
0.96
0.94
VDD = 3.5 V
0.92
0.90
0.88
0
10
20
25
30
40
50
60
70
T(°C)
TABLE 11-1:
RC OSCILLATOR FREQUENCIES
Cext
Average
Fosc @ 5 V, 25°C
Rext
20 pF
3.3 k
5k
10 k
100 k
100 pF
3.3 k
5k
10 k
100 k
300 pF
3.3 k
5.0 k
10 k
160 k
The frequencies are measured on DIP packages.
4.973 MHz
3.82 MHz
2.22 MHz
262.15 kHz
1.63 MHz
1.19 MHz
684.64 kHz
71.56 kHz
660 kHz
484.1 kHz
267.63 kHz
29.44 kHz
± 27%
± 21%
± 21%
± 31%
± 13%
± 13%
± 18%
± 25%
± 10%
± 14%
± 15%
± 19%
The percentage variation indicated here is part-to-part variation due to normal process distribution. The variation
indicated is ±3 standard deviation from average value for VDD = 5 V.
1998 Microchip Technology Inc.
Preliminary
DS40191A-page 63
PIC16CR54C
PIC16CR54C
FIGURE 11-2: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD, CEXT = 20 PF
6.00
R=3.3K
5.00
R=5.0K
Fosc(MHz)
4.00
3.00
R=10K
2.00
Cext=20pF, T=25C
1.00
R=100K
0.00
2.5
3
3.5
4
4.5
5
5.5
6
5.5
6
VDD(Volts)
FIGURE 11-3: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD, CEXT = 100 PF
1.80
R=3.3K
1.60
1.40
R=5.0K
Fosc(MHz)
1.20
1.00
0.80
R=10K
0.60
Cext=100pF, T=25C
0.40
0.20
R=100K
0.00
2.5
3
3.5
4
4.5
5
VDD(Volts)
DS40191A-page 64
Preliminary
1998 Microchip Technology Inc.
PIC16CR54C
PIC16CR54C
FIGURE 11-4: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD, CEXT = 300 PF
700.00
R=3.3K
600.00
500.00
Fosc(KHz)
R=5.0K
400.00
300.00
R=10K
200.00
Cext=300pF, T=25C
100.00
R=100K
0.00
2.5
3
3.5
4
4.5
5
5.5
6
VDD(Volts)
FIGURE 11-5: TYPICAL IPD vs. VDD, WATCHDOG DISABLED (25°C)
2.5
2
Ipd(nA)
Ipd(µA)
1.5
1
0.5
0
2.5
3
3.5
4
4.5
5
5.5
6
VDD(Volts)
1998 Microchip Technology Inc.
Preliminary
DS40191A-page 65
PIC16CR54C
PIC16CR54C
FIGURE 11-6: TYPICAL IPD vs. VDD, WATCHDOG ENABLED (25°C)
25
20
IPD (uA)
15
10
5
0
2.5
3
3.5
4
4.5
5
5.5
6
5.5
6
VDD (Volts)
FIGURE 11-7: TYPICAL IPD vs. VDD, WATCHDOG ENABLED (–40°C, 85°C)
35
30
25
IPD (uA)
20
15
10
(-40°C)
5
(+85°C)
0
2.5
3
3.5
4
4.5
5
VDD (Volts)
DS40191A-page 66
Preliminary
1998 Microchip Technology Inc.
PIC16CR54C
PIC16CR54C
FIGURE 11-8: VTH (INPUT THRESHOLD TRIP POINT VOLTAGE) OF I/O PINS vs. VDD
2.00
1.80
VTH (Volts)
1.60
25°C
Typ (+
)
1.40
1.20
1.00
0.80
0.60
2.5
3.0
3.5
4.0
4.5
VDD (Volts)
5.0
5.5
6.0
FIGURE 11-9: VIH, VIL OF MCLR, T0CKI AND OSC1 (IN RC MODE) vs. VDD
4.5
5°C)
to +8
C
°
(–40
max
VIH
°C
+25
typ
5°C)
VIH
to +8
C
°
(–40
min
VIH
4.0
VIH, VIL (Volts)
3.5
3.0
2.5
2.0
°C to +85°C)
VIL max (–40
VIL typ +25°C
1.5
1.0
5°C)
VIL min (–40°C to +8
0.5
0.0
2.5
3.0
3.5
4.0
4.5
VDD (Volts)
5.0
5.5
6.0
Note: These input pins have Schmitt Trigger input buffers.
1998 Microchip Technology Inc.
Preliminary
DS40191A-page 67
PIC16CR54C
PIC16CR54C
FIGURE 11-10: VTH (INPUT THRESHOLD TRIP POINT VOLTAGE) OF OSC1 INPUT
(IN XT, HS, AND LP MODES) vs. VDD
3.4
3.2
3.0
2.8
VTH (Volts)
2.6
2.4
(
Typ
2.2
+25
°C)
2.0
1.8
1.6
1.4
1.2
1.0
2.5
3.0
3.5
4.0
4.5
VDD (Volts)
5.0
5.5
6.0
FIGURE 11-11: TYPICAL IDD vs. FREQUENCY (WDT DIS, RC MODE @ 20 PF, 25°C)
10000
Idd(uA)
1000
5.5V
100
4.5V
3.5V
2.5V
10
100000
1000000
10000000
Freq(Hz)
DS40191A-page 68
Preliminary
1998 Microchip Technology Inc.
PIC16CR54C
PIC16CR54C
FIGURE 11-12: TYPICAL IDD vs. FREQUENCY (WDT DIS, RC MODE @ 100 PF, 25°C)
10000
Idd(uA)
1000
5.5V
100
4.5V
3.5V
2.5V
10
10000
100000
1000000
10000000
Freq(Hz)
FIGURE 11-13: TYPICAL IDD vs. FREQUENCY (WDT DIS, RC MODE @ 300 PF, 25°C)
10000
Idd(uA)
1000
100
5.5V
4.5V
3.5V
2.5V
10
10000
100000
1000000
Freq(Hz)
1998 Microchip Technology Inc.
Preliminary
DS40191A-page 69
PIC16CR54C
PIC16CR54C
FIGURE 11-14: WDT TIMER TIME-OUT
PERIOD vs. VDD
50
45
40
WDT period (ms)
35
30
Typ +125°C
25
Typ +85°C
20
Typ +25°C
15
Typ –40°C
10
5
2
DS40191A-page 70
3
4
5
VDD (Volts)
6
7
Preliminary
1998 Microchip Technology Inc.
PIC16CR54C
PIC16CR54C
FIGURE 11-15: IOH vs. VOH, VDD = 3 V
FIGURE 11-17: IOL vs. VOL, VDD = 3 V
0
45
Max –40°C
40
–5
35
Min +85°C
IOL (mA)
IOH (mA)
30
–10
Typ +25°C
–15
Max –40°C
25
Typ +25°C
20
15
Min +85°C
–20
10
5
–25
0
0.5
1.0
1.5
2.0
2.5
3.0
0
0.0
VOH (Volts)
FIGURE 11-16: IOH vs. VOH, VDD = 5 V
0.5
1.0 1.5 2.0
VOL (Volts)
3.0
FIGURE 11-18: IOL vs. VOL, VDD = 5 V
90
0
80
Max –40°C
70
–10
60
Typ +125°C
Typ +25°C
–20
IOL (mA)
IOH (mA)
2.5
Typ +85°C
Typ +25°C
50
40
Min +85°C
Typ –40°C
30
–30
20
–40
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
10
VOH (Volts)
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
VOL (Volts)
1998 Microchip Technology Inc.
Preliminary
DS40191A-page 71
PIC16CR54C
PIC16CR54C
NOTES:
DS40191A-page 72
Preliminary
1998 Microchip Technology Inc.
PIC16CR54C
12.0
PACKAGING INFORMATION
12.1
Package Marking Information
18-Lead PDIP
Example
MMMMMMMMMMMMXXX
MMMMMMMMXXXXXXX
AABB CDE
18-Lead SOIC
PIC16CR54C04/P123
9813 HBA
Example
MMMMMMMMM
XXXXXXXXX
PIC16CR54C04I/S0218
AABB CDE
20-Lead SSOP
Example
MMMMMMMM
XXXXXXXX
AABB CDE
PIC16CR54C
04I/218
9810 HBP
Legend: MM...M
XX...X
AA
BB
C
D
E
Note:
*
9810 HDK
Microchip part number information
Customer specific information*
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Facility code of the plant at which wafer is manufactured
O = Outside Vendor
C = 5” Line
S = 6” Line
H = 8” Line
Mask revision number
Assembly code of the plant or country of origin in which
part was assembled
In the event the full Microchip part number cannot be marked on one line,
it will be carried over to the next line thus limiting the number of available
characters for customer specific information.
Standard ROM marking consists of Microchip part number, year code, week
code, facility code, mask rev#, and assembly code. For ROM marking
beyond this, certain price adders apply. Please check with your Microchip
Sales Office.
1998 Microchip Technology Inc.
Preliminary
DS40191A-page 73
PIC16CR54C
Package Type:
K04-007 18-Lead Plastic Dual In-line (P) – 300 mil
E
D
2
n
α
1
E1
A1
A
R
L
c
A2
B1
β
p
B
eB
Units
Dimension Limits
PCB Row Spacing
Number of Pins
Pitch
Lower Lead Width
Upper Lead Width
Shoulder Radius
Lead Thickness
Top to Seating Plane
Top of Lead to Seating Plane
Base to Seating Plane
Tip to Seating Plane
Package Length
Molded Package Width
Radius to Radius Width
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
INCHES*
NOM
0.300
18
0.100
0.013
0.018
0.055
0.060
0.000
0.005
0.005
0.010
0.110
0.155
0.075
0.095
0.000
0.020
0.125
0.130
0.890
0.895
0.245
0.255
0.230
0.250
0.310
0.349
5
10
5
10
MIN
n
p
B
B1†
R
c
A
A1
A2
L
D‡
E‡
E1
eB
α
β
MAX
0.023
0.065
0.010
0.015
0.155
0.115
0.020
0.135
0.900
0.265
0.270
0.387
15
15
MILLIMETERS
NOM
MAX
7.62
18
2.54
0.33
0.46
0.58
1.40
1.52
1.65
0.00
0.13
0.25
0.13
0.25
0.38
2.79
3.94
3.94
1.91
2.41
2.92
0.00
0.51
0.51
3.18
3.30
3.43
22.61
22.73
22.86
6.22
6.48
6.73
5.84
6.35
6.86
7.87
8.85
9.83
5
10
15
5
10
15
MIN
* Controlling Parameter.
†
Dimension “B1” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003”
(0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B1.”
‡
Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed 0.010” (0.254 mm) per side or 0.020” (0.508 mm) more than dimensions “D” or “E.”
DS40191A-page 74
Preliminary
1998 Microchip Technology Inc.
PIC16CR54C
Package Type:
K04-051 18-Lead Plastic Small Outline (SO) – Wide, 300 mil
E1
p
E
D
2
B
1
n
X
45 °
α
L
R2
c
A
R1
β
Units
Dimension Limits
Pitch
Number of Pins
Overall Pack. Height
Shoulder Height
Standoff
Molded Package Length
Molded Package Width
Outside Dimension
Chamfer Distance
Shoulder Radius
Gull Wing Radius
Foot Length
Foot Angle
Radius Centerline
Lead Thickness
Lower Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
L1
φ
A2
INCHES*
NOM
0.050
18
0.093
0.099
0.048
0.058
0.004
0.008
0.450
0.456
0.292
0.296
0.394
0.407
0.010
0.020
0.005
0.005
0.005
0.005
0.016
0.011
0
4
0.015
0.010
0.011
0.009
0.017
0.014
0
12
0
12
MIN
p
n
A
A1
A2
D‡
E‡
E1
X
R1
R2
L
φ
L1
c
B†
α
β
A1
MAX
0.104
0.068
0.011
0.462
0.299
0.419
0.029
0.010
0.010
0.021
8
0.020
0.012
0.019
15
15
MILLIMETERS
NOM
MAX
1.27
18
2.64
2.36
2.50
1.73
1.22
1.47
0.28
0.10
0.19
11.73
11.43
11.58
7.59
7.42
7.51
10.64
10.01
10.33
0.74
0.25
0.50
0.25
0.13
0.13
0.25
0.13
0.13
0.53
0.28
0.41
4
8
0
0.51
0.25
0.38
0.30
0.23
0.27
0.48
0.36
0.42
0
12
15
0
12
15
MIN
*
Controlling Parameter.
†
Dimension “B” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003”
(0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B.”
‡
Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed 0.010” (0.254 mm) per side or 0.020” (0.508 mm) more than dimensions “D” or “E.”
1998 Microchip Technology Inc.
Preliminary
DS40191A-page 75
PIC16CR54C
Package Type:
K04-072 20-Lead Plastic Shrink Small Outine (SS) – 5.30 mm
E1
E
p
D
B
2
1
n
α
L
R2
c
A
A1
R1
φ
L1
A2
β
Units
Dimension Limits
Pitch
Number of Pins
Overall Pack. Height
Shoulder Height
Standoff
Molded Package Length
Molded Package Width
Outside Dimension
Shoulder Radius
Gull Wing Radius
Foot Length
Foot Angle
Radius Centerline
Lead Thickness
Lower Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
INCHES
NOM
0.026
20
0.073
0.068
0.036
0.026
0.005
0.002
0.283
0.278
0.208
0.205
0.306
0.301
0.005
0.005
0.005
0.005
0.020
0.015
0
4
0.005
0.000
0.007
0.005
0.012
0.010
0
5
0
5
MIN
p
n
A
A1
A2
D‡
E‡
E1
R1
R2
L
φ
L1
c
B†
α
β
MAX
0.078
0.046
0.008
0.289
0.212
0.311
0.010
0.010
0.025
8
0.010
0.009
0.015
10
10
MILLIMETERS*
NOM
MAX
0.65
20
1.73
1.86
1.99
0.66
0.91
1.17
0.05
0.13
0.21
7.07
7.20
7.33
5.20
5.29
5.38
7.65
7.78
7.90
0.13
0.13
0.25
0.13
0.13
0.25
0.38
0.51
0.64
8
0
4
0.00
0.13
0.25
0.13
0.18
0.22
0.25
0.32
0.38
0
5
10
0
5
10
MIN
*
Controlling Parameter.
†
Dimension “B” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003”
(0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B.”
‡
Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed 0.010” (0.254 mm) per side or 0.020” (0.508 mm) more than dimensions “D” or “E.”
DS40191A-page 76
Preliminary
1998 Microchip Technology Inc.
PIC16CR54C
APPENDIX A: COMPATIBILITY
To convert code written for PIC16CXX to PIC16C5X,
the user should take the following steps:
1.
2.
3.
4.
5.
6.
7.
Check any CALL, GOTO or instructions that
modify the PC to determine if any program
memory page select operations (PA2, PA1, PA0
bits) need to be made.
Revisit any computed jump operations (write to
PC or add to PC, etc.) to make sure page bits
are set properly under the new scheme.
Eliminate any special function register page
switching. Redefine data variables to reallocate
them.
Verify all writes to STATUS, OPTION, and FSR
registers since these have changed.
Change reset vector to proper value for
processor used.
Remove any use of the ADDLW and SUBLW
instructions.
Rewrite any code segments that use interrupts.
1998 Microchip Technology Inc.
Preliminary
DS40191A-page 77
PIC16CR54C
NOTES:
DS40191A-page 78
Preliminary
1998 Microchip Technology Inc.
PIC16CR54C
INDEX
M
A
MCLR ................................................................................ 29
Memory Map ...................................................................... 13
PIC16C54s/CR54s/C55s ................................................... 13
Memory Organization ........................................................ 13
Data Memory ..................................................................... 13
Program Memory ............................................................... 13
MP-DriveWay™ - Application Code Generator ................. 51
MPLAB C ........................................................................... 51
MPLAB Integrated Development Environment Software ... 50
Absolute Maximum Ratings ............................................... 53
ALU ...................................................................................... 9
Applications .......................................................................... 5
Architectural Overview ......................................................... 9
Assembler
MPASM Assembler ............................................................ 50
B
Block Diagram
On-Chip Reset Circuit ........................................................ 29
PIC16CR54C Series Block Diagram .................................. 10
Timer0 ................................................................................ 21
TMR0/WDT Prescaler ........................................................ 24
Watchdog Timer ................................................................. 33
Brown-Out Protection Circuit ............................................. 34
C
Carry bit ............................................................................... 9
Clocking Scheme ............................................................... 12
Code Protection ........................................................... 25, 35
Configuration Bits ............................................................... 25
Configuration Word ............................................................ 25
PIC16CR54C ..................................................................... 25
D
DC and AC Characteristics - PIC16CR54C ....................... 63
DC Characteristics ............................................................. 54
Development Support ........................................................ 49
Development Tools ............................................................ 49
Device Varieties ................................................................... 7
Digit Carry bit ....................................................................... 9
E
Electrical Characteristics
PIC16CR54C ..................................................................... 53
External Power-On Reset Circuit ....................................... 30
F
Family of Devices
PIC16C5X ............................................................................ 6
Features ............................................................................... 1
FSR .................................................................................... 29
FSR Register ..................................................................... 18
Fuzzy Logic Dev. System (fuzzyTECH-MP) ................... 51
I
I/O Interfacing .................................................................... 19
I/O Ports ............................................................................. 19
I/O Programming Considerations ....................................... 20
ICEPIC Low-Cost PIC16CXXX In-Circuit Emulator ........... 49
INDF ................................................................................... 29
INDF Register .................................................................... 18
Indirect Data Addressing .................................................... 18
Instruction Cycle ................................................................ 12
Instruction Flow/Pipelining ................................................. 12
Instruction Set Summary .................................................... 37
K
KeeLoq Evaluation and Programming Tools ................... 51
L
Loading of PC .................................................................... 17
1998 Microchip Technology Inc.
O
One-Time-Programmable (OTP) Devices ............................7
OPTION Register .............................................................. 16
OSC selection .................................................................... 25
Oscillator Configurations ................................................... 26
Oscillator Types
HS ...................................................................................... 26
LP ...................................................................................... 26
RC ..................................................................................... 26
XT ...................................................................................... 26
P
Package Marking Information ............................................ 73
Packaging Information ....................................................... 73
PC ................................................................................ 17, 29
PIC16CR54C Product Identification System ..................... 83
PICDEM-1 Low-Cost PICmicro Demo Board .................... 49
PICDEM-2 Low-Cost PIC16CXX Demo Board .................. 50
PICDEM-3 Low-Cost PIC16CXXX Demo Board ............... 50
PICMASTER In-Circuit Emulator .................................... 49
PICSTART Plus Entry Level Development System ........ 49
Pin Configurations ................................................................1
Pinout Description - PIC16CR54C .................................... 11
POR
Device Reset Timer (DRT) .......................................... 25, 32
PD ................................................................................ 28, 34
Power-On Reset (POR) ......................................... 25, 29, 30
TO ................................................................................ 28, 34
PORTA ........................................................................ 19, 29
PORTB ........................................................................ 19, 29
Power-Down Mode ............................................................ 35
Prescaler ........................................................................... 24
PRO MATE II Universal Programmer ............................. 49
Program Counter ............................................................... 17
Q
Q cycles ............................................................................. 12
Quick-Turnaround-Production (QTP) Devices ......................7
R
RC Oscillator ..................................................................... 27
Read Only Memory (ROM) Devices .....................................7
Read-Modify-Write ............................................................. 20
Register File Map .............................................................. 13
Registers
Special Function ................................................................ 13
Reset ........................................................................... 25, 28
Reset on Brown-Out .......................................................... 34
S
SEEVAL Evaluation and Programming System ............. 51
Serialized Quick-Turnaround-Production (SQTP) Devices ..7
SLEEP ......................................................................... 25, 35
Software Simulator (MPLAB-SIM) ..................................... 51
Special Features of the CPU ............................................. 25
DS40191A-page 79
PIC16CR54C
Special Function Registers ................................................ 13
Stack .................................................................................. 17
STATUS ............................................................................. 29
STATUS Register ........................................................... 9, 15
T
Timer0
Switching Prescaler Assignment ........................................ 24
Timer0 (TMR0) Module ...................................................... 21
TMR0 with External Clock .................................................. 23
Timing Diagrams and Specifications .................................. 57
Timing Parameter Symbology and Load Conditions .......... 56
TRIS Registers ................................................................... 19
U
UV Erasable Devices ........................................................... 7
W
W ........................................................................................ 29
Wake-up from SLEEP ........................................................ 35
Watchdog Timer (WDT) ............................................... 25, 32
Period ................................................................................. 32
Programming Considerations ............................................. 32
Z
Zero bit ................................................................................. 9
DS40191A-page 80
1998 Microchip Technology Inc.
PIC16CR54C
ON-LINE SUPPORT
Microchip provides on-line support on the Microchip
World Wide Web (WWW) site.
The web site is used by Microchip as a means to make
files and information easily available to customers. To
view the site, the user must have access to the Internet
and a web browser, such as Netscape or Microsoft
Explorer. Files are also available for FTP download
from our FTP site.
Connecting to the Microchip Internet Web Site
Systems Information and Upgrade Hot Line
The Systems Information and Upgrade Line provides
system users a listing of the latest versions of all of
Microchip's development systems software products.
Plus, this line provides information on how customers
can receive any currently available upgrade kits.The
Hot Line Numbers are:
1-800-755-2345 for U.S. and most of Canada, and
1-602-786-7302 for the rest of the world.
980106
The Microchip web site is available by using your
favorite Internet browser to attach to:
www.microchip.com
The file transfer site is available by using an FTP service to connect to:
ftp://ftp.futureone.com/pub/microchip
The web site and file transfer site provide a variety of
services. Users may download files for the latest
Development Tools, Data Sheets, Application Notes,
User's Guides, Articles and Sample Programs. A variety of Microchip specific business information is also
available, including listings of Microchip sales offices,
distributors and factory representatives. Other data
available for consideration is:
• Latest Microchip Press Releases
• Technical Support Section with Frequently Asked
Questions
• Design Tips
• Device Errata
• Job Postings
• Microchip Consultant Program Member Listing
• Links to other useful web sites related to
Microchip Products
• Conferences for products, Development Systems,
technical information and more
• Listing of seminars and events
1998 Microchip Technology Inc.
Trademarks: The Microchip name, logo, PIC, PICSTART,
PICMASTER and PRO MATE are registered trademarks
of Microchip Technology Incorporated in the U.S.A. and
other countries. PICmicro, FlexROM, MPLAB and fuzzyLAB are trademarks and SQTP is a service mark of Microchip in the U.S.A.
fuzzyTECH is a registered trademark of Inform Software
Corporation. IBM, IBM PC-AT are registered trademarks
of International Business Machines Corp. Pentium is a
trademark of Intel Corporation. Windows is a trademark
and MS-DOS, Microsoft Windows are registered trademarks of Microsoft Corporation. CompuServe is a registered trademark of CompuServe Incorporated.
All other trademarks mentioned herein are the property of
their respective companies.
DS40191A-page 81
PIC16CR54C
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (602) 786-7578.
Please list the following information, and use this outline to provide us with your comments about this Data Sheet.
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Address
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Telephone: (_______) _________ - _________
FAX: (______) _________ - _________
Application (optional):
Would you like a reply?
Device: PIC16CR54C
Y
N
Literature Number: DS40191A
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this data sheet easy to follow? If not, why?
4. What additions to the data sheet do you think would enhance the structure and subject?
5. What deletions from the data sheet could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
8. How would you improve our software, systems, and silicon products?
DS40191A-page 82
1998 Microchip Technology Inc.
PIC16CR54C
PIC16CR54C PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
X
-XX
Frequency Temperature
Range
Range
/XX
XXX
Package
Pattern
Device
PIC16CR54C(2), PIC16CR54CT(3)
Frequency
Range
04
20
C
= 4 MHz
= 20 MHz
Temperature
Range
b(1)
I
= 0°C to
= -40°C to
Package
P
SO
SS
= PDIP
= SOIC (Gull Wing, 300 mil body)
= SSOP (209 mil body)
Pattern
3-digit Pattern Code for ROM (blank otherwise)
1998 Microchip Technology Inc.
+70°C
+85°C
Examples:
a)
b)
PIC16CR54C -04/P 301 = Commercial
temp., PDIP package, 4MHz, normal VDD
limitis, pattern #301.
PIC16CR54C - 20I/P355 = ROM program memory, Industrial temp., PDIP
package, 20MHz, normal VDD limits.
(Commercial)
(Industrial)
Preliminary
Note 1: b = blank
2: CR = ROM Version, Standard VDD
range
3: T = in tape and reel - SOIC, SSOP
packages only.
DS40191A-page 83
M
WORLDWIDE SALES AND SERVICE
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC (continued)
Corporate Office
Hong Kong
Taiwan, R.O.C
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Technical Support: 602 786-7627
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Singapore
4/3/98
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Toronto
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Tel: 905-405-6279 Fax: 905-405-6253
All rights reserved. © 1998, Microchip Technology Incorporated, USA. 4/98
Microchip received ISO 9001 Quality
System certification for its worldwide
headquarters, design, and wafer
fabrication facilities in January, 1997.
Our field-programmable PICmicro™
8-bit MCUs, Serial EEPROMs,
related specialty memory products
and development systems conform
to the stringent quality standards of
the International Standard
Organization (ISO).
Printed on recycled paper.
Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation or warranty is given and no
liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use
or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or
otherwise, under any intellectual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other
trademarks mentioned herein are the property of their respective companies.
DS40191A-page 84
1998 Microchip Technology Inc.