62X.bk Page 1 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X
OTP 8-Bit CMOS MCU with EEPROM Data Memory
Devices included in this data sheet:
Pin Diagrams
• PIC16CE623
• PIC16CE624
• PIC16CE625
PDIP, SOIC, Windowed CERDIP
Device
Program
Memory
PIC16CE623
512x14
PIC16CE624
PIC16CE625
•
•
•
•
RAM
EEPROM
Data
Data
Memory Memory
96x8
128x8
1Kx14
96x8
128x8
2Kx14
128x8
128x8
Interrupt capability
16 special function hardware registers
8-level deep hardware stack
Direct, Indirect and Relative addressing modes
18
17
16
15
14
13
12
11
10
RA1/AN1
RA0/AN0
OSC1/CLKIN
OSC2/CLKOUT
VDD
RB7
RB6
RB5
RB4
PIC16CE62X
• Only 35 instructions to learn
• All single-cycle instructions (200 ns), except for
program branches which are two-cycle
• Operating speed:
- DC - 20 MHz clock input
- DC - 200 ns instruction cycle
•1
2
3
4
5
6
7
8
9
PIC16CE62X
RA2/AN2/VREF
RA3/AN3
RA4/T0CKI
MCLR
VSS
RB0/INT
RB1
RB2
RB3
High Performance RISC CPU:
20
19
18
17
16
15
14
13
12
11
RA1/AN1
RA0/AN0
OSC1/CLKIN
OSC2/CLKOUT
VDD
VDD
RB7
RB6
RB5
RB4
SSOP
RA2/AN2/VREF
RA3/AN3
RA4/T0CKI
MCLR
VSS
VSS
RB0/INT
RB1
RB2
RB3
•1
2
3
4
5
6
7
8
9
10
Peripheral Features:
Special Microcontroller Features (cont’d)
• 13 I/O pins with individual direction control
• High current sink/source for direct LED drive
• Analog comparator module with:
- Two analog comparators
- Programmable on-chip voltage reference
(VREF) module
- Programmable input multiplexing from device
inputs and internal voltage reference
- Comparator outputs can be output signals
• Timer0: 8-bit timer/counter with 8-bit
programmable prescaler
• 1,000,000 erase/write cycle EEPROM data memory
• EEPROM data retention > 40 years
• Programmable code protection
• Power saving SLEEP mode
• Selectable oscillator options
• Four user programmable ID locations
Special Microcontroller Features:
• In-Circuit Serial Programming (ICSP™) (via two
pins)
• Power-on Reset (POR)
• Power-up Timer (PWRT) and Oscillator Start-up
Timer (OST)
• Brown-out Reset
• Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation
1998 Microchip Technology Inc.
CMOS Technology:
• Low-power, high-speed CMOS EPROM/EEPROM
technology
• Fully static design
• Wide operating voltage range
- 3.0V to 5.5V
• Commercial, industrial and extended temperature range
• Low power consumption
- < 2.0 mA @ 5.0V, 4.0 MHz
- 15 µA typical @ 3.0V, 32 kHz
- < 1.0 µA typical standby current @ 3.0V
Preliminary
DS40182A-page 1
62X.bk Page 2 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X
Table of Contents
1.0
General Description..................................................................................................................................................................... 3
2.0
PIC16CE62X Device Varieties .................................................................................................................................................... 5
3.0
Architectural Overview ................................................................................................................................................................ 7
4.0
Memory Organization ................................................................................................................................................................ 11
5.0
I/O Ports .................................................................................................................................................................................... 23
6.0
EEPROM Peripheral Operation................................................................................................................................................. 29
7.0
Timer0 Module .......................................................................................................................................................................... 35
8.0
Comparator Module................................................................................................................................................................... 41
9.0
Voltage Reference Module........................................................................................................................................................ 47
10.0 Special Features of the CPU..................................................................................................................................................... 49
11.0 Instruction Set Summary ........................................................................................................................................................... 65
12.0 Development Support................................................................................................................................................................ 77
13.0 Electrical Specifications............................................................................................................................................................. 81
14.0 Packaging Information............................................................................................................................................................... 93
Appendix A:
Code for Accessing EEPROM Data Memory ............................................................................................................. 99
Index .................................................................................................................................................................................................. 101
PIC16CE62X Product Identification System ...................................................................................................................................... 105
To Our Valued Customers
We constantly strive to improve the quality of all our products and documentation. To this end, we recently converted to a new publishing software package which we believe will enhance our entire documentation process and
product. As in any conversion process, information may have accidently been altered or deleted. We have spent an
exceptional amount of time to ensure that these documents are correct. However, we realize that we may have
missed a few things. If you find any information that is missing or appears in error from the previous version of this
data sheet (PIC16CE62X Data Sheet, Literature Number DS40182A), please use the reader response form in the
back of this data sheet to inform us. We appreciate your assistance in making this a better document.
DS40182A-page 2
Preliminary
1998 Microchip Technology Inc.
62X.bk Page 3 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X
1.0
GENERAL DESCRIPTION
The PIC16CE62X are 18 and 20 Pin EPROM-based
members of the versatile PICmicro™ family of low-cost,
high-performance,
CMOS,
fully-static,
8-bit
microcontrollers with EEPROM data memory.
All PICmicro™ microcontrollers employ an advanced
RISC architecture. The PIC16CE62X have enhanced
core features, eight-level deep stack, and multiple internal and external interrupt sources. The separate
instruction and data buses of the Harvard architecture
allow a 14-bit wide instruction word with the separate
8-bit wide data. The two-stage instruction pipeline
allows all instructions to execute in a single-cycle,
except for program branches (which require two
cycles). A total of 35 instructions (reduced instruction
set) are available. Additionally, a large register set gives
some of the architectural innovations used to achieve a
very high performance.
A highly reliable Watchdog Timer with its own on-chip
RC oscillator provides protection against software
lock- up.
A UV-erasable CERDIP-packaged version is ideal for
code development while the cost-effective One-Time
Programmable (OTP) version is suitable for production
in any volume.
Table 1-1 shows the features of the PIC16CE62X
mid-range microcontroller families.
A simplified block diagram of the PIC16CE62X is
shown in Figure 3-1.
PIC16CE62X microcontrollers typically achieve a 2:1
code compression and a 4:1 speed improvement over
other 8-bit microcontrollers in their class.
The PIC16CE62X series fit perfectly in applications
ranging from multi-pocket battery chargers to
low-power remote sensors. The EPROM technology
makes customization of application programs (detection levels, pulse generation, timers, etc.) extremely
fast and convenient. The small footprint packages
make this microcontroller series perfect for all applications with space limitations. Low-cost, low-power,
high-performance, ease of use and I/O flexibility make
the PIC16CE62X very versatile.
The PIC16CE623 and PIC16CE624 have 96 bytes of
RAM. The PIC16CE625 has 128 bytes of RAM. Each
microcontroller contains a 128x8 EEPROM memory
array for storing non-volatile information such as calibration data or security codes. This memory has an
endurance of 1,000,000 erase/write cycles and a retention of 40 plus years.
The PIC16CE62X family is supported by a full-featured
macro assembler, a software simulator, an in-circuit
emulator, a low-cost development programmer and a
full-featured programmer. A “C” compiler and fuzzy
logic support tools are also available.
1.1
Development Support
Each device has 13 I/O pins and an 8-bit timer/counter
with an 8-bit programmable prescaler. In addition, the
PIC16CE62X adds two analog comparators with a
programmable on-chip voltage reference module. The
comparator module is ideally suited for applications
requiring a low-cost analog interface (e.g., battery
chargers,
threshold
detectors,
white
goods
controllers, etc).
PIC16CE62X devices have special features to reduce
external components, thus reducing system cost,
enhancing system reliability and reducing power consumption. There are four oscillator options, of which the
single pin RC oscillator provides a low-cost solution,
the LP oscillator minimizes power consumption, XT is a
standard crystal, and the HS is for High Speed crystals.
The SLEEP (power-down) mode offers power savings.
The user can wake up the chip from SLEEP through
several external and internal interrupts and reset.
1998 Microchip Technology Inc.
Preliminary
DS40182A-page 3
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PIC16CE62X
TABLE 1-1:
PIC16CE62X FAMILY OF DEVICES
Clock
Maximum Frequency
of Operation (MHz)
20
20
20
EPROM Program
Memory
(x14 words)
512
1K
2K
Data Memory (bytes)
96
96
128
EEPROM Data Memory (bytes)
128
128
128
Timer Module(s)
TMR0
TMR0
TMR0
Comparators(s)
2
2
2
Internal Reference
Voltage
Yes
Yes
Yes
Interrupt Sources
4
4
4
I/O Pins
13
13
13
Voltage Range (Volts)
3.0-5.5
3.0-5.5
3.0-5.5
PIC16CE623
Memory
Peripherals
Features
PIC16CE624
PIC16CE625
Brown-out Reset
Yes
Yes
Yes
Packages
18-pin DIP,
SOIC;
20-pin SSOP
18-pin DIP,
SOIC;
20-pin SSOP
18-pin DIP,
SOIC;
20-pin SSOP
All PICmicro™ Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current
capability. All PIC16CE62X Family devices use serial programming with clock pin RB6 and data pin RB7.
DS40182A-page 4
Preliminary
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PIC16CE62X
2.0
PIC16CE62X DEVICE
VARIETIES
2.3
A variety of frequency ranges and packaging options are
available. Depending on application and production
requirements the proper device option can be selected
using the information in the PIC16CE62X Product
Identification System section at the end of this data
sheet. When placing orders, please use this page of the
data sheet to specify the correct part number.
2.1
UV Erasable Devices
The UV erasable version, offered in CERDIP package
is optimal for prototype development and pilot
programs. This version can be erased and
reprogrammed to any of the oscillator modes.
Microchip's
PICSTART
and
PRO MATE
programmers both support programming of the
PIC16CE62X.
2.2
One-Time-Programmable (OTP)
Devices
The availability of OTP devices is especially useful for
customers who need the flexibility for frequent code
updates and small volume applications. In addition to
the program memory, the configuration bits must also
be programmed.
1998 Microchip Technology Inc.
Quick-Turn-Programming (QTP)
Devices
Microchip offers a QTP Programming Service for
factory production orders. This service is made
available for users who chose not to program a medium
to high quantity of units and whose code patterns have
stabilized. The devices are identical to the OTP devices
but with all EPROM locations and configuration options
already programmed by the factory. Certain code and
prototype verification procedures apply before
production shipments are available. Please contact
your Microchip Technology sales office for more details.
2.4
Serialized Quick-Turn-Programming
(SQTPSM) Devices
Microchip offers a unique programming service where
a few user-defined locations in each device are
programmed with different serial numbers. The serial
numbers may be random, pseudo-random or
sequential.
Serial programming allows each device to have a
unique number which can serve as an entry-code,
password or ID number.
Preliminary
DS40182A-page 5
62X.bk Page 6 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X
NOTES:
DS40182A-page 6
Preliminary
1998 Microchip Technology Inc.
62X.bk Page 7 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X
3.0
ARCHITECTURAL OVERVIEW
The high performance of the PIC16CE62X family can
be attributed to a number of architectural features
commonly found in RISC microprocessors. To begin
with, the PIC16CE62X uses a Harvard architecture, in
which, program and data are accessed from separate
memories using separate busses. This improves
bandwidth over traditional von Neumann architecture
where program and data are fetched from the same
memory. Separating program and data memory further
allows instructions to be sized differently than 8-bit
wide data word. Instruction opcodes are 14-bits wide
making it possible to have all single word instructions.
A 14-bit wide program memory access bus fetches a
14-bit instruction in a single cycle. A two-stage pipeline
overlaps fetch and execution of instructions.
Consequently, all instructions (35) execute in a single-cycle (200 ns @ 20 MHz) except for program
branches.
The PIC16CE623 addresses 512 x 14 on-chip program
memory. The PIC16CE624 addresses 1K x 14 program
memory. The PIC16CE625 addresses 2K x 14 program
memory. All program memory is internal.
The PIC16CE62X devices contain an 8-bit ALU and
working register. The ALU is a general purpose
arithmetic unit. It performs arithmetic and Boolean
functions between data in the working register and any
register file.
The ALU is 8-bit wide and capable of addition,
subtraction, shift and logical operations. Unless
otherwise mentioned, arithmetic operations are two's
complement in nature. In two-operand instructions,
typically one operand is the working register
(W register). The other operand is a file register or an
immediate constant. In single operand instructions, the
operand is either the W register or a file register.
The W register is an 8-bit working register used for ALU
operations. It is not an addressable register.
Depending on the instruction executed, the ALU may
affect the values of the Carry (C), Digit Carry (DC), and
Zero (Z) bits in the STATUS register. The C and DC bits
operate as a Borrow and Digit Borrow out bit,
respectively, bit in subtraction. See the SUBLW and
SUBWF instructions for examples.
A simplified block diagram is shown in Figure 3-1, with
a description of the device pins in Table 3-1.
The PIC16CE62X can directly or indirectly address its
register files or data memory. All special function
registers including the program counter are mapped in
the data memory. The PIC16CE62X have an orthogonal (symmetrical) instruction set that makes it possible
to carry out any operation on any register using any
addressing mode. This symmetrical nature and lack of
‘special optimal situations’ make programming with the
PIC16CE62X simple yet efficient. In addition, the
learning curve is reduced significantly.
1998 Microchip Technology Inc.
Preliminary
DS40182A-page 7
62X.bk Page 8 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X
FIGURE 3-1:
BLOCK DIAGRAM
Device
Data Memory
(RAM)
Program Memory
PIC16CE623
PIC16CE624
PIC16CE625
512 X 14
1K X14
2K X 14
96 X 8
96 X 8
128 X 8
EEPROM DATA
MEMORY
128 X 8
128 X 8
128 X 8
13
8
Data Bus
Program Counter
Voltage
Reference
EPROM
Program
Memory
Program
Bus
RAM
File
Registers
8 Level Stack
(13-bit)
14
RAM Addr (1)
9
Comparator
RA0/AN0
Addr MUX
Instruction reg
Direct Addr
7
8
Indirect
Addr
FSR reg
RA1/AN1
+
RA2/AN2/VREF
RA3/AN3
+
STATUS reg
TMR0
3
MUX
Power-up
Timer
Instruction
Decode &
Control
Timing
Generation
OSC1/CLKIN
OSC2/CLKOUT
RA4/T0CKI
Oscillator
Start-up Timer
ALU
Power-on
Reset
W reg
Watchdog
Timer
Brown-out
Reset
I/O Ports
PORTB
MCLR
SCL
VDD, VSS
SDA
VDD
EEPROM
Data
Memory
128x8
EEINTF
Note 1: Higher order bits are from the STATUS register.
DS40182A-page 8
Preliminary
1998 Microchip Technology Inc.
62X.bk Page 9 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X
TABLE 3-1:
PIC16CE62X PINOUT DESCRIPTION
DIP/
SOIC
Pin #
SSOP
Pin #
OSC1/CLKIN
16
18
I
OSC2/CLKOUT
15
17
O
—
Oscillator crystal output. Connects to crystal or resonator
in crystal oscillator mode. In RC mode, OSC2 pin outputs
CLKOUT which has 1/4 the frequency of OSC1, and
denotes the instruction cycle rate.
MCLR/VPP
4
4
I/P
ST
Master clear (reset) input/programming voltage input.
This pin is an active low reset to the device.
RA0/AN0
17
19
I/O
ST
Analog comparator input
RA1/AN1
18
20
I/O
ST
Analog comparator input
RA2/AN2/VREF
1
1
I/O
ST
Analog comparator input or VREF output
RA3/AN3
2
2
I/O
ST
Analog comparator input /output
RA4/T0CKI
3
3
I/O
ST
Can be selected to be the clock input to the Timer0
timer/counter or a comparator output. Output is open
drain type.
Name
I/O/P
Type
Buffer
Type
Description
ST/CMOS Oscillator crystal input/external clock source input.
PORTA is a bi-directional I/O port.
PORTB is a bi-directional I/O port. PORTB can be
software programmed for internal weak pull-up on all
inputs.
RB0/INT
6
7
I/O
TTL/ST(1)
RB1
7
8
I/O
TTL
RB2
8
9
I/O
TTL
RB3
9
10
I/O
TTL
RB4
10
11
I/O
TTL
RB5
11
12
I/O
TTL
RB6
12
13
I/O
TTL/ST(2)
RB0/INT can also be selected as an external
interrupt pin.
Interrupt on change pin.
Interrupt on change pin.
Interrupt on change pin. Serial programming clock.
RB7
13
14
I/O
TTL/ST(2)
VSS
5
5,6
P
—
Ground reference for logic and I/O pins.
VDD
14
15,16
P
—
Positive supply for logic and I/O pins.
Interrupt on change pin. Serial programming data.
Legend:
O = output
I/O = input/output
P = power
— = Not used
I = Input
ST = Schmitt Trigger input
TTL = TTL input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
Note 2: This buffer is a Schmitt Trigger input when used in serial programming mode.
1998 Microchip Technology Inc.
Preliminary
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PIC16CE62X
Clocking Scheme/Instruction Cycle
3.1
3.2
The clock input (OSC1/CLKIN pin) is internally divided
by four to generate four non-overlapping quadrature
clocks namely Q1, Q2, Q3 and Q4. Internally, the
program counter (PC) is incremented every Q1, the
instruction is fetched from the program memory and
latched into the instruction register in Q4. The
instruction is decoded and executed during the
following Q1 through Q4. The clocks and instruction
execution flow is shown in Figure 3-2.
Instruction Flow/Pipelining
An “Instruction Cycle” consists of four Q cycles (Q1,
Q2, Q3 and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle
while decode and execute takes another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (e.g., GOTO)
then two cycles are required to complete the instruction
(Example 3-1).
A fetch cycle begins with the program counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the “Instruction Register (IR)” in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3, and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
FIGURE 3-2:
CLOCK/INSTRUCTION CYCLE
Q1
Q2
Q3
Q4
Q2
Q1
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
Q1
Q2
Internal
phase
clock
Q3
Q4
PC
OSC2/CLKOUT
(RC mode)
EXAMPLE 3-1:
PC
PC+1
Fetch INST (PC)
Execute INST (PC-1)
PC+2
Fetch INST (PC+1)
Execute INST (PC)
Fetch INST (PC+2)
Execute INST (PC+1)
INSTRUCTION PIPELINE FLOW
1. MOVLW 55h
2. MOVWF PORTB
3. CALL
SUB_1
4. BSF
PORTA, BIT3
Fetch 1
Execute 1
Fetch 2
Execute 2
Fetch 3
Execute 3
Fetch 4
Flush
Fetch SUB_1 Execute SUB_1
5. Instruction @
address SUB_1
All instructions are single cycle, except for any program branches. These take two cycles since the fetch
instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed.
DS40182A-page 10
Preliminary
1998 Microchip Technology Inc.
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PIC16CE62X
4.0
MEMORY ORGANIZATION
4.1
Program Memory Organization
FIGURE 4-2:
The PIC16CE62X has a 13-bit program counter capable of addressing an 8K x 14 program memory space.
Only the first 512 x 14 (0000h - 01FFh) for the
PIC16CE623, 1K x 14 (0000h - 03FFh) for the
PIC16CE624 and 2K x 14 (0000h - 07FFh) for the
PIC16CE625 are physically implemented. Accessing a
location above these boundaries will cause a
wrap-around within the first 512 x 14 space
(PIC16CE623) or 1K x 14 space (PIC16CE624) or 2K
x 14 space (PIC16CE625). The reset vector is at 0000h
and the interrupt vector is at 0004h (Figure 4-1,
Figure 4-2, Figure 4-3).
FIGURE 4-1:
PROGRAM MEMORY MAP
AND STACK FOR THE
PIC16CE624
PC<12:0>
CALL, RETURN
RETFIE, RETLW
13
Stack Level 1
Stack Level 2
Stack Level 8
PROGRAM MEMORY MAP
AND STACK FOR THE
PIC16CE623
Reset Vector
000h
Interrupt Vector
0004
0005
PC<12:0>
CALL, RETURN
RETFIE, RETLW
On-chip Program
Memory
13
03FFh
0400h
Stack Level 1
Stack Level 2
1FFFh
Stack Level 8
Reset Vector
FIGURE 4-3:
000h
PROGRAM MEMORY MAP
AND STACK FOR THE
PIC16CE625
PC<12:0>
CALL, RETURN
RETFIE, RETLW
Interrupt Vector
0004
0005
13
Stack Level 1
Stack Level 2
On-chip Program
Memory
Stack Level 8
01FFh
0200h
Reset Vector
000h
Interrupt Vector
0004
0005
1FFFh
On-chip Program
Memory
07FFh
0800h
1FFFh
1998 Microchip Technology Inc.
Preliminary
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PIC16CE62X
4.2
Data Memory Organization
4.2.1
The data memory (Figure 4-4 and Figure 4-5) is
partitioned into two Banks which contain the general
purpose registers and the special function registers.
Bank 0 is selected when the RP0 bit is cleared. Bank 1
is selected when the RP0 bit (STATUS <5>) is set. The
Special Function Registers are located in the first 32
locations of each Bank. Register locations 20-7Fh
(Bank0) on the PIC16CE623/624 and 20-7Fh (Bank0)
and A0-BFh (Bank1) on the PIC16CE625 are general
purpose registers implemented as static RAM. Some
special purpose registers are mapped in Bank 1. In all
three microcontrollers, address space F0h-FFh is
mapped to 70-7Fh.
DS40182A-page 12
GENERAL PURPOSE REGISTER FILE
The register file is organized as 96 x 8 in the
PIC16CE623/624 and 128 x 8 in the PIC16CE625.
Each is accessed either directly or indirectly through
the File Select Register FSR (Section 4.4).
Preliminary
1998 Microchip Technology Inc.
62X.bk Page 13 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X
FIGURE 4-4:
DATA MEMORY MAP FOR
THE PIC16CE623/624
File
Address
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
INDF(1)
TMR0
PCL
STATUS
FSR
PORTA
PORTB
INDF(1)
OPTION
PCL
STATUS
FSR
TRISA
TRISB
PCLATH
INTCON
PIR1
PCLATH
INTCON
PIE1
PCON
EEINTF
CMCON
VRCON
FIGURE 4-5:
File
Address
File
Address
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
A0h
INDF(1)
OPTION
PCL
STATUS
FSR
TRISA
TRISB
PCLATH
INTCON
PIR1
PCLATH
INTCON
PIE1
PCON
EEINTF
CMCON
EFh
F0h
VRCON
General
Purpose
Register
Accesses
70h-7Fh
FFh
7Fh
Bank 1
Unimplemented data memory locations, read as '0'.
Note 1: Not a physical register.
1998 Microchip Technology Inc.
INDF(1)
TMR0
PCL
STATUS
FSR
PORTA
PORTB
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
A0h
BFh
C0h
Accesses
70h-7Fh
Bank 0
File
Address
General
Purpose
Register
General
Purpose
Register
7Fh
DATA MEMORY MAP FOR
THE PIC16CE625
F0h
FFh
Bank 0
Bank 1
Unimplemented data memory locations, read as '0'.
Note 1: Not a physical register.
Preliminary
DS40182A-page 13
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PIC16CE62X
4.2.2
The special registers can be classified into two sets
(core and peripheral). The special function registers
associated with the “core” functions are described in
this section. Those related to the operation of the
peripheral features are described in the section of that
peripheral feature.
SPECIAL FUNCTION REGISTERS
The special function registers are registers used by the
CPU and Peripheral functions for controlling the
desired operation of the device (Table 4-1). These
registers are static RAM.
TABLE 4-1:
SPECIAL REGISTERS FOR THE PIC16CE62X
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR/BOR
Reset
Value on all
other
resets(1)
xxxx xxxx
xxxx xxxx
Bank 0
Addressing this location uses contents of FSR to address data memory (not a physical
register)
00h
INDF
01h
TMR0
Timer0 Module’s Register
xxxx xxxx
uuuu uuuu
02h
PCL
Program Counter's (PC) Least Significant Byte
0000 0000
0000 0000
03h
STATUS
04h
FSR
IRP(2)
RP1(2)
RP0
PD
TO
Z
DC
C
Indirect data memory address pointer
0001 1xxx
000q quuu
xxxx xxxx
uuuu uuuu
05h
PORTA
—
—
—
RA4
RA3
RA2
RA1
RA0
---x 0000
---u 0000
06h
PORTB
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
xxxx xxxx
uuuu uuuu
07h
Unimplemented
—
—
08h
Unimplemented
—
—
09h
Unimplemented
—
—
0Ah
PCLATH
—
---0 0000
---0 0000
0Bh
INTCON
0Ch
PIR1
—
—
Write buffer for upper 5 bits of program counter
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000x
—
CMIF
—
—
—
—
—
—
-0-- ----
-0-- ----
—
—
C2OUT
C1OUT
—
—
CIS
CM2
CM1
CM0
00-- 0000
00-- 0000
xxxx xxxx
xxxx xxxx
0Dh-1Eh Unimplemented
1Fh
CMCON
Bank 1
80h
INDF
Addressing this location uses contents of FSR to address data memory (not a physical
register)
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
81h
OPTION
82h
PCL
83h
STATUS
84h
FSR
85h
TRISA
—
—
—
TRISA4
TRISA3
TRISA2
TRISA1
86h
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
87h
Unimplemented
88h
PS0
Program Counter's (PC) Least Significant Byte
IRP
RP1
RP0
TO
PD
Z
DC
C
Indirect data memory address pointer
1111 1111
1111 1111
0000 0000
0000 0000
0001 1xxx
000q quuu
xxxx xxxx
uuuu uuuu
TRISA0
---1 1111
---1 1111
TRISB0
1111 1111
1111 1111
—
—
Unimplemented
—
—
89h
Unimplemented
—
—
8Ah
PCLATH
—
---0 0000
---0 0000
8Bh
INTCON
8Ch
PIE1
8Dh
Unimplemented
8Eh
PCON
—
—
Write buffer for upper 5 bits of program counter
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000x
—
CMIE
—
—
—
—
—
—
-0-- ----
-0-- ----
—
—
—
—
—
—
—
—
POR
BOR
---- --0x
---- --uq
8Fh-9Eh
Unimplemented
—
—
90h
EEINTF
—
—
—
—
—
EESCL
EESDA
EEVDD
uuuu u111
uuuu u111
VRCON
VREN
VROE
VRR
—
VR3
VR2
VR1
VR0
000- 0000
000- 0000
9Fh
Legend: — = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition,
shaded = unimplemented
Note 1: Other (non power-up) resets include MCLR reset, Brown-out Reset and Watchdog Timer Reset during
normal operation.
Note 2: IRP & RPI bits are reserved, always maintain these bits clear.
DS40182A-page 14
Preliminary
1998 Microchip Technology Inc.
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PIC16CE62X
4.2.2.1
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register because these instructions do not
affect any status bit. For other instructions, not affecting
any status bits, see the “Instruction Set Summary”.
STATUS REGISTER
The STATUS register, shown in Figure 4-6, contains
the arithmetic status of the ALU, the RESET status and
the bank select bits for data memory.
The STATUS register can be the destination for any
instruction, like any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
Note 1:
The IRP and RP1 bits (STATUS<7:6>)
are not used by the PIC16CE62X and
should be programmed as ’0'. Use of
these bits as general purpose R/W bits is
NOT recommended, since this may
affect upward compatibility with future
products.
Note 2:
The C and DC bits operate as a Borrow
and Digit Borrow out bit, respectively, in
subtraction. See the SUBLW and SUBWF
instructions for examples.
For example, CLRF STATUS will clear the upper-three
bits and set the Z bit. This leaves the status register as
000uu1uu (where u = unchanged).
FIGURE 4-6:
STATUS REGISTER (ADDRESS 03H OR 83H)
Reserved Reserved
IRP
RP1
R/W-0
R-1
R-1
R/W-x
R/W-x
R/W-x
RP0
TO
PD
Z
DC
C
bit7
bit 7:
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
-x = Unknown at POR reset
IRP: The IRP bit is reserved on the PIC16CE62X, always maintain this bit clear.
bit 6:5 RP1: RPO: Register Bank Select bits (used for direct addressing)
11 = Bank 3 (180h - 1FFh)
10 = Bank 2 (100h - 17Fh)
01 = Bank 1 (80h - FFh)
00 = Bank 0 (00h - 7Fh)
Each bank is 128 bytes. The RP1 bit is reserved, always maintain this bit clear.
bit 4:
TO: Time-out bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time-out occurred
bit 3:
PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2:
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1:
DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)(for borrow the polarity is reversed)
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
bit 0:
C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)
1 = A carry-out from the most significant bit of the result occurred
0 = No carry-out from the most significant bit of the result occurred
Note: For borrow the polarity is reversed. A subtraction is executed by adding the two’s complement of the
second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of
the source register.
1998 Microchip Technology Inc.
Preliminary
DS40182A-page 15
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PIC16CE62X
4.2.2.2
OPTION REGISTER
Note: To achieve a 1:1 prescaler assignment for
TMR0, assign the prescaler to the WDT
(PSA = 1).
The OPTION register is a readable and writable
register which contains various control bits to configure
the TMR0/WDT prescaler, the external RB0/INT
interrupt, TMR0, and the weak pull-ups on PORTB.
FIGURE 4-7:
OPTION REGISTER (ADDRESS 81H)
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
bit7
bit0
bit 7:
RBPU: PORTB Pull-up Enable bit
1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values
bit 6:
INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin
bit 5:
T0CS: TMR0 Clock Source Select bit
1 = Transition on RA4/T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)
bit 4:
T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on RA4/T0CKI pin
0 = Increment on low-to-high transition on RA4/T0CKI pin
bit 3:
PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
R = Readable bit
W = Writable bit
- n = Value at POR reset
bit 2-0: PS2:PS0: Prescaler Rate Select bits
Bit Value
TMR0 Rate
WDT Rate
000
001
010
011
100
101
110
111
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1:1
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
DS40182A-page 16
Preliminary
1998 Microchip Technology Inc.
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PIC16CE62X
4.2.2.3
INTCON REGISTER
Note:
The INTCON register is a readable and writable
register which contains the various enable and flag bits
for all interrupt sources except the comparator module.
See Section 4.2.2.4 and Section 4.2.2.5 for a
description of the comparator enable and flag bits.
FIGURE 4-8:
R/W-0
GIE
bit7
Interrupt flag bits get set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>).
INTCON REGISTER (ADDRESS 0BH OR 8BH)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-x
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
-x = Unknown at POR reset
bit 7:
GIE: Global Interrupt Enable bit
1 = Enables all un-masked interrupts
0 = Disables all interrupts
bit 6:
PEIE: Peripheral Interrupt Enable bit
1 = Enables all un-masked peripheral interrupts
0 = Disables all peripheral interrupts
bit 5:
T0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt
bit 4:
INTE: RB0/INT External Interrupt Enable bit
1 = Enables the RB0/INT external interrupt
0 = Disables the RB0/INT external interrupt
bit 3:
RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
bit 2:
T0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
bit 1:
INTF: RB0/INT External Interrupt Flag bit
1 = The RB0/INT external interrupt occurred (must be cleared in software)
0 = The RB0/INT external interrupt did not occur
bit 0:
RBIF: RB Port Change Interrupt Flag bit
1 = When at least one of the RB7:RB4 pins changed state (must be cleared in software)
0 = None of the RB7:RB4 pins have changed state
1998 Microchip Technology Inc.
Preliminary
DS40182A-page 17
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PIC16CE62X
4.2.2.4
PIE1 REGISTER
This register contains the individual enable bit for the
comparator interrupt.
FIGURE 4-9:
U-0
—
PIE1 REGISTER (ADDRESS 8CH)
R/W-0
CMIE
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit7
bit0
bit 7:
Unimplemented: Read as '0'
bit 6:
CMIE: Comparator Interrupt Enable bit
1 = Enables the Comparator interrupt
0 = Disables the Comparator interrupt
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 5-0: Unimplemented: Read as '0'
4.2.2.5
PIR1 REGISTER
This register contains the individual flag bit for the comparator interrupt.
Note:
Interrupt flag bits get set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User
software should ensure the appropriate
interrupt flag bits are clear prior to enabling
an interrupt.
FIGURE 4-10: PIR1 REGISTER (ADDRESS 0CH)
U-0
R/W-0
U-0
U-0
U-0
U-0
U-0
U-0
—
CMIF
—
—
—
—
—
—
bit7
bit0
bit 7:
Unimplemented: Read as '0'
bit 6:
CMIF: Comparator Interrupt Flag bit
1 = Comparator input has changed
0 = Comparator input has not changed
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 5-0: Unimplemented: Read as '0'
DS40182A-page 18
Preliminary
1998 Microchip Technology Inc.
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PIC16CE62X
4.2.2.6
PCON REGISTER
The PCON register contains flag bits to differentiate
between a Power-on Reset, an external MCLR reset,
WDT reset or a Brown-out Reset.
Note: BOR is unknown on Power-on Reset. It
must then be set by the user and checked
on subsequent resets to see if BOR is
cleared, indicating a brown-out has
occurred. The BOR status bit is a "don't
care" and is not necessarily predictable if
the brown-out circuit is disabled (by
programming
BODEN
bit
in
the
Configuration word).
FIGURE 4-11: PCON REGISTER (ADDRESS 8Eh)
U-0
—
bit7
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
POR
R/W-0
BOR
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 7-2: Unimplemented: Read as '0'
bit 1:
POR: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0:
BOR: Brown-out Reset Status bit
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
1998 Microchip Technology Inc.
Preliminary
DS40182A-page 19
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PIC16CE62X
4.3
PCL and PCLATH
4.3.2
The program counter (PC) is 13-bits wide. The low byte
comes from the PCL register, which is a readable and
writable register. The high byte (PC<12:8>) is not directly
readable or writable and comes from PCLATH. On any
reset, the PC is cleared. Figure 4-12 shows the two
situations for the loading of the PC. The upper example in
the figure shows how the PC is loaded on a write to PCL
(PCLATH<4:0> → PCH). The lower example in the figure
shows how the PC is loaded during a CALL or GOTO
instruction (PCLATH<4:3> → PCH).
FIGURE 4-12: LOADING OF PC IN
DIFFERENT SITUATIONS
PCH
The PIC16CE62X family has an 8 level deep x 13-bit
wide hardware stack (Figure 4-2 and Figure 4-3). The
stack space is not part of either program or data space
and the stack pointer is not readable or writable. The
PC is PUSHed onto the stack when a CALL instruction
is executed or an interrupt causes a branch. The stack
is POPed in the event of a RETURN, RETLW or a RETFIE
instruction execution. PCLATH is not affected by a
PUSH or POP operation.
The stack operates as a circular buffer. This means that
after the stack has been PUSHed eight times, the ninth
push overwrites the value that was stored from the first
push. The tenth push overwrites the second push (and
so on).
PCL
12
8
7
0
PC
5
8
PCLATH<4:0>
Note 1:
There are no STATUS bits to indicate
stack overflow or stack underflow
conditions.
Note 2:
There are no instruction mnemonics
called PUSH or POP. These are actions
that occur from the execution of the
CALL, RETURN, RETLW and RETFIE
instructions, or the vectoring to an
interrupt address.
Instruction with
PCL as
Destination
ALU result
PCLATH
PCH
12
11 10
STACK
PCL
8
0
7
PC
GOTO, CALL
2
PCLATH<4:3>
11
Opcode <10:0>
PCLATH
4.3.1
COMPUTED GOTO
A computed GOTO is accomplished by adding an
offset to the program counter (ADDWF PCL). When doing
a table read using a computed GOTO method, care
should be exercised if the table location crosses a PCL
memory boundary (each 256 byte block). Refer to the
application note “Implementing a Table Read" (AN556).
DS40182A-page 20
Preliminary
1998 Microchip Technology Inc.
62X.bk Page 21 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X
4.4
Indirect Addressing, INDF and FSR
Registers
A simple program to clear RAM location 20h-2Fh using
indirect addressing is shown in Example 4-1.
The INDF register is not a physical register. Addressing
the INDF register will cause indirect addressing.
EXAMPLE 4-1:
Indirect addressing is possible by using the INDF register. Any instruction using the INDF register actually
accesses data pointed to by the file select register
(FSR). Reading INDF itself indirectly will produce 00h.
Writing to the INDF register indirectly results in a
no-operation (although status bits may be affected). An
effective 9-bit address is obtained by concatenating the
8-bit FSR register and the IRP bit (STATUS<7>), as
shown in Figure 4-13. However, IRP is not used in the
PIC16CE62X.
NEXT
INDIRECT ADDRESSING
movlw
0x20
movwf
FSR
;initialize pointer
;to RAM
clrf
INDF
;clear INDF register
incf
btfss
FSR
FSR,4
;inc pointer
;all done?
goto
NEXT
;no clear next
;yes continue
CONTINUE:
FIGURE 4-13: DIRECT/INDIRECT ADDRESSING PIC16CE62X
Direct Addressing
(1)RP1
RP0
bank select
6
from opcode
Indirect Addressing
0
IRP
(1)
7
bank select
location select
00
01
10
FSR register
0
location select
11
00h
00h
not used
Data
Memory
7Fh
7Fh
Bank 0
Bank 1
Bank 2
Bank 3
For memory map detail see Figure 4-4 and Figure 4-5.
Note 1: The RP1 and IRP bits are reserved, always maintain these bits clear.
1998 Microchip Technology Inc.
Preliminary
DS40182A-page 21
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PIC16CE62X
NOTES:
DS40182A-page 22
Preliminary
1998 Microchip Technology Inc.
62X.bk Page 23 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X
5.0
I/O PORTS
Note:
The PIC16CE62X parts have two ports, PORTA and
PORTB. Some pins for these I/O ports are multiplexed
with an alternate function for the peripheral features on
the device. In general, when a peripheral is enabled,
that pin may not be used as a general purpose I/O pin.
5.1
PORTA and TRISA Registers
PORTA is a 5-bit wide latch. RA4 is a Schmitt Trigger input
and an open drain output. Port RA4 is multiplexed with the
T0CKI clock input. All other RA port pins have Schmitt
Trigger input levels and full CMOS output drivers. All pins
have data direction bits (TRIS registers) which can configure these pins as input or output.
A '1' in the TRISA register puts the corresponding output
driver in a hi- impedance mode. A '0' in the TRISA register
puts the contents of the output latch on the selected pin(s).
Reading the PORTA register reads the status of the pins
whereas writing to it will write to the port latch. All write
operations are read-modify-write operations. So a write
to a port implies that the port pins are first read, then this
value is modified and written to the port data latch.
The PORTA pins are multiplexed with comparator and
voltage reference functions. The operation of these
pins are selected by control bits in the CMCON
(comparator control register) register and the VRCON
(voltage reference control register) register. When
selected as a comparator input, these pins will read
as '0's.
FIGURE 5-1:
Data
bus
D
BLOCK DIAGRAM OF
RA1:RA0 PINS
TRISA controls the direction of the RA pins, even when
they are being used as comparator inputs. The user
must make sure to keep the pins configured as inputs
when using them as comparator inputs.
The RA2 pin will also function as the output for the
voltage reference. When in this mode, the VREF pin is a
very high impedance output. The user must configure
TRISA<2> bit as an input and use high impedance
loads.
In one of the comparator modes defined by the
CMCON register, pins RA3 and RA4 become outputs
of the comparators. The TRISA<4:3> bits must be
cleared to enable outputs to use this function.
EXAMPLE 5-1:
CLRF
;Initialize PORTA by setting
;output data latches
MOVLW 0X07
;Turn comparators off and
MOVWF CMCON
;enable pins for I/O
;functions
BSF
STATUS, RP0 ;Select Bank1
MOVLW 0x1F
;Value used to initialize
;data direction
MOVWF TRISA
;Set RA<4:0> as inputs
;TRISA<7:5> are always
;read as '0'.
FIGURE 5-2:
Data
bus
CK
Q
WR
TRISA
P
CK
Q
VDD
CK
D
WR
TRISA
Q
N
BLOCK DIAGRAM OF RA2 PIN
Q
I/O Pin
Q
N
CK
VSS
RD TRISA
Schmitt Trigger
Input Buffer
Q
Schmitt Trigger
Input Buffer
Q
D
D
EN
EN
RD PORTA
RD PORTA
To Comparator
VROE
To Comparator
Note: I/O pins have protection diodes to VDD and VSS.
1998 Microchip Technology Inc.
VSS
Analog
Input Mode
Analog
Input Mode
RD TRISA
RA2 Pin
Q
TRIS Latch
Q
TRIS Latch
P
Data Latch
Data Latch
D
D
WR
PortA
Q
INITIALIZING PORTA
PORTA
VDD
WR
PortA
On reset, the TRISA register is set to all
inputs. The digital inputs are disabled and
the comparator inputs are forced to ground
to reduce excess current consumption.
VREF
Note: I/O pins have protection diodes to VDD and VSS.
Preliminary
DS40182A-page 23
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PIC16CE62X
FIGURE 5-3:
Data
bus
BLOCK DIAGRAM OF RA3 PIN
Comparator Mode = 110
D
Q
Comparator Output
WR
PortA
VDD
CK Q
Data Latch
D
P
Q
N
WR
TRISA
CK
RA3 Pin
Q
VSS
TRIS Latch
Analog
Input Mode
Schmitt Trigger
Input Buffer
RD TRISA
Q
D
EN
RD PORTA
To Comparator
Note:
I/O pins have protection diodes to VDD and VSS
FIGURE 5-4:
Data
bus
BLOCK DIAGRAM OF RA4 PIN
Comparator Mode = 110
D
Q
Comparator Output
WR
PortA
CK
Q
Data Latch
D
WR
TRISA
Q
N
CK
RA4 Pin
Q
VSS
TRIS Latch
Schmitt Trigger
Input Buffer
RD TRISA
Q
D
EN
RD PORTA
TMR0 Clock Input
Note:
RA4 has protection diodes to VSS only
DS40182A-page 24
Preliminary
1998 Microchip Technology Inc.
62X.bk Page 25 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X
TABLE 5-1:
PORTA FUNCTIONS
Name
Bit #
Buffer
Type
RA0/AN0
RA1/AN1
RA2/AN2/VREF
RA3/AN3
RA4/T0CKI
bit0
bit1
bit2
bit3
bit4
ST
ST
ST
ST
ST
Function
Input/output or comparator input
Input/output or comparator input
Input/output or comparator input or VREF output
Input/output or comparator input/output
Input/output or external clock input for TMR0 or comparator output.
Output is open drain type.
Legend: ST = Schmitt Trigger input
TABLE 5-2:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR / BOR
Value on
All Other
Resets
---u 0000
05h
PORTA
—
—
—
RA4
RA3
RA2
RA1
RA0
---x 0000
85h
TRISA
—
—
—
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
---1 1111
---1 1111
1Fh
CMCON
C2OUT
C1OUT
—
—
CIS
CM2
CM1
CM0
00-- 0000
00-- 0000
9Fh
VRCON
VREN
VROE
VRR
—
VR3
VR2
VR1
VR0
000- 0000
000- 0000
Legend: — = Unimplemented locations, read as ‘0’
Note:
Note: Shaded bits are not used by PORTA.
1998 Microchip Technology Inc.
Preliminary
DS40182A-page 25
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PIC16CE62X
5.2
PORTB and TRISB Registers
PORTB is an 8-bit wide bi-directional port. The
corresponding data direction register is TRISB. A '1' in
the TRISB register puts the corresponding output driver
in a high impedance mode. A '0' in the TRISB register
puts the contents of the output latch on the selected
pin(s).
Reading PORTB register reads the status of the pins,
whereas writing to it will write to the port latch. All write
operations are read-modify-write operations. So a write
to a port implies that the port pins are first read, then
this value is modified and written to the port data latch.
Each of the PORTB pins has a weak internal pull-up
(≈200 µA typical). A single control bit can turn on all the
pull-ups. This is done by clearing the RBPU
(OPTION<7>) bit. The weak pull-up is automatically
turned off when the port pin is configured as an output.
The pull-ups are disabled on Power-on Reset.
Four of PORTB’s pins, RB7:RB4, have an interrupt on
change feature. Only pins configured as inputs can
cause this interrupt to occur (i.e., any RB7:RB4 pin
configured as an output is excluded from the interrupt
on change comparison). The input pins (of RB7:RB4)
are compared with the old value latched on the last
read of PORTB. The “mismatch” outputs of RB7:RB4
are OR’ed together to generate the RBIF interrupt (flag
latched in INTCON<0>).
FIGURE 5-5:
a)
Any read or write of PORTB. This will end the
mismatch condition.
Clear flag bit RBIF.
b)
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition, and
allow flag bit RBIF to be cleared.
This interrupt on mismatch feature, together with
software configurable pull-ups on these four pins allow
easy interface to a key pad and make it possible for
wake-up on key-depression. (See AN552 in the
Microchip Embedded Control Handbook.)
Note:
The interrupt on change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt on change
feature. Polling of PORTB is not recommended while
using the interrupt on change feature.
FIGURE 5-6:
BLOCK DIAGRAM OF
RB3:RB0 PINS
VDD
Data bus
VDD
weak
P pull-up
I/O
pin(1)
CK
weak
P pull-up
Data Latch
D
Q
WR PortB
Data Latch
D
Q
WR PortB
If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the RBIF interrupt flag may not get set.
RBPU(2)
BLOCK DIAGRAM OF
RB7:RB4 PINS
RBPU(2)
Data bus
This interrupt can wake the device from SLEEP. The
user, in the interrupt service routine, can clear the
interrupt in the following manner:
D
WR TRISB
I/O
pin(1)
CK
Q
TTL
Input
Buffer
CK
TRIS Latch
D
Q
WR TRISB
TTL
Input
Buffer
CK
RD TRISB
ST
Buffer
Q
RD PortB
RD TRISB
D
EN
Latch
Q
D
RB0/INT
EN
RD PortB
ST
Buffer
Set RBIF
From other
RB7:RB4 pins
Q
D
RD Port
Note 1: I/O pins have diode protection to VDD and VSS.
EN
RD Port
Note 2: TRISB = 1 enables weak pull-up if RBPU = '0'
(OPTION<7>).
RB7:RB6 in serial programming mode
Note 1: I/O pins have diode protection to VDD and VSS.
Note 2: TRISB = 1 enables weak pull-up if RBPU = '0'
(OPTION<7>).
DS40182A-page 26
Preliminary
1998 Microchip Technology Inc.
62X.bk Page 27 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X
TABLE 5-3:
Name
PORTB FUNCTIONS
Bit #
Buffer Type
Function
Input/output or external interrupt input. Internal software programmable
TTL/ST
weak pull-up.
RB1
bit1
TTL
Input/output pin. Internal software programmable weak pull-up.
RB2
bit2
TTL
Input/output pin. Internal software programmable weak pull-up.
RB3
bit3
TTL
Input/output pin. Internal software programmable weak pull-up.
RB4
bit4
TTL
Input/output pin (with interrupt on change). Internal software
programmable weak pull-up.
RB5
bit5
TTL
Input/output pin (with interrupt on change). Internal software
programmable weak pull-up.
RB6
bit6
Input/output pin (with interrupt on change). Internal software
TTL/ST(2)
programmable weak pull-up. Serial programming clock pin.
RB7
bit7
Input/output pin (with interrupt on change). Internal software
TTL/ST(2)
programmable weak pull-up. Serial programming data pin.
Legend: ST = Schmitt Trigger, TTL = TTL input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
Note 2: This buffer is a Schmitt Trigger input when used in serial programming mode.
RB0/INT
bit0
TABLE 5-4:
(1)
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Address Name
Bit 7
Bit 6
06h
PORTB
RB7
RB6
86h
TRISB
TRISB7
TRISB6
81h
OPTION
RBPU
INTEDG
Note:
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR / BOR
Value on
All Other
Resets
RB5
RB4
RB3
RB2
RB1
RB0
xxxx xxxx
uuuu uuuu
TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111
1111 1111
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
1111 1111
Shaded bits are not used by PORTB.
u = unchanged
x = unknown
1998 Microchip Technology Inc.
Preliminary
DS40182A-page 27
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PIC16CE62X
5.3
I/O Programming Considerations
5.3.1
BI-DIRECTIONAL I/O PORTS
EXAMPLE 5-2:
READ-MODIFY-WRITE
INSTRUCTIONS ON AN
I/O PORT
Any instruction which writes, operates internally as a
read followed by a write operation. The BCF and BSF
instructions, for example, read the register into the
CPU, execute the bit operation and write the result back
to the register. Caution must be used when these
instructions are applied to a port with both inputs and
outputs defined. For example, a BSF operation on bit5
of PORTB will cause all eight bits of PORTB to be read
into the CPU. Then the BSF operation takes place on
bit5 and PORTB is written to the output latches. If
another bit of PORTB is used as a bidirectional I/O pin
(e.g., bit0) and it is defined as an input at this time, the
input signal present on the pin itself would be read into
the CPU and re-written to the data latch of this
particular pin, overwriting the previous content. As long
as the pin stays in the input mode, no problem occurs.
However, if bit0 is switched into output mode later on,
the content of the data latch may now be unknown.
; Initial PORT settings: PORTB<7:4> Inputs
;
;
PORTB<3:0> Outputs
; PORTB<7:6> have external pull-up and are not
; connected to other circuitry
;
;
PORT latch PORT pins
;
---------- ----------
Reading the port register, reads the values of the port
pins. Writing to the port register writes the value to the
port latch. When using read modify write instructions
(ex. BCF, BSF, etc.) on a port, the value of the port pins
is read, the desired operation is done to this value, and
this value is then written to the port latch.
The actual write to an I/O port happens at the end of an
instruction cycle, whereas for reading, the data must be
valid at the beginning of the instruction cycle
(Figure 5-7). Therefore, care must be exercised if a
write followed by a read operation is carried out on the
same I/O port. The sequence of instructions should be
such to allow the pin voltage to stabilize (load
dependent) before the next instruction which causes
that file to be read into the CPU is executed. Otherwise,
the previous state of that pin may be read into the CPU
rather than the new state. When in doubt, it is better to
separate these instructions with an NOP or another
instruction not accessing this I/O port.
BCF
BCF
BSF
BCF
BCF
5.3.2
A pin actively outputting a Low or High should not be
driven from external devices at the same time in order
to change the level on this pin (“wired-or”, “wired-and”).
The resulting high output currents may damage
the chip.
PC
Instruction
fetched
pppp
pppp
11pp pppp
11pp pppp
pppp
pppp
11pp pppp
10pp pppp
SUCCESSIVE OPERATIONS ON I/O PORTS
SUCCESSIVE I/O OPERATION
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
PC
PC + 1
PC + 2
PC + 3
MOVWF PORTB
Write to
PORTB
MOVF PORTB, W
Read PORTB
NOP
NOP
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
TPD
Execute
MOVWF
PORTB
Note:
This example shows write to PORTB
followed by a read from PORTB.
Note that:
data setup time = (0.25 TCY - TPD)
where TCY = instruction cycle and
TPD = propagation delay of Q1 cycle
to output valid.
RB7:RB0
RB <7:0>
DS40182A-page 28
; 01pp
; 10pp
;
; 10pp
; 10pp
;
; Note that the user may have expected the pin
; values to be 00pp pppp. The 2nd BCF caused
; RB7 to be latched as the pin value (High).
Example 5-2 shows the effect of two sequential
read-modify-write instructions (ex., BCF, BSF, etc.) on
an I/O port.
FIGURE 5-7:
PORTB, 7
PORTB, 6
STATUS,RP0
TRISB, 7
TRISB, 6
Port pin
sampled here
Execute
MOVF
PORTB, W
Preliminary
Therefore, at higher clock frequencies,
a write followed by a read may be
problematic.
Execute
NOP
1998 Microchip Technology Inc.
62X.bk Page 29 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X
6.0
EEPROM PERIPHERAL
OPERATION
The PIC16CE623/624/625 each have 128 bytes of
EEPROM data memory. The EEPROM data memory
supports a bi-directional 2-wire bus and data transmission protocol. These two-wires are serial data (SDA)
and serial clock (SCL), that are mapped to bit1 and bit2,
respectively, of the EEINTF register (SFR 90h). In
addition, the power to the EEPROM can be controlled
using bit0 (EEVDD) of the EEINTF register. For most
applications, all that is required is calls to the following
functions:
; Byte_Write: Byte write routine
;
Inputs: EEPROM Address
EEADDR
;
EEPROM Data
EEDATA
;
Outputs:
Return 01 in W if OK, else
return 00 in W
;
; Read_Current: Read EEPROM at address
currently held by EE device.
;
Inputs: NONE
;
Outputs:
EEPROM Data
EEDATA
;
Return 01 in W if OK, else
return 00 in W
;
; Read_Random: Read EEPROM byte at supplied
address
;
Inputs: EEPROM Address
EEADDR
;
Outputs:
EEPROM Data
EEDATA
;
Return 01 in W if OK,
else return 00 in W
FIGURE 6-1:
U-0
-
The code for these functions is not yet determined, but
will be available on our web site (www.microchip.com)
when it is completed. The code will be accessed by
either including the source code FLASH62X.INC or by
linking FLASH62X.ASM.
6.0.1
SERIAL DATA
SDA is a bi-directional pin used to transfer addresses
and data into and data out of the memory.
For normal data transfer SDA is allowed to change only
during SCL low. Changes during SCL high are
reserved for indicating the START and STOP conditions.
6.0.2
SERIAL CLOCK
This SCL input is used to synchronize the data transfer
from and to the memory.
6.0.3
EEINTF REGISTER
The EEINTF register (SFR 90h) controls the access to
the EEPROM. Figure 6.1 details the function of each
bit. User code must generate the clock and data signals.
EEINFT REGISTER (ADDRESS 90h)
U-0
-
U-0
-
U-0
-
U-0
-
R/W-1
EESCL
R/W-1
EESDA
bit7
R/W-1
EEVDD
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 7-3: Unimplemented: Read as '0'
bit 2:
EESCL: Clock line to the EEPROM
1 = Clock high
0 = Clock low
bit 1:
EESDA: Data line to EEPROM
1 = Data line is high (pin is tri-stated, line is pulled high by a pull-up resistor)
0 = Data line is low
bit 0:
EEVDD: VDD control bit for EEPROM
1 = VDD is turned on EEPROM
0 = VDD is turned off EEPROM (all pins are tri-stated and the EEPROM is powered down)
Note:
EESDA, EESCL and EEVDD will read ‘0’ if EEVDD is turned off
1998 Microchip Technology Inc.
Preliminary
DS40182A-page 29
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PIC16CE62X
6.1
6.1.5
BUS CHARACTERISTICS
In this section, the term “processor” refers to the portion
of the PIC16CE62X that interfaces to the EEPROM
through software manipulating the EEINTF register.
The following bus protocol is to be used with the
EEPROM data memory.
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted by the EEPROM as a START or STOP
condition.
Accordingly, the following bus conditions have been
defined (Figure 6-2).
6.1.1
BUS NOT BUSY (A)
Both data and clock lines remain HIGH.
6.1.2
ACKNOWLEDGE
The EEPROM will generate an acknowledge after the
reception of each byte. The processor must generate
an extra clock pulse which is associated with this
acknowledge bit.
Note:
Acknowledge bits are not generated if an
internal programming cycle is in progress.
When the EEPROM acknowledges, it pulls down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. The processor must signal an end of data to
the EEPROM by not generating an acknowledge bit on
the last byte that has been clocked out of the EEPROM.
In this case, the EEPROM must leave the data line
HIGH to enable the processor to generate the STOP
condition (Figure 6-3).
START DATA TRANSFER (B)
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition. All
commands must be preceded by a START condition.
6.1.3
STOP DATA TRANSFER (C)
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.
6.1.4
DATA VALID (D)
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The data on the line must be changed during the LOW
period of the clock signal. There is one bit of data per
clock pulse.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the processor and
is theoretically unlimited, although only the last sixteen
will be stored when doing a write operation. When an
overwrite does occur, it will replace data in a first-in,
first-out fashion.
DS40182A-page 30
Preliminary
1998 Microchip Technology Inc.
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PIC16CE62X
FIGURE 6-2:
SCL
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(B)
(C)
START
CONDITION
ADDRESS OR
ACKNOWLEDGE
VALID
(A)
(D)
(C)
(A)
SDA
FIGURE 6-3:
STOP
CONDITION
DATA
ALLOWED
TO CHANGE
ACKNOWLEDGE TIMING
Acknowledge
Bit
SCL
1
2
SDA
3
4
5
6
7
8
9
1
Device Addressing
Receiver must release the SDA line at this point
so the Transmitter can continue sending data.
FIGURE 6-4:
The last bit of the control byte determines the operation
to be performed. When set to a one a read operation is
selected, and when set to a zero a write operation is
selected. (Figure 6-4). The bus is monitored for its corresponding EEPROM address all the time. It generates
an acknowledge bit if the EEPROM address was true
and it is not in a programming mode.
CONTROL BYTE FORMAT
Read/Write Bit
After generating a START condition, the processor
transmits a control byte consisting of a EEPROM
address and a Read/Write bit that indicates what type
of operation is to be performed. The EEPROM address
consists of a 4-bit device code (1010) followed by three
don't care bits.
1998 Microchip Technology Inc.
3
Data from transmitter
Data from transmitter
Transmitter must release the SDA line at this point
allowing the Receiver to pull the SDA line low to
acknowledge the previous eight bits of data.
6.2
2
Device Select
Bits
S
1
0
1
Don’t Care
Bits
0
X
X
X R/W ACK
EEPROM Address
Start Bit
Preliminary
Acknowledge Bit
DS40182A-page 31
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PIC16CE62X
6.3
WRITE OPERATIONS
6.4
6.3.1
BYTE WRITE
Since the EEPROM will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the stop condition for a write command has been issued from the processor, the
EEPROM initiates the internally timed write cycle. ACK
polling can be initiated immediately. This involves the
processor sending a start condition followed by the
control byte for a write command (R/W = 0). If the
device is still busy with the write cycle, then no ACK will
be returned. If no ACK is returned, then the start bit and
control byte must be re-sent. If the cycle is complete,
then the device will return the ACK and the processor
can then proceed with the next read or write command.
See Figure 6-5 for flow diagram.
Following the start signal from the processor, the
device code (4 bits), the don't care bits (3 bits), and the
R/W bit which is a logic low is placed onto the bus by
the processor. This indicates to the EEPROM that a
byte with a word address will follow after it has generated an acknowledge bit during the ninth clock cycle.
Therefore the next byte transmitted by the processor is
the word address and will be written into the address
pointer of the EEPROM. After receiving another
acknowledge signal from the EEPROM the processor
will transmit the data word to be written into the
addressed memory location. The EEPROM acknowledges again and the processor generates a stop condition. This initiates the internal write cycle, and during
this time the EEPROM will not generate acknowledge
signals (Figure 6-6).
6.3.2
ACKNOWLEDGE POLLING
FIGURE 6-5:
PAGE WRITE
ACKNOWLEDGE POLLING
FLOW
Send
Write Command
The write control byte, word address and the first data
byte are transmitted to the EEPROM in the same way
as in a byte write. But instead of generating a stop condition the processor transmits up to eight data bytes to
the EEPROM which are temporarily stored in the onchip page buffer and will be written into the memory
after the processor has transmitted a stop condition.
After the receipt of each word, the three lower order
address pointer bits are internally incremented by one.
The higher order five bits of the word address remains
constant. If the processor should transmit more than
eight words prior to generating the stop condition, the
address counter will roll over and the previously
received data will be overwritten. As with the byte write
operation, once the stop condition is received an internal write cycle will begin (Figure 6-7).
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Did EEPROM
Acknowledge
(ACK = 0)?
NO
YES
Next
Operation
FIGURE 6-6:
BYTE WRITE
BUS ACTIVITY
PROCESSOR
S
T
A
R
T
SDA LINE
S
BUS ACTIVITY
CONTROL
BYTE
1
0
1
0
X
X
WORD
ADDRESS
X
X
0
X
X
S
T
O
P
DATA
P
X
A
C
K
A
C
K
A
C
K
X = Don’t Care Bit
DS40182A-page 32
Preliminary
1998 Microchip Technology Inc.
62X.bk Page 33 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X
FIGURE 6-7:
BUS ACTIVITY
PROCESSOR
SDA LINE
PAGE WRITE
S
T
A
R
T
CONTROL
BYTE
P
A
C
K
READ OPERATION
6.8
Current Address Read
The EEPROM contains an address counter that maintains the address of the last word accessed, internally
incremented by one. Therefore, if the previous access
(either a read or write operation) was to address n, the
next current address read operation would access data
from address n + 1. Upon receipt of the EEPROM
address with R/W bit set to one, the EEPROM issues
an acknowledge and transmits the eight bit data word.
The processor will not acknowledge the transfer but
does generate a stop condition and the EEPROM discontinues transmission (Figure 6-8).
6.7
S
T
O
P
DATAn + 7
DATAn + 1
A
C
K
A
C
K
Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the
EEPROM address is set to one. There are three basic
types of read operations: current address read, random
read, and sequential read.
6.6
DATA n
S
BUS ACTIVITY
6.5
WORD
ADDRESS (n)
Random Read
A
C
K
A
C
K
Sequential Read
Sequential reads are initiated in the same way as a random read except that after the EEPROM transmits the
first data byte, the processor issues an acknowledge as
opposed to a stop condition in a random read. This
directs the EEPROM to transmit the next sequentially
addressed 8-bit word (Figure 6-10).
To provide sequential reads the EEPROM contains an
internal address pointer which is incremented by one at
the completion of each operation. This address pointer
allows the entire memory contents to be serially read
during one operation.
6.9
Noise Protection
The EEPROM employs a VCC threshold detector circuit
which disables the internal erase/write logic if the VCC
is below 1.5 volts at nominal conditions.
The SCL and SDA inputs have Schmitt trigger and filter
circuits which suppress noise spikes to assure proper
device operation even on a noisy bus.
Random read operations allow the processor to access
any memory location in a random manner. To perform
this type of read operation, first the word address must
be set. This is done by sending the word address to the
EEPROM as part of a write operation. After the word
address is sent, the processor generates a start condition following the acknowledge. This terminates the
write operation, but not before the internal address
pointer is set. Then the processor issues the control
byte again but with the R/W bit set to a one. The
EEPROM will then issue an acknowledge and transmits the eight bit data word. The processor will not
acknowledge the transfer but does generate a stop
condition and the EEPROM discontinues transmission
(Figure 6-9).
1998 Microchip Technology Inc.
Preliminary
DS40182A-page 33
62X.bk Page 34 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X
FIGURE 6-8:
CURRENT ADDRESS READ
BUS ACTIVITY
PROCESSOR
S
T
A
R
T
SDA LINE
S
CONTROL
BYTE
S
T
O
P
DATA n
P
A
C
K
BUS ACTIVITY
N
O
A
C
K
FIGURE 6-9:
RANDOM READ
S
T
CONTROL
BYTE
BUS ACTIVITY A
PROCESSOR R
S
T
A
R
T
WORD
ADDRESS (n)
T
S
SDA LINE
CONTROL
BYTE
S
T
O
P
DATA n
P
S
A
C
K
A
C
K
BUS ACTIVITY
N
O
A
C
K
A
C
K
FIGURE 6-10: SEQUENTIAL READ
BUS ACTIVITY
PROCESSOR
A
C
K
CONTROL
BYTE
S
T
O
P
A
C
K
A
C
K
P
SDA LINE
BUS ACTIVITY
A
C
K
DATA n
DATA n + 1
DATA n + 2
DATA n + X
N
O
A
C
K
DS40182A-page 34
Preliminary
1998 Microchip Technology Inc.
62X.bk Page 35 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X
7.0
TIMER0 MODULE
bit (OPTION<4>). Clearing the T0SE bit selects the
rising edge. Restrictions on the external clock input are
discussed in detail in Section 7.2.
The Timer0 module timer/counter has the following
features:
•
•
•
•
•
•
The prescaler is shared between the Timer0 module
and the WatchdogTimer. The prescaler assignment is
controlled in software by the control bit PSA
(OPTION<3>). Clearing the PSA bit will assign the
prescaler to Timer0. The prescaler is not readable or
writable. When the prescaler is assigned to the Timer0
module, prescale value of 1:2, 1:4, ..., 1:256 are
selectable. Section 7.3 details the operation of the
prescaler.
8-bit timer/counter
Readable and writable
8-bit software programmable prescaler
Internal or external clock select
Interrupt on overflow from FFh to 00h
Edge select for external clock
Figure 7-1 is a simplified block diagram of the Timer0
module.
7.1
Timer mode is selected by clearing the T0CS bit
(OPTION<5>). In timer mode, the TMR0 will increment
every instruction cycle (without prescaler). If Timer0 is
written, the increment is inhibited for the following two
cycles (Figure 7-2 and Figure 7-3). The user can work
around this by writing an adjusted value to TMR0.
Timer0 interrupt is generated when the TMR0 register
timer/counter overflows from FFh to 00h. This overflow
sets the T0IF bit. The interrupt can be masked by
clearing the T0IE bit (INTCON<5>). The T0IF bit
(INTCON<2>) must be cleared in software by the
Timer0 module interrupt service routine before
re-enabling this interrupt. The Timer0 interrupt cannot
wake the processor from SLEEP since the timer is shut
off during SLEEP. See Figure 7-4 for Timer0 interrupt
timing.
Counter mode is selected by setting the T0CS bit. In
this mode Timer0 will increment either on every rising
or falling edge of pin RA4/T0CKI. The incrementing
edge is determined by the source edge (T0SE) control
FIGURE 7-1:
TIMER0 Interrupt
TIMER0 BLOCK DIAGRAM
Data bus
RA4/T0CKI
pin
FOSC/4
0
PSout
1
1
Programmable
Prescaler
8
Sync with
Internal
clocks
0
TMR0
PSout
(2 cycle delay)
T0SE
Set Flag bit T0IF
on Overflow
PSA
PS2:PS0
T0CS
Note 1:
2:
Bits T0SE, T0CS, PS2, PS1, PS0 and PSA are located in the OPTION register.
The prescaler is shared with Watchdog Timer (Figure 7-6)
FIGURE 7-2:
PC
(Program
Counter)
TIMER0 (TMR0) TIMING: INTERNAL CLOCK/NO PRESCALER
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC-1
Instruction
Fetch
TMR0
T0
PC
PC+1
MOVWF TMR0
MOVF TMR0,W
T0+1
Instruction
Executed
1998 Microchip Technology Inc.
PC+2
MOVF TMR0,W
PC+3
MOVF TMR0,W
T0+2
NT0
NT0
Write TMR0
executed
Read TMR0
reads NT0
Read TMR0
reads NT0
Preliminary
PC+4
MOVF TMR0,W
NT0
Read TMR0
reads NT0
PC+5
PC+6
MOVF TMR0,W
NT0+1
Read TMR0
reads NT0 + 1
NT0+2
T0
Read TMR0
reads NT0 + 2
DS40182A-page 35
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PIC16CE62X
FIGURE 7-3:
TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC
(Program
Counter)
PC-1
Instruction
Fetch
PC
PC+1
MOVWF TMR0
MOVF TMR0,W
PC+3
Instruction
Execute
PC+5
MOVF TMR0,W
PC+6
MOVF TMR0,W
NT0+1
NT0
Read TMR0
reads NT0
Write TMR0
executed
FIGURE 7-4:
PC+4
MOVF TMR0,W
T0+1
T0
TMR0
PC+2
MOVF TMR0,W
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0 + 1
TIMER0 INTERRUPT TIMING
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
CLKOUT(3)
TMR0 timer
FEh
FFh
1
T0IF bit
(INTCON<2>)
00h
01h
02h
1
GIE bit
(INTCON<7>)
Interrupt Latency Time
INSTRUCTION FLOW
PC
PC
Instruction
fetched
Inst (PC)
Instruction
executed
Inst (PC-1)
PC +1
PC +1
Inst (PC+1)
Inst (PC)
Dummy cycle
0004h
0005h
Inst (0004h)
Inst (0005h)
Dummy cycle
Inst (0004h)
Note 1: T0IF interrupt flag is sampled here (every Q1).
2: Interrupt latency = 4TCY, where TCY = instruction cycle time.
3: CLKOUT is available only in RC oscillator mode.
DS40182A-page 36
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7.2
Using Timer0 with External Clock
When an external clock input is used for Timer0, it must
meet certain requirements. The external clock
requirement is due to internal phase clock (TOSC)
synchronization. Also, there is a delay in the actual
incrementing of Timer0 after synchronization.
7.2.1
EXTERNAL CLOCK SYNCHRONIZATION
When no prescaler is used, the external clock input is
the same as the prescaler output. The synchronization
of T0CKI with the internal phase clocks is
accomplished by sampling the prescaler output on the
Q2 and Q4 cycles of the internal phase clocks
(Figure 7-5). Therefore, it is necessary for T0CKI to be
high for at least 2TOSC (and a small RC delay of 20 ns)
and low for at least 2TOSC (and a small RC delay of
20 ns). Refer to the electrical specification of the
desired device.
FIGURE 7-5:
When a prescaler is used, the external clock input is
divided by the asynchronous ripple-counter type
prescaler so that the prescaler output is symmetrical.
For the external clock to meet the sampling
requirement, the ripple-counter must be taken into
account. Therefore, it is necessary for T0CKI to have a
period of at least 4TOSC (and a small RC delay of
40 ns) divided by the prescaler value. The only
requirement on T0CKI high and low time is that they do
not violate the minimum pulse width requirement of
10 ns. Refer to parameters 40, 41 and 42 in the
electrical specification of the desired device.
7.2.2
TIMER0 INCREMENT DELAY
Since the prescaler output is synchronized with the
internal clocks, there is a small delay from the time the
external clock edge occurs to the time the TMR0 is
actually incremented. Figure 7-5 shows the delay from
the external clock edge to the timer incrementing.
TIMER0 TIMING WITH EXTERNAL CLOCK
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
External Clock Input or
Prescaler output (2)
Q1 Q2 Q3 Q4
Small pulse
misses sampling
(1)
(3)
External Clock/Prescaler
Output after sampling
Increment Timer0 (Q4)
Timer0
T0
T0 + 1
T0 + 2
Note 1: Delay from clock input change to Timer0 increment is 3Tosc to 7Tosc. (Duration of Q = Tosc).
Therefore, the error in measuring the interval between two edges on Timer0 input = ±4Tosc max.
2: External clock if no prescaler selected, Prescaler output otherwise.
3: The arrows indicate the points in time where sampling occurs.
1998 Microchip Technology Inc.
Preliminary
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7.3
Prescaler
The PSA and PS2:PS0 bits (OPTION<3:0>) determine
the prescaler assignment and prescale ratio.
An 8-bit counter is available as a prescaler for the
Timer0 module, or as a postscaler for the Watchdog
Timer, respectively (Figure 7-6). For simplicity, this
counter is being referred to as “prescaler” throughout
this data sheet. Note that there is only one prescaler
available which is mutually exclusive between the
Timer0 module and the Watchdog Timer. Thus, a
prescaler assignment for the Timer0 module means
that there is no prescaler for the Watchdog Timer, and
vice-versa.
FIGURE 7-6:
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g., CLRF 1, MOVWF 1,
BSF 1,x....etc.) will clear the prescaler. When
assigned to WDT, a CLRWDT instruction will clear the
prescaler along with the Watchdog Timer. The
prescaler is not readable or writable.
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
Data Bus
CLKOUT (=Fosc/4)
0
T0CKI
pin
8
M
U
X
1
M
U
X
0
1
SYNC
2
Cycles
TMR0 reg
T0SE
T0CS
0
Watchdog
Timer
1
M
U
X
Set flag bit T0IF
on Overflow
PSA
8-bit Prescaler
8
8-to-1MUX
PS0 - PS2
PSA
WDT Enable bit
1
0
MUX
PSA
WDT
Time-out
Note: T0SE, T0CS, PSA, PS0-PS2 are bits in the OPTION register.
DS40182A-page 38
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7.3.1
SWITCHING PRESCALER ASSIGNMENT
To change prescaler from the WDT to the TMR0
module use the sequence shown in Example 7-2. This
precaution must be taken even if the WDT is disabled.
The prescaler assignment is fully under software
control (i.e., it can be changed “on the fly” during
program execution). To avoid an unintended device
RESET,
the
following
instruction
sequence
(Example 7-1) must be executed when changing the
prescaler assignment from Timer0 to WDT.
EXAMPLE 7-2:
CHANGING PRESCALER
(WDT→TIMER0)
CLRWDT
EXAMPLE 7-1:
CHANGING PRESCALER
(TIMER0→WDT)
STATUS, RP0 ;Skip if already in
; Bank 0
2.CLRWDT
;Clear WDT
3.CLRF
TMR0
;Clear TMR0 & Prescaler
4.BSF
STATUS, RP0 ;Bank 1
5.MOVLW '00101111’b; ;These 3 lines (5, 6, 7)
6.MOVWF OPTION
; are required only if
; desired PS<2:0> are
7.CLRWDT
; 000 or 001
8.MOVLW '00101xxx’b ;Set Postscaler to
9.MOVWF OPTION
; desired WDT rate
10.BCF
STATUS, RP0 ;Return to Bank 0
;Clear WDT and
;prescaler
BSF
MOVLW
STATUS, RP0
b'xxxx0xxx'
MOVWF
BCF
OPTION_REG
STATUS, RP0
1.BCF
TABLE 7-1:
;Select TMR0, new
;prescale value and
;clock source
REGISTERS ASSOCIATED WITH TIMER0
Address
Name
Bit 7
Bit 6
01h
TMR0
0Bh/8Bh
INTCON
GIE
PEIE
81h
OPTION
RBPU
85h
TRISA
—
Bit 5
Value on:
POR / BOR
Value on
All Other
Resets
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
T0IE
INTE
RBIE
T0IF
INTF
RBIF
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111 1111 1111
—
—
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
---1 1111 ---1 1111
Timer0 module register
xxxx xxxx uuuu uuuu
0000 000x 0000 000x
Legend: — = Unimplemented locations, read as ‘0’.
Note:
Shaded bits are not used by TMR0 module.
1998 Microchip Technology Inc.
Preliminary
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NOTES:
DS40182A-page 40
Preliminary
1998 Microchip Technology Inc.
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PIC16CE62X
8.0
COMPARATOR MODULE
The comparator module contains two analog
comparators. The inputs to the comparators are
multiplexed with the RA0 through RA3 pins. The
on-chip Voltage Reference (Section 9.0) can also be an
input to the comparators.
FIGURE 8-1:
R-0
C2OUT
bit7
The CMCON register, shown in Figure 8-1, controls the
comparator input and output multiplexers. A block
diagram of the comparator is shown in Figure 8-2.
CMCON REGISTER (ADDRESS 1Fh)
R-0
C1OUT
U-0
U-0
bit 7:
C2OUT: Comparator 2 output
1 = C2 VIN+ > C2 VIN–
0 = C2 VIN+ < C2 VIN–
bit 6:
C1OUT: Comparator 1 output
1 = C1 VIN+ > C1 VIN–
0 = C1 VIN+ < C1 VIN–
R/W-0
CIS
R/W-0
CM2
R/W-0
CM1
R/W-0
CM0
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n =Value at POR reset
bit 5-4: Unimplemented: Read as '0'
bit 3:
CIS: Comparator Input Switch
When CM<2:0>: = 001:
1 = C1 VIN– connects to RA3
0 = C1 VIN– connects to RA0
When CM<2:0> = 010:
1 = C1 VIN– connects to RA3
C2 VIN– connects to RA2
0 = C1 VIN– connects to RA0
C2 VIN– connects to RA1
bit 2-0: CM<2:0>: Comparator mode
Figure 8-2.
1998 Microchip Technology Inc.
Preliminary
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8.1
Comparator Configuration
There are eight modes of operation for the
comparators. The CMCON register is used to select the
mode. Figure 8-2 shows the eight possible modes. The
TRISA register controls the data direction of the comparator pins for each mode. If the comparator mode is
FIGURE 8-2:
RA0/AN0
RA3/AN3
RA1/AN1
RA2/AN2
changed, the comparator output level may not be valid
for the specified mode change delay shown in
Table 13-2.
Note:
Comparator interrupts should be disabled
during a comparator mode change otherwise a false interrupt may occur.
COMPARATOR I/O OPERATING MODES
A
VIN-
A
VIN+
A
VIN-
A
VIN+
+
Off
(Read as '0')
C1
+
Off
(Read as '0')
C2
RA0/AN0
RA3/AN3
RA1/AN1
RA2/AN2
D
VIN-
D
VIN+
D
VIN-
D
VIN+
+
C1
Off
(Read as '0')
C2
Off
(Read as '0')
+
CM<2:0> = 000
Comparators Reset
RA0/AN0
RA3/AN3
RA1/AN1
RA2/AN2
A
VIN-
A
VIN+
A
VIN-
A
VIN+
CM<2:0> = 111
Comparators Off
+
C1
C1OUT
+
C2
C2OUT
RA0/AN0 A
CIS=0 VIN-
RA3/AN3 A
CIS=1 VIN+
RA1/AN1 A
CIS=0 VIN-
RA2/AN2 A
CIS=1 VIN+
+
RA0/AN0
RA3/AN3
RA1/AN1
RA2/AN2
A
VIN-
+
D
VIN+
A
VIN-
A
VIN+
+
C1
RA0/AN0
C1OUT
RA3/AN3
+
C2
RA1/AN1
C2OUT
CM<2:0> = 011
C2
C2OUT
From VREF Module
Four Inputs Multiplexed to
Two Comparators
-
C1OUT
-
CM<2:0> = 100
Two Independent Comparators
C1
A
VIN-
D
VIN+
A
VIN-
A
VIN+
CM<2:0> = 010
+
C1
C1OUT
C2
C2OUT
-
+
RA2/AN2
RA4 Open Drain
CM<2:0> = 110
Two Common Reference Comparators
Two Common Rference Comparators with Outputs
RA0/AN0
RA3/AN3
RA1/AN1
RA2/AN2
D
VIN-
D
VIN+
A
VIN-
A
VIN+
+
C1
Off
(Read as '0')
RA0/AN0
RA3/AN3
+
C2
C2OUT
RA1/AN1
RA2/AN2
A
A
CIS=0
VINCIS=1
VIN+
+
A
VIN-
A
VIN+
C1OUT
C2
C2OUT
+
CM<2:0> = 101
One Independent Comparator
C1
CM<2:0> = 001
Three Inputs Multiplexed to
Two Comparators
A = Analog Input, Port Reads Zeros Always
D = Digital Input
CIS = CMCON<3>, Comparator Input Switch
DS40182A-page 42
Preliminary
1998 Microchip Technology Inc.
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PIC16CE62X
The code example in Example 8-1 depicts the steps
required to configure the comparator module. RA3 and
RA4 are configured as digital output. RA0 and RA1 are
configured as the V- inputs and RA2 as the V+ input to
both comparators.
EXAMPLE 8-1:
FLAG_REG
CLRF
CLRF
MOVF
ANDLW
IORWF
MOVLW
MOVWF
BSF
MOVLW
MOVWF
BCF
CALL
MOVF
BCF
BSF
BSF
BCF
BSF
BSF
8.2
INITIALIZING
COMPARATOR MODULE
8.3
Comparator Reference
An external or internal reference signal may be used
depending on the comparator operating mode. The
analog signal that is present at VIN– is compared to the
signal at VIN+, and the digital output of the comparator
is adjusted accordingly (Figure 8-3).
FIGURE 8-3:
EQU
FLAG_REG
PORTA
CMCON,W
0xC0
FLAG_REG,F
0x03
CMCON
STATUS,RP0
0x07
TRISA
0X20
;Init flag register
;Init PORTA
;Move comparator contents to W
;Mask comparator bits
;Store bits in flag register
;Init comparator mode
;CM<2:0> = 011
;Select Bank1
;Initialize data direction
;Set RA<2:0> as inputs
;RA<4:3> as outputs
;TRISA<7:5> always read ‘0’
STATUS,RP0 ;Select Bank 0
DELAY 10
;10µs delay
CMCON,F
;Read CMCON to end change condition
PIR1,CMIF
;Clear pending interrupts
STATUS,RP0 ;Select Bank 1
PIE1,CMIE
;Enable comparator interrupts
STATUS,RP0 ;Select Bank 0
INTCON,PEIE ;Enable peripheral interrupts
INTCON,GIE ;Global interrupt enable
Comparator Operation
VIN–
+
–
Output
VIN–
VIN+
Output
8.3.1
A single comparator is shown in Figure 8-3 along with
the relationship between the analog input levels and
the digital output. When the analog input at VIN+ is less
than the analog input VIN–, the output of the
comparator is a digital low level. When the analog input
at VIN+ is greater than the analog input VIN–, the output
of the comparator is a digital high level. The shaded
areas of the output of the comparator in Figure 8-3
represent the uncertainty due to input offsets and
response time.
1998 Microchip Technology Inc.
VIN+
SINGLE COMPARATOR
EXTERNAL REFERENCE SIGNAL
When external voltage references are used, the
comparator module can be configured to have the comparators operate from the same or different reference
sources. However, threshold detector applications may
require the same reference. The reference signal must
be between VSS and VDD, and can be applied to either
pin of the comparator(s).
8.3.2
INTERNAL REFERENCE SIGNAL
The comparator module also allows the selection of an
internally generated voltage reference for the
comparators. Section 13, Instruction Sets, contains a
detailed description of the Voltage Reference Module
that provides this signal. The internal reference signal
is used when the comparators are in mode
CM<2:0>=010 (Figure 8-2). In this mode, the internal
voltage reference is applied to the VIN+ pin of both comparators.
Preliminary
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8.4
Comparator Response Time
8.5
Response time is the minimum time, after selecting a
new reference voltage or input source, before the
comparator output is guaranteed to have a valid level.
If the internal reference is changed, the maximum
delay of the internal voltage reference must be
considered when using the comparator outputs.
Otherwise the maximum delay of the comparators
should be used (Table 13-2 ).
Comparator Outputs
The comparator outputs are read through the CMCON
register. These bits are read only. The comparator
outputs may also be directly output to the RA3 and RA4
I/O pins. When the CM<2:0> = 110, multiplexors in the
output path of the RA3 and RA4 pins will switch and the
output of each pin will be the unsynchronized output of
the comparator. The uncertainty of each of the
comparators is related to the input offset voltage and
the response time given in the specifications.
Figure 8-4 shows the comparator output block
diagram.
The TRISA bits will still function as an output
enable/disable for the RA3 and RA4 pins while in this
mode.
Note 1: When reading the PORT register, all pins
configured as analog inputs will read as
a ‘0’. Pins configured as digital inputs will
convert an analog input according to the
Schmitt Trigger input specification.
2: Analog levels on any pin that is defined
as a digital input may cause the input
buffer to consume more current than is
specified.
FIGURE 8-4:
COMPARATOR OUTPUT BLOCK DIAGRAM
Port Pins
MULTIPLEX
+
-
To RA3 or
RA4 Pin
Bus
Data
Q
RD CMCON
Set
CMIF
Bit
D
EN
Q
From
Other
Comparator
D
EN
CL
RD CMCON
NRESET
DS40182A-page 44
Preliminary
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8.6
Comparator Interrupts
wake up the device from SLEEP mode when enabled.
While the comparator is powered-up, higher sleep
currents than shown in the power down current
specification will occur. Each comparator that is
operational will consume additional current as shown in
the comparator specifications. To minimize power
consumption while in SLEEP mode, turn off the
comparators, CM<2:0> = 111, before entering sleep. If
the device wakes-up from sleep, the contents of the
CMCON register are not affected.
The comparator interrupt flag is set whenever there is
a change in the output value of either comparator.
Software will need to maintain information about the
status of the output bits, as read from CMCON<7:6>, to
determine the actual change that has occurred. The
CMIF bit, PIR1<6>, is the comparator interrupt flag.
The CMIF bit must be reset by clearing ‘0’. Since it is
also possible to write a '1' to this register, a simulated
interrupt may be initiated.
8.8
The CMIE bit (PIE1<6>) and the PEIE bit
(INTCON<6>) must be set to enable the interrupt. In
addition, the GIE bit must also be set. If any of these
bits are clear, the interrupt is not enabled, though the
CMIF bit will still be set if an interrupt condition occurs.
Note:
A device reset forces the CMCON register to its reset
state. This forces the comparator module to be in the
comparator reset mode, CM2:CM0 = 000. This
ensures that all potential inputs are analog inputs.
Device current is minimized when analog inputs are
present at reset time. The comparators will be
powered-down during the reset interval.
If a change in the CMCON register
(C1OUT or C2OUT) should occur when a
read operation is being executed (start of
the Q2 cycle), then the CMIF (PIR1<6>)
interrupt flag may not get set.
8.9
The user, in the interrupt service routine, can clear the
interrupt in the following manner:
a)
b)
Comparator Operation During SLEEP
When a comparator is active and the device is placed
in SLEEP mode, the comparator remains active and
the interrupt is functional if enabled. This interrupt will
FIGURE 8-5:
Analog Input Connection
Considerations
A simplified circuit for an analog input is shown in
Figure 8-5. Since the analog pins are connected to a
digital output, they have reverse biased diodes to VDD
and VSS. The analog input therefore, must be between
VSS and VDD. If the input voltage deviates from this
range by more than 0.6V in either direction, one of the
diodes is forward biased and a latch-up may occur. A
maximum
source
impedance
of
10 kΩ
is
recommended for the analog sources. Any external
component connected to an analog input pin, such as
a capacitor or a Zener diode, should have very little
leakage current.
Any read or write of CMCON. This will end the
mismatch condition.
Clear flag bit CMIF.
A mismatch condition will continue to set flag bit CMIF.
Reading CMCON will end the mismatch condition, and
allow flag bit CMIF to be cleared.
8.7
Effects of a RESET
ANALOG INPUT MODEL
VDD
VT = 0.6V
RS
RIC < 10K
AIN
CPIN
5 pF
VA
VT = 0.6V
ILEAKAGE
±500 nA
VSS
Legend
CPIN
VT
ILEAKAGE
RIC
RS
VA
1998 Microchip Technology Inc.
= Input Capacitance
= Threshold Voltage
= Leakage Current At The Pin Due To Various Junctions
= Interconnect Resistance
= Source Impedance
= Analog Voltage
Preliminary
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TABLE 8-1:
Address
Name
1Fh
9Fh
REGISTERS ASSOCIATED WITH COMPARATOR MODULE
Bit 7
Bit 6
CMCON
C2OUT
VRCON
VREN
0Bh
INTCON
0Ch
PIR1
8Ch
85h
Note:
Bit 5
Bit 4
C1OUT
—
VROE
VRR
GIE
PEIE
—
CMIF
PIE1
—
CMIE
—
TRISA
—
—
—
Value on
POR / BOR
Value on
All Other
Resets
Bit 3
Bit 2
Bit 1
Bit 0
—
CIS
CM2
CM1
CM0
00-- 0000 00-- 0000
—
VR3
VR2
VR1
VR0
000- 0000 000- 0000
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x 0000 000x
—
—
—
—
—
—
-0-- ---- -0-- ----
—
—
—
—
—
-0-- ---- -0-- ----
TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 ---1 1111 ---1 1111
x = Unknown
- = Unimplemented, read as "0"
DS40182A-page 46
Preliminary
1998 Microchip Technology Inc.
62X.bk Page 47 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X
9.0
VOLTAGE REFERENCE
MODULE
9.1
The Voltage Reference can output 16 distinct voltage
levels for each range.
The Voltage Reference is a 16-tap resistor ladder
network that provides a selectable voltage reference.
The resistor ladder is segmented to provide two ranges
of VREF values and has a power-down function to
conserve power when the reference is not being used.
The VRCON register controls the operation of the
reference as shown in Figure 9-1. The block diagram is
given in Figure 9-2.
FIGURE 9-1:
R/W-0
VREN
bit7
Configuring the Voltage Reference
The equations used to calculate the output of the
Voltage Reference are as follows:
if VRR = 1: VREF = (VR<3:0>/24) x VDD
if VRR = 0: VREF = (VDD x 1/4) + (VR<3:0>/32) x VDD
The setting time of the Voltage Reference must be
considered when changing the VREF output
(Table 13-2). Example 9-1 shows an example of how to
configure the Voltage Reference for an output voltage
of 1.25V with VDD = 5.0V.
VRCON REGISTER(ADDRESS 9Fh)
R/W-0
VROE
R/W-0
VRR
U-0
—
R/W-0
VR3
R/W-0
VR2
bit 7:
VREN: VREF Enable
1 = VREF circuit powered on
0 = VREF circuit powered down, no IDD drain
bit 6:
VROE: VREF Output Enable
1 = VREF is output on RA2 pin
0 = VREF is disconnected from RA2 pin
bit 5:
VRR: VREF Range selection
1 = Low Range
0 = High Range
bit 4:
Unimplemented: Read as '0'
R/W-0
VR1
R/W-0
VR0
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n =Value at POR reset
bit 3-0: VR<3:0>: VREF value selection 0 ≤ VR [3:0] ≤ 15
when VRR = 1: VREF = (VR<3:0>/ 24) * VDD
when VRR = 0: VREF = 1/4 * VDD + (VR<3:0>/ 32) * VDD
FIGURE 9-2:
VOLTAGE REFERENCE BLOCK DIAGRAM
16 Stages
VREN
8R
R
R
R
R
8R
VRR
VR3
VREF
(From VRCON<3:0>)
16-1 Analog Mux
VR0
Note:
R is defined in Table 13-3.
1998 Microchip Technology Inc.
Preliminary
DS40182A-page 47
62X.bk Page 48 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X
EXAMPLE 9-1:
VOLTAGE REFERENCE
CONFIGURATION
9.4
Effects of a Reset
A device reset disables the Voltage Reference by clearing bit VREN (VRCON<7>). This reset also disconnects
the reference from the RA2 pin by clearing bit VROE
(VRCON<6>) and selects the high voltage range by
clearing bit VRR (VRCON<5>). The VREF value select
bits, VRCON<3:0>, are also cleared.
MOVLW
0x02
; 4 Inputs Muxed
MOVWF
BSF
CMCON
STATUS,RP0
; to 2 comps.
; go to Bank 1
MOVLW
0x07
; RA3-RA0 are
MOVWF
TRISA
; outputs
MOVLW
MOVWF
0xA6
VRCON
; enable VREF
; low range
9.5
; set VR<3:0>=6
BCF
CALL
STATUS,RP0
DELAY10
The Voltage Reference Module operates independently
of the comparator module. The output of the reference
generator may be connected to the RA2 pin if the
TRISA<2> bit is set and the VROE bit, VRCON<6>, is
set. Enabling the Voltage Reference output onto the
RA2 pin with an input signal present will increase current consumption. Connecting RA2 as a digital output
with VREF enabled will also increase current consumption.
; go to Bank 0
; 10µs delay
Voltage Reference Accuracy/Error
9.2
The full range of VSS to VDD cannot be realized due to
the construction of the module. The transistors on the
top and bottom of the resistor ladder network
(Figure 9-2) keep VREF from approaching VSS or VDD.
The Voltage Reference is VDD derived and therefore,
the VREF output changes with fluctuations in VDD. The
absolute accuracy of the Voltage Reference can be
found in Table 13-3.
9.3
Connection Considerations
The RA2 pin can be used as a simple D/A output with
limited drive capability. Due to the limited drive
capability, a buffer must be used in conjunction with the
Voltage Reference output for external connections to
VREF. Figure 9-3 shows an example buffering
technique.
Operation During Sleep
When the device wakes up from sleep through an
interrupt or a Watchdog Timer time-out, the contents of
the VRCON register are not affected. To minimize
current consumption in SLEEP mode, the Voltage
Reference should be disabled.
FIGURE 9-3:
VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE
R(1)
VREF
RA2
•
Module
+
–
•
VREF Output
Voltage
Reference
Output
Impedance
Note 1: R is dependent upon the Voltage Reference Configuration VRCON<3:0> and VRCON<5>.
TABLE 9-1:
REGISTERS ASSOCIATED WITH VOLTAGE REFERENCE
Address
Name
9Fh
VRCON
1Fh
CMCON
85h
TRISA
—
Note:
Bit 7
Bit 2
Bit 1
Bit 0
Value On
POR / BOR
Value On
All Other
Resets
Bit 6
Bit 5
Bit 4
Bit 3
VREN
VROE
VRR
—
VR3
VR2
VR1
VR0
000- 0000
000- 0000
C2OUT
C1OUT
—
—
CIS
CM2
CM1
CM0
00-- 0000
00-- 0000
—
—
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
---1 1111
---1 1111
- = Unimplemented, read as "0"
DS40182A-page 48
Preliminary
1998 Microchip Technology Inc.
62X.bk Page 49 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X
10.0
SPECIAL FEATURES OF THE
CPU
What sets a microcontroller apart from other
processors are special circuits to deal with the needs of
real time applications. The PIC16CE62X family has a
host of such features intended to maximize system
reliability, minimize cost through elimination of external
components, provide power saving operating modes
and offer code protection.
These are:
1.
2.
3.
4.
5.
6.
7.
8.
OSC selection
Reset
Power-on Reset (POR)
Power-up Timer (PWRT)
Oscillator Start-Up Timer (OST)
Brown-out Reset (BOR)
Interrupts
Watchdog Timer (WDT)
SLEEP
Code protection
ID Locations
In-circuit serial programming
1998 Microchip Technology Inc.
The PIC16CE62X has a Watchdog Timer which is
controlled by configuration bits. It runs off its own RC
oscillator for added reliability. There are two timers that
offer necessary delays on power-up. One is the
Oscillator Start-up Timer (OST), intended to keep the
chip in reset until the crystal oscillator is stable. The
other is the Power-up Ttimer (PWRT), which provides a
fixed delay of 72 ms (nominal) on power-up only,
designed to keep the part in reset while the power
supply stabilizes. There is also circuitry to reset the
device if a brown-out occurs which provides at least a
72 ms reset. With these three functions on-chip, most
applications need no external reset circuitry.
The SLEEP mode is designed to offer a very low
current power-down mode. The user can wake-up from
SLEEP through external reset, Watchdog Timer
wake-up or through an interrupt. Several oscillator
options are also made available to allow the part to fit
the application. The RC oscillator option saves system
cost while the LP crystal option saves power. A set of
configuration bits are used to select various options.
Preliminary
DS40182A-page 49
62X.bk Page 50 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X
10.1
Configuration Bits
The configuration bits can be programmed (read as '0')
or left unprogrammed (read as '1') to select various
device configurations. These bits are mapped in
program memory location 2007h.
The user will note that address 2007h is beyond
the user program memory space. In fact, it belongs
to the special test/configuration memory space
(2000h – 3FFFh), which can be accessed only during
programming.
FIGURE 10-1: CONFIGURATION WORD
CP1
CP0(2)
CP1
CP0(2)
CP1
CP0(2)
—
BODE(1) CP1
CP0(2) PWRTE(1) WDTE F0SC1
bit13
bit 13-8
5-4:
F0SC0
bit0
CONFIG
Address
REGISTER: 2007h
CP1:CP0 Pairs: Code protection bits(2)
Code protection for 2K program memory
11 = Program memory code protection off
10 = 0400h-07FFh code protected
01 = 0200h-07FFh code protected
00 = 0000h-07FFh code protected
Code protection for 1K program memory
11 = Program memory code protection off
10 =Program memory code protection on
01 = 0200h-03FFh code protected
00 = 0000h-03FFh code protected
Code protection for 0.5K program memory
11 = Program memory code protection off
10 = Program memory code protection of
01 = Program memory code protection of
00 = 0000h-01FFh code protected
bit 7:
Unimplemented: Read as '1'
bit 6:
BODEN: Brown-out Reset Enable bit (1)
1 = BOR enabled
0 = BOR disabled
bit 3:
PWRTE: Power-up Timer Enable bit (1)
1 = PWRT disabled
0 = PWRT enabled
bit 2:
WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 1-0:
FOSC1:FOSC0: Oscillator Selection bits
11 = RC oscillator
10 = HS oscillator
01 = XT oscillator
00 = LP oscillator
Note 1: Enabling Brown-out Reset automatically enables Power-up Timer (PWRT) regardless of the value of bit PWRTE. Ensure
the Power-up Timer is enabled anytime Brown-out Reset is enabled.
2: All of the CP1:CP0 pairs have to be given the same value to enable the code protection scheme listed.
DS40182A-page 50
Preliminary
1998 Microchip Technology Inc.
62X.bk Page 51 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X
10.2
Oscillator Configurations
10.2.1
OSCILLATOR TYPES
TABLE 10-1:
The PIC16CE62X can be operated in four different
oscillator options. The user can program two
configuration bits (FOSC1 and FOSC0) to select one of
these four modes:
•
•
•
•
LP
XT
HS
RC
10.2.2
Low Power Crystal
Crystal/Resonator
High Speed Crystal/Resonator
Resistor/Capacitor
Ranges Tested:
Mode
XT
455 kHz
2.0 MHz
4.0 MHz
8.0 MHz
16.0 MHz
TABLE 10-2:
Osc Type
LP
To internal logic
XT
SLEEP
OSC2
RS
HS
see Note
PIC16CE62X
See Table 10-1 and Table 10-2 for recommended
values of C1 and C2.
Note:
Open
OSC2
Crystal
Freq
Cap. Range
C1
Cap. Range
C2
33 pF
32 kHz
33 pF
200 kHz
15 pF
15 pF
200 kHz
47-68 pF
47-68 pF
1 MHz
15 pF
15 pF
4 MHz
15 pF
15 pF
4 MHz
15 pF
15 pF
8 MHz
15-33 pF
15-33 pF
20 MHz
15-33 pF
15-33 pF
Crystals Used
Epson C-001R32.768K-A
± 20 PPM
200 kHz
STD XTL 200.000KHz
± 20 PPM
1 MHz
ECS ECS-10-13-1
± 50 PPM
4 MHz
ECS ECS-40-20-1
± 50 PPM
8 MHz
EPSON CA-301 8.000M-C
± 30 PPM
20 MHz
EPSON CA-301 20.000M-C
± 30 PPM
1.
Recommended values of C1 and C2 are identical to the
ranges tested table.
2.
Higher capacitance increases the stability of oscillator but
also increases the start-up time.
3.
Since each resonator/crystal has its own characteristics,
the user should consult the resonator/crystal manufacturer for appropriate values of external components.
4.
Rs may be required in HS mode as well as XT mode to
avoid overdriving crystals with low drive level specification.
PIC16CE62X
1998 Microchip Technology Inc.
CAPACITOR SELECTION
FOR CRYSTAL OSCILLATOR,
PIC16CE62X
32 kHz
FIGURE 10-3: EXTERNAL CLOCK INPUT
OPERATION (HS, XT OR LP
OSC CONFIGURATION)
OSC1
± 0.3%
± 0.5%
± 0.5%
± 0.5%
± 0.5%
These values are for design guidance only. See
notes at bottom of page.
A series resistor may be required for
AT strip cut crystals.
Clock from
ext. system
Panasonic EFO-A455K04B
Murata Erie CSA2.00MG
Murata Erie CSA4.00MG
Murata Erie CSA8.00MT
Murata Erie CSA16.00MX
All resonators used did not have built-in capacitors.
OSC1
C2
OSC2
68 - 100 pF
15 - 68 pF
15 - 68 pF
10 - 68 pF
10 - 22 pF
Resonators Used:
FIGURE 10-2: CRYSTAL OPERATION
(OR CERAMIC RESONATOR)
(HS, XT OR LP OSC
CONFIGURATION)
RF
OSC1
68 - 100 pF
15 - 68 pF
15 - 68 pF
10 - 68 pF
10 - 22 pF
These values are for design guidance only. See
notes at bottom of page.
In XT, LP or HS modes a crystal or ceramic resonator
is connected to the OSC1 and OSC2 pins to establish
oscillation (Figure 10-2). The PIC16CE62X) oscillator
design requires the use of a parallel cut crystal. Use of
a series cut crystal may give a frequency out of the
crystal manufacturers specifications. When in XT, LP or
HS modes, the device can have an external clock
source to drive the OSC1 pin (Figure 10-3).
XTAL
Freq
455 kHz
2.0 MHz
4.0 MHz
8.0 MHz
16.0 MHz
HS
CRYSTAL OSCILLATOR / CERAMIC
RESONATORS
C1
CERAMIC RESONATORS,
PIC16CE62X
Preliminary
DS40182A-page 51
62X.bk Page 52 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X
10.2.3
EXTERNAL CRYSTAL OSCILLATOR
CIRCUIT
10.2.4
Either a prepackaged oscillator can be used or a simple
oscillator circuit with TTL gates can be built.
Prepackaged oscillators provide a wide operating
range and better stability. A well-designed crystal
oscillator will provide good performance with TTL
gates. Two types of crystal oscillator circuits can be
used; one with series resonance, or one with parallel
resonance.
Figure 10-4 shows implementation of a parallel resonant oscillator circuit. The circuit is designed to use the
fundamental frequency of the crystal. The 74AS04
inverter performs the 180° phase shift that a parallel
oscillator requires. The 4.7 kΩ resistor provides the
negative feedback for stability. The 10 kΩ
potentiometers bias the 74AS04 in the linear region.
This could be used for external oscillator designs.
FIGURE 10-4: EXTERNAL PARALLEL
RESONANT CRYSTAL
OSCILLATOR CIRCUIT
+5V
To other
Devices
10k
74AS04
4.7k
PIC16CE62X
10k
XTAL
10k
20 pF
For timing insensitive applications the “RC” device
option offers additional cost savings. The RC oscillator
frequency is a function of the supply voltage, the
resistor (Rext) and capacitor (Cext) values, and the
operating temperature. In addition to this, the oscillator
frequency will vary from unit to unit due to normal
process parameter variation. Furthermore, the
difference in lead frame capacitance between package
types will also affect the oscillation frequency,
especially for low Cext values. The user also needs to
take into account variation due to tolerance of external
R and C components used. Figure 10-6 shows how the
R/C combination is connected to the PIC16CE62X. For
Rext values below 2.2 kΩ, the oscillator operation may
become unstable, or stop completely. For very high
Rext values (e.g., 1 MΩ), the oscillator becomes
sensitive to noise, humidity and leakage. Thus, we
recommend to keep Rext between 3 kΩ and 100 kΩ.
Although the oscillator will operate with no external
capacitor (Cext = 0 pF), we recommend using values
above 20 pF for noise and stability reasons. With no or
small external capacitance, the oscillation frequency
can vary dramatically due to changes in external
capacitances, such as PCB trace capacitance or
package lead frame capacitance.
See Section 14.0 for RC frequency variation from part
to part due to normal process variation. The variation is
larger for larger R (since leakage current variation will
affect RC frequency more for large R) and for smaller C
(since variation of input capacitance will affect RC frequency more).
CLKIN
74AS04
RC OSCILLATOR
See Section 14.0 for variation of oscillator frequency
due to VDD for given Rext/Cext values as well as
frequency variation due to operating temperature for
given R, C, and VDD values.
20 pF
Figure 10-5 shows a series resonant oscillator circuit.
This circuit is also designed to use the fundamental
frequency of the crystal. The inverter performs a 180°
phase shift in a series resonant oscillator circuit. The
330 kΩ resistors provide the negative feedback to bias
the inverters in their linear region.
FIGURE 10-5: EXTERNAL SERIES
RESONANT CRYSTAL
OSCILLATOR CIRCUIT
The oscillator frequency, divided by 4, is available on
the OSC2/CLKOUT pin, and can be used for test
purposes or to synchronize other logic (Figure 3-2 for
waveform).
FIGURE 10-6: RC OSCILLATOR MODE
VDD
PIC16CE62X
Rext
OSC1
330
To other
Devices
330
74AS04
74AS04
74AS04
Internal Clock
Cext
PIC16CE62X
CLKIN
VDD
0.1 µF
Fosc/4
OSC2/CLKOUT
XTAL
DS40182A-page 52
Preliminary
1998 Microchip Technology Inc.
62X.bk Page 53 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X
10.3
Reset
The PIC16CE62X differentiates between various kinds
of reset:
a)
b)
c)
d)
e)
f)
Power-on reset (POR)
MCLR reset during normal operation
MCLR reset during SLEEP
WDT reset (normal operation)
WDT wake-up (SLEEP)
Brown-out Reset (BOR)
state” on Power-on reset, on MCLR or WDT reset and
on MCLR reset during SLEEP. They are not affected by
a WDT wake-up, since this is viewed as the resumption
of normal operation. TO and PD bits are set or cleared
differently in different reset situations as indicated in
Table 10-4. These bits are used in software to determine the nature of the reset. See Table 10-6 for a full
description of reset states of all registers.
A simplified block diagram of the on-chip reset circuit is
shown in Figure 10-7.
Some registers are not affected in any reset condition;
their status is unknown on POR and unchanged in any
other reset. Most other registers are reset to a “reset
The MCLR reset path has a noise filter to detect and
ignore small pulses. See Table 13-6 for pulse width
specification.
FIGURE 10-7: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External
Reset
MCLR/
VPP Pin
WDT
Module
SLEEP
WDT
Time-out
Reset
VDD rise
detect
Power-on Reset
VDD
Brown-out
Reset
S
BODEN
OST/PWRT
OST
Chip_Reset
10-bit Ripple-counter
OSC1/
CLKIN
Pin
On-chip(1)
RC OSC
R
Q
PWRT
10-bit Ripple-counter
Enable PWRT
See Table 10-3 for time-out situations.
Enable OST
Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.
1998 Microchip Technology Inc.
Preliminary
DS40182A-page 53
62X.bk Page 54 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X
10.4
10.4.1
Power-on Reset (POR), Power-up
Timer (PWRT), Oscillator Start-up
Timer (OST) and Brown-out Reset
(BOR)
disable (if set) or enable (if cleared or programmed) the
Power-up Timer. The Power-up Timer should always be
enabled when Brown-out Reset is enabled.
The Power-Up Time delay will vary from chip to chip
and due to VDD, temperature and process variation.
See DC parameters for details.
POWER-ON RESET (POR)
The on-chip POR circuit holds the chip in reset until
VDD has reached a high enough level for proper operation. To take advantage of the POR, just tie the MCLR
pin directly (or through a resistor) to VDD. This will
eliminate external RC components usually needed to
create Power-on Reset. A maximum rise time for VDD
is required. See Electrical Specifications for details.
10.4.3
The Oscillator Start-Up Timer (OST) provides a 1024
oscillator cycle (from OSC1 input) delay after the
PWRT delay is over. This ensures that the crystal
oscillator or resonator has started and stabilized.
The OST time-out is invoked only for XT, LP and HS
modes and only on power-on reset or wake-up from
SLEEP.
The POR circuit does not produce internal reset when
VDD declines.
When the device starts normal operation (exits the
reset condition), device operating parameters (voltage,
frequency, temperature, etc.) must be met to ensure
operation. If these conditions are not met, the device
must be held in reset until the operating conditions are
met.
10.4.4
BROWN-OUT RESET (BOR)
The PIC16CE62X members have on-chip Brown-out
Reset circuitry. A configuration bit, BODEN, can disable (if clear/programmed) or enable (if set) the
Brown-out Reset circuitry. If VDD falls below 4.0V (refer
to BVDD parameter D005) for greater than parameter
(TBOR) in Table 13-6, the brown-out situation will reset
the chip. A reset is not guaranteed to occur if VDD falls
below 4.0V for less than parameter (TBOR). The chip
will remain in Brown-out Reset until VDD rises above
BVDD. The Power-up Timer will now be invoked and will
keep the chip in reset an additional 72 ms. If VDD drops
below BVDD while the Power-up Timer is running, the
chip will go back into a Brown-out Reset and the
Power-up Timer will be initialized. Once VDD rises
above BVDD, the Power-Up Timer will execute a 72 ms
reset. The Power-up Timer should always be enabled
when Brown-out Reset is enabled. Figure 10-8 shows
typical Brown-out situations.
For additional information, refer to Application Note
AN607 “Power-up Trouble Shooting”.
10.4.2
OSCILLATOR START-UP TIMER (OST)
POWER-UP TIMER (PWRT)
The Power-up Timer provides a fixed 72 ms (nominal)
time-out on power-up only, from POR or Brown-out
Reset. The Power-up Timer operates on an internal RC
oscillator. The chip is kept in reset as long as PWRT is
active. The PWRT delay allows the VDD to rise to an
acceptable level. A configuration bit, PWRTE can
FIGURE 10-8: BROWN-OUT SITUATIONS
VDD
Internal
Reset
BVDD
72 ms
VDD
Internal
Reset
BVDD
<72 ms
72 ms
VDD
Internal
Reset
DS40182A-page 54
BVDD
72 ms
Preliminary
1998 Microchip Technology Inc.
62X.bk Page 55 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X
10.4.5
10.4.6
TIME-OUT SEQUENCE
On power-up the time-out sequence is as follows: First
PWRT time-out is invoked after POR has expired. Then
OST is activated. The total time-out will vary based on
oscillator configuration and PWRTE bit status. For
example, in RC mode with PWRTE bit erased (PWRT
disabled), there will be no time-out at all. Figure 10-9,
Figure 10-10 and Figure 10-11 depict time-out
sequences.
The power control/status register, PCON (address
8Eh) has two bits.
Bit0 is BO (Brown-out). BO is unknown on
power-on-reset. It must then be set by the user and
checked on subsequent resets to see if BO = 0
indicating that a brown-out has occurred. The BO
status bit is a don’t care and is not necessarily
predictable if the brown-out circuit is disabled (by
setting BODEN bit = 0 in the Configuration word).
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the time-outs will expire. Then
bringing MCLR high will begin execution immediately
(see Figure 10-10). This is useful for testing purposes
or to synchronize more than one PICmicro device operating in parallel.
Bit1 is POR (Power-on-reset). It is a ‘0’ on
power-on-reset and unaffected otherwise. The user
must write a ‘1’ to this bit following a power-on-reset.
On a subsequent reset if POR is ‘0’, it will indicate that
a power-on-reset must have occurred (VDD may have
gone too low).
Table 10-5 shows the reset conditions for some special
registers, while Table 10-6 shows the reset conditions
for all the registers.
TABLE 10-3:
POWER CONTROL (PCON)/STATUS
REGISTER
TIME-OUT IN VARIOUS SITUATIONS
Power-up
Brown-out Reset
Wake-up
from SLEEP
1024 TOSC
72 ms + 1024 TOSC
1024 TOSC
—
72 ms
—
Oscillator Configuration
PWRTE = 0
PWRTE = 1
XT, HS, LP
72 ms + 1024 TOSC
RC
72 ms
TABLE 10-4:
STATUS/PCON BITS AND THEIR SIGNIFICANCE
POR
BOR
TO
PD
0
X
1
1
Power-on-reset
0
X
0
X
Illegal, TO is set on POR
0
X
X
0
Illegal, PD is set on POR
1
0
X
X
Brown-out Reset
1
1
0
1
WDT Reset
1
1
0
0
WDT Wake-up
1
1
u
u
MCLR reset during normal operation
1
1
1
0
MCLR reset during SLEEP
1998 Microchip Technology Inc.
Preliminary
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PIC16CE62X
TABLE 10-5:
INITIALIZATION CONDITION FOR SPECIAL REGISTERS
Program
Counter
STATUS
Register
PCON
Register
000h
0001 1xxx
---- --0x
MCLR reset during normal operation
000h
000u uuuu
---- --uu
MCLR reset during SLEEP
000h
0001 0uuu
---- --uu
Condition
Power-on Reset
WDT reset
000h
0000 1uuu
---- --uu
PC + 1
uuu0 0uuu
---- --uu
000h
0001 1uuu
---- --u0
PC + 1(1)
uuu1 0uuu
---- --uu
WDT Wake-up
Brown-out Reset
Interrupt Wake-up from SLEEP
Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’.
Note 1: When the wake-up is due to an interrupt and global enable bit, GIE is set, the PC is loaded with the interrupt vector
(0004h) after execution of PC+1.
TABLE 10-6:
INITIALIZATION CONDITION FOR REGISTERS
Register
Address
W
-
INDF
00h
TMR0
Power-on Reset
• MCLR Reset during
normal operation
• MCLR Reset during
SLEEP
• WDT Reset
• Brown-out Reset (1)
• Wake up from SLEEP
through interrupt
• Wake up from SLEEP
through WDT time-out
01h
xxxx xxxx
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
PCL
02h
0000 0000
0000 0000
PC + 1(3)
STATUS
03h
FSR
04h
PORTA
05h
PORTB
06h
CMCON
1Fh
PCLATH
0Ah
0001
xxxx
---x
xxxx
00----0
000q quuu(4)
uuuu uuuu
---u uuuu
uuuu uuuu
00-- 0000
---0 0000
uuuq quuu(4)
uuuu uuuu
---u uuuu
uuuu uuuu
uu-- uuuu
---u uuuu
INTCON
0Bh
0000 000x
0000 000x
uuuu uuuu(2)
PIR1
0Ch
OPTION
81h
TRISA
85h
-0-- ---1111 1111
---1 1111
-0-- ---1111 1111
---1 1111
-u-- ----(2)
uuuu uuuu
---u uuuu
TRISB
86h
PIE1
8Ch
1111 1111
-0-- ----
1111 1111
-0-- ----
uuuu uuuu
-u-- ----
PCON
8Eh
---- --0x
---- --uq(1)
---- --uu
EEINTF
90h
uuuu u111
uuuu u111
uuuu u111
1xxx
xxxx
xxxx
xxxx
0000
0000
000- 0000
000- 0000
uuu- uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’,q = value depends on condition.
VRCON
9Fh
Note 1: If VDD goes too low, Power-on Reset will be activated and registers will be affected differently.
2: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up).
3: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt
vector (0004h).
4: See Table 10-5 for reset value for specific condition.
DS40182A-page 56
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PIC16CE62X
FIGURE 10-9: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 10-10: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 10-11: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
1998 Microchip Technology Inc.
Preliminary
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PIC16CE62X
FIGURE 10-12: EXTERNAL POWER-ON
RESET CIRCUIT (FOR SLOW
VDD POWER-UP)
FIGURE 10-13: EXTERNAL BROWN-OUT
PROTECTION CIRCUIT 1
VDD
D
VDD
33k
VDD
VDD
10k
MCLR
R
40k
R1
PIC16CE62X
MCLR
C
PIC16CE62X
Note 1: External power-on reset circuit is required
only if VDD power-up slope is too slow.
The diode D helps discharge the capacitor quickly when VDD powers down.
2: < 40 kΩ is recommended to make sure
that voltage drop across R does not violate the device’s electrical specification.
3: R1 = 100Ω to 1 kΩ will limit any current
flowing into MCLR from external capacitor C in the event of MCLR/VPP pin breakdown due to Electrostatic Discharge
(ESD) or Electrical Overstress (EOS).
Note 1: This circuit will activate reset when VDD
goes below (Vz + 0.7V) where
Vz = Zener voltage.
2: Internal Brown-out Reset circuitry
should be disabled when using this circuit.
FIGURE 10-14: EXTERNAL BROWN-OUT
PROTECTION CIRCUIT 2
VDD
VDD
R1
Q1
MCLR
R2
40k
PIC16CE62X
Note 1: This brown-out circuit is less expensive,
albeit less accurate. Transistor Q1 turns
off when VDD is below a certain level
such that:
R1
VDD x
= 0.7 V
R1 + R2
2: Internal brown-out detection should be
disabled when using this circuit.
3: Resistors should be adjusted for the
characteristics of the transistor.
DS40182A-page 58
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PIC16CE62X
10.5
Interrupts
the interrupt can be determined by polling the interrupt
flag bits. The interrupt flag bit(s) must be cleared in software before re-enabling interrupts to avoid RB0/INT
recursive interrupts.
The PIC16CE62X has 4 sources of interrupt:
•
•
•
•
External interrupt RB0/INT
TMR0 overflow interrupt
PortB change interrupts (pins RB7:RB4)
Comparator interrupt
The interrupt control register (INTCON) records
individual interrupt requests in flag bits. It also has
individual and global interrupt enable bits.
A global interrupt enable bit, GIE (INTCON<7>)
enables (if set) all un-masked interrupts or disables (if
cleared) all interrupts. Individual interrupts can be
disabled through their corresponding enable bits in
INTCON register. GIE is cleared on reset.
For external interrupt events, such as the INT pin or
PORTB change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends when the interrupt event occurs
(Figure 10-16). The latency is the same for one or two
cycle instructions. Once in the interrupt service routine
the source(s) of the interrupt can be determined by
polling the interrupt flag bits. The interrupt flag bit(s)
must be cleared in software before re-enabling interrupts to avoid multiple interrupt requests. Individual
interrupt flag bits are set regardless of the status of
their corresponding mask bit or the GIE bit.
The “return from interrupt” instruction, RETFIE, exits
interrupt routine as well as sets the GIE bit, which
re-enable RB0/INT interrupts.
Note 1:
Individual interrupt flag bits are set
regardless of the status of their
corresponding mask bit or the GIE bit.
The INT pin interrupt, the RB port change interrupt and
the TMR0 overflow interrupt flags are contained in the
INTCON register.
2:
When an instruction that clears the GIE
bit is executed, any interrupts that were
pending for execution in the next cycle
are ignored. The CPU will execute a
NOP in the cycle immediately following
the instruction which clears the GIE bit.
The interrupts which were ignored are
still pending to be serviced when the GIE
bit is set again.
The peripheral interrupt flag is contained in the special
register PIR1. The corresponding interrupt enable bit is
contained in special registers PIE1.
When an interrupt is responded to, the GIE is cleared
to disable any further interrupt, the return address is
pushed into the stack and the PC is loaded with 0004h.
Once in the interrupt service routine the source(s) of
FIGURE 10-15: INTERRUPT LOGIC
Wake-up
(If in SLEEP mode)
T0IF
T0IE
INTF
INTE
Interrupt
to CPU
RBIF
RBIE
CMIF
CMIE
PEIE
GIE
1998 Microchip Technology Inc.
Preliminary
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PIC16CE62X
10.5.1
10.5.3
RB0/INT INTERRUPT
An input change on PORTB <7:4> sets the RBIF
(INTCON<0>) bit. The interrupt can be enabled/disabled by setting/clearing the RBIE (INTCON<4>) bit.
For operation of PORTB (Section 5.2).
External interrupt on RB0/INT pin is edge triggered:
either rising if INTEDG bit (OPTION<6>) is set, or falling, if INTEDG bit is clear. When a valid edge appears
on the RB0/INT pin, the INTF bit (INTCON<1>) is set.
This interrupt can be disabled by clearing the INTE
control bit (INTCON<4>). The INTF bit must be cleared
in software in the interrupt service routine before
re-enabling this interrupt. The RB0/INT interrupt can
wake-up the processor from SLEEP, if the INTE bit was
set prior to going into SLEEP. The status of the GIE bit
decides whether or not the processor branches to the
interrupt vector following wake-up. See Section 10.8 for
details on SLEEP and Figure 10-19 for timing of
wake-up from SLEEP through RB0/INT interrupt.
10.5.2
PORTB INTERRUPT
Note:
10.5.4
If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the RBIF interrupt flag may not get set.
COMPARATOR INTERRUPT
See Section 8.6 for complete description of comparator
interrupts.
TMR0 INTERRUPT
An overflow (FFh → 00h) in the TMR0 register will
set the T0IF (INTCON<2>) bit. The interrupt can
be enabled/disabled by setting/clearing T0IE
(INTCON<5>) bit. For operation of the Timer0 module,
see Section 7.0.
FIGURE 10-16: INT PIN INTERRUPT TIMING
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
CLKOUT 3
4
INT pin
1
1
INTF flag
(INTCON<1>)
Interrupt Latency 2
5
GIE bit
(INTCON<7>)
INSTRUCTION FLOW
PC
PC
Instruction
fetched
Inst (PC)
Instruction
executed
Inst (PC-1)
Inst (PC+1)
Inst (PC)
0004h
PC+1
PC+1
—
Dummy Cycle
0005h
Inst (0004h)
Inst (0005h)
Dummy Cycle
Inst (0004h)
Note 1: INTF flag is sampled here (every Q1).
2: Interrupt latency = 3-4 Tcy where Tcy = instruction cycle time.
Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
3: CLKOUT is available only in RC oscillator mode.
4: For minimum width of INT pulse, refer to AC specs.
5: INTF is enabled to be set anytime during the Q4-Q1 cycles.
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PIC16CE62X
10.6
Context Saving During Interrupts
10.7
During an interrupt, only the return PC value is saved
on the stack. Typically, users may wish to save key registers during an interrupt e.g. W register and STATUS
register. This will have to be implemented in software.
Example 10-1 stores and restores the STATUS and W
registers. The user register, W_TEMP, must be defined
in both banks and must be defined at the same offset
from the bank base address (i.e., W_TEMP is defined
at 0x70 in Bank 0 and it must also be defined at 0xF0
in Bank 1). The user register, STATUS_TEMP, must be
defined in Bank 0. The Example 10-1:
•
•
•
•
Stores the W register
Stores the STATUS register in Bank 0
Executes the ISR code
Restores the STATUS (and bank select bit
register)
• Restores the W register
MOVWF
W_TEMP
;copy W to temp register,
;could be in either bank
SWAPF
STATUS,W
;swap status to be saved into W
BCF
STATUS,RP0
;change to bank 0 regardless
;of current bank
MOVWF
STATUS_TEMP
;save status to bank 0
;register
The WDT has a nominal time-out period of 18 ms, (with
no prescaler). The time-out periods vary with temperature, VDD and process variations from part to part (see
DC specs). If longer time-out periods are desired, a
prescaler with a division ratio of up to 1:128 can be
assigned to the WDT under software control by writing
to the OPTION register. Thus, time-out periods up to
2.3 seconds can be realized.
The CLRWDT and SLEEP instructions clear the WDT
and the postscaler, if assigned to the WDT, and prevent
it from timing out and generating a device RESET.
10.7.2
(ISR)
:
SWAPF
STATUS_TEMP,W
;swap STATUS_TEMP register
;into W, sets bank to original
;state
MOVWF
STATUS
;move W into STATUS register
SWAPF
W_TEMP,F
;swap W_TEMP
SWAPF
W_TEMP,W
;swap W_TEMP into W
1998 Microchip Technology Inc.
WDT PERIOD
The TO bit in the STATUS register will be cleared upon
a Watchdog Timer time-out.
:
:
The watchdog timer is a free running on-chip RC oscillator which does not require any external components.
This RC oscillator is separate from the RC oscillator of
the CLKIN pin. That means that the WDT will run, even
if the clock on the OSC1 and OSC2 pins of the device
has been stopped, for example, by execution of a
SLEEP instruction. During normal operation, a WDT
time-out generates a device RESET. If the device is in
SLEEP mode, a WDT time-out causes the device to
wake-up and continue with normal operation. The WDT
can be permanently disabled by programming the configuration bit WDTE as clear (Section 10.1).
10.7.1
EXAMPLE 10-1: SAVING THE STATUS AND
W REGISTERS IN RAM
Watchdog Timer (WDT)
WDT PROGRAMMING CONSIDERATIONS
It should also be taken in account that under worst case
conditions (VDD = Min., Temperature = Max., max.
WDT prescaler) it may take several seconds before a
WDT time-out occurs.
Preliminary
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PIC16CE62X
FIGURE 10-17: WATCHDOG TIMER BLOCK DIAGRAM
From TMR0 Clock Source
(Figure 7-6)
0
Watchdog
Timer
1
•
M
U
X
Postscaler
8
8 - to -1 MUX
PS<2:0>
•
To TMR0 (Figure 7-6)
PSA
WDT
Enable Bit
1
0
MUX
PSA
WDT
Time-out
Note: T0SE, T0CS, PSA, PS0-PS2 are bits in the OPTION register.
FIGURE 10-18: SUMMARY OF WATCHDOG TIMER REGISTERS
Address
Name
2007h
Config. bits
81h
OPTION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
---
BODEN
CP1
CP0
PWRTE
WDTE
FOSC1
FOSC0
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
Legend: Shaded cells are not used by the Watchdog Timer.
Note:
_ = Unimplemented location, read as “0”
+ = Reserved for future use
DS40182A-page 62
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PIC16CE62X
10.8
Power-Down Mode (SLEEP)
The Power-down mode is entered by executing a
SLEEP instruction.
If enabled, the Watchdog Timer will be cleared but
keeps running, the PD bit in the STATUS register is
cleared, the TO bit is set, and the oscillator driver is
turned off. The I/O ports maintain the status they had,
before SLEEP was executed (driving high, low, or
hi-impedance).
For lowest current consumption in this mode, all I/O
pins should be either at VDD, or VSS, with no external
circuitry drawing current from the I/O pin and the comparators and VREF should be disabled. I/O pins that are
hi-impedance inputs should be pulled high or low externally to avoid switching currents caused by floating
inputs. The T0CKI input should also be at VDD or VSS
for lowest current consumption. The contribution from
on chip pull-ups on PORTB should be considered.
The first event will cause a device reset. The two latter
events are considered a continuation of program execution. The TO and PD bits in the STATUS register can
be used to determine the cause of device reset. PD
bit, which is set on power-up is cleared when SLEEP is
invoked. TO bit is cleared if WDT Wake-up occurred.
When the SLEEP instruction is being executed, the
next instruction (PC + 1) is pre-fetched. For the device
to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled). Wake-up
is regardless of the state of the GIE bit. If the GIE bit is
clear (disabled), the device continues execution at the
instruction after the SLEEP instruction. If the GIE bit is
set (enabled), the device executes the instruction after
the SLEEP instruction and then branches to the interrupt address (0004h). In cases where the execution of
the instruction following SLEEP is not desirable, the
user should have an NOP after the SLEEP instruction.
Note:
The MCLR pin must be at a logic high level (VIHMC).
Note:
10.8.1
It should be noted that a RESET generated
by a WDT time-out does not drive MCLR
pin low.
WAKE-UP FROM SLEEP
The device can wake-up from SLEEP through one of
the following events:
1.
2.
3.
If the global interrupts are disabled (GIE is
cleared), but any interrupt source has both
its interrupt enable bit and the corresponding interrupt flag bits set, the device will
immediately wakeup from sleep. The sleep
instruction is completely executed.
The WDT is cleared when the device wakes-up from
sleep, regardless of the source of wake-up.
External reset input on MCLR pin
Watchdog Timer Wake-up (if WDT was enabled)
Interrupt from RB0/INT pin, RB Port change, or
the Peripheral Interrupt (Comparator).
FIGURE 10-19: WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
Q1
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
Q1 Q2 Q3
Q4
OSC1
TOST(2)
CLKOUT(4)
INT pin
INTF flag
(INTCON<1>)
Interrupt Latency
(Note 2)
GIE bit
(INTCON<7>)
Processor in
SLEEP
INSTRUCTION FLOW
PC
PC
Instruction
fetched
Inst(PC) = SLEEP
Instruction
executed
Inst(PC - 1)
Note 1:
2:
3:
4:
PC+1
PC+2
PC+2
Inst(PC + 1)
Inst(PC + 2)
SLEEP
Inst(PC + 1)
PC + 2
Dummy cycle
0004h
0005h
Inst(0004h)
Inst(0005h)
Dummy cycle
Inst(0004h)
XT, HS or LP oscillator mode assumed.
TOST = 1024TOSC (drawing not to scale) This delay will not be there for RC osc mode.
GIE = '1' assumed. In this case after wake- up, the processor jumps to the interrupt routine. If GIE = '0', execution will continue in-line.
CLKOUT is not available in these osc modes, but shown here for timing reference.
1998 Microchip Technology Inc.
Preliminary
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PIC16CE62X
10.9
Code Protection
10.11
If the code protection bit(s) have not been
programmed, the on-chip program memory can be
read out for verification purposes.
Note:
10.10
Microchip does not recommend code
protecting windowed devices.
ID Locations
Four memory locations (2000h-2003h) are designated
as ID locations where the user can store checksum or
other code-identification numbers. These locations are
not accessible during normal execution but are
readable and writable during program/verify. Only the
least significant 4 bits of the ID locations are used.
In-Circuit Serial Programming
The PIC16CE62X microcontrollers can be serially
programmed while in the end application circuit. This is
simply done with two lines for clock and data, and three
other lines for power, ground, and the programming
voltage. This allows customers to manufacture boards
with unprogrammed devices, and then program the
microcontroller just before shipping the product. This
also allows the most recent firmware or a custom
firmware to be programmed.
The device is placed into a program/verify mode by
holding the RB6 and RB7 pins low while raising the
MCLR (VPP) pin from VIL to VIHH (see programming
specification). RB6 becomes the programming clock
and RB7 becomes the programming data. Both RB6
and RB7 are Schmitt Trigger inputs in this mode.
After reset, to place the device into programming/verify
mode, the program counter (PC) is at location 00h. A
6-bit command is then supplied to the device.
Depending on the command, 14-bits of program data
are then supplied to or from the device, depending if the
command was a load or a read. For complete details of
serial
programming,
please
refer
to
the
PIC16C6X/7X/9XX Programming Specifications (Literature #DS30228).
A typical in-circuit serial programming connection is
shown in Figure 10-20.
FIGURE 10-20: TYPICAL IN-CIRCUIT SERIAL
PROGRAMMING
CONNECTION
External
Connector
Signals
To Normal
Connections
PIC16CE62X
+5V
VDD
0V
VSS
VPP
MCLR/VPP
CLK
RB6
Data I/O
RB7
VDD
To Normal
Connections
DS40182A-page 64
Preliminary
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PIC16CE62X
11.0
INSTRUCTION SET SUMMARY
Each PIC16CE62X instruction is a 14-bit word divided
into an OPCODE which specifies the instruction type
and one or more operands which further specify the
operation of the instruction. The PIC16CE62X instruction set summary in Table 11-2 lists byte-oriented,
bit-oriented, and literal and control operations.
Table 11-1 shows the opcode field descriptions.
For byte-oriented instructions, 'f' represents a file
register designator and 'd' represents a destination
designator. The file register designator specifies which
file register is to be used by the instruction.
The destination designator specifies where the result of
the operation is to be placed. If 'd' is zero, the result is
placed in the W register. If 'd' is one, the result is placed
in the file register specified in the instruction.
For bit-oriented instructions, 'b' represents a bit field
designator which selects the number of the bit affected
by the operation, while 'f' represents the number of the
file in which the bit is located.
For literal and control operations, 'k' represents an
eight or eleven bit constant or literal value.
TABLE 11-1:
OPCODE FIELD
DESCRIPTIONS
Field
The instruction set is highly orthogonal and is grouped
into three basic categories:
• Byte-oriented operations
• Bit-oriented operations
• Literal and control operations
All instructions are executed within one single
instruction cycle, unless a conditional test is true or the
program counter is changed as a result of an
instruction. In this case, the execution takes two
instruction cycles with the second cycle executed as a
NOP. One instruction cycle consists of four oscillator
periods. Thus, for an oscillator frequency of 4 MHz, the
normal instruction execution time is 1 µs. If a
conditional test is true or the program counter is
changed as a result of an instruction, the instruction
execution time is 2 µs.
Table 11-1 lists the instructions recognized by the
MPASM assembler.
Figure 11-1 shows the three general formats that the
instructions can have.
Note:
To maintain upward compatibility with
future PICmicro™ products, do not use the
OPTION and TRIS instructions.
All examples use the following format to represent a
hexadecimal number:
Description
0xhh
f
W
Register file address (0x00 to 0x7F)
Working register (accumulator)
where h signifies a hexadecimal digit.
b
k
Bit address within an 8-bit file register
Literal field, constant data or label
FIGURE 11-1: GENERAL FORMAT FOR
INSTRUCTIONS
x
Don't care location (= 0 or 1)
The assembler will generate code with x = 0. It is the
recommended form of use for compatibility with all
Microchip software tools.
Destination select; d = 0: store result in W,
d = 1: store result in file register f.
Default is d = 1
d
label Label name
TOS Top of Stack
PC Program Counter
GIE
[ ]
( )
→
<>
∈
0
d = 0 for destination W
d = 1 for destination f
f = 7-bit file register address
Bit-oriented file register operations
13
10 9
7 6
OPCODE
b (BIT #)
f (FILE #)
PCLATH Program Counter High Latch
WDT
TO
PD
dest
Byte-oriented file register operations
13
8 7 6
OPCODE
d
f (FILE #)
Global Interrupt Enable bit
0
b = 3-bit bit address
f = 7-bit file register address
Watchdog Timer/Counter
Time-out bit
Power-down bit
Destination either the W register or the specified
register file location
Options
Literal and control operations
General
13
Contents
8
7
OPCODE
Assigned to
0
k (literal)
k = 8-bit immediate value
Register bit field
In the set of
CALL and GOTO instructions only
italics User defined term (font is courier)
13
11
OPCODE
10
0
k (literal)
k = 11-bit immediate value
1998 Microchip Technology Inc.
Preliminary
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PIC16CE62X
TABLE 11-2:
PIC16CE62X INSTRUCTION SET
Mnemonic,
Operands
Description
Cycles
14-Bit Opcode
MSb
LSb
Status
Affected
Notes
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
DECFSZ
INCF
INCFSZ
IORWF
MOVF
MOVWF
NOP
RLF
RRF
SUBWF
SWAPF
XORWF
f, d
f, d
f
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
f, d
f, d
f, d
f, d
f, d
Add W and f
AND W with f
Clear f
Clear W
Complement f
Decrement f
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
Move W to f
No Operation
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Swap nibbles in f
Exclusive OR W with f
1
1
1
1
1
1
1(2)
1
1(2)
1
1
1
1
1
1
1
1
1
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
0111
0101
0001
0001
1001
0011
1011
1010
1111
0100
1000
0000
0000
1101
1100
0010
1110
0110
dfff
dfff
lfff
0xxx
dfff
dfff
dfff
dfff
dfff
dfff
dfff
lfff
0xx0
dfff
dfff
dfff
dfff
dfff
ffff
ffff
ffff
xxxx
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
0000
ffff
ffff
ffff
ffff
ffff
1
1
1 (2)
1 (2)
01
01
01
01
00bb
01bb
10bb
11bb
bfff
bfff
bfff
bfff
ffff
ffff
ffff
ffff
1
1
2
1
2
1
1
2
2
2
1
1
1
11
11
10
00
10
11
11
00
11
00
00
11
11
111x
1001
0kkk
0000
1kkk
1000
00xx
0000
01xx
0000
0000
110x
1010
kkkk
kkkk
kkkk
0110
kkkk
kkkk
kkkk
0000
kkkk
0000
0110
kkkk
kkkk
kkkk
kkkk
kkkk
0100
kkkk
kkkk
kkkk
1001
kkkk
1000
0011
kkkk
kkkk
C,DC,Z
Z
Z
Z
Z
Z
Z
Z
Z
C
C
C,DC,Z
Z
1,2
1,2
2
1,2
1,2
1,2,3
1,2
1,2,3
1,2
1,2
1,2
1,2
1,2
1,2
1,2
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
f, b
f, b
f, b
f, b
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
1,2
1,2
3
3
LITERAL AND CONTROL OPERATIONS
ADDLW
ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLW
RETFIE
RETLW
RETURN
SLEEP
SUBLW
XORLW
k
k
k
k
k
k
k
k
k
Add literal and W
AND literal with W
Call subroutine
Clear Watchdog Timer
Go to address
Inclusive OR literal with W
Move literal to W
Return from interrupt
Return with literal in W
Return from Subroutine
Go into standby mode
Subtract W from literal
Exclusive OR literal with W
C,DC,Z
Z
TO,PD
Z
TO,PD
C,DC,Z
Z
Note 1: When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present
on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external
device, the data will be written back with a '0'.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned
to the Timer0 Module.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
DS40182A-page 66
Preliminary
1998 Microchip Technology Inc.
62X.bk Page 67 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X
11.1
Instruction Descriptions
ADDLW
Add Literal and W
Syntax:
[ label ] ADDLW
Operands:
ANDLW
AND Literal with W
Syntax:
[ label ] ANDLW
0 ≤ k ≤ 255
Operands:
0 ≤ k ≤ 255
Operation:
(W) + k → (W)
Operation:
(W) .AND. (k) → (W)
Status Affected:
C, DC, Z
Status Affected:
Z
Encoding:
11
k
111x
kkkk
kkkk
Encoding:
11
k
1001
kkkk
kkkk
Description:
The contents of the W register are
added to the eight bit literal 'k' and the
result is placed in the W register.
Description:
The contents of W register are
AND’ed with the eight bit literal 'k'. The
result is placed in the W register.
Words:
1
Words:
1
Cycles:
1
Cycles:
1
Example
ADDLW
Example
0x15
=
W
0x10
=
ADDWF
Add W and f
Syntax:
[ label ] ADDWF
Operands:
=
0xA3
After Instruction
After Instruction
W
0x5F
Before Instruction
Before Instruction
W
ANDLW
W
0x25
ANDWF
=
0x03
AND W with f
Syntax:
[ label ] ANDWF
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
(W) + (f) → (dest)
Operation:
(W) .AND. (f) → (dest)
Status Affected:
C, DC, Z
Status Affected:
Z
Encoding:
Description:
00
f,d
0111
dfff
ffff
Encoding:
00
Add the contents of the W register
with register 'f'. If 'd' is 0 the result is
stored in the W register. If 'd' is 1 the
result is stored back in register 'f'.
Description:
Words:
1
Words:
1
Cycles:
1
Cycles:
1
Example
ADDWF
FSR, 0
Example
Before Instruction
W =
FSR =
1998 Microchip Technology Inc.
0101
dfff
ffff
AND the W register with register 'f'. If
'd' is 0 the result is stored in the W
register. If 'd' is 1 the result is stored
back in register 'f'.
ANDWF
FSR, 1
Before Instruction
0x17
0xC2
W =
FSR =
After Instruction
W =
FSR =
f,d
0x17
0xC2
After Instruction
0xD9
0xC2
W =
FSR =
Preliminary
0x17
0x02
DS40182A-page 67
62X.bk Page 68 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X
BCF
Bit Clear f
Syntax:
[ label ] BCF
BTFSC
Bit Test, Skip if Clear
Syntax:
Operands:
[ label ] BTFSC f,b
0 ≤ f ≤ 127
0≤b≤7
Operands:
0 ≤ f ≤ 127
0≤b≤7
Operation:
0 → (f<b>)
Operation:
skip if (f<b>) = 0
Status Affected:
None
Status Affected:
None
Encoding:
01
f,b
00bb
bfff
ffff
Description:
Bit 'b' in register 'f' is cleared.
Words:
1
Cycles:
1
Example
BCF
Encoding:
Description:
FLAG_REG, 7
Before Instruction
FLAG_REG = 0xC7
After Instruction
FLAG_REG = 0x47
01
Words:
1
Cycles:
1(2)
Example
10bb
bfff
ffff
If bit 'b' in register 'f' is '0' then the next
instruction is skipped.
If bit 'b' is '0' then the next instruction
fetched during the current instruction
execution is discarded, and a NOP is
executed instead, making this a
two-cycle instruction.
HERE
FALSE
TRUE
BTFSC
GOTO
•
•
•
FLAG,1
PROCESS_CODE
Before Instruction
PC =
address HERE
After Instruction
if FLAG<1> = 0,
PC =
address TRUE
if FLAG<1>=1,
PC =
address FALSE
BSF
Bit Set f
Syntax:
[ label ] BSF
Operands:
0 ≤ f ≤ 127
0≤b≤7
Operation:
1 → (f<b>)
Status Affected:
None
Encoding:
Description:
01
01bb
bfff
ffff
Bit 'b' in register 'f' is set.
Words:
1
Cycles:
1
Example
f,b
BSF
FLAG_REG,
7
Before Instruction
FLAG_REG = 0x0A
After Instruction
FLAG_REG = 0x8A
DS40182A-page 68
Preliminary
1998 Microchip Technology Inc.
62X.bk Page 69 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X
BTFSS
Bit Test f, Skip if Set
CLRF
Clear f
Syntax:
[ label ] BTFSS f,b
Syntax:
[ label ] CLRF
Operands:
0 ≤ f ≤ 127
0≤b<7
Operands:
0 ≤ f ≤ 127
Operation:
Operation:
skip if (f<b>) = 1
00h → (f)
1→Z
Status Affected:
None
Status Affected:
Z
Encoding:
Description:
01
11bb
bfff
ffff
If bit 'b' in register 'f' is '1' then the next
instruction is skipped.
If bit 'b' is '1', then the next instruction
fetched during the current instruction
execution, is discarded and a NOP is
executed instead, making this a
two-cycle instruction.
Words:
1
Cycles:
1(2)
Example
HERE
FALSE
TRUE
Encoding:
Description:
00
f
0001
1fff
ffff
The contents of register 'f' are cleared
and the Z bit is set.
Words:
1
Cycles:
1
Example
CLRF
FLAG_REG
Before Instruction
FLAG_REG
BTFSS
GOTO
•
•
•
=
0x5A
=
=
0x00
1
After Instruction
FLAG,1
PROCESS_CODE
FLAG_REG
Z
Before Instruction
PC =
address HERE
After Instruction
if FLAG<1> = 0,
PC =
address FALSE
if FLAG<1> = 1,
PC =
address TRUE
CALL
Call Subroutine
CLRW
Syntax:
[ label ] CALL k
Syntax:
[ label ] CLRW
Operands:
0 ≤ k ≤ 2047
Operands:
None
Operation:
(PC)+ 1→ TOS,
k → PC<10:0>,
(PCLATH<4:3>) → PC<12:11>
Operation:
00h → (W)
1→Z
Status Affected:
Z
Status Affected:
None
Encoding:
Encoding:
Description:
10
kkkk
kkkk
Call Subroutine. First, return address
(PC+1) is pushed onto the stack. The
eleven bit immediate address is loaded
into PC bits <10:0>. The upper bits of
the PC are loaded from PCLATH.
CALL is a two-cycle instruction.
Words:
1
Cycles:
2
Example
0kkk
Description:
Clear W
00
Words:
1
Cycles:
1
Example
0001
0xxx
xxxx
W register is cleared. Zero bit (Z) is
set.
CLRW
Before Instruction
W
HERE
CALL
=
0x5A
After Instruction
THERE
W
Z
Before Instruction
=
=
0x00
1
PC = Address HERE
After Instruction
PC = Address THERE
TOS = Address HERE+1
1998 Microchip Technology Inc.
Preliminary
DS40182A-page 69
62X.bk Page 70 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X
CLRWDT
Clear Watchdog Timer
DECF
Syntax:
[ label ] CLRWDT
Syntax:
[ label ] DECF f,d
Operands:
None
Operands:
Operation:
00h → WDT
0 → WDT prescaler,
1 → TO
1 → PD
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
(f) - 1 → (dest)
Status Affected:
Z
Status Affected:
Description:
Encoding:
TO, PD
Encoding:
00
0000
0110
0100
CLRWDT instruction resets the
Watchdog Timer. It also resets the
prescaler of the WDT. Status bits TO
and PD are set.
Words:
1
Cycles:
1
Example
Decrement f
Description:
00
Words:
1
Cycles:
1
Example
DECF
CLRWDT
WDT counter =
WDT counter =
WDT prescaler=
TO
=
PD
=
COMF
Complement f
Syntax:
[ label ] COMF
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
Status Affected:
=
=
0x01
0
=
=
0x00
1
After Instruction
?
CNT
Z
0x00
0
1
1
DECFSZ
Decrement f, Skip if 0
Syntax:
[ label ] DECFSZ f,d
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
(f) → (dest)
Operation:
(f) - 1 → (dest);
Z
Status Affected:
None
Encoding:
00
1001
f,d
dfff
ffff
The contents of register 'f' are
complemented. If 'd' is 0 the result is
stored in W. If 'd' is 1 the result is
stored back in register 'f'.
Words:
1
Cycles:
1
ffff
CNT, 1
CNT
Z
After Instruction
Example
dfff
Before Instruction
Before Instruction
Description:
0011
Decrement register 'f'. If 'd' is 0 the
result is stored in the W register. If 'd'
is 1 the result is stored back in register
'f'.
COMF
REG1,0
Before Instruction
REG1
=
0x13
=
=
0x13
0xEC
After Instruction
REG1
W
Encoding:
Description:
00
dfff
ffff
The contents of register 'f' are
decremented. If 'd' is 0 the result is
placed in the W register. If 'd' is 1 the
result is placed back in register 'f'.
If the result is 0, the next instruction,
which is already fetched, is discarded. A
NOP is executed instead making it a
two-cycle instruction.
Words:
1
Cycles:
1(2)
Example
1011
skip if result = 0
HERE
DECFSZ
GOTO
CONTINUE •
•
•
CNT, 1
LOOP
Before Instruction
PC
=
address HERE
After Instruction
CNT
if CNT
PC
if CNT
PC
DS40182A-page 70
Preliminary
=
=
=
≠
=
CNT - 1
0,
address CONTINUE
0,
address HERE+1
1998 Microchip Technology Inc.
62X.bk Page 71 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X
GOTO
Unconditional Branch
INCFSZ
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 ≤ k ≤ 2047
Operands:
Operation:
k → PC<10:0>
PCLATH<4:3> → PC<12:11>
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
(f) + 1 → (dest), skip if result = 0
Status Affected:
None
Status Affected:
None
Encoding:
Description:
GOTO k
10
1kkk
kkkk
kkkk
GOTO is an unconditional branch. The
eleven bit immediate value is loaded
into PC bits <10:0>. The upper bits of
PC are loaded from PCLATH<4:3>.
GOTO is a two-cycle instruction.
Words:
1
Cycles:
2
Example
GOTO THERE
After Instruction
PC =
Address THERE
Increment f, Skip if 0
Encoding:
Description:
00
INCFSZ f,d
1111
dfff
ffff
The contents of register 'f' are
incremented. If 'd' is 0 the result is
placed in the W register. If 'd' is 1 the
result is placed back in register 'f'.
If the result is 0, the next instruction,
which is already fetched, is discarded.
A NOP is executed instead making it
a two-cycle instruction.
Words:
1
Cycles:
1(2)
Example
HERE
INCFSZ
GOTO
CONTINUE •
•
•
CNT,
LOOP
1
Before Instruction
PC
=
address HERE
After Instruction
CNT =
if CNT=
PC
=
if CNT≠
PC
=
CNT + 1
0,
address CONTINUE
0,
address HERE +1
INCF
Increment f
IORLW
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
0 ≤ k ≤ 255
(f) + 1 → (dest)
Operation:
(W) .OR. k → (W)
Operation:
Status Affected:
Z
Status Affected:
Z
Encoding:
Description:
INCF f,d
Encoding:
00
1010
dfff
ffff
The contents of register 'f' are
incremented. If 'd' is 0 the result is
placed in the W register. If 'd' is 1 the
result is placed back in register 'f'.
Description:
1
1
Words:
1
Cycles:
1
Example
INCF
11
IORLW k
1000
kkkk
IORLW
0x35
Before Instruction
CNT, 1
W
Before Instruction
CNT
Z
kkkk
The contents of the W register is
OR’ed with the eight bit literal 'k'. The
result is placed in the W register.
Words:
Cycles:
Example
Inclusive OR Literal with W
=
0x9A
After Instruction
=
=
0xFF
0
=
=
0x00
1
W
Z
=
=
0xBF
1
After Instruction
CNT
Z
1998 Microchip Technology Inc.
Preliminary
DS40182A-page 71
62X.bk Page 72 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X
IORWF
Inclusive OR W with f
MOVF
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
(W) .OR. (f) → (dest)
Operation:
(f) → (dest)
Status Affected:
Z
Status Affected:
Z
Encoding:
Description:
00
IORWF
f,d
0100
dfff
ffff
Inclusive OR the W register with
register 'f'. If 'd' is 0 the result is placed
in the W register. If 'd' is 1 the result is
placed back in register 'f'.
Words:
1
Cycles:
1
Example
IORWF
RESULT, 0
Before Instruction
RESULT =
W
=
0x13
0x91
Move f
Encoding:
Description:
00
1000
1
Cycles:
1
Example
MOVF
FSR, 0
0x13
0x93
1
W = value in FSR register
Z =1
MOVLW
Move Literal to W
MOVWF
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 ≤ k ≤ 255
Operands:
0 ≤ f ≤ 127
Operation:
k → (W)
Operation:
(W) → (f)
Status Affected:
None
Status Affected:
None
11
MOVLW k
00xx
kkkk
kkkk
Description:
The eight bit literal 'k' is loaded into W
register. The don’t cares will assemble
as 0’s.
Words:
1
Cycles:
1
Example
0000
f
1fff
ffff
Move data from W register to register
'f'.
Words:
1
Cycles:
1
MOVWF
OPTION
Before Instruction
After Instruction
=
00
MOVWF
Description:
0x5A
W
Move W to f
Encoding:
Example
MOVLW
ffff
After Instruction
RESULT =
W
=
Z
=
Encoding:
dfff
The contents of register f is moved to
a destination dependant upon the
status of d. If d = 0, destination is W
register. If d = 1, the destination is file
register f itself. d = 1 is useful to test a
file register since status flag Z is
affected.
Words:
After Instruction
MOVF f,d
OPTION =
W
=
0x5A
0xFF
0x4F
After Instruction
OPTION =
W
=
DS40182A-page 72
Preliminary
0x4F
0x4F
1998 Microchip Technology Inc.
62X.bk Page 73 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X
NOP
No Operation
RETFIE
Return from Interrupt
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
None
Operands:
None
Operation:
No operation
Operation:
Status Affected:
None
TOS → PC,
1 → GIE
Status Affected:
None
Encoding:
Description:
00
NOP
0000
0xx0
0000
Encoding:
No operation.
Words:
1
Cycles:
1
Example
RETFIE
00
Description:
0000
0000
1001
Return from Interrupt. Stack is POPed
and Top of Stack (TOS) is loaded in
the PC. Interrupts are enabled by
setting Global Interrupt Enable bit,
GIE (INTCON<7>). This is a two-cycle
instruction.
NOP
Words:
1
Cycles:
2
Example
RETFIE
After Interrupt
PC =
GIE =
OPTION
Load Option Register
RETLW
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
None
Operands:
0 ≤ k ≤ 255
Operation:
(W) → OPTION
Operation:
k → (W);
TOS → PC
Status Affected:
None
OPTION
Return with Literal in W
Status Affected: None
Encoding:
Description:
00
0000
0110
0010
The contents of the W register are
loaded in the OPTION register. This
instruction is supported for code
compatibility with PIC16C5X products.
Since OPTION is a readable/writable
register, the user can directly
address it.
Encoding:
Description:
11
1
Words:
1
Cycles:
1
Cycles:
2
Example
To maintain upward compatibility
with future PICmicro™ products,
do not use this instruction.
RETLW k
01xx
kkkk
kkkk
The W register is loaded with the eight
bit literal 'k'. The program counter is
loaded from the top of the stack (the
return address). This is a two-cycle
instruction.
Words:
Example
TOS
1
CALL TABLE
•
value
•
TABLE •
ADDWF
RETLW
RETLW
•
•
•
RETLW
;W contains table
;offset value
;W now has table
PC
k1
k2
;W = offset
;Begin table
;
kn
; End of table
Before Instruction
W
=
0x07
After Instruction
W
1998 Microchip Technology Inc.
Preliminary
=
value of k8
DS40182A-page 73
62X.bk Page 74 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X
RETURN
Return from Subroutine
RRF
Rotate Right f through Carry
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
None
Operands:
Operation:
TOS → PC
0 ≤ f ≤ 127
d ∈ [0,1]
Status Affected:
None
Operation:
See description below
Status Affected:
C
Encoding:
Description:
00
0000
0000
1000
Return from subroutine. The stack is
POPed and the top of the stack (TOS)
is loaded into the program counter.
This is a two cycle instruction.
Words:
1
Cycles:
2
Example
RETURN
Encoding:
Description:
RRF f,d
00
1100
dfff
ffff
The contents of register 'f' are rotated
one bit to the right through the Carry
Flag. If 'd' is 0 the result is placed in
the W register. If 'd' is 1 the result is
placed back in register 'f'.
C
Register f
RETURN
After Interrupt
PC =
TOS
Words:
1
Cycles:
1
Example
RRF
REG1,0
Before Instruction
REG1
C
=
=
1110 0110
0
=
=
=
1110 0110
0111 0011
0
After Instruction
REG1
W
C
RLF
Rotate Left f through Carry
SLEEP
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
None
Operation:
See description below
Operation:
Status Affected:
C
00h → WDT,
0 → WDT prescaler,
1 → TO,
0 → PD
Status Affected:
TO, PD
Encoding:
Description:
RLF
00
1101
dfff
ffff
The contents of register 'f' are rotated
one bit to the left through the Carry
Flag. If 'd' is 0 the result is placed in
the W register. If 'd' is 1 the result is
stored back in register 'f'.
C
Words:
1
Cycles:
1
Example
f,d
RLF
Encoding:
Before Instruction
REG1
C
=
=
1110 0110
0
=
=
=
1110 0110
1100 1100
1
0000
0110
0011
Description:
The power-down status bit, PD is
cleared. Time-out status bit, TO is
set. Watchdog Timer and its
prescaler are cleared.
The processor is put into SLEEP
mode with the oscillator stopped.
See Section 10.8 for more details.
Words:
1
Cycles:
1
Example:
SLEEP
Register f
REG1,0
00
SLEEP
After Instruction
REG1
W
C
DS40182A-page 74
Preliminary
1998 Microchip Technology Inc.
62X.bk Page 75 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X
SUBLW
Subtract W from Literal
SUBWF
Subtract W from f
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 ≤ k ≤ 255
Operands:
Operation:
k - (W) → (W)
0 ≤ f ≤ 127
d ∈ [0,1]
Status
Affected:
C, DC, Z
Operation:
(f) - (W) → (dest)
C, DC, Z
Encoding:
11
Status
Affected:
Description:
Words:
SUBLW k
110x
kkkk
kkkk
The W register is subtracted (2’s complement method) from the eight bit literal
'k'. The result is placed in the W register.
Encoding:
1
Example 1:
SUBLW
0x02
Before Instruction
W
C
=
=
Example 2:
=
=
1
Cycles:
1
Example 1:
SUBWF
1
?
Example 3:
=
=
REG1
W
C
1
1; result is posi-
REG1
W
C
2
?
=
=
Example 2:
3
2
?
=
=
=
1
2
1; result is positive
Before Instruction
REG1
W
C
0
1; result is zero
=
=
=
2
2
?
After Instruction
3
?
REG1
W
C
After Instruction
W =
C
=
tive
=
=
=
After Instruction
Before Instruction
W
C
REG1,1
Before Instruction
After Instruction
W
C
ffff
Words:
Before Instruction
W
C
dfff
Subtract (2’s complement method)
W register from register 'f'. If 'd' is 0 the
result is stored in the W register. If 'd' is 1
the result is stored back in register 'f'.
After Instruction
W =
C
=
tive
0010
Description:
1
Cycles:
00
SUBWF f,d
0xFF
0; result is nega-
Example 3:
=
=
=
0
2
1; result is zero
Before Instruction
REG1
W
C
=
=
=
1
2
?
After Instruction
REG1
W
C
1998 Microchip Technology Inc.
Preliminary
=
=
=
0xFF
2
0; result is negative
DS40182A-page 75
62X.bk Page 76 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X
SWAPF
Swap Nibbles in f
XORLW
Exclusive OR Literal with W
Syntax:
[ label ] SWAPF f,d
Syntax:
[ label ]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
0 ≤ k ≤ 255
Operation:
(f<3:0>) → (dest<7:4>),
(f<7:4>) → (dest<3:0>)
Operation:
(W) .XOR. k → (W)
Status Affected:
Z
Status Affected:
None
Words:
Cycles:
11
1010
kkkk
The contents of the W register are
XOR’ed with the eight bit literal 'k'.
The result is placed in the
W register.
Words:
1
1
Cycles:
1
1
Example:
XORLW
00
1110
dfff
ffff
The upper and lower nibbles of
register 'f' are exchanged. If 'd' is 0
the result is placed in W register. If 'd'
is 1 the result is placed in register 'f'.
Example
SWAPF REG,
0xAF
Before Instruction
0
W
Before Instruction
REG1
=
0xA5
W
REG1
W
=
=
=
0xB5
After Instruction
After Instruction
=
0x1A
0xA5
0x5A
TRIS
Load TRIS Register
XORWF
Exclusive OR W with f
Syntax:
[ label ] TRIS
Syntax:
[ label ] XORWF
Operands:
5≤f≤7
Operands:
Operation:
(W) → TRIS register f;
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
(W) .XOR. (f) → (dest)
Status Affected:
Z
f
Status Affected: None
Encoding:
Description:
kkkk
Description:
Encoding:
Description:
Encoding:
XORLW k
00
0000
0110
0fff
The instruction is supported for code
compatibility with the PIC16C5X
products. Since TRIS registers are
readable and writable, the user can
directly address them.
Words:
1
Cycles:
1
Example
To maintain upward compatibility
with future PICmicro™ products,
do not use this instruction.
Encoding:
Description:
00
0110
f,d
dfff
ffff
Exclusive OR the contents of the
W register with register 'f'. If 'd' is 0 the
result is stored in the W register. If 'd'
is 1 the result is stored back in register
'f'.
Words:
1
Cycles:
1
Example
XORWF
REG
1
Before Instruction
REG
W
=
=
0xAF
0xB5
=
=
0x1A
0xB5
After Instruction
REG
W
DS40182A-page 76
Preliminary
1998 Microchip Technology Inc.
62X.bk Page 77 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X
12.0
DEVELOPMENT SUPPORT
12.1
Development Tools
The PICmicrο microcontrollers are supported with a
full range of hardware and software development tools:
• PICMASTER/PICMASTER CE Real-Time
In-Circuit Emulator
• ICEPIC Low-Cost PIC16C5X and PIC16CXXX
In-Circuit Emulator
• PRO MATE II Universal Programmer
• PICSTART Plus Entry-Level Prototype
Programmer
• PICDEM-1 Low-Cost Demonstration Board
• PICDEM-2 Low-Cost Demonstration Board
• PICDEM-3 Low-Cost Demonstration Board
• MPASM Assembler
• MPLAB SIM Software Simulator
• MPLAB-C17 (C Compiler)
• Fuzzy Logic Development System
(fuzzyTECH−MP)
12.2
PICMASTER: High Performance
Universal In-Circuit Emulator with
MPLAB IDE
12.3
ICEPIC: Low-Cost PICmicro™
In-Circuit Emulator
ICEPIC is a low-cost in-circuit emulator solution for the
Microchip PIC12CXXX, PIC16C5X and PIC16CXXX
families of 8-bit OTP microcontrollers.
ICEPIC is designed to operate on PC-compatible
machines ranging from 286-AT through Pentium
based machines under Windows 3.x environment.
ICEPIC features real time, non-intrusive emulation.
12.4
PRO MATE II: Universal Programmer
The PRO MATE II Universal Programmer is a full-featured programmer capable of operating in stand-alone
mode as well as PC-hosted mode. PRO MATE II is CE
compliant.
The PRO MATE II has programmable VDD and VPP
supplies which allows it to verify programmed memory
at VDD min and VDD max for maximum reliability. It has
an LCD display for displaying error messages, keys to
enter commands and a modular detachable socket
assembly to support various package types. In standalone mode the PRO MATE II can read, verify or program
PIC12CXXX,
PIC14C000,
PIC16C5X,
PIC16CXXX and PIC17CXX devices. It can also set
configuration and code-protect bits in this mode.
The PICMASTER Universal In-Circuit Emulator is
intended to provide the product development engineer
with a complete microcontroller design tool set for all
microcontrollers in the PIC14C000, PIC12CXXX,
PIC16C5X, PIC16CXXX and PIC17CXX families.
PICMASTER is supplied with the MPLAB Integrated
Development Environment (IDE), which allows editing,
“make” and download, and source debugging from a
single environment.
12.5
Interchangeable target probes allow the system to be
easily reconfigured for emulation of different processors. The universal architecture of the PICMASTER
allows expansion to support all new Microchip microcontrollers.
PICSTART Plus supports all PIC12CXXX, PIC14C000,
PIC16C5X, PIC16CXXX and PIC17CXX devices with
up to 40 pins. Larger pin count devices such as the
PIC16C923, PIC16C924 and PIC17C756 may be supported with an adapter socket. PICSTART Plus is CE
compliant.
The PICMASTER Emulator System has been
designed as a real-time emulation system with
advanced features that are generally found on more
expensive development tools. The PC compatible 386
(and higher) machine platform and Microsoft Windows
3.x environment were chosen to best make these features available to you, the end user.
PICSTART Plus Entry Level
Development System
The PICSTART programmer is an easy-to-use, lowcost prototype programmer. It connects to the PC via
one of the COM (RS-232) ports. MPLAB Integrated
Development Environment software makes using the
programmer simple and efficient. PICSTART Plus is
not recommended for production programming.
A CE compliant version of PICMASTER is available for
European Union (EU) countries.
1998 Microchip Technology Inc.
DS40182A - page 77
62X.bk Page 78 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X
12.6
PICDEM-1 Low-Cost PICmicro
Demonstration Board
The PICDEM-1 is a simple board which demonstrates
the capabilities of several of Microchip’s microcontrollers. The microcontrollers supported are: PIC16C5X
(PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X,
PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and
PIC17C44. All necessary hardware and software is
included to run basic demo programs. The users can
program the sample microcontrollers provided with
the PICDEM-1 board, on a PRO MATE II or
PICSTART-Plus programmer, and easily test firmware. The user can also connect the PICDEM-1
board to the PICMASTER emulator and download
the firmware to the emulator for testing. Additional prototype area is available for the user to build some additional hardware and connect it to the microcontroller
socket(s). Some of the features include an RS-232
interface, a potentiometer for simulated analog input,
push-button switches and eight LEDs connected to
PORTB.
12.7
PICDEM-2 Low-Cost PIC16CXX
Demonstration Board
The PICDEM-2 is a simple demonstration board that
supports the PIC16C62, PIC16C64, PIC16C65,
PIC16C73 and PIC16C74 microcontrollers. All the
necessary hardware and software is included to
run the basic demonstration programs. The user
can program the sample microcontrollers provided
with the PICDEM-2 board, on a PRO MATE II programmer or PICSTART-Plus, and easily test firmware.
The PICMASTER emulator may also be used with the
PICDEM-2 board to test firmware. Additional prototype
area has been provided to the user for adding additional hardware and connecting it to the microcontroller
socket(s). Some of the features include a RS-232 interface, push-button switches, a potentiometer for simulated analog input, a Serial EEPROM to demonstrate
usage of the I2C bus and separate headers for connection to an LCD module and a keypad.
12.8
PICDEM-3 Low-Cost PIC16CXXX
Demonstration Board
The PICDEM-3 is a simple demonstration board that
supports the PIC16C923 and PIC16C924 in the PLCC
package. It will also support future 44-pin PLCC
microcontrollers with a LCD Module. All the necessary hardware and software is included to run the
basic demonstration programs. The user can program the sample microcontrollers provided with
the PICDEM-3 board, on a PRO MATE II programmer or PICSTART Plus with an adapter socket, and
easily test firmware. The PICMASTER emulator may
also be used with the PICDEM-3 board to test firmware. Additional prototype area has been provided to
the user for adding hardware and connecting it to the
microcontroller socket(s). Some of the features include
DS40182A - page 78
an RS-232 interface, push-button switches, a potentiometer for simulated analog input, a thermistor and
separate headers for connection to an external LCD
module and a keypad. Also provided on the PICDEM-3
board is an LCD panel, with 4 commons and 12 segments, that is capable of displaying time, temperature
and day of the week. The PICDEM-3 provides an additional RS-232 interface and Windows 3.1 software for
showing the demultiplexed LCD signals on a PC. A simple serial interface allows the user to construct a hardware demultiplexer for the LCD signals.
12.9
MPLAB™ Integrated Development
Environment Software
The MPLAB IDE Software brings an ease of software
development previously unseen in the 8-bit microcontroller market. MPLAB is a windows based application
which contains:
• A full featured editor
• Three operating modes
- editor
- emulator
- simulator
• A project manager
• Customizable tool bar and key mapping
• A status bar with project information
• Extensive on-line help
MPLAB allows you to:
• Edit your source files (either assembly or ‘C’)
• One touch assemble (or compile) and download
to PICmicro tools (automatically updates all
project information)
• Debug using:
- source files
- absolute listing file
• Transfer data dynamically via DDE (soon to be
replaced by OLE)
• Run up to four emulators on the same PC
The ability to use MPLAB with Microchip’s simulator
allows a consistent platform and the ability to easily
switch from the low cost simulator to the full featured
emulator with minimal retraining due to development
tools.
12.10
Assembler (MPASM)
The MPASM Universal Macro Assembler is a PChosted symbolic assembler. It supports all microcontroller series including the PIC12C5XX, PIC14000,
PIC16C5X, PIC16CXXX, and PIC17CXX families.
MPASM offers full featured Macro capabilities, conditional assembly, and several source and listing formats.
It generates various object code formats to support
Microchip's development tools as well as third party
programmers.
MPASM allows full symbolic debugging from
PICMASTER, Microchip’s Universal Emulator System.
1998 Microchip Technology Inc.
62X.bk Page 79 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X
MPASM has the following features to assist in developing software for specific use applications.
• Provides translation of Assembler source code to
object code for all Microchip microcontrollers.
• Macro assembly capability.
• Produces all the files (Object, Listing, Symbol, and
special) required for symbolic debug with
Microchip’s emulator systems.
• Supports Hex (default), Decimal and Octal source
and listing formats.
MPASM provides a rich directive language to support
programming of the PICmicro. Directives are helpful in
making the development of your assemble source code
shorter and more maintainable.
12.11
Software Simulator (MPLAB-SIM)
The MPLAB-SIM Software Simulator allows code
development in a PC host environment. It allows the
user to simulate the PICmicro series microcontrollers
on an instruction level. On any given instruction, the
user may examine or modify any of the data areas or
provide external stimulus to any of the pins. The input/
output radix can be set by the user and the execution
can be performed in; single step, execute until break, or
in a trace mode.
MPLAB-SIM fully supports symbolic debugging using
MPLAB-C and MPASM. The Software Simulator offers
the low cost flexibility to develop and debug code outside of the laboratory environment making it an excellent multi-project software development tool.
12.12
C Compiler (MPLAB-C17)
12.14
MP-DriveWay – Application Code
Generator
MP-DriveWay is an easy-to-use Windows-based Application Code Generator. With MP-DriveWay you can
visually configure all the peripherals in a PICmicro
device and, with a click of the mouse, generate all the
initialization and many functional code modules in C
language. The output is fully compatible with Microchip’s MPLAB-C C compiler. The code produced is
highly modular and allows easy integration of your own
code. MP-DriveWay is intelligent enough to maintain
your code through subsequent code generation.
12.15
SEEVAL Evaluation and
Programming System
The SEEVAL SEEPROM Designer’s Kit supports all
Microchip 2-wire and 3-wire Serial EEPROMs. The kit
includes everything necessary to read, write, erase or
program special features of any Microchip SEEPROM
product including Smart Serials and secure serials.
The Total Endurance Disk is included to aid in tradeoff analysis and reliability calculations. The total kit can
significantly reduce time-to-market and result in an
optimized system.
12.16
KEELOQ Evaluation and
Programming Tools
KEELOQ evaluation and programming tools support
Microchips HCS Secure Data Products. The HCS evaluation kit includes an LCD display to show changing
codes, a decoder to decode transmissions, and a programming interface to program test transmitters.
The MPLAB-C Code Development System is a
complete ‘C’ compiler and integrated development
environment for Microchip’s PIC17CXXX family of
microcontrollers. The compiler provides powerful integration capabilities and ease of use not found with
other compilers.
For easier source level debugging, the compiler provides symbol information that is compatible with the
MPLAB IDE memory display.
12.13
Fuzzy Logic Development System
(fuzzyTECH-MP)
fuzzyTECH-MP fuzzy logic development tool is available in two versions - a low cost introductory version,
MP Explorer, for designers to gain a comprehensive
working knowledge of fuzzy logic system design; and a
full-featured version, fuzzyTECH-MP, Edition for implementing more complex systems.
Both versions include Microchip’s fuzzyLAB demonstration board for hands-on experience with fuzzy logic
systems implementation.
1998 Microchip Technology Inc.
DS40182A - page 79
Emulator Products
Software Tools
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
PIC16C6X PIC16C7XX PIC16C8X PIC16C9XX PIC17C4X
MPLAB C17
Compiler
fuzzyTECH-MP
Explorer/Edition
Fuzzy Logic
Dev. Tool
ü
ü
MP-DriveWay
Applications
Code Generator
PIC17C75X
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
Programmers
Total Endurance
Software Model
PICSTARTPlus
Low-Cost
Universal Dev. Kit
PRO MATE II
Universal
Programmer
KEELOQ
Programmer
Demo Boards
1998 Microchip Technology Inc.
PICDEM-2
PICDEM-3
KEELOQ
Evaluation Kit
HCS200
HCS300
HCS301
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
SEEVAL
Designers Kit
PICDEM-1
24CXX
25CXX
93CXX
ü
ü
ü
ü
ü
ü
ü
ü
ü
62X.bk Page 80 Tuesday, March 10, 1998 3:40 PM
PIC16CXXX
PIC16CE62X
MPLAB
Integrated
Development
Environment
PIC16C5X
DEVELOPMENT TOOLS FROM MICROCHIP
ICEPIC Low-Cost
In-Circuit Emulator
PIC14000
TABLE 12-1:
DS40182A - page 80
PICMASTER/
PICMASTER-CE
In-Circuit Emulator
PIC12C5XX
62X.bk Page 81 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X
13.0
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings †
Ambient Temperature under bias .............................................................................................................. -40° to +125°C
Storage Temperature................................................................................................................................. -65° to +150°C
Voltage on any pin with respect to VSS (except VDD and MCLR)....................................................... -0.6V to VDD +0.6V
Voltage on VDD with respect to VSS ................................................................................................................ 0 to +7.5V
Voltage on MCLR with respect to VSS (Note 2)..................................................................................................0 to +14V
Total power Dissipation (Note 1) ...............................................................................................................................1.0W
Maximum Current out of VSS pin...........................................................................................................................300 mA
Maximum Current into VDD pin .............................................................................................................................250 mA
Input Clamp Current, IIK (VI <0 or VI> VDD) ......................................................................................................................±20 mA
Output Clamp Current, IOK (VO <0 or VO>VDD) ...............................................................................................................±20 mA
Maximum Output Current sunk by any I/O pin ........................................................................................................25 mA
Maximum Output Current sourced by any I/O pin ...................................................................................................25 mA
Maximum Current sunk by PORTA and PORTB ...................................................................................................200 mA
Maximum Current sourced by PORTA and PORTB ..............................................................................................200 mA
Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOl x IOL)
† NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above
those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions
for extended periods may affect device reliability.
1998 Microchip Technology Inc.
Preliminary
DS40182A-page 81
62X.bk Page 82 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X
TABLE 13-1:
OSC
CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS
AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES)
PIC16CE62X-04
PIC16CE62X-20
PIC16CE62X/JW
RC
VDD: 3.0V to 5.5V
IDD: 3.3 mA max.
@5.5V
IPD: 2.5 µA max.
@4.0V, WDT DIS
Freq: 4.0 MHz
max.
VDD: 3.0V to 5.5V
IDD: 1.8 mA typ.
@5.5V
IPD: 1.0 µA typ.
@4.0V, WDT DIS
Freq: 4.0 MHz
max.
VDD: 3.0V to 5.5V
IDD: 3.3 mA max.
@5.5V
IPD: 2.5 µA max.
@4.0V, WDT DIS
Freq: 4.0 MHz
max.
XT
VDD: 3.0V to 5.5V
IDD: 3.3 mA max.
@5.5V
IPD: 2.5 µA max.
@4.0V, WDT DIS
Freq: 4.0 MHz
max.
VDD: 3.0V to 5.5V
IDD: 1.8 mA typ.
@5.5V
IPD: 1.0 µA typ.
@4.0V, WDT DIS
Freq: 4.0 MHz
max.
VDD: 3.0V to 5.5V
IDD: 3.3 mA max.
@5.5V
IPD: 2.5 µA max.
@4.0V, WDT DIS
Freq: 4.0 MHz
max.
HS
VDD: 4.5V to 5.5V
IDD: 3.0 mA typ.
@5.5V
IPD: 1.0 µA typ.
@4.0V, WDT DIS
Freq: 4.0 MHz
max.
VDD: 4.5V to 5.5V
IDD: 7.5 mA max.
@5.5V
IPD: 2.5 µA max.
@4.0V, WDT DIS
Freq: 20 MHz
max.
VDD: 4.5V to 5.5V
IDD: 7.5 mA max.
@5.5V
IPD: 2.5 µA max.
@4.0V, WDT DIS
Freq: 20 MHz
max.
LP
VDD: 3.0V to 5.5V
IDD: 70 µA max.
@32 kHz, 3.0V, WDT DIS
IPD: 2.5 µA max.
@4.0 V, WDT DIS
Freq: 200 kHz
max.
Do not use in
LP mode
VDD: 3.0V to 5.5V
IDD: 70 µA max.
@32 kHz, 3.0V, WDT DIS
IPD: 2.5 µA max.
@4.0V, WDT DIS
Freq: 200 kHz
max.
The shaded sections indicate oscillator selections which are tested for functionality, but not for MIN/MAX specifications. It is recommended that the user select the device type that ensures the specifications required.
DS40182A-page 82
Preliminary
1998 Microchip Technology Inc.
62X.bk Page 83 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X
13.1
DC CHARACTERISTICS:
PIC16CE62X-04 (Commercial, Industrial, Extended)
PIC16CE62X-20 (Commercial, Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
–40°C ≤ TA ≤ +85°C for industrial and
0°C ≤ TA ≤ +70°C for commercial and
–40°C ≤ TA ≤ +125°C for extended
Param
No.
Sym
Characteristic
Min
Typ†
Max
Units
3.0
4.5
–
1.5*
5.5
5.5
–
V
V
V
XT, RC and LP osc configuration
HS osc configuration
Device in SLEEP mode
–
VSS
–
V
See section on power-on reset for
details
0.05*
–
–
V/ms
3.7
3.7
4.0
4.0
4.3
4.4
V
See section on power-on reset for
details
BODEN configuration bit is cleared
(Automotive)
–
1.8
3.3
mA
D010A
–
35
70
µA
D013
–
3.0
7.5
mA
Power Down Current (Note 3)
–
1.0
2.5
15
µA
µA
VDD=4.0V, WDT disabled
(125°C)
µA
µA
µA
VDD = 4.0V
(125°C)
BOR enabled, VDD = 5.0V
D001
D001A
VDD
Supply Voltage
D002
VDR
D003
VPOR
RAM Data Retention
Voltage (Note 1)
VDD start voltage to
ensure Power-on Reset
D004
SVDD
D005
D005A
D010
VBOR
VDD rise rate to ensure
Power-on Reset
Brown-out Reset Voltage
IDD
Supply Current (Note 2)
Conditions
XT and RC osc configuration
FOSC = 4 MHz, VDD = 5.5V, WDT disabled (Note 4)
LP osc configuration,
PIC16CE62X-04 only
FOSC = 32 kHz, VDD = 4.0V, WDT disabled
HS osc configuration
FOSC = 20 MHz, VDD = 5.5V, WDT disabled
D021
IPD
D022
∆IWDT
WDT Current (Note 5)
–
6.0
D022A
∆IBOR
–
75
D023
∆ICOMP
–
60
100
µA
VDD = 4.0V
D023A
∆IVREF
Brown-out Reset Current (Note
5)
Comparator Current for each
Comparator (Note 5)
VREF Current (Note 5)
20
25
150
–
90
200
µA
VDD = 4.0V
*
†
Note 1:
2:
3:
4:
5:
These parameters are characterized but not tested.
Data in "Typ" column is at 5.0V, 25°C, unless otherwise stated. These parameters are for design guidance only and are
not tested.
This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and
switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tri-stated, pulled to VDD,
MCLR = VDD; WDT enabled/disabled as specified.
The power down current in SLEEP mode does not depend on the oscillator type. Power down current is measured with
the part in SLEEP mode, with all I/O pins in hi-impedence state and tied to VDD or VSS.
For RC osc configuration, current through Rext is not included. The current through the resistor can be estimated by the
formula Ir = VDD/2Rext (mA) with Rext in kΩ.
The ∆ current is the additional current consumed when this peripheral is enabled. This current should be added to the
base IDD or IPD measurement.
1998 Microchip Technology Inc.
Preliminary
DS40182A-page 83
62X.bk Page 84 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X
13.2
DC CHARACTERISTICS:
PIC16CE62X-04 (Commercial, Industrial, Extended)
PIC16CE62X-20 (Commercial, Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature –40˚C ≤ TA ≤ +85˚C for industrial and
0˚C ≤ TA ≤ +70˚C for commercial and
–40˚C ≤ TA ≤ +125˚C for extended
Operating voltage VDD range as described in DC spec Table 13-1 and Table 13-2
Characteristic
Parm Sym
No.
Min
Typ†
Max
VSS
-
0.8V
0.15VDD
VSS
Vss
-
Vss
-
Unit
Conditions
VIL Input Low Voltage
I/O ports
with TTL buffer
D030
D030A
with Schmitt Trigger input
MCLR, RA4/T0CKI,OSC1 (in
RC mode)
OSC1 (in XT and HS)
OSC1 (in LP)
D031
D032
D033
0.2VDD
0.2VDD
0.3VDD
0.6VDD 1.0
V VDD = 4.5V to 5.5V
otherwise(4)
V For entire VDD range
V Note1
V
VIH Input High Voltage
I/O ports
with TTL buffer
2.0V
0.25VDD +
0.8V
D041
with Schmitt Trigger input 0.8VDD
D042
MCLR RA4/T0CKI
0.8VDD
OSC1 (XT, HS and LP)
0.7VDD
D042A
D043
OSC1 (in RC mode)
0.9VDD
D070 IPURB PORTB weak pull-up current
50
200
Input Leakage Current
IIL (Notes 2, 3)
D060
I/O ports (Except PORTA)
D060A
PORTA
D060B
RA4/T0CKI
OSC1, MCLR
D061
D040
D040A
VDD
VDD
V VDD = 4.5V to 5.5V
otherwise (4)
VDD
VDD
VDD
V
V
400
Note1
µA VDD = 5.0V, VPIN = VSS
±1.0
±0.5
±1.0
±5.0
µA
µA
µA
µA
VSS ≤ VPIN ≤ VDD, pin at hi-impedance
Vss ≤ VPIN ≤ VDD, pin at hi-impedance
Vss ≤ VPIN ≤ VDD
Vss ≤ VPIN ≤ VDD, XT, HS and LP osc
configuration
0.6
0.6
0.6
0.6
V
V
V
V
IOL=8.5 mA, VDD=4.5V,
IOL=7.0 mA, VDD=4.5V,
IOL=1.6 mA, VDD=4.5V,
IOL=1.2 mA, VDD=4.5V,
For entire VDD range
VOL Output Low Voltage
I/O ports
D080
D080A
D083
OSC2/CLKOUT (RC only)
-
-
-40° to +85°C
+125°C
-40° to +85°C
+125°C
VOH Output High Voltage (Note 3)
D090
I/O ports (Except RA4)
VDD-0.7
V IOH=-3.0 mA, VDD=4.5V, -40° to +85°C
These parameters are characterized but not tested.
Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
Note 1: In RC oscillator configuration, the OSC1 pin is a Schmitt Trigger input. It is not recommended that the
PIC16CE62X be driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different
input voltages.
3: Negative current is defined as coming out of the pin.
4: The better of the two specifications may be used. For VIL, this would be the higher voltage and for
VIH, this would be the lower voltage.
*
†
DS40182A-page 84
Preliminary
1998 Microchip Technology Inc.
62X.bk Page 85 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X
13.2
DC CHARACTERISTICS:
PIC16CE62X-04 (Commercial, Industrial, Extended)
PIC16CE62X-20 (Commercial, Industrial, Extended) (Cont.)
Standard Operating Conditions (unless otherwise stated)
Operating temperature –40˚C ≤ TA ≤ +85˚C for industrial and
0˚C ≤ TA ≤ +70˚C for commercial and
–40˚C ≤ TA ≤ +125˚C for extended
Operating voltage VDD range as described in DC spec Table 13-1 and Table 13-2
Parm Sym
No.
Characteristic
D090A
D092
OSC2/CLKOUT (RC only)
D150
VOD Open-Drain High Voltage
Capacitive Loading Specs
on Output Pins
D100 COSC OSC2 pin
Min
Typ†
Max
VDD-0.7
-
-
VDD-0.7
VDD-0.7
-
10*
15
2
D101
Cio All I/O pins/OSC2 (in RC
Unit
Conditions
V IOH=-2.5 mA,
VDD=4.5V, +125°C
V IOH=-1.3 mA, VDD=4.5V, -40° to +85°C
V IOH=-1.0 mA, VDD=4.5V, +125°C
V RA4 pin
pF In XT, HS and LP modes when external
clock used to drive OSC1.
pF
50
mode)
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
Note 1: In RC oscillator configuration, the OSC1 pin is a Schmitt Trigger input. It is not recommended that the
PIC16CE62X be driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different
input voltages.
3: Negative current is defined as coming out of the pin.
4: The better of the two specifications may be used. For VIL, this would be the higher voltage and for
VIH, this would be the lower voltage.
1998 Microchip Technology Inc.
Preliminary
DS40182A-page 85
62X.bk Page 86 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X
TABLE 13-2:
COMPARATOR SPECIFICATIONS
Operating Conditions: Vdd range as described in Table 12-1, -40°C<TA<+125°C. Current consumption is specified in
Table 13-1.
Param No.
Characteristics
Sym
Min
Typ
± 5.0
D300
Input offset voltage
VIOFF
D301
Input common mode voltage
VICM
D302
CMRR
CMRR
300
Response Time(1)
TRESP
301
Comparator Mode Change to
Output Valid
TMC2OV
0
Max
Units
± 10
mV
VDD - 1.5
+55*
Comments
V
db
150*
400*
ns
10*
µs
PIC16CE62X
* These parameters are characterized but not tested.
Note 1: Response time measured with one comparator input at (VDD - 1.5)/2 while the other input transitions from
VSS to VDD.
TABLE 13-3:
VOLTAGE REFERENCE SPECIFICATIONS
Operating Conditions:Vdd range as described in Table 12-1, -40°C<TA<+125°C. Current consumption is specified in
Table 13-1.
Param
No.
Characteristics
Sym
D310
Resolution
VRES
D311
Absolute Accuracy
VRAA
D312
Unit Resistor Value (R)
VRUR
310
(1)
Settling Time
Min
Typ
VDD/24
Max
Units
VDD/32
LSB
+1/4
+1/2
LSB
LSB
Ω
2K*
TSET
10*
Comments
Low Range (VRR=1)
High Range
(VRR=0)
Figure 9-2
µs
* These parameters are characterized but not tested.
Note 1: Settling time measured while VRR = 1 and VR<3:0> transitions from 0000 to 1111.
DS40182A-page 86
Preliminary
1998 Microchip Technology Inc.
62X.bk Page 87 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X
13.3
Timing Parameter Symbology
The timing parameter symbols have been created with one of the following formats:
1. TppS2ppS
2. TppS
T
F
Frequency
Lowercase subscripts (pp) and their meanings:
pp
ck
CLKOUT
io
I/O port
mc
MCLR
Uppercase letters and their meanings:
S
F
Fall
H
High
I
Invalid (Hi-impedance)
L
Low
T
Time
osc
t0
OSC1
T0CKI
P
R
V
Z
Period
Rise
Valid
Hi-Impedance
FIGURE 13-1: LOAD CONDITIONS
Load condition 2
Load condition 1
VDD/2
RL
CL
Pin
CL
Pin
VSS
VSS
RL = 464Ω
CL = 50 pF
15 pF
1998 Microchip Technology Inc.
for all pins except OSC2
for OSC2 output
Preliminary
DS40182A-page 87
62X.bk Page 88 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X
13.4
Timing Diagrams and Specifications
FIGURE 13-2: EXTERNAL CLOCK TIMING
Q4
Q1
Q3
Q2
Q4
Q1
OSC1
1
3
3
4
4
2
CLKOUT
TABLE 13-4:
Parameter
No.
1
EXTERNAL CLOCK TIMING REQUIREMENTS
Sym
Characteristic
Min
Fos
External CLKIN Frequency
(Note 1)
DC
—
4
MHz
XT and RC osc mode, VDD=5.0V
DC
—
20
MHz
HS osc mode
Oscillator Frequency
(Note 1)
DC
DC
0.1
—
—
—
200
4
4
kHz
MHz
MHz
LP osc mode
RC osc mode, VDD=5.0V
XT osc mode
1
DC
—
–
20
200
MHz
kHz
HS osc mode
LP osc mode
250
50
—
—
—
—
ns
ns
XT and RC osc mode
HS osc mode
5
250
—
—
—
—
µs
ns
LP osc mode
RC osc mode
250
50
5
—
—
—
10,000
1,000
—
ns
ns
µs
XT osc mode
HS osc mode
LP osc mode
Tosc
External CLKIN Period
(Note 1)
Oscillator Period
(Note 1)
Typ†
Max
Units Conditions
2
TCY
Instruction Cycle Time (Note 1)
1.0
Fosc/4
DC
µs
TCYS=FOSC/4
3*
TosL,
TosH
External Clock in (OSC1) High or
Low Time
100*
2*
—
—
—
—
ns
µs
XT oscillator, TOSC L/H duty cycle
LP oscillator, TOSC L/H duty cycle
20*
—
—
ns
HS oscillator, TOSC L/H duty
cycle
25*
50*
—
—
—
—
ns
ns
XT oscillator
LP oscillator
15*
—
—
ns
HS oscillator
4*
TosR,
TosF
External Clock in (OSC1) Rise or
Fall Time
*
†
These parameters are characterized but not tested.
Data in "Typ" column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are
based on characterization data for that particular oscillator type under standard operating conditions with the
device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or
higher than expected current consumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1 pin.
When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices.
DS40182A-page 88
Preliminary
1998 Microchip Technology Inc.
62X.bk Page 89 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X
FIGURE 13-3: CLKOUT AND I/O TIMING
Q1
Q4
Q2
Q3
OSC1
11
10
22
23
CLKOUT
13
19
14
12
18
16
I/O Pin
(input)
15
17
I/O Pin
(output)
new value
old value
20, 21
Note: All tests must be do with specified capacitance loads (Figure 13-1) 50 pF on I/O pins and CLKOUT
TABLE 13-5:
Parameter #
CLKOUT AND I/O TIMING REQUIREMENTS
Sym
Characteristic
10*
TosH2ckL
OSC1↑ to CLKOUT↓ (1)
11*
TosH2ckH
12*
TckR
13*
TckF
CLKOUT fall time
14*
TckL2ioV
CLKOUT ↓ to Port out valid
15*
TioV2ckH
Port in valid before CLKOUT ↑
OSC1↑ to CLKOUT↑
Min
Typ†
Max
Units
—
75
200
ns
—
75
200
ns
—
35
100
ns
—
35
100
ns
—
—
20
ns
Tosc +200 ns
—
—
ns
ns
(1)
(1)
CLKOUT rise time
(1)
(1)
(1)
16*
TckH2ioI
Port in hold after CLKOUT ↑
17*
TosH2ioV
OSC1↑ (Q1 cycle) to Port out valid
18*
TosH2ioI
OSC1↑ (Q2 cycle) to Port input invalid (I/O in hold
time)
0
—
—
—
50
150
ns
100
—
—
ns
(1)
19*
TioV2osH
Port input valid to OSC1↑ (I/O in setup time)
0
—
—
ns
20*
TioR
Port output rise time
—
10
40
ns
21*
TioF
Port output fall time
—
10
40
ns
22*
Tinp
RB0/INT pin high or low time
25
—
—
ns
23
Trbp
RB<7:4> change interrupt high or low time
TCY
—
—
ns
* These parameters are characterized but not tested
† Data in "Typ" column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC
1998 Microchip Technology Inc.
Preliminary
DS40182A-page 89
62X.bk Page 90 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X
FIGURE 13-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Timeout
32
OSC
Timeout
Internal
RESET
Watchdog
Timer
RESET
31
34
34
I/O Pins
FIGURE 13-5: BROWN-OUT RESET TIMING
BVDD
VDD
35
TABLE 13-6:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER REQUIREMENTS
Parameter
No.
Sym
30
31
*
†
Characteristic
Min
Typ†
Max
Units
Conditions
TmcL
MCLR Pulse Width (low)
2000
—
—
ns
-40° to +85°C
Twdt
Watchdog Timer Time-out Period
(No Prescaler)
7*
18
33*
ms
VDD = 5.0V, -40° to +85°C
32
Tost
Oscillation Start-up Timer Period
—
1024 TOSC
—
—
TOSC = OSC1 period
33
Tpwrt
Power-up Timer Period
28*
72
132*
ms
VDD = 5.0V, -40° to +85°C
34
TIOZ
I/O hi-impedance from MCLR low
—
2.0
µs
35
TBOR
Brown-out Reset Pulse Width
—
—
µs
100*
3.7V ≤ VDD ≤ 4.3V
These parameters are characterized but not tested.
Data in "Typ" column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
DS40182A-page 90
Preliminary
1998 Microchip Technology Inc.
62X.bk Page 91 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X
FIGURE 13-6: TIMER0 CLOCK TIMING
RA4/T0CKI
41
40
42
TMR0
TABLE 13-7:
Parameter
No.
40
TIMER0 CLOCK REQUIREMENTS
Sym Characteristic
Tt0H T0CKI High Pulse Width
Min
No Prescaler
Tt0L T0CKI Low Pulse Width
No Prescaler
*
†
Tt0P T0CKI Period
Units Conditions
—
—
ns
10*
—
—
ns
0.5 TCY + 20*
—
—
ns
10*
—
—
ns
TCY + 40*
N
—
—
ns
With Prescaler
42
Max
0.5 TCY + 20*
With Prescaler
41
Typ†
N = prescale value
(1, 2, 4, ..., 256)
These parameters are characterized but not tested.
Data in "Typ" column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
1998 Microchip Technology Inc.
Preliminary
DS40182A-page 91
62X.bk Page 92 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X
13.5
EEPROM Timing
TABLE 13-8:
AC CHARACTERISTICS
Parameter
Symbol
STANDARD
MODE
Vcc = 4.5 - 5.5V
FAST MODE
Min.
Max.
Min.
Max.
Units
Remarks
Clock frequency
Clock high time
Clock low time
SDA and SCL rise time
SDA and SCL fall time
START condition hold time
FCLK
THIGH
TLOW
TR
TF
THD:STA
—
4000
4700
—
—
4000
100
—
—
1000
300
—
—
600
1300
—
—
600
400
—
—
300
300
—
kHz
ns
ns
ns
ns
ns
START condition setup time
TSU:STA
4700
—
600
—
ns
Data input hold time
Data input setup time
STOP condition setup time
Output valid from clock
Bus free time
THD:DAT
TSU:DAT
TSU:STO
TAA
TBUF
0
250
4000
—
4700
—
—
—
3500
—
0
100
600
—
1300
—
—
—
900
—
ns
ns
ns
ns
ns
TOF
—
250
250
ns
TSP
—
50
20 +0.1
CB
—
(Note 2)
Time the bus must be free
before a new transmission
can start
(Note 1), CB ≤ 100 pF
50
ns
(Note 3)
Output fall time from VIH
minimum to VIL maximum
Input filter spike suppression
(SDA and SCL pins)
Write cycle time
Endurance
Note 1:
2:
3:
4:
(Note 1)
(Note 1)
After this period the first
clock pulse is generated
Only relevant for repeated
START condition
(Note 2)
—
10
—
10
ms
Byte or Page mode
10M
—
10M
25°C, Vcc = 5.0V, Block
—
—
cycles
1M
1M
Mode (Note 4)
Not 100% tested. CB = total capacitance of one bus line in pF.
As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
The combined TSP and VHYS specifications are due to new Schmitt trigger inputs which provide improved
noise spike suppression. This eliminates the need for a TI specification for standard operation.
This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model which can be obtained on our website.
TWR
FIGURE 13-7: BUS TIMING DATA
TR
TF
THIGH
TLOW
SCL
TSU:STA
SDA
IN
THD:DAT
TSU:DAT
TSU:STO
THD:STA
TSP
TAA
THD:STA
TAA
TBUF
SDA
OUT
DS40182A-page 92
Preliminary
1998 Microchip Technology Inc.
62X.bk Page 93 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X
14.0
PACKAGING INFORMATION
Package Type:
K04-010 18-Lead Ceramic Dual In-line with Window (JW) – 300 mil
E
D
W2
2
n
1
W1
E1
A
R
A1
L
c
A2
eB
B1
p
B
Units
Dimension Limits
PCB Row Spacing
Number of Pins
Pitch
Lower Lead Width
Upper Lead Width
Shoulder Radius
Lead Thickness
Top to Seating Plane
Top of Lead to Seating Plane
Base to Seating Plane
Tip to Seating Plane
Package Length
Package Width
Radius to Radius Width
Overall Row Spacing
Window Width
Window Length
MIN
n
p
B
B1
R
c
A
A1
A2
L
D
E
E1
eB
W1
W2
0.098
0.016
0.050
0.010
0.008
0.175
0.091
0.015
0.125
0.880
0.285
0.255
0.345
0.130
0.190
INCHES*
NOM
0.300
18
0.100
0.019
0.055
0.013
0.010
0.183
0.111
0.023
0.138
0.900
0.298
0.270
0.385
0.140
0.200
MAX
0.102
0.021
0.060
0.015
0.012
0.190
0.131
0.030
0.150
0.920
0.310
0.285
0.425
0.150
0.210
MILLIMETERS
MAX
NOM
7.62
18
2.59
2.49
2.54
0.53
0.41
0.47
1.52
1.27
1.40
0.38
0.25
0.32
0.30
0.20
0.25
4.83
4.45
4.64
3.33
2.31
2.82
0.76
0.00
0.57
3.81
3.18
3.49
22.35
22.86
23.37
7.87
7.24
7.56
7.24
6.86
6.48
9.78
10.80
8.76
0.15
0.14
0.13
0.2
0.21
0.19
MIN
* Controlling Parameter.
1998 Microchip Technology Inc.
Preliminary
DS40182A-page 93
62X.bk Page 94 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X
Package Type:
K04-007 18-Lead Plastic Dual In-line (P) – 300 mil
E
D
2
n
α
1
E1
A1
A
R
L
c
A2
B1
β
p
B
eB
Units
Dimension Limits
PCB Row Spacing
Number of Pins
Pitch
Lower Lead Width
Upper Lead Width
Shoulder Radius
Lead Thickness
Top to Seating Plane
Top of Lead to Seating Plane
Base to Seating Plane
Tip to Seating Plane
Package Length
Molded Package Width
Radius to Radius Width
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
INCHES*
NOM
0.300
18
0.100
0.013
0.018
0.055
0.060
0.000
0.005
0.005
0.010
0.110
0.155
0.075
0.095
0.000
0.020
0.125
0.130
0.890
0.895
0.245
0.255
0.230
0.250
0.310
0.349
5
10
5
10
MIN
n
p
B
B1†
R
c
A
A1
A2
L
D‡
E‡
E1
eB
α
β
MAX
0.023
0.065
0.010
0.015
0.155
0.115
0.020
0.135
0.900
0.265
0.270
0.387
15
15
MILLIMETERS
NOM
MAX
7.62
18
2.54
0.33
0.46
0.58
1.40
1.52
1.65
0.00
0.13
0.25
0.13
0.25
0.38
2.79
3.94
3.94
1.91
2.41
2.92
0.00
0.51
0.51
3.18
3.30
3.43
22.61
22.73
22.86
6.22
6.48
6.73
5.84
6.35
6.86
7.87
8.85
9.83
5
10
15
5
10
15
MIN
* Controlling Parameter.
†
Dimension “B1” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003”
(0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B1.”
‡
Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed 0.010” (0.254 mm) per side or 0.020” (0.508 mm) more than dimensions “D” or “E.”
DS40182A-page 94
Preliminary
1998 Microchip Technology Inc.
62X.bk Page 95 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X
Package Type:
K04-072 20-Lead Plastic Shrink Small Outine (SS) – 5.30 mm
E1
E
p
D
B
2
1
n
α
L
R2
c
A
A1
R1
φ
L1
A2
β
Units
Dimension Limits
Pitch
Number of Pins
Overall Pack. Height
Shoulder Height
Standoff
Molded Package Length
Molded Package Width
Outside Dimension
Shoulder Radius
Gull Wing Radius
Foot Length
Foot Angle
Radius Centerline
Lead Thickness
Lower Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
INCHES
NOM
0.026
20
0.073
0.068
0.036
0.026
0.005
0.002
0.283
0.278
0.208
0.205
0.306
0.301
0.005
0.005
0.005
0.005
0.020
0.015
0
4
0.005
0.000
0.007
0.005
0.012
0.010
0
5
0
5
MIN
p
n
A
A1
A2
D‡
E‡
E1
R1
R2
L
φ
L1
c
B†
α
β
MAX
0.078
0.046
0.008
0.289
0.212
0.311
0.010
0.010
0.025
8
0.010
0.009
0.015
10
10
MILLIMETERS*
NOM
MAX
0.65
20
1.86
1.99
1.73
0.91
1.17
0.66
0.13
0.21
0.05
7.20
7.33
7.07
5.29
5.38
5.20
7.65
7.78
7.90
0.25
0.13
0.13
0.25
0.13
0.13
0.38
0.64
0.51
8
0
4
0.00
0.25
0.13
0.13
0.22
0.18
0.25
0.38
0.32
0
5
10
0
5
10
MIN
*
Controlling Parameter.
†
Dimension “B” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003”
(0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B.”
‡
Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed 0.010” (0.254 mm) per side or 0.020” (0.508 mm) more than dimensions “D” or “E.”
1998 Microchip Technology Inc.
Preliminary
DS40182A-page 95
62X.bk Page 96 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X
Package Type:
K04-051 18-Lead Plastic Small Outline (SO) – Wide, 300 mil
E1
p
E
D
2
B
1
n
X
45 °
α
L
R2
c
A
R1
β
Units
Dimension Limits
Pitch
Number of Pins
Overall Pack. Height
Shoulder Height
Standoff
Molded Package Length
Molded Package Width
Outside Dimension
Chamfer Distance
Shoulder Radius
Gull Wing Radius
Foot Length
Foot Angle
Radius Centerline
Lead Thickness
Lower Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
L1
φ
A2
INCHES*
NOM
0.050
18
0.093
0.099
0.048
0.058
0.004
0.008
0.450
0.456
0.292
0.296
0.394
0.407
0.010
0.020
0.005
0.005
0.005
0.005
0.016
0.011
0
4
0.015
0.010
0.011
0.009
0.017
0.014
0
12
0
12
MIN
p
n
A
A1
A2
D‡
E‡
E1
X
R1
R2
L
φ
L1
c
B†
α
β
A1
MAX
0.104
0.068
0.011
0.462
0.299
0.419
0.029
0.010
0.010
0.021
8
0.020
0.012
0.019
15
15
MILLIMETERS
NOM
MAX
1.27
18
2.64
2.36
2.50
1.73
1.22
1.47
0.28
0.10
0.19
11.73
11.43
11.58
7.59
7.42
7.51
10.64
10.01
10.33
0.74
0.25
0.50
0.25
0.13
0.13
0.25
0.13
0.13
0.53
0.28
0.41
4
8
0
0.51
0.25
0.38
0.30
0.23
0.27
0.48
0.36
0.42
0
12
15
0
12
15
MIN
*
Controlling Parameter.
†
Dimension “B” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003”
(0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B.”
‡
Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed 0.010” (0.254 mm) per side or 0.020” (0.508 mm) more than dimensions “D” or “E.”
DS40182A-page 96
Preliminary
1998 Microchip Technology Inc.
62X.bk Page 97 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X
14.1
Package Marking Information
18-Lead PDIP
Example
XXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXX
AABBCDE
18-Lead SOIC (.300")
XXXXXXXXXXXX
XXXXXXXXXXXX
XXXXXXXXXXXX
AABBCDE
PIC16CE625
-04I/P423
9807CDK
Example
PIC16CE625
-04I/S0218
9807 CDK
18-Lead CERDIP Windowed
Example
XXXXXXXX
XXXXXXXX
AABBCDE
20-Lead SSOP
16CE625
/JW
9807 CBA
Example
XXXXXXXXXX
XXXXXXXXXX
AABBCDE
Legend: MM...M
XX...X
AA
BB
C
D
E
Note:
*
PIC16CE625
-04I/218
9807 CBP
Microchip part number information
Customer specific information*
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Facility code of the plant at which wafer is manufactured
O = Outside Vendor
C = 5” Line
S = 6” Line
H = 8” Line
Mask revision number
Assembly code of the plant or country of origin in which
part was assembled
In the event the full Microchip part number cannot be marked on one line,
it will be carried over to the next line thus limiting the number of available
characters for customer specific information.
Standard OTP marking consists of Microchip part number, year code, week
code, facility code, mask rev#, and assembly code. For OTP marking beyond
this, certain price adders apply. Please check with your Microchip Sales Office.
For QTP devices, any special marking adders are included in QTP price.
1998 Microchip Technology Inc.
Preliminary
DS40182A-page 97
62X.bk Page 98 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X
NOTES:
DS40182A-page 98
Preliminary
1998 Microchip Technology Inc.
62X.bk Page 99 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X
APPENDIX A: CODE FOR
ACCESSING EEPROM DATA
MEMORY
To be determined. Please check our web site at
www.microchip.com for code availability.
1998 Microchip Technology Inc.
Preliminary
DS40182A-page 99
62X.bk Page 100 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X
NOTES:
DS40182A-page 100
Preliminary
1998 Microchip Technology Inc.
62X.bk Page 101 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X
INDEX
A
ADDLW Instruction ............................................................. 67
ADDWF Instruction ............................................................. 67
ANDLW Instruction ............................................................. 67
ANDWF Instruction ............................................................. 67
Architectural Overview .......................................................... 7
Assembler
MPASM Assembler..................................................... 78
B
BCF Instruction ................................................................... 68
Block Diagram
TIMER0....................................................................... 35
TMR0/WDT PRESCALER .......................................... 38
Brown-Out Detect (BOD) .................................................... 54
BSF Instruction ................................................................... 68
BTFSC Instruction............................................................... 68
BTFSS Instruction............................................................... 69
C
CALL Instruction ................................................................. 69
Clocking Scheme/Instruction Cycle .................................... 10
CLRF Instruction ................................................................. 69
CLRW Instruction................................................................ 69
CLRWDT Instruction ........................................................... 70
CMCON Register ................................................................ 41
Code Protection .................................................................. 64
COMF Instruction ................................................................ 70
Comparator Configuration................................................... 42
Comparator Interrupts......................................................... 45
Comparator Module ............................................................ 41
Comparator Operation ........................................................ 43
Comparator Reference ....................................................... 43
Configuration Bits................................................................ 50
Configuring the Voltage Reference..................................... 47
Crystal Operation ................................................................ 51
D
Data Memory Organization ................................................. 12
DECF Instruction................................................................. 70
DECFSZ Instruction ............................................................ 70
Development Support ......................................................... 77
Development Tools ............................................................. 77
ANDLW....................................................................... 67
ANDWF ...................................................................... 67
BCF ............................................................................ 68
BSF............................................................................. 68
BTFSC........................................................................ 68
BTFSS ........................................................................ 69
CALL........................................................................... 69
CLRF .......................................................................... 69
CLRW ......................................................................... 69
CLRWDT .................................................................... 70
COMF ......................................................................... 70
DECF.......................................................................... 70
DECFSZ ..................................................................... 70
GOTO ......................................................................... 71
INCF ........................................................................... 71
INCFSZ....................................................................... 71
IORLW........................................................................ 71
IORWF........................................................................ 72
MOVF ......................................................................... 72
MOVLW ...................................................................... 72
MOVWF...................................................................... 72
NOP............................................................................ 73
OPTION...................................................................... 73
RETFIE....................................................................... 73
RETLW ....................................................................... 73
RETURN..................................................................... 74
RLF............................................................................. 74
RRF ............................................................................ 74
SLEEP ........................................................................ 74
SUBLW....................................................................... 75
SUBWF....................................................................... 75
SWAPF....................................................................... 76
TRIS ........................................................................... 76
XORLW ...................................................................... 76
XORWF ...................................................................... 76
Instruction Set Summary .................................................... 65
INT Interrupt ....................................................................... 60
INTCON Register ............................................................... 17
Interrupts ............................................................................ 59
IORLW Instruction .............................................................. 71
IORWF Instruction .............................................................. 72
K
KeeLoq Evaluation and Programming Tools ................... 79
E
M
EEPROM Peripheral Operation .......................................... 29
External Crystal Oscillator Circuit ....................................... 52
MOVF Instruction................................................................ 72
MOVLW Instruction ............................................................ 72
MOVWF Instruction ............................................................ 72
MP-DriveWay™ - Application Code Generator .................. 79
MPLAB C ............................................................................ 79
MPLAB Integrated Development Environment Software.... 78
F
Fuzzy Logic Dev. System (fuzzyTECH-MP) .................... 79
G
General purpose Register File ............................................ 12
GOTO Instruction................................................................ 71
NOP Instruction .................................................................. 73
I
I/O Ports .............................................................................. 23
I/O Programming Considerations........................................ 28
ICEPIC Low-Cost PIC16CXXX In-Circuit Emulator ............ 77
ID Locations ........................................................................ 64
INCF Instruction .................................................................. 71
INCFSZ Instruction ............................................................. 71
In-Circuit Serial Programming............................................. 64
Indirect Addressing, INDF and FSR Registers ................... 21
Instruction Flow/Pipelining .................................................. 10
Instruction Set
ADDLW ....................................................................... 67
ADDWF....................................................................... 67
1998 Microchip Technology Inc.
N
O
One-Time-Programmable (OTP) Devices .............................5
OPTION Instruction ............................................................ 73
OPTION Register ............................................................... 16
Oscillator Configurations .................................................... 51
Oscillator Start-up Timer (OST) .......................................... 54
P
Package Marking Information ............................................. 97
Packaging Information ........................................................ 93
PCL and PCLATH .............................................................. 20
PCON Register ................................................................... 19
PICDEM-1 Low-Cost PICmicro Demo Board ..................... 78
Preliminary
DS40182A-page 101
62X.bk Page 102 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X
PICDEM-2 Low-Cost PIC16CXX Demo Board ................... 78
PICDEM-3 Low-Cost PIC16CXXX Demo Board................. 78
PICMASTER In-Circuit Emulator...................................... 77
PICSTART Plus Entry Level Development System ......... 77
PIE1 Register ...................................................................... 18
Pinout Description ................................................................. 9
PIR1 Register...................................................................... 18
Port RB Interrupt ................................................................. 60
PORTA................................................................................ 23
PORTB................................................................................ 26
Power Control/Status Register (PCON) .............................. 55
Power-Down Mode (SLEEP)............................................... 63
Power-On Reset (POR) ...................................................... 54
Power-up Timer (PWRT)..................................................... 54
Prescaler ............................................................................. 38
PRO MATE II Universal Programmer............................... 77
Program Memory Organization ........................................... 11
Q
Quick-Turnaround-Production (QTP) Devices ...................... 5
R
RC Oscillator ....................................................................... 52
Reset................................................................................... 53
RETFIE Instruction.............................................................. 73
RETLW Instruction .............................................................. 73
RETURN Instruction............................................................ 74
RLF Instruction.................................................................... 74
RRF Instruction ................................................................... 74
S
SEEVAL Evaluation and Programming System ............... 79
Serialized Quick-Turnaround-Production (SQTP) Devices ... 5
SLEEP Instruction ............................................................... 74
Software Simulator (MPLAB-SIM)....................................... 79
Special Features of the CPU............................................... 49
Special Function Registers ................................................. 14
Stack ................................................................................... 20
Status Register.................................................................... 15
SUBLW Instruction.............................................................. 75
SUBWF Instruction.............................................................. 75
SWAPF Instruction.............................................................. 76
T
Timer0
TIMER0 ....................................................................... 35
TIMER0 (TMR0) Interrupt ........................................... 35
TIMER0 (TMR0) Module ............................................. 35
TMR0 with External Clock........................................... 37
Timer1
Switching Prescaler Assignment................................. 39
Timing Diagrams and Specifications................................... 88
TMR0 Interrupt .................................................................... 60
TRIS Instruction .................................................................. 76
TRISA.................................................................................. 23
TRISB.................................................................................. 26
V
Voltage Reference Module.................................................. 47
VRCON Register................................................................. 47
W
Watchdog Timer (WDT) ...................................................... 61
X
XORLW Instruction ............................................................. 76
XORWF Instruction ............................................................. 76
DS40182A-page 102
Preliminary
1998 Microchip Technology Inc.
62X.bk Page 103 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X
ON-LINE SUPPORT
Microchip provides on-line support on the Microchip
World Wide Web (WWW) site.
The web site is used by Microchip as a means to make
files and information easily available to customers. To
view the site, the user must have access to the Internet
and a web browser, such as Netscape or Microsoft
Explorer. Files are also available for FTP download
from our FTP site.
Connecting to the Microchip Internet Web Site
Systems Information and Upgrade Hot Line
The Systems Information and Upgrade Line provides
system users a listing of the latest versions of all of
Microchip's development systems software products.
Plus, this line provides information on how customers
can receive any currently available upgrade kits.The
Hot Line Numbers are:
1-800-755-2345 for U.S. and most of Canada, and
1-602-786-7302 for the rest of the world.
980106
The Microchip web site is available by using your
favorite Internet browser to attach to:
www.microchip.com
The file transfer site is available by using an FTP service to connect to:
ftp://ftp.futureone.com/pub/microchip
The web site and file transfer site provide a variety of
services. Users may download files for the latest
Development Tools, Data Sheets, Application Notes,
User's Guides, Articles and Sample Programs. A variety of Microchip specific business information is also
available, including listings of Microchip sales offices,
distributors and factory representatives. Other data
available for consideration is:
• Latest Microchip Press Releases
• Technical Support Section with Frequently Asked
Questions
• Design Tips
• Device Errata
• Job Postings
• Microchip Consultant Program Member Listing
• Links to other useful web sites related to
Microchip Products
• Conferences for products, Development Systems,
technical information and more
• Listing of seminars and events
1998 Microchip Technology Inc.
Trademarks: The Microchip name, logo, PIC, PICSTART,
PICMASTER and PRO MATE are registered trademarks
of Microchip Technology Incorporated in the U.S.A. and
other countries. PICmicro, FlexROM, MPLAB and fuzzyLAB are trademarks and SQTP is a service mark of Microchip in the U.S.A.
All other trademarks mentioned herein are the property of
their respective companies.
DS40182A-page 103
62X.bk Page 104 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (602) 786-7578.
Please list the following information, and use this outline to provide us with your comments about this Data Sheet.
To:
Technical Publications Manager
RE:
Reader Response
Total Pages Sent
From: Name
Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________
FAX: (______) _________ - _________
Application (optional):
Would you like a reply?
Device: PIC16CE62X
Y
N
Literature Number: DS40182A
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this data sheet easy to follow? If not, why?
4. What additions to the data sheet do you think would enhance the structure and subject?
5. What deletions from the data sheet could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
8. How would you improve our software, systems, and silicon products?
DS40182A-page 104
1998 Microchip Technology Inc.
62X.bk Page 105 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X
PIC16CE62X PRODUCT IDENTIFICATION SYSTEM
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed
sales offices.
PART NO.
-XX
X /XX XXX
Pattern:
3-Digit Pattern Code for QTP (blank otherwise)
Package:
P
SO
SS
JW*
=
=
=
=
PDIP
SOIC (Gull Wing, 300 mil body)
SSOP (209 mil)
Examples:
Windowed CERDIP
Temperature
Range:
I
E
=
=
=
0˚C to +70˚C
–40˚C to +85˚C
–40˚C to +125˚C
Frequency
Range:
04
04
20
=
=
=
200kHz (LP osc)
4 MHz (XT and RC osc)
20 MHz (HS osc)
Device:
PIC16CE62X :VDD range 3.0V to 5.5V
PIC16CE62XT:VDD range 3.0V to 5.5V (Tape and Reel)
a) PIC16CE623-04/P301 =
Commercial temp., PDIP package, 4 MHz, normal VDD limits,
QTP pattern #301.
b) PIC16CE623-04I/SO =
Industrial temp., SOIC package, 4MHz, industrial VDD limits.
* JW Devices are UV erasable and can be programmed to any device configuration. JW Devices meet the electrical requirement of
each oscillator type.
Sales and Support
Products supported by a preliminary Data Sheet may possibly have an errata sheet describing minor operational differences and
recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1.
Your local Microchip sales office.
2.
The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
For latest version information and upgrade kits for Microchip Development Tools, please call 1-800-755-2345 or 1-602-786-7302.
1998 Microchip Technology Inc.
Preliminary
DS40182A-page 105
62X.bk Page 106 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X
NOTES:
DS40182A-page 106
Preliminary
1998 Microchip Technology Inc.
62X.bk Page 107 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X
NOTES:
1998 Microchip Technology Inc.
Preliminary
DS40182A-page 107
62X.bk Page 108 Tuesday, March 10, 1998 3:40 PM
M
WORLDWIDE SALES AND SERVICE
AMERICAS
ASIA/PACIFIC
Corporate Office
Hong Kong
Taiwan, R.O.C
Microchip Technology Inc.
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 602-786-7200 Fax: 602-786-7277
Technical Support: 602 786-7627
Web: http://www.microchip.com
Microchip Asia Pacific
RM 3801B, Tower Two
Metroplaza
223 Hing Fong Road
Kwai Fong, N.T., Hong Kong
Tel: 852-2-401-1200 Fax: 852-2-401-3431
Microchip Technology Taiwan
10F-1C 207
Tung Hua North Road
Taipei, Taiwan, ROC
Tel: 886-2-2717-7175 Fax: 886-2-2545-0139
Atlanta
India
EUROPE
Microchip Technology Inc.
500 Sugar Mill Road, Suite 200B
Atlanta, GA 30350
Tel: 770-640-0034 Fax: 770-640-0307
Microchip Technology Inc.
India Liaison Office
No. 6, Legacy, Convent Road
Bangalore 560 025, India
Tel: 91-80-229-0061 Fax: 91-80-229-0062
United Kingdom
Boston
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Microchip Technology Inc.
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Microchip Technology Inc.
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Japan
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Tel: 81-45-471- 6166 Fax: 81-45-471-6122
Korea
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Seoul, Korea
Tel: 82-2-554-7200 Fax: 82-2-558-5934
Shanghai
Microchip Technology
RM 406 Shanghai Golden Bridge Bldg.
2077 Yan’an Road West, Hong Qiao District
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Tel: 86-21-6275-5700
Fax: 86 21-6275-5060
Singapore
ASIA/PACIFIC (CONTINUED)
Arizona Microchip Technology Ltd.
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Tel: 44-1189-21-5858 Fax: 44-1189-21-5835
France
Arizona Microchip Technology SARL
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2 Rue du Buisson aux Fraises
91300 Massy, France
Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79
Germany
Arizona Microchip Technology GmbH
Gustav-Heinemann-Ring 125
D-81739 Müchen, Germany
Tel: 49-89-627-144 0 Fax: 49-89-627-144-44
Italy
Arizona Microchip Technology SRL
Centro Direzionale Colleoni
Palazzo Taurus 1 V. Le Colleoni 1
20041 Agrate Brianza
Milan, Italy
Tel: 39-39-6899939 Fax: 39-39-6899883
Microchip Technology Taiwan
Singapore Branch
200 Middle Road
#07-02 Prime Centre
Singapore 188980
Tel: 65-334-8870 Fax: 65-334-8850
San Jose
Microchip Technology Inc.
2107 North First Street, Suite 590
San Jose, CA 95131
Tel: 408-436-7950 Fax: 408-436-7955
Toronto
Microchip Technology Inc.
5925 Airport Road, Suite 200
Mississauga, Ontario L4V 1W1, Canada
Tel: 905-405-6279 Fax: 905-405-6253
All rights reserved. © 1998, Microchip Technology Incorporated, USA. 3/98
1/13/98
Microchip received ISO 9001 Quality
System certification for its worldwide
headquarters, design, and wafer
fabrication facilities in January, 1997.
Our field-programmable PICmicro™
8-bit MCUs, Serial EEPROMs,
related specialty memory products
and development systems conform
to the stringent quality standards of
the International Standard
Organization (ISO).
Printed on recycled paper.
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DS40182A-page 108
1998 Microchip Technology Inc.