MICROCHIP PIC16F62X

PIC16F62X
PIC16F62X Silicon/Data Sheet Errata
The PIC16F62X (Rev. A) parts you have received conform functionally to the Device Data Sheet
(DS40300B), except for the anomalies described
below.
1. Module: I/O Ports
A read of the PORTB Data Direction Register
(TRISB) returns the Data Direction state on the
port pins themselves and not the contents of the
TRISB register latch.
FIGURE 1:
BLOCK DIAGRAM OF RB0/INT PIN
VDD
VDD
RBPU
Weak
P Pull-up
RB0/INT pin
Data Bus
WR PORTB
D
Q
VSS
CK
Data Latch
D
WR TRISB
Q
TTL
Input
Buffer
CK
TRIS Latch
Schmitt Trigger
Buffer
RD TRISB
Q
D
EN
EN
RD PORTB
INT Input
 2002 Microchip Technology Inc.
DS80073F-page 1
PIC16F62X
FIGURE 2:
BLOCK DIAGRAM OF RB1/TX/DT PIN
VDD
RBPU
P Weak Pull-up
Port/Peripheral Select(1)
USART Data Output
0
VDD
1
Data Bus
WR PORTB
D
Q
CK
Q
P
VDD
Data Latch
WR TRISB
D
Q
CK
Q
RB1/RX/DT
pin
N
VSS
TRIS Latch
VSS
RD TRISB
TTL
Input
Buffer
Peripheral OE(2)
Q
D
RD PORTB
EN
USART Receive Input
RD PORTB
Schmitt
Trigger
Note 1: Port/Peripheral select signal selects between port data and peripheral output.
2: Peripheral OE (output enable) is only active if peripheral select is active.
DS80073F-page 2
 2002 Microchip Technology Inc.
PIC16F62X
FIGURE 3:
BLOCK DIAGRAM OF RB2/TX/CK PIN
VDD
RBPU
P Weak Pull-up
VDD
Port/Peripheral Select(1)
USART TX/CK Output
0
VDD
1
Data Bus
WR PORTB
D
Q
CK
Q
RB2/TX/CK
pin
P
VSS
Data Latch
WR TRISB
D
Q
CK
Q
N
TRIS Latch
Vss
RD TRISB
TTL
Input
Buffer
Peripheral OE(2)
Q
D
RD PORTB
EN
EN
USART Slave Clock In
Schmitt
Trigger
RD PORTB
Note 1: Port/Peripheral select signal selects between port data and peripheral output.
2: Peripheral OE (output enable) is only active if peripheral select is active.
 2002 Microchip Technology Inc.
DS80073F-page 3
PIC16F62X
FIGURE 4:
BLOCK DIAGRAM OF THE RB3/CCP1 PIN
VDD
RBPU
P Weak Pull-up
Port/Peripheral Select(1)
PWM/Compare Output
0
VDD
1
Data Bus
WR PORTB
D
Q
CK
Q
P
VDD
Data Latch
D
WR TRISB
CK
RB3/CCP1
pin
Q
N
Q
VSS
TRIS Latch
Vss
RD TRISB
TTL
Input
Buffer
Q
D
RD PORTB
EN
EN
CCP Input
Schmitt
Trigger
RD PORTB
Note 1: Peripheral select is defined by CCP1M3:CCP1M0 (CCP1CON<3:0>).
DS80073F-page 4
 2002 Microchip Technology Inc.
PIC16F62X
FIGURE 5:
BLOCK DIAGRAM OF RB4/PGM PIN
VDD
RBPU
P Weak Pull-up
VDD
Data Bus
WR PORTB
D
Q
CK
Q
P
VDD
Data Latch
WR TRISB
D
Q
CK
Q
RB4/PGM
N
VSS
TRIS Latch
VSS
RD TRISB
LVP
RD PORTB
PGM Input
TTL
Input
Buffer
Schmitt
Trigger
Q
D
EN
Q1
Set RBIF
From other
RB<7:4> pins
Q
D
RD Port
EN
Q3
Note 1: The Low Voltage Programming disables the interrupt-on-change and the weak pull-ups on RB4.
 2002 Microchip Technology Inc.
DS80073F-page 5
PIC16F62X
FIGURE 6:
BLOCK DIAGRAM OF RB5 PIN
VDD
RBPU
Data Bus
D
Weak
P Pull-up
VDD
Q
RB5 pin
WR PORTB
CK
Data Latch
VSS
D
WR TRISB
Q
CK
TRIS Latch
TTL
Input
Buffer
RD TRISB
Q
D
RD PORTB
EN
Q1
Set RBIF
From other
RB<7:4> pins
Q
D
RD Port
EN
DS80073F-page 6
Q3
 2002 Microchip Technology Inc.
PIC16F62X
FIGURE 7:
BLOCK DIAGRAM OF RB6/T1OSO/T1CKI PIN
VDD
RBPU
P Weak Pull-up
VDD
Data Bus
WR PORTB
D
Q
CK
Q
P
VDD
Data Latch
WR TRISB
D
Q
CK
Q
RB6/
T1OSO/
T1CKI pin
N
VSS
TRIS Latch
VSS
RD TRISB
T1OSCEN
TTL
Input
Buffer
RD PORTB
TMR1 Clock
From RB7
Schmitt
Trigger
TMR1 Oscillator
Serial Programming Clock
Q
D
EN
Q1
Set RBIF
From other
RB<7:4> pins
Q
D
RD Port
EN
 2002 Microchip Technology Inc.
Q3
DS80073F-page 7
PIC16F62X
FIGURE 8:
BLOCK DIAGRAM OF THE RB7/T10SI PIN
VDD
RBPU
TMR1 Oscillator
P Weak Pull-up
To RB6
T1OSCEN
VDD
VDD
Data Bus
WR PORTB
D
Q
CK
Q
P
RB7/T1OSI
pin
Data Latch
WR TRISB
D
Q
CK
Q
VSS
N
TRIS Latch
Vss
RD TRISB
T10SCEN
TTL
Input
Buffer
RD PORTB
Serial Programming Input
Schmitt
Trigger
Q
D
EN
Q1
Set RBIF
From other
RB<7:4> pins
Q
D
RD Port
EN
DS80073F-page 8
Q3
 2002 Microchip Technology Inc.
PIC16F62X
2.
Module: Comparator Mode 1
Work around
Mode 1 allows AN2 to drive the (+) inputs of both
comparators. AN1 continues to drive the (-) input
of Comparator 2, but AN0 and AN3 can be
switched into the (-) input of Comparator 1. The
state of the CIS bit chooses which input is to be
connected to the comparator. When CIS = 0, AN0
is attached and the comparator functions correctly.
When CIS = 1, AN3 is not completely connected to
the comparator, resulting in incorrect behavior.
Option 1
Use the CCP toggle output on Compare Match
mode (CCP1CON<3.0> = “0010”).
Option 2
Since the problem occurs after two changes to the
Compare and Match mode, it is only necessary to
reset the CCP1CON register before the third
change is made. To remain backwards compatible
with earlier versions of the CCP module, always
reset the CCP1CON register when changing from
the clear output on Match mode to the set output
on Match mode, as described in the following
steps.
Mode 2 is also a Multiplex mode using the CIS bit.
This mode functions correctly.
All other modes are unaffected by this Errata.
3.
Module: Low Voltage Programming Mode
The high voltage override for low voltage programming does not operate as specified in the programming specification. In the Low Voltage
Programming (LVP) mode, the device can be programmed without using 12V on VPP (pin 4). However, when high voltage programming is used
while the part has low voltage programming
enabled, the Low Voltage mode is not overridden.
If RB4 goes high for any reason during high voltage programming with LVP enabled, the programming will be interrupted.
1.
2.
3.
5.
Ensure the RB3 data latch is set to 0.
Clear the CCP1CON register (clrf
CCP1CON).
Set the CCP1CON<3:0> bits to ”1000” for
set output on match.
Module: MCLR/RA5 in LVP Mode
When the PIC16F62X device has LVP enabled,
MCLR is always enabled, regardless of the
CONFIG register settings.
Work around
Pull RB4 (pin 10) to ground during the initial programming to prevent programming interruptions.
Once LVP has been disabled, it remedies this
issue with RB4.
4.
Module: CCP (Compare Mode)
The CCP1 output latch, observed on RB3/CCP1/
P1A, can change unexpectedly when the CCP
module is changed from a set output on match
(CCP1CON<3:0> = “1000”) to clear output on
match (CCP1CON<3:0> = “1001”) or vice versa.
This condition will occur following a CCP Reset at
the beginning of the third iteration of the following
sequence.
• CCPR1<3:0> is changed from “1001” to
“1000” or vice versa.
• The TMR1H:TMR1L register pair matches
the CCP1R1H:CCPR1L register pair.
Step 1 of the third iteration will cause the CCP1
output latch to immediately and erroneously
change to the inverse of the CCPR1<0> bit. This
gives the appearance of an inverted CCP
response to the third and subsequent compare
match events.
The apparent inverted response will persist until
the CCP1CON<3> bit is cleared (exiting Compare
mode). Interrupts always occur correctly on the
match condition. The error is only in the state of the
CCP1 output latch.
 2002 Microchip Technology Inc.
DS80073F-page 9
PIC16F62X
Clarifications/Corrections to the Data
Sheet:
In the Device Data Sheet (DS40300B), the following
clarifications and corrections should be noted.
1.
Module: T1SYNC (Register T1CON)
The bit T1SYNC in the Register T1CON (address
10h) should be asserted logic low (i.e., T1SYNC).
Table 4-1, page 15, and Table 10-2, page 65, of
DS40300B should be listed as follows:
2.
Module: ADEN (Register RCSTA)
The bit ADEN in Register RCSTA (address 18h),
Table 4-1, is misspelled. The correct spelling
should be ADDEN. This also appears in Figures
and text on pages 72, 79, 80, 81, 82, 83, 84, 85, 86
and 89.
TABLE 4-1:
Address
SPECIAL REGISTERS SUMMARY BANK0
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR Reset
Value on all
other
RESETS(1)
Bank 0
10h
T1CON
—
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
18h
RCSTA SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D 0000 -00x 0000 -00x
Legend: x = unknown, u = unchanged, - = unimplemented locations, read as ‘0’, q = value depends on condition,
shaded = unimplemented
Note 1: Other (non power-up) RESETS include MCLR Reset, Brown-out Detect and Watchdog Timer Reset during normal
operation.
TABLE 10-2:
Address
10h
Legend:
REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, AND TIMER1
Name
Bit 7
Bit 6
T1CON
—
—
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR
Value on
all other
RESETS
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by Capture and Timer1.
DS80073F-page 10
 2002 Microchip Technology Inc.
PIC16F62X
17.1
DC Characteristics: PIC16F62X-04 (Commercial, Industrial, Extended)
PIC16F62X-20 (Commercial, Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
–40°C ≤ TA ≤ +85°C for industrial and
0°C ≤ TA ≤ +70°C for commercial and
–40°C ≤ TA ≤ +125°C for extended
DC Characteristics
Param
No.
D001
Sym
VDD
Characteristic
Supply Voltage
(1)
Min
Typ†
Max
Units
3.0
—
5.5
V
Conditions
D002
VDR
RAM Data Retention Voltage
—
1.5*
—
V
Device in SLEEP mode
D003
VPOR
VDD start voltage to
ensure Power-on Reset
—
Vss
—
V
See section on Power-on Reset for details
D004
SVDD
VDD rise rate to ensure
Power-on Reset
0.05*
—
—
D005
VBOD
Brown-out Detect Voltage
3.65
3.65
4.0
—
4.35
4.4
V
V
BODEN configuration bit is set
BODEN configuration bit is set, Extended
D010
IDD
Supply Current(2)
—
—
—
—
—
—
—
—
4.0
—
—
—
0.7
2.0
7.0
6.0
2.0
10
mA
mA
mA
mA
mA
µA
FOSC = 4.0 MHz, VDD = 3.0
FOSC = 4.0 MHz, VDD = 5.5*
FOSC = 20.0 MHz, VDD = 5.5
FOSC = 20.0 MHz, VDD = 4.5*
FOSC = 10.0 MHz, VDD = 3.0*, Commercial
FOSC = 32 kHz, VDD = 3.0*
D020
IPD
Power-down Current(3)
—
—
—
—
—
—
—
—
2.2
5.0
9.0
30.0
µA
µA
µA
µA
VDD = 3.0, Commercial, Industrial
VDD = 4.5*, Commercial, Industrial
VDD = 5.5, Commercial, Industrial
VDD = 5.5, Extended
D022
∆IWDT
WDT Current(4)
—
6.0
Brown-out Detect Current(4)
Comparator Current for each
Comparator(4)
VREF Current(4)
—
—
75
30
20
25
125
50
µA
µA
µA
µA
VDD = 4.0V, Commercial, Industrial
VDD = 4.0V, Extended
BOD enabled, VDD = 5.0V
VDD = 4.0V
135
µA
VDD = 4.0V
D013
D014
D022A ∆IBOD
D023
∆ICOMP
D023A ∆IVREF
—
V/ms See section on Power-on Reset for details
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5.0V, 25°C, unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and
switching rate, oscillator type, internal code execution pattern and temperature also have an impact on the current consumption.
The test conditions for all IDD measurements in active Operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD, MCLR = VDD;
WDT disabled.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with
the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS.
4: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be added to the
base IDD or IPD measurement.
 2002 Microchip Technology Inc.
DS80073F-page 11
PIC16F62X
17.2
DC Characteristics: PIC16LF62X-04 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
–40°C ≤ TA ≤ +85°C for industrial and
0°C ≤ TA ≤ +70°C for commercial
Operating voltage VDD range as described in DC spec Table 17-1 and
Table 12-2
DC Characteristics
Param
No.
D001
Sym
VDD
Characteristic
Supply Voltage
(1)
Min
Typ†
Max
Units
2.0
—
5.5
V
Conditions
D002
VDR
RAM Data Retention Voltage
—
1.5*
—
V
Device in SLEEP mode
D003
VPOR
VDD start voltage to
ensure Power-on Reset
—
Vss
—
V
See section on Power-on Reset for details
D004
SVDD
VDD rise rate to ensure
Power-on Reset
0.05*
—
—
D005
VBOD
Brown-out Detect Voltage
3.65
4.0
4.35
V
D010
IDD
Supply Current(2)
—
—
—
—
—
—
—
—
4.0
—
—
—
0.6
0.7
7.0
6.0
2.0
TBD
mA
mA
mA
mA
mA
µA
FOSC = 4.0 MHz, VDD = 2.0
FOSC = 4.0 MHz, VDD = 5.5*
FOSC = 20.0 MHz, VDD = 5.5
FOSC = 20.0 MHz, VDD = 4.5*
FOSC = 10.0 MHz, VDD = 3.0, Commercial
FOSC = 32 kHz, VDD = 2.0*
D020
IPD
Power-down Current(2), (3)
—
—
—
—
1.98
9.0
µA
µA
VDD = 2.0
VDD = 5.5
D022
D022A
D023
∆IWDT
∆IBOD
∆ICOMP
WDT Current(4)
Brown-out Detect Current(4)
Comparator Current for each
Comparator(4)
VREF Current(4)
—
—
—
6.0
75
30
15
125
50
µA
µA
µA
VDD = 3.0V
BOD enabled, VDD = 5.0V
VDD = 3.0V
135
µA
VDD = 3.0V
D013
D014
∆IVREF
D023A
—
V/ms See section on Power-on Reset for details
BODEN configuration bit is cleared
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5.0V, 25°C, unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and
switching rate, oscillator type, internal code execution pattern and temperature also have an impact on the current
consumption.
The test conditions for all IDD measurements in active Operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD,
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with
the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS.
4: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be added to the
base IDD or IPD measurement.
DS80073F-page 12
 2002 Microchip Technology Inc.
PIC16F62X
17.3
DC Characteristics: PIC16F62X (Commercial, Industrial, Extended)
PIC16LF62X (Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
–40°C ≤ TA ≤ +85°C for industrial and
0°C ≤ TA ≤ +70°C for commercial and
–40°C ≤ TA ≤ +125°C for extended
Operating voltage VDD range as described in DC spec Table 17-1 and Table 12-2
DC Characteristics
Param.
No.
Sym
VIL
Characteristic
Min
Typ†
Max
Unit Conditions
—
0.8
0.15 VDD
V
0.2 VDD
V
0.2 VDD
V
Input Low Voltage
I/O ports:
D030
with TTL buffer
VSS
D031
with Schmitt Trigger input
VSS
D032
MCLR, RA4/T0CKI,OSC1 (in ER
mode)
VSS
—
OSC1 (in XT and HS)
VSS
—
0.3 VDD
V
OSC1 (in LP)
VSS
—
0.6 VDD-1.0
V
V
D033
VIH
Input High Voltage
I/O ports:
—
—
VDD
VDD
with Schmitt Trigger input
0.8 VDD
—
VDD
MCLR RA4/T0CKI
OSC1 (EC mode)
0.8 VDD
0.8 VDD
—
—
VDD
VDD
OSC1 (XT, HS and LP)
0.7 VDD
—
VDD
V
50
200
400
µA
±1.0
µA
VSS ≤ VPIN ≤ VDD, pin at hi-impedance
—
—
±0.5
µA
VSS ≤ VPIN ≤ VDD, pin at hi-impedance
with TTL buffer
D041
D042
D070
IPURB
IIL
VDD = 4.5V to 5.5V
otherwise
2.0V
.25 VDD + 0.8V
D040
D043
VDD = 4.5V to 5.5V
otherwise
PORTB weak pull-up current
V
V
VDD = 5.0V, VPIN = VSS
Current(1), (2)
Input Leakage
I/O ports (except PORTA)
D060
PORTA
D061
RA4/T0CKI
—
—
±1.0
µA
VSS ≤ VPIN ≤ VDD
D063
OSC1, MCLR
—
—
±5.0
µA
VSS ≤ VPIN ≤ VDD, XT, HS and LP osc
configuration
VOL
D080
Output Low Voltage
I/O ports
D083
OSC2/CLKOUT (ER only)
VOH
D090
OSC2/CLKOUT (ER only)
*D150
VOD
—
0.6
V
IOL=8.5 mA, VDD=4.5V, -40° to +85°C
—
0.6
V
IOL=7.0 mA, VDD=4.5V, +125°C
—
—
0.6
V
IOL=1.6 mA, VDD=4.5V, -40° to +85°C
—
—
0.6
V
IOL=1.2 mA, VDD=4.5V, +125°C
Output High Voltage(2)
I/O ports (except RA4)
D092
—
—
VDD-0.7
—
—
V
IOH=-3.0 mA, VDD=4.5V, -40° to +85°C
VDD-0.7
—
—
V
IOH=-2.5 mA, VDD=4.5V, +125°C
VDD-0.7
—
—
V
IOH=-1.3 mA, VDD=4.5V, -40° to +85°C
VDD-0.7
—
—
V
IOH=-1.0 mA, VDD=4.5V, +125°C
—
8.5*
V
RA4 pin PIC16F62X, PIC16LF62X
—
15
pF
In XT, HS and LP modes when external
clock used to drive OSC1
—
50
pF
Open Drain High Voltage
Capacitive Loading Specs on Output Pins
D100
COSC2 OSC2 pin
D101
Note
CIO
All I/O pins/OSC2 (in ER mode)
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
1:
The leakage current on the MCLR pin is strongly dependent on applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages.
Negative current is defined as coming out of the pin.
2:
 2002 Microchip Technology Inc.
DS80073F-page 13
PIC16F62X
3.
Module: I/O Ports (RA5/MCLR/VPP)
The following block diagram shown in Section 5,
Figure 5-5 is incorrect. The following figure should
be used instead.
FIGURE 5-5:
BLOCK DIAGRAM OF THE RA5/MCLR/VPP PIN
MCLRE
MCLR Circuit
MCLR Filter(1)
Program Mode
VDD
HV Detect
RA5/MCLR/VPP
VSS
Data Bus
Q
D
EN
RD Port
DS80073F-page 14
 2002 Microchip Technology Inc.
PIC16F62X
4.
Module: Comparator
The example given in Section 9, Example 9-1,
concerning “Initializing the Comparator Module” is
incorrect. The following code example should be
used instead.
EXAMPLE 9-1:
INITIALIZING COMPARATOR MODULE
BCF
BCF
CLRF
MOVLW
MOVWF
BSF
MOVLW
MOVWF
INTCON,GIE
INTCON,PEIE
PORTA
0X03
CMCON
STATUS,RP0
0x07
TRISA
BCF
CALL
STATUS,RP0
DELAY10
MOVF
BCF
BSF
BSF
BCF
BSF
BSF
CMCON,F
PIR1,CMIF
STATUS,RP0
PIE1,CMIE
STATUS,RP0
INTCON,PEIE
INTCON,GIE
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
Turn OFF Global Interrupts
Turn OFF Peripheral Interrupts
Init Port A
Init comparator mode
CM<2:0> = 011
Select BANK 1
Initialize Port A Direction
Set RA<2:0> as Inputs
RA<4:3> as outputs
TRIS<5> always reads ’0’
Select BANK 0
Wait 10us for comparator output to become valid
See Table 17-1 Parameter 301
Read CMCON to end change condition
Clear pending interrupts
Select BANK 1
Enable Comparator Interrupts
Select BANK 0
Enable Peripheral Interrupts
Global Interrupt Enable
; Insert Your code....
; Helper function is the Delay for 10us routine show below.
DELAY10
; burns 8 cycles + the call
goto $+1
; goto the next instruction
call retlbl ; goto the next instruction
retlbl return
; go back and burn 2 cycles
 2002 Microchip Technology Inc.
for 10 cycles or 10us at 4Mhz
and burn 2 cycles
and burn 2 more cycles
(actualy done 2x for 4 cycles consumed)
DS80073F-page 15
PIC16F62X
5.
Module: Data EEPROM
EXAMPLE 13-3:
The examples given in Section 13, concerning the
Data EEPROM are incorrect. The EEPROM registers are all located in Bank 1. The examples show
the registers in Bank 0 and Bank 1. The following
code examples should be used instead to use this
feature.
; after the write in complete (i.e. in the
write interrupt)
BSF
STATUS, RP0 ; Bank 1
MOVF
EEDATA, W
; load the last
written value into W
BSF
EECON1, RD
; start a read
;
; Is the value written (in W Reg) and
; read (in EEDATA) the same?
;
SUBWF
EEDATA, W
; the EEDATA has fresh
data
BTFSS
STATUS, Z
; Is the Zero flag set?
GOTO
WRITE_ERR
; NO, Write Error
; YES, Good Write
; continue program
EXAMPLE 13-1:
BSF
MOVLW
MOVWF
BSF
MOVF
BCF
DATA EEPROM READ
STATUS, RP0
CONFIG_ADDR
EEADR
EECON1, RD
EEDATA, W
STATUS, RP0
EXAMPLE 13-2:
;
;
;
;
;
;
Bank 1
Address to read
EE Read
W = EEDATA
Bank 0
DATA EEPROM WRITE
; set up the data and the address
BSF
STATUS, RP0 ; Bank 1
MOVLW
CONFIG_ADDR ;
MOVWF
EEADR
; Address to write
MOVLW
CONFIG_DATA ;
MOVWF
EEDATA
; Data to write
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BCF
6.
DATA EEPROM VERIFY
Module: Comparator
Under Section 9.5 Comparator Outputs, in the
fourth sentence, “When the CM<2:0> = 110 or
001, multiplexors...”, remove “or 001”.
; perform the write
operation
EECON1, WREN ; Enable Write
INTCON, GIE ; Disable INTs
055h
;
EECON2
; Write 55
0AAh
;
EECON2
; Write AA
EECON1, WR
; Set WR bit
STATUS, RP0 ; Bank 0
DS80073F-page 16
 2002 Microchip Technology Inc.
PIC16F62X
REVISION HISTORY
Rev A Document (6/00)
Original errata document.
Rev B Document (11/00)
Issue 3 (CCP Compare Mode), Table 1 and 2 were
added (page 2).
Under the Clarifications/Corrections Section, Item 1,
Table 15-12 was updated with additional information
(page 3).
Under the Clarifications/Corrections Section, the
following Items were added:
Rev C Document (6/01)
Issues 2 and 3 were added.
Under Clarifications/Corrections, Items 2 and 3 were
changed and Item numbers were renumbered
accordingly.
Rev D Document (9/01)
Item 3 was rewritten (page 9).
Under the Clarifications/Corrections to the Data Sheet
Section, the following items were changed:
Item 2, Tables 17.1 and 17.2, were updated with minor
changes (page 11 and page 12).
Item 6 was added (page 16).
Rev E Document (2/02)
Item 4 was added, MCLR/RA5 in LVP mode (page 9).
Rev F Document (4/02)
Under Clarifications/Corrections, Item 2, Tables 17-1,
17.2 and 17.3 were updated with minor changes
(pages 11, 12 and 13).
 2002 Microchip Technology Inc.
DS80073F-page 17
PIC16F62X
NOTES:
DS80073F-page 18
 2002 Microchip Technology Inc.
Note the following details of the code protection feature on PICmicro® MCUs.
•
•
•
•
•
•
The PICmicro family meets the specifications contained in the Microchip Data Sheet.
Microchip believes that its family of PICmicro microcontrollers is one of the most secure products of its kind on the market today,
when used in the intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the PICmicro microcontroller in a manner outside the operating specifications contained in the data sheet.
The person doing so may be engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable”.
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of
our product.
If you have any further questions about this matter, please contact the local sales office nearest to you.
Information contained in this publication regarding device
applications and the like is intended through suggestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microchip Technology Incorporated with respect
to the accuracy or use of such information, or infringement of
patents or other intellectual property rights arising from such
use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with
express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property
rights.
Trademarks
The Microchip name and logo, the Microchip logo, FilterLab,
KEELOQ, microID, MPLAB, PIC, PICmicro, PICMASTER,
PICSTART, PRO MATE, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
dsPIC, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, microPort,
Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM,
MXDEV, MXLAB, PICC, PICDEM, PICDEM.net, rfPIC, Select
Mode and Total Endurance are trademarks of Microchip
Technology Incorporated in the U.S.A.
Serialized Quick Turn Programming (SQTP) is a service mark
of Microchip Technology Incorporated in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2002, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999. The
Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs and microperipheral
products. In addition, Microchip’s quality
system for the design and manufacture of
development systems is ISO 9001 certified.
 2002 Microchip Technology Inc.
DS80073F - page 19
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DS80073F-page 20
 2002 Microchip Technology Inc.