PLL102-05 Low Skew Output Buffer FEATURES • • • • • • • Frequency range 25 ~ 60MHz. Internal phase locked loop will allow spread spectrum modulation on reference clock to pass to the outputs (up to 100kHz SST modulation). Zero input - output delay. Less than 700 ps device - device skew. Less than 250 ps skew between outputs. Less than 150 ps cycle - cycle jitter. Output Enable function tri-state outputs. 3.3V operation. Available in 8-Pin 150mil SOIC. REF 1 CLK2 2 CLK1 3 GND 4 PLL 102-05 • • PIN CONFIGURATION 8 CLKOUT 7 CLK4 6 VDD 5 CLK3 Remark If REF clock is stopped for more than 10us after it has already been provided to the chip, and after power-up, the output clocks will disappear. In that instance, a full power-up reset is required in order to reactivate the output clocks. DESCRIPTION The PLL102-05 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOIC package. It has four outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the input of the PLL. Since the skew between the input and output is less than ±350 ps, the device acts as a zero delay buffer. BLOCK DIAGRAM REF PLL CLKOUT CLK1 CLK2 CLK3 CLK4 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/22/05 Page 1 PLL102-05 Low Skew Output Buffer PIN DESCRIPTIONS Name Number Type REF 1 1 I CLK2 2 CLK1 2 GND CLK3 2 VDD CLK4 2 CLKOUT 2 2 3 4 5 6 7 8 O O P O P O O Description Input reference frequency. Spread spectrum modulation on this signal will be passed to the output (up to 100kHz SST modulation). Buffered clock output. Buffered clock output. Ground. Buffered clock output. 3.3V Power Supply. Buffered clock output. Buffered clock output. Internal feed back on this pin. Notes: 1: Weak pull-down. 2: Weak pull-down on all outputs. ELECTRICAL SPECIFICATIONS 1. Absolute Maximum Ratings PARAMETERS SYMBOL Supply Voltage Input Voltage, dc Output Voltage, dc Storage Temperature Ambient Operating Temperature* Junction Temperature Lead Temperature (soldering, 10s) ESD Protection, Human Body Model MIN. V DD VI VO TS TA TJ -0.5 -0.5 -65 -40 MAX. UNITS 4.6 V DD +0.5 V DD +0.5 150 85 125 260 2 V V V °C °C °C °C kV Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. * Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only. 2. Electrical Characteristics PARAMETERS SYMBOL Supply Voltage Input Low Voltage Input High Voltage Input Low Current Input High Current Output Low Voltage Output High Voltage Power Down Supply Current V DD V IL V IH I IL I IH V OL V OH I DD Supply Current I DD CONDITIONS MIN. TYP. MAX. UNITS 3.63 0.8 V V V 19 0.10 0.25 2.9 0.3 50.0 100.0 0.4 µA µA V V 50.0 µA 35 45 mA 2.97 2.0 V IN = 0V V IN = V DD I OL = 50mA I OH = 50mA REF = 0MHz Unloaded outputs at 133MHz, SEL inputs at V DD or GND 2.4 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/22/05 Page 2 PLL102-05 Low Skew Output Buffer 3. Switching Characteristics PARAMETERS SYMBOL Output Frequency DESCRIPTION MIN. t1 Duty Cycle ( t2 ÷ t1 ) Dt1 Duty Cycle ( t2 ÷ t1 ) Dt2 Rise Time Tr Fall Time Tf Output to Output Skew T skew Delay, REF Rising Edge to CLKOUT Rising Edge T delay Device to Device Skew T dsk-dsk Cycle to Cycle Jitter T cyc-cyc PLL Lock Time T lock Jitter; Absolute Jitter Jitter; 1-sima T jabs T j1-s TYP. 25 Measured at 1.4V, C L =30pF, F out = 60MHz Measured at 1.4V Measured between 0.8V and 2.0V, C L =30pF Measured between 2.0V and 0.8V, C L =30pF All outputs equally loaded, C L =20pF MAX. UNITS 60 MHz 40.0 50.0 60.0 % 45.0 50.0 55.0 % 1.2 1.5 ns 1.2 1.5 ns 250 ps 0 ±350 ps 0 700 ps 150 ps 1.0 ms 100 20 ps ps Measured at 1.4V Measured at V DD /2 on the CLKOUT pins of devices Loaded outputs Stable power supply, valid clock presented on REF pin At 10,000 cycles, C L =30pF At 10,000 cycles, C L =30pF 70 10 SWITCHING WAVEFORMS Duty Cycle Timing Output - Output Skew t1 t2 1.4V 1.4V Output 1.4V 1.4V 1.4V Output TSKEW 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/22/05 Page 3 PLL102-05 Low Skew Output Buffer SWITCHING WAVE FORMS All Outputs Rise/Fall Time Output 3.3V 2.0V 2.0V 0.8V 0.8V tr 0V tf Input to Output Propagation Delay Input VDD/2 Output VDD/2 Tdelay Device to Device Skew Device1 CLKOUT Device2 CLKOUT VDD/2 VDD/2 Tdsk - dsk 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/22/05 Page 4 PLL102-05 Low Skew Output Buffer Output-Output Skew The skew between CLKOUT and the CLK(1-4) outputs is not dynamically adjusted by the PLL. Since CLKOUT is one of the inputs to the PLL, zero phase difference is maintained from REF to CLKOUT. If all outputs are equally loaded, zero phase difference will maintained from REF to all outputs. If applications requiring zero output-output skew, all the outputs must equally loaded. If the CLK(1-4) outputs are less loaded than CLKOUT, CLK(1-4) outputs will lead it; if the CLK(0-4) is more loaded than CLKOUT, CLK(1-4) will lag the CLKOUT. Since the CLKOUT and the CLK(1-4) outputs are identical, they all start at the same time, but difference loads cause them to have different rise times and different times crossing the measurement thresholds. REF REF CLKOUT CLKOUT CLK(1-4) CLK(1-4) Zero Delay REF input and all outputs loaded equally Advanced REF input and CLK(1-4) outputs loaded equally, with CLK(1-4) less loaded than CLKOUT. REF CLKOUT CLK(1-4) Delayed REF input and CLK(1-4) outputs loaded equally, with CLK(1-4) more loaded than CLKOUT. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/22/05 Page 5 PLL102-05 Low Skew Output Buffer PACKAGE INFORMATION 8 PIN Narrow SOIC ( mm ) SOIC Symbol Min. Max. A 1.55 1.73 A1 0.15 0.18 B 0.35 0.49 C D 0.19 4.80 0.25 4.98 E 3.81 3.99 H 5.84 6.20 L 0.41 e E H D 0.89 A A 1 1.27 BSC C L B e ORDERING INFORMATION For part ordering, please contact our Sales Department: 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER The order number for this device is a combination of the following: Device number, Package type and Operating temperature range PLL102-05 X X X X NONE= TUBE R=TAPE AND REEL PART NUMBER NONE=NORMAL PACKAGE L=GREEN PACKAGE TEMPERATURE C=COMMERCIAL, I=INDUSTRIAL PACKAGE TYPE S=SOIC Part / Order Number PLL102-05SC-R PLL102-05SC PLL102-05SCL-R PLL102-05SCL Marking P102-05SC P102-05SC P102-05SCL P102-05SCL Package Option SOIC SOIC SOIC SOIC - Tape and Reel – Tube - Tape and Reel – Tube Temperature 0 0 0 0 to to to to +70ﾟC +70ﾟC +70ﾟC +70ﾟC PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/22/05 Page 6