128K x 32 SRAM Module PUMA 2/67S4000/A-020/025/35 Elm Road, West Chirton, NORTH SHIELDS, Tyne & Wear NE29 8SE, England Tel. +44 (0191) 2930500 Fax. +44 (0191) 2590997 Description Features Available in PGA (PUMA 2) and JLCC (PUMA 67) footprints the PUMA **S4000 is a 4 Mbit SRAM module, user configurable as 128K x 32, 256K x 16 or 512K x 8. The device is available with fast access times of 20, 25 and 35ns and may be screened in accordance with MIL-STD-883C. • • • • • • • • • Issue 4.4 : April 2001 4 Megabit SRAM module. Fast Access Times of 20/25/35 ns. Output Configurable as 32 / 16 / 8 bit wide. Upgradeable footprint. Operating Power 3740 / 2310 / 1595 mW (Max). Low Power Standby 880 mW (Max). TTL Compatible Inputs and Outputs. May be screened in accordance with MIL-STD-883. PUMA 2 - 66 pin ceramic PGA. PUMA 67 - 68 pin ceramic JLCC. Block Diagram Block Diagram PUMA 2S4000, 67S4000A, 67S4000B PUMA 67S4000 A0~A16 A0-A16 OE WE OE WE4 WE3 WE2 WE1 128Kx8 SRAM 128Kx8 SRAM 128Kx8 SRAM 128Kx8 SRAM CS1 CS2 CS3 CS4 D0~7 D8~15 D16~23 D24~31 128Kx8 SRAM 128Kx8 SRAM 128Kx8 SRAM 128Kx8 SRAM CS1 CS2 CS3 CS4 D0-7 D8-15 D16-23 D24-31 Pin Functions A0~A16 CS1~4 OE GND Address Input Chip Select Output Enable Ground D0~D31 WE1~4 Vcc Data Inputs/Outputs Write Enables Power (+5V) PUMA 2/67/77S4000/A - 020/025/35 Issue 4.4 : April 2001 DC OPERATING CONDITIONS Absolute Maximum Ratings (1) Voltage on any pin relative to GND(2) Power Dissipation Storage Temperature VT PT TSTG -0.5V to +7.0 4 -65 to +150 V W ° C Notes (1) Stresses above those listed may cause permanent damage. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Recommended Operating Conditions Supply Voltage Input High Voltage Input Low Voltage Operating Temperature VCC VIH VIL TA TAI TAM min typ max 4.5 2.2 -0.5 0 -40 -55 5.0 - 5.5 6.0 0.8 70 85 125 V V V ° C ° C (Suffix I) ° C (Suffix M, MB) DC Electrical Characteristics (VCC=5V±10%,TA=-55°C to +125°C) Parameter Symbol Test Condition min typ Input Leakage Current ILI1 -8 - 8 µA -8 - 8 µA Output Leakage Current ILO VIN=0V to VCC (1) CS =VIH or OE=VIH, VI/O=0V to VCC max Unit WE=VIL Operating Supply Current 32 bit ICC32 Min cycle,duty=100%,II/O=0mA,CS=VIL - - 680 mA 16 bit ICC16 As above - - 420 mA 8 bit ICC8 Min cycle,duty=100%,II/O=0mA,CS=VIL - - 290 mA ISB1 CS ≥VIH VCC = 5.5V - - 160 mA Output Voltage Low VOL IOL = 8.0mA - - 0.4 V Output Voltage High VOH IOH = -4.0mA 2.4 - - V Standby Supply Current (TTL) (1) Notes: (1) CS and WE above are accessed through CS1~4 and WE1~4 respectively. These inputs must be operated simultaneously for 32 bit mode, in pairs for 16 bit mode and singly for 8 bit mode. Capacitance (VCC=5V±10%,TA=25°C) Note: (1) On the standard module, WE = 30 pF max. Parameter Input Capacitance Address, OE WE1~4(1), CS1~4 I/O Capacitance D0~D31 Symbol CIN1 CIN2 CI/O Test Condition typ VIN =0V VIN =0V VI/O=0V - These parameters are calculated, not measured. 2 max Unit 30 16 30 pF pF pF (8 bit mode) PUMA 2/67/77S4000/A - 020/025/35 Issue 4.4 : April 2001 Operating Modes The table below shows the logic inputs required to control the operating modes of each of the SRAMs on the modules. Mode CS OE WE Not Selected 1 X X Output Disable 0 1 Read 0 Write 0 VCC Current I/O Pin Reference Cycle ISB1,ISB2 High Z Power Down 1 ICC High Z - 0 1 ICC DOUT Read Cycle X 0 ICC DIN Write Cycle 1 = VIH, 0 = VIL, X = Don't Care Note: CS above is accessed through CS1~4 (and WE by WE1~4 on the PUMA 2S4000, 67S4000A, 77S4000A). For correct operation, CS1~ 4 (and WE1~4) must operate simultaneously for 32 bit operation, in pairs for 16 bit operation, or singly for 8 bit operation. AC Test Conditions Output Load I/O Pin *Input pulse levels: 0.0V to 3.0V *Input rise and fall times: 3 ns *Input and Output timing reference levels: 1.5V *Vcc=5V±10% *PUMA module is tested in 32 bit mode. 166 Ω 1.76V 30pF 3 PUMA 2/67/77S4000/A - 020/025/35 Issue 4.4 : April 2001 AC OPERATING CONDITIONS Read Cycle Parameter 020 max Read Cycle Time tRC 20 - 25 - 35 - ns Address Access Time tAA - 20 - 25 - 35 ns Chip Select Access Time tACS - 20 - 25 - 35 ns Output Enable to Output Valid tOE - 9 - 8 - 12 ns Output Hold from Address Change tOH 5 - 5 - 5 - ns Chip Selection to Output in Low Z tCLZ 6 - 5 - 5 - ns tOLZ 0 - 0 - 0 - ns Chip Deselection to Output in High Z tCHZ 0 9 - 15 - 15 ns 0 9 - 15 - 15 ns (3) Output Disable to Output in High Z (3) tOHZ min 35 max Units min Output Enable to Output in Low Z min 025 max Symbol Write Cycle 020 025 35 Parameter Symbol min max min max min max Unit Write Cycle Time tWC 20 - 25 - 35 - ns Chip Selection to End of Write tCW 15 - 16 - 20 - ns Address Valid to End of Write tAW 15 - 16 - 20 - ns Address Setup Time tAS 0 - 0 - 0 - ns Write Pulse Width tWP 15 - 15 - 20 - ns Write Recovery Time tWR 0 - 5 - 5 - ns Data to Write Time Overlap tDW 0 15 10 - 15 - ns Output Active from End of Write tOW 15 - 3 - 3 - ns Data Hold from Write Time tDH 2* - 2* - 2* - ns Write to Output High Z tWHZ 5 - 0 10 0 10 ns * Note : Only applies to PUMA 67S4000/A otherwise tDH (min) = 0 4 PUMA 2/67/77S4000/A - 020/025/35 Issue 4.4 : April 2001 Read Cycle Timing Waveform (1,2) t RC A0~A16 t AA OE t OE t OH t OLZ CS1~4 t CLZ t ACS t CHZ(3) t OHZ(3) High-Z D0~31 Data Valid Notes: (1) During the Read Cycle, WE is high for the modules. (2) Address valid prior to or coincident with CS transition Low. (3) tCHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. These parameters are sampled and not 100% tested. Write Cycle No.1 Timing Waveform t WC A0~A16 OE t AS(3) t AW tWR t CW(4) (2) (6) CS1~4 t WP(1) WE1~4 t OHZ(3,9) D0~31out D0~31in t OW High-Z t DW High-Z 5 t DH PUMA 2/67/77S4000/A - 020/025/35 Issue 4.4 : April 2001 Write Cycle No.2 Timing Waveform (5) t WC A0~A16 tCW CS1~4 (4) (6) t AW t WR(2) t WP(1) WE1~4 t AS(3) t OH t WHZ(3,9) t OW D0~31out t DW D0~31in (8) (7) High-Z tDH High-Z AC Characteristics Notes (1) A write occurs during the overlap (tWP) of a low CS and a low WE. (2) tWR is measured from the earlier of CS or WE going high to the end of write cycle. (3) During this period, I/O pins are in the output state. Input signals out of phase must not be applied. (4) If the CS low transition occurs simultaneously with the WE low transition or after the WE low transition, outputs remain in a high impedance state. (5) OE is continuously low. (OE=VIL) (6) DOUT is in the same phase as written data of this write cycle. (7) DOUT is the read data of next address. (8) If CS is low during this period, I/O pins are in the output state. Input signals out of phase must not be applied. (9) tWHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. These parameters are sampled and not 100% tested. WE above refers to WE1~4 on the PUMA 2S4000, 67S4000A AND 77S4000A. 6 PUMA 2/67/77S4000/A - 020/025/35 Issue 4.4 : April 2001 Package Details PUMA 67S4000 25.40 (1.000) sq. 1.35 (0.053) 0.94 (0.037) 24.89 (0.980) sq. 24.99 (0.984) sq. 24.49 (0.964) sq. 0.10 (0.004) 5.13 (0.202) max R=0.76 (0.030) typ. 23.11 (0.910) sq. 24.13 (0.950) sq. 0.64 (0.025) min 20.07 (0.790) sq. 0.43 (0.017) typ. 20.57 (0.810) sq. 21.08 (0.830) 21.37 (0.840) 1.27 (0.050) typ. PUMA 2S4000 27.69 (1.090) square 2.54 (0.010) 4.83 (0.190) 4.32 (0.170) 27.08 (1.066) square 15.24 (0.60) typ 3.81 (0.150) ref 0.53 (0.021) 0.38 (0.015) 1.27 (0.050) 1.27 (0.050) 1.66 (0.026) LEAD FINISH IS 300 INCH MINIMUM SOLDER OVER 50 TO 350 INCH NICKEL 6.86 (0.270) max 1.52 (0.060) 1.02 (0.040) 7 2.54 (0.010) 10.67 (0.420) 10.16 (0.400) PUMA 2/67/77S4000/A - 020/025/35 Issue 4.4 : April 2001 Pin Definitions 2 1 68 67 66 65 64 63 62 61 A9 A10 3 Vcc 4 A8 CS3 GND 5 A7 A5 6 CS4 A4 7 WE1 A6 A3 8 A1 A0 9 A2 NC 1 68 67 66 65 64 63 62 61 A10 2 Vcc 3 A9 4 A8 CS3 GND 5 A7 A5 6 CS4 A4 7 WE1 A6 A3 8 A1 A0 9 PUMA 67S4000A A2 NC PUMA 67S4000 D0 10 60 D16 D0 10 60 D16 D1 11 59 D17 D1 11 59 D17 D2 12 58 D18 D2 12 58 D18 D3 13 57 D19 D3 13 57 D19 D4 14 56 D20 D4 14 56 D20 D5 15 55 D21 D5 15 55 D21 D6 16 54 D22 D6 16 54 D22 D7 17 53 D23 D7 17 53 D23 GND 18 52 GND GND 18 52 GND D8 19 51 D24 D8 19 51 D24 D9 20 50 D25 D9 20 50 D25 D10 21 49 D26 D10 21 D11 22 48 D27 D11 D12 23 47 D28 D13 24 46 D29 D14 25 45 D15 26 44 49 D26 22 48 D27 D12 23 47 D28 D13 24 46 D29 D30 D14 25 45 D30 D31 D15 26 44 D31 NC A0 A1 A2 A3 A4 A5 /CS3 GND /CS4 /WE1 A6 A7 A8 A9 A10 Vcc 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 10 60 11 59 12 58 13 57 14 56 15 55 16 54 17 53 VIEW 18 52 FROM 19 51 20 50 ABOVE 21 49 22 48 23 47 24 46 25 45 26 44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 PUMA 67S4000B NC GND NC WE4 WE2 WE3 NC CS2 OE CS1 PUMA 2S4000 D16 D17 D18 D19 D20 D21 D22 D23 GND D24 D25 D26 D27 D28 D29 D30 D31 1 12 23 34 45 56 D8 D15 D24 35 VCC D31 2 WE2 13 46 57 D9 CS2 D25 CS4 D30 8 24 3 14 D14 25 36 47 58 D10 4 GND 15 D13 26 D26 37 WE4 48 D29 59 A13 D11 D12 A6 D27 D28 5 16 27 38 49 60 A14 6 A10 17 OE A7 A3 50 A0 61 A15 7 A11 18 NC A16 A12 WE1 8 19 30 NC VCC 20 D7 31 A9 42 WE3 53 D23 D0 10 CS1 D6 D16 CS3 D22 21 32 43 54 65 D1 11 NC D5 D17 GND D21 22 33 44 55 66 D2 D3 D4 D18 D19 D20 9 Vcc A11 A12 A13 A14 A15 A16 /CS1 /OE /CS2 NC /WE2 /WE3 /WE4 NC NC NC D0 D1 D2 D3 D4 D5 D6 D7 GND D8 D9 D10 D11 D12 D13 D14 D15 A16 Vcc NC GND NC NC NC NC NC CS2 OE CS1 A16 A15 A14 A13 A12 A11 PUMA 67S4000B A15 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 Vcc ABOVE A14 ABOVE FROM A13 FROM VIEW A12 VIEW PUMA 67S4000A A11 PUMA 67S4000 28 29 VIEW FROM ABOVE 39 NC A4 A1 40 51 62 A8 A5 41 52 A2 63 64 PUMA 2/67/77S4000/A - 020/025/35 Issue 4.4 : April 2001 SCREENING Military Screening Procedure MultiChip Screening Flow for high reliability product is in accordance with Mil-883 method 5004 . MB MULTICHIP MODULE SCREENING FLOW SCREEN TEST METHOD LEVEL Visual and Mechanical Internal visual Temperature cycle Constant acceleration 2010 Condition B or manufacturers equivalent 1010 Condition C (10 Cycles,-65oC to +150oC) 2001 Condition B (Y1 & Y2) (10,000g) 100% 100% 100% Pre-Burn-in electrical Burn-in Per applicable device specifications at TA=+25oC TA=+125oC,160hrs minimum. 100% 100% Burn-In Final Electrical Tests Per applicable Device Specification Static (DC) a) @ TA=+25oC and power supply extremes b) @ temperature and power supply extremes 100% 100% Functional a) @ TA=+25oC and power supply extremes b) @ temperature and power supply extremes 100% 100% Switching (AC) a) @ TA=+25oC and power supply extremes b) @ temperature and power supply extremes 100% 100% Percent Defective allowable (PDA) Calculated at post-burn-in at TA=+25oC Hermeticity 1014 Fine Gross Condition A Condition C Quality Conformance Per applicable Device Specification External Visual 2009 Per vendor or customer specification 9 10% 100% 100% Sample 100% PUMA 2/67/77S4000/A - 020/025/35 Issue 4.4 : April 2001 Ordering Information PUMA 2S4000ALMB-020 Speed 020 025 35 Temp. range/screening Blank I M MB = 20 ns = 25 ns = 35 ns = = = = Commercial Temperature Industrial Temperature Military Temperature processed in accordance with MIL-STD-883 Power Consumption Blank = Standard Power WE Option Blank = Single WE (PUMA 67 / 77 only) WE1~4 (PUMA 2 only) A = WE1~4 (PUMA 67 / 77 only) B = Pinout variant 4000 = 128Kx 32, user confiurable as 256K x 16 and 512K x 8 Organisation Technology Package S = SRAM MEMORY PUMA 2 = JEDEC 66 Pin Ceramic PGA package PUMA 67 = JEDEC 68 J-Leaded Ceramic Surface Mount package Note : Although this data is believed to be accurate, the information contained herein is not intended to, and does not create any warranty of merchantibility or fitness for a particular purpose. Our products are subject to a constant process of development. Data may be changed at any time without notice. Products are not authorised for use as critical components in life support devices without the express written approval of a company director. 10