INFINEON Q67100

Standard EEPROM ICs
SLx 24C164/P
16 Kbit (2048 × 8 bit)
Serial CMOS-EEPROM with
I2C Synchronous 2-Wire Bus
and Page Protection Mode™
Data Sheet 1998-07-27
SLx 24C164/P
Revision History:
Current Version: 1998-07-27
Previous Version:
06.97
Page
Page
(in previous (in current
Version)
Version)
Subjects (major changes since last revision)
3
3
Text was changed to “Typical programming time 5 ms for up to
16 bytes”.
5
5
WP = VCC protects the upper half entire memory.
11, 12
11, 12
The erase/write cycle is finished latest after 10 8 ms.
15
15
Figure 11: second command byte is a CSR and not CSW.
21
21
The write or erase cycle is finished latest after 10 4 ms.
19
24
“Capacitive load …” were added.
25
25
Some timings were changed.
25
25
The line “erase/write cycle” was removed.
25
25
Chapter 8.4 “Erase and Write Characteristics” has been added.
I2C Bus
Purchase of Siemens I2C components conveys the license under the Philips I2C patent to use the components in
the I2C system provided the system conforms to the I2C specifications defined by Philips.
Edition 1998-07-27
Published by Siemens AG,
Bereich Halbleiter, MarketingKommunikation, Balanstraße 73,
81541 München
© Siemens AG 1998.
All Rights Reserved.
Attention please!
As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes
and circuits implemented within components or assemblies.
The information describes the type of component and shall not be considered as assured characteristics.
Terms of delivery and rights to change design reserved.
For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies
and Representatives worldwide (see address list).
Due to technical requirements components may contain dangerous substances. For information on the types in question please contact
your nearest Siemens Office, Semiconductor Group.
Siemens AG is an approved CECC manufacturer.
Packing
Please use the recycling operators known to you. We can also help you – get in touch with your nearest sales office. By agreement we
will take packing material back, if it is sorted. You must bear the costs of transport.
For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred.
Components used in life-support devices or systems must be expressly authorized for such purpose!
Critical components1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2 with the express
written approval of the Semiconductor Group of Siemens AG.
1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the
failure of that life-support device or system, or to affect its safety or effectiveness of that device or system.
2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered.
16 Kbit (2048 × 8 bit) Serial CMOS
EEPROMs, I2C Synchronous 2-Wire Bus,
Page Protection Mode™
SLx 24C164/P
Features
• Data EEPROM internally organized as
2048 bytes and 128 pages × 16 bytes
• Page protection mode, flexible page-by-page
hardware write protection
– Additional protection EEPROM of 128 bits, 1 bit
per data page
P-DIP-8-4
– Protection setting for each data page by writing its
protection bit
– Protection management without switching WP pin
• Low power CMOS
• VCC = 2.7 to 5.5 V operation
• Two wire serial interface bus, I2C-Bus
compatible
• Three chip select pins to address 8 devices
• Filtered inputs for noise suppression with
P-DSO-8-3
Schmitt trigger
• Clock frequency up to 400 kHz
• High programming flexibility
– Internal programming voltage
– Self timed programming cycle including erase
– Byte-write and page-write programming, between 1 and 16 bytes
– Typical programming time 5 ms for up to 16 bytes
• High reliability
– Endurance 106 cycles1)
– Data retention 40 years1)
– ESD protection 4000 V on all pins
• 8 pin DIP/DSO packages
• Available for extended temperature ranges
– Industrial:
− 40 °C to + 85 °C
– Automotive:
− 40°C to + 125 °C
1)
Values are temperature dependent, for further information please refer to your Siemens Sales office.
Semiconductor Group
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1998-07-27
SLx 24C164/P
Ordering Information
Type
Ordering Code Package
Temperature
Voltage
SLA 24C164-D/P
Q67100-H3504 P-DIP-8-4
– 40 °C … + 85 °C 4.5 V...5.5 V
SLA 24C164-S/P
Q67100-H3499 P-DSO-8-3 – 40 °C … + 85 °C 4.5 V...5.5 V
SLA 24C164-D-3/P
Q67100-H3502 P-DIP-8-4
SLA 24C164-S-3/P
Q67100-H3498 P-DSO-8-3 – 40 °C … + 85 °C 2.7 V...5.5 V
SLE 24C164-D/P
Q67100-H3503 P-DIP-8-4
SLE 24C164-S/P
Q67100-H3497 P-DSO-8-3 – 40°C … + 125 °C 4.5 V...5.5 V
– 40 °C … + 85 °C 2.7 V...5.5 V
– 40°C … + 125 °C 4.5 V...5.5 V
Other types are available on request
– Temperature range (– 55 °C … + 150 °C)
– Package (die, wafer delivery)
1
Pin Configuration
P-DIP-8-4
P-DSO-8-3
CS0
1
8
V CC
CS1
2
7
WP
CS2
3
6
SCL
VSS
4
5
SDA
CS0
CS1
CS2
VSS
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
IEP02124
IEP02125
Figure 1
Pin Configuration (top view)
Pin Definitions and Functions
Table 1
Pin No.
Symbol
Function
1, 2, 3
CS0, CS1, CS2
Chip select inputs
4
VSS
Ground
5
SDA
Serial bidirectional data bus
6
SCL
Serial clock input
7
WP
Write protection input
8
VCC
Supply voltage
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SLx 24C164/P
Pin Description
Serial Clock (SCL)
The SCL input is used to clock data into the device on the rising edge and to clock data
out of the device on the falling edge.
Serial Data (SDA)
SDA is a bidirectional pin used to transfer addresses, data or control information into the
device or to transfer data out of the device. The output is open drain, performing a wired
AND function with any number of other open drain or open collector devices. The SDA
bus requires a pull-up resistor to VCC.
Chip Select (CS0, CS1, CS2)
The CS0, CS1 and CS2 pins are chip select inputs either hard wired or actively driven
to VCC or VSS. These inputs allow the selection of one of eight possible devices sharing
a common bus.
Write Protection (WP)
WP switched to VSS allows normal read/write operations.
WP switched to VCC protects the entire EEPROM against changes (hardware write
protection).
Additionally write protection is managed by a protection bit associated to each page.
(refer to chapter 7 Page Protection ModeTM)
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SLx 24C164/P
2
Description
The SLx 24C164/P device is a serial electrically erasable and programmable read only
memory (EEPROM), organized as 2048 × 8 bit. The data memory is divided into
128 pages. The 16 bytes of a page can be programmed simultaneously. Each page may
be protected individually against changes by its associated protection bit.
The device conforms to the specification of the 2-wire serial I2C-Bus. Three chip select
pins allow the addressing of 8 devices on the I2C-Bus. Low voltage design permits
operation down to 2.7 V with low active and standby currents. All devices have a
minimum endurance of 106 erase/write cycles.
The device operates at 5.0 V ± 10% with a maximum clock frequency of 400 kHz and at
2.7 ... 4.5 V with a maximum clock frequency of 100 kHz. The device is available as 5 V
type (VCC = 4.5 … 5.5 V) with two temperature ranges for industrial and automotive
applications and as 3 V type (VCC = 2.7 … 5.5 V) for industrial applications. The
EEPROMs are mounted in eight-pin DIP and DSO packages or are also supplied as
chips.
V SS
V CC
CS0
CS1
CS2
Chip Address
Control
Logic
WP
Programming
Control
H.V. Pump
Start/
Stop
Logic
SCL
Serial
Control
Logic
SDA
Address
Logic
X
DEC
EEPROM
Page
Prot. Bit
EEPROM
Page Logic
Y DEC
Dout/ACK
IEB02271
Figure 2
Block Diagram
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SLx 24C164/P
3
I2C-Bus Characteristics
The SLx 24C164/P devices support a master/slave bidirectional bus oriented protocol in
which the EEPROM always takes the role of a slave.
V CC
Slave 1
Slave 2
Slave 3
Slave 4
Slave 5
Slave 6
Slave 7
Slave 8
SCL
Master
SDA
V CC
IES02183
Figure 3
Bus Configuration
Master
Device that initiates the transfer of data and provides the clock for both
transmit and receive operations.
Slave
Device addressed by the master, capable of receiving and transmitting
data.
Transmitter The device with the SDA as output is defined as the transmitter. Due to
the open drain characteristic of the SDA output the device applying a low
level wins.
Receiver
The device with the SDA as input is defined as the receiver.
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SLx 24C164/P
The conventions for the serial clock line and the bidirectional data line are shown in
figure 4.
SCL
1
2
8
9
SDA
START Condition
ACK
Data allowed
to Change
Acknowledge
1
9
ACK
STOP Condition
IED02128
Figure 4
I2C-Bus Timing Conventions for START Condition, STOP Condition, Data Validation and Transfer of Acknowledge ACK
Standby
Mode in which the bus is not busy (no serial transmission, no
programming): both clock (SCL) and data line (SDA) are in high
state. The device enters the standby mode after a STOP condition
or after a programming cycle.
START Condition
High to low transition of SDA when SCL is high, preceding all
commands.
STOP Condition
Low to high transition of SDA when SCL is high, terminating all
communications. A STOP condition initiates an EEPROM
programming cycle. A STOP condition after reading a data byte
from the EEPROM initiates the Standby mode.
Acknowledge
A successful reception of eight data bits is indicated by the
receiver by pulling down the SDA line during the following clock
cycle of SCL (ACK). The transmitter on the other hand has to
release the SDA line after the transmission of eight data bits.
The EEPROM as the receiving device responds with an
acknowledge, when addressed. The master, on the other side,
acknowledges each data byte transmitted by the EEPROM and
can at any time end a read operation by releasing the SDA line (no
ACK) followed by a STOP condition.
Data Transfer
Data must change only during low SCL state, data remains valid
on the SDA bus during high SCL state. Nine clock pulses are
required to transfer one data byte, the most significant bit (MSB)
is transmitted first.
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SLx 24C164/P
4
Device Addressing and EEPROM Addressing
After a START condition, the master always transmits a Command Byte CSW or CSR.
After the acknowledge of the EEPROM a Control Byte follows, its content and the
transmitter depend on the previous Command Byte. The description of the Command
and Control Bytes is shown in table 2.
Command Byte
Selects one of the 8 addressable devices: the chip select bits c2,
c1 and c0 (bit positions b6 to b4) are compared to their
corresponding hard wired input pins CS2, CS1 and CS0,
respectively (c1 is the complement of CS1 pin).
Selects operation: the least significant bit b0 is low for a write
operation (Chip Select Write Command Byte CSW) or set high for a
read operation (Chip Select Read Command Byte CSR).
Contains address information: in the CSW Command Byte, the
bit positions b3 to b1 are decoded for the three uppermost EEPROM
address bits A10, A9, A8 (in the CSR Command Byte, the bit
positions b3 to b1 are left undefined).
Control Byte
Following CSW (b0 = 0): contains the eight lower bits of the
EEPROM address (EEA) bit A7 to A0, or an additional command
byte for the handling of the protection bit.
Following CSR (b0 = 1): contains the data read out, transmitted by
the EEPROM. The EEPROM data are read as long as the master
pulls down SDA after each byte in order to acknowledge the
transfer. The read operation is stopped by the master by releasing
SDA (no acknowledge is applied) followed by a STOP condition.
Table 2
Command and Control Byte for I2C-Bus Addressing of Chip and EEPROM
Definition
b7 b6 b5 b4 b3
Function
b2 b1 b0
CSW
1
c2
c1
c0
A10 A9 A8 0
Chip Select for Write
CSR
1
c2
c1
c0
x
Chip Select for Read
EEA
A7 A6 A5 A4 A3
x
x
1
A2 A1 A0 EEPROM address
The device has an internal address counter which points to the current EEPROM
address.
The address counter is incremented
– after a data byte to be written has been acknowledged, during entry of further data
byte
– during a byte read, thus the address counter points to the following address after
reading a data byte.
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SLx 24C164/P
The timing conventions for read and write operations are described in figures 5 and 6.
Command Byte (CSW)
Data Transfer to EEPROM
SCL
1
2
3
4
SDA
1
c2
c1
c0 A10 A9
5
START from Master
6
7
8
A8
0
9
10
11
12
13
14
15
16
A7
A6
A5
A4
A3
A2
A1 A0 ACK
Acknowledge from EEPROM
17
18
Acknowledge from EEPROM
IED02184
Figure 5
Timing of the Command Byte CSW
Command Byte (CSR)
Data Transfer from EEPROM
SCL
1
2
3
4
5
6
7
8
9
SDA
1
c2
c1
c0
X
X
X
1
ACK
START from Master
10
Acknowledge from EEPROM
11
12
13
14
15
16
17
18
ACK
Acknowledge from Master
IED02275
Figure 6
Timing of the Command Byte CSR
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SLx 24C164/P
5
Write Operations
Changing of the EEPROM data is initiated by the master with the command byte CSW.
Depending on the state of the Write Protection pin WP and of the Protection Bits (refer
to chapter 7 Page Protection ModeTM) either one byte (Byte Write) or up to 16 byte
(Page Write) are modified in one programming procedure.
5.1
Byte Write
Address Setting
After a START condition the master transmits the Chip Select
Write byte CSW. The EEPROM acknowledges the CSW byte
during the ninth clock cycle. The following byte with the
EEPROM address (A0 to A7) is loaded into the address
counter of the EEPROM and acknowledged by the EEPROM.
Transmission of Data
Finally the master transmits the data byte which is also
acknowledged by the EEPROM into the internal buffer.
Programming Cycle
Then the master applies a STOP condition which starts the
internal programming procedure. The data bytes are written in
the memory location addressed in the EEA byte (A0 to A7)
and the CSW byte (A8 to A10). The programming procedure
consists of an internally timed erase/write cycle. In the first
step, the selected byte is erased to “1”. With the next internal
step, the addressed byte is written according to the contents
of the buffer.
Bus Activity
Master
SDA Line
Bus Activity
EEPROM
S
T
A Command Byte EEPROM Address
R
CSW
EEA
T
S
S
T
O
P
Data Byte
0
P
A
C
K
A
C
K
A
C
K
IED02129
Figure 7
Byte Write Sequence
The erase/write cycle is finished latest after 8 ms. Acknowledge polling may be used for
speed enhancement in order to indicate the end of the erase/write cycle (refer to
chapter 5.3 Acknowledge Polling).
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SLx 24C164/P
5.2
Page Write
Address Setting
The page write procedure is the same as the byte write
procedure up to the first data byte. In a page write instruction
however, entry of the EEPROM address byte EEA is followed
by a sequence of one to maximum sixteen data bytes with the
new data to be programmed. These bytes are transferred to
the internal page buffer of the EEPROM.
Transmission of Data
The first entered data byte will be stored according to the
EEPROM address n given by EEA (A0 to A7) and CSW (A8 to
A10). The internal address counter is incremented
automatically after the entered data byte has been
acknowledged. The next data byte is then stored at the next
higher EEPROM address. EEPROM addresses within the
same page have common page address bits A4 through A10.
Only the respective four least significant address bits A0
through A3 are incremented, as all data bytes to be
programmed simultaneously have to be within the same page.
Programming Cycle
The master stops data entry by applying a STOP condition,
which also starts the internally timed erase/write cycle. In the
first step, all selected bytes are erased to “1”. With the next
internal step, the addressed bytes are written according to the
contents of the page buffer.
Those bytes of the page that have not been addressed are not included in the
programming.
Bus Activity
Master
SDA Line
S
T
A Command Byte EEPROM Address
R
EEA n
CSW
T
S
Bus Activity
EEPROM
Data Byte n
Data Byte n+1
S
T
O
P
Data Byte n+15
0
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
IED02140
Figure 8
Page Write Sequence
The erase/write cycle is finished latest after 8 ms. Acknowledge polling may be used for
speed enhancement in order to indicate the end of the erase/write cycle (refer to
chapter 5.3 Acknowledge Polling).
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SLx 24C164/P
5.3
Acknowledge Polling
During the erase/write cycle the EEPROM will not respond to a new command byte until
the internal write procedure is completed. At the end of active programming the chip
returns to the standby mode and the last entered EEPROM byte remains addressed by
the address counter. To determine the end of the internal erase/write cycle acknowledge
polling can be initiated by the master by sending a START condition followed by a
command byte CSR or CSW (read with b0 = 1 or write with b0 = 0). If the internal erase/
write cycle is not completed, the device will not acknowledge the transmission. If the
internal erase/write cycle is completed, the device acknowledges the received command
byte and the protocol activities can continue.
Internal Programming
Procedure
Send Start
Send CS-Byte
Acknowledge
from EEPROM
received?
No
Yes
Next Operation
IED02131
Figure 9
Flow Chart “Acknowledge Polling”
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SLx 24C164/P
STOP from Master initiates erase/write cycle
START from Master
CSR
SDA P
S
1
CSR
CSR
1
S
S
1
S
P
Acknowledge of EEPROM
indicates complete erase/
write cycle
STOP from Master initiates erase/write cycle
e.g. STOP condition
START from Master
CSW
SDA P
S
0
CSW
S
CSW
0
S
S
0
Acknowledge of EEPROM
indicates complete erase/
write cycle
P
IED02166
Figure 10
Principle of Acknowledge Polling
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SLx 24C164/P
6
Read Operations
Reading of the EEPROM data is initiated by the Master with the command byte CSR.
6.1
Random Read
Random read operations allow the master to access any memory location.
Address Setting
The master generates a START condition followed by the
command byte CSW. The receipt of the CSW-byte is
acknowledged by the EEPROM with a low on the SDA line.
Now the master transmits the EEPROM address (EEA) to the
EEPROM and the internal address counter is loaded with the
desired address.
Transmission of CSR
After the acknowledge for the EEPROM address is received,
the master generates a START condition, which terminates
the initiated write operation. Then the master transmits the
command byte CSR for read, which is acknowledged by the
EEPROM.
Transmission of
EEPROM Data
During the next eight clock pulses the EEPROM transmits the
data byte and increments the internal address counter.
STOP Condition from
Master
During the following clock cycle the masters releases the bus
and then transmits the STOP condition.
Bus Activity
Master
SDA Line
S
T
A Command Byte EEPROM Address
R
EEA n
CSW
T
S
Bus Activity
EEPROM
0
S
T
A Command Byte
R
CSR
T
S
T
O
P
1
P
S
A
C
K
A
C
K
A
C
K
Data Byte
IED02133
Figure 11
Random Read
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SLx 24C164/P
6.2
Current Address Read
The EEPROM content is read without setting an EEPROM address, in this case the
current content of the address counter will be used (e.g. to continue a previous read
operation after the Master has served an interrupt).
Transmission of CSR
For a current address read the master generates a START
condition, which is followed by the command byte CSR (chip
select read). The receipt of the CSR-byte is acknowledged by
the EEPROM with a low on the SDA line.
Transmission of
EEPROM Data
During the next eight clock pulses the EEPROM transmits the
data byte and increments the internal address counter.
STOP Condition from
Master
During the following clock cycle the masters releases the bus
and then transmits the STOP condition.
Bus Activity
Master
SDA Line
S
T
A Command Byte
R
CSR
T
S
T
O
P
1
P
S
A
C
K
Bus Activity
EEPROM
Data Byte
IED02132
Figure 12
Current Address Read
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SLx 24C164/P
6.3
Sequential Read
A sequential read is initiated in the same way as a current read or a random read except
that the master acknowledges the data byte transmitted by the EEPROM. The EEPROM
then continues the data transmission. The internal address counter is incremented by
one during each data byte transmission.
A sequential read allows the entire memory to be read during one read operation. After
the highest addressable memory location is reached, the internal address pointer “rolls
over” to the address 0 and the sequential read continues.
The transmission is terminated by the master by releasing the SDA line (no
acknowledge) and generating a STOP condition (see figure 13).
Bus Activity
Master
SDA Line
Bus Activity
EEPROM
S
T
A Command Byte
R
CSW
T
S
S
T
O
P
A
C
K
A
C
K
1
P
A
C
K
Data Byte n
Data Byte n+1
Data Byte n+x
IED02134
Figure 13
Sequential Read
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SLx 24C164/P
7
Page Protection ModeTM
Each page (16 byte) in the Data Memory can be protected against unintended data
changes by an associated protection bit. The protection bit memory consists of an
additional EEPROM of 128 bit (figure 14).
Data in the Data Memory can be modified only if the assigned protection bit is erased
(logical state “1”). After writing the data bytes to a page, the protection is achieved by
writing the associated protection bit (logical state “0”). Further changes in the data in a
protected page is possible only after erasing the protection bit.
Page 0
0
Page 1
1
Page 2
2
Page 3
.
.
.
3
.
.
.
Page n 0 1 2 3
.
.
.
...
Byte
15
Protection Bit Memory Area
Data Memory Area
n
Bit
IED02272
Figure 14
Data Page and Assigned Protection Memory
A special procedure to write or erase a protection bit guarantees proper activation or
deactivation respectively of page protection. For protection bit write or erase, all 16 data
bytes of the respective page have to be entered for a second time. The data then are
compared internally with the data to be protected, and in case of identity the protection
bit is written or erased respectively.
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SLx 24C164/P
7.1
Protection Bit Handling
The bits of the protection memory can be addressed directly for reading or programming.
A protection bit address corresponds to the lowest address within the respective page
(A4 to A10, A0 to A3 = zero). The status of each protection bit is sensed internally. A
written state (“0”) prevents programming in the associated page. If an already protected
memory page is accidentally addressed for programming, the programming procedure
is suppressed.
The conventional I2C-Bus protocol allows data bytes to be read and programmed only.
Therefore an independent instruction sequence for addressing and manipulation of
protection bits is implemented. For protection bit instructions, the command byte CSW
with its preceding START condition followed by the associated control byte has to be
entered twice (figures 15 through 17). The first command byte CSW (with A8 to A10) is
followed by the control byte EEA with the bit/page address A0 through A3 always at zero.
The second CSW is required for entering a control byte CTx for protection bit
manipulation. The three control bytes for read, write or erase of a protection bit are listed
below (table 3):
Table 3
Control Byte for Protection Bit Manipulation
Address
Name
Definition
b7
b6
b5
b4
b3
b2
b1
b0
CTR
x
x
x
x
x
x
0
0
Protection bit read
CTW
x
x
x
x
x
x
0
1
Protection bit write
CTE
x
x
x
x
x
x
1
1
Protection bit erase
Semiconductor Group
Function
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1998-07-27
SLx 24C164/P
7.2
Protection Bit Write and Erase
For writing or erasing a protection bit, the data of the respective page have to be known
by the master. The data of the page are not affected by the write or erase procedure of
the protection bit. The I2C-Bus protocol is shown in figure 15 for protection bit write and
figure 16 for protection bit erase.
Bus Activity
Master
SDA Line
S
T Command
A
Byte
R CSW
T
S
EEPROM
Address
EEA n
0
S
0000
A
C
K
Bus Activity
EEPROM
S
T Command
A
Byte
R CSW
T
0
A
C
K
Data
Byte n
Control
Byte
CTW
S
T
O
P
Data ... Data
Byte n+1 Byte n+15
P
01
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
IED02273
Figure 15
Sequence for Protection Bit Write
Bus Activity
Master
SDA Line
S
T Command
A
Byte
R CSW
T
S
Bus Activity
EEPROM
S
T Command
A
Byte
R CSW
T
EEPROM
Address
EEA n
0
S
0000
A
C
K
A
C
K
Control
Byte
CTE
0
Data
Byte n
S
T
O
P
Data ... Data
Byte n+1 Byte n+15
P
11
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
IED02274
Figure 16
Sequence for Protection Bit Erase
The first command byte CSW followed by the control byte EEA addresses the page to
be protected. The second command byte CSW (identical content of first CSW) is
followed by the control byte CTW = 01H for protection bit write or CTE = 03H for protection
bit erase. Depending on CTx, the addressed protection bit will be either written or
erased.
Semiconductor Group
20
1998-07-27
SLx 24C164/P
The control byte CTx is followed by 16 parameter bytes identical to the 16 data bytes of
the page to be protected or unprotected. The data of the first entered byte must be
identical to the data byte stored at the lowest address of the current page. The other 15
bytes have to be identical to the bytes stored in ascending address order within the same
page.
A successful verification of each byte is indicated by the EEPROM by pulling the SDA
line to low (acknowledge ACK).
After verification of the last byte, the bit programming procedure is initiated by the STOP
condition. Programming is started only if all 128 bits of a page have been verified
successfully. If bit programming has taken place, the address counter points to the
uppermost address of the respective page. The write or erase cycle is finished latest
after 4 ms. Acknowledge polling may be used for speed enhancement in order to
indicate the end of the write or erase cycle (refer to chapter 5.3 Acknowledge Polling).
Semiconductor Group
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1998-07-27
SLx 24C164/P
7.3
Protection Bit Read
The byte sequence for random bit read is shown in figure 17.
Bus Activity
Master
SDA Line
S
T Command
A
Byte
R CSW
T
S
EEPROM
Address
EEA n
0
S
0000
A
C
K
Bus Activity
EEPROM
S
T Command
A
Byte
R CSW
T
A
C
K
0
00 b
A
C
K
A Data
C Byte n
K
S
T
O
P
A
C
K
A
C
K
Control
Byte
CTR
b
P
b
Data
Byte n+1
...
A
C
K
IED02139
b = Protection Bit
Figure 17
Byte Sequence for Protection Bit Read
The first command byte CSW followed by the control byte EEA addresses the protection
bit to be read. The second command byte CSW is followed by the control byte 00H for
protection bit read. The first bit (MSB) of the transferred byte is the protection bit of the
addressed page. The other 7 bits are not valid. The page protection status is indicated
as following
Protection Bit = 1: A normal write operation changes the data in the associated page
Protection Bit = 0: The data in the associated page are protected against changes.
If the master acknowledges a byte with a low state of the SDA line, the protection bit of
the next page can be read as the first bit of the following byte. If the master releases the
SDA line, a STOP condition has to complete the read procedure. Any number of bytes
with a page protection status at the first bit position can be requested by the master. If
the bit of the uppermost page has been addressed, the counter has its overflow to the
lowest address according to the first page.
Semiconductor Group
22
1998-07-27
SLx 24C164/P
8
Electrical Characteristics
The listed characteristics are ensured over the operating range of the integrated circuit.
Typical characteristics specify mean values expected over the production spread. If not
otherwise specified, typical characteristics apply at TA = 25 °C and the given supply
voltage.
8.1
Absolute Maximum Ratings
Stresses above those listed here may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operational section of this data sheet is not implied.
Exposure to absolute maximum ratings for extended periods may affect device reliability.
Parameter
Limit Values
Units
– 40 to + 85
– 40 to + 125
°C
°C
Storage temperature
– 65 to + 150
°C
Supply voltage
– 0.3 to + 7.0
V
All inputs and outputs with respect to ground
– 0.3 to VCC + 0.5
V
ESD protection (human body model)
4000
V
Operating temperature
8.2
range 1 (industrial)
range 2 (automotive)
DC Characteristics
Parameter
Symbol
Limit Values
min.
Supply voltage
Units Test Condition
typ. max.
VCC
4.5
5.5
V
5 V type
VCC
2.7
5.5
V
3 V type
3
mA
VCC = 5 V; fc = 100 kHz
50
µA
Inputs at VCC or VSS
Supply current1)
(write)
ICC
Standby
current2)
ISB
Input leakage
current
ILI
0.1
10
µA
VIN = VCC or VSS
Output leakage
current
ILO
0.1
10
µA
VOUT = VCC or VSS
Input low
voltage
VIL
Semiconductor Group
1
0.3 × VCC V
– 0.3
23
1998-07-27
SLx 24C164/P
8.2
DC Characteristics (cont’d)
Parameter
Symbol
Limit Values
min.
Units Test Condition
typ. max.
0.7 × VCC
Input high
voltage
VIH
VCC + 0.5 V
Output low
voltage
VOL
0.4
V
Input/output
capacitance
(SDA)
CI/O
83)
pF
IOL = 3 mA; VCC = 5 V
IOL = 2.1 mA; VCC = 3 V
VIN = 0 V; VCC = 5 V
Input
capacitance
(other pins)
CIN
63)
pF
VIN = 0 V; VCC = 5 V
400
pF
Capacitive load Cb
for each bus line
1)
The values for ICC are maximum peak values
2)
Valid over the whole temperature range
This parameter is characterized only
3)
Semiconductor Group
24
1998-07-27
SLx 24C164/P
8.3
AC Characteristics
Parameter
Limit Values
Limit Values
VCC = 2.7-5.5 V
VCC = 4.5-5.5 V
min.
min.
Symbol
fSCL
tlow
Clock pulse width low
thigh
Clock pulse width high
tR
SDA and SCL rise time
tF
SDA and SCL fall time
tSU.STA
Start set-up time
tHD.STA
Start hold time
tSU.DAT
Data in set-up time
tHD.DAT
Data in hold time
tAA
SCL low to SDA data out valid
tDH
Data out hold time
tSU.STO
Stop set-up time
Time the bus must be free before tBUF
max.
100
SCL clock frequency
Units
max.
400
kHz
4.7
1.2
µs
4.0
0.6
µs
1000
1)
300
ns
300
1)
300
ns
4.7
0.6
µs
4.0
0.6
µs
200
100
ns
0
0
µs
0.1
4.5
0.1
0.9
µs
100
50
ns
4.0
0.6
µs
4.7
1.2
µs
a new transmission can start
SDA and SCL spike suppression tl
time at constant inputs
1)
50
100
50
100
ns
The minimum rise and fall times can be calculated as follows: 20 + (0.1/pF) × Cb [ns]
Example: Cb = 100 pF → tR = 20 + 0.1 × 100 [ns] = 30 ns
8.4
Erase and Write Characteristics
Limit Values
VCC = 2.7-5.5 V
Limit Values Units
VCC = 4.5-5.5 V
typ.
max.
typ.
max.
5
8
5
8
ms
Erase page protection bit
2.5
4
2.5
4
ms
Write page protection bit
2.5
4
2.5
4
ms
Parameter
Erase + write cycle (per page)
Semiconductor Group
Symbol
tWR
25
1998-07-27
SLx 24C164/P
tR
tF
t LOW
t HIGH
SCL
t SU.STA
t SU.DAT
t HD.STA
t HD.DAT
t SU.STO
t BUF
SDA In
Start Condition
t AA
t DH
Stop Condition
SDA Out
IED02127
Figure 18
Bus Timing Data
Semiconductor Group
26
1998-07-27
SLx 24C164/P
9
Package Outlines
GPD05583
P-DIP-8-4
(Plastic Dual In-line Package)
GPS09032
P-DSO-8-3
(Plastic Dual Small Outline Package)
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”.
SMD = Surface Mounted Device
Semiconductor Group
27
Dimensions in mm
1998-07-27