QL16x24B pASIC® 1 Family Very-High-Speed CMOS FPGA Rev C pASIC HIGHLIGHTS …4,000 usable ASIC gates, 122 I/O pins Very High Speed – ViaLink metal-to-metal programmable–via antifuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns. High Usable Density – A 16-by-24 array of 384 logic cells provides 4,000 usable ASIC gates (7,000 PLD gates) in 84-pin PLCC, 100-pin and 144-pin TQFP, 144-pin CPGA and 160-pin CQFP packages. Low-Power, High-Output Drive – Standby current typically 2 mA. A 16-bit counter operating at 100 MHz consumes less than 50 mA. Minimum IOL of 12 mA and IOH of 8 mA QL16x24B Block Diagram 384 Logic Cells = Up to 114 prog. I/O cells, 6 Input high-drive cells, 2 Input/Clk (high-drive) cells 4-21 4 pASIC 1 Low-Cost, Easy-to-Use Design Tools – Designs entered and simulated using QuickLogic's new QuickWorks development environment, or with third-party CAE tools including Viewlogic, Synopsys, Mentor, Cadence and Veribest. Fast, fully automatic place and route on PC and workstation platforms using QuickLogic software. QL16x24B PRODUCT SUMMARY The QL16x24B is a member of the pASIC 1 Family of very-high-speed CMOS user-programmable ASIC devices. The 384 logic cell fieldprogrammable gate array (FPGA) offers 4,000 usable ASIC gates (equivalent to 7,000 PLD gates) of high-performance general-purpose logic in 84-pin PLCC, 100-pin and 144-pin TQFP, 144-pin CPGA, and 160-pin CQFP. Low-impedance, metal-to-metal, ViaLink interconnect technology provides nonvolatile custom logic capable of operating above 150 MHz. Logic cell delays under 2 ns, combined with input delays of under 1.5 ns and output delays under 3 ns, permit high-density programmable devices to be used with today’s fastest microprocessors and DSPs. Designs can be entered using QuickLogic’s QuickWorks Toolkit or most populart third-party CAE tools. QuickWorks combines Verilog/VHDL design entry and simulation tools with device-specific place & route and programming software. Ample on-chip routing channels allow fast, fully automatic place and route of designs using up to 100% of the logic and I/O cells, while maintaining fixed pin-outs. FEATURES Total of 122 I/O pins – 114 Bidirectional Input/Output pins – 6 Dedicated Input/High-Drive pins – 2 Clock/Dedicated input pins with fanout-independent, low-skew clock networks Input + logic cell + output delays under 6 ns Chip-to-chip operating frequencies up to 110 MHz Internal state machine frequencies up to 150 MHz Clock skew < 0.5 ns Input hysteresis provides high noise immunity Built-in scan path permits 100% factory testing of logic and I/O cells and functional testing with Automatic Test Vector Generation (ATVG) software after programming Packages are 84-pin PLCC, 100-pin and 144-pin TQFP, 144-pin CPGA, and 160-pin CQFP 84-pin PLCC compatible with QL12x16B 100-pin TQFP compatible with QL8x12B and QL12x16B 144-pin TQFP compatible with QL24x32B 0.65µ CMOS process with ViaLink programming technology 4-22 QL16x24B Pinout Diagram 84-pin PLCC 4 4-23 pASIC 1 Pinout Diagram 100-pin TQFP QL16x24B Pinout Diagram 144-pin TQFP 4-24 QL16x24B Pinout Diagram 144-pin CPGA M 4 pASIC 1 4-25 QL16x24B CPGA 144 Function/Connector Table PIN FUNC PIN FUNC PIN FUNC PIN FUNC A2 B3 C4 A3 B4 A4 C3 B5 A5 C6 B6 A6 A7 B7 C5 A8 B8 C8 C7 A9 B9 C11 A10 A11 B10 A12 B11 C10 A13 C9 B12 A14 B13 C12 A15 B14 IO IO IO IO IO IO VCC IO IO IO IO IO IO IO GND IO I/(SCLK) I/CLK/(SM) VCC I/(P) I VCC IO IO IO IO IO IO IO GND IO IO IO IO IO IO B15 C14 D13 C15 D14 E13 D15 E14 E15 F13 F14 F15 G15 C13 G14 H15 H14 G13 H13 J15 J14 J13 K15 L15 K14 M15 L14 K13 N15 L13 M14 P15 N14 M13 R15 P14 IO IO IO IO IO VCC IO IO IO IO IO IO IO GND IO IO IO GND IO IO IO VCC IO IO IO IO IO IO IO GND IO IO IO IO IO nc R14 P13 N12 R13 P12 R12 N13 P11 R11 N10 P10 R10 R9 P9 N11 R8 P8 N8 N9 R7 P7 N5 R6 R5 P6 R4 P5 N6 R3 N7 P4 R2 P3 N4 R1 P2 IO IO IO IO IO IO VCC IO IO IO IO IO IO IO GND IO I/(SI) I/CLK VCC I I/(SO) VCC IO IO IO IO IO IO IO GND IO IO IO IO IO IO P1 N2 M3 N1 M2 L3 M1 L2 L1 K3 K2 K1 J1 N3 J2 H1 H2 J3 H3 G1 G2 G3 F1 E1 F2 D1 E2 F3 C1 E3 D2 B1 C2 D3 A1 B2 IO IO IO IO IO VCC IO IO IO IO IO IO IO GND IO IO IO GND IO IO IO VCC IO IO IO IO IO IO IO GND IO IO IO IO IO nc 4-26 QL16x24B Pinout Daigram 160-pin CQFP 4 pASIC 1 4-27 QL16x24B ABSOLUTE MAXIMUM RATINGS Supply Voltage ................................. –0.5 to 7.0V Input Voltage ....................... –0.5 to VCC +0.5V ESD Pad Protection .................................. ±2000V DC Input Current...................................... ±20 mA Latch-up Immunity................................. ±200 mA Storage Temperature .......–65°C to + 150°C Lead Temperature ...................................300°C OPERATING RANGE Symbol VCC TA TC K Parameter Supply Voltage Ambient Temperature Case Temperature -X Speed Grade Delay Factor -0 Speed Grade -1 Speed Grade -2 Speed Grade Military Min Max 4.5 5.5 -55 125 0.39 0.39 1.82 1.56 Industrial Min Max 4.5 5.5 -40 85 Commercial Min Max 4.75 5.25 0 70 0.4 0.4 0.4 0.4 0.46 0.46 0.46 0.46 2.75 1.67 1.43 1.35 Unit V °C °C 2.55 1.55 1.33 1.25 DC CHARACTERISTICS over operating range Symbol VIH VIL Parameter Input HIGH Voltage Input LOW Voltage VOH Output HIGH Voltage VOL Output LOW Voltage II IOZ CI IOS Input Leakage Current 3-State Output Leakage Current Input Capacitance [1] Output Short Circuit Current [2] ICC D.C. Supply Current [3] Conditions Min 2.0 Max 0.8 IOH = -4 mA IOH = -8 mA IOH = -10 µA IOL = 12 mA* IOL = 10 µA VI = VCC or GND VI = VCC or GND VO = GND VO = VCC VI, VIO = VCC or GND 3.7 2.4 VCC-0.1 -10 -10 -10 30 0.4 0.1 10 10 10 -80 140 10 Unit V V V V V V V µA µA pF mA mA mA *IOL = 12 mA for commercial range only. IOL = 8 mA for the industrial and military ranges. Notes: [1] [2] [3] [4] [5] Capacitance is sample tested only. CI = 20 pF max on I/(SI). Only one output at a time. Duration should not exceed 30 seconds. Commercial temperature grade only. Maximum Icc for industrial grade is 15mA and for military grade is 20 mA. For AC conditions use the formula described in the Section 9 — Power vs Operating Frequency. Stated timing for worst case Propagation Delay over process variation at VCC = 5.0V and TA = 25°C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as specified in the Operating Range. These limits are derived from a representative selection of the slowest paths through the pASIC logic cell including net delays. Worst case delay values for specific paths should be determined from timing analysis of your particular design . 4-28 QL16x24B AC CHARACTERISTICS at VCC = 5V, TA = 25°C (K = 1.00) Logic Cell Symbol tPD tSU tH tCLK tCWHI tCWLO tSET tRESET tSW tRW Parameter 1 1.7 2.1 0.0 1.0 2.0 2.0 1.7 1.5 1.9 1.8 Combinatorial Delay [5] Setup Time [5] Hold Time Clock to Q Delay Clock High Time Clock Low Time Set Delay Reset Delay Set Width Reset Width Propagation Delays (ns) Fanout 2 3 4 2.2 2.6 3.2 2.1 2.1 2.1 0.0 0.0 0.0 1.5 1.9 2.6 2.0 2.0 2.0 2.0 2.0 2.0 2.2 2.6 3.2 1.9 2.2 2.7 1.9 1.9 1.9 1.8 1.8 1.8 8 5.3 2.1 0.0 4.7 2.0 2.0 5.3 4.4 1.9 1.8 4 Input Cells tIN tINI tIO tGCK tGCKHI tGCKLO Propagation Delays (ns) [4] Parameter 1 2.8 3.0 1.4 2.7 2.0 2.0 High Drive Input Delay [6] High Drive Input, Inverting Delay [6] Input Delay (bidirectional pad) Clock Buffer Delay [7] Clock Buffer Min High [7] Clock Buffer Min Low [7] 2 2.9 3.1 1.9 2.8 2.0 2.0 3 3.0 3.2 2.2 2.9 2.0 2.0 4 3.1 3.3 2.9 3.0 2.0 2.0 6 4.0 4.1 4.7 3.1 2.0 2.0 8 5.3 5.7 6.5 3.3 2.0 2.0 Output Cell Symbol tOUTLH tOUTHL tPZH tPZL tPHZ tPLZ Parameter 30 2.7 2.8 4.0 3.6 2.9 3.3 Output Delay Low to High Output Delay High to Low Output Delay Tri-state to High Output Delay Tri-state to Low Output Delay High to Tri-state [8] Output Delay Low to Tri-state [8] Propagation Delays (ns) [4] Output Load Capacitance (pF) 50 75 100 3.4 4.2 5.0 3.7 4.7 5.6 4.9 6.1 7.3 4.2 5.0 5.8 150 6.7 7.6 9.7 7.3 Notes: [6] [7] [8] See High Drive Buffer Table for more information. Clock buffer fanout refers to the maximum number of flip flops per half column. The number of half columns used does not affect clock buffer delay. tPHZ 1KΩ The following loads are used for tPXZ: 5 pF 1KΩ tPLZ 5 pF 4-29 pASIC 1 Symbol QL16x24B High Drive Buffer Clock Drivers Wired Together Symbol Parameter tIN High Drive Input Delay tINI High Drive Input, Inverting Delay 1 2 3 4 1 2 3 4 Propagation Delays (ns) [4] Fanout 12 24 48 72 96 5.3 6.7 4.5 6.6 5.3 6.2 7.2 5.4 6.2 5.7 7.2 4.6 6.8 5.5 6.4 7.4 5.6 6.4 AC Performance Propagation delays depend on routing, fanout, load capacitance, supply voltage, junction temperature, and process variation. The AC Characteristics are a design guide to provide initial timing estimates at nominal conditions. Worst case estimates are obtained when nominal propagation delays are multiplied by the appropriate Delay Factor, K, as specified in the Delay Factor table (Operating Range). The effects of voltage and temperature variation are illustrated in the graphs on page 4-47, K Factor versus Voltage and Temperature. The pASIC Development Tools incorporate data sheet AC Characteristics into the QDIF database for pre-place-and-route timing analysis. The SpDE Delay Modeler extracts specific timing parameters for precise path analysis or simulation results following place and route. ORDERING INFORMATION QL 16x24B - 1 PF144 C QuickLogic pASIC device Operating Range C = Commercial I = Industrial M = Military M/883C = MIL STD 883 pASIC device part number B = 0.65 micron CMOS Package Code PL84 = 84-pin PLCC PF100 = 100-pin TQFP PF144 = 144-pin TQFP CG144 = 144-pin CPGA CF160 = 160-pin CQFP Speed Grade X = quick 0 = fast 1 = faster 2 = fastest 4-30