QL3012 - pASIC 3 FPGATM 12,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density QL3012 - pASIC 3 FPGA DEVICE HIGHLIGHTS Device Highlights High Performance & High Density ■ 12,000 Usable PLD Gates with 118 I/Os ■ 16-bit counter speeds over 300 MHz, data path speeds over 400 MHz ■ 0.35um four-layer metal non-volatile CMOS process for smallest die sizes Easy to Use / Fast Development Cycles ■ 100% routable with 100% utilization and complete pin-out stability ■ Variable-grain logic cells provide high performance and 100% utilization ■ Comprehensive design tools include high quality Verilog/VHDL synthesis Advanced I/O Capabilites FIGURE 1. 320 Logic Cells ■ Interfaces with both 3.3 volt and 5.0 volt devices ■ PCI compliant with 3.3V and 5.0V buses for -1/-2/-3/-4 speed grades ■ Full JTAG boundary scan ■ Registered I/O cells with individually controlled clocks and output enables Total of 118 I/O Pins ■ 110 bidirectional input/output pins, PCI-compliant for 5.0 volt and 3.3 volt buses for -1/-2/-3/-4 speed grades ■ 4 high-drive input-only pins ■ 4 high-drive input/distributed network pins Four Low-Skew Distributed Networks ■ Two array clock/control networks available to the logic cell flip- flop clock, set and reset inputs - each driven by an input-only pin ■ Six global clock/control networks available to the logic cell F1, clock set and reset inputs and the input and I/O register clock, reset and enable inputs as well as the output enable control - each driven by an input-only or I/O pin, or any logic cell output or I/O cell feedback High Performance ■ Input + logic cell + output total delays under 6 ns ■ Data path speeds over 400 MHz ■ Counter speeds over 300 MHz QL3012 Rev C PRODUCT SUMMARY Product Summary The QL3012 is a 12,000 usable PLD gate member of the pASIC 3 family of FPGAs. pASIC 3 FPGAs are fabricated on a 0.35mm four-layer metal process using QuickLogic’s patented ViaLink technology to provide a unique combination of high performance, high density, low cost, and extreme ease-of-use. The QL3012 contains 320 logic cells. With a maximum of 118 I/Os, the QL3012 is available in 84-pin PLCC, 100-pin TQFP, and 144-pin TQFP packages. Software support for the complete pASIC 3 family, including the QL3012, is available through three basic packages. The turnkey QuickWorks“ package provides the most complete FPGA software solution from design entry to logic synthesis, to place and route, to simulation. The QuickToolsTM for Workstations package provides a solution for designers who use Cadence, Exemplar, Mentor, Synopsys, Synplicity, Viewlogic, Veribest, or other third-party tools for design entry, synthesis, or simulation. 7-19 QL3012 - pASIC 3 FPGATM PASIC PINOUT DIAGRAM pASIC Pinout Diagram FIGURE 2. 84-Pin PLCC pASIC Pinout Table 100-Pin TQFP 7-20 20 Preliminary QL3012 - pASIC 3 FPGATM PINOUT DIAGRAM Pinout Diagram Pin #76 Pin #1 pASIC QL3012-1PF100C Pin #51 Pin #26 FIGURE 3. 100-Pin TQFP Pin #173 Pin #1 pASIC QL3012-1PQ144C Pin #109 Pin #37 FIGURE 4. 144-Pin TQFP 7-21 QL3012 - pASIC 3 FPGATM 100 & 144 TQFP PINOUT TABLE 100 & 144 TQFP Pinout Table 144 TQFP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 100 144 Function TQFP TQFP 2 I/O 38 3 I/O 39 NC I/O 40 4 I/O 41 NC I/O 42 5 I/O 43 NC VCC 44 6 I/O 45 NC I/O 46 7 I/O 47 NC I/O 48 NC I/O 49 8 I/O 50 NC I/O 51 9 GND 52 10 I/O 53 11 I 54 12 ACLK / I 55 13 VCC 56 14 I 57 15 GCLK / I 58 16 VCC 59 17 I/O 60 18 I/O 61 NC I/O 62 19 I/O 63 NC I/O 64 20 I/O 65 21 I/O 66 NC GND 67 NC I/O 68 22 I/O 69 23 I/O 70 NC I/O 71 NC I/O 72 24 25 I/O I/O 73 74 100 144 Function TQFP TQFP 26 TDI 75 27 I/O 76 28 I/O 77 29 I/O 78 NC VCC 79 30 I/O 80 31 I/O 81 NC I/O 82 32 I/O 83 33 I/O 84 NC I/O 85 34 I/O 86 35 GND 87 36 I/O 88 NC I/O 89 37 I/O 90 38 GND 91 39 I/O 92 40 I/O 93 41 I/O 94 42 VCCIO 95 NC I/O 96 43 I/O NC 44 I/O 97 45 I/O 98 NC I/O 99 NC I/O 100 46 I/O 101 NC GND 102 NC I/O 103 NC I/O 104 47 I/O 105 48 I/O 106 49 TRSTB 107 50 TMS 108 51 52 I/O I/O 109 110 100 144 Function TQFP TQFP 53 I/O 111 54 I/O 112 55 I/O 113 NC I/O 114 NC VCC 115 NC I/O 116 56 I/O 117 NC I/O 118 57 I/O 119 NC I/O 120 58 I/O 121 NC I/O 122 59 GND 123 60 I/O 124 61 I 125 62 ACLK / I 126 63 VCC 127 64 I 128 65 GCLK / I 129 66 VCC 130 67 I/O 131 NC I/O 132 68 I/O 133 NC I/O 134 69 I/O 135 NC I/O 136 70 I/O NC 71 I/O 137 NC GND 138 NC I/O 139 72 I/O 140 NC I/O 141 73 I/O 142 74 I/O 143 75 I/O 144 76 77 7-22 22 Preliminary TCK STM 100 Function TQFP 78 I/O 79 I/O 80 I/O NC VCC 81 I/O 82 I/O 83 I/O NC I/O 84 I/O NC I/O NC I/O 85 GND NC I/O 86 I/O 87 I/O 88 GND 89 I/O 90 I/O 91 I/O 92 VCCIO NC I/O 93 I/O NC I/O 94 I/O NC I/O NC I/O 95 I/O NC I/O NC GND 96 I/O 97 I/O 98 I/O 99 I/O 100 TDO 1 I/O QL3012 - pASIC 3 FPGATM PIN DESCRIPTIONS Pin Descriptions Pin TDI Function Test Data In for JTAG TRSTB Active low Reset for JTAG TMS Test Mode Select for JTAG TCK Test Clock for JTAG TDO Test data out for JTAG STM Special Test Mode I/ACLK I High-drive input and/or array network driver High-drive input and/or global network driver High-drive input I/O Input/Output pin Can be configured as an input and/or output. VCC Power supply pin Connect to 3.3V supply. VCCIO Input voltage tolerance pin GND Ground pin Connect to 5.0 volt supply if 5 volt input tolerance is required, otherwise connect to 3.3V supply. Connect to ground. I/GCLK Description Hold HIGH during normal operation. Connect to VCC if not used for JTAG. Hold LOW during normal operation. Connect to ground if not used for JTAG. Hold HIGH during normal operation. Connect to VCC if not used for JTAG. Hold HIGH or LOW during normal operation. Connect to VCC or ground if not used for JTAG. Output that must be left unconnected if not used for JTAG. Must be grounded during normal operation. Can be configured as either or both. Can be configured as either or both. Use for input signals with high fanout. Ordering Information QL 3012 - 1 PF144 C QuickLogic pASIC device pASIC 3 device part number Speed Grade 0 = quick 1 = fast 2 = faster 3 = faster *4 = fastest Operating Range C = Commercial I = Industrial M = Military Package Code PL84 = 84-pin PLCC PF100 = 100-pin TQFP PF144 = 144-pin TQFP * Contact QuickLogic regarding availability 7-23 QL3012 - pASIC 3 FPGATM Absolute Maximum Ratings VCC Voltage . . . . . . . . . . . . . . . . . . . -0.5 to 4.6V DC Input Current . . . . . . . . . . . . . . . . . . . ±20 mA VCCIO Voltage . . . . . . . . . . . . . . . . . -0.5 to 7.0V ESD Pad Protection . . . . . . . . . . . . . . . . . ±2000V Input Voltage . . . . . . . . . . . . -0.5 to VCCIO +0.5V Storage Temperature . . . . . . . . . -65°C to +150°C Latch-up Immunity . . . . . . . . . . . . . . . . . ±200 mA Lead Temperature . . . . . . . . . . . . . . . . . . . 300°C Operating Range Symbol Parameter VCC VCCIO TA TC Supply Voltage I/O Input Tolerance Voltage Ambient Temperature Case Temperature -0 Speed Grade Delay Factor -1 Speed Grade -2 Speed Grade -3 Speed Grade -4 Speed Grade K Military Min Max 3.0 3.6 3.0 5.5 -55 125 0.42 0.42 N/A N/A 1.64 1.37 N/A N/A Industrial Min Max 3.0 3.6 3.0 5.5 -40 85 Commercial Min Max 3.0 3.6 3.0 5.25 0 70 0.43 0.43 0.43 0.43 0.43 0.46 0.46 0.46 0.46 0.46 1.90 1.54 1.28 0.90 0.82 Unit V V °C °C 1.85 1.50 1.25 0.88 0.80 DC Characteristics Symbol VIH VIL VOH Parameter Input HIGH Voltage Input LOW Voltage Output HIGH Voltage Conditions VOL Output LOW Voltage II IOZ CI IOS I or I/O Input Leakage Current 3-State Output Leakage Current Input Capacitance [2] Output Short Circuit Current [3] ICC ICCIO D.C. Supply Current [4] D.C. Supply Current on VCCIO Min Max Unit 0.5VCC VCCIO+0.5 V -0.5 0.3VCC V IOH = -12 mA 2.4 V 0.9VCC V IOH = -500 µA IOL = 16 mA [1] 0.45 V IOL = 1.5 mA 0.1VCC V VI = VCCIO or GND -10 10 µA VI = VCCIO or GND -10 10 µA 10 pF VO = GND -15 -180 mA VO = VCC 40 210 mA VI, VIO = VCCIO or GND 0.50 (typ) 2 mA 0 100 µA Notes: [1] Applies only to -1/-2/-3/-4 commercial grade devices. These speed grades are also PCI-compliant. All other devices have 8 mA IOL specifications. [2] Capacitance is sample tested only. Clock pins are 12 pF maximum. [3] Only one output at a time. Duration should not exceed 30 seconds. [4] For -1/-2/-3/-4 commercial grade devices only. Maximum ICC is 3 mA for -0 commercial grade and all industrial grade devices, and 5 mA for all military grade devices. For AC conditions, contact QuickLogic customer engineering. 7-24 24 Preliminary QL3012 - pASIC 3 FPGATM AC Characteristics at VCC = 3.3V, TA = 25°C (K = 1.00) (To calculate delays, multiply the appropriate K factor in the "Operating Range" section by the following numbers.) Logic Cells Symbol tPD tSU tH tCLK tCWHI tCWLO tSET tRESET tSW tRW Propagation Delays (ns) Fanout [5] 2 3 4 1.7 1.9 2.2 1.7 1.7 1.7 0.0 0.0 0.0 1.0 1.2 1.5 1.2 1.2 1.2 1.2 1.2 1.2 1.3 1.5 1.8 1.1 1.3 1.6 1.9 1.9 1.9 1.8 1.8 1.8 Parameter Combinatorial Delay [6] Setup Time [6] Hold Time Clock to Q Delay Clock High Time Clock Low Time Set Delay Reset Delay Set Width Reset Width 1 1.4 1.7 0.0 0.7 1.2 1.2 1.0 0.8 1.9 1.8 8 3.2 1.7 0.0 2.5 1.2 1.2 2.8 2.6 1.9 1.8 Input-Only/Clock Cells Symbol tIN tINI tISU tIH tlCLK tlRST tlESU tlEH Parameter High Drive Input Delay High Drive Input, Inverting Delay Input Register Set-Up Time Input Register Hold Time Input Register Clock To Q Input Register Reset Delay Input Register clock Enable Set-Up Time Input Register Clock Enable Hold Time 1 1.5 1.6 3.1 0.0 0.7 0.6 2.3 0.0 Propagation Delays (ns) Fanout [5] 2 3 4 8 12 1.6 1.8 1.9 2.4 2.9 1.7 1.9 2.0 2.5 3.0 3.1 3.1 3.1 3.1 3.1 0.0 0.0 0.0 0.0 0.0 0.8 1.0 1.1 1.6 2.1 0.7 0.9 1.0 1.5 2.0 2.3 2.3 2.3 2.3 2.3 0.0 0.0 0.0 0.0 0.0 24 4.4 4.5 3.1 0.0 3.6 3.5 2.3 0.0 Notes: [5] Stated timing for worst case Propagation Delay over process variation at VCC=3.3V and TA=25°C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as specified in the Operating Range. [6] These limits are derived from a representative selection of the slowest paths through the pASIC 3 logic cell including typical net delays. Worst case delay values for specific paths should be determined from timing analysis of your particular design. 7-25 QL3012 - pASIC 3 FPGATM Clock Cells Symbol tACK tGCKP tGCKB Parameter 1 1.2 0.7 0.8 Array Clock Delay Global Clock Pin Delay Global Clock Buffer Delay Propagation Delays (ns) Loads per Half Column [7] 2 3 4 8 10 1.2 1.3 1.3 1.5 1.6 0.7 0.7 0.7 0.7 0.7 0.8 0.9 0.9 1.1 1.2 11 1.7 0.7 1.3 I/O Cells Symbol Parameter tI/O tISU tIH tlOCLK tlORST tlESU tlEH Input Delay (bidirectional pad) Input Register Set-Up Time Input Register Hold Time Input Register Clock To Q Input Register Reset Delay Input Register clock Enable Set-Up Time Input Register Clock Enable Hold Time Symbol Parameter tOUTLH tOUTHL tPZH tPZL tPHZ tPLZ Output Delay Low to High Output Delay High to Low Output Delay Tri-state to High Output Delay Tri-state to Low Output Delay High to Tri-State [8] Output Delay Low to Tri-State [8] 1 1.3 3.1 0.0 0.7 0.6 2.3 0.0 30 2.1 2.2 1.2 1.6 2.0 1.2 Propagation Delays (ns) Fanout [5] 2 3 4 8 1.6 1.8 2.1 3.1 3.1 3.1 3.1 3.1 0.0 0.0 0.0 0.0 1.0 1.2 1.5 2.5 0.9 1.1 1.4 2.4 2.3 2.3 2.3 2.3 0.0 0.0 0.0 0.0 10 3.6 3.1 0.0 3.0 2.9 2.3 0.0 Propagation Delays (ns) Output Load Capacitance (pF) 50 75 100 2.5 3.1 3.6 2.6 3.2 3.7 1.7 2.2 2.8 2.0 2.6 3.1 150 4.7 4.8 3.9 4.2 Notes: [7] The array distributed networks consist of 40 half columns and the global distributed networks consist of 44 half columns, each driven by an independent buffer. The number of half columns used does not affect clock buffer delay. The array clock has up to 8 loads per half column. The global clock has up to 11 loads per half column. [8] The following loads are used for tPXZ: tPHZ 1KΩ 5 pF 1KΩ tPLZ 5 pF 7-26 26 Preliminary