R8822 Datasheet 16-BIT RISC MICRO-CONTROLLER RDC RISC DSP Communication RDC Semiconductor Co., Ltd http://www.rdc.com.tw TEL: 886-3-666-2866 FAX: 886-3-563-1498 R8822 Datasheet Final Version 1.7 May 19, 2005 1 RDC® R8822 RISC DSP Communication 16-Bit RISC Micro-controller CONTENTS 1. Features..............................................................................................5 2. Block Diagram....................................................................................6 3. Pin Description ..................................................................................7 3.1 Pin Placement................................................................................................................7 3.1.1 PQFP......................................................................................................................................... 7 3.1.2 LQFP......................................................................................................................................... 8 3.2 3.3 R8822 PQFP & LQFP Pin-Out Table .............................................................................9 Functional Description .................................................................................................10 3.4 R8822 I/O Characteristics of Each Pin.........................................................................16 4. Basic Application System Block ....................................................19 5. Read/Write Timing Diagram............................................................21 6. Crystal Characteristics....................................................................23 6.1 Fundamental Mode ......................................................................................................23 7. Execution Unit..................................................................................24 7.1 7.2 7.3 7.4 General Registers ........................................................................................................24 Segment Registers ......................................................................................................25 Instruction Pointer and Status Flags Registers ............................................................25 Address Generation .....................................................................................................27 8. Peripheral Register List ..................................................................28 9. Power-Save & Power-Down ............................................................30 10. Reset ..............................................................................................33 11. Bus Interface Unit .........................................................................35 11.1 2 Memory and I/O Interface..........................................................................................35 R8822 Datasheet Final Version 1.7 May 19, 2005 RDC® 11.2 11.3 11.4 11.5 R8822 RISC DSP Communication 16-Bit RISC Micro-controller Data Bus ................................................................................................................... 36 Wait States................................................................................................................ 36 Bus Hold ................................................................................................................... 37 Bus Width ................................................................................................................. 38 12. Chip Select Unit ............................................................................ 40 12.1 12.2 12.3 12.4 UCS_n ...................................................................................................................... 40 LCS_n....................................................................................................................... 41 MCSx_n .................................................................................................................... 42 PCSx_n..................................................................................................................... 45 13. Interrupt Controller Unit............................................................... 46 13.1 13.2 13.3 13.4 13.5 Master Mode and Slave Mode .................................................................................. 47 Interrupt Vectors, Types and Priorities ...................................................................... 48 Interrupt Requests .................................................................................................... 49 Interrupt Acknowledge .............................................................................................. 49 Programming Registers ............................................................................................ 50 14. DMA Unit........................................................................................ 68 14.1 14.2 14.3 DMA Operation ......................................................................................................... 68 External Requests..................................................................................................... 75 Serial Port/DMA Transfers ........................................................................................ 78 15. Timer Control Unit ........................................................................ 79 15.1 Timer/Counter Unit Output Mode .............................................................................. 84 16. Watchdog Timer............................................................................ 85 17. Asynchronous Serial Port ........................................................... 87 17.1 17.2 17.3 Serial Port Flow Control ............................................................................................ 87 17.1.1 DCE/DTE Protocol..................................................................................................................88 17.1.2 CTS/RTR Protocol..................................................................................................................88 DMA Transfers to/from Serial Ports........................................................................... 89 Asynchronous Modes ............................................................................................... 89 18. PIO Unit ......................................................................................... 95 R8822 Datasheet Final Version 1.7 May 19, 2005 3 RDC® 18.1 R8822 RISC DSP Communication 16-Bit RISC Micro-controller PIO Multi-Function Pins.............................................................................................95 19. DRAM Controller ...........................................................................99 19.1 19.2 Programmable Read/Write Cycle Time .....................................................................99 Programmable Refresh Control...............................................................................100 20. DC Electrical Characteristics.....................................................102 20.1 20.2 20.3 Absolute Maximum Rating ......................................................................................102 Recommended DC Operating Conditions ...............................................................102 DC Electrical Characteristics...................................................................................102 21. AC Electrical Characteristics.....................................................103 22. Thermal Characteristics ............................................................. 116 23. Instruction Set OP-Code and Clock Cycles.............................. 117 24. R8822 Execution Timing ............................................................121 25. Package Information...................................................................122 25.1 25.2 PQFP ......................................................................................................................122 LQFP.......................................................................................................................123 26. Revision History..........................................................................124 4 R8822 Datasheet Final Version 1.7 May 19, 2005 RDC® R8822 RISC DSP Communication 16-Bit RISC Micro-controller 1.16-Bit Micro-controller with 8-Bit or 16-Bit External Data Bus 1. Features z Five-stage pipeline z RISC architecture z Static & synthesizable design z Bus interface - Multiplexed address and data bus z Supports 64Kx16, 128Kx16, 256Kx16 EDO or FP DRAM with auto-refresh control z Three independent 16-bit timers and one independent programmable watchdog timer z The Interrupt controller with seven maskable - Supports a non-multiplexed address bus A[19:0] external interrupts and one non-maskable external - 8-bit or 16-bit external bus dynamic access interrupt - 1M-byte memory address space z Two independent DMA channels - 64K-byte I/O space z Programmable chip-select logic for memory or I/O z Software is compatible with the 80C186 microprocessor z Supports two asynchronous serial channels with bus cycle decoder z Programmable wait-state generators z With 8-bit or 16-bit boot ROM bus size hardware handshaking signals. z Supports CPU ID z Supports 32 PIO pins R8822 Datasheet Final Version 1.7 May 19, 2005 5 RDC® 2. R8822 RISC DSP Communication 16-Bit RISC Micro-controller Block Diagram INT2/INTA0_n INT1/SELECT_n CLKOUTA INT3/INTA1_n/IRQ CLKOUTB INT6-INT4 X1 VCC GND X2 Clock and Power Management INT0 NMI Interrupt Control Unit TMROUT0 TMROUT1 TMRIN0 TMRIN1 Timer Control Unit DRQ0 DRQ1 DMA Unit RST_n LCS_n/ONCE0_n/RAS0_n UCS_n/ONCE1_n MCS0_n MCS1_n/UCAS_n MCS2_n/LCAS_n MCS3_n/RAS1_n PCS5_n/A1 PCS6_n/A2 ARDY SRDY Chip Select Unit DRAM Control Unit Refresh Control Unit Instruction Queue (64bits) Instruction Decoder Micro ROM PIO Unit Register File General, Segment, Eflag Register EA / LA Address RTS0_n/RTR0_n Asynchronous Serial Port0 S2_n/BWSEL S1_n~S0_n DT/R_n DEN_n HOLD HLDA S6/CLKDIV2_n UZI_n A[19:0](MA[8:0]) AD[15:0] 6 PIO[31:0] Control Signal CTS0_n/ENRX0_n TXD0 RXD0 RTS1_n/RTR1_n Bus Interface Unit ALU (Special, Logic, Adder, BSF) Execution Unit Asynchronous Serial Port1 CTS1_n/ENRX1_n TXD1 RXD1 RD_n WHB_n WLB_n WR_n ALE BHE_n/ADEN_n R8822 Datasheet Final Version 1.7 May 19, 2005 RDC® 3. R8822 RISC DSP Communication 16-Bit RISC Micro-controller Pin Description 3.1 Pin Placement AD10 AD2 AD9 82 81 84 83 AD11 AD3 85 AD12 AD4 86 AD5 88 87 AD13 GND 91 89 AD6 92 90 AD14 VCC 93 AD15 AD7 96 94 S6/CLKDIV2_n/PIO29 97 95 TXD1/PIO27 UZI_n/PIO26 98 CTS0_n/ENRX0_n/PIO21 RXD1/PIO28 99 PQFP 100 3.1.1 RXD0/PIO23 1 80 AD1 TXD0/PIO22 2 79 AD8 RTS0_n/RTR0_n/PIO20 3 78 AD0 BHE_n/ADEN_n 4 77 DRQ0/INT5/PIO12 WR_n RD_n 5 76 DRQ1/INT6/PIO13 6 75 TMRIN0/PIO11 ALE 7 74 TMROUT0/PIO10 ARDY 8 73 TMROUT1/PIO1 TMRIN1/PIO0 S2_n/BWSEL 9 72 S1_n 10 71 RST_n S0_n 11 70 GND GND 12 69 MCS3_n/RAS1_n/PIO25 X1 13 68 MCS2_n/LCAS_n/PIO24 X2 14 67 VCC VCC 15 66 PCS0_n/PIO16 CLKOUTA 16 65 PCS1_n/PIO17 CLKOUTB 17 64 GND R8822 GND 18 63 PCS2_n/CTS1_n/ENRX1_n/PIO18 A19/PIO9 19 62 PCS3_n/RTS1_n/RTR1_n/PIO19 A18/PIO8 20 61 VCC VCC 21 60 PCS5_n/A1/PIO3 A17/MA8/PIO7 22 59 PCS6_n/A2/PIO2 LCS_n/ONCE0_n/RAS0_n R8822 Datasheet Final Version 1.7 May 19, 2005 42 43 44 45 46 47 48 49 50 WHB_n WLB_n HLDA HOLD SRDY/PIO6 NMI DT/R_n/PIO4 DEN_n/PIO5 MCS0_n/PIO14 MCS1_n/UCAS_n/PIO15 41 51 40 30 A0 A9/MA4 GND INT4/PIO30 39 INT3/INTA1_n/IRQ 52 38 53 29 VCC 28 A10 A1/MA0 A11/MA5 37 INT2/INTA0_n/PIO31 A2 54 36 INT1/SELECT_n A12 35 55 27 A4 26 A3/MA1 A13/MA6 34 INT0 33 56 A6 25 A5/MA2 UCS_n/ONCE1_n A14 32 57 31 58 24 A8 23 A7/MA3 A16 A15/MA7 7 8 47 48 49 50 A13/MA6 A12 40 CLKOUTB A14 39 CLKOUTA A15/MA7 38 46 37 X2 VCC 45 36 X1 A16 35 GND A17/MA8/PIO7 34 S0_n 44 33 S1_n VCC 32 43 31 ARDY S2_n/BWSEL A18/PIO8 30 ALE 42 29 RD_n 41 28 WR_n GND 27 A19/PIO9 26 BHE_n/ADEN_n INT1/SELECT_n INT2/INTA0_n/PIO31 INT3/INTA1_n/IRQ 76 79 77 INT0 80 RISC DSP Communication 78 LCS_n/ONCE0_n/RAS0_n UCS_n/ONCE1_n 81 PCS5_n/A1/PIO3 PCS6_n/A2/PIO2 VCC 84 82 PCS3_n/RTS1_n/RTR1_n/PIO19 85 83 GND PCS2_n/CTS1_n/ENRX1_n/PIO18 86 PCS1_n/PIO17 87 PCS0_n/PIO16 88 92 89 MCS3_n/RAS1_n/PIO25 93 MCS2_n/LCAS_n/PIO24 GND 94 VCC RST_n 95 90 TMRIN1/PIO0 96 91 TMROUT0/PIO10 TMROUT1/PIO1 97 DRQ1/INT6/PIO13 TMRIN0/PIO11 98 DRQ0/INT5/PIO12 99 100 3.1.2 RTS0_n/RTR0_n/PIO20 RDC® R8822 16-Bit RISC Micro-controller LQFP AD0 1 75 INT4/PIO30 AD8 2 74 MCS1_n/UCAS_n/PIO15 AD1 3 73 MCS0_n/PIO14 AD9 4 72 DEN_n/PIO5 AD2 5 71 DT/R_n/PIO4 AD10 6 70 NMI VCC 15 61 AD14 16 60 A2 AD7 17 59 A3/MA1 AD15 18 58 A4 S6/CLKDIV2_n/PIO29 19 57 A5/MA2 UZI_n/PIO26 20 56 A6 TXD1/PIO27 21 55 A7/MA3 AD3 7 69 SRDY/PIO6 AD11 8 68 HOLD AD4 9 67 HLDA AD12 10 66 WLB_n AD5 11 65 WHB_n GND 12 64 GND AD13 13 63 A0 AD6 14 62 A1/MA0 VCC R8822 RXD1/PIO28 22 54 A8 CTS0_n/ENRX0_n/PIO21 23 53 A9/MA4 RXD0/PIO23 24 52 A10 TXD0/PIO22 25 51 A11/MA5 R8822 Datasheet Final Version 1.7 May 19, 2005 RDC® R8822 RISC DSP Communication 16-Bit RISC Micro-controller 3.2 R8822 PQFP & LQFP Pin-Out Table Pin Name AD0 AD8 AD1 AD9 AD2 AD10 AD3 AD11 AD4 AD12 AD5 GND AD13 AD6 VCC AD14 AD7 AD15 S6/CLKDIV2_n/PIO29 UZI_n/PIO26 TXD1/PIO27 RXD1/PIO28 CTS0_n/ENRX0_n/PIO21 RXD0/PIO23 TXD0/PIO22 RTS0_n/RTR0_n/PIO20 BHE_n/ADEN_n WR_n RD_n ALE ARDY S2_n/BWSEL S1_n S0_n GND X1 X2 VCC CLKOUTA CLKOUTB GND A19/PIO9 A18/PIO8 VCC A17/MA8/PIO7 A16 A15/MA7 A14 A13/MA6 A12 R8822 Datasheet Final Version 1.7 May 19, 2005 LQFP Pin No. PQFP Pin No. Pin Name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 A11/MA5 A10 A9/MA4 A8 A7/MA3 A6 A5/MA2 A4 A3/MA1 A2 VCC A1/MA0 A0 GND WHB_n WLB_n HLDA HOLD SRDY/PI O6 NMI DT/R_n/PIO4 DEN_n/PIO5 MCS0_n/PIO14 MCS1_n/UCAS_n/PIO15 INT4/PIO30 INT3/INTA1_n/IRQ INT2/INTA0_n/PIO31 INT1/SELECT_n INT0 UCS_n/ONCE1_n LCS_n/ONCE0_n/RAS0_n PCS6_n/A2/PIO2 PCS5_n/A1/PIO3 VCC PCS3_n/RTS1_n/RTR1_n/PIO19 PCS2_n/CTS1_n/ENRX1_n/PIO18 GND PCS1_n/PIO17 PCS0_n/PIO16 VCC MCS2_n/LCAS_n/PIO24 MCS3_n/RAS1_n/PIO25 GND RST_n TMRIN1/PIO0 TMROUT1/PIO1 TMROUT0/PIO10 TMRIN0/PIO11 DRQ1/INT6/PIO13 DRQ0/INT5/PIO12 LQFP Pin No. PQFP Pin No. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 31 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 9 RDC® R8822 RISC DSP Communication 16-Bit RISC Micro-controller 3.3 Functional Description I = Input; O = Output; z CPU Core PIN No. (PQFP) 15, 21, 38, 61, 67, 92 12, 18, 41, 64, 70, 89 Symbol Type VCC I System power: +5 volt power supply. GND I System ground. 71 RST_n I 13 14 X1 X2 I O 16 CLKOUTA O 17 CLKOUTB O Description Reset inputReset Input. When RST_n is asserted, the CPU immediately terminates all operations, clears the internal registers & logic, and transfers the address to the reset address FFFF0h. Input to the oscillator amplifier. Output from the inverting oscillator amplifier. Clock Output A. CLKOUTA operates at the crystal input frequency (X1). CLKOUTA remains active during reset and bus hold conditions. Clock Output B. CLKOUTB operates at the crystal input frequency (X1). CLKOUTB remains active during reset and bus hold conditions. z Asynchronous Serial Port Interface 10 PIN No. (PQFP) Symbol Type 1 RXD0/PIO23 I/O 2 TXD0/PIO22 O/I 3 RTS0_n/RTR0_n/PIO20 O/I 100 CTS0_n/ENRX0_n/PIO21 I/O 98 TXD1/PIO27 O/I 99 RXD1/PIO28 I/O Description Receive Data for Asynchronous Serial Port 0. This pin receives asynchronous serial data. Transmit Data for Asynchronous Serial Port 0. This pin transmits asynchronous serial data from the UART of the micro-controllers. Ready to Send/Ready to Receive Signals for Asynchronous Serial Port 0. When the RTS0 bit in the AUXCON register is set and the FC bit in the Serial Port 0 Control register is set, the RTS0_n signal is enabled. Otherwise, when the RTS0 bit is cleared and the FC bit is set, the RTR0_n signal is enabled. Clear to Send/Enable Receiver Request Signals for Asynchronous Serial Port 0. When the ENRX0 bit in the AUXCON register is cleared and the FC bit in the Serial Port 0 Control register is set, the CTS0_n signal is enabled. Otherwise, when the ENRX0 bit is set and the FC bit is set, the ENRX0_n signal is enabled. Transmit Data for Asynchronous Serial Port 1. This pin transmits asynchronous serial data from the UART of the micro-controllers. Receive Data for Asynchronous Serial Port 1. This pin receives asynchronous serial data. R8822 Datasheet Final Version 1.7 May 19, 2005 RDC® R8822 RISC DSP Communication 16-Bit RISC Micro-controller 62 PCS3_n/RTS1_n/RTR1_n /PIO19 O/I 63 PCS2_n/CTS1_n /ENRX1_n/PIO18 I/O Ready to Send/Ready to Receive Signals for Asynchronous Serial Port 1. When the RTS1 bit in the AUXCON register is set and FC bit in the Serial Port 1 Control register is set, the RTS1_n signal is enabled. Otherwise, when the RTS1 bit is cleared and the FC bit is set, the RTR1_n signal is enabled. Clear to Send/Enable Receiver Request Signals for Asynchronous Serial Port 1. When the ENRX1 bit in the AUXCON register is cleared and the FC bit in the Serial Port 1 Control register is set, the CTS1_n signal is enabled. Otherwise, when the ENRX1 bit is set and the FC bit is set, the ENRX1_n signal is enabled. z Bus Interface PIN No. Symbol Type 4 BHE_n/ADEN_n O/I 5 WR_n O 6 RD_n O 7 ALE O 8 ARDY I R8822 Datasheet Final Version 1.7 May 19, 2005 Description Bus High Enable/Address Enable. During a memory access, the BHE_n and (AD0 or A0) encodings indicate types of the bus cycle. BHE_n is asserted during T1 and keeps the asserted to T3 and Tw. This pin is floating during bus holds and resets. BHE_n and (AD0 or A0) Encodings BHE_n AD0 or A0 Types of Bus Cycle 0 0 Word transfer 0 1 High byte transfer (D[15:8]) 1 0 Low byte transfer (D[7:0]) 1 1 Refresh The address portion of the AD bus can be enabled or disabled by the DA bit in the LMCS and UMCS register during LCS or UCS bus cycle accesses if BHE_n/ADEN_n is held high during power-on resets. No external pull-up resistor is required because BHE_n/ADEN_n is with a weak internal pull-up resistor. The AD bus always drives both addresses and data during LCS or UCS bus cycle accesses if the BHE_n/ADEN_n pin is with an external pull-low resistor during resets. Write Strobe. This pin indicates that the data on the bus is to be written into a memory or an I/O device. WR_n is active during T2, T3 and Tw of any write cycle, floating during a bus hold or reset. Read Strobe. It’s an active low signal indicates that the micro-controller is performing a memory or I/O read cycle. RD_n is floating during a bus hold or reset. Address Latch Enable. Active high. This pin indicates that an address output on the AD bus. The address is guaranteed to be valid on the trailing edge of ALE. This pin is tri-stated during ONCE mode and never floating during a bus hold or reset. Asynchronous Ready. This pin indicates to the micro-controller that the address memory space or I/O device will complete a data transfer. The ARDY pin accepts a rising edge that is asynchronous to CLKOUTA and is active high. The falling edge of ARDY must be synchronized to CLKOUTA. Tie ARDY high, so the micro-controller is always asserted in ready condition. If ARDY is not used, tie this pin low to yield control to SRDY. Both SRDY and ARDY should be tied to high if the system need not assert wait-states by externality. 11 RDC® 9 10 11 S2_n/BWSEL S1_n S0_n 19 20 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 39 40 A19/PIO9 A18/PIO8 A17/MA8/PIO7 A16 A15/MA7 A14 A13/MA6 A12 A11/M15 A10 A9/MA4 A8 A7/MA3 A6 A5/MA2 A4 A3/MA1 A2 A1/MA0 A0 94, 91, 88, 86, 84, 82, 80, 78 95, 93, 90, 87, 85, 83, 81, 79 42 12 R8822 RISC DSP Communication 16-Bit RISC Micro-controller O/I O O Address Bus. Non-multiplexed memory or I/O addresses. The A bus is one half of a CLKOUTA period earlier than the AD bus. These pins are high-impedance during bus holds or resets. O/I MA[8:0]: DRAM Address Interface. The MA bus is multiplexed with A bus. When the DRAM is accessed, the bus performs row or column address, otherwise the bus performs address bus. AD[7:0] I/O AD[15:8] WHB_n Bus Cycle Status. These pins are encoded to indicate the bus status. S2_n can be used as memory or I/O indicator. S1_n can be used as DT/R_n indicator. These pins are floating during bus holds and resets. S2_n/BWSEL is to decide the boot ROM bus width when the RST_n pin goes from low to high. If S2_n/BWSEL is with a pull-low resistor (330 ohm), the boot ROM bus width is 8 bits. Otherwise, the boot ROM bus width is 16 bits. Bus Cycle Encoding Description S2_n S1_n S0_n Bus Cycle 0 0 0 Interrupt acknowledge 0 0 1 Read data from I/O 0 1 0 Write data to I/O 0 1 1 Halt 1 0 0 Instruction fetch 1 0 1 Read data from memory 1 1 0 Write data to memory 1 1 1 Passive O The Multiplexed Address and Data Bus for Memory or I/O Accesses. The address is present during the t1 clock phase and the data bus phase is in t2-t4 cycle. The address phase of the AD bus cannot be disabled when the BHE_n/ADEN_n pin is with an external pull-low resistor during resets. The AD bus is in high-impedance state during bus hold or reset conditions. This bus can also be used to load system configuration information (with pull-up or pull-low resistors) into the RESCON register when the reset input goes from low to high. Write High Byte. This pin indicates that the high byte data (AD[15:8]) on the bus is to be written to a memory or I/O device. WHB_n is the logic OR of BHE_n and WR_n. This pin is floating during resets or bus holds. R8822 Datasheet Final Version 1.7 May 19, 2005 RDC® R8822 RISC DSP Communication 16-Bit RISC Micro-controller 43 WLB_n O 44 HLDA O 45 HOLD I 46 SRDY/PIO6 I/O 48 DT/R_n/PIO4 O/I 49 DEN_n/PIO5 O/I 96 S6/CLKDIV2_n/PIO29 O/I 97 UZI_n/PIO26 O/I R8822 Datasheet Final Version 1.7 May 19, 2005 Write Low Byte. This pin indicates that the low byte data (AD[7:0]) on the bus is to be written to a memory or I/O device. WLB_n is the logic OR of WR_n and A0. This pin is floating during resets or bus holds. Bus Hold Acknowledge. Active high. The micro-controller will issue an HLDA in response to a HOLD request by the external bus master at the end of T4 or Ti. When the micro-controller is in hold status (HLDA is high), AD[15:0], A[19:0], WR_n, RD_n, DEN_n, S0_n–S2_n, S6, BHE_n, DT/R_n, WHB_n and WLB_n are floating, and UCS_n, LCS_n, PCS6_n–PCS5_n, MCS3_n–MCS0_n and PCS3_n–PCS0_n will be driven high. After HOLD is detected as being low, the micro-controller will lower HLDA. Bus Hold Request. Active high. This pin indicates that another bus master is requesting the local bus. Synchronous Ready. This pin indicates to the micro-controller that the address memory space or I/O device will complete a data transfer. The SRDY pin accepts a falling edge that is asynchronous to CLKOUTA and is active high. SRDY is accomplished by elimination of the one-half clock period required to internally synchronize ARDY. Tie SRDY high, so the micro-controller is always asserted in ready condition. If SRDY is not used, tie this pin low to yield control to ARDY. Both SRDY and ARDY should be tied to high if the system need not assert wait-states by externality. Data Transmit or Receive. This pin indicates the direction of data flow through an external data-bus transceiver. When DT/R_n is asserted low, the micro-controller receives data. When DT/R_n is asserted high, the micro-controller writes data to the data bus. Data Enable. This pin is provided as a data bus transceiver output enable. DEN_n is asserted during memory and I/O accesses. DEN_n is driven high when DT/R_n changes states. It is floating during bus hold or reset conditions. Bus Cycle Status bit6/Clock Divided by 2. For S6 feature, this pin is set to low to indicate a micro-controller-initiated bus cycle or high to indicate a DMA-initiated bus cycle during T2, T3, Tw and T4. For CLKDIV2_n feature, the internal clock of the micro-controller is the external clock divided by 2 (CLKOUTA, CLKOUTB=X1/2) if this pin is held low during power-on resets. The pin is sampled on the rising edge of RST_n. Upper Zero Indicate. This pin is the logical OR of the inverted A[19:16]. It is asserted in the T1 and held throughout the cycle. 13 RDC® R8822 RISC DSP Communication 16-Bit RISC Micro-controller z Chip Select Unit Interface PIN No. Symbol Type 50 51 68 69 MCS0_n/PIO14 MCS1_n/UCAS_n/PIO15 MCS2_n/LCAS_n/PIO24 MCS3_n/RAS1_n/PIO25 O/I 57 UCS_n/ONCE1_n O/I 58 LCS_n/ONCE0_n/RAS0_n O/I 59 60 PCS6_n/A2/PIO2 PCS5_n/A1/PIO3 O/I 62 63 65 66 PCS3_n/RTS1_n/RTR1_n/PIO19 PCS2_n/CTS1_n/ENRX1_n/PIO18 PCS1_n/PIO17 PCS0_n/PIO16 O/I 14 Description Midrange Memory Chip Selects. For MCS_n feature, these pins are active low when the MMCS register is enabled to access a memory. The address ranges are programmable. MCS3_n–MCS0_n are held high during bus holds. When bit 6 of the UMCS (A0h) register is set to 1, UCS_n will be disabled and MCS3_n–MCS1_n will be activated as bank1 control signals RAS1_n, LCAS_n and UCAS_n of the DRAM controller. The DRAM memory is located from 80000h to FFFFFh. Upper Memory Chip Select/ONCE Mode Request 1. For UCS_n feature, this pin is active low when the system accesses the defined upper 512K-byte (80000h-FFFFFh) memory block. UCS_n defaults to active from F0000h to FFFFFh after power-on resets. UCS_n address range is programmed by software. For ONCE1_n feature, if ONCE0_n and ONCE1_n are sampled low on the rising edge of RST_n, the micro-controller enters ONCE mode. In ONCE mode, all pins are high-impedance. This pin incorporates a weak pull-up resistor. Lower Memory Chip Select/ONCE Mode Request 0. For LCS_n feature, this pin is active low when the micro-controller accesses the defined lower 512K-byte (00000h-7FFFFh) memory block. LCS_n address range is programmed by software. For ONCE0_n feature, please see UCS_n/ONCE1_n description. This pin incorporates a weak pull-up resistor. When bit 6 of the LMCS (A2h) register is set to 1, this pin will be activated as RAS0_n which is the row address of DRAM bank 0. Peripheral Chip Selects/Latched Address bits. For PCS_n feature, these pins are active low when the micro-controller accesses the fifth or sixth region of the peripheral memory (I/O or memory space). The base address of PCS_n is programmable. These pins are asserted with the AD address bus and not floating during bus holds. For latched address bit feature, these pins output the latched addresses A2 and A1 when the EX bit in the PCS_n and MCS_n auxiliary register is cleared. A2 and A1 retain previous latched data during bus holds. Peripheral Chip Selects. These pins are active low when the micro-controller accesses the defined memory area of the peripheral memory block (I/O or memory addresses). For I/O accesses, the base address can be programmed in the region from 00000h to 0FFFFh. For memory address accesses, the base address can be located in the 1M-byte memory address region. These pins are asserted with the multiplexed AD address bus and not floating during bus holds. R8822 Datasheet Final Version 1.7 May 19, 2005 RDC® R8822 RISC DSP Communication 16-Bit RISC Micro-controller z Interrupt Control Unit Interface PIN No. Symbol Type 47 NMI I 52 INT4/PIO30 I/O 53 INT3/INTA1_n/IRQ I/O 54 INT2/INTA0_n/PIO31 I/O 55 INT1/SELECT_n I/O 56 INT0 I/O Description Non-maskable Interrupt. NMI is the highest priority hardware interrupt and is non-maskable. When this pin is asserted (the NMI transition from low to high), the micro-controller always transfers the address bus to the location specified by the non-maskable interrupt vector in the micro-controller interrupt vector table. The NMI pin must be asserted for at least one CLKOUTA period to guarantee that the interrupt is recognized. Maskable Interrupt Request 4. Active high. This pin indicates that an interrupt request has occurred. The micro-controller will jump to the INT4 address vector to execute the service routine if INT4 is enabled. The interrupt input can be configured to be either edge- or level-triggered. The requesting device must hold INT4 until the request is acknowledged to guarantee interrupt recognition. Maskable Interrupt Request 3/Interrupt Acknowledge 1/Slave Interrupt Request. For INT3 feature, except the differences in interrupt line and interrupt address vector, the function of INT3 is the same as that of INT4. For INTA1_n feature, in cascade mode or special fully-nested mode, this pin corresponds to INT1. For IRQ feature, when the micro-controller is as a slave device, this pin issues an interrupt request to the master interrupt controller. Maskable Interrupt Request 2/Interrupt Acknowledge 0. For INT2 feature, except the differences in interrupt line and interrupt address vector, the function of INT2 is the same as that of INT4. For INTA0_n feature, in cascade mode or special fully-nested mode, this pin corresponds to INT0. Maskable Interrupt Request 1/Slave Select. For INT1 feature, except the differences in interrupt line and interrupt address vector, the function of INT1 is the same as that of INT4. For SELECT_n feature, when the micro-controller is as a slave device, this pin is driven from the master interrupt controller decoding. This pin is activated to indicate that an interrupt appears on the address and data bus. INT0 must be active before SELECT_n is activated when the interrupt type appears on the bus. Maskable Interrupt Request 0. Except the differences in interrupt line and interrupt address vector, the function of INT0 is the same as that of INT4. z Timer Control Unit Interface PIN No. Symbol Type 72 75 TMRIN1/PIO0 TMRIN0/PIO11 I/O 73 74 TMROUT1/PIO1 TMROUT0/PIO10 O/I R8822 Datasheet Final Version 1.7 May 19, 2005 Description Timer Inputs. These pins can be used as clock or control signal inputs, depending upon the programmed timer mode. After internally synchronizing low to high transitions on TMRIN, the timer controller increments. These pins must be pulled up if not used. Timer outputs. Depending upon timer mode selects, these pins provide single pulses or continuous waveforms. The duty cycles of the waveforms can be programmable. These pins are floating during a bus hold or reset. 15 RDC® R8822 RISC DSP Communication 16-Bit RISC Micro-controller z DMA Unit Interface PIN No. Symbol Type 76 77 DRQ1/INT6/PIO13 DRQ0/INT5/PIO12 I/O Description DMA Request. These pins are asserted high by an external device when the device is ready for DMA channel 1 or channel 0 to perform a transfer. These pins are level-triggered and internally synchronized. The DRQ signals are not latched and must remain active until finish is serviced. For INT6/INT5: When the DMA function is not used, INT6 and INT5 can be used as additional external interrupt requests. They share the corresponding interrupt types and register control bits. INT6/5 are level-triggered only and not necessary to be held until the interrupt is acknowledged. (Interrupt requests are kept on such high levels.) Notes: 1. When the PIO mode and direction registers are configured as PIO modes, the 32 MUX definition pins can be set as PIO pins. For example, DRQ1/INT6/PIO13 (pin76) can be set as PIO13. 2. The PIO status during power-on resets: PIO1, PIO10, PIO22 and PIO23 are inputs with pull-downs, PIO4 to PIO9 are in normal operations, and the others are inputs with pull-ups. 3.4 R8822 I/O Characteristics of Each Pin 16 PQFP Pin No. Pin Name 71 RST_n 8 ARDY 45 47 HOLD NMI CMOS input, with a 50K internal pull-down resistor 56 55 16 17 INT0 INT1/SELECT_n CLKOUTA CLKOUTB Schmitt trigger TTL input, with a 10K internal pull-down resistor 9 S2_n/BWSEL 10 11 43 6 5 S1_n S0_n WLB_n RD_n WR_n 19 20 22 23 24 A19/PIO9 A18/PIO8 A17/MA8/PIO7 A16 A15/MA7 Characteristics Schmitt trigger input, with a 50K internal pull-up resistor Schmitt trigger input, with a 50K internal pull-down resistor 8mA 3-state CMOS output Bi-directional I/O, with a 50K internal pull-up resistor and 4mA TTL output 4mA 3-state CMOS output 12mA 3-state CMOS output Bi-directional I/O, with a 10K enabled/disabled internal pull-up resistor when functioning as PIO and the 10K pull-up resistor disabled for normal function; 16mA TTL output 16mA 3-state CMOS output R8822 Datasheet Final Version 1.7 May 19, 2005 RDC® R8822 RISC DSP Communication PQFP Pin No. Pin Name 25 26 27 28 29 30 31 32 33 34 35 36 37 39 40 78 80 82 84 86 88 91 94 79 81 83 85 87 90 93 95 A14 A13/MA6 A12 A11/MA5 A10 A9/MA4 A8 A7/MA3 A6 A5/MA2 A4 A3/MA1 A2 A1/MA0 A0 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 7 ALE 46 74 73 2 1 SRDY/PIO6 TMROUT0/PIO10 TMROUT1/PIO1 TXD0/PIO22 RXD0/PIO23 4 BHE_n/ADEN_n 42 WHB_n 44 HLDA 54 52 INT2/INTA0_n/PIO31 INT4/PIO30 53 INT3/INTA1_n/IRQ R8822 Datasheet Final Version 1.7 May 19, 2005 16-Bit RISC Micro-controller Characteristics Bi-directional I/O; 16mA TTL output Bi-directional I/O, with a 50K internal pull-down resistor; 4mA TTL output Bi-directional I/O, with a 10K enabled/disabled internal pull-down resistor when functioning as PIO and the 10k pull-down resistor disabled for normal function; 8mA TTL output. Bi-directional I/O, with a 50K internal pull-up resistor; 4mA TTL output Bi-directional I/O, with a 50K internal pull-up resistor; 12mA TTL output 4mA CMOS output Bi-directional I/O, with a 10K enabled/disabled internal pull-up resistor when functioning as PIO and the 10k pull-up resistor disabled for normal function; 8mA TTL output; TTL schmitt trigger input Bi-directional I/O, with a 10K internal pull-up resistor; 8mA TTL output,; TTL schmitt trigger input 17 RDC® PQFP Pin No. Pin Name 57 58 UCS_n/ONCE1_n LCS_n/ONCE0_n/RAS0_n 49 DEN_n/PIO5 48 DT/R_n/PIO4 66 PCS0_n/PIO16 65 PCS1_n/PIO17 63 PCS2_n/CTS1_n/ENRX1_n/PIO18 62 PCS3_n/RTS1_n/RTR1_n/PIO19 60 59 50 51 68 69 18 R8822 RISC DSP Communication 16-Bit RISC Micro-controller Characteristics Bi-directional I/O, with a 10K internal pull-up resistor; 8mA TTL output; TTL schmitt trigger input PCS5_n/A1/PIO3 PCS6_n/A2/PIO2 MCS0_n/PIO14 MCS1_n/UCAS_n/PIO15 MCS2_n/LCAS_n/PIO24 97 MCS3_n/RAS1_n/PIO25 UZI_n/PIO26 96 S6/CLKDIV2_n/PIO29 75 TMRIN0/PIO11 72 TMRIN1/PIO0 77 DRQ0/INT5/PIO12 76 DRQ1/INT6/PIO13 98 TXD1/PIO27 99 RXD1/PIO28 100 CTS0_n/ENRX0_n/PIO21 3 RTS0_n/RTR0_n/PIO20 Bi-directional I/O, with a 10K enabled/disabled internal pull-up resistor when functioning as PIO and the 10k pull-up resistor disabled for normal function; 8mA TTL output R8822 Datasheet Final Version 1.7 May 19, 2005 RDC® 4. R8822 RISC DSP Communication 16-Bit RISC Micro-controller Basic Application System Block Flash ROM AD[15:0] Data(16) A[19:1] Address X1 WR_n WE_n RD_n OE_n UCS_n CE_n X2 RS232 Serial port 0 SRAM Level Converter Data(16) R8822 Address RS232 Level Serial port 1 WE_n OE_n Converter Timer0-1 INTx_n LCS_n CE_n A0 LB_n BHE_n UB_n DMA Peripheral VCC PIO Data Address 100K WE_n OE_n RST_n 1uF PCSx_n CS_n BASIC APPLICATION SYSTEM BLOCK (A) Flash ROM High Byte X1 AD[15:0] D[15:8] A[19:1] Low Byte D[7:0] Address Address RD_n OE_n OE_n UCS_n CE_n CE_n WHB_n WE_n WE_n X2 RS232 Serial port 0 WLB_n SRAM Level High Byte Converter R8822 RS232 Level Serial port 1 Converter Low Byte D[15:8] D[7:0] Address Address OE_n OE_n CE_n CE_n WE_n WE_n Timer0-1 LCS_n INTx_n DMA VCC Peripheral PIO Data Address 100K OE_n RST_n 1uF PCSx_n CS_n WR_n WE_n BASIC APPLICATION SYSTEM BLOCK (B) R8822 Datasheet Final Version 1.7 May 19, 2005 19 RDC® R8822 RISC DSP Communication 16-Bit RISC Micro-controller Flash ROM X1 AD[15:0] A[19:0] WR_n RD_n UCS_n X2 Data(16)or(8) Address WE_n OE_n CE_n S2_n/BWSEL 330R EDO/FP-DRAM RS232 Flash ROM byte/word access selection byte access with a 330ohm pull-low resistor Level Serial port 0 R8822 Converter RS232 Level Serial port 1 RAS_n UCAS_n LCAS_n WR_n RD_n Converter (256Kx16) Timer0-1 INTx_n VCC DMA PIO Peripheral 100K 1uF RST_n Data(16) MA[0:8] RAS_n UCAS_n LCAS_n WE_n OE_n PCSx_n WR_n RD_n Data(16)or(8) Address CS_n WE_n OE_n BASIC APPLICATION SYSTEM BLOCK (C) 20 R8822 Datasheet Final Version 1.7 May 19, 2005 RDC® R8822 RISC DSP Communication 16-Bit RISC Micro-controller 4.5. Read/Write Timing Diagram T1 T2 T3 CLKOUTA T4 TW A[19:0] ADDRESS S6 AD[15:0] ADDRESS DATA ALE RD_n BHE_n UCS_n,LCS_n PCSx_n,MCSx_n DEN_n DT/R_n S2_n~S0_n STATUS UZI_n READ CYCLE R8822 Datasheet Final Version 1.7 May 19, 2005 21 RDC® R8822 RISC DSP Communication 16-Bit RISC Micro-controller T1 T2 T3 CLKOUTA T4 TW A[19:0] ADDRESS S6 AD[15:0] ADDRESS DATA ALE WR_n WHB_n, WLB_n BHE_n UCS_n, LCS_n PCSx_n, MCSx_n DEN_n DT/R_n S2_n~S0_n STATUS UZI_n WRITE CYCLE 22 R8822 Datasheet Final Version 1.7 May 19, 2005 RDC® 6. R8822 RISC DSP Communication 16-Bit RISC Micro-controller Crystal Characteristics 4.16.1 Fundamental Mode X1 Rf C1 X2 R8822 C2 L C3 For fundamental-mode crystal: Reference values Frequency Rf C1 C2 C3 L 10.8288MHz None 10Pf 10Pf None None 19.66MHz None 10Pf 10Pf None None 30MHz None None 10Pf None None 33MHz None None 10Pf None None 28.322MHz 1.5M 15Pf 30Pf 220Pf 10uL 33.177MHz 1.5M 15Pf 30Pf 220Pf 4.7uL 40MHz 1.5M 15Pf 30Pf 220Pf 2.7uL 40MHz None None 10Pf None None For third-overtone mode crystal: Reference values Frequency Rf C1 C2 C3 L R8822 Datasheet Final Version 1.7 May 19, 2005 22.1184MHz 1M 15Pf 30Pf None None 23 RDC® 7. R8822 RISC DSP Communication 16-Bit RISC Micro-controller Execution Unit 6.17.1 General Registers The R8822 has eight 16-bit general registers. The AX, BX, CX and DX can be subdivided into two 8-bit registers (AH, AL, BH, BL, CH, CL, DH and DL). The functions of these registers are described as follows: AX: word divide, word multiply, word I/O operation AH: byte divide, byte multiply, byte I/O, decimal arithmetic, translate operation AL: byte divide, byte multiply operation BX: translate operation CX: loops, string operation CL: variable shift and rotate operation DX: word divide, word multiply, indirect I/O operation SP: stack operations (POP, POPA, POPF, PUSH, PUSHA and PUSHF) BP: general-purpose registers which can be used to determine offset address of operands in memory SI: string operations DI: string operations High 15 Data Group Index Group and Pointer Low 8 7 0 AX AH AL Accumulator BX BH BL Base Register CX CH CL Count/Loop/Repeat/Shift DX DH DL Data SP Stack Pointer BP Base Pointer SI Source Index DI Destination Index GENERAL REGISTERS 24 R8822 Datasheet Final Version 1.7 May 19, 2005 RDC® R8822 RISC DSP Communication 16-Bit RISC Micro-controller 6.27.2 Segment Registers The R8822 has four 16-bit segment registers: CS, DS, SS and ES. The segment registers contain the base addresses (starting location) of these memory segments. They are immediately addressable for code (CS), data (DS & ES) and stack (SS) memory. CS (Code Segment): The CS register points to the current code segment, which contains instructions to be fetched. The default memory space for all instructions is 64K. The initial value of CS register is 0FFFFh. DS (Data Segment): The DS register points to the current data segment, which generally contains program variables. The DS register is initialized to 0000h. SS (Stack Segment): The SS register points to the current stack segment, which is for all stack operations, such as pushes and pops. The stack segment is used for temporary space. The SS register is initialized to 0000h. ES (Extra Segment): The ES register points to the current extra segment, which is typically for data storage, such as large string operations and large data structures. The DS ES register is initialized to 0000h. 15 8 7 0 CS Code Segment DS Data Segment SS Stack Segment ES Extra Segment SEGMENT REGISTERS 6.37.3 Instruction Pointer and Status Flags Registers IP (Instruction Pointer): The IP is a 16-bit register containing the offset of the next instruction to be fetched. This register cannot be directly accessed by software. It is updated by the bus interface unit and can be changed, saved or restored as a result of program execution. The IP register is initialized to 0000h and the starting execution address for CS:IP is at 0FFFF0h. R8822 Datasheet Final Version 1.7 May 19, 2005 25 RDC® R8822 RISC DSP Communication 16-Bit RISC Micro-controller Register Name: Processor Status Flags Register Reset Value 0000h 15 14 : 13 12 Reserved 11 10 9 8 7 6 5 4 3 2 1 0 OF DF IF TF SF ZF Rsvd AF Rsvd PF Rsvd CF These flags reflect the status after the Execution Unit is executed. Bit Name 15-12 Rsvd 11 OF 10 DF 9 IF 8 TF 7 SF 6 ZF 5 Rsvd 4 AF 3 Rsvd 2 PF 1 Rsvd 0 CF 26 Description Reserved. Overflow Flag. If an arithmetic overflow occurs, this flag will be set. Direction Flag. If this flag is set, the string instructions are in the process of incrementing addresses. If DF is cleared, the string instructions are in the process of decrementing addresses. Refer to the STD and CLD instructions for setting and clearing the DF flag. Interrupt-Enable Flag. Refer to the STI and CLI instructions for setting and clearing the IF flag. Set 1: The CPU enables the maskable interrupt requests. Set 0: The CPU disables the maskable interrupt requests. Trace Flag. Set to enable single-step mode for debugging; cleared to disable the single-step mode. If an application program sets the TF flag with a POPF or IRET instruction, a debug exception is generated after the instruction (The CPU automatically generates an interrupt after each instruction) that follows the POPF or IRET instruction. Sign Flag. If this flag is set, the high-order bit of the result of an operation will be 1, indicating the state of being negative. Zero Flag. If this flag is set, the result of the operation will be zero. Reserved Auxiliary Flag. If this flag is set, there will be a carry from the low nibble to the high one or a borrow from the high nibble to the low one of the AL general-purpose register. It is used in BCD operation. Reserved Parity Flag. If this flag is set, the result of the low-order 8-bit operation will have even parities. Reserved Carry Flag. If CF is set, there will be a carry out or a borrow into the high-order bit of the instruction result. R8822 Datasheet Final Version 1.7 May 19, 2005 RDC® R8822 RISC DSP Communication 16-Bit RISC Micro-controller 6.47.4 Address Generation 6.5 The Execution Unit generates a 20-bit physical address to the Bus Interface Unit by Address Generation. Memory is organized in sets of segments. Each segment contains a 16-bit value. Memory is addressed with a two-component address that consists of a 16-bit segment and 16-bit offset. The Physical Address Generation figure describes how the logical address is transferred to the physical address. Shift left 4 bits 1 2 F 15 1 2 F 9 19 0 0 0 1 15 1 0 2 0 9 Segment Base 0 0 1 15 2 Logical Address Offset 0 2 0 F A 19 2 Physical Address 0 TO Memory Physical Address Generation R8822 Datasheet Final Version 1.7 May 19, 2005 27 RDC® R8822 RISC DSP Communication 16-Bit RISC Micro-controller 7.8. Peripheral Register List The peripheral control block can be mapped into either memory or I/O space by programming the FEh register. It starts at FF00h in I/O space when the microprocessor is reset. The definitions of all the peripheral control block registers are listed in the following table and the complete descriptions arranged in the related block units. Offset (HEX) FE FA F6 F4 F2 F0 E6 E4 E2 DA D8 D6 D4 D2 D0 CA C8 C6 C4 C2 C0 A8 A6 A4 A2 A0 88 86 84 82 80 7A 78 76 74 72 70 28 Register Name Peripheral Control Block Relocation Register Disable Peripheral Clock Register Reset Configuration Register Processor Release Level Register Auxiliary Configuration Register Power-Save Control Register Watchdog Timer Control Register Refresh Counter Register Refresh Reload Value Counter Register DMA 1 Control Register DMA 1 Transfer Count Register DMA 1 Destination Address High Register DMA 1 Destination Address Low Register DMA 1 Source Address High Register DMA 1 Source Address Low Register DMA 0 Control Register DMA 0 Transfer Count Register DMA 0 Destination Address High Register DMA 0 Destination Address Low Register DMA 0 Source Address High Register DMA 0 Source Address Low Register PCS_n and MCS_n Auxiliary Register Midrange Memory Chip Select Register Peripheral Chip Select Register Low Memory Chip Select Register Upper Memory Chip Select Register Serial Port 0 Baud Rate Divisor Register Serial Port 0 Receive Register Serial Port 0 Transmit Register Serial Port 0 Status Register Serial Port 0 Control Register PIO Data 1 Register PIO Direction 1 Register PIO Mode 1 Register PIO Data 0 Register PIO Direction 0 Register PIO Mode 0 Register Page 29 32 34 29 39 31 83 99 98 72 73 73 73 74 74 69 71 71 71 72 72 44 43 45 41 40 90 90 90 89 88 94 94 95 95 95 96 Offset (HEX) Register Name Page 66 62 60 5E 5C 5A 58 56 54 52 50 46 44 42 40 3E 3C 3A 38 36 34 32 30 2E 2C 2A 28 26 24 22 20 18 16 14 12 10 Timer 2 Mode/Control Register Timer 2 Maxcount Compare A Register Timer 2 Count Register Timer 1 Mode/Control Register Timer 1 Maxcount Compare B Register Timer 1 Maxcount Compare A Register Timer 1 Count Register Timer 0 Mode/Control Register Timer 0 Maxcount Compare B Register Timer 0 Maxcount Compare A Register Timer 0 Count Register Power-Down Configuration Register Serial Port 0 Interrupt Control Register Serial Port 1 Interrupt Control Register INT4 Control Register INT3 Control Register INT2 Control Register INT1 Control Register INT0 Control Register DMA1/INT6 Interrupt Control Register DMA0/INT5 Interrupt Control Register Timer Interrupt Control Register Interrupt Status Register Interrupt Request Register Interrupt In-Service Register Interrupt Priority Mask Register Interrupt Mask Register Interrupt Poll Status Register Interrupt Poll Register End-of-Interrupt Register Interrupt Vector Register Serial Port 1 Baud Rate Divisor Register Serial Port 1 Receive Register Serial Port 1 Transmit Register Serial Port 1 Status Register Serial Port 1 Control Register 81 82 82 80 81 80 80 77 79 79 79 32 51 51 52 53 53 54 55 56 57 58 59 60 61 63 64 65 65 66 67 92 91 91 91 91 R8822 Datasheet Final Version 1.7 May 19, 2005 RDC® Register Offset: R8822 RISC DSP Communication 16-Bit RISC Micro-controller FEh Register Name: Peripheral Control Block Relocation Register Reset Value 000020FFh 15 14 Rsvd S/M_n : 13 12 11 10 9 8 7 Rsvd M/IO_n 6 5 4 3 2 1 0 R [19:8] The Peripheral Control Block (PCB) is mapped into either memory or I/O space by programming this register. When the other chip selects (PCSx_n or MCSx_n) are programmed to zero wait state and the external ready is ignored, PCSx_n or MCSx_n can overlap the control block. Bit Name Attribute Description 15 Rsvd RO Reserved. 14 S/M_n R/W Slave/Master – configures the interrupt controller. Set 0: Master mode. Set 1: Slave mode. 13 Rsvd RO Reserved. 12 M/IO_n R/W 11-0 R[19:8] R/W Memory/IO space. At reset, this bit is set to 0 and the PCB map starts at FF00h in I/O space. Set 1: The peripheral control block (PCB) is located in memory space. Set 0: The PCB is located in I/O space (default). Relocation Address bits. The upper address bits of the PCB base address. The lower eight bits default to 00h. When the PCB is mapped into I/O space, R[19:16] must be programmed to 0000b. Register Offset: F4h Register Name: Processor Release Level Register Reset Value --00D90h 15 14 : 13 12 11 10 9 PRL 8 7 6 5 4 3 2 1 0 1 01 0 1 1 0 0 1 This read-only register specifies the processor release version and RDC identification number. Bit Name Attribute Description 15-13 Read only:011 12-8 Processor Version. 01h: Version A. 02h: Version B 03h: Version C 04h: Version D 7-0 PRL RO ID RO R8822 Datasheet Final Version 1.7 May 19, 2005 RDC identification number is --D9. 29 RDC® 9. R8822 RISC DSP Communication 16-Bit RISC Micro-controller Power-Save & Power-Down PSEN(F0h.15) PWD(46h.15) enable/disable Microprocessor Internal Clock enable/disable CLKIN X1 X2 CLKIN or CLKIN/2 CLK CLOCK Divisior (CLK/2-CLK/128) MUX CLKOUTA CAD(F0h.8) CLKIN/2 Select Divisor Select CAF(F0h.9) F2-F0(F0h.2-F0h.0) S6/CLKDIV2_n MUX CLKOUTB CBD(F0h.10) CBF(F0h.11) System Clock The CPU provides power-save & power-down functions. * Power-Save: In power-save mode, users can program the Power-Save Control Register to divide the internal operating clock. Users can also disable each non-used peripheral clock by programming the Disable Peripheral Clock Register. * Power-Down: The CPU can enter power-down mode (stop clock) when the Power-Down Configuration Register is programmed and the CPU runs in full-speed or power-save mode. The CPU will be waked up when each one of the external INT0, INT1, INT2, INT3 and INT4 pins is active high, and the CPU operating clock will go back to full-speed mode if the INT function is serviced (the interrupt flag is enabled). If the interrupt flag is disabled, the CPU will be waked up by INT, the operating clock will go back to the previous operating clock state, and the CPU will execute the next program counter instruction. It will wait 19-bit counter time for the crystal clock to be stable when the CPU wakes up from the stop clock mode. 30 R8822 Datasheet Final Version 1.7 May 19, 2005 RDC® R8822 RISC DSP Communication 16-Bit RISC Micro-controller Register Offset: F0h Register Name: Power-Save Control Register Reset Value 0000000h : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PSEN MCSBI T 0 0 CBF CBD CAF CAD 0 0 0 0 0 F2 F1 F0 Bit Name Attribute 15 PSEN R/W 14 MCSBIT R/W 13-12 Rsvd RO 11 CBF R/W 10 CBD R/W 9 CAF R/W 8 CAD R/W 7-3 Rsvd RO Description Enable Power-Save Mode. This bit is cleared by hardware when an external interrupt occurs. This bit will not change when software interrupts (INT instructions) and exceptions occur. Set 1: Enable power-save mode and divide the internal operating clock by values in F[2:0]. MCS0_n Control bit. Set 0: MCS0_n operates normally. Set 1: MCS0_n is active over the entire MCSx_n range Reserved. CLKOUTB Output Frequency selection. Set 1: The CLKOUTB output frequency is the same as the crystal input frequency. Set 0: The CLKOUTB output frequency, which is the same as the internal clock frequency of the microprocessor, is generated from the clock divisor. CLKOUTB Drive Disable Set 1: Disable CLKOUTB. This pin will be three-stated. Set 0: Enable CLKOUTB. CLKOUTA Output Frequency selection. Set 1: The CLKOUTA output frequency is the same as the crystal input frequency. Set 0: The CLKOUTA output frequency, which is the same as the internal clock frequency of the microprocessor, is generated from the clock divisor. CLKOUTA Drive Disable. Set 1: Disable CLKOUTA. This pin will be three-stated. Set 0: Enable CLKOUTA. Reserved. Clock Divisor Select. F2, 2-0 F[2:0] R8822 Datasheet Final Version 1.7 May 19, 2005 R/W F1, F0 ----- Divider Factor 0, 0, 0 ---- Divide by 1 0, 0, 1 ---- Divide by 2 0, 1, 0 ---- Divide by 4 0, 1, 1 ---- Divide by 8 1, 0, 0 ---- Divide by 16 1, 0, 1 ---- Divide by 32 1, 1, 1, 1, 0 1 ------- Divide by 64 Divide by 128 31 RDC® R8822 RISC DSP Communication 16-Bit RISC Micro-controller Register Offset: FAh Register Name: Disable Peripheral Clock Register Reset Value 0000000h : 15 14 13 12 IntClk UART Clk DMA Clk Timer Clk 11 10 9 8 7 6 5 4 3 2 0 Reserved Bit Name Attribute 15 IntClk R/W Set 1 to stop the Interrupt controller clock. 14 UARTClk R/W Set 1 to stop the asynchronous serial port controller clock. 13 DMAClk R/W Set 1 to stop the DMA controller clock. 12 TimerClk R/W Set 1 to stop the timer controller clock. 11-0 Rsvd RO Reserved. Description Register Offset: 46h Register Name: Power-Down Configuration Register Reset Value 00000h : 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PWD 0 0 0 0 0 0 WIF 0 0 0 I4 I3 I2 I1 I0 Bit 32 Name Attribute Description 15 PWD R/W Power-Down Enable. When this bit is set to 1, the CPU will enter power-down mode, then the crystal clock will stop. The CPU will be waked up when an external INT (INT4–INT0]) is active high. It will wait 19-bit counter time for the crystal clock to be stable before the CPU is waked up. 14-9 Rsvd RO Reserved. 8 WIF R/W Wake-up Interrupt Flag. Read-only bit. When the CPU is waked up by interrupts from power-down mode, this bit will be set to 1 by hardware. Otherwise this bit is 0. 7-5 Rsvd RO Reserved. 4-0 I[4:0] R/W Enable the external interrupt (INT4 – INT0) wake-up function. Set these bits to 1 to make the INT pins function as power-down wake-up pins. R8822 Datasheet Final Version 1.7 May 19, 2005 RDC® R8822 RISC DSP Communication 16-Bit RISC Micro-controller 10. Reset Processor initialization is accomplished with activation of the RST_n pin. To reset the processor, this pin should be held low for at least seven oscillator periods. The Reset Status Figure shows the status of the RST_n pin and the other related pins. When RST_n goes from low to high, the state of input pins (with weak pull-up or pull-down resistors) will be latched, and each pin will perform its individual function. AD [15:0] will be latched into Register F6h. UCS_n/ONCE1_n and LCS_n/ONCE0_n/RAS0_n will enter ONCE mode (all of the pins will be floating except X1 and X2) when they are with pull-low resistors. The input clock will be divided by 2 when S6/CLKDIV2_n is with a pull-low resistor. The AD[15:0] bus will drive both of the address and data regardless of the DA bit setting during UCS_n and LCS_n cycles if BHE_n/ADEN_n is with a pull-low resistor CLKOUTA RST_n min 7T A[19:0] ffff0 (float) (input) S6 AD[15:0] (input) ea fff0 ALE (float) (float) RD_n (input) BHE_n (input) UCS_n (float) DEN_n DT/R_n (float) S2_n~S0_n 7 (float) 4 7 4 Reset Status R8822 Datasheet Final Version 1.7 May 19, 2005 33 RDC® R8822 RISC DSP Communication 16-Bit RISC Micro-controller Register Offset: F6h Register Name: Reset Configuration Register Reset Value AD [15:0] 15 14 : 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RC Bit 15-0 34 Name RC Attribute Description RO Reset Configuration AD[15:0]. AD [15:0] must be with weak pull-up or pull-down resistors to correspond to the contents when they are latched into this register as the RST_n signal goes from low to high. The value of the Reset Configuration Register provides system information when this register is read by software. This register is read only and the contents remain valid until next processor is reset. R8822 Datasheet Final Version 1.7 May 19, 2005 RDC® R8822 RISC DSP Communication 16-Bit RISC Micro-controller 10.11. Bus Interface Unit The bus interface unit drives address, data, status and control information to define a bus cycle. A[19:0] form a non-multiplexed memory or I/O address bus and AD[15:0] form a multiplexed address and data bus for memory or I/O accesses. S2_n–S0_n are encoded to indicate the bus status, which is described in Chapter 3.3 (Functional Description). The Basic Application System Block (Chapter 4) and Read/Write Timing Diagram (Chapter 5) describe the basic bus operations. When the DRAM controller is enabled and the microcontroller accesses the DRAM, AD[15:0] will perform the DRAM data bus. MA[8:0] form a bus which is multiplexed with Address bus. 10.211.1 Memory and I/O Interface The memory space consists of 1M bytes (512K 16-bit port) and the I/O space consists of 64K bytes (32K 16-bit port). Memory devices exchange information with the CPU during memory read, memory write and instruction fetch bus cycles. I/O read and I/O write bus cycles use a separate I/O address space. Only IN/OUT instructions can access I/O address space, and information must be transferred between the peripheral devices and the AX register. The first 256 bytes of I/O space can be accessed directly by the I/O instructions. The entire 64K-byte I/O address space can be accessed indirectly through the DX register. The I/O instructions always force address A[19:16] to low level. FFFFFH Memory Space 1M Bytes 0FFFFH I/O Space 0 64K Bytes 0 Memory and I/O Space R8822 Datasheet Final Version 1.7 May 19, 2005 35 RDC® 10.311.2 R8822 RISC DSP Communication 16-Bit RISC Micro-controller Data Bus The data bus for memory address space is physically implemented by dividing the address space into two banks of up to 512K bytes. One bank connects to the lower half of the data bus and contains the even-addressed bytes (A0=0); the other bank connects to the upper half of the data bus and contains odd-addressed bytes (A0=1). A0 and BHE_n determine either one bank or both banks participate in data transfers. A19:1 512K Bytes FFFFF FFFFD 512K Bytes FFFFE FFFFC 5 3 1 4 2 0 D15:8 BHE_n D7:0 A0 Physical Data Bus Models 10.411.3 Wait States Wait states extend the data phase of the bus cycle. As long as the ARDY or SRDY input remains with low level, wait states will be inserted in. If R2 bit=0, wait states can also be inserted in by programming the internal chip select registers. The R2 bit of UMCS (offset A0h) defaults to be low, so either ARDY or SRDY should be in ready state (with a pull-high resistor) when at power-on resets or external resets. The wait-state counter value is decided by the R3, R1 and R0 bits in each chip select register. There are five groups of the R3, R1 and R0 bits in Register offset A0h, A2h, A4h, A6h and A8h, and each group is independent. R2 bit in control registers SRDY D ARDY D Q CLKOUTA CLKOUTA Bus Ready Q Falling Edge Wait-State Counter Rising Edge Bus Ready is active High Wait State Block Diagram 36 The R2 bit in UMCS defaults to "0", so the CPU requires external ready at power-on reset. The wait-state counter value is located at control registers in chip select unit. R8822 Datasheet Final Version 1.7 May 19, 2005 RDC® 10.611.4 R8822 RISC DSP Communication 16-Bit RISC Micro-controller Bus Hold When another bus master requests a bus hold condition (HOLD is active high), the microprocessor will issue an HLDA in response to a HOLD request at the end of T4 or Ti. When the microprocessor is in hold status (HLDA is high), AD[15:0], A[19:0], WR_n, RD_n, DEN_n, S2_n–S0_n, S6, BHE_n, DT/R_n, WHB_n and WLB_n are floating, and UCS_n, LCS_n, PCS6_n–PCS5_n, MCS3_n–MCS0_n and PCS3_n–PCS0_n will be driven high. After HOLD is detected as being low, the microprocessor will lower HLDA. Case 1 Case 2 Ti T3 Ti T4 Ti Ti Ti Ti CLKOUTA HOLD HLDA AD[15:0] Floating Floating A[19:0] Floating DEN_n S6 Floating RD_n Floating WR_n Floating DT/R_n Floating S2_n-S0_n 2 7 Floating Floating WLB_n BUS HOLD ENTER WAVEFORMS R8822 Datasheet Final Version 1.7 May 19, 2005 37 RDC® R8822 RISC DSP Communication Case 1 Case 2 16-Bit RISC Micro-controller Ti Ti Ti Ti Ti T4 Ti Ti T1 T1 CLKOUTA HOLD HLDA AD[15:0] A[19:0] Floating DATA Floating ADDRESS Floating DEN_n S6 RD_n WR_n DT/R_n S2_n-S0_n WLB_n Floating Floating Floating Floating Floating 7 6 Floating BUS HOLD LEAVE WAVEFORMS 11.5 Bus Width The R8822 defaults to 16-bit bus access and the bus can be programmed as 8-bit or 16-bit access when memory or I/O access is located in the LCS_n, MCSx_n or PCSx_n address space. The UCS_n code fetch selection can be 8-bit or 16-bit bus width, which is decided by the S2_n/BWSEL pin input status as the RST_n pin goes from low to high. When the S2_n/BWSEL pin is with a pull-low resistor, the code fetch selection is 8-bit bus width. The DRAM bus width is 16 bits, which cannot be changed. 38 R8822 Datasheet Final Version 1.7 May 19, 2005 RDC® R8822 RISC DSP Communication 16-Bit RISC Micro-controller Register Offset: F2h Register Name: Auxiliary Configuration Register Reset Value 0000h 15 14 : 13 12 11 Reserved 10 9 8 7 6 5 4 3 USIZ ENRX1 RTS1 ENRX0 RTS0 2 1 0 LSIZ MSIZ IOSIZ Bit Name Attribute Description 15-8 Rsvd RO 7 USIZ R/W 6 ENRX1 R/W 5 RTS1 R/W 4 ENRX0 R/W 3 RTS0 R/W 2 LSIZ R/W 1 MSIZ R/W 0 IOSIZ R/W Reserved. Boot Code Bus Width. This bit reflects the S2_n/BWSEL pin input status when the RST_n pin goes from low to high. Set 0: 16-bit bus width booting when the S2_n/BWSEL pin is without a pull-low resistor. Set 1: 8-bit bus width booting when the S2_n/BWSEL pin is with a 330 ohm pull-low resistor. Enable the Receiver Request of Serial Port 1. Set 1: The CTS1_n/ENRX1_n pin is configured as ENRX1_n. Set 0: The CTS1_n/ENRX1_n pin is configured as CTS1_n. Enable Request to Send of Serial Port 1. Set 1: The RTR1_n/RTS1_n pin is configured as RTS1_n. Set 0: The RTR1_n/RTS1_n pin is configured as RTR1_n. Enable the Receiver Request of Serial Port 0. Set 1: The CTS0_n/ENRX0_n pin is configured as ENRX0_n. Set 0: The CTS0_n/ENRX0_n pin is configured as CTS0_n. Enable Request to Send of Serial port 0. Set 1: The RTR0_n/RTS0_n pin is configured as RTS0_n. Set 0: The RTR0_n/RTS0_n pin is configured as RTR0_n. LCS_n Data Bus Size selection. This bit cannot be changed while executing from the LCS_n space or while the Peripheral Control Block is overlaid with the PCS_n space. Set 1: 8-bit data bus access when the memory access is located in the LCS_n memory space. Set 0: 16-bit data bus access when the memory access is located in the LCS_n memory space. MCSx_n and PCSx_n Memory Space Data Bus Size selection. This bit cannot be changed while executing from the associated address space or while the Peripheral Control Block is overlaid on this address space. Set 1: 8-bit data bus access when the memory access is located in the selected memory space. Set 0: 16-bit data bus access when the memory access is located in the selected memory space. I/O Space Data Bus Size selection. This bit determines the width of the data bus for all I/O space accesses. Set 1: 8-bit data bus access. Set 0: 16-bit data bus access. R8822 Datasheet Final Version 1.7 May 19, 2005 39 RDC® R8822 RISC DSP Communication 16-Bit RISC Micro-controller 11.12. Chip Select Unit The Chip Select Unit provides 12 programmable chip select pins to access a specific memory or peripheral device. The chip selects are programmed through five peripheral control registers (A0h, A2h, A4h, A6h and A8h) and all the chip selects can be inserted wait states in by programming the peripheral control registers. 11.112.1 UCS_n UCS_n defaults to active on reset for code accesses with a default memory range of 64K bytes (F0000h – FFFFFh) and three wait states automatically inserted. However, the base address and size of the upper memory block are programmable up to 512K bytes (80000h – FFFFFh). If no wait states are inserted, UCS_n will be driven low within four CLKOUTA oscillatorsCLKOUTA when active.three Register Offset: A0h Register Name: Upper Memory Chip Select Register Reset Value F03Bh 15 1 : 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 DA UDEN 1 1 1 R2 R1 R0 LB [2:0] Bit Name Attribute Description 15 Rsvd RO Reserved. 14-12 LB[2:0] R/W LB[2:0], Memory block size selection for the UCS_n chip select pin. The region in which the UCS_n chip select pin is active can be configured by LB[2:0]. The default memory block size is from F0000h to FFFFFh. LB2, LB1, LB0 ---- Memory Block size , Start address, End Address 1 , 1 , 1 ---- 64K , F0000h , FFFFFh 1 , 1 , 0 ---- 128K , E0000h , FFFFFh 1 , 0 , 0 ---- 256K , C0000h , FFFFFh 0 , 0 , 0 ---- 512K , 80000h , FFFFFh 11-8 Rsvd RO Reserved 40 7 DA R/W 6 UDEN R/W Disable Address. If the BHE_n/ADEN_n pin is held high on the rising edge of RST_n, the DA bit will be valid to enable/disable the address phase of the AD bus. If the BHE_n/ADEN_n pin is held low on the rising edge of RST_n, the AD bus will always drive both the address and data, regardless of the DA bit setting. Set 1: Disable the address phase of the AD[15:0] bus cycle when UCS_n is asserted. Set 0: Enable the address phase of the AD[15:0] bus cycle when UCS_n is asserted. Upper DRAM Enable. Set this bit to enable the bank2 (80000h – FFFFFh) DRAM controller. When the UDEN bit is set, the MCS3_n pin becomes RAS1_n, and the MCS1_n and MCS2_n pins become UCAS_n and LCAS_n respectively. The UCS_n R8822 Datasheet Final Version 1.7 May 19, 2005 RDC® R8822 RISC DSP Communication 16-Bit RISC Micro-controller pin is disabled when the UDEN bit is set to 1. Users can boot the code from flash memory with the UCS_n pin and switch space to DRAM bank 1 after system initialization. 5-3 Rsvd RO 2 R2 R/W 1-0 R[1:0] R/W 11.212.2 Reserved Ready Mode. This bit is used to configure the ready mode for the UCS_n chip select. Set 1: external ready is ignored. Set 0: external ready is required. R1-R0, Wait-State value. When R2 is set to 0, wait states can be inserted into an access to the UCS_n memory area. The reset value of (R1,R0) is (1,1). R1, R0 -- Wait States 0, 0 -0 0, 1 -1 1, 0 -2 1, 1 -3 LCS_n LCS_n means lower memory chip selects. The base address and size of the lower memory block (which have no default size on reset) are programmable up to 512K bytes (00000h-7FFFFh). Register A2h must be programmed first before the target memory range is accessed. The LCS_n pin is not active on reset, but any read or write access to the A2h register activates this pin. Register Offset: A2h Register Name: Low Memory Chip Select Register Reset Value : ----- 13 12 15 0 14 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 DA LDEN 1 1 1 R2 R1 R0 UB [2:0] Bit Name Attribute Description 15 Rsvd RO Reserved. 14-12 UB[2:0] R/W UB[2:0], Memory block size selection for the LCS_n chip select pin. The region in which the LCS_n chip select pin is active can be configured by UB[2:0]. The LCS_n pin is not active on reset, but any read or write access to the A2h (LMCS) register activates this pin. UB2, UB1, UB0 ---- Memory Block size , Start address, End Address 0 , 0 , 0 ---64K , 00000h , 0FFFFh 0 , 0 , 1 ---- 128K , 00000h , 1FFFFh 0 , 1 , 1 ---- 256K , 00000h , 3FFFFh 1 , 1 , 1 ---- 512K , 00000h , 7FFFFh 11-8 Rsvd RO Reserved 7 DA R/W Disable Address. If the BHE_n/ADEN_n pin is held high on the rising edge of R8822 Datasheet Final Version 1.7 May 19, 2005 41 RDC® R8822 RISC DSP Communication 6 LDEN R/W 5-3 Rsvd RO 2 R2 R/W 1-0 R[1:0] R/W 12.3 MCSx_n 16-Bit RISC Micro-controller RST_n, the DA bit will be valid to enable/disable the address phase of the AD bus. If the BHE_n/ADEN_n pin is held low on the rising edge of RST_n, the AD bus will always drive the address and data. Set 1: Disable the address phase of the AD[15:0] bus cycle when LCS_n is asserted. Set 0: Enable the address phase of the AD[15:0] bus cycle when LCS_n is asserted. Lower DRAM Enable. This bit is used to enable the bank 0 (00000h-7FFFFh) DRAM controller. Set LDEN to 1, the LCS_n pin becomes RAS0_n and the MCS1_n and MCS2_n pins become UCAS_n and LCAS_n respectively. Reserved Ready Mode. This bit is used to configure the ready mode for the LCS_n chip select. Set 1: external ready is ignored. Set 0: external ready is required. Wait-state value. When R2 is set to 0, wait states can be inserted into an access to the LCS_n memory area. R1, R0 -- Wait States 0, 0 -0 0, 1 -1 1, 0 -2 1, 1 -3 The memory block of MCS3_n – MCS0_n can be located anywhere within the 1M-byte memory space, exclusive of the areas associated with the UCS_n and LCS_n chip selects. The base address and size of the midrange memory block are programmable up to 512K bytes. The 512K MCSx_n block size can only be used when located at address 00000h, and the LCS_n chip selects must not be active in this case. Locating the 512K MCSx_n block size at 80000h is not allowed because it always in conflict with the range of UCS_n or RAS1_n. The MCS_n chip selects are programmed through two registers A6h and A8h, but these select pins are not active on resets. Both of the A6h and A8h registers must be accessed with a read or write to activate MCS3_n–MCS0_n. There is no default value in the A6h and A8h registers, so the A6h and A8h must be programmed first before MCS3_n–MCS0_n are activated. When the DRAM controller is enabled, MCS3_n–MCS1_n are performed as DRAM interface. (Refer to the DRAM Controller unit.) 42 R8822 Datasheet Final Version 1.7 May 19, 2005 RDC® R8822 RISC DSP Communication 16-Bit RISC Micro-controller Register Offset: A6h Register Name: Midrange Memory Chip Select Register Reset Value : ---- 13 12 15 14 11 BA[19:13] Bit Name Attribute 15-9 BA[19:13] R/W 8-3 Rsvd RO 2 R2 R/W 1-0 R[1:0] R/W R8822 Datasheet Final Version 1.7 May 19, 2005 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 R2 R1 R0 Description Base Address. BA[19:13] correspond to bit[19:13] of the 1M-byte (20-bit) programmable base address of the MCS_n chip select block. Bits 12 to 0 of the base address are always 0. The base address can be set to any integer multiple of the size of the memory block size selected in these bits. For example, if the midrange block is 32K bytes, only bits BA[19:15] can be programmed. Therefore, the block address could be located at 20000h or 38000h but not 22000h. The base address of the MCS_n chip select can be set to 00000h only if the LCS_n chip select is not active. The MCS_n chip select address range is not allowed to overlap the LCS_n chip select address range. The MCS_n chip select address range is not allowed to overlap the UCS_n chip select address range, either. Reserved. Ready Mode. This bit is configured to enable/disable the wait states inserted for the MCS_n chip selects. The R1 and R0 bits of this register determine the number of wait states to be inserted. Set 1: external ready is ignored. Set 0: external ready is required. Wait-State Value. R1 and R0 determine the number of wait states inserted into an access to the MCS_n memory area R1, R0 -- Wait States 0, 0 -0 0, 1 -1 1, 0 -2 1, 1 -3 43 RDC® R8822 RISC DSP Communication 16-Bit RISC Micro-controller Register Offset: A8h Register Name: PCS_n and MCS_n Auxiliary Register Reset Value : ── 13 12 15 14 Rsvd 11 M[6:0] 10 9 8 7 6 EX MS 5 4 Reserved 3 2 1 0 R2 R1 R0 Bit Name Attribute Description 15 Rsvd RO 14-8 M[6:0] R/W 7 EX R/W 6 MS R/W Reserved. MCS_n Block Size. These bits determine the total block size for the MCS3_n – MCS0_n chip selects. Each individual chip select is active for one quarter of the total block size. For example, if the block size is 32K bytes and the base address located at 20000h, MCS3_n to MCS0_n are individually active from: MCS0_n – 20000h to 21FFFh; MCS1_n – 22000h to 23FFFh; MCS2_n – 24000h to 25FFFh; MCS3_n – 26000h to 27FFFh. MCSx_n total block size is defined by M[6:0], M[6:0] , Total block size, MCSx_n address active range 0000001b , 8K , 2K 0000010b , 16K , 4K 0000100b , 32K , 8K 0001000b , 64K , 16K 0010000b , 128K , 32K 0100000b , 256K , 64K 1000000b , 512K , 128K Pin Selector. Setting this bit configures the multiplexed outputs as chip selects (PCS6_n – PCS5_n) or A2-A1. Set 1: PCS6_n and PCS5_n are configured as peripheral chip select pins. Set 0: PCS6_n is configured as address bit A2 and PCS5_n configured as A1. Memory or I/O space selector. This bit determines whether the PCSx_n pins are active during memory or I/O bus cycle. Set 1: The PCSx_n pins are active for memory bus cycle. Set 0: The PCSx_n pins are active for I/O bus cycle. 5-3 Rsvd RO 2 R2 R/W 1-0 R[1:0] R/W 44 Reserved. Ready Mode. This bit is configured to enable/disable the wait states inserted for the PCS5_n and PCS6_n chip selects. The R1 and R0 bits of this register determine the number of wait states to be inserted. Set 1: external ready is ignored. Set 0: external ready is required. Wait-State Value. R1 and R0 determine the number of wait states inserted into an access to the PCS5_n – PCS6_n memory area. R1, R0 -- Wait States 0, 0 -0 0, 1 -1 1, 0 -2 1, 1 -3 R8822 Datasheet Final Version 1.7 May 19, 2005 RDC® 11.312.4 R8822 RISC DSP Communication 16-Bit RISC Micro-controller PCSx_n In order to define these pins, the peripheral or memory chip selects are programmed through the A4h and A8h registers. The base address memory block can be located anywhere within the 1M-byte memory space, exclusive of the areas associated with the UCS_n, LCS_n and MCS_n chip selects. If the chip selects are mapped to I/O space, the access range will be 64k bytes. PCS6_n–PCS5_n can be configured from 0 to 3 wait states. PCS3_n–PCS0_n can be configured from 0 to 15 wait states Register Offset: A4h Register Name: Peripheral Chip Select Register Reset Value 0000h---- 15 14 : 13 12 11 10 9 8 7 BA [19:11] Bit Name Attribute 6 5 4 3 2 1 0 1 1 1 R3 R2 R1 R0 Description Base Address. BA[19:11] correspond to bit [19:11] of the 1M-byte (20-bit) programmable base address of the PCS_n chip select block. When the PCS_n chip selects are mapped to I/O space, BA[19:16] must be written to 0000b because the I/O address bus is only 64K bytes (16 bits) wide. PCSx_n address range: PCS0_n : Base Address Base Address+255 PCS1_n : Base Address+256 Base Address+511 PCS2_n : Base Address+512 Base Address+767 PCS3_n : Base Address+768 Base Address+1023 PCS5_n : Base Address+1280 Base Address+1535 PCS6_n : Base Address+1536 Base Address+1791 15-7 BA[19:12] R/W 6-4 Rsvd RO Reserved. 3 R3 R/W 2 R2 R/W See bit[1:0]. Ready Mode. This bit is configured to enable/disable the wait states inserted for the PCS3_n–PCS0_n chip selects. The R3, R1 and R0 bits determine the number of wait states to be inserted. Set 1: external ready is ignored. Set 0: external ready is required. Bit 3, Bit 1-0: R3, R1, R0, Wait-State Value. R3, R1 and R0 determine the number of wait states inserted into an access to the PCS3_n–PCS0_n memory area. 1-0 R[1:0] R8822 Datasheet Final Version 1.7 May 19, 2005 R/W R3, 0, 0, 0, 0, 1, 1, 1, 1, R1, 0, 0, 1, 1, 0, 0, 1, 1, R0 0 1 0 1 0 1 0 1 -- Wait States -0 -1 -2 -3 -5 -7 -9 -15 45 RDC® R8822 RISC DSP Communication 16-Bit RISC Micro-controller 13. Interrupt Controller Unit There are 16 interrupt request sources connected to the controller: 7 maskable interrupt pins (INT0 – INT6); 2 non-maskable interrupts (NMI and WDT); 7 internal unit request sources (Timer 0, 1 and 2; DMA 0 and 1; Asynchronous serial port 0 and 1). Master/Slave Mode Select (FEH.14) Timer0/1/2 Interrupt REQ. 0 Timer0 REQ. 1 INT0 0 Timer1 REQ. 1 INT1 0 Timer2 REQ. 1 DMA0 Interrupt REQ. INT5 Interrupt Type Execation Unit Interrupt REQ. NMI NMI Watchdog Timer Interrupt Control Logic DMA1 Interrupt REQ. 16 Bit INT6 INT2 INT3 EOI Register INT4 Acknowledge Asynchronous Serial Port 0 In-Service Register Asynchronous Serial Port 1 Acknowledge to DMA, Timer,Serial port Unit 16 Bit Internal Address/Data Bus Interrupt Control Unit Block Diagram 46 R8822 Datasheet Final Version 1.7 May 19, 2005 RDC® 13.1 R8822 RISC DSP Communication 16-Bit RISC Micro-controller Master Mode and Slave Mode The interrupt controller can be programmed as master or slave mode (by programming FEh [14]). The master mode has two connections: fully nested mode or cascade mode. INT0 INT1 INT2 INT3 INT4 INT5 INT6 Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Source Source Source Source Source Source Source R8822 Fully Nested Mode Connections Interrupt Sources IR7 INT INT0 INT4 8259 INT5 8259 INT6 INTA CAS3-CAS0 INTA0_n Interrupt Sources CAS3-CAS0 R8822 IR7 INT1 Interrupt Sources 8259 8259 INTA1_n CAS3-CAS0 INT INTA CAS3-CAS0 Interrupt Sources Cascade Mode Connection R8822 Datasheet Final Version 1.7 May 19, 2005 47 RDC® R8822 RISC DSP Communication 16-Bit RISC Micro-controller INT0 8259 INTA0_n R8822 Cascade Address Decode Select_n IRQ Slave Mode Connection 13.2 Interrupt Vectors, Types and Priorities The following table shows the interrupt vector addresses, types and priorities. Programming the priority registers may change the maskable interrupt priorities. The vector address for each interrupt is fixed. Interrupt Source Interrupt Type Divide Error Exception 00h Trace interrupt 01h NMI 02h Breakpoint Interrupt 03h INTO Detected Over Flow Exception 04h Array Bounds Exception 05h Undefined Opcode Exception 06h ESC Opcode Exception 07h Timer 0 08h Reserved 09h DMA 0/INT5 0Ah DMA 1/INT6 0Bh INT0 0Ch INT1 0Dh INT2 0Eh INT3 0Fh INT4 10h Asynchronous Serial port 1 11h Timer 1 12h Timer 2 13h Asynchronous Serial port 0 14h Reserved 15h-1Fh Vector EOI Address Type 00h 04h 08h 0Ch 10h 14h 18h 1Ch 20h 08h 1 1-1 1-2 1 1 1 1 1 2-1 28h 2Ch 30h 34h 38h 3Ch 40h 44h 48h 4Ch 50h 3 4 5 6 7 8 9 9 2-2 2-3 9 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 08h 08h 14h Priority Note * * */** ** ** */** */** Note *: When interrupts occur at the same time, the priority is (1-1 > 1-2); (2-1> 2-2 > 2-3). Note **: The interrupt types of these sources are programmable in slave mode. 48 R8822 Datasheet Final Version 1.7 May 19, 2005 RDC® 13.3 R8822 RISC DSP Communication 16-Bit RISC Micro-controller Interrupt Requests When an interrupt is requested, the internal interrupt controller verifies that the interrupt is enabled (the IF flag is enabled, but no MSK bit is set) and that there is no higher priority interrupt request being serviced or pending. If the interrupt is granted, the interrupt controller uses the interrupt type to access a vector from the interrupt vector table. If the external INT is active (level-triggered) to request the interrupt controller service, the INT pins must be held till the micro-controller enters the interrupt service routine. There is no interrupt-acknowledge output when the micro-controller runs in fully nested mode, so the PIO pin should be used to simulate the interrupt-acknowledge pin if necessary. 13.4 Interrupt Acknowledge The processor requires the interrupt type as an index into the interrupt table. An internal interrupt controller can provide the interrupt type or an external interrupt controller can provide the interrupt type. When the internal interrupt controller provides the interrupt type to the processor, no external bus cycle is generated. When the external interrupt controller provides the interrupt type, the processor will generate two acknowledge bus cycles and the interrupt type will be written to the AD[15:0] lines by the external interrupt controller. R8822 Datasheet Final Version 1.7 May 19, 2005 49 RDC® R8822 RISC DSP Communication 16-Bit RISC Micro-controller T1 T2 T3 T4 T1 T2 T3 T4 CLKOUTA ADDRESS A[19:0] S6 Interrupt TYPE AD[15:0] ALE BHE_n INTA0_n,INTA1_n DEN_n DT/R_n S2_n-S0_n 7 0 INTR ACK 7 0 INTR ACK INTERRUPT ACKNOWLEDGE CYCLE (CASECADE OR SLAVE MODE) 13.5 Programming Registers Registers (Master mode: 44h, 42h, 40h, 3Eh, 3Ch, 3Ah, 38h, 36h, 34h, 32h, 30h, 2Eh, 2Ch, 2Ah, 28h, 26h, 24h and 22h; Slave Mode: 3Ah, 38h, 36h, 34h, 32h, 30h, 2Eh, 2Ch, 2Ah, 28h, 22h and 20h) are programmed by software to define the interrupt controller operation. 50 R8822 Datasheet Final Version 1.7 May 19, 2005 RDC® R8822 RISC DSP Communication 16-Bit RISC Micro-controller Register Offset: 44h Register Name: Serial Port 0 Interrupt Control Register Reset Value 0001Fh 15 14 : 13 12 11 10 9 8 7 6 5 Reserved 4 3 2 1 0 1 MSK PR2 PR1 PR0 (Master Mode) Bit Name Attribute 15-4 Rsvd RO 3 MSK R/W 2-0 PR[2:0] R/W Description Reserved Mask. Set 1: Mask the interrupt source for asynchronous serial port 0. Set 0: Enable serial port 0 interrupts. Priority. These bits determine the priority of the serial port relative to the other interrupt signals. The priority selection: PR[2:0] Priority 000 (High) 0 001 1 010 2 011 3 100 4 101 5 110 6 111 (Low) 7 Register Offset: 42h Register Name: Serial Port 1 Interrupt Control Register Reset Value 0000Fh 15 14 : 13 12 11 10 9 8 7 6 5 4 Reserved 3 2 1 0 MSK PR2 PR1 PR0 (Master Mode) Bit Name Attribute 15-4 Rsvd RO Reserved 3 MSK R/W Mask. Set 1: Mask the interrupt source for asynchronous serial port 1. Set 0: Enable serial port 1 interrupts. 2-0 PR[2:0] R/W Priority. These bits determine the priority of the serial port relative to the other R8822 Datasheet Final Version 1.7 May 19, 2005 Description 51 RDC® R8822 RISC DSP Communication 16-Bit RISC Micro-controller interrupt signals. The priority selection: PR[2:0] Priority 000 001 010 011 100 101 110 111 Register Offset: 40h Register Name: INT4 Control Register Reset Value 000Fh 15 14 : 13 12 11 Reserved 10 9 (High) 0 1 2 3 4 5 6 (Low) 7 8 7 ETM 6 5 Reserved 4 3 2 1 0 LTM MSK PR2 PR1 PR0 (Master Mode) Bit Name Attribute Description 15-8 Rsvd RO 7 ETM R/W 6-5 Rsvd RO 4 LTM R/W 3 MSK R/W 2-0 PR[2:0] R/W Reserved. Edge-Triggered Mode enabled. When this bit is set to 1 and bit 4 set cleared to 0, an interrupt is triggered by a low to high edge. The low to high edge will be latched (one level) till this interrupt is serviced. Reserved. Level-Triggered Mode. Set 1: An interrupt is triggered by the active-high level. Set 0: An interrupt is triggered by the low to high edge. Mask. Set 1: Mask the interrupt source for INT4. Set 0: Enable INT4 interrupts. Interrupt Priority. These bit settings for priority selections are the same as those of bit[2:0] in the 44h register. 52 R8822 Datasheet Final Version 1.7 May 19, 2005 RDC® R8822 RISC DSP Communication 16-Bit RISC Micro-controller Register Offset: 3Eh Register Name: INT3 Control Register Reset Value 000Fh 15 14 : 13 12 11 10 9 8 Reserved 7 ETM 6 5 Reserved 4 3 2 1 0 LTM MSK PR2 PR1 PR0 (Master Mode) Bit Name Attribute Description 15-8 Rsvd RO 7 ETM R/W 6-5 Rsvd RO 4 LTM R/W 3 MSK R/W 2-0 PR[2:0] R/W Reserved Edge-Triggered Mode enabled. When this bit is set to 1 and bit 4 set cleared to 0, an interrupt is triggered by a low to high edge. The low to high edge will be latched (one level) till this interrupt is serviced. Reserved Level-Triggered Mode. Set 1: An interrupt is triggered by the active-high level. Set 0: An interrupt is triggered by the low to high edge. Mask. Set 1: Mask the interrupt source for INT3. Set 0: Enable INT3 interrupts. Interrupt Priority. These bit settings for priority selections are the same as those of bit[2:0] in the 44h register. Register Offset: 3Ch Register Name: INT2 Control Register Reset Value 000Fh 15 14 : 13 12 11 Reserved 10 9 8 7 ETM 6 5 Reserved 4 3 2 1 0 LTM MSK PR2 PR1 PR0 (Master Mode) Bit Name Attribute Description 15-8 Rsvd RO 7 ETM R/W 6-5 Rsvd RO 4 LTM R/W 3 MSK R/W 2-0 PR[2:0] R/W Reserved. Edge-Triggered Mode enabled. When this bit is set and bit 4 set cleared to 0, an interrupt is triggered by a low to high edge. The low to high edge will be latched (one level) till this interrupt is serviced. Reserved Level-Triggered Mode. Set 1: An Interrupt is triggered by the active-high level. Set 0: An interrupt is triggered by the low to high edge. Mask. Set 1: Mask the interrupt source for INT2. Set 0: Enable INT2 interrupts. Interrupt Priority. These bit settings for priority selections are the same as those of bit[2:0] in the 44h register. R8822 Datasheet Final Version 1.7 May 19, 2005 53 RDC® R8822 RISC DSP Communication 16-Bit RISC Micro-controller Register Offset: 3Ah Register Name: INT1 Control Register Reset Value 000Fh 15 14 : 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 ETM SFNM C LTM MSK PR2 PR1 PR0 (Master Mode) Bit Name Attribute Description 15-8 Rsvd RO 7 ETM R/W 6 SFNM R/W 5 C R/W 4 LTM R/W 3 MSK R/W 2-0 PR[2:0] R/W Reserved. Edge-Triggered Mode enabled. When this bit is set and bit 4 set cleared to 0, an interrupt is triggered by a low to high edge. The low to high edge will be latched (one level) till this interrupt is serviced. Special Fully Nested Mode. Set 1: Enable the special fully nested mode for INT1 Cascade Mode. Set 1: Enable the cascade mode for INT1 or INT0. Level-Triggered Mode. Set 1: An Interrupt is triggered by the active-high level. Set 0: An interrupt is triggered by the low to high edge. Mask. Set 1: Mask the interrupt source for INT1. Set 0: Enable INT1 interrupts. Interrupt Priority. These bit settings for priority selections are the same as those of bit[2:0] in the 44h register. Register Offset: 3Ah Register Name: Timer 2 Interrupt Control Register Reset Value 000Fh 15 14 : 13 12 11 10 9 8 7 6 5 4 Reserved 3 2 1 0 MSK PR2 PR1 PR0 (Slave Mode) Bit Name Attribute 15-4 Rsvd RO 3 MSK R/W 2-0 PR[2:0] R/W 54 Description Reserved. Mask. Set 1: Mask the interrupt source for Timer 2. Set 0: Enable Timer 2 interrupts. Interrupt Priority. These bit settings for priority selections are the same as those of bit[2:0] in the 44h register. R8822 Datasheet Final Version 1.7 May 19, 2005 RDC® R8822 RISC DSP Communication 16-Bit RISC Micro-controller Register Offset: 38h Register Name: INT0 Control Register Reset Value 000Fh 15 14 : 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 ETM SFNM C LTM MSK PR2 PR1 PR0 (Master Mode) Bit Name Attribute Description 15-8 Rsvd RO 7 ETM R/W 6 SFNM R/W 5 C R/W 4 LTM R/W 3 MSK R/W 2-0 PR[2:0] R/W Reserved. Edge-Triggered Mode enabled. When this bit is set and bit 4 set cleared to 0, an interrupt is triggered by a low to high edge. The low to high edge will be latched (one level) till this interrupt is serviced. Special Fully Nested Mode. Set 1: Enable the special fully nested mode for INT0 Cascade Mode. Set 1: Enable the cascade mode for INT1 or INT0. Level-Triggered Mode. Set 1: An Interrupt is triggered by the active-high level. Set 0: An interrupt is triggered by the low to high edge. Mask. Set 1: Mask the interrupt source for INT0. Set 0: Enable INT0 interrupts. Interrupt Priority. These bit settings for priority selections are the same as those of bit[2:0] in the 44h register. Register Offset: 38h Register Name: Timer 1 Interrupt Control Register Reset Value 0000h 15 14 : 13 12 11 10 9 8 7 6 5 4 Reserved 3 2 1 0 MSK PR2 PR1 PR0 (Slave Mode) Bit Name Attribute 15-4 Rsvd RO 3 MSK R/W 2-0 PR[2:0] R/W R8822 Datasheet Final Version 1.7 May 19, 2005 Description Reserved. Mask. Set 1: Mask the interrupt source for Timer 1. Set 0: Enable Timer 1 interrupts. Interrupt Priority. These bit settings for priority selections are the same as those of bit[2:0] in the 44h register. 55 RDC® R8822 RISC DSP Communication 16-Bit RISC Micro-controller Register Offset: 36h Register Name: DMA1/INT6 Interrupt Control Register Reset Value 000Fh : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 MSK PR2 PR1 PR0 (Master Mode) Bit Name Attribute 15-4 Rsvd RO 3 MSK R/W 2-0 PR[2:0] R/W Description Reserved. Mask. Set 1: Mask the interrupt source for the DMA1 controller. Set 0: Enable DMA1 interrupts. Interrupt Priority. These bit settings for priority selections are the same as those of bit[2:0] in the 44h register. Register Offset: 36h Register Name: DMA1/INT6 Interrupt Control Register Reset Value 0000h : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 MSK PR2 PR1 PR0 (Slave Mode) Bit Name Attribute 15-4 Rsvd RO 3 MSK R/W 2-0 PR[2:0] R/W 56 Description Reserved. Mask. Set 1: Mask the interrupt source for the DMA 1 controller. Set 0: Enable DMA1 interrupts. Interrupt Priority. These bit settings for priority selections are the same as those of bit[2:0] in the 44h register. R8822 Datasheet Final Version 1.7 May 19, 2005 RDC® R8822 RISC DSP Communication 16-Bit RISC Micro-controller Register Offset: 34h Register Name: DMA0/INT5 Interrupt Control Register Reset Value 000Fh : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 MSK PR2 PR1 PR0 (Master Mode) Bit Name Attribute Description 15-4 Rsvd RO 3 MSK R/W 2-0 PR[2:0] R/W Reserved. Mask. Set 1: Mask the interrupt source for the DMA 0 controller. Set 0: Enable DMA0 interrupts. Interrupt Priority. These bit settings for priority selections are the same as those of bit[2:0] in the 44h register. Register Offset: 34h Register Name: DMA0/INT5 Interrupt Control Register Reset Value 0000h : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 MSK PR2 PR1 PR0 (Slave Mode) Bit Name 15-4 Rsvd Attribute Description RO 3 MSK R/W 2-0 PR[2:0] R/W R8822 Datasheet Final Version 1.7 May 19, 2005 Reserved. Mask. Set 1: Mask the interrupt source for the DMA 0 controller. Set 0: Enable DMA0 interrupts. Interrupt Priority. These bit settings for priority selections are the same as those of bit[2:0] in the 44h register. 57 RDC® R8822 RISC DSP Communication 16-Bit RISC Micro-controller Register Offset: 32h Register Name: Timer Interrupt Control Register Reset Value 000Fh : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 MSK PR2 PR1 PR0 (Master Mode) Bit Name Attribute 15-4 Rsvd RO 3 MSK R/W 2-0 PR[2:0] R/W Description Reserved Mask. Set 1: Mask the interrupt sources for timer controllers. Set 0: Enable interrupts for timer controllers. Interrupt Priority. These bit settings for priority selections are the same as those of bit[2:0] in the 44h register. Register Offset: 32h Register Name: Timer 0 Interrupt Control Register Reset Value 000Fh : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 MSK PR2 PR1 PR0 (Slave Mode) Bit Name Attribute 15-4 Rsvd RO 3 MSK R/W 2-0 PR[2:0] R/W 58 Description Reserved. Mask. Set 1: Mask the interrupt source for the Timer 0 controller. Set 0: Enable Timer 0 interrupts. Interrupt Priority. These bit settings for priority selections are the same as those of bit[2:0] in the 44h register. R8822 Datasheet Final Version 1.7 May 19, 2005 RDC® R8822 RISC DSP Communication 16-Bit RISC Micro-controller Register Offset: 30h Register Name: Interrupt Status Register Reset Value : ---- 13 12 15 14 11 10 DHLT 9 8 7 6 5 4 3 Reserved 2 1 0 TMR2 TMR1 TMR0 (Master Mode) Bit Name Attribute 15 DHLT RO 14-3 Rsvd RO Description DMA Halt. Set 1: Halt any DMA activity when non-maskable interrupts occur. Set 0: When an IRET instruction is executed. Reserved. 2-0 TMR[2:0] R/W Set 1: Indicate that the corresponding timer has an interrupt request pending. Register Offset: 30h Register Name: Interrupt Status Register Reset Value 0000h 15 14 : 13 12 11 DHLT 10 9 8 Reserved 7 6 5 4 3 2 1 0 TMR2 TMR1 TMR0 (Slave Mode) Bit Name Attribute 15 DHLT RO 14-3 Rsvd RO Description DMA Halt. Set 1: Halt any DMA activity when non-maskable interrupts occur. Set 0: When an IRET instruction is executed. Reserved. 2-0 TMR[2:0] R/W Set 1: Indicate that the corresponding timer has an interrupt request pending. R8822 Datasheet Final Version 1.7 May 19, 2005 59 RDC® R8822 RISC DSP Communication 16-Bit RISC Micro-controller Register Offset: 2Eh Register Name: Interrupt Request Register Reset Value : ---- 13 12 15 14 11 Reserved 10 9 8 7 6 5 4 SP0 SP1 I4 I13 1I2 1I1 1I0 3 2 D1/I61 D0/I5 1 0 Rsvd TMR (Master Mode) The Interrupt Request register is a read-only register. For internal interrupts (SP0, SP1, D1/I6, D0/I5 and TMR), the corresponding bit is set to 1 when the device requests an interrupt. The bit is reset during the internally generated interrupt acknowledge. For INT4-INT0 external interrupts, the corresponding bits (I[4:0]) reflect the current values of the external signals. Bit Name Attribute Description 15-11 Rsvd RO Reserved. 10 SP0 RO Serial Port 0 Interrupt Request. Indicates the interrupt status of serial port 0. 9 SP1 RO Serial Port 1 Interrupt Request. Indicates the interrupt status of serial port 1. 8-4 1I[4:10] R/WRO 3-2 D1/1I6 D0/I5 1 Rsvd RO 0 TMR R/WRO Interrupt Requests. Set 1: The corresponding INT pin has an interrupt pending. DMA Channel or INT Interrupt Request. R/WRO Set 1: The corresponding DMA channel or INT has an interrupt pending. Reserved. Timer Interrupt Request. Set 1: The timer control unit has an interrupt pending. Register Offset: 2Eh Register Name: Interrupt Request Register Reset Value 0000h 15 14 : 13 12 11 10 Reserved 9 8 7 6 5 4 3 2 1TMR2 1TRM1 D1/I61 D0/I5 1 0 Rsvd TMR0 (Slave Mode) The Interrupt Request register is a read-only register. For internal interrupts (D1/I6, D0/I5, TMR2, TMR1 and TMR0), the corresponding bit is set to 1 when the device requests an interrupt. The bit is reset during the internally generated interrupt acknowledge. 60 R8822 Datasheet Final Version 1.7 May 19, 2005 RDC® R8822 RISC DSP Communication Bit Name 15-6 Rsvd RO 1 Rsvd RO 0 TMR0 R/WRO 6-4 3-2 16-Bit RISC Micro-controller Attribute Description Reserved. Timer2/Timer1 Interrupt Request. 1TMR[2: R/WRO Set 1: Indicates the state of any interrupt requests from the associated timer. 11] DMA Channel or INT Interrupt Request. D1/I6 R/WRO D0/I5 Set 1: The corresponding DMA channel or INT has an interrupt pending. Reserved. Timer0 Interrupt Request. Set 1: Indicates the state of an interrupt request from Timer 0. Register Offset: 2Ch Register Name: Interrupt In-Service Register Reset Value 0000h 15 14 : 13 12 Reserved 11 10 9 8 7 6 5 4 SP0 SP1 I4 1I3 1I2 1I1 1I0 3 2 D1/1I6 D0/1I5 1 0 Rsvd TMR (Master Mode) In this Register, bits are set by the interrupt controller when the interrupt is taken and cleared by writing the corresponding interrupt type to the EOI register. Bit Name Attribute 15-11 Rsvd RO 10 SP0 RO 9 SP1 RO 8-4 1I[4:10] RO 3-2 D1/1I6 – D0/1I5 RO 1 Rsvd RO 0 TMR RO R8822 Datasheet Final Version 1.7 May 19, 2005 Description Reserved. Serial Port 0 Interrupt In-Service. Set 1: The serial port 0 interrupt is currently being serviced. Serial Port 1 Interrupt In-Service. Set 1: The serial port 1 interrupt is currently being serviced. Interrupt In-Service. Set 1: The corresponding INT interrupt is currently being serviced. DMA Channel or INT Interrupt In-Service. Set 1:The corresponding DMA channel or INT interrupt is currently being serviced. Reserved. Timer Interrupt In-Service. Set 1: The timer interrupt is currently being serviced. 61 RDC® R8822 RISC DSP Communication 16-Bit RISC Micro-controller Register Offset: 2Ch Register Name: Interrupt In-Service Register Reset Value 0000h 15 14 : 13 12 11 10 9 Reserved 8 7 6 5 4 3 2 TMR2 TMR1 D1/16 D0/15 1 0 Rsvd TMR0 (Slave Mode) In this Register, bits are set by the interrupt controller when the interrupt is taken and cleared by writing the corresponding interrupt type to the EOI register. Bit Name Attribute 15-6 Rsvd RO 5-4 TMR[2:1] Ro 3-2 D1/1I6 – D0/1I5 RO 1 Rsvd RO 0 TMR0 RO 62 Description Reserved. Timer2/Timer1 Interrupt In-Service. Set 1: The corresponding timer interrupt is currently being serviced. DMA Channel or INT Interrupt In-Service. Set 1: The corresponding DMA Channel or INT Interrupt is currently being serviced. Reserved. Timer 0 Interrupt In-Service. Set 1: The Timer 0 interrupt is currently being serviced. R8822 Datasheet Final Version 1.7 May 19, 2005 RDC® R8822 RISC DSP Communication 16-Bit RISC Micro-controller Register Offset: 2Ah Register Name: Interrupt Priority Mask Register Reset Value 0007h : 15 14 13 12 11 10 9 8 7 6 5 4 3 0 0 0 0 0 0 0 0 0 0 0 0 0 2 1 0 PRM2 PRM1 PRM0 (Master Mode) It determines the minimum priority level at which maskable interrupts can generate interrupts. Bit Name Attribute 15-3 Rsvd RO Reserved. R/W Priority Field Mask, It determines the minimum priority that is required in order for a maskable interrupt source to generate an interrupt. Priority PR[2:0] 000 (High) 0 001 1 010 2 011 3 100 4 101 5 110 6 111 (Low) 7 2-0 PRM[2:0] Description Register Offset: 2Ah Register Name: Interrupt Priority Mask Register Reset Value 0007h : 15 14 13 12 11 10 9 8 7 6 5 4 3 0 0 0 0 0 0 0 0 0 0 0 0 0 2 1 0 PRM2 PRM1 PRM0 (Slave Mode) It determines the minimum priority level at which maskable interrupts can generate interrupts. Bit Name Attribute 15-3 Rsvd RO Reserved. R/W Priority Field Mask, It determines the minimum priority that is required in order for a maskable interrupt source to generate an interrupt. Priority PR[2:0] 000 (High) 0 001 1 010 2 011 3 100 4 101 5 110 6 111 (Low) 7 2-0 PRM[2:0] R8822 Datasheet Final Version 1.7 May 19, 2005 Description 63 RDC® R8822 RISC DSP Communication 16-Bit RISC Micro-controller Register Offset: 28h Register Name: Interrupt Mask Register Reset Value 07FD0h 15 14 : 13 12 11 Reserved 10 9 8 7 6 5 4 SP0 SP1 I4 1I3 1I2 1I1 1I0 3 2 D1/1I6 D0/1I5 1 0 Rsvd TMR (Master Mode) Bit Name Attribute 15-11 Rsvd RO 10 SP0 RO 9 SP1 RO 8-4 I[4:0] RO 3-2 D1/1I6 – D0/1I5 RO 1 Rsvd RO 0 TMR RO Description Reserved. Serial Port 0 Interrupt Mask. It indicates the state of the mask bit for the asynchronous serial port 0 interrupt. Serial Port 1 Interrupt Mask. It indicates the state of the mask bit for the asynchronous serial port 1 interrupt. Interrupt Masks. They indicate the states of the mask bits for the corresponding interrupts. DMA Channel or INT Interrupt Masks. They indicate the states of the mask bits for the corresponding DMA channel or INT interrupts. Reserved. Timer Interrupt Mask. It indicates the state of the mask bit for the timer control unit. Register Offset: 28h Register Name: Interrupt Mask Register Reset Value 0030Dh 15 14 : 13 12 11 10 Reserved 9 8 7 6 5 4 3 2 TMR2 TMR1 D1/1I6 D0/1I5 1 0 Rsvd TMR0 (Slave Mode) Bit Name Attribute Description 15-6 Rsvd RO 5-4 TMR[2:1] RO 3-2 D1/1I6 – D0/1I5 RO Reserved. Timer2/Timer1 Interrupt Mask. They indicate the states of the mask bits in the Timer Interrupt Control Register. Set 1: Timer2 or Time1 has its interrupt requests masked DMA Channel or INT Interrupt Masks. They indicate the states of the mask bits in the corresponding DMA or INT6/INT5 Control Registers. 1 Rsvd RO Reserved. 0 TMR0 RO Timer0 Interrupt Mask. It indicates the state of the mask bit in the Timer Interrupt Control Register 64 R8822 Datasheet Final Version 1.7 May 19, 2005 RDC® R8822 RISC DSP Communication 16-Bit RISC Micro-controller Register Offset: 26h Register Name: Interrupt Poll Status Register Reset Value : ── 13 12 15 14 11 IREQ 10 9 8 7 6 5 4 3 Reserved 2 1 0 S[4:0] (Master Mode) The Interrupt Poll Status Register mirrors the current state of the Interrupt Poll Register. This register can be read without affecting the current interrupt requests. Bit Name Attribute Description Interrupt Request. Set 1: if an interrupt is pending. The S[4:0] field contains valid data. 15 IREQ R/W 14-5 Rsvd RO Reserved. 4-0 S[4:0] R/W Poll Status. It indicates the interrupt type of the highest priority pending interrupts. Register Offset: 24h Register Name: Interrupt Poll Register Reset Value : ── 13 12 15 14 IREQ 11 10 9 8 7 6 5 4 Reserved 3 2 1 0 S[4:0] (Master Mode) When the Interrupt Poll Register is read, the current interrupt is acknowledged and the next interrupt takes its place in the Interrupt Poll Register. Bit Name Attribute 15 IREQ R/W Interrupt Request. Set 1: if an interrupt is pending. The S[4:0] field contains valid data. 14-5 Rsvd RO Reserved. 4-0 S[4:0] R/W Poll Status. It indicates the interrupt type of the highest priority pending interrupts. R8822 Datasheet Final Version 1.7 May 19, 2005 Description 65 RDC® R8822 RISC DSP Communication 16-Bit RISC Micro-controller Register Offset: 22h Register Name: End-of-Interrupt Register Reset Value : ---- 13 12 15 14 11 NSPEC 10 9 8 7 6 5 4 3 Reserved 2 1 0 S[4:0] (Master Mode) Bit Name 15 NSPEC 14-5 Rsvd 4-0 S[4:0] Description Attribute Non-Specific EOI. Set 1: indicates the non-specific EOI. Set 0: indicates the specific EOI interrupt type in S[4:0]. Reserved. RO Source EOI Type. R/WWO It specifies the EOI type of the interrupt that is currently being processed. R/W Note: We suggest that the specific EOI is the most secure method to use for resetting the In-Service bit. Register Offset: 22h Register Name: Specific End-of-Interrupt Register Reset Value 0000h : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 L2 L1 L0 (Slave Mode) Bit Name Attribute 15-3 Rsvd RO 2-0 L[2:0] RWO 66 Description Reserved. Interrupt Type. The encoded value indicates the priority of the IS (interrupt service) bit to be reset. Writes to these bits cause an EOI issued for the interrupt type in slave mode. R8822 Datasheet Final Version 1.7 May 19, 2005 RDC® R8822 RISC DSP Communication 16-Bit RISC Micro-controller Register Offset: 20h Register Name: Interrupt Vector Register Reset Value 0000h : 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 T[4:0] 3 2 1 0 0 0 0 (Slave Mode) Bit Name Attribute Description 15-8 Rsvd RO Reserved. 7-3 T[4:0] R/W Interrupt Types. The following interrupt types in slave mode can be programmed. Timer 2 interrupt controller: (T4, T3, T2, T1, T0, 1, 0, 1) b. Timer 1 interrupt controller: (T4, T3, T2, T1, T0, 1, 0, 0) b. DMA 1 interrupt controller: (T4, T3, T2, T1, T0, 0, 1, 1) b. DMA 0 interrupt controller: (T4, T3, T2, T1, T0, 0, 1, 0) b. Timer 0 interrupt controller: (T4, T3, T2, T1, T0, 0, 0, 0) b. 2-0 Rsvd RO Reserved. R8822 Datasheet Final Version 1.7 May 19, 2005 67 RDC® R8822 RISC DSP Communication 16-Bit RISC Micro-controller 14. DMA Unit The DMA controller provides the data transfers between the memory and peripherals without the intervention of the CPU. There are two DMA channels in the DMA unit. Each channel can accept DMA requests from one of three sources: external pins (DRQ0 for channel 0 or DRQ1 for channel 1), serial ports (port 0 or port 1), or Timer 2 overflow. The data transfers from sources to destinations can be memory to memory, memory to I/O, I/O to I/O, or I/O to memory. Either bytes or words can be transferred to or from even or odd addresses and two bus cycles are necessary (reads from sources and writes to destinations) for each data transfer. 20-bit Adder/Subtractor Adder Control Logic CAH.4-Channel 0 TDRQ DAH.4-Channel 1 20 bit Timer 2 Request C8h-Transfer Counter Channel 0 C2h,C0h-Source Address Channel 0 C6h,C4h-Destination Address Channel 0 D8h-Transfer Counter Channel 1 DMA Control Logic DRQ0 Request Arbitration Logic DRQ1 Serial Port0 Serial Port1 D2h,D0h-Source Address Channel 1 Interrupt Request D6h,D4h-Destination Address Channel 1 CAh.8-Channel 0 INT DAh.8-Channel 1 Channel Control Register0,CAh 20 bit Channel Control Register1,DAh 16 bit Internal Address/Data Bus DMA Unit Block 14.1 DMA Operation Every DMA transfer consists of two bus cycles (see figure of Typical DMA Transfers). These two bus cycles cannot be separated by a bus hold request, a refresh request or another DMA request. Registers CAh, C8h, C6h, C4h, C2h, C0h, DAh, D8h, D6h, D4h, D2h and D0h are used to configure and operate the two DMA channels. 68 R8822 Datasheet Final Version 1.7 May 19, 2005 RDC® R8822 RISC DSP Communication 16-Bit RISC Micro-controller T1 T2 T3 T4 T1 T2 T3 T4 CLKOUTA ALE A[19:0] Address AD[15:0] Address Data Address Data Address RD_n WR_n Typical DMA Trarsfers Register Offset: CAh (DMA0) Register Name: DMA0 Control Register Reset Value FFF9h0000h 15 14 DM/IO_n DDEC : 13 12 11 DINC SM/IO_n SDEC Bit Name Attribute 15 DM/IO_n R/W 14 DDEC R/W 13 DINC R/W 12 SM/IO_n R/W R8822 Datasheet Final Version 1.7 May 19, 2005 10 9 8 7 6 5 4 3 2 1 0 SINC TC INT SYN1 SYN0 P TDRQ EXT CHG ST B_n/W Description Destination Address Space Select. Set 1: The destination address is in memory space. Set 0: The destination address is in I/O space. Destination Decrement. Set 1: The destination address is automatically decremented after each transfer. The B_n/W (bit 0) bit determines the decremented value is by 1 or 2. When both the DDEC and DINC bits are set to the same value (1 or 0), the address remains constant. Set 0: Disable the decrement function. Destination Increment. Set 1: The destination address is automatically incremented after each transfer. The B_n/W (bit 0) bit determines the incremented value is by 1 or 2. Set 0: Disable the increment function. Source Address Space Select. 69 RDC® 70 R8822 RISC DSP Communication 11 SDEC R/W 10 SINC R/W 9 TC R/W 8 INT R/W 7-6 SYN[1:0] R/W 5 P R/W 4 TDRQ R/W 3 RsvdEXT RO/W 2 CHG R/W 1 ST R/W 0 B_n/W R/W 16-Bit RISC Micro-controller Set 1: The Source address is in memory space. Set 0: The Source address is in I/O space. Source Decrement. Set 1: The Source address is automatically decremented after each transfer. The B_n/W (bit 0) bit determines the decremented value is by 1 or 2. When both the SDEC and SINC bits are set to the same value (1 or 0), the address remains constant. Set 0: Disable the decrement function. Source Increment. Set 1: The Source address is automatically incremented after each transfer. The B_n/W (bit 0) bit determines the incremented value is by 1 or 2. Set 0: Disable the increment function. Terminal Count. Set 1: Synchronized DMA transfers terminate when the DMA Transfer Count Register reaches 0. Set 0: Synchronized DMA transfers do not terminate when the DMA Transfer Count Register reaches 0. Unsynchronized DMA transfers always terminate when the DMA transfer count register reaches 0, regardless of the setting of this bit. Interrupt. Set 1: The DMA unit generates an interrupt request on completion of the transfer count. The TC bit must be set to 1 to generate an interrupt. Synchronization Type Selection. SYN1 , SYN0 -- Synchronization Type 0 , 0 -- Unsynchronized 0 , 1 -- Source synchronized 1 , 0 -- Destination synchronized 1 , 1 -- Reserved Priority. Set 1: It selects high priority for this channel when both DMA 0 and DMA 1 are transferred at the same time. Timer Enable/Disable Request. Set 1: Enable the DMA requests from Timer 2. Set 0: Disable the DMA requests from Timer 2. External IReservednterrupt Enable bit. Set 1: The external pin functions as an interrupt pin (The DMA 0 function is disabled.) Set 0: The external pin functions as a DRQ pin. Changed Start bit. This bit must be set to 1 when the ST bit is modified. Start/Stop DMA channel. Set 1: Start the DMA channel Set 0: Stop the DMA channel Byte/Word Select. Set 1: Word select. The address is incremented or decremented by 2 after each transfer. Set 0: Byte select. The address is incremented or decremented by 1 after each transfer. R8822 Datasheet Final Version 1.7 May 19, 2005 RDC® R8822 Datasheet Final Version 1.7 May 19, 2005 R8822 RISC DSP Communication 16-Bit RISC Micro-controller 71 RDC® R8822 RISC DSP Communication 16-Bit RISC Micro-controller Register Offset: C8h (DMA0) Register Name: DMA0 Transfer Count Register Reset Value 0000h 15 14 : 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TC[15:0] Bit Name Attribute 15-0 TC[15:0] R/W Description DMA0 Transfer Count. The value of this register will be decremented by 1 after each transfer. Register Offset: C6h (DMA0) Register Name: DMA0 Destination Address High Register Reset Value : ----- 13 12 15 14 11 10 9 8 7 6 5 4 3 Reserved 2 1 0 DDA[19:16] Bit Name Attribute Description 15-4 Rsvd RO 3-0 DDA[19:16] R/W Reserved High DMA 0 Destination Address. These bits are mapped to A[19:16] during a DMA transfer when the destination address is in memory or I/O space. If the destination address is in I/O space (64K bytes), these bits must be programmed to 0000b. Register Offset: C4h (DMA0) Register Name: DMA0 Destination Address Low Register Reset Value : ----- 13 12 15 14 11 10 9 8 7 6 5 4 3 2 1 0 DDA[15:0] Bit Name 15-0 DDA[15:0] 72 Attribute Description R/W Low DMA0 Destination Address. These bits are mapped to A[15:0] during a DMA transfer. The value of DDA [19:0] will be incremented or decremented by 2 or 1 after each DMA transfer. R8822 Datasheet Final Version 1.7 May 19, 2005 RDC® R8822 RISC DSP Communication 16-Bit RISC Micro-controller Register Offset: C2h (DMA0) Register Name: DMA0 Source Address High Register Reset Value : ----- 13 12 15 14 11 10 9 8 7 6 5 4 3 Reserved 2 1 0 DSA[19:16] Bit Name Attribute Description 15-4 Rsvd RO 3-0 DSA[19:16] R/W Reserved High DMA0 Source Address. These bits are mapped to A[19:16] during a DMA transfer when the source address is in memory or I/O space. If the source address is in I/O space (64K bytes), these bits must be programmed to 0000b Register Offset: C0h (DMA0) Register Name: DMA0 Source Address Low Register Reset Value : ----- 13 12 15 14 11 10 9 8 7 6 5 4 3 2 1 0 DSA[15:0] Bit Name 15-0 DSA[15:0] Attribute Description R/W Low DMA0 Source Address. These bits are mapped to A[15:0] during a DMA transfer. The value of DSA [19:0] will be incremented or decremented by 2 or 1 after each DMA transfer. Register Offset: DAh (DMA1) Register Name: DMA1 Control Register Reset Value FFF9h0000h 15 14 DM/IO_n DDEC : 13 12 11 DINC SM/IO_n SDEC 10 9 8 7 6 5 4 3 2 1 0 SINC TC INT SYN1 SYN0 P TDRQ EXT CHG ST B_n/W The definitions of bit[15:0] for DMA 1 are the same as those of bit[15:0] in Register CAh for DMA0. R8822 Datasheet Final Version 1.7 May 19, 2005 73 RDC® R8822 RISC DSP Communication 16-Bit RISC Micro-controller Register Offset: D8h (DMA1) Register Name: DMA1 Transfer Count Register Reset Value 0000h 15 14 : 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TC[15:0] Bit Name Attribute 15-0 TC[15:0] R/W Description DMA 1 transfer Count. The value of this register will be decremented by 1 after each transfer. Register Offset: D6h (DMA1) Register Name: DMA1 Destination Address High Register Reset Value : ----- 13 12 15 14 11 10 9 8 7 6 5 4 3 Reserved Bit Name Attribute 15-4 Rsvd RO 3-0 DDA[19:16] R/W 0 Description Reserved High DMA1 Destination Address. These bits are mapped to A[19:16] during a DMA transfer when the destination address is in memory or I/O space. If the destination address is in I/O space (64K bytes), these bits must be programmed to 0000b. D4h (DMA1) Register Name: DMA1 Destination Address Low Register Reset Value : ----- 13 12 14 1 DDA[19:16] Register Offset: 15 2 11 10 9 8 7 6 5 4 3 2 1 0 DDA[15:0] Bit Name 15-0 DDA[15:0] 74 Attribute R/W Description Low DMA 1 Destination Address. These bits are mapped to A[15:0] during a DMA transfer. The value of DDA [19:0] will be incremented or decremented by 2 or 1 after each DMA transfer. R8822 Datasheet Final Version 1.7 May 19, 2005 RDC® R8822 RISC DSP Communication 16-Bit RISC Micro-controller Register Offset: D2h (DMA1) Register Name: DMA1 Source Address High Register Reset Value : ----- 13 12 15 14 11 10 9 8 7 6 5 4 3 Reserved 2 1 0 DSA[19:16] Bit Name Attribute Description 15-4 Rsvd RO 3-0 DSA[19:16] R/W Reserved High DMA 1 Source Address. These bits are mapped to A[19:16] during a DMA transfer when the source address is in memory or I/O space. If the source address is in I/O space (64K bytes), these bits must be programmed to 0000b. Register Offset: D0h (DMA1) Register Name: DMA1 Source Address Low Register Reset Value : ----- 13 12 15 14 11 10 9 8 7 6 5 4 3 2 1 0 DSA[15:0] Bit Name 15-0 DSA[15:0] 14.2 Attribute Description R/W Low DMA1 Source Address. These bits are mapped to A[15:0] during a DMA transfer. The value of DSA[19:0] will be incremented or decremented by 2 or 1 after each DMA transfer. External Requests External DMA requests are asserted on the DRQ pins. The DRQ pins are sampled on the falling edge of CLKOUTACLKOUTA. It takes a minimum of four clocks before the DMA cycle is initiated by the Bus Interface. The DMA request is cleared four clocks before the end of the DMA cycle. No DMA acknowledge is provided, since the chip-selects (MCSx_n and MCSx_n,PCSx_n) can be programmed to be active for a given block of memory or I/O space, and the DMA source and destination address registers can be programmed to point to the same given block. DMA transfers can be either source- or destination-synchronized, and they can also be unsynchronized. The Source-Synchronized Transfers figure shows the typical source-synchronized transfers which provide the source device at least three clock cycles from the time it is acknowledged to de-assert its DRQ line. R8822 Datasheet Final Version 1.7 May 19, 2005 75 RDC® R8822 RISC DSP Communication 16-Bit RISC Micro-controller Fetch Cycle T1 T2 T3 Fetch Cycle T4 T1 T2 T3 T4 CLKOUTA DRQ(Case1) DRQ(Case2) NOTES: Case1 : The current source synchronized transfer will not be immediately followed by another DMA transfer. Case2 : The current source synchronized transfer will be immediately followed by antoher DMA transfer. Source-Synchronized Transfers The Destination-Synchronized Transfers figure shows the typical destination-synchronized transfer which differs from a source-synchronized transfer in which two idle states are added to the end of the deposit cycle. The two idle states extend the DMA cycle to allow the destination device to de-assert its DRQ pin four clocks before the end of the cycle. If the two idle states were not inserted, the destination device would not have time to de-assert its DRQ signal. Fetch Cycle T1 T2 T3 Fetch Cycle T4 T1 T2 T3 T4 TI TI CLKOUTA DRQ(Case1) DRQ(Case2) NOTES: Case1 : The current destination synchronized transfer will not be immediately followed by another DMA transfer. Case2 : The current destination synchronized transfer will be immediately followed by another DMA transfer. Destination-Synchronized Transfers 76 R8822 Datasheet Final Version 1.7 May 19, 2005 Fetch Cycle RDC ® T1 T2 T3 Fetch Cycle T4 T1 T2 RISCCLKOUTA DSP Communication T3 T4 R8822 16-Bit RISC Micro-controller DRQ(Case1) DRQ(Case2) NOTES: Case1 : Current source synchronized transfer will not be immediately followed by another DMA transfer. Case2 : Current source synchronized transfer will be immediately followed by antoher DMA transfer. Source-Synchronized Transfers R8822 Datasheet Final Version 1.7 May 19, 2005 77 RDC® 14.3 R8822 RISC DSP Communication 16-Bit RISC Micro-controller Serial Port/DMA Transfers Serial port data can be transferred to or from memory or I/O space via DMA. The B_n/W bit of the DMA Control Register must be set to 0 for byte transfers. The map address of the Transmit Data Register is written to the DMA Destination Address Register and the memory or I/O address to the DMA Source Address Register when the data are transmitted. The mapped address of the Receive Data Register is written to the DMA Source Address Register and the memory or I/O address to the DMA Destination Address Register when the data are received. The Serial Port Control Register is programmed by software to perform the serial port/DMA transfers. When a DMA channel is in use by a serial port, the corresponding external DMA request signal is de-activated. For DMA transfers to the serial port, the DMA channel should be configured as being destination-synchronized. For DMA transfers from the serial port, the DMA channel should be configured as being source-synchronized. 78 R8822 Datasheet Final Version 1.7 May 19, 2005 RDC® R8822 RISC DSP Communication 16-Bit RISC Micro-controller 15. Timer Control Unit TMRIN1 TMRIN0 Microprocessor Clock 50h,Timer 0 Count Register TMROUT1 52h,54h,Timer0 Maxcount Compare Register Counter Element & Control Logic 58h,Timer 1 Count Register 5Ah,5Ch,Timer 1 Maxcount Compare Register 60h,Timer 2 Count Register TMROUT2 (Timer2) DMA Request (Timer0,1,2) Interrupt Request 62h,Timer 2 Compare Register 16 bit 56h,Timer 0 Control Register 16 bit 5Eh,Timer 1 Control Register 66h,Timer 2 Control Register 16 bit Internal Address/Data Bus Timer / Counter Unit Block There are three 16-bit programmable timers in the R8822. The timer operation is independent of the CPU. These three timers can be programmed as timer elements or as counter elements. Timer 0 and 1 are each connected to two external pins (TMRIN0, TMROUT0, TMRIN1 and TMROUT1), which can be used to count or time external events, or used to generate variable-duty-cycle waveforms. Timer 2 is not connected to any external pins. It can be used as a pre-scaler to Timer 0 and Timer 1 or as a DMA request source. Register Offset: 56h Register Name: Timer 0 Mode/Control Register Reset Value 0000h : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EN INH_n INT RIU 0 0 0 0 0 0 MC RTG P EXT ALT CONT Bit Name 15 EN 14 INH_n R8822 Datasheet Final Version 1.7 May 19, 2005 Attribute Description Enable bit. Set 1: Timer 0 is enabled. Set 0: Timer 0 is inhibited from counting. R/W The INH_n bit must be set to 1 when the EN bit is written, and both the INH_n and EN bits must be in the same write. Inhibit bit. R/W 79 RDC® 80 R8822 RISC DSP Communication 13 INT R/W 12 RIU R/W 11-6 Rsvd RO 5 MC R/W 4 RTG R/W 3 P R/W 2 EXT R/W 1 ALT R/W 0 CONT R/W 16-Bit RISC Micro-controller This bit allows selectively updating the EN bit. The INH_n bit must be set to 1 when the EN bit is written, and both the INH_n and EN bits must be in the same write. This bit is not stored and always read as 0. Interrupt bit. Set 1: An interrupt request is generated when the count register equals a maximum count. If the timer is configured in dual max-count mode, an interrupt is generated each time when the count reaches Max-Count A or Max-Count B. Set 0: Timer 0 will not issue interrupt requests. Register in Use bit. Set 1: The Maxcount Compare B Register of Timer 0 is being used. Set 0: The Maxcount Compare A Register of Timer 0 is being used. Reserved Maximum Count bit. When the timer reaches its maximum count, the MC bit will be set to 1 by H/W. In dual maxcount mode, this bit is set each time when either the Maxcount Compare A or Maxcount Compare B register is reached. This bit is set regardless of the INT bit (offset 56h.13). Re-trigger bit. This bit defines the control function by the input signal of the TMRIN0 pin. When EXT=1 (56h.2), this bit is ignored. Set 1: Timer 0 Count Register (50h) counts internal events; resets the counting on every TMRIN0 input signal from low to high (rising edge trigger). Set 0: Low input holds the Timer 0 Count Register (50h) value; high input enables the counting which counts internal events. The definitions of setting the (EXT, RTG) (0, 0) – Timer 0 counts the internal events if the TMRIN0 pin remains high. (0, 1) – Timer 0 counts the internal events; the count register is reset on every rising transition on the TMRIN0 pin. (1, x) – The TMRIN0 pin input functions as clock source and Timer 0 Count Register is incremented by one every external clock. Pre-scaler bit. This bit and EXT (56h.2) define Timer 0 clock source. The definitions of setting the (EXT, P) (0, 0) – The Timer 0 Count Register is incremented by one every four internal processor clock. (0, 1) – The Timer 0 Count Register is incremented by one which is pre-scaled by Timer 2. (1, x) – The TMRIN0 pin input functions as clock source and the Timer 0 Count Register is incremented by one every external clock. External Clock bit. Set 1: Timer 0 clock source from external events. Set 0: Timer 0 clock source from system clock. Alternate Compare bit. This bit controls whether the timer runs in single or dual maximum count mode. Set 1: Specify dual maximum count mode. In this mode, the timer counts to Maxcount Compare A and resets the count register to 0. Then the timer counts to Maxcount Compare B, resets the count register to 0 again, and starts over with Maxcount Compare A. Set 0: Specify single maximum count mode. In this mode, the timer counts to the value contained in Maxcount Compare A and resets the count register to 0. Then the timer counts to Maxcount Compare A again. Maxcount Compare B is not used in this mode. Continuous Mode bit. Set 1: The timer runs continuously. Set 0: The timer will halt after each counting to the maximum count and the EN bit will be cleared. R8822 Datasheet Final Version 1.7 May 19, 2005 RDC® R8822 RISC DSP Communication 16-Bit RISC Micro-controller Register Offset: 50h Register Name: Timer 0 Count Register Reset Value : ----- 13 12 15 14 11 10 9 8 7 6 5 4 3 2 1 0 TC[15:0] Attribute Description 15-0 TC[15:0] R/W Timer 0 Count Value. This register contains the current count of Timer 0. The count is incremented by one every four internal processor clocks, pre-scaled by Timer 2, or incremented by one every external clock which is through configuring the external clock select bit based on the TMRIN0 signal. Register Offset: 52h Register Name: Timer 0 Maxcount Compare A Register Reset Value : ----- 13 12 Bit 15 Name 14 11 10 9 8 7 6 5 4 3 2 1 0 3 2 1 0 TC[15:0] Bit Name Description Attribute Timer 0 Compare A Value. 15-0 TC[15:0] R/W Register Offset: 54h Register Name: Timer 0 Maxcount Compare B Register Reset Value : ----- 13 12 15 14 11 10 9 8 7 6 5 4 TC[15:0] Bit Name 15-0 TC[15:0] R8822 Datasheet Final Version 1.7 May 19, 2005 Description Attribute R/W Timer 0 Compare B Value. 81 RDC® R8822 RISC DSP Communication 16-Bit RISC Micro-controller Register Offset: 5Eh Register Name: Timer 1 Mode/Control Register Reset Value 0000h : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EN INH_n INT RIU 0 0 0 0 0 0 MC RTG P EXT ALT CONT 3 2 1 0 These bit definitions for timer 1 are the same as those in Register 56h for timer 0. Register Offset: 58h Register Name: Timer 1 Count Register Reset Value : ----- 13 12 15 14 11 10 9 8 7 6 5 4 TC[15:0] Bit Name Attribute Description Timer 1 Count Value. This register contains the current count of Timer 1. The count is incremented by one every four internal processor clocks, pre-scaled by Timer 2, or incremented by one every external clock which is through configuring the external clock select bit based on the TMRIN1 signal. 15-0 TC[15:0] R/W Register Offset: 5Ah Register Name: Timer 1 Maxcount Compare A Register Reset Value : ----- 13 12 15 14 11 10 9 8 7 6 5 4 3 2 1 0 TC[15:0] Bit Name 15-0 TC[15:0] 82 Description Attribute R/W Timer 1 Compare A Value. R8822 Datasheet Final Version 1.7 May 19, 2005 RDC® R8822 RISC DSP Communication 16-Bit RISC Micro-controller Register Offset: 5Ch Register Name: Timer 1 Maxcount Compare B Register Reset Value : ----- 13 12 15 14 11 10 9 8 7 6 5 4 3 2 1 0 TC[15:0] Bit Name Description Attribute Timer 1 Compare B Value. 15-0 TC[15:0] R/W Register Offset: 66h Register Name: Timer 2 Mode/Control Register Reset Value 0000h : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EN INH_n INT 0 0 0 0 0 0 0 MC 0 0 0 0 CONT Bit Name Attribute 15 EN R/W 14 INH_n R/W 13 INT R/W 12-6 Rsvd RO 5 MC R/W 4-1 Rsvd RO 0 CONT R/W R8822 Datasheet Final Version 1.7 May 19, 2005 Description Enable bit. Set 1: Timer 2 is enabled. Set 0: Timer 2 is inhibited from counting. The INH_n bit must be set to 1 when the EN bit is written, and both the INH_n and EN bits must be in the same write. Inhibit bit. This bit allows selectively updating the EN bit. The INH_n bit must be set to 1 when the EN bit is written, and both the INH_n and EN bits must be in the same write. This bit is not stored and is always read as 0. Interrupt bit. Set 1: An interrupt request is generated when the count register equals a maximum count. Set 0: Timer 2 will not issue interrupt requests. Reserved Maximum Count bit. When the timer reaches its maximum count, the MC bit will be set to 1 by H/W. This bit is set regardless of the INT bit (66h.13). Reserved Continuous Mode bit. Set 1: The timer is continuously running when it reaches the maximum count. Set 0: The EN bit (66h.15) is cleared and the timer is held after each timer count reaches the maximum count. 83 RDC® R8822 RISC DSP Communication 16-Bit RISC Micro-controller Register Offset: 60h Register Name: Timer 2 Count Register Reset Value : ── 13 12 15 14 11 10 9 8 7 6 5 4 3 2 1 0 TC[15:0] Bit Name Description Timer 2 Count Value. This register contains the current count of Timer 2. The count is incremented by one every four internal processor clocks. Attribute 15-0 TC[15:0] R/W Register Offset: 62h Register Name: Timer 2 Maxcount Compare A Register Reset Value : ── 13 12 15 14 11 10 9 8 7 6 5 4 3 2 1 0 TC[15:0] Bit Name 15-0 TC[15:0] 15.1 Attribute R/W Description Timer 2 Compare A Value. Timer/Counter Unit Output Mode Timers 0 and 1 can use one maximum count value or two maximum count values. Timer 2 can use only one maximum count value. Timer 0 and Timer 1 can be configured to be single or dual maximum count mode. The TMROUT0 or TMROUT1 signals can be used to generate waveforms of various duty cycles. Maxcount A Maxcount B Maxcount A Maxcount B Dual Maximum Count Mode Single Maximum Count Mode Maxcount A 1T Maxcount A 1T Maxcount A * 1T:One Microprocessor clock Timer/Counter Unit Output Modes 84 R8822 Datasheet Final Version 1.7 May 19, 2005 RDC® 15.216. R8822 RISC DSP Communication 16-Bit RISC Micro-controller Watchdog Timer The R8822 has one independent watchdog timer, which is programmable. The watchdog timer is active after reset and the timeout count is with a maximum count value. The keyed sequence (3333h, CCCCh) must be written to the register (E6h) first, then the new configuration to the Watchdog Timer Control Register. It is a single write, so every write to the Watchdog Timer Control Register must follow this rule. When the watchdog timer is active, an internal counter is counting. If this internal count is over the watchdog timer duration, the watchdog timeout will happen. The keyed sequence (AAAAh, 5555h) must be written to the register (E6h) to reset the internal count and prevent the watchdog timeout. The internal count should be reset before the watchdog timer timeout period is modified to ensure that an immediate timeout will not occur. Register Offset: 60hE6h Register Name: Timer 2 Count RegisterWatchdog Timer Control Register Reset Value ──C080h 15 14 ENA WRST : 13 12 11 RSTFLAG NMIFLAG Bit Name Attribute 15 ENA R/W 14 WRST R/W 13 RSTFLAG R/W 12 NMIFLAG R/W 11-8 Rsvd RO R8822 Datasheet Final Version 1.7 May 19, 2005 10 9 Reserved 8 7 6 5 4 3 2 1 0 COUNT Description Enable the Watchdog Timer. Set 1: Enable the watchdog timer. Set 0: Disable the watchdog timer. Watchdog Reset. Set 1: The WDT generates a system reset when the WDT timeout count is reached. Set 0: The WDT will generate an NMI interrupt when the WDT timeout count is reached if the NMIFLAG bit is 0. If the NMIFLAG bit is 1, the WDT will generate a system reset when timeout. Reset Flag. When a watchdog timer reset event occurs, this bit will be set to 1 by hardware. This bit will be cleared by any read from this register or through external reset. This bit is 0 after an external reset or 1 after a watchdog timer reset. NMI Status Flag After the WDT generates an NMI interrupt, this bit will be set to 1 by H/W. This bit will be cleared by any keyed sequence written to this register. Reserved 85 RDC® 7-0 86 R8822 RISC DSP Communication COUNT R/W 16-Bit RISC Micro-controller Timeout Count. The COUNT setting determines the duration of the watchdog timer timeout interval. Exponent a. The duration equation: Duration =( 2 ) / (Frequency/2) b. The Exponent of the COUNT setting: (bit 7, bit 6, bit 5, bit 4, bit 3, bit 2, bit 1, bit 0) = (Exponent) ( 0 , 0 , 0 , 0, 0 , 0 , 0 , 0 ) = (N/A) ( x , x , x , x, x , x , x , x 1) = ( 10 ) ( x , x , x , x, x , x , 1 , 0 ) = ( 20 ) ( x , x , x , x, x , 1 , 0 , 0 ) = ( 21 ) ( x , x , x , x, 1 , 0 , 0 , 0 ) = ( 22 ) ( x , x , x , 1, 0 , 0 , 0 , 0 ) = ( 23 ) ( x , x , 1 , 0, 0 , 0 , 0 , 0 ) = ( 24 ) ( x , 1 , 0 , 0, 0 , 0 , 0 , 0 ) = ( 25 ) ( 1 , 0 , 0 , 0, 0 , 0 , 0 , 0 ) = ( 26 ) c. Watchdog timer duration reference table: Frequency\ Exponent 10 20 MHz 25 MHz 33 MHz 40 MHz 51 us 40 us 30 us 25 us 20 21 52 ms 104 ms 41 ms 83 ms 31 ms 62 ms 26 ms 52 ms 22 23 209 ms 167 ms 125 ms 104 ms 419 ms 335 ms 251 ms 209 ms 24 25 838 ms 1.67 s 671 ms 1.34 s 503 ms 1.00 s 419 ms 838 ms 26 3.35 s 2.68 s 2.01 s 1.67 s R8822 Datasheet Final Version 1.7 May 19, 2005 RDC® R8822 RISC DSP Communication 16-Bit RISC Micro-controller 16.17. Asynchronous Serial Port The R8822 has two asynchronous serial ports, which provide the TXD and RXD pins for the full duplex bi-directional data transfers with handshaking signals CTS_n, ENRX_n, RTS_n and RTR_n. The serial ports support: 9-bit, 8-bit or 7-bit data transfers; odd parities, even parities or no parity; 1 stop bit; error detection; DMA transfers through the serial ports; multi-drop protocol (9-bit) support; double buffers for transmit and receive. The receive/transmit clock is based on the microprocessor clock. The serial ports can be used in power-saved mode, but the transfer rate must be adjusted to correctly reflect the new internal operating frequency. Software can configure the asynchronous serial ports through programming the registers (80h, 82h, 84h, 86h and 88h – for port 0; 10h, 12h, 14h, 16h and18h – for port 1). Internal Address/Data Bus 16 bit 16 bit Transmit Data Register(84h),(14h) Receive Data Register(86h),(16h) 16 bit 8 bit 8 bit 8 bit TXD Transmit Shift Regoster Transmit Hold Register Receive Buffer 8 bit Interrupt Request RTS_n ENRX_n CTS_n RTR_n Control Register(80h),(10h) Control Logic Receive Shift Register Status Register(82h),(12h) Baud Rate Divisor Register(88h),(18h) RXD Serial Port Block Diagram 17.1 Serial Port Flow Control The two serial ports provide two data pins (RXD and TXD) and two flow control signals (RTS_n and RTR_n). Hardware flow control is enabled when the FC bit in the Serial Port Control Register is set. The flow control signals are configured by software to support several different protocols. R8822 Datasheet Final Version 1.7 May 19, 2005 87 RDC® 17.1.1 R8822 RISC DSP Communication 16-Bit RISC Micro-controller DCE/DTE Protocol The R8822 can function as a DCE (Data Communication Equipment) or a DTE (Data Terminal Equipment). This protocol provides flow control where one serial port is receiving data and the other serial port is sending data. To implement the DCE device, the ENRX bit should be set and the RTS bit should be cleared for the associated serial ports. To implement the DTE device, the ENRX bit should be cleared and the RTS bit should be set for the associated serial ports. The ENRX and RTS bits are found in Register F2h. The DCE/DTE protocol is asymmetric interface since the DTE device cannot signal the DCE device that it is ready to receive data, and the DCE cannot send the requests to send signals. ENRX_n DCE RTR_n RTS_n DTE RTS_n:Request to send CTS_n:Clear to send RTR_n:Ready to receive ENRX_n:Enable receiver request CTS_n DCE/DTE Protocol Connection The DCE/DTE protocol communication steps: a. DTE sends data to DCE b. The RTS_n signal is asserted by the DTE when data is available. c. The RTS_n signal interpreted by the DCE device functions as a request to enable its receiver. d. The DCE asserts the RTR_n signal to response that the DCE is ready to receive data. 17.1.2 CTS/RTR Protocol The serial ports can be programmed as CTS/RTS protocols by clearing both of the ENRX and RTS bits. This protocol is a symmetric interface, which provides flow control when both of the ports are sending and receiving data. CTS_n RTR_n CTS_n:Clear to send RTR_n:Ready to receive RTR_n CTS_n CTS/RTR Protocol Connection 88 R8822 Datasheet Final Version 1.7 May 19, 2005 RDC® 17.2 R8822 RISC DSP Communication 16-Bit RISC Micro-controller DMA Transfers to/from Serial Ports DMA transfers to serial ports function as destination-synchronized DMA transfers. A new transfer is requested when the Transmit Holding Register is empty. When a port is configured for DMA transmits, the corresponding transmit interrupt is disabled regardless of the TXIE bit setting. DMA transfers from serial ports function as source-synchronized DMA transfers. A new transfer is requested when the Receive Buffer contains valid data. When a port is configured for DMA receives, the corresponding receive interrupt is disabled regardless of the RXIE bit setting. The DMA request is generated internally when a DMA channel is used for serial port transfers. DRQ0 or DRQ1 are not active when serial port DMA transfers occur. Hardware handshaking may be used in conjunction with serial port DMA transfers. 17.3 Asynchronous Modes There are 4 mode operations in the asynchronous serial ports. Mode1: Mode 1 is an 8-bit asynchronous communications mode. Each frame consists of a start bit, eight data bits and a stop bit. When parities are used, the eighth data bit becomes a parity bit. Mode 2: Mode 2 is used together with Mode 3 for multiprocessor communications over a common serial link. In mode 2, the RX machine will not complete a reception unless the ninth data bit is a one. Any character received with the ninth bit equal to zero is ignored. No flags are set, no interrupts occur and no data are transferred to the Receive Data Register. In mode 3, characters are received regardless of the state of the ninth data bit. Mode 3: Mode 3 is a 9-bit asynchronous communications mode. Mode 3 is the same as mode 1 except that a frame contains nine data bits. The ninth data bit becomes a parity bit when the parity feature is enabled. Mode 4: Mode 4 is a 7-bit asynchronous communications mode. Each frame consists of a start bit, seven data bits and a stop bit. Parity bits are not available in mode 4. R8822 Datasheet Final Version 1.7 May 19, 2005 89 RDC® R8822 RISC DSP Communication Register Offset: 80h Register Name: Serial Port 0 Control Register Reset Value 0000h 15 14 : 13 DMA 12 11 10 9 8 7 RISE BRK TB8 FC TXIE RXIE Bit Name Attribute 15-13 DMA R/W 12 RSIE R/W 11 BRK R/W 10 TB8 R/W 9 FC R/W 8 TXIE R/W 7 RXIE R/W 6 TMODE R/W 5 RMODE R/W 4 EVN R/W 90 16-Bit RISC Micro-controller 6 5 TMOD RMOD E E 4 3 EVN PE 2 1 0 MODE Description DMA Control Field. With DMA transfers listed as follows, these bits can be configured for serial port use. DMA control bits Transmit (bit 15, bit 14, bit 13) --Receive --( 0, 0, 0 ) --- No DMA --No DMA ( 0, 0, 1 ) --DMA 0 --DMA 1 ( 0, 1, 0 ) --DMA 1 --DMA 0 ( 0, 1, 1 ) --N/A --N/A ( 1, 0, 0 ) --DMA 0 --No DMA ( 1, 0, 1 ) --DMA 1 --No DMA ( 1, 1, 0 ) --- No DMA --DMA 0 ( 1, 1, 1 ) --- No DMA --DMA 1 Receive Status Interrupt Enable. It will generate an interrupt when an error is detected (frame error, parity error or overrun error) or a break interrupt bit is received in serial port 0. Set 1: Enable the serial port 0 to generate an interrupt request. Send Break. Set 1: The TXD pin is always driven low. Long Break: The TXD pin is driven low for greater than (2M+3) bit times; Short break: The TXD pin is driven low for greater than M bit times; * M= start bit + data bit number + parity bit + stop bit Transmit Bit 8. This bit is transmitted as the ninth data bit in mode 2 and mode 3. This bit is cleared after every transmission. Flow Control Enable. Set 1: Enable the hardware flow control for serial port 0. Set 0: Disable the hardware flow control for serial port 0. Transmitter Ready Interrupt Enable. When the Transmit Holding Register is empty (the THRE bit in the Status Register is set), an interrupt will occur. Set 1: Enable the Interrupt. Set 0: Disable the interrupt. Receive Data Ready Interrupt Enable. When the receive buffer contains valid data (the RDR bit in Status Register is set), an interrupt will be generated. Set 1: Enable the Interrupt. Set 0: Disable the interrupt. Transmit Mode. Set 1: Enable the TX machines. Set 0: Disable the TX machines. Receive Mode. Set 1: Enable the RX machines. Set 0: Disable the RX machines. Even Parity. This bit is valid only when the PE bit is set. Set 1: The even parity checking is enforced (even number of 1s in frame). R8822 Datasheet Final Version 1.7 May 19, 2005 RDC® R8822 RISC DSP Communication 16-Bit RISC Micro-controller Set 0: Odd parity checking is enforced (odd number of 1s in frame). 3 2-0 PE Parity Enable. Set 1: Enable the parity checking. Set 0: Disable the parity checking. Modes of Operations. (bit2, bit1, bit0) MODE ( 0 , 0 , 1) Mode 1 ( 0 , 1 , 0) Mode 2 ( 0 , 1 , 1) Mode 3 ( 1 , 0 , 0) Mode 4 R/W MODE R/W Register Offset: 82h Register Name: Serial Port 0 Status Register Reset Value ──----- 15 14 : 13 12 11 Reserved Data Bits 7 or 8 9 8 or 9 7 Parity Bits 1 or 0 N/A 1 or 0 N/A Stop Bits 1 1 1 1 10 9 8 7 6 5 4 3 2 1 0 BRK1 BRK0 RB8 RDR THRE FER OER PER TEMT HS0 Rsvd The Serial Port 0 Status Register provides information about the current status of Serial Port 0. Bit Name Attribute Description 15-11 Rsvd RO 10 BRK1 R/W 9 BRK0 R/W 8 RB8 R/W 7 RDR RO 6 THRE RO 5 FER R/W 4 OER R/W 3 PER R/W 2 TEMT RO 1 HS0 RO 0 Rsvd RO Reserved. Long Break Detected. This bit should be reset by software. When a long break is detected, this bit will be set high. Short Break Detected. This bit should be reset by software. When a short break is detected, this bit will be set high. Received Bit 8. This bit should be reset by software. This bit contains the ninth data bit received in mode 2 and mode 3. Received Data Ready. Read only. The Received Data Register contains valid data. This bit is set high and can only be reset through reading the Serial Port 0 Receive Register. Transmit Holding Register Empty. Read only. When the Transmit Hold Register is ready to accept data, this bit will be set. This bit will be reset when data is written to the Transmit Hold Register. Framing Error detected. This bit should be reset by software. This bit is set when a framing error is detected. Overrun Error Detected. This bit should be reset by software. This bit is set when an overrun error is detected. Parity Error Detected. This bit should be reset by software. This bit is set when a parity error (for mode 1 and mode 3) is detected. Transmitter Empty. This bit is read only. When the Transmit Shift Register is empty, this bit will be set. Handshake Signal 0. This bit is read only. This bit reflects the inverted value of the external CTS0_n pin. Reserved. R8822 Datasheet Final Version 1.7 May 19, 2005 91 RDC® R8822 RISC DSP Communication 16-Bit RISC Micro-controller Register Offset: 84h Register Name: Serial Port 0 Transmit Register Reset Value -----── 15 14 : 13 12 11 10 9 8 7 6 5 4 Reserved 3 2 1 0 TDATA Bit Name Attribute Description 15-8 Rsvd RO 7-0 TDATA RO Reserved. Transmit Data. This register is written by software with data transmitted on Serial Port 0. Register Offset: 86h Register Name: Serial Port 0 Receive Register Reset Value -----── 15 14 : 13 12 11 10 9 8 7 6 5 Reserved 4 3 2 1 0 RDATA Bit Name Attribute Description 15-8 Rsvd RO 7-0 RDATA RO Reserved. Receive DATA. In order to avoid invalid data being read, the RDR bit (82h.4) should be read as 1 before this register is read. Register Offset: 88h Register Name: Serial Port 0 Baud Rate Divisor Register Reset Value 0000h── 15 14 : 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BAUDDIV Bit Name BAUDDI 15-0 V 92 Attribute Description R/W Baud Rate Divisor. The general formula for baud rate divisor is Baud Rate = Microprocessor Clock / (16 x BAUDDIV). For example, if the microprocessor clock is 22.1184MHz and the BAUDDIV=12 (decimal), the baud rate of the serial port will be 115.2K. R8822 Datasheet Final Version 1.7 May 19, 2005 RDC® R8822 RISC DSP Communication 16-Bit RISC Micro-controller Register Offset: 10h Register Name: Serial Port 1 Control Register Reset Value 0000h 15 14 : 13 DMA 12 11 10 9 8 7 RISE BRK TB8 FC TXIE RXIE 6 5 TMOD RMOD E E 4 3 EVN PE 2 1 0 MODE These bit definitions are the same as those of Register 80h. Register Offset: 12h Register Name: Serial Port 1 Status Register Reset Value ──----- 15 14 : 13 12 11 Reserved 10 9 8 7 6 5 4 3 2 1 0 BRK1 BRK0 RB8 RDR THRE FER OER PER TEMT HS0 Rsvd 5 4 3 2 1 0 2 1 0 These bit definitions are the same as those of Register 82h. Register Offset: 14h Register Name: Serial Port 1 Transmit Register Reset Value -----── 15 14 : 13 12 11 10 9 8 7 6 Reserved TDATA These bit definitions are the same as those of Register 84h. Register Offset: 16h Register Name: Serial Port 1 Receive Register Reset Value -----── 15 14 : 13 12 11 10 9 8 7 Reserved 6 5 4 3 RDATA These bit definitions are the same as those of Register 86h. R8822 Datasheet Final Version 1.7 May 19, 2005 93 RDC® R8822 RISC DSP Communication 16-Bit RISC Micro-controller Register Offset: 18h Register Name: Serial Port 1 Baud Rate Divisor Register Reset Value 0000h── 15 14 : 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BAUDDIV These bit definitions are the same as those of Register 88h. 94 R8822 Datasheet Final Version 1.7 May 19, 2005 RDC® R8822 RISC DSP Communication 16-Bit RISC Micro-controller 17.18. PIO Unit The R8822 provides 32 programmable I/O signals, which are multi-function pins with other normal function signals. Through programming Registers 7Ah, 78h, 76h, 74h, 72h and 70h, software can configure these multi-function pins as PIOs or normal functions. For internal pull-up VCC PIO PIO Mode Direction Normal Function Pin D PIO Data In/Out Q VCC Write PDATA Q Read PDATA OE D Microprocessor Clock For internal pull-down Normal Data In "0":abnormal function PIO Pin Operation Diagram 17.118.1 PIO No. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 R8822 Datasheet Final Version 1.7 May 19, 2005 PIO Multi-Function Pins Pin No. (PQFP) Multi Function 72 TMRIN1 73 TMROUT1 59 PCS6_n/A2 60 PCS5_n/A1 48 DT/R_n 49 DEN_n 46 SRDY 22 A17/MA8 20 A18 19 A19 74 TMROUT0 75 TMRIN0 77 DRQ0/INT5 76 DRQ1/INT6 50 MCS0_n 51 MCS1_n/UCAS_n 66 PCS0_n 65 PCS1_n 63 PCS2_n/CTS1_n/ENRX1_n Reset status/PIO internal resistor Input with 10k pull-up Input with 10k pull-down Input with 10k pull-up Input with 10k pull-up Normal operation/Input with 10k pull-up Normal operation/Input with 10k pull-up Normal operation/Input with 10k pull-down Normal operation/Input with 10k pull-up Normal operation/Input with 10k pull-up Normal operation/Input with 10k pull-up Input with 10k pull-down Input with 10k pull-up Input with 10k pull-up Input with 10k pull-up Input with 10k pull-up Input with 10k pull-up Input with 10k pull-up Input with 10k pull-up Input with 10k pull-up 95 RDC® R8822 RISC DSP Communication 19 20 21 22 23 24 25 26 27 28 29 30 31 62 3 100 2 1 68 69 97 98 99 96 52 54 16-Bit RISC Micro-controller PCS3_n/RTS1_n/RTR1_n RTS0_n/RTR0_n CTS0_n/ENRX0_n TXD0 RXD0 MCS2_n/LCAS_n MCS3_n/RAS1_n UZI_n TXD1 RXD1 S6/CLKDIV2_n INT4 INT2 Register Offset: 7Ah Register Name: PIO Data 1 Register Reset Value : ----- 13 12 15 14 11 10 9 8 7 Input with 10k pull-up Input with 10k pull-up Input with 10k pull-up Input with 10k pull-down Input with 10k pull-down Input with 10k pull-up Input with 10k pull-up Input with 10k pull-up Input with 10k pull-up Input with 10k pull-up Input with 10k pull-up Input with 10k pull-up Input with 10k pull-up 6 5 4 3 2 1 0 PDATA [31:16] Bit Name 15-0 PDATA [31:16] Attribute Description R/W PIO Data bits. These bits PDATA[31:16] are mapped to PIO[31:16], which indicate to the driven level when the PIO pin is as an output or reflect the external level when the PIO pin is as an input. Register Offset: 78h Register Name: PIO Direction 1 Register Reset Value FFFFh 15 14 : 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PDIR [31:16] Bit Name 15-0 PDIR[31:16] 96 Attribute R/W Description PIO Direction Register. Set 1: Configure the PIO pin as an input. Set 0: Configure the PIO pin as an output or normal function pin. R8822 Datasheet Final Version 1.7 May 19, 2005 RDC® R8822 RISC DSP Communication 16-Bit RISC Micro-controller Register Offset: 76h Register Name: PIO Mode 1 Register Reset Value 0000h 15 14 : 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PMODE [31:16] Bit 15-0 Name PMODE [31:16] Description Attribute PIO Mode bits. PIO pin definitions are configured by the combination of PIO mode and PIO direction. The PIO pins are programmed individually. The definitions (PIO mode, PIO direction) for PIO pin functions: ( 0 , 0 ) – Normal operation , ( 0 , 1 ) – PIO input with pull-up/pull-down ( 1 , 0 ) – PIO output , ( 1 , 1 ) -- PIO input without pull-up/pull-down R/W Register Offset: 74h Register Name: PIO Data 0 Register Reset Value : ----- 13 12 15 14 11 10 9 8 7 6 5 4 3 2 1 0 PDATA [15: 0] Bit Name Attribute 15-0 PDATA [15:0] R/W Description PIO Data bits. These bits PDATA[15:0] are mapped to PIO[15:0], which indicate to the driven level when the PIO pin is as an output or reflect the external level when the PIO pin is as an input. Register Offset: 72h Register Name: PIO Direction 0 Register Reset Value FC0Fh 15 14 : 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PDIR [15:0] Bit Name 15-0 PDIR[15:0] R8822 Datasheet Final Version 1.7 May 19, 2005 Attribute R/W Description PIO Direction Register. Set 1: Configure the PIO pin as an input. Set 0: Configure the PIO pin as an output or normal function pin. 97 RDC® R8822 RISC DSP Communication 16-Bit RISC Micro-controller Register Offset: 70h Register Name: PIO Mode 0 Register Reset Value 0000h 15 14 : 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PMODE [15:0] Bit Name Attribute 15-0 PMODE[15:0] R/W 98 Description PIO Mode bits. R8822 Datasheet Final Version 1.7 May 19, 2005 RDC® R8822 RISC DSP Communication 16-Bit RISC Micro-controller 19. DRAM Controller The R8822 supports 16-bit EDO or FP DRAM control interface. The supporting types are 256K*16,128K*16, 64K*16 or 32K*16. The DRAM control pins are multiplexed pins, which have been described in the Pin Description Chapter. The Basic System Application Block Diagram shows the connection between the microcontroller and DRAM. The DRAM controller supports two banks and dual CAS_n signals (high byte signal UCAS_n and low byte signal LCAS_n operating modes) accesses. When bit 6 of LMCS (A2h) register is set to 1, bank 0 will be enabled and all the bit definitions of A2h are for bank 0 of the DRAM controller. When bit 6 of UMCS (A0h) is set to 1, bank 1 is enabled and all bit definitions of A0h are for bank 1 of the DRAM controller. The memory block size of DRAM is programmable. The memory space of bank 0 is from 00000h to 7FFFFh. Users can program register A2h (LMCS) to select 64K-, 128K-, 256K- or 512K-byte memory block size. The memory space of bank 1 is from 80000h to FFFFFh. Users can configure register A0h (UMCS) to select 64K-, 128K-, 256K- or 512K-byte memory block size. The Address Mapping of MA8 – MA0 & Row, Column Signals: DRAM Address MA0(A1) MA1(A3) MA2(A5) MA3(A7) MA4(A9) MA5(A11) MA6(A13) MA7(A15) MA8(A17) BANK 0 BANK 1 RAS0_n (Pin 58) RAS1_n (Pin 69) Row Address Mapping A1 A3 A5 A7 A9 A11 A13 A15 A17 Column Address Mapping A2 A4 A6 A8 A10 A12 A14 A16 A18 UCAS_n (Pin 51) LCAS_n (Pin 68) UCAS_n (Pin 51) LCAS_n (Pin 68) WE_n (Pin 5) WE_n (Pin 5) OE_n (Pin 6) OE_n (Pin 6) *** The pin numbers are for PQFP configuration *** 19.1 Programmable Read/Write Cycle Time The DRAM Controller read/write cycle depends on the external wait-state signal (ARDY or SRDY) and bit 0 and bit 1 of registers A0h and A2h. The default wait-state of bank 1 is 3 wait-states. The wait-state bits for bank 0 should be programmed after the CPU is reset. R8822 Datasheet Final Version 1.7 May 19, 2005 99 RDC® 19.2 R8822 RISC DSP Communication 16-Bit RISC Micro-controller Programmable Refresh Control The DRAM controller provides self-refresh or CAS_n before RAS_n refresh control. The hardware will auto-stop the self-refresh operation when the controller accesses the DRAM data when the DRAM is in self-refresh mode. During a refresh cycle, the AD bus will drive the address to FFFFFh and the UCS_n signal won’t be asserted. The CPU will enter the idle state during a refresh cycle and be held for 7 clock cycles. If two banks of DRAM are being used in a system, both banks will be refreshed at the same time. The reload counter (E2h) should be set to more than 12h. Users should base on the system clock to configure the reload value. The normal refresh rate on a DRAM is 15.6us. The refresh counter will be started when the EN bit (bit 15 of E4h) is enabled. Wait States & Refresh Counter Values for Reference: System clock DRAM Speed Wait States Refresh Cycle clocks 25 MHz 70ns 0 7 33MHz 70ns 1 7 60ns 0 7 40MHz 70ns 2 7 60ns 1 7 50ns 0 7 40ns 0 7 Register Offset: E2h Register Name: Refresh Reload Value Counter Register Reset Value : ----- 13 12 15 14 11 10 0 9 8 7 6 5 Refresh Reload Counter Value 186h 203h 203h 270h 270h 270h 270h 4 3 2 1 0 RC[14:0] Bit Name Attribute 15 Rsvd RO Reserved 14-0 RC[14:0] R/W Refresh Counter Reload Values. The counter value should be set to more than 12h. 100 Description R8822 Datasheet Final Version 1.7 May 19, 2005 RDC® R8822 RISC DSP Communication 16-Bit RISC Micro-controller Register Offset: E4h Register Name: Refresh Counter Register Reset Value : ----- 13 12 15 14 11 EN 10 9 8 7 6 5 4 3 2 1 0 T[14:0] Bit Name Attribute 15 EN R/W 14-0 T[14:0] RO R8822 Datasheet Final Version 1.7 May 19, 2005 Description Enable RCU. Set 1: Enable the refresh counter unit This bit will be cleared to 0 after hardware reset. Refresh Count. Read-only bits. These bits present the value of the down counter which triggers refresh requests. 101 RDC® R8822 RISC DSP Communication 16-Bit RISC Micro-controller 20. DC Electrical Characteristics 20.1 Symbol VTerm TA 20.2 Absolute Maximum Rating Rating Terminal Voltage with Respect to GND Ambient Temperature Commercial Unit -0.5~VCC+0.5 V 0~+70 °C Note Recommended DC Operating Conditions Symbol Parameter Vcc Supply Voltage GND Ground Min. Typ. Max. Unit 4.75 5 5.25 V 0 0 0 V Vih Input High Voltage (Note 1) 2.0 --- Vcc+0.5 V Vih1 Input High Voltage (RST_n) 3 --- Vcc+0.5 V Vih2 Input High Voltage (X1) 3 --- Vcc+0.5 V -0.5 0 0.8 V Vil Input Low voltage Note 1: The RST_n and X1 pins are not included. 20.3 DC Electrical Characteristics Symbol Parameter Test Condition Vcc=Vmax Ili Input Leakage Current Vin=GND to Vmax Input Leakage Current Vcc=Vmax Ili (with 10K pull R) with Pull_R 10K enable Vin=GND to Vmax Input Leakage Current Vcc=Vmax Ili (with 50K pull R) with Pull_R 50K Vin=GND to Vmax Vcc=Vmax Ilo Output Leakage Current Vin=GND to Vmax Iol=6mA, VOL Output Low Voltage Vcc=Vmin. Ioh=-6mA, VOH Output High Voltage Vcc=Vmin. Vcc=5.25V Icc Max Operating Current 40MHz Min. Max. Unit -10 10 uA -400 400 uA -120 120 uA -10 10 uA --- 0.4 V 2.4 --- V --- 180 mA Note 2: Vmax=5.25V Vmin=4.75V Symbol FMax 102 Parameter Max operation clock frequency of commercial Min. Max. Unit Note --- 40 MHz VCC ± 5% R8822 Datasheet Final Version 1.7 May 19, 2005 RDC® R8822 RISC DSP Communication 16-Bit RISC Micro-controller 21. AC Electrical Characteristics T1 T2 T3 CLKOUTA T4 TW 2 A[19:0] ADDRESS 1 4 3 S6 6 5 AD[15:0] 8 ADDRESS DATA 10 9 ALE 11 7 12 13 15 14 RD_n BHE_n 16 17 UCS_n, LCS_n 18 19 PCSx_n, MCSx_n 20 21 DEN_n 22 23 DT/R_n 24 25 S2_n~S0_n STATUS 26 27 UZI_n READ CYCLE R8822 Datasheet Final Version 1.7 May 19, 2005 103 RDC® No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 R8822 RISC DSP Communication Description CLKOUTA high to A Address valid A address valid to RD_n low S6 active delay S6 inactive delay AD address valid delay Address hold Data in setup Data in hold ALE active delay ALE inactive delay Address valid after ALE inactive ALE width RD_n active delay RD_n pulse width RD_n inactive delay CLKOUTA high to LCS_n/UCS_n valid UCS_n/LCS_n inactive delay PCS_n/MCS_n active delay PCS_n/MCS_n inactive delay DEN_n active delay DEN_n inactive delay DT/R_n active delay DT/R_n inactive delay Status active delay Status inactive delay UZI_n active delay UZI_n inactive delay 16-Bit RISC Micro-controller Min. 0 1.5T-9 0 0 0 0 5 2 0 0 T/2-5 T-5 0 2T-10 0 0 0 0 0 0 0 0 0 0 0 0 0 Max. 12 15 15 12 12 12 12 12 12 15 15 15 15 15 15 15 15 15 15 15 15 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1. T means a clock period time 2. All timing parameters are measured at 1.5V with 50 pF loading on CLKOUTA . 104 All output test conditions are with CL=50 pF R8822 Datasheet Final Version 1.7 May 19, 2005 RDC® R8822 RISC DSP Communication 16-Bit RISC Micro-controller T1 T2 T3 CLKOUTA T4 TW 2 A[19:0] ADDRESS 1 4 3 S6 5 6 AD[15:0] ADDRESS 7 DATA 9 8 ALE 10 11 13 12 WR_n 14 15 WHB_n, WLB_n 16 17 BHE_n 18 19 UCS_n, LCS_n 20 21 PCSx_n, MCSx_n 22 23 DEN_n 24 25 DT/R_n 26 27 S2_n~S0_n STATUS 28 29 UZI_n WRITE CYCLE R8822 Datasheet Final Version 1.7 May 19, 2005 105 RDC® No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 106 R8822 RISC DSP Communication Description CLKOUTA high to A Address valid A address valid to WR_n low S6 active delay S6 inactive delay AD address valid delay Address hold ALE active delay ALE width ALE inactive delay Address valid after ALE inactive WR_n active delay WR_n pulse width WR_n inactive delay WHB_n/WLB_n active delay WHB_n/WLB_n inactive delay BHE_n active delay BHE_n inactive delay CLKOUTA high to UCS_n/LCS_n valid UCS_n/LCS_n inactive delay PCS_n/MCS_n active delay PCS_n/MCS_n inactive delay DEN_n active delay DEN_n inactive delay DT/R_n active delay DT/R_n inactive delay Status active delay Status inactive delay UZI_n active delay UZI_n inactive delay 16-Bit RISC Micro-controller Min. 0 1.5T-9 0 0 0 Max. 12 0 T-10 0 1/2T-5 0 2T-10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12 15 15 12 12 12 12 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns R8822 Datasheet Final Version 1.7 May 19, 2005 RDC® R8822 RISC DSP Communication 16-Bit RISC Micro-controller T1 T2 T3 T4 T1 T2 T3 T4 T1 CLKOUTA A[19:0] c0000 d00C0 AD[15:0] 0 0 20000 0 2211 2211 101fc * 1fc * ALE RD_n WR_n WLB_n WHB_n UCS_n DEN_n DT/R_n S2_n~S0_n 7 5 7 6 7 6 S6 1 DRQ0 DMA (1) * The source-synchronized transfer is not followed immediately by another DMA transfer. No. Description 1 DRQ is confirmed time R8822 Datasheet Final Version 1.7 May 19, 2005 Min. 5 Max. 1T-5 Unit ns 107 RDC® R8822 RISC DSP Communication T1 T2 T3 16-Bit RISC Micro-controller T4 T1 T2 T3 T4 T1 T2 T3 T4 T1 T2 T3 T4 T1 CLKOUTA A[19:0] AD[15:0] c0000 0 20000 0 2211 * 2211 C0002 2 20002 4433 2 * 4433 101fc 1fc ALE RD_n WR_n WLB_n WHB_n UCS_n DEN_n DT/R_n S2_n~S0_n 5 7 6 7 5 7 6 7 6 S6 1 DRQ0 DMA (2) * The source-synchronized transfer is followed immediately by another DMA transfer. No. 1 108 Description DRQ is confirmed time Min. 2 Max. 0 Unit ns R8822 Datasheet Final Version 1.7 May 19, 2005 RDC® R8822 RISC DSP Communication T1 T2 16-Bit RISC Micro-controller T3 Tw Tw Tw T4 Ti Ti Ti Ti Ti Ti Ti Ti Ti Ti Ti Ti T1 CLKOUTA A[19:0] ffff4 AD[15:0] fff6 f0 f0000 fff* zZZZZ ffff6 0 fff6 0 b8 ALE RD_n WR_n WLB_n UCS_n DEN_n DT/R_n S2_n~S0_n 4 7 4 z 7 1 7 4 3 HOLD 2 4 HLDA HOLD/HLDA Timing No. 1 2 3 4 Description HOLD setup time HLDA rising valid delay HOLD hold time HLDA falling valid delay R8822 Datasheet Final Version 1.7 May 19, 2005 Min. 5 0 2 0 Max. 0 15 0 15 Unit ns ns ns ns 109 RDC® R8822 RISC DSP Communication T1 16-Bit RISC Micro-controller T2 T3 Tw Tw Tw Tw Tw Tw T4 T1 CLKOUTA ALE 2 1 ARDY SRDY LCS_n ARDY Timing No. 1 2 Description ARDY resolution transition setup time ARDY active hold time T1 T2 Min. 5 5 T3 Tw Tw Max. 0 0 Tw Unit ns ns Tw Tw T4 T1 CLKOUTA ALE ARDY 2 1 SRDY LCS_n SRDY Timing No. 1 2 110 Description SRDY transition setup time SRDY transition hold time Min. 5 5 Max. 0 0 Unit ns ns R8822 Datasheet Final Version 1.7 May 19, 2005 RDC® R8822 RISC DSP Communication t3 16-Bit RISC Micro-controller t1 t4 t2 t4 t3 t1 CLKOUTA 2 1 Addr. AD[15:0] Data 3 4 5 Row MA[8:0] Column 6 7 RAS_n 8 9 CAS_n 10 11 RD_n DRAM Read Cycle with No Wait States No. 1 2 3 4 5 6 7 8 9 10 11 R8822 Datasheet Final Version 1.7 May 19, 2005 Description CLKOUTA low to A Address valid Data setup time Data hold time CLKOUTA high to Row address valid CLKOUTA low to Column address valid CLKOUTA low to RAS_n active CLKOUTA high to RAS_n inactive CLKOUTA high to CAS_n active CLKOUTA low to CAS_n inactive CLKOUTA low to RD_n active CLKOUTA low to RD_n inactive Min. 0 5 2 0 0 3 3 3 3 0 0 Max. 12 12 12 12 12 12 12 12 12 Unit ns ns ns ns ns ns ns ns ns ns ns 111 RDC® R8822 RISC DSP Communication 16-Bit RISC Micro-controller t1 t4 t2 tw t3 t4 t1 CLKOUTA 1 AD[15:0] 2 Addr. Data 3 4 5 MA[8:0] Column Row 6 7 RAS_n 8 9 CAS_n 10 11 RD_n DRAM Read Cycle with Wait-States No. 1 2 3 4 5 6 7 8 9 10 11 112 Description CLKOUTA low to A Address valid Data setup time Data hold time CLKOUTA high to Row address valid CLKOUTA low to Column address valid CLKOUTA low to RAS_n active CLKOUTA high to RAS_n inactive CLKOUTA high to CAS_n active CLKOUTA low to CAS_n inactive CLKOUTA low to RD_n active CLKOUTA low to RD_n inactive Min. 0 5 2 0 0 3 3 3 3 0 0 Max. 12 12 12 12 12 12 12 12 Unit ns ns ns ns ns ns ns ns ns ns ns R8822 Datasheet Final Version 1.7 May 19, 2005 RDC® R8822 RISC DSP Communication 16-Bit RISC Micro-controller t4 t1 t2 t3 t4 CLKOUTA 1 2 Addr. AD[15:0] 3 Data 4 Row MA[8:0] Column 5 6 RAS_n 7 8 CAS_n 9 10 WR_n DRAM Write Cycle with No Wait-States No. 1 2 3 4 5 6 7 8 9 10 Description CLKOUTA low to A Address valid CLKOUTA low to A Data valid CLKOUTA high to Row address valid CLKOUTA low to Column address valid CLKOUTA low to RAS_n active CLKOUTA high to RAS_n inactive CLKOUTA high to CAS_n active CLKOUTA low to CAS_n inactive CLKOUTA low to WR_n active CLKOUTA low to WR_n inactive R8822 Datasheet Final Version 1.7 May 19, 2005 Min. 0 0 0 0 3 3 3 3 0 0 Max. 12 12 12 12 12 12 12 12 12 12 Unit ns ns ns ns ns ns ns ns ns ns 113 RDC® R8822 RISC DSP Communication 16-Bit RISC Micro-controller t4 t1 t2 t3 tw t4 t1 CLKOUTA 1 2 Addr. AD[15:0] Data 4 3 MA[8:0] Row Column 5 6 RAS_n CAS_n 8 7 9 10 WR_n DRAM Write Cycle with Wait-States No. 1 2 3 4 5 6 7 8 9 10 114 Description CLKOUTA low to A Address valid CLKOUTA low to A Data valid CLKOUTA high to Row address valid CLKOUTA low to Column address valid CLKOUTA low to RAS_n active CLKOUTA high to RAS_n inactive CLKOUTA high to CAS_n active CLKOUTA low to CAS_n inactive CLKOUTA low to WR_n active CLKOUTA low to WR_n inactive Min. 0 0 0 0 3 3 3 3 0 0 Max. 12 12 12 12 12 12 12 12 12 12 Unit ns ns ns ns ns ns ns ns ns ns R8822 Datasheet Final Version 1.7 May 19, 2005 RDC® R8822 RISC DSP Communication 16-Bit RISC Micro-controller t1 t4 tw t2 tw tw t3 t4 t1 CLKOUTA 1 AD[15:0] FFFF 2 3 MA[8:0] 5 4 RAS_n 7 6 CAS_n 8 9 RD_n DRAM Refresh Cycle No. 1 2 3 4 5 6 7 8 9 Description CLKOUTA high to Data drive FFFF CLKOUTA high to Row address valid CLKOUTA low to Column address valid CLKOUTA high to RAS_n active CLKOUTA low to RAS_n inactive CLKOUTA high to CAS_n active CLKOUTA low to CAS_n inactive CLKOUTA low to RD_n active CLKOUTA low to RD_n inactive R8822 Datasheet Final Version 1.7 May 19, 2005 Min. 0 0 0 3 3 3 3 0 0 Max. 12 12 12 12 12 12 12 12 12 Unit ns ns ns ns ns ns ns ns ns 115 RDC® R8822 RISC DSP Communication 16-Bit RISC Micro-controller 22. Thermal Characteristics θJA: thermal resistance from device junction to ambient temperature P: operation power TA: maximum ambient temperature in operation mode TA=TJ–( P×θJA ) Package/Board PQFP/2-Layer LQFP/2-Layer PQFP/4-Layer LQFP/4-Layer Air Flow (m/s) 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 θJA 48.8 44.9 42.7 41.9 53.6 48.9 45.5 44.5 38.9 35.7 33.8 33.3 42.6 38.0 36.1 35.3 Unit: °C/Watt Recommended Storage Temperature: –65°C to +125°C Note: The IC should be mounted on PCB within 7 days after the dry pack is opened. If the IC is out of dry pack more than 7 days, it should be burned in oven (+125°C, > 12 hours) before mounted on PCB. 116 R8822 Datasheet Final Version 1.7 May 19, 2005 RDC® R8822 RISC DSP Communication 16-Bit RISC Micro-controller 20.23. Instruction Set OP-Code and Clock Cycles Function DATA TRANSFER INSTRUCTIONS MOV = Move register to register/memory register/memory to register immediate to register/memory immediate to register memory to accumulator accumulator to memory register/memory to segment register segment register to register/memory PUSH = Push memory register segment register immediate POP = Pop memory register segment register Format 1000100w 1000101w 1100011w mod reg r/m mod reg r/m mod 000 r/m 1011w reg data 1010000w 1010001w 10001110 10001100 addr-low addr-low mod 0 reg r/m mod 0 reg r/m 11111111 01010 reg 000reg110 011010s0 mod 110 r/m data data data if w=1 addr-high addr-high data if w=1 8 3 2 1 data if s=0 36 44 1000011w mod reg r/m 10010 reg 11010111 3/8 3 10 1110010w port 1110110w 12 12 1110010w port 1110110w 12 12 1 14 14 11001001 10011111 10011110 10011100 10011101 ARITHMETIC INSTRUCTIONS ADD = Add reg/memory with register to either 000000dw 10001101 11000101 11000100 11001000 mod reg r/m mod reg r/m mod reg r/m data-low Notes 1/1 1/6 1/1 1 6 1 3/8 2/2 10001111 mod 000 r/m 01011 reg 000 reg (reg≠01) 111 01100000 01100001 PUSHA = Push all POPA = Pop all XCHG = Exchange register/memory register with accumulator XTAL = Translate byte to AL IN = Input from fixed port variable port OUT = Output from fixed port variable port LEA = Load EA to register LDS = Load pointer to DS LES = Load pointer to ES ENTER = Build stack frame L=0 L=1 L>1 LEAVE = Tear down stack frame LAHF = Load AH with flags SAHF = Store AH into flags PUSHF = Push flags POPF = Pop flags 8 6 8 (mod≠11) (mod≠11) data-high L 7 11 11+10(L-1) 7 2 2 2 11 mod reg r/m 1/7 immediate to register/memory 100000sw mod 000 r/m data immediate to accumulator 0000010w data data if w=1 R8822 Datasheet Final Version 1.7 May 19, 2005 Clocks data if sw=01 1/8 1 117 RDC® R8822 RISC DSP Communication 16-Bit RISC Micro-controller Function ADC = Add with carry reg/memory with register to either immediate to register/memory immediate to accumulator INC = Increment register/memory register SUB = Subtract reg/memory with register to either Format 000100dw Clocks mod reg r/m 1/7 100000sw mod 010 r/m data 0001010w data data if w=1 1111111w 01000 reg mod 000 r/m 001010dw mod reg r/m data if sw=01 1/8 1 1/8 1 1/7 data if sw=01 immediate from register/memory 100000sw mod 101 r/m data immediate from accumulator SBB = Subtract with borrow reg/memory with register to either immediate from register/memory immediate from accumulator DEC = Decrement register/memory register NEG = Change sign register/memory CMP = Compare register/memory with register register with register/memory 0001110w data data if w=1 1 000110dw 100000sw 0001110w mod reg r/m mod 011 r/m data data if w=1 1/7 1/8 1 1111111w 01001 reg mod 001 r/m 1/8 1 1111011w mod reg r/m 1/8 0011101w 0011100w mod reg r/m mod reg r/m 1/7 1/7 immediate with register/memory 100000sw mod 111 r/m data immediate with accumulator 0011110w data data if w=1 MUL = multiply (unsigned) 1111011w register-byte register-word memory-byte memory-word IMUL = Integer multiply (signed) 1111011w register-byte register-word memory-byte memory-word register/memory multiply immediate (signed) 011010s1 DIV = Divide (unsigned) register-byte register-word memory-byte memory-word IDIV = Integer divide (signed) register-byte register-word memory-byte memory-word 1111011W AAS = ASCII adjust for subtraction DAS = Decimal adjust for subtraction AAA = ASCII adjust for addition DAA = Decimal adjust for addition AAD = ASCII adjust for divide AAM = ASCII adjust for multiply CBW = Corrvert byte to word CWD = Convert word to double-word 00111111 00101111 00110111 00100111 11010101 11010100 10011000 10011001 118 Notes data if sw=01 1/8 1/7 1 mod 100 r/m 13 21 18 26 mod 101 r/m mod reg r/m data data if s=0 16 24 21 29 23/28 mod 110 r/m 18 26 23 31 1111011w mod 111 r/m 18 26 23 31 00001010 00001010 3 2 3 2 14 15 2 2 R8822 Datasheet Final Version 1.7 May 19, 2005 RDC® R8822 RISC DSP Communication 16-Bit RISC Micro-controller Function BIT MANIPULATION INSTRUCTUIONS NOT = Invert register/memory AND = And reg/memory and register to either immediate to register/memory immediate to accumulator OR = Or reg/memory and register to either immediate to register/memory immediate to accumulator XOR = Exclusive or reg/memory and register to either immediate to register/memory immediate to accumulator TEST = And function to flags , no result register/memory and register immediate data and register/memory immediate data and accumulator Sifts/Rotates register/memory by 1 register/memory by CL register/memory by Count STRING MANIPULATION INSTRUCTIONS MOVS = Move byte/word INS = Input byte/word from DX port OUTS = Output byte/word to DX port CMPS = Compare byte/word SCAS = Scan byte/word LODS = Load byte/word to AL/AX STOS = Store byte/word from AL/AX Format Clocks 1111011w mod 010 r/m 001000dw 1000000w 0010010w mod reg r/m mod 100 r/m data data data if w=1 data if w=1 1/7 1/8 1 000010dw 1000000w 0000110w mod reg r/m mod 001 r/m data data data if w=1 data if w=1 1/7 1/8 1 001100dw 1000000w 0011010w mod reg r/m mod 110 r/m data data data if w=1 data if w=1 1/7 1/8 1 1000010w 1111011w 1010100w mod reg r/m mod 000 r/m data data data if w=1 data if w=1 1/7 1/8 1 1101000w 1101001w 1100000w mod TTT r/m mod TTT r/m mod TTT r/m 1010010w 0110110w 0110111w 1010011w 101011w 1010110w 1010101w Notes 1/7 count 2/8 1+n / 7+n 1+n / 7+n 13 13 13 18 13 13 7 Repeated by count in CX: MOVS = Move byte/word INS = Input byte/word from DX port OUTS = Output byte/word to DX port CMPS = Compare byte/word SCAS = Scan byte/word LODS = Load byte/word to AL/AX STOS = Store byte/word from AL/AX PROGRAM TRANSFER INSTRUCTIONS Conditional Transfers — jump if: JE/JZ = equal/zero JL/JNGE = less/not greater or equal JLE/JNG = less or equal/not greater JC/JB/JNAE = carry/below/not above or equal JBE/JNA = below or equal/not above JP/JPE = parity/parity even JO = overflow JS = sign JNE/JNZ = not equal/not zero JNL/JGE = not less/greater or equal JNLE/JG = not less or equal/greater JNC/JNB/JAE = not carry/not below /above or equal JNBE/JA = not below or equal/above JNP/JPO = not parity/parity odd JNO = not overflow R8822 Datasheet Final Version 1.7 May 19, 2005 11110010 11110010 11110010 1111011z 1111001z 11110010 11110100 1010010w 0110110w 0110111w 1010011w 1010111w 0101001w 0101001w 4+9n 5+9n 5+9n 4+18n 4+13n 3+9n 4+3n 01110100 01111100 01111110 disp disp disp 1/9 1/9 1/9 01110010 disp 1/9 01110110 01111010 01110000 01111000 01110101 01111101 01111111 01110011 disp disp disp disp disp disp disp disp 1/9 1/9 1/9 1/9 1/9 1/9 1/9 1/9 01110111 01111011 01110001 disp disp disp 1/9 1/9 1/9 119 RDC® R8822 RISC DSP Communication JNS = not sign 16-Bit RISC Micro-controller 01111001 disp Function 1/9 Format Clocks Notes Unconditional Transfers CALL = Call procedure direct within segment reg/memory indirect within segment indirect intersegment direct intersegment RET = Retum from procedure within segment within segment adding immed to SP intersegment instersegment adding immed to SP JMP = Unconditional jump short/long direct within segment reg/memory indirect within segment indirect intersegment direct intersegment 11101000 11111111 11111111 10011010 11000011 11000010 11001011 1001010 disp-low disp-high mod 010 r/m (mod≠11) mod 011 r/m segment offset selector data-low data-high data-low data-high 11 12/17 25 18 16 16 23 23 11101011 11101001 11111111 11111111 11101010 disp-low disp-low disp-high mod 100 r/m mod 101 r/m (mod ?11) segment offset selector 9/9 9 11/16 18 11 11100010 11100001 disp disp 7/16 7/16 Iteration Control LOOP = Loop CX times LOOPZ/LOOPE = Loop while zero/equal LOOPNZ/LOOPNE = Loop while not zero/equal JCXZ = Jump if CX = zero 11100000 disp 7/16 11100011 disp 7/15 Interrupt INT = Interrupt Type specified Type 3 INTO = Interrupt on overflow BOUND = Detect value out of range IRET = Interrupt return 11001101 11001100 11001110 01100010 11001111 type 41 41 43/4 21-60 31 PROCESSOR CONTROL INSTRUCTIONS CLC = clear carry CMC = Complement carry STC = Set carry CLD = Clear direction STD = Set direction CLI = Clear interrupt STI = Set interrupt HLT = Halt WAIT = Wait LOCK = Bus lock prefix ESC = Math coprocessor escape NOP = No operation 11111000 11110101 11111001 11111100 11111101 11111010 11111011 11110100 10011011 11110000 11011MMM mod PPP r/m 10010000 2 2 2 2 2 5 5 1 1 1 1 1 SEGMENT OVERRIDE PREFIX CS SS DS ES 00101110 00110110 00111110 00100110 2 2 2 2 120 mod reg r/m R8822 Datasheet Final Version 1.7 May 19, 2005 RDC® R8822 RISC DSP Communication 16-Bit RISC Micro-controller 21.24. R8822 Execution Timing The above instruction timings represent the minimum execution time in clock cycles for each instruction. The timings given are based on the following assumptions: 1. The opcode, along with data or displacement required for execution, has been prefetched and resided in the instruction queue at the time needed. 2. No wait states or bus holds occur. 3. All word -data are located on even-address boundaries. 4. One RISC micro operation (uOP) maps one cycle (according to the pipeline stages described below), except the following case: Pipeline stages for single micro operations (one cycle): Fetch Æ Decode Æ op_r Æ ALU Æ WB (For ALU function uOP) Fetch Æ Decode Æ EA Æ Access Æ WB (For memory function uOP) 4.1 Memory read uOP needs 6 cycles for bus. Pipeline stages for memory read uOP (6 cycles): Fetch Æ Decode ÆEA Æ Access Æ Idle Æ T0 Æ T1 Æ T2 Æ T3 Æ WB Bus Cycle 4.2 Memory push uOP needs 1 cycle if it has no previous memory push uOP, and 5 cycles if it has previous memory push or memory write uOP. Pipeline stages for memory push uOP after memory push uOP (another 5 cycles): Fetch Æ Decode Æ EA Æ Access Æ Idle Æ (2nd uOP) Fetch Æ Decode ÆEA Æ Access Æ T0 Æ T1 Æ T2 Æ T3 Æ WB Access Æ Access Æ Access Æ Access (1st memory push uOP) ÆIdle Æ T0 Æ T1 Æ T2 Æ T3 Æ WB pipeline stall 4.3 MUL uOP and DIV of ALU function uOP for 8-bit operations need both 8 cycles, for 16-bit operations need both 16 cycles. 4.4 All jumps, calls, ret and loopXX instructions required to fetch the next instruction for the destination address (unconditional fetch uOP) will need 9 cycles. Pipeline stages for unconditional fetch: Fetch Æ Decode Æ EA Æ Access Æ Idle Æ T0 Æ T1 Æ T2 Æ T3 ÆFetch (Fetch uOP) (next uOP) FetchÆ Decode Æ EA Æ Access Æ Access Æ Access Æ Access Æ Access ÆIdle Æ T0Æ T1Æ T2ÆT3ÆWB will be flushed These 9 cycles cause branch penalty ÆFetchÆ Decode Æfollowing stages...(New uOP) Note: op_r: operand read stage; EA: Calculate Effective Address stage; Idle: Bus Idle stage; T0..T3: Bus T0..T3 stage; Access: Access data from cache memory stage. R8822 Datasheet Final Version 1.7 May 19, 2005 121 RDC® R8822 RISC DSP Communication 16-Bit RISC Micro-controller 25. Package Information 25.1 PQFP D 23.20 0.20 D1 20.00 0.10 0.20 E 17.20 0.10 E1 14.00 "A" "A" 0.65 BSC 0.10 0.25 MIN A1 SEATING PLANE c 0.25~0.38 7 TYP 15 TYP 1.60 REF L1 A2 2.85 0.12 DETAIL A 3.40 Max. L 0.88 0.15 0.25 DETAIL A UNIT:mm 122 R8822 Datasheet Final Version 1.7 May 19, 2005 RDC® 16-Bit RISC Micro-controller LQFP 16.00 0.15 14.00 0.10 75 25 51 50 0.127(TYP) 26 0.15 1 16.00 76 0.10 100 14.00 25.2 R8822 RISC DSP Communication 0.50(TYP) 0.22 0.05 "A" 0 ~ 7 0.10 0.60 0.2S(TYP) GAUGE PLANE 1.40 0.05 0.08(MAX) 0.05 1.60(MAX) Sealing Plane 0.15 1.00(REF) UNIT:mm R8822 Datasheet Final Version 1.7 May 19, 2005 123 RDC® R8822 RISC DSP Communication 16-Bit RISC Micro-controller 26. Revision History Rev. P10 F11 F12 F13 F14 F15 F16 F17 Date 2000/7/31 2001/5/17 2001/8/10 2001/11/29 2001/12/25 2002/05/08 2004/01/05 2005/05/19 History Preliminary Version Final Version 1.1: Formal release Modify Wait State Description (Page 30) DC Characteristics Modify Oscillator Characteristics Modify Wait State Description Modify DC Characteristics and add Thermal Characteristics. Final Version 1.7 Page 120 & 121: Package Information modified. RDC reserves the right to make changes without further notice to any products or data herein to improve reliability, function, or design. Information furnished by RDC is believed to be accurate and reliable. However, RDC does not assure any liability arising out of the application or use of this information, nor the application or use of any product or circuit described herein, neither does it convey any license under its patent rights nor the rights of others. 124 R8822 Datasheet Final Version 1.7 May 19, 2005