ETC RGE7500PL

Intel® E7500 Chipset
Datasheet
Intel® E7500 Memory Controller Hub (MCH)
February 2002
Document Number: 290730-001
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The Intel® E7500 chipset MCH component may contain design defects or errors known as errata which may cause the product to deviate from
published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
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Copyright© 2002, Intel Corporation
2
Datasheet
Contents
1
Introduction ................................................................................................................11
1.1
1.2
1.3
1.4
2
Signal Description ...................................................................................................17
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3
System Bus Interface Signals .............................................................................19
DDR Channel A Signals ......................................................................................22
DDR Channel B Signals ......................................................................................23
Hub Interface_A Signals......................................................................................24
Hub Interface_B Signals......................................................................................25
Hub Interface_C Signals .....................................................................................26
Hub Interface_D Signals .....................................................................................27
Clocks, Reset, Power, and Miscellaneous Signals .............................................28
Pin States During and After Reset ......................................................................28
Register Description ...............................................................................................31
3.1
3.2
3.3
3.4
3.5
3.6
Datasheet
Glossary of Terms ...............................................................................................11
Reference Documents.........................................................................................12
Intel® E7500 Chipset System Architecture..........................................................12
1.3.1 Intel® 82801CA I/O Controller Hub 3-S (ICH3-S)...................................13
1.3.2 Intel® 82870P2 PCI/PCI-X 64-bit Hub 2 (P64H2)...................................14
Intel® E7500 MCH Overview...............................................................................14
1.4.1 Processor System Interface ...................................................................15
1.4.2 Main Memory Interface...........................................................................15
1.4.3 Hub Interface_A (HI_A) ..........................................................................15
1.4.4 Hub Interface_B–D (HI_B–D).................................................................16
1.4.5 MCH Clocking ........................................................................................16
1.4.6 SMBus Interface.....................................................................................16
Register Terminology ..........................................................................................31
Platform Configuration.........................................................................................32
General Routing Configuration Accesses ...........................................................33
3.3.1 Standard PCI Configuration Mechanism ................................................33
3.3.2 Logical PCI Bus 0 Configuration Mechanism .........................................34
3.3.3 Primary PCI Downstream Configuration Mechanism .............................34
3.3.4 HI_B, HI_C, HI_D Bus Configuration Mechanism ..................................34
Sticky Registers...................................................................................................35
I/O Mapped Registers .........................................................................................35
3.5.1 CONF_ADDR—Configuration Address Register ...................................35
3.5.2 CONF_DATA—Configuration Data Register..........................................36
DRAM Controller Registers (Device 0, Function 0).............................................37
3.6.1 VID—Vendor Identification Register (D0:F0) .........................................38
3.6.2 DID—Device Identification Register (D0:F0) ..........................................38
3.6.3 PCICMD—PCI Command Register (D0:F0) ..........................................39
3.6.4 PCISTS—PCI Status Register (D0:F0) ..................................................40
3.6.5 RID—Revision Identification Register (D0:F0) .......................................41
3.6.6 SUBC—Sub-Class Code Register (D0:F0) ............................................41
3.6.7 BCC—Base Class Code Register (D0:F0).............................................41
3.6.8 MLT—Master Latency Timer Register (D0:F0) ......................................42
3
3.6.9
3.6.10
3.6.11
3.6.12
3.6.13
3.7
4
HDR—Header Type Register (D0:F0).................................................... 42
SVID—Subsystem Vendor Identification Register (D0:F0) .................... 42
SID—Subsystem Identification Register (D0:F0) ................................... 43
MCHCFG—MCH Configuration Register (D0:F0).................................. 43
MCHCFGNS—MCH Memory Scrub and Initialization Configuration
Register (D0:F0)..................................................................................... 45
3.6.14 FDHC—Fixed DRAM Hole Control Register (D0:F0)............................. 46
3.6.15 PAM[0:6]—Programmable Attribute Map Registers (D0:F0).................. 47
3.6.16 DRB—DRAM Row Boundary Register (D0:F0) ..................................... 49
3.6.17 DRA—DRAM Row Attribute Register (D0:F0) ....................................... 50
3.6.18 DRT—DRAM Timing Register (D0:F0) .................................................. 51
3.6.19 DRC—DRAM Controller Mode Register (D0:F0) ................................... 52
3.6.20 CLOCK_DIS—CK/CK# Disable Register (D0:F0).................................. 53
3.6.21 SMRAM—System Management RAM Control Register (D0:F0) ........... 54
3.6.22 ESMRAMC—Extended System Management RAM Control Register
(D0:F0) ................................................................................................... 55
3.6.23 TOLM—Top of Low Memory Register (D0:F0) ...................................... 56
3.6.24 REMAPBASE—Remap Base Address Register (D0:F0)....................... 56
3.6.25 REMAPLIMIT—Remap Limit Address Register (D0:F0)........................ 57
3.6.26 SKPD—Scratchpad Data Register (D0:F0)............................................ 57
3.6.27 DVNP—Device Not Present Register (D0:F0) ....................................... 58
DRAM Controller Error Reporting Registers (Device 0, Function 1) ................... 59
3.7.1 VID—Vendor Identification Register (D0:F1) ......................................... 60
3.7.2 DID—Device Identification Register (D0:F1).......................................... 60
3.7.3 PCICMD—PCI Command Register (D0:F1) .......................................... 61
3.7.4 PCISTS—PCI Status Register (D0:F1) .................................................. 61
3.7.5 RID—Revision Identification Register (D0:F1) ....................................... 62
3.7.6 SUBC—Sub-Class Code Register (D0:F1) ............................................ 62
3.7.7 BCC—Base Class Code Register (D0:F1)............................................. 63
3.7.8 MLT—Master Latency Timer Register (D0:F1) ...................................... 63
3.7.9 HDR—Header Type (D0:F1) .................................................................. 64
3.7.10 SVID—Subsystem Vendor Identification Register (D0:F1) .................... 65
3.7.11 SID—Subsystem Identification Register (D0:F1) ................................... 65
3.7.12 FERR_GLOBAL—Global Error Register (D0:F1)................................... 66
3.7.13 NERR_GLOBAL—Global Error Register (D0:F1) .................................. 67
3.7.14 HIA_FERR—Hub Interface_A First Error Register (D0:F1) ................... 68
3.7.15 HIA_NERR—Hub Interface_A Next Error Register (D0:F1)................... 69
3.7.16 SCICMD_HIA—SCI Command Register (D0:F1) .................................. 70
3.7.17 SMICMD_HIA—SMI Command Register (D0:F1).................................. 71
3.7.18 SERRCMD_HIA—SERR Command Register (D0:F1) .......................... 72
3.7.19 SYSBUS_FERR—System Bus First Error Register (D0:F1).................. 73
3.7.20 SYSBUS_NERR—System Bus Next Error Register (D0:F1)................. 74
3.7.21 SCICMD_SYSBUS—SCI Command Register (D0:F1).......................... 75
3.7.22 SMICMD_SYSBUS—SMI Command Register (D0:F1) ......................... 76
3.7.23 SERRCMD_SYSBUS—SERR Command Register (D0:F1).................. 77
3.7.24 DRAM_FERR—DRAM First Error Register (D0:F1) .............................. 78
3.7.25 DRAM_NERR—DRAM Next Error Register (D0:F1) ............................. 78
3.7.26 SCICMD_DRAM—SCI Command Register (D0:F1).............................. 79
3.7.27 SMICMD_DRAM—SMI Command Register (D0:F1) ............................. 79
3.7.28 SERRCMD_DRAM—SERR Command Register (D0:F1)...................... 80
Datasheet
3.8
3.9
3.10
3.11
Datasheet
3.7.29 DRAM_CELOG_ADD—DRAM First Correctable Memory Error
Address Register (D0:F1).......................................................................80
3.7.30 DRAM_UELOG_ADD—DRAM First Uncorrectable Memory Error
Address Register (D0:F1).......................................................................81
3.7.31 DRAM_CELOG_SYNDROME—DRAM First Correctable Memory
Error Register (D0:F1) ............................................................................81
HI_B Virtual PCI-to-PCI Bridge Registers (Device 2, Function 0) .......................82
3.8.1 VID2—Vendor Identification Register (D2:F0) .......................................83
3.8.2 DID2—Device Identification Register (D2:F0) ........................................83
3.8.3 PCICMD2—PCI Command Register (D2:F0) ........................................84
3.8.4 PCISTS2—PCI Status Register (D2:F0) ................................................85
3.8.5 RID2—Revision Identification Register (D2:F0) .....................................86
3.8.6 SUBC2—Sub-Class Code Register (D2:F0) ..........................................86
3.8.7 BCC2—Base Class Code Register (D2:F0) ...........................................87
3.8.8 MLT2—Master Latency Timer Register (D2:F0) ....................................87
3.8.9 HDR2—Header Type Register (D2:F0)..................................................88
3.8.10 PBUSN2—Primary Bus Number Register (D2:F0) ................................88
3.8.11 BUSN2—Secondary Bus Number Register (D2:F0) ..............................89
3.8.12 SUBUSN2—Subordinate Bus Number Register (D2:F0) .......................89
3.8.13 SMLT2—Secondary Bus Master Latency Timer Register (D2:F0) ........90
3.8.14 IOBASE2—I/O Base Address Register (D2:F0).....................................91
3.8.15 IOLIMIT2—I/O Limit Address Register (D2:F0)......................................91
3.8.16 SEC_STS2—Secondary Status Register (D2:F0) .................................92
3.8.17 MBASE2—Memory Base Address Register (D2:F0) .............................93
3.8.18 MLIMIT2—Memory Limit Address Register (D2:F0) ..............................94
3.8.19 PMBASE2—Prefetchable Memory Base Address Register (D2:F0)......95
3.8.20 PMLIMIT2—Prefetchable Memory Limit Address Register (D2:F0).......95
3.8.21 BCTRL2—Bridge Control Register (D2:F0) ...........................................96
HI_B Virtual PCI-to-PCI Bridge Registers (Device 2, Function 1) .......................97
3.9.1 VID—Vendor Identification Register (D2:F1) .........................................98
3.9.2 DID—Device Identification Register (D2:F1) ..........................................98
3.9.3 PCICMD—PCI Command Register (D2:F1) ..........................................99
3.9.4 PCISTS—PCI Status Register (D2:F1) ..................................................99
3.9.5 RID—Revision Identification Register (D2:F1) .....................................100
3.9.6 SUBC—Sub-Class Code Register (D2:F1) ..........................................100
3.9.7 BCC—Base Class Code Register (D2:F1)...........................................101
3.9.8 HDR—Header Type Register (D2:F1)..................................................101
3.9.9 SVID—Subsystem Vendor Identification Register (D2:F1) ..................102
3.9.10 SID—Subsystem Identification Register (D2:F1) .................................102
3.9.11 HIB_FERR—Hub Interface_B First Error Register (D2:F1) .................103
3.9.12 HIB_NERR—Hub Interface_B Next Error Register (D2:F1).................104
3.9.13 SERRCMD2—SERR Command Register (D2:F1) ..............................105
3.9.14 SMICMD2—SMI Command Register (D2:F1)......................................106
3.9.15 SCICMD2—SCI Command Register (D2:F1) ......................................107
HI_C Virtual PCI-to-PCI Bridge Registers (Device 3, Function 0,1)..................108
3.10.1 DID—Device Identification Register (D3:F0) ........................................108
3.10.2 DID—Device Identification Register (D3:F1) ........................................108
HI_D Virtual PCI-to-PCI Bridge Registers (Device 4, Function 0,1)..................109
3.11.1 DID—Device Identification Register (D4:F0) ........................................109
3.11.2 DID—Device Identification Register (D4:F1) ........................................109
5
4
System Address Map............................................................................................ 111
4.1
4.2
4.3
4.4
5
Reliability, Availability, Serviceability, Usability, and
Manageability (RASUM) ....................................................................................... 121
5.1
5.2
5.3
5.4
6
Absolute Maximum Ratings .............................................................................. 123
Thermal Characteristics .................................................................................... 123
Power Characteristics ....................................................................................... 124
I/O Interface Signal Groupings.......................................................................... 125
DC Characteristics ............................................................................................ 127
Ballout and Package Specifications............................................................... 131
7.1
7.2
7.3
6
DRAM ECC ....................................................................................................... 121
DRAM Scrubbing .............................................................................................. 121
DRAM Auto-Initialization ................................................................................... 121
SMBus Access .................................................................................................. 121
Electrical Characteristics.................................................................................... 123
6.1
6.2
6.3
6.4
6.5
7
System Memory Spaces ................................................................................... 111
4.1.1 VGA and MDA Memory Spaces........................................................... 113
4.1.2 PAM Memory Spaces .......................................................................... 114
4.1.3 ISA Hole Memory Space ...................................................................... 115
4.1.4 I/O APIC Memory Space ...................................................................... 115
4.1.5 System Bus Interrupt Memory Space................................................... 115
4.1.6 Device 2 Memory and Prefetchable Memory ....................................... 115
4.1.7 Device 3 Memory and Prefetchable Memory ....................................... 116
4.1.8 Device 4 Memory and Prefetchable Memory ....................................... 116
4.1.9 HI_A Subtractive Decode ..................................................................... 116
4.1.10 Main Memory Addresses...................................................................... 116
I/O Address Space ............................................................................................ 117
SMM Space....................................................................................................... 117
4.3.1 System Management Mode (SMM) Memory Range ............................ 117
4.3.2 TSEG SMM Memory Space................................................................. 118
4.3.3 High SMM Memory Space ................................................................... 118
4.3.4 SMM Space Restrictions ...................................................................... 118
4.3.5 SMM Space Definition.......................................................................... 119
Memory Reclaim Background ........................................................................... 120
4.4.1 Memory Re-Mapping............................................................................ 120
Ballout ............................................................................................................... 131
Package Specifications ..................................................................................... 141
Chipset Interface Trace Length Compensation................................................. 143
7.3.1 MCH System Bus Signal Package Trace Length Data ........................ 144
7.3.1.1 MCH DDR Channel A Signal Package Trace Length Data..... 145
7.3.1.2 MCH DDR Channel B Signal Package Trace Length Data..... 148
7.3.1.3 MCH Hub Interface_A Signal Package Trace Length
Data......................................................................................... 151
7.3.1.4 MCH Hub Interface_B Signal Package Trace Length
Data......................................................................................... 151
7.3.1.5 MCH Hub Interface_C Signal Package Trace Length
Data......................................................................................... 152
7.3.1.6 MCH Hub Interface_D Signal Package Trace Length
Data......................................................................................... 152
Datasheet
8
Testability ..................................................................................................................153
8.1
XOR Chains ......................................................................................................154
1-1
2-1
3-1
4-1
4-2
7-1
7-2
7-3
7-4
7-5
Intel® E7500 Chipset Platform Block Diagram ....................................................13
MCH Interface Signals ........................................................................................18
PAM Registers ....................................................................................................48
System Address Map ........................................................................................111
Detailed Extended Memory Range Address Map .............................................112
Intel® E7500 MCH Ballout (Top View) ..............................................................131
Intel® E7500 MCH Ballout (Left Half of Top View) ............................................132
Intel® E7500 MCH Ballout (Right Half of Top View)..........................................133
MCH Package Dimensions (Top View) .............................................................141
MCH Package Dimensions (Side View) ............................................................142
1-1
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
3-1
3-2
3-3
3-4
3-5
3-6
4-1
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-10
6-11
6-12
6-13
6-14
6-15
Supported DIMM Configuration...........................................................................15
System Bus Interface Signals .............................................................................19
DDR Channel_A Interface Signals ......................................................................22
DDR Channel_B Interface Signals ......................................................................23
HI _A Signals.......................................................................................................24
HI_B Signals........................................................................................................25
HI_C Signals .......................................................................................................26
HI_D Signals .......................................................................................................27
Clocks, Reset, Power, and Miscellaneous Signals .............................................28
Intel® E7500 MCH Logical Configuration Resources ..........................................33
DRAM Controller Register Map (HI_A—D0:F0) ..................................................37
PAM Associated Attribute Bits.............................................................................48
DRAM Controller Register Map (HI_A—D0:F1) ..................................................59
HI_B Virtual PCI-to-PCI Bridge Register Map (HI_A—D2:F0) ............................82
HI_B Virtual PCI-to-PCI Bridge Register Map (HI_A—D2:F1) ............................97
SMM Address Range ........................................................................................119
Absolute Maximum Ratings...............................................................................123
MCH Package Thermal Resistance ..................................................................123
Thermal Power Dissipation (VCC1_2 = 1.2 V ±5%)..........................................124
DC Characteristics Functional Operating Range (VCC1_2 = 1.2 V ±5%).........124
Signal Groups System Bus Interface ................................................................125
Signal Groups DDR Interface............................................................................125
Signal Groups Hub Interface 2.0 (HI_B–D) .......................................................126
Signal Groups Hub Interface 1.5 (HI_A)............................................................126
Signal Groups SMBus .......................................................................................126
Signal Groups Reset and Miscellaneous ..........................................................126
Operating Condition Supply Voltage (VCC1_2 = 1.2 V ±5%)............................127
System Bus Interface (VCC1_2 = 1.2 V ±5%)...................................................127
DDR Interface (VCC1_2 = 1.2 V ±5%) ..............................................................128
Hub Interface 2.0 Configured for 50 Ω (VCC1_2 = 1.2 V ±5%).........................129
Hub Interface 1.5 with Parallel Buffer Mode Configured for 50 Ω
(VCC1_2 = 1.2 V ±5%)......................................................................................130
Figures
Tables
Datasheet
7
7-1
7-2
7-3
7-4
7-5
7-6
7-7
7-8
7-9
8-1
8
MCH Signal List ................................................................................................ 134
Example Normalization Table ........................................................................... 143
MCH LPKG Data for the System Bus ................................................................. 144
MCH LPKG Data for DDR Channel A................................................................. 145
MCH LPKG Data for DDR Channel B................................................................. 148
MCH LPKG Data for Hub Interface_A ................................................................ 151
MCH LPKG Data for Hub Interface_B ................................................................ 151
MCH LPKG Data for Hub Interface_C ................................................................ 152
MCH LPKG Data for Hub Interface_D ................................................................ 152
XOR Chains ...................................................................................................... 154
Datasheet
Revision History
Rev.
-001
Datasheet
Description
Initial Release
Date
February 2002
9
Intel® E7500 MCH Features
■
■
■
Processor/Host Bus Support
— Intel® Xeon™ processor with 512-KB
L2 cache
— 400 MHz system bus
(2x address, 4x data)
— Symmetric Multiprocessing Protocol
(SMP) for up to two processors at
400 MT/s
— System bus Dynamic Bus Inversion
(DBI)
— 36-bit system bus addressing
— 12-deep in-order queue
— AGTL+ bus driver technology with
on-die termination resistors
— Parity protection on system bus data,
address/request, and response signals
Memory System
— One 144-bit wide DDR memory port
(with Chipkill* technology ECC)
— Peak memory bandwidth of 3.2 GB/s
— Supports 64 Mb, 128 Mb, 256 Mb,
512 Mb DRAM densities
— Supports a maximum of 16 GB of
memory using (x4) double-sided DIMM
— Supports x72, Registered, ECC DDR
DIMMs (in pairs)
Hub Interface_A to Intel® ICH3-S
— Supports connection to ICH3-S via
hub interface 1.5
— 266 MB/s point-to-point hub
interface 1.5 interface to ICH3-S
— Parity protected
— 66 MHz base clock running 4x
(533 MB/s) data transfer
— Isochronous support
— Parallel termination mode only
— 64-bit addressing on inbound
transactions (maximum 16 GB memory
decode space)
■
■
■
■
10
Hub Interface_B, Hub Interface_C, and
Hub Interface_D
— Supports connection to Intel® P64H2 via
HI 2.0
— Each hub interface is an independent
1 GB/s point-to-point 16-bit connection
— ECC protected
— 66 MHz base clock running 8x (1 GB/s)
data transfers
— Supports snooped and non-snooped
inbound accesses
— Parallel termination mode
— 64-bit inbound addressing
— 32-bit outbound addressing supported
for PCI-X
PCI / PCI-X
— Supports 33 MHz PCI on ICH3-S
— Supports 33 MHz and 66 MHz PCI on
P64H2
— Supports 66 MHz, 100 MHz or
133 MHz PCI-X on P64H2
RASUM
— Supports S4EC/D4ED ECC
— Provides x4 Chipkill technology ECC
support
— Correct any number of errors contained
in a 4-bit nibble
— Detect all errors contained entirely
within two 4-bit nibbles
— Hub Interface_A protected by parity
— Hub Interface_B–D protected by ECC
— Memory auto-initialization by hardware
implemented to allow main memory to
be initialized with valid ECC
— Memory scrubbing supported
— SMBus target interface access to MCH
error registers
— P64H2 and ICH3-S have SMBus target
interface for access to registers
— ICH3-S master SMBus interface reads
serial presence detect (SPD) on DIMMs
Package
— 1005-ball, 42.5 mm FC-BGA package
Datasheet
Introduction
1
Introduction
The Intel® E7500 chipset is targeted for the server market, both front-end and general purpose lowto mid-range. It is intended to be used with the Intel® Xeon™ processor with 512-KB L2 cache.
The E7500 chipset consists of three major components: the Intel® E7500 Memory Controller Hub
(MCH), the Intel® I/O Controller Hub 3 (ICH3-S), and the PCI/PCI-X 64-bit Hub 2.0 (P64H2).
The MCH provides the system bus interface, memory controller, hub interface for legacy I/O, and
three high-performance hub interfaces for PCI/PCI-X bus expansion.
This document describes the E7500 Memory Controller Hub (MCH). Section 1.3, “Intel® E7500
Chipset System Architecture” on page 1-12 provides an overview of each of the components of the
E7500 chipset. For details on other components of the chipset, refer to that component’s datasheet.
1.1
Glossary of Terms
Term
Datasheet
Description
DBI
Dynamic Bus Inversion.
DDR
Double Data Rate memory technology.
DP
Dual Processor.
Full Reset
The term “a full MCH reset” is used in this document when RSTIN# is asserted.
HI
Hub Interface. The proprietary hub interconnect that ties the MCH to the ICH3-S and
P64H2. In this document HI cycles originating from or destined for the primary PCI
interface on the ICH3-S are generally referred to as HI/PCI_A or simply HI_A cycles.
Cycles originating from or destined for any target on the second, third or fourth HI
interfaces are described as HI_B, HI_C, and HI_D cycles respectively. Note that there are
two versions of HI used on the Intel® E7500 MCH: an 8-bit HI 1.5 protocol is implemented
on HI_A and a 16-bit HI 2.0 protocol is used for the HI_B, HI_C and HI_D.
Host
This term is used synonymously with processor.
IB
Inbound, refers to traffic moving from PCI or other I/O toward DRAM or the system bus.
ICH3-S
The I/O Controller Hub 3-S component that contains the primary PCI interface, LPC
interface, USB, ATA-100, and other legacy functions. It communicates with the MCH over
a proprietary interconnect called the hub interface.
Intel® Xeon™
processor with
512-KB L2 cache
The processor supported by the Intel® E7500 chipset. This processor is the second
generation of processors based on the Intel® NetBurst™ microarchitecture. This
processor delivers performance levels that are significantly higher than previous
generations of IA-32 processors. This processor supports 1-2 processors on a single
system bus and has a 512 KB integrated L2 cache.
MCH
The Memory Controller Hub component that contains the processor interface and DRAM
interface. It communicates with the I/O Controller Hub 3-S (ICH3-S) and P64H2 over a
proprietary interconnect called the Hub Interface (HI).
OB
Outbound, refers to traffic moving from the system bus to PCI or other I/O.
Intel® P64H2
PCI/PCI-X 64-bit Hub 2.0 component. The Bus Controller Hub component has a 16-bit
hub interconnect 2.0 on its primary side and two, 64-bit PCI-X bus segments on the
secondary side.
11
Introduction
Term
1.2
Description
Primary PCI or
PCI_A
The physical PCI bus that is driven directly by the ICH3-S component. It supports 5 V,
32-bit, 33 MHz PCI 2.2 compliant components. Communication between PCI_A and the
MCH occurs over HI_A. Note that even though the Primary PCI bus is referred to as
PCI_A it is not PCI Bus #0 from a configuration standpoint.
RASUM
Reliability, Availability, Serviceability, Usability and Manageability.
Reference Documents
Document
Document
Number
Intel® Xeon™ Processor with 512 KB L2 Cache and Intel® E7500 Chipset Platform Design
Guide
298649
Intel® 82801CA I/O Controller Hub 3-S (ICH3-S) Datasheet
290733
Intel®
290732
82870P2 PCI/PCI-X 64-bit Hub 2 (P64H2) Datasheet
Intel®
E7500 Chipset: E7500 Memory Controller Hub (MCH) Thermal and Mechanical
Design Guidelines
298647
Intel® PCI/PCI-X 64-bit Hub 2 (P64H2) Thermal and Mechanical Design Guidelines
298648
Intel® 82802B/AC Firmware Hub (FWH) Datasheet
290658
Intel® Xeon™ Processor with 512-KB L2 Cache Datasheet
NOTE: Refer to the Intel® Xeon™ Processor with 512-KB L2 Cache and Intel® E7500 Chipset Platform Design
Guide for an expanded set of reference documents.
1.3
Intel® E7500 Chipset System Architecture
The E7500 chipset is optimized for the Intel Xeon processor with 512-KB L2 cache. The
architecture of the chipset provides the performance and feature-set required for dual-processor
based severs in the entry-level and mid-range, front-end and general-purpose server market
segments. A new chipset component interconnect, the hub interface 2.0 (HI2.0), is designed into
the E7500 chipset to provide more efficient communication between chipset components for highspeed I/O. Each HI2.0 provides 1.066 GB/s I/O bandwidth. The E7500 chipset has three HI2.0
connections, delivering 3.2 GB/s bandwidth for high-speed I/O, which can be used for PCI-X. The
system bus, used to connect the processor with the E7500 chipset, utilizes a 400 MT/s transfer rate
for data transfers, delivering a bandwidth of 3.2 GB/s. The E7500 chipset architecture supports a
144-bit wide, 200 MHz Double Data Rate (DDR) memory interface also capable of transferring
data at 3.2 GB/s.
In addition to these performance features, E7500 chipset-based platforms also provide the RASUM
(Reliability, Availability, Serviceability, Usability, and Manageability) features required for entrylevel and mid-range servers. These features include: Chipkill* technology ECC for memory, ECC
for all high-performance I/O, out-of-bound manageability through SMBus target interfaces on all
major components, memory scrubbing and auto-initialization, processor thermal monitoring, and
hot-plug PCI/PCI-X.
12
Datasheet
Introduction
The E7500 chipset consists of three major components: the Memory Controller Hub (MCH), the
I/O Controller Hub 3-S (ICH3-S), and the PCI/PCI-X 64-bit Hub 2.0 (P64H2). The chipset
components communicate via hub interfaces (HIs). The MCH provides four hub interface
connections: one for the ICH3-S and three for high-speed I/O using P64H2 bridges. The hub
interfaces are point-to-point and therefore only support two agents (the MCH plus one I/O device),
providing connections for up to 3 P64H2 bridges. The P64H2 provides bridging functions between
hub interface_B–D and the PCI/PCI-X bus. Up to six PCI-X busses are supported. Each PCI-X bus
is 66 MHz, 100 MHz, and 133 MHz PCI-X capable.
Additional platform features supported by the E7500 chipset include four ATA/100 IDE drives,
Low Pin Count interface (LPC), integrated LAN Controller, Audio Codec, and Universal Serial
Bus (USB).
The E7500 chipset is also ACPI compliant and supports Full-on, Stop Grant, Suspend to Disk, and
Soft-off power management states. Through the use of an appropriate LAN device, the E7500
chipset also supports wake-on-LAN* for remote administration and troubleshooting.
Figure 1-1. Intel® E7500 Chipset Platform Block Diagram
Processor
Processor
DDR Channel A
Main Memory
(16 GB Max)
200 MHz
Interface
MCH
DDR Channel B
USB 1.1
(6 ports)
8-Bit
HI 1.5
ATA-100
(4 drives)
SMBus 1.1
Intel® ICH3-S
16-Bit
HI 2.0
16-Bit
HI 2.0
GPIOs
PCI-X
Intel®
P64H2
Hot Plug
P64H2
Hot Plug
PCI-X
PCI-X
10/100 LAN
Controller
PCI-X
AC '97
FWH (1-4)
1.3.1
16-Bit
HI 2.0
PCI-X
P64H2
PCI Bus
Hot Plug
PCI-X
Intel® 82801CA I/O Controller Hub 3-S (ICH3-S)
The ICH3-S is a highly-integrated, multi-functional I/O Controller Hub that provides the interface
to the PCI bus and integrates many of the functions needed in today’s PC platforms. The MCH and
ICH3-S communicate over a dedicated hub interface. Intel 82801CA ICH3-S functions and
capabilities include:
•
•
•
•
•
Datasheet
PCI Local Bus Specification, Revision 2.2-compliant with support for 33 MHz PCI operations.
PCI slots ( supports up to 6 Req/Gnt pairs)
ACPI Power Management Logic Support
Enhanced DMA Controller, Interrupt Controller, and Timer Functions
Integrated IDE controller supports Ultra ATA100/66/33
13
Introduction
• USB host interface with support for 6 USB ports; 3 UHCI host controllers
• Integrated LAN Controller
• System Management Bus (SMBus) Specification, Version 1.1 with additional support for I2C
devices
• Audio Codec ’97, Revision 2.2 Specification (a.k.a., AC ’97 Component Specification,
Rev. 2.2) Compliant Link for Audio and Telephony codecs (up to 6 channels)
• Low Pin Count (LPC) interface
• Firmware Hub (FWH) interface support
• Alert On LAN* (AOL) and Alert On LAN 2* (AOL2)
1.3.2
Intel® 82870P2 PCI/PCI-X 64-bit Hub 2 (P64H2)
The 82870P2 PCI/PCI-X 64-bit Hub 2 (P64H2) is a peripheral chip that performs PCI bridging
functions between the MCH hub interface and the PCI -X busses. The P64H2 interfaces to the
MCH via a 16-bit hub interface. Each P64H2 has two independent 64-bit PCI bus interfaces that
can be configured to operate in PCI or PCI-X mode. Each PCI bus interface contains an
I/OAPIC with 24 interrupts and a hot-plug controller. Functions and capabilities include:
• 16-Bit hub interface to MCH
• Two PCI bus interfaces
— PCI Specification, Revision 2.2 compliant
— PCI-PCI Bridge Specification, Revision 1.1 compliant
— PCI-X Specification, Revision 1.0 compliant
— PCI hot plug 1.0 compliant
• SMBus interface
• Hot-plug controller for each PCI bus segment
• I/OAPIC for each PCI bus segment
1.4
Intel® E7500 MCH Overview
The MCH provides the processor interface, main memory interface, and hub interfaces in an E7500
chipset-based server platform. It supports Intel Xeon processor with 512 KB L2 cache processor.
The MCH is offered in a 1005-ball, 42.5 mm FC-BGA package and has the following
functionality:
•
•
•
•
•
•
•
14
Supports single or dual processor configurations at 400 MT/s
AGTL+ host bus with integrated termination supporting 36-bit host addressing
144-bit wide DDR channel supporting 200 MHz dual data rate operation
16 GB DDR DRAM (512 Mb devices) support
8-bit, 66 MHz 4x hub interface A to ICH3-S
Three 16-bit, 66 MHz 8x hub interface
Distributed arbitration for highly concurrent operation
Datasheet
Introduction
1.4.1
Processor System Interface
The E7500 MCH is optimized for use with processors based on the Intel® NetBurst™
microarchitecture. It supports the following features:
•
•
•
•
•
•
•
1.4.2
400 MHz system bus (2x address, 4x data)
Symmetric multiprocessing protocol (SMP) for up to two processors at 400 MT/s
System bus dynamic bus inversion (DBI)
36-bit system bus addressing
12-deep in-order queue
AGTL+bus driver technology with on die termination resistors
Parity protection on system bus data, address/ request, and response signals
Main Memory Interface
The MCH directly supports two channels of DDR DRAM operating in lock-step. These channels
are organized to provide minimum latency for the critical segment of data. The MCH DDR
channels run at 200 MHz. The MCH supports 64-Mb, 128-Mb, 256-Mb, or 512-Mb memory
technology. The MCH provides ECC error checking with Chipkill technology, on x4 DIMMS to
ensure DRAM data integrity. The MCH supports x72, registered, ECC DDR DIMMs. The MCH
memory interface supports the following operations:
•
•
•
•
Provides x4 Chipkill technology ECC support
Corrects any number of errors contained in a 4-bit nibble
Detects all errors contained entirely within two 4-bit nibbles
8 KB–64 KB page sizes support 64 Mb to 512 Mb DRAM Devices
The supported DIMM configurations are listed in Table 1-1.
Table 1-1. Supported DIMM Configuration
Density
Device Width
64 Mbit
128 Mbit
X4
X8
256 Mbit
X4
X8
X4
Single / Double
SS / DS
SS / DS
SS / DS
SS / DS
SS / DS
184 Pin DDR DIMM
Capacity
128 MB /
256 MB
64 MB/
128 MB
256 MB /
512 MB
128 MB /
256 MB
512 MB /
1024 MB
X8
512 Mbit
X4
X8
SS / DS
SS / DS
SS / DS
256 MB /
512 MB
1024MB/ 512MB/
2048MB 1024 MB
NOTE: DIMMs must be populated in pairs, and the DIMMs in a pair must be identical.
1.4.3
Hub Interface_A (HI_A)
The 8-bit HI_A connects the MCH to the ICH3-S. All communication between the MCH and the
ICH3-S occurs over HI_A, running at 66 MHz base clock 4x (266 MB/s). HI_A supports upstream
64-bit addressing and downstream 32-bit addressing. All incoming accesses on HI_A are snooped.
HI_A provides preferential treatment for isochronous transfers. The interface supports parallel
termination only.
Datasheet
15
Introduction
1.4.4
Hub Interface_B–D (HI_B–D)
The MCH supports three 16-bit hub interfaces that run at 66 MHz 8x (1 GB/s). The 16-bit HI 2.0
interfaces support 32-bit downstream addressing and 64-bit upstream addressing. For Hub
Interface_B–D to main memory accesses, memory read and write accesses are supported. For
processor to Hub Interface_B–D accesses, memory reads, memory writes, I/O reads, and I/O writes
are supported.
The 16-bit hub interfaces 2.0 support parallel termination only. The 16-bit HI 2.0 may or may not
be connected to a device. The MCH detects the presence of a device on each 16-bit hub. If a hub
interface is not connected to a valid hub interface device, the bridge configuration register space for
that interface is disabled.
1.4.5
MCH Clocking
The MCH has the following clock input pins:
• Differential HCLKINP/HCLKINN for the host interface
• 66 MHz clock input for the HI_A, HI_B, HI_C, HI_D interfaces
Clock synthesizer chip(s) generate the system bus clock and hub interface clock. The system bus
interface clock speed is 100 MHz. The MCH does not require any relationship between the
HCLKIN host clock and the 66 MHz clock generated for hub interfaces. The HI_A, HI_B, HI_C
and HI_D interfaces run at a 66 MHz base clock frequency. HI_A runs at 4x, HI_B, HI_C, and
HI_D run at 8x.
The DDR clocks generated by the MCH have a 1:1 relationship with the system bus.
1.4.6
SMBus Interface
The SMBus address for the MCH is 011_0000. This interface has no configuration registers
associated with it. The SMBus controller has access to all internal MCH registers. It does not allow
access to devices on the hub interface or PCI buses. The SMBus port can read all MCH error
registers. It can only write a special set of “shadowed” error registers. These error registers are an
exact copy of what the processor has access to. This allows the processor to read and clear its set of
error registers independently from the set the SMBus port controls. The SMBus port can only write
the error registers to clear them; the only supported write operation is a byte write. Reads are
always performed as 4-byte accesses.
16
Datasheet
Signal Description
Signal Description
2
This section provides a detailed description of MCH signals. The signals are arranged in functional
groups according to their associated interface.
The “#” symbol at the end of a signal name indicates that the active, or asserted state occurs when
the signal is at a low voltage level. When “#” is not present after the signal name the signal is
asserted when at the high voltage level.
The following notations are used to describe the signal type:
I
Input pin
O
Output pin
I/O
Bidirectional Input/Output pin
as/t/s
Active Sustained tristate. This applies to some of the hub interface (HI)
signals. This pin is weakly driven to its last driven value
2x
Double-pump clocking. Addressing at 2x of HCLKINx
4x
Quad-pump clocking. Data transfer at 4x of HCLKINx
SSTL-2
Stub series terminated logic for 2.5 Volts. Refer to the JEDEC
specification D8-9A for complete details
The signal description also includes the type of buffer used for the particular signal:
Note:
Datasheet
AGTL+
Open drain AGTL+ interface signal. Refer to the AGTL+ I/O
Specification for complete details. The MCH integrates AGTL+
termination resistors
CMOS
CMOS buffers
Certain signals are logically inverted signals. The logical values are the inversion of the electrical
values on the system bus.
17
Signal Description
Figure 2-1. MCH Interface Signals
HA[35:3]#
HD[63:0]#
ADS#
BNR#
BPRI#
DBSY#
DEFER#
DRDY#
HIT#
HITM#
HLOCK#
HREQ[4:0]#
HTRDY#
RS[2:0]#
CPURST#
BREQ0#
DBI[3:0]#
HADSTB[1:0]#
HDSTBP[3:0]#/HDSTBN[3:0]#
AP[1:0]#
XERR#
BINIT#
DP[3:0]#
RSP#
HCLKINP, HLCKINN
HDVREF[3:0]
HAVREF[1:0]
HCCVREF
HXSWNG, HYSWNG
HXRCOMP, HYRCOMP
CB_A[7:0]
DQ_A[63:0]
DQS_A[17:0]
CMDCLK_A[3:0], CMDCLK_A[3:0]#
MA_A[12:0]
BA_A[1:0]
RAS_A#
CAS_A#
WE_A#
CS_A[7:0]#
CKE_A
RCVENIN_A#
RCVENOUT_A#
DDRCOMP_A
DDRCVOH_A
DDRCVOL_A
DDRVREF_A[5:0]
CB_B[7:0]
DQ_B[63:0]
DQS_B[17:0]
CMDCLK_A[3:0], CMDCLK_B[3:0]#
MA_B[12:0]
BA_B[1:0]
RAS_B#
CAS_B#
WE_B#
CS_B[7:0]#
CKE_B
RCVENIN_B#
RCVENOUT_B#
DDRCOMP_B
DDRCVOH_B
DDRCVOL_B
DDRVREF_B[5:0]
18
Hub
Interface
A
Processor
System
Bus
Interface
Hub
Interface
B
Hub
Interface
C
Hub
Interface
D
DDR
Channel
A
Clocks
and
Reset
HI_A[11:0]
HI_STBF
HI_STBS
HIRCOMP_A
HISWNG_A
HIVREF_A
CLK66
HI_B[21:20]
HI_B[18:0]
PSTRBF_B
PSTRBS_B
PUSTRBF_B
PUSTRBS_B
HIRCOMP_B
HISWNG_B
HIVREF_B
CLK66
HI_C[21:20]
HI_C[18:0]
PSTRBF_C
PSTRBS_C
PUSTRBF_C
PUSTRBS_C
HIRCOMP_C
HISWNG_C
HIVREF_C
CLK66
HI_D[21:20]
HI_D[18:0]
PSTRBF_D
PSTRBS_D
PUSTRF_D
PUSTRS_D
HIRCOMP_D
HISWNG_D
HIVREF_D
CLK66
RSTIN#
XORMODE#
PWRGOOD
SMB_CLK
SMB_DATA
DDR
Channel
B
Datasheet
Signal Description
2.1
System Bus Interface Signals
Table 2-1. System Bus Interface Signals (Sheet 1 of 3)
Signal Name
ADS#
AP[1:0]#
XERR#
BINIT#
BNR#
BPRI#
BREQ0#
CPURST#
DBSY#
DEFER#
DP[3:0]#
Type
I/O
Description
AGTL+
Address Strobe: The system bus owner asserts ADS# to indicate the first of
two cycles of a request phase.
I/O
Address Parity: The AP[1:0]# lines are driven by the request initiator and
provide parity protection for the Request Phase signals. AP[1:0]# are common
clock signals and are driven one common clock after the request phase.
AGTL+
I
AGTL+
I
AGTL+
I/O
AGTL+
O
AGTL+
I/O
AGTL+
O
AGTL+
I/O
AGTL+
O
AGTL+
I/O
AGTL+
Address parity is correct if there are an even number of electrically low signals
(low voltage) in the set consisting of the covered signals plus the parity signal.
Note that the MCH only connects to HA[35:3]#.
Bus Error: This signal may be connected to the MCERR# signal or IERR#
signal, depending on system usage. The MCH detects an electrical high to low
transition on this input and set the correct error bit. The MCH will take no other
action except setting that bit.
Bus Initialize: This signal indicates an unrecoverable error occurred and can
be driven by the processor. It is latched by the MCH.
Block Next Request: BNR# is used to block the current request bus owner
from issuing a new requests. This signal is used to dynamically control the
system bus pipeline depth.
Priority Agent Bus Request: The MCH is the only Priority Agent on the
system bus. It asserts this signal to obtain ownership of the address bus. The
MCH has priority over symmetric bus requests and will cause the current
symmetric owner to stop issuing new transactions unless the HLOCK# signal is
asserted.
Bus Request 0: The MCH pulls the processor bus BREQ0# signal low during
CPURST#. The signal is sampled by the processors on the active-to-inactive
transition of CPURST#. The minimum setup time for this signal is four HCLKs.
The minimum hold time is two HCLKs and the maximum hold time is 20 HCLKs.
BREQ0# should be Tristate after the hold time requirement has been satisfied.
CPU Reset: The MCH asserts CPURST# while RSTIN# (PCIRST# from
ICH3-S) is asserted and for approximately 1 ms after RSTIN# is deasserted.
CPURST# allows the processors to begin execution in a known state.
Data Bus Busy: This signal is used by the data bus owner to hold the data bus
for transfers requiring more than one cycle.
Defer: When asserted, the MCH will terminate the transaction currently being
snooped with either a deferred response or with a retry response.
Host Data Parity: The DP[3:0]# signals provide parity protection for HD[63:0]#.
The DP[3:0]# signals are common clock signals and are driven one common
clock after the data phases they cover. DP[3:0]# are driven by the same agent
driving HD[63:0]#.
Data parity is correct if there are an even number of electrically low signals (low
voltage) in the set consisting of the covered signals plus the parity signal.
I/O
DBI[3:0]#
AGTL+
4x
DRDY#
Datasheet
I/O
AGTL+
Dynamic Bus Inversion: The DBI[3:0]# signals are driven along with the
HD[63:0]# signals. They indicate when the associated signals are inverted.
DBI[3:0]# are asserted such that the number of data bits driven electrically low
(low voltage) within the corresponding 16 bit group never exceeds 8.
Data Ready: This signal is asserted for each cycle that data is transferred.
19
Signal Description
Table 2-1. System Bus Interface Signals (Sheet 2 of 3)
Signal Name
Type
I/O
HA[35:3]#
GTL+
2x
Description
Host Address Bus: HA[35:3]# connect to the system address bus. During
processor cycles, HA[35:3]# are inputs. The MCH drives HA[35:3]# during
snoop cycles on behalf of hub interface initiators.
I/O
HADSTB[1:0]#
AGTL+
Host Address Strobe: The source synchronous strobes are used to latch
HA[35:3]# and HREQ[4:0]#.
2x
I/O
HD[63:0]#
AGTL+
Host Data: These signals are connected to the system data bus.
4x
Differential Host Data Strobes: The differential source synchronous strobes
are used to latch HD[63:0]# and DBI[3:0]#.
HDSTBP[3:0]#
HDSTBN[3:0]#
I/O
Strobe Data Bits Associated
AGTL+
HDSTBP3#, HDSTBN3# HD[63:48]#, DBI3#
4x
HDSTBP2#, HDSTBN2# HD[47:32]#, DBI2#
HDSTBP1#, HDSTBN1# HD[31:16]#, DBI1#
HDSTBP0#, HDSTBN0# HD[15:0]#, DBI0#
HIT#
HITM#
HLOCK#
I/O
AGTL+
I/O
AGTL+
I
AGTL+
I/O
HREQ[4:0]#
AGTL+
2x
HTRDY#
O
AGTL+
Hit: HIT# indicates that a caching agent holds an unmodified version of the
requested line. This signal is also driven in conjunction with HITM# by the target
to extend the snoop window.
Hit Modified: HITM# indicates that a caching agent holds a modified version of
the requested line and that this agent assumes responsibility for providing the
line. HITM# is driven in conjunction with HIT# to extend the snoop window.
Host Lock: All system bus cycles are sampled with the assertion of HLOCK#
and ADS#, until the negation of HLOCK#. This operation is atomic.
Host Request Command: HREQ[4:0]# defines the attributes of the request.
These signals are asserted by the requesting agent during both halves of a
request phase. In the first half the signals define the transaction type to a level
of detail that is sufficient to begin a snoop request. In the second half the signals
carry additional information to define the complete transaction type.
Host Target Ready: HTRDY# indicates that the target of the processor
transaction is able to enter the data transfer phase.
Response Signals: RS[2:0]# indicate the type of response according to the
following table:
RS[2:0] Response Type
RS[2:0]#
RSP#
AGTL+
O
AGTL+
HCLKINP,
I
HLCKINN
CMOS
HDVREF[3:0]
20
O
I
Analog
000 Idle state
001 Retry response
010 Deferred response
011 Reserved (not driven by MCH)
100 Hard Failure (not driven by MCH)
101 No data response
110 Implicit Writeback
111 Normal data response
Response Parity: RSP# provides parity protection for the RS[2:0]# signals.
RSP# is always driven by the MCH and must be valid on all clocks. Response
parity is correct when there are an even number of low signals (low voltage) in
the set consisting of the RS[2:0]# signals and the RSP# signal itself.
Differential Host Clock In: These input pins receive a differential host clock
from the external clock synthesizer. The clock is used by all the MCH logic in
the host clock domain.
Host Data Reference Voltage: RHDVREF[3:0] are the reference voltage inputs
for the 4x data signals of the Host GTL interface.
Datasheet
Signal Description
Table 2-1. System Bus Interface Signals (Sheet 3 of 3)
Signal Name
HAVREF[1:0]
HCCVREF
Datasheet
Type
I
Analog
I
Analog
HXSWNG,
I
HYSWNG
Analog
HXRCOMP,
I
HYRCOMP
Analog
Description
Host Address Reference Voltage: HAVREF[1:0] are the reference voltage
inputs for the 2x address signals of the Host GTL interface.
Host Common Clock Reference Voltage: HCCVREF is the reference voltage
input for the common clock signals of the Host GTL interface
Host Voltage Swing: These signals provide a reference voltage used by the
system bus RCOMP circuit.
Host RCOMP: These signals are used to calibrate the Host AGTL+ I/O buffers.
21
Signal Description
2.2
DDR Channel A Signals
Table 2-2. DDR Channel_A Interface Signals
Signal Name
CB_A[7:0]
DQ_A[63:0]
DQS_A[17:0]
I/O
SSTL-2
I/O
SSTL-2
I/O
SSTL-2
CMDCLK_A[3:0],
O
CMDCLK_A[3:0]#
CMOS
MA_A[12:0]
BA_A[1:0]
RAS_A#
CAS_A#
WE_A#
CS_A[7:0]#
CKE_A
RCVENIN_A#
RCVENOUT_A#
DDRCOMP_A
DDRCVOH_A
DDRCVOL_A
DDRVREF_A[5:0]
22
Type
O
SSTL-2
O
SSTL-2
O
SSTL-2
O
SSTL-2
O
SSTL-2
O
SSTL-2
O
SSTL-2
I
SSTL-2
O
SSTL-2
I
CMOS
I
Analog
I
Analog
I
Analog
Description
DDR Channel A Check bits: These check bits are required to
provide ECC support.
DDR Channel A Data Bus: The DDR data bus provides the data
interface for the DRAM devices.
DDR Channel A Data Strobes: DQS_A[17:0] are the DDR data
strobes. Each data strobe is used to strobe a set of 4 or 8 data
signals.
DDR Channel A Command CLOCK: These signals are the DDR
command clocks used by the DDR DRAMs to latch MA[12:0],
BA[1:0], RAS#, CAS#, WE#, CKE#, and CS# signals.
DDR Channel A Memory Address: MA_A[12:0] are the DDR
memory address signals.
DDR Channel A Bank Address: BA_A[1:0] are the DDR bank
address signals. These bits select the bank within the DDR DRAM.
DDR Channel A Row Address Strobe: RAS_A# is used to indicate
a valid row address and open a row.
DDR Channel A Column Address Strobe: CAS_A# is used to
indicate a valid column address and initiate a transaction.
DDR Channel A Write Enable: WE_A# is used to indicate a write
cycle.
DDR Channel A Chipselect: The chip select signals are used to
indicate which DRAM device cycles are targeted.
DDR Channel a Clock Enable: CKE_A is the DDR clock enable
signal.
Receive Enable Input: RCVENIN_A# is used for DRAM timing.
Receive Enable Output: RCVENOUT_A# is used for DRAM timing.
Compensation for DDR A: This signal is used to calibrate the DDR
buffers.
Compensation for DDR A: This signal is used to calibrate the DDR
buffers.
Compensation for DDR A: This signal is used to calibrate the DDR
buffers.
DDR Channel A Voltage Reference: DDR reference voltage input.
Datasheet
Signal Description
2.3
DDR Channel B Signals
Table 2-3. DDR Channel_B Interface Signals
Signal Name
CB_B[7:0]
DQ_B[63:0]
DQS_B[17:0]
I/O
SSTL-2
I/O
SSTL-2
I/O
SSTL-2
CMDCLK_B[3:0],
O
CMDCLK_B[3:0]#
CMOS
MA_B[12:0]
BA_B[1:0]
RAS_B#
CAS_B#
WE_B#
CS_B[7:0]#
CKE_B
RCVENIN_B#
RCVENOUT_B#
DDRCOMP_B
DDRCVOH_B
DDRCVOL_B
DDRVREF_B[5:0]
Datasheet
Type
O
SSTL-2
O
SSTL-2
O
SSTL-2
O
SSTL-2
O
SSTL-2
O
SSTL-2
O
SSTL-2
I
SSTL-2
O
SSTL-2
I/O
CMOS
I
Analog
I
Analog
I
Analog
Description
DDR Channel B Check bits: These check bits are required to provide
ECC support.
DDR Channel B Data Bus: The DDR data bus provides the data interface
for the DRAM devices.
DDR Channel B Data Strobes: DQS_B[17:0] are the DDR data strobes.
Each data strobe is used to strobe a set of 4 or 8 data signals.
DDR Channel B Command CLOCK: These signals are the DDR
command clocks used by the DDR DRAMs to latch MA[12:0], BA[1:0],
RAS#, CAS#, WE#, CKE#, and CS# signals.
DDR Channel B Memory Address: MA_B[12:0] are the DDR memory
address signals.
DDR Channel B Bank Address: BA_B[1:0] are the DDR bank address
signals. These bits select the bank within the DDR DRAM.
DDR Channel B Row Address Strobe: RAS_B# is used to indicate a
valid row address and open a row.
DDR Channel B Column Address Strobe: CAS_B# is used to indicate a
valid column address and initiate a transaction.
DDR Channel B Write Enable: WE_B# is used to indicate a write cycle.
DDR Channel B Chipselect: The chip select signals are used to indicate
which DRAM device cycles are targeted.
DDR Channel B Clock Enable: CKE_B is the DDR clock enable signal.
Receive Enable Input: RCVENIN_B# is used for DRAM timing.
Receive Enable Output: RCVENOUT_B# is used for DRAM timing.
Compensation for DDR B: This signal is used to calibrate the DDR
buffers.
Compensation for DDR A: This signal is used to calibrate the DDR
buffers.
Compensation for DDR A: This signal is used to calibrate the DDR
buffers.
DDR Channel B Voltage Reference: DDR reference voltage input.
23
Signal Description
2.4
Hub Interface_A Signals
Table 2-4. HI _A Signals
Signal Name
Type
Description
I/O
HI_A[11:0]
(as/t/s)
HI_A Signals: HI_A[11:0] are the signals used for the hub interface between
the ICH3-S and the MCH.
CMOS
I/O
HI_STBF
HI_STBS
(as/t/s)
CMOS
Note:In Normal Buffer Mode (HI 1.0) the HI_STBF signal is called HI_STB#.
Refer to the platform design guide and the MCH documentation for
appropriate hub interface strobe signals.
I/O
HI_A Strobe Compliment: HI_STBS is one of the two strobes signals used to
transmit or receive packet data over HI_A.
(as/t/s)
CMOS
HIRCOMP_A
HISWNG_A
HIVREF_A
CLK661
HI_A Strobe: HI_STBF is one of the two strobe signals used to transmit and
receive packet data over HI_A.
I
Analog
I
Analog
I
Analog
I
CMOS
Note: In Normal Buffer Mode (HI 1.0) the HI_STB# signal is called HI_STB.
Refer to the platform design guide and the MCH documentation for
appropriate hub interface strobe signals.
Compensation for HI_A: This signal is used to calibrate the HI_A I/O buffers.
HI_A Voltage Swing: This signal provides a reference voltage used by the
HI_A RCOMP circuit.
HI_A Reference: HIVREF_A is a reference voltage input for the HI_A
interface.
66 MHz Clock In:. This pin receives a 66 MHz clock from the clock
synthesizer. This clock is shared by the HI_A, HI_B, HI_C, and HI_D.
NOTES:
1. Clk66 is being shared by HI_A-D. Physically there is one CLK 66 pin on the MCH.
24
Datasheet
Signal Description
2.5
Hub Interface_B Signals
1)
Table 2-5. HI_B Signals
Signal Name
Type
Description
I/O
HI_B[21:20]
(as/t/s)
HI_B Signals: HI_B[21:20] are the ECC signals used for connection between
the 16-bit hub and the MCH.
CMOS
I/O
HI_B[18:0]
(as/t/s)
HI_B Signals: The HI_B[18:0] signals are used for connection between the
16-bit hub and the MCH.
CMOS
I/O
PSTRBF_B
(as/t/s)
HI_B Strobe First: PSTRBF_B is one of two strobes signal pairs used to
transmit or receive lower 8-bit data over HI_B.
CMOS
I/O
PSTRBS_B
(as/t/s)
HI_B Strobe Second: PSTRBS_B is one of two strobes signal pairs used to
transmit or receive lower 8-bit packet data over HI_B.
CMOS
I/O
PUSTRBF_B
(as/t/s)
HI_B Upper Strobe First: PUSTRBF_B is one of two strobes signal pairs
used to transmit or receive upper 8-bit packet data over HI_B.
CMOS
I/O
PUSTRBS_B
(as/t/s)
HI_B Upper Strobe Second: PUSTRBS_B is one of two strobes signal pairs
used to transmit or receive upper 8-bit packet data over HI_B.
CMOS
HIRCOMP_B
HISWNG_B
HIVREF_B
CLK661
I/O
CMOS
I
Analog
I
Analog
I
CMOS
Compensation for HI_B: This signal is used to calibrate the HI_B I/O buffers.
HI_B Voltage Swing: This signal provides a reference voltage used by the
HI_B RCOMP circuit.
HI_B Reference: HIVREF_B is a reference voltage input for the HI_B
interface.
66 MHz Clock In: This pin receives a 66 MHz clock from the clock
synthesizer. This clock is shared by the HI_A, HI_B, HI_C and HI_D.
NOTES:
1. Clk66 is being shared by HI_A-D. Physically there is one CLK 66 pin on the MCH.
Datasheet
25
Signal Description
2.6
Hub Interface_C Signals
Table 2-6. HI_C Signals
Signal Name
Type
Description
I/O
HI_C[21:20]
(as/t/s)
HI_C Signals: HI_C[21:20] are the ECC signals used for connection between
the 16-bit hub and the MCH.
CMOS
I/O
HI_C[18:0]
(as/t/s)
HI_C Signals: HI_C[18:0] are the signals used for the connection between the
16-bit hub and the MCH.
CMOS
I/O
PSTRBF_C
(as/t/s)
HI_C Strobe First: PSTRBF_C is one of two strobe signal pairs used to
transmit or receive lower 8-bit data over HI_C.
CMOS
I/O
PSTRBS_C
(as/t/s)
HI_C Strobe second: PSTRBS_C is one of two strobe signals pairs used to
transmit or receive lower 8-bit data over HI_C.
CMOS
I/O
PUSTRBF_C
(as/t/s)
HI_C Upper Strobe First: PUSTRBF_C is one of two strobe signals pairs used
to transmit or receive upper 8-bit data over HI_C.
CMOS
I/O
PUSTRBS_C
(as/t/s)
HI_C Upper Strobe Second: PUSTRBS_C is one of two strobe signals pairs
used to transmit or receive upper 8-bit data over HI_C.
CMOS
HIRCOMP_C
HISWNG_C
HIVREF_C
CLK661
I/O
CMOS
I
Analog
I
Analog
I
CMOS
Compensation for HI_C: This signal is used to calibrate the HI_C I/O buffers.
HI_C Voltage Swing: This signal provides a reference voltage used by the
HI_C RCOMP circuit.
HI_C Reference: HIVREF_C is a reference voltage input for the HI_C interface.
66 MHz Clock In:. This pin receives a 66 MHz clock from the clock synthesizer.
This clock is shared by the HI_A, HI_B, HI_C and HI_D.
NOTES:
1. Clk66 is being shared by HI_A-D. Physically there is one CLK 66 pin on the MCH.
26
Datasheet
Signal Description
2.7
Hub Interface_D Signals
Table 2-7. HI_D Signals
Signal Name
Type
Description
I/O
HI_D[21:20]
(as/t/s)
HI_D Signals: HI_D[21:20] are ECC signals used for connection between the
16-bit hub and the MCH.
CMOS
I/O
HI_D[18:0]
(as/t/s)
HI_D Signals: HI_D[18:0] are the signals used for the connection between the
16-bit hub and the MCH.
CMOS
I/O
PSTRBF_D
(as/t/s)
HI_D Strobe First: PSTRBF_D is one of two strobe signal pairs used to
transmit or receive lower 8-bit data over HI_D.
CMOS
I/O
PSTRBS_D
(as/t/s)
HI_D Strobe Second: PSTRBS_D is one of two strobe signal pairs used to
transmit or receive lower 8-bit data over HI_D.
CMOS
I/O
PUSTRF_D
(as/t/s)
HI_D Upper Strobe First: PUSTRF_D is one of two strobe signal pairs used to
transmit or receive upper 8-bit data over HI_D.
CMOS
I/O
PUSTRS_D
(as/t/s)
HI_D Upper Strobe Second: PUSTRS_D is one of two strobe signal pairs
used to transmit or receive upper 8-bit data over HI_D.
CMOS
HIRCOMP_D
HISWNG_D
HIVREF_D
CLK661
I/O
CMOS
I
Analog
I
Analog
I
CMOS
Compensation for HI_D: This signal is used to calibrate the HI_D I/O buffers.
HI_D Voltage Swing: This signal provides a reference voltage used by the
HI_DRCOMP circuit.
HI_D Reference: HIVREF_D is the reference voltage input for the HI_D
interface.
66 MHz Clock In:. This pin receives a 66 MHz clock from the clock synthesizer.
This clock is shared by the HI_A, HI_B, HI_C and HI_D.
NOTES:
1. Clk66 is being shared by HI_A-D. Physically there is one CLK 66 pin on the MCH.
Datasheet
27
Signal Description
2.8
Clocks, Reset, Power, and Miscellaneous Signals
The voltage reference pins are described in the signal description sections for the associated
interface.
Table 2-8. Clocks, Reset, Power, and Miscellaneous Signals
Signal Name
RSTIN#
XORMODE#
PWRGOOD
2.9
Type
I
CMOS
I
CMOS
I
Description
Reset In: When asserted, RSTIN# asynchronously resets the MCH logic.
This signal is connected to the PCIRST# output of the ICH3-S.
Test Input: When XORMODE# is asserted, the MCH places all outputs in
XOR mode for board-level testing.
Power Good: This signal resets the MCH component, including “sticky”
logic. It is driven by external logic to indicate all power rails are present.
SMB_CLK
I/O
SMBus Clock: This is the clock pin for the SMBus interface.
SMB_DATA
I/O
SMBus Data: This is the data pin for the SMBus interface.
VCC1_2
Power: These pins are 1.2 V power input pins for HI_A–D, and the MCH
core.
VCCA1_2
Power: These pins are 1.2 V analog power input pins.
VCCAHI1_2
Power: This pin is a 1.2 V analog power input pin.
VCCACPU1_2
Power: This pin is a 1.2 V analog power input pin.
VCC_CPU
Power: For the system bus interface.
VCC2_5
Power: These pins are 2.5 V power input pins for DDR.
VSS
Ground: Ground pin.
Pin States During and After Reset
This section provides the signal states during reset (assertion of RSTIN#) and immediately
following reset (deassertion of RSTIN#).
28
Legend
Interpretation
Drive
Strong drive (to normal value supplied by core logic, if not otherwise stated
TERM
Normal termination devices on
LV
Low voltage
HV
High voltage
IN
Input buffer enabled
ISO
Isolate inputs in inactive states
TRI
Tri-state
PU
Weak pull-up
PD
Weak pull-down
Datasheet
Signal Description
Signal Name
State During
RSTIN#
Assertion
State After
RSTIN#
Deassertion
Signal Name
TERM HV
(after 1ms)
TERM HV 1
TERM HV 2
HADSTB[1:0]#
TERM HV
TERM HV
AP[1:0]#
TERM HV
TERM HV
HA[35:3]#
Datasheet
DRIVE LV
State After
RSTIN#
Deassertion
DDR Channel A Interface
System Bus Interface
CPURST#
State During
RSTIN#
Assertion
HD[63:0]#
TERM HV
TERM HV
HDSTBp[3:0]#
TERM HV
TERM HV
HDSTBn[3:0]#
TERM HV
TERM HV
DEP[3:0]#
TERM HV
TERM HV
DBI[3:0]#
TERM HV
TERM HV
ADS#
TERM HV
TERM HV
BNR#
TERM HV
TERM HV
BPRI#
TERM HV
TERM HV
DBSY#
TERM HV
TERM HV
CB_A[7:0]
TRI
TRI
DQ_A[63:0]
TRI
TRI
DQS_A[17:0]
TRI
TRI
CMDCLK_A[3:0]
LV
Starts to
toggle
CMDCLK_A[3:0]#
LV
Starts to
toggle
MA_A[12:0]
Note 4
Note 4
BA_A[1:0]
Note 4
Note 4
RAS_A#
LV
LV
CAS_A#
HV
HV
WE_A#
HV
HV
CS_A[7:0]#
HV
HV
CKE_A
LV
Note 6
RCVENIN_A#
IN
IN
RCVENOUT_A#
HV
HV
DEFER#
TERM HV
TERM HV
DRDY#
TERM HV
TERM HV
HIT#
TERM HV
TERM HV
HITM#
TERM HV
TERM HV
CB_B[7:0]
TRI
TRI
HLOCK#
TERM HV
TERM HV
DQ_B[63:0]
TRI
TRI
HREQ[4:0]#
TERM HV
TERM HV
DQS_B[17:0]
TRI
TRI
HTRDY#
TERM HV
TERM HV
CMDCLK_B[3:0]
LV
RS[2:0]#
TERM HV
TERM HV
Starts to
toggle
RSP#
TERM HV
TERM HV
CMDCLK_B[3:0]#
LV
Starts to
toggle
BERR#
TERM HV
TERM HV
MA_B[12:0]
Note 4
Note 4
BREQ0#
TERM HV
DRIVE LV 3
BA_B[1:0]
Note 4
Note 4
HDVREF[3:0]
IN
IN
RAS_B#
LV
LV
HAVREF[1:0]
IN
IN
CAS_B#
HV
HV
HCCVREF
IN
IN
WE_B#
HV
HV
HXRCOMP
TRI
TRI after
RCOMP
CS_B[7:0]#
HV
HV
LV
Note 6
TRI
TRI after
RCOMP
CKE_B
HYRCOMP
RCVENIN_B#
IN
IN
HXSWNG
IN
IN
RCVENOUT_B#
HV
HV
HYSWNG
IN
IN
DDR Channel B Interface
29
Signal Description
Signal Name
State During
RSTIN#
Assertion
State After
RSTIN#
Deassertion
Signal Name
State After
RSTIN#
Deassertion
Clocks and Miscellaneous
Hub Interface_A
HI7_A
Weak PU
TERM LV
HCLKIN[N:P]
IN
IN
HI_A[11:8,6:0]
Weak PD
TERM LV
CLK66
IN
IN
HI_STBF
Weak PD
TERM LV
RSTIN#
IN
IN
HI_STBS
Weak PD
TERM LV
XORMODE#
IN
IN
TRI
TRI after
RCOMP
PWRGOOD
IN
IN
HIVREF_A
IN
IN
HISWNG_A
IN
IN
HIRCOMP_A
Hub Interface_B–D
HI_x[21:17,15:0]
HI16_x
30
State During
RSTIN#
Assertion
Weak PD
TERM LV
Note 5
TERM LV
PSTRBF_x,
PUSTRBF_x
Weak PD
TERM LV
PSTRBS_x,
PUSTRBS_x
Weak PD
TERM LV
HIRCOMP_x
TRI
TRI after
RCOMP
HIVREF_x
IN
IN
HISWNG_x
IN
IN
NOTES:
1. DRIVE LV if POC or Straps are set
2. Any signals driven LV from POC Register go to
TERM HV two clocks after CPURST# deasserts
3. Drive LV and hold until two clocks after CPURST#
is deasserted, and then TERM HV.
4. Active 0 or 1, either is ok
5. Weak PU for Swizzle; Weak PD for non-Swizzle
6. Remains low and is asserted after 256 clocks
Datasheet
Register Description
3
Register Description
The MCH contains two sets of software accessible registers, accessed via the host processor I/O
address space:
• Control registers – These registers are I/O mapped into the processor I/O space, which control
access to PCI configuration space (see Section 3.5, “I/O Mapped Registers” on page 3-35)
• Internal configuration registers – These registers, which reside within the MCH, are
partitioned into multiple logical device register sets (“logical” since they reside within a single
physical device). One register set is dedicated to Host-HI Bridge functionality (controls
PCI_A, DRAM configuration, other chipset operating parameters, and optional features).
Other sets of registers map to HI_B, HI_C and HI_D.
The MCH supports PCI configuration space accesses using the mechanism denoted as
Configuration Mechanism #1 in the PCI specification.
The MCH internal registers (I/O mapped and configuration registers) are accessible by the host.
The registers can be accessed as Byte (8-bit), Word (16-bit), or DWord (32-bit) quantities, with the
exception of the CONF_ADDR Register, which can only be accessed as a DWord. All multi-byte
numeric fields use “little-endian” ordering (i.e., lower addresses contain the least significant parts
of the field).
3.1
Register Terminology
Term
Datasheet
Description
RO
Read Only. In some cases, If a register is read only, writes to this register location have no
effect. However, in other cases, two separate registers are located at the same location
where a read accesses one of the registers and a write accesses the other register. See the
I/O and memory map tables for details.
WO
Write Only. In some cases, If a register is write only, reads to this register location have no
effect. However, in other cases, two separate registers are located at the same location
where a read accesses one of the registers and a write accesses the other register. See the
I/O and memory map tables for details.
R/W
Read/Write. A register with this attribute can be read and written.
R/WC
Read/Write Clear. A register bit with this attribute can be read and written. However, a write
of 1 clears (sets to 0) the corresponding bit and a write of 0 has no effect.
R/W/L
Read/Write/Lock. A register with this attribute can be read, written and locked.
R/WO
Read/Write Once. A register (bit) with this attribute can be written only once after power up.
After the first write, the register (bit) becomes read only.
L
Lock. A register bit with this attribute becomes read only after a lock bit is set.
31
Register Description
3.2
Term
Description
Reserved Bits
Some of the MCH registers described in this chapter contain reserved bits. These bits are
labeled Reserved (Rsvd). Software must deal correctly with fields that are reserved. On
reads, software must use appropriate masks to extract the defined bits and not rely on
reserved bits being any particular value. On writes, software must ensure that the values of
reserved bit positions are preserved. That is, the values of reserved bit positions must first be
read, merged with the new values for other bit positions and then written back. Note the
software does not need to perform read, merge, and write operations for the configuration
address register.
Reserved
Registers
The MCH contains address locations in the configuration space of the Host-HI Bridge entity
that are marked “Reserved”. Registers that are marked as “Reserved” must not be modified
by system software. Writes to “Reserved” registers may cause system failure. Reads to
“Reserved” registers may return a non-zero value.
Default Value
upon Reset
Upon a Reset, the MCH sets its internal configuration registers to predetermined default
states. At reset, some register values are determined by external strapping options. A
register’s default value represents the minimum functionality feature set required to
successfully bring up the system. Hence, it does not represent the optimal system
configuration. It is the responsibility of the system initialization software (usually BIOS) to
properly determine the DRAM configurations, operating parameters and optional system
features that are applicable, and to program the MCH registers accordingly.
Platform Configuration
The MCH and the ICH3-S are physically connected by HI_A. From a configuration standpoint,
HI_A is logically PCI bus 0. As a result, all devices internal to the MCH and ICH3-S appear to be
on PCI bus 0. The system’s primary PCI expansion bus is physically attached to the ICH3-S and,
from a configuration perspective appears to be a hierarchical PCI bus behind a PCI-to-PCI bridge
and therefore has a programmable PCI Bus number.
Note:
The primary PCI bus is referred to as PCI_A in this document and is not PCI bus 0 from a
configuration standpoint.
The 16-bit hub interface ports appear to system software to be real PCI buses behind PCI-to-PCI
bridges resident as devices on PCI bus 0.
The MCH decodes multiple PCI Device numbers. The configuration registers for the devices are
mapped as devices residing on PCI bus 0. Each Device Number may contain multiple functions.
• Device 0: Host-HI_A Bridge/DRAM Controller. Logically this appears as a PCI device
residing on PCI bus 0. Physically Device 0 contains the standard PCI bridge registers, DRAM
registers, configuration for HI_A, and other MCH specific registers.
• Device 2: Host-HI_B Bridge. Logically this bridge appears to be a PCI-to-PCI bridge device
residing on PCI bus 0. Physically, Device 2 contains the standard PCI bridge registers and
configuration registers for HI_B.
• Device 3: Host-HI_C Bridge. Logically this bridge appears to be a PCI-to-PCI bridge device
residing on PCI bus 0. Physically, Device 3 contains the standard PCI bridge registers and
configuration registers for HI_C.
• Device 4: Host-HI_D Bridge. Logically this bridge appears to be a PCI-to-PCI bridge device
residing on PCI bus 0. Physically, Device 4 contains the standard PCI bridge registers and
configuration registers for HI_D.
32
Datasheet
Register Description
Table 3-1 shows the Device # assignment for the various internal MCH devices. All of these
devices are on Bus #0.
Table 3-1. Intel® E7500 MCH Logical Configuration Resources
Intel® MCH Function
3.3
Device #, Function #
DRAM Controller (8 bit HI_A)
Device 0, Function 0
DRAM Controller Error Reporting (8 bit HI_A)
Device 0, Function 1
Host-to-HI_B Bridge Controller (16 bit PCI2PCI)
Device 2, Function 0
Host-to-HI_B Bridge Error Reporting (16 bit PCI2PCI)
Device 2, Function 1
Host-to-HI_C Bridge Controller (16 bit PCI2PCI)
Device 3, Function 0
Host-to-HI_C Bridge Error Reporting (16 bit PCI2PCI)
Device 3, Function 1
Host-to-HI_D Bridge Controller (16 bit PCI2PCI)
Device 4, Function 0
Host-to-HI_D Bridge Error Reporting (16 bit PCI2PCI)
Device 4, Function 1
General Routing Configuration Accesses
The MCH supports up to four hub interfaces: HI_A, HI_B, HI_C, and HI_D. PCI configuration
cycles are selectively routed to one of these interfaces. The MCH is responsible for routing PCI
configuration cycles to the proper interface. PCI configuration cycles to ICH3-S internal devices
and Primary PCI (including downstream devices) are routed to the ICH3-S via HI_A. PCI
configuration cycles to any of the 16-bit hub interfaces are routed to HI_B, HI_C, and HI_D.
Routing of configuration accesses to HI_B, HI_C, and HI_D is controlled via the standard PCI-PCI
bridge mechanism using information contained within the primary bus number, the secondary bus
number, and the subordinate bus number registers of the corresponding PCI-PCI bridge device.
A detailed description of the mechanism for translating processor I/O bus cycles to configuration
cycles on one of the buses is described below.
Note:
3.3.1
The MCH supports a variety of connectivity options. When any of the MCH’s interfaces are
disabled, the associated interface’s device registers are not visible. Configuration cycles to these
registers will return all 1s for a read and master abort for a write.
Standard PCI Configuration Mechanism
The PCI bus defines a slot-based configuration space that allows each device to contain up to eight
functions; each function contains up to 256, 8-bit configuration registers. The PCI specification
defines two bus cycles to access the PCI configuration space: Configuration Read and
Configuration Write. Memory and I/O spaces are supported directly by the processor.
Configuration space is supported by a mapping mechanism implemented within the MCH. The PCI
specification defines two mechanisms to access configuration space, Mechanism 1 and Mechanism
2. The MCH supports only Mechanism 1.
The configuration access mechanism makes use of the CONF_ADDR Register and CONF_DATA
Register. To reference a configuration register a DWord I/O write cycle is used to place a value into
CONF_ADDR that specifies the PCI bus, the device on that bus, the function within the device,
and a specific configuration register of the device function being accessed. CONF_ADDR[31]
must be 1 to enable a configuration cycle. CONF_DATA then becomes a window into the four
Datasheet
33
Register Description
bytes of configuration space specified by the contents of CONF_ADDR. Any read or write to
CONF_DATA results in the MCH translating the CONF_ADDR into the appropriate configuration
cycle.
The MCH is responsible for translating and routing the processor’s I/O accesses to the
CONF_ADDR and CONF_DATA Registers to internal MCH configuration registers for HI_A,
HI_B, HI_C, and HI_D.
3.3.2
Logical PCI Bus 0 Configuration Mechanism
The MCH decodes the Bus Number (bits 23:16) and the Device Number fields of the
CONF_ADDR Register. When the Bus Number field of CONF_ADDR is 0, the configuration
cycle is targeting a PCI bus 0 device.
•
•
•
•
The Host-HI_A bridge entity within the MCH is hardwired as Device 0 on PCI Bus 0.
The Host-HI_B bridge entity within the MCH is hardwired as Device 2 on PCI Bus 0.
The Host-HI_C bridge entity within the MCH is hardwired as Device 3 on PCI Bus 0.
The Host-HI_D bridge entity within the MCH is hardwired as Device 4 on PCI Bus 0.
Configuration cycles to any of the MCH’s enabled internal devices are confined to the MCH and
not sent over HI_A. Accesses to devices 8 to 31 are forwarded over HI_A as Type 0. The ICH3-S
decodes the Type 0 access and generates a configuration access to the selected internal device.
3.3.3
Primary PCI Downstream Configuration Mechanism
When the Bus Number in the CONF_ADDR is non-zero, and does not lie between the Secondary
Bus Number registers and the Subordinate Bus Number registers for one of the HI_16, the MCH
will generate a type 1 HI_A configuration cycle.
When the cycle is forwarded to the ICH3-S via HI_A, the ICH3-S compares the non-zero Bus
Number with the Secondary Bus Number and Subordinate Bus Number registers of its PCI- PCI
bridges to determine if the configuration cycle is meant for Primary PCI, or a downstream PCI bus.
3.3.4
HI_B, HI_C, HI_D Bus Configuration Mechanism
From the chipset configuration perspective, HI_B, HI_C and HI_D are seen as PCI bus interfaces
residing on a Secondary Bus side of the “virtual” PCI-PCI bridges referred to as the MCH HostHI_B, HI_C and HI_D bridge.
Note:
There is no requirement that the secondary and subordinate bus number values from one Hub
Interface be contiguous with any other Hub Interfaces. It is possible that HI_B will decode buses 2
through 5, HI_C will decode buses 8 through 12, and HI_D will decode buses 13 through 15. In
this case there is a gap where buses 6 and 7 are subtractively decoded to HI_A.
When the bus number is non-zero, greater than the value programmed into the Secondary Bus
Number Register, and less than or equal to the value programmed into the corresponding
Subordinate Bus Number Register, the configuration cycle is targeting a PCI bus downstream of
the targeted hub interface. The MCH generates a Type 1configuration cycle on the appropriate hub
interface.
34
Datasheet
Register Description
3.4
Sticky Registers
Certain registers in the MCH are sticky through a hard-reset. They will only be reset on a powergood reset. These registers in general are the error logging registers and a few special cases. The
error command registers are not sticky. The following registers are sticky:
•
•
•
•
•
3.5
Device 0, Function 1 error registers
Device 2, Function 1 error registers
Device 3, Function 1 error registers
Device 4, Function 1 error registers
Others that are determined to need to hold state through reset for function or test purposes
I/O Mapped Registers
The MCH contains two registers that reside in the processor I/O address space; the Configuration
Address (CONF_ADDR) Register and the Configuration Data (CONF_DATA) Register. The
Configuration Address Register enables/disables the configuration space and determines what
portion of configuration space is visible through the Configuration Data window.
3.5.1
CONF_ADDR—Configuration Address Register
I/O Address:
Default Value:
Access:
Size:
0CF8h Accessed as a DWord
00000000h
R/W
32 bits
CONF_ADDR is a 32-bit register that can be accessed only as a DWord. A Byte or Word reference
will pass through the Configuration Address Register and HI_A onto the PCI_A bus as an I/O
cycle. The CONF_ADDR Register contains the Bus Number, Device Number, Function Number,
and Register Number that a subsequent configuration access is intended.
Bit
Descriptions
Configuration Enable (CFGE).
31
0 = Disable
1 = Enable
Datasheet
30:24
Reserved (These bits are read only and have a value of 0).
23:16
Bus Number. Contains the bus number being targeted by the config cycle.
15:11
Device Number. Selects one of the 32 possible devices per bus.
10:8
Function Number. Selects one of 8 possible functions within a device.
7:2
Register Number: This field selects one register within a particular Bus, Device, and Function as
specified by the other fields in the Configuration Address Register. This field is mapped to A[7:2]
during HI_A–D Configuration cycles.
1:0
Reserved.
35
Register Description
3.5.2
CONF_DATA—Configuration Data Register
I/O Address:
Default Value:
Access:
Size:
0CFCh
00000000h
Read/Write
32 bits
CONF_DATA is a 32-bit read/write window into configuration space. The portion of configuration
space that is referenced by CONF_DATA is determined by the contents of CONF_ADDR.
Bit
31:0
36
Descriptions
Configuration Data Window (CDW). If bit 31 of CONF_ADDR is 1, any I/O access to the
CONF_DATA register are mapped to configuration space using the contents of CONF_ADDR.
Datasheet
Register Description
3.6
DRAM Controller Registers (Device 0, Function 0)
The DRAM Controller registers are in Device 0 (D0), Function 0 (F0). Table 3-2 provides the
register address map for this device, function.
Warning:
Address locations that are not listed the table are considered reserved register locations. Writes to
“Reserved” registers may cause system failure. Reads to “Reserved” registers may return a nonzero value.
Table 3-2. DRAM Controller Register Map (HI_A—D0:F0)
Offset
Datasheet
Mnemonic
Register Name
Default
Type
00–01h
VID
Vendor ID
8086h
RO
02–03h
DID
Device ID
2540h
RO
04–05h
PCICMD
PCI Command
0006h
RO, R/W
06–07h
PCISTS
PCI Status
0090h
RO, R/WC
Revision ID
02h
RO
Sub Class Code
00h
RO
08h
RID
0Ah
SUBC
0Bh
BCC
Base Class Code
06h
RO
0Dh
MLT
Master Latency Timer
00h
—
0Eh
HDR
Header Type
2C–2Dh
SVID
Subsystem Vendor Identification
00h
RO
0000h
R/WO
Subsystem Identification
0000h
R/WO
MCH Configuration
0004h
R/W
MCH Memory Scrub and Init Configuration
2E–2Fh
SID
50–51h
MCHCFG
52–53h
MCHCFGNS
58h
FDHC
59–5Fh
PAM[0:6]
60–6Fh
DRB
70–77h
DRA
DRAM Row Attribute
00h
R/W
78–7Bh
DRT
DRAM Timing
00000010h
R/W
7C–7Fh
DRC
DRAM Controller Mode
8Ch
CLOCK_DIS
9Dh
SMRAM
0000h
RO, R/W
Fixed DRAM Hole Control
00h
R/W
Programmable Attribute Map (7 registers)
00h
R/W
DRAM Row Boundary
00h
R/W
00440009h
R/W
CK/CK# Disable
00h
R/W
System Management RAM Control
02h
RO, R/W, L
38h
R/W, R/WC,
R/W/L
Top of Low Memory
0800h
R/W
Extended System Management RAM
Control
9Eh
ESMRAMC
C4–C5h
TOLM
C6–C7h
REMAPBASE
Remap Base Address
03FFh
R/W
C8–C8h
REMAPLIMIT
Remap Limit Address
0000h
R/W
DE–DFh
SKPD
Scratchpad Data
0000h
R/W
E0–E1h
DVNP
Device Not Present
1D1Fh
R/W
37
Register Description
3.6.1
VID—Vendor Identification Register (D0:F0)
Address Offset:
Default:
Access:
Size:
00–01h
8086h
RO
16 Bits
The VID Register contains the vendor identification number. This 16-bit register combined with
the Device Identification Register uniquely identify any PCI device.
Bits
15:0
3.6.2
Default,
Access
8086h
RO
Description
Vendor Identification (VID). This register field contains the PCI standard identification
for Intel (VID=8086h).
DID—Device Identification Register (D0:F0)
Address Offset:
Default:
Access:
Size:
02–03h
2540h
RO
16 Bits
This 16-bit register combined with the Vendor Identification register uniquely identifies any PCI
device.
Bits
15:0
38
Default,
Access
2540h
RO
Description
Device Identification Number (DID). This is a 16-bit value assigned to the MCH HostHI Bridge Function 0.
Datasheet
Register Description
3.6.3
PCICMD—PCI Command Register (D0:F0)
Address Offset:
Default:
Access:
Size:
O4–05h
0006h
RO, R/W
16 Bits
Since MCH Device 0 does not physically reside on a physical PCI bus portions of this register are
not implemented.
Bits
Default,
Access
15:10
00h
Reserved
0b
Fast Back-to-Back Enable (FB2B). Hardwired to 0. This bit controls whether or not the
master can do fast back-to-back writes. Since device 0 is strictly a target this bit is not
implemented.
9
RO
Description
SERR Enable (SERRE). This is a global enable bit for Device 0 SERR messaging. The
MCH does not have an SERR signal. The MCH communicates the SERR condition by
sending an SERR message over HI_A to the ICH3-S.
8
0b
R/W
0 = Disable. SERR message is not generated by the MCH for Device 0.
1 = Enable. The MCH is enabled to generate SERR messages over HI_A for specific
Device 0 error conditions that are individually enabled in the ERRCMD register. The
error status is reported in the ERRSTAT and PCISTS registers. When SERRE is
cleared, the SERR message is not generated by the MCH for Device 0.
NOTE: This bit only controls SERR messaging for the Device 0. Devices 2–4 have their
own SERR bits to control error reporting for error conditions occurring on their
respective devices. The control bits are used in a logical OR configuration to
enable the SERR HI message mechanism.
7
0b
RO
Address/Data Stepping Enable (ADSTEP). Hardwired to 0. Address/data stepping is
not implemented in the MCH.
Parity Error Enable (PERRE).
6
5
4
3
2
1
0
Datasheet
0b
R/W
0b
RO
0b
RO
0b
RO
1b
RO
1b
RO
0b
RO
0 = Disable. MCH takes no action when it detects a parity error on HI_A.
1 = Enable. MCH generates an SERR message over HI_A to the ICH3-S when an
address or data parity error is detected by the MCH on HI_A (DPE set in PCISTS).
VGA Palette Snoop Enable (VGASNOOP). Hardwired to 0. The MCH does not
implement this bit.
Memory Write and Invalidate Enable (MWIE). Hardwired to 0. The MCH will never
issue memory write and invalidate commands.
Special Cycle Enable (SCE). Hardwired to 0. The MCH does not implement this bit.
Bus Master Enable (BME). Hardwired to 1. The MCH is always enabled as a master on
HI_A.
Memory Access Enable (MAE). Hardwired to 1. The MCH always allows access to
main memory.
I/O Access Enable (IOAE). Hardwired to 0. This bit is not implemented in the MCH.
39
Register Description
3.6.4
PCISTS—PCI Status Register (D0:F0)
Address Offset:
Default:
Access:
Size:
06–07h
0090h
RO, R/WC
16 Bits
PCISTS is a 16-bit status register that reports the occurrence of error events on Device 0’s PCI
interface. All other bits are Read Only. Since MCH Device 0 does not physically reside on a PCI
bus, many of these bits are not implemented.
Note:
Software must write a 1 to clear bits that are set.
Bits
15
Default,
Access
0b
R/WC
Description
Detected Parity Error (DPE).
0 = No Parity error detected.
1 = MCH detected an address or data parity error on the HI_A interface.
Signaled System Error (SSE).
14
13
12
11
10:9
8
7
6:0
40
0b
R/WC
0b
RO
0b
R/WC
0b
RO
00b
RO
0b
RO
0 = No SERR generated by MCH Device 0.
1 = MCH Device 0 generates an SERR message over HI_A for any enabled Device 0
error condition. Device 0 error conditions are enabled in the PCICMD and
ERRCMD Registers. Device 0 error flags are read/reset from the PCISTS or
ERRSTAT Registers.
Received Master Abort Status (RMAS). Hardwired to 0. The ICH3-S never sends a
Master Abort completion.
Received Target Abort Status (RTAS).
0 = No received Target Abort generated by MCH.
1 = MCH generated a HI_A request that received a Target Abort.
Signaled Target Abort Status (STAS). Hardwired to 0. The MCH will not generate a
Target Abort on HI_A. This bit is not implemented.
DEVSEL Timing (DEVT). These bits are hardwired to 00. Device 0 does not physically
connect to PCI_A. These bits are set to 00 (fast decode) so that optimum DEVSEL
timing for PCI_A is not limited by the MCH.
Master Data Parity Error Detected (DPD). Hardwired to 0. PERR signaling and
messaging are not implemented by the MCH.
RO
Fast Back-to-Back (FB2B). Hardwired to 1. Device 0 does not physically connect to
PCI_A. This bit is set to 1 (indicating fast back-to-back capability) so that the optimum
setting for PCI_A is not limited by the MCH.
00h
Reserved
1b
Datasheet
Register Description
3.6.5
RID—Revision Identification Register (D0:F0)
Address Offset:
Default:
Access:
Size:
08h
See table below
RO
8 Bits
This register contains the revision number of the MCH Device 0.
Bits
7:0
3.6.6
Default,
Access
00h
RO
Description
Revision Identification Number (RID). This is an 8-bit value that indicates the revision
identification number for the MCH Device 0.
02h = A2 stepping
SUBC—Sub-Class Code Register (D0:F0)
Address Offset:
Default:
Access:
Size:
0Ah
00h
RO
8 Bits
This register contains the Sub-Class Code for the MCH Device 0.
Bits
7:0
3.6.7
Default,
Access
Description
00h
Sub-Class Code (SUBC). This is an 8-bit value that indicates the category of Bridge into
which the MCH falls.
RO
00h = Host bridge.
BCC—Base Class Code Register (D0:F0)
Address Offset:
Default:
Access:
Size:
0Bh
06h
RO
8 Bits
This register contains the Base Class Code of the MCH Device 0.
Bits
7:0
Datasheet
Default,
Access
Description
06h
Base Class Code (BASEC). This is an 8-bit value that indicates the Base Class Code for
the MCH.
RO
06h = Bridge device.
41
Register Description
3.6.8
MLT—Master Latency Timer Register (D0:F0)
Address Offset:
Default:
Access:
Size:
0Dh
00h
Reserved
8 Bits
Device 0 in the MCH is not a PCI master. Therefore, this register is not implemented.
3.6.9
Bits
Default,
Access
7:0
00h
Description
Reserved
HDR—Header Type Register (D0:F0)
Address Offset:
Default:
Access:
Size:
0Eh
00h
RO
8 Bits
This register identifies the header layout of the configuration space.
Bits
7:0
3.6.10
Default,
Access
00h
RO
Description
PCI Header (HDR). This register returns 00 when Device 0, Function 1 is disabled. If
Device 0, Function 1 is enabled via the DVNP Register, this register (HDR) returns 80h.
SVID—Subsystem Vendor Identification Register (D0:F0)
Address Offset:
Default:
Access:
Size:
2C–2Dh
0000h
R/WO
16 Bits
This value is used to identify the vendor of the subsystem.
Bits
15:0
42
Default,
Access
0000h
R/WO
Description
Subsystem Vendor ID (SUBVID). This field should be programmed during boot-up to
indicate the vendor of the system board. After it has been written once, it becomes read
only.
Datasheet
Register Description
3.6.11
SID—Subsystem Identification Register (D0:F0)
Address Offset:
Default:
Access:
Size:
2E–2Fh
0000h
R/WO
16 Bits
This value is used to identify a particular subsystem.
Bits
15:0
3.6.12
Default,
Access
0000h
R/WO
Description
Subsystem ID (SUBID). This field should be programmed during BIOS initialization. After
it has been written once, it becomes read only.
MCHCFG—MCH Configuration Register (D0:F0)
Address Offset:
Default:
Access:
Size:
50–51h
0004h
R/W
16 Bits
This register controls how the MCH tracks and routes system bus transactions.
Bits
15:13
Default,
Access
000b,
R/W
Description
Number of Stop Grant Cycles (NSG). These bits indicate the number of Stop Grant
transactions expected on the system bus before a Stop Grant Acknowledge packet is sent
to the ICH3-S. This field is programmed by the BIOS after it has enumerated the
processors and before it has enabled Stop Clock generation in the ICH3-S. Once this field
has been set, it should not be modified.
000 = HI_A Stop Grant generated after 1 Stop Grant
001 = HI_A Stop Grant generated after 2 Stop Grant
010 = HI_A Stop Grant generated after 3 Stop Grant
011 = HI_A Stop Grant generated after 4 Stop Grant
Others = Reserved
12:6
Datasheet
000000b
Reserved
43
Register Description
Bits
Default,
Access
Description
MDA Present (MDAP). This bit works with the VGA Enable bits in the BCTRL Registers
of devices 2–4 to control the routing of processor initiated transactions targeting MDA
compatible I/O and memory address ranges. This bit should not be set if none of the VGA
Enable bits are set. When none of the VGA enable bits are set, accesses to I/O address
range x3BCh–x3BFh are forwarded to HI_A. When the VGA enable bit is not set,
accesses to I/O address range x3BCh–x3BFh are treated just like any other I/O accesses.
That is, the cycles are forwarded to HI_B–D if the address is within the corresponding
IOBASE and IOLIMIT and ISA enable bit is not set; otherwise, they are forwarded to HI_A.
MDA resources are defined as the following:
Memory: 0B0000h – 0B7FFFh
5
0b
R/W
I/O: 3B4h, 3B5h, 3B8h, 3B9h, 3BAh, 3BFh,
(including ISA address aliases, A[15:10] are not used in decode)
Any I/O reference that includes the I/O locations listed above, or their aliases, will be
forwarded to the hub interface, even if the reference includes I/O locations not listed
above.
The following shows the behavior for all combinations of MDA and VGA:
VGAMDABehavior
0 0 All References to MDA and VGA go to HI_A
0 1 Illegal Combination (DO NOT USE)
1 0 All References to VGA go to device with VGA enable set. MDA-only references (I/
O address 3BFh and aliases) will go to HI_A.
1 1 VGA References go to the hub interface that has its VGAEN bit set. MDA
References go to HI_A
Throttled-Write Occurred.
4
3
0b
R/W
0b
0 =Writing a zero clears this bit.
1 =This bit is set when a write is throttled. This bit is set when the maximum allowed
number of writes has been reached during a time-slice and there is at least one more
write to be completed.
Reserved
In-Order Queue Depth (IOQD). This bit reflects the value sampled on HA7# on the
deassertion of the CPURST#. It indicates the depth of the processor bus in-order queue.
2
1:0
44
0b
RO
00b
0 = When IOQD is set to 0 (HA7# is sampled asserted; i.e., 1; or an electrical low), the
depth of the IOQ is set to 1 (i.e., no pipelining support on the processor bus). HA7#
may be driven low during CPURST# by an external source.
1 = When IOQD is set to 1 (HA7# sampled as 0; an electrical high), the depth of the
processor bus in-order queue is configured to the maximum allowed by the
processor protocol (i.e., 12).
Reserved
Datasheet
Register Description
3.6.13
MCHCFGNS—MCH Memory Scrub and Initialization
Configuration Register (D0:F0)
Address Offset:
Default:
Access:
Size:
52–53h
0000h
RO, R/W
16 Bits
This register controls the mode and status of the DRAM memory scrubber.
Bits
Default,
Access
15:4
000h
3
2
0b
RO
0b
R/W
Description
Reserved
Valid ECC Initialization Complete. BIOS should poll this bit after enabling autoinitialization to determine when all the ECC values have been written to DRAM.
1 = The scrub unit sets this bit to 1 after it has completed placing valid ECC data in each
line of memory.
Initialization/Scrub Mode Select. This bit determines if the MCH is initializing memory
(with valid ECC data) or running standard memory scrubbing. In the Initialization Mode,
the MCH issues memory writes as quickly as possible and places valid ECC in each
memory location. In Scrubbing Mode, the MCH scrubs a memory location (read a memory
line and correct any ECC errors) every 32,000 clocks. This scrubs an entire 16 GB
memory array in approximately 1 day.
0 = Valid ECC Init Mode
1 = ECC Scrub Mode
BIOS should set this bit to 0, enable scrubbing via bit 0, wait until bit 3 (Valid ECC Init
Complete) is set, and set this bit to 1 (or disable scrubbing).
1
0
Datasheet
0b
Reserved
0b
Memory Initialization/Scrub Enable. This bit enables Valid ECC Init Mode or ECC Scrub
Mode depending on the value in bit 2 (Init/Scrub Mode Select).
R/W
0 = Disable
1 = Enable
45
Register Description
3.6.14
FDHC—Fixed DRAM Hole Control Register (D0:F0)
Address Offset:
Default:
Sticky:
Access:
Size:
58h
00h
No
R/W
8 Bits
This 8-bit register controls a fixed DRAM hole from 15 MB –16 MB
Bit Field
Default and
Access
Description
Hole Enable (HEN). This field enables a memory hole in DRAM space. The
DRAM that lies "behind" this space is not remapped.
7
0b
RW
0 =No memory hole
1 =Memory hole from 15 MB to 16 MB. Accesses to this range will be sent to
HI_A.
6:0
46
00h
Reserved
Datasheet
Register Description
3.6.15
PAM[0:6]—Programmable Attribute Map Registers (D0:F0)
Address Offset:
Default Value:
Access:
Size:
59–5Fh (PAM0–PAM6)
00h
R/W
8 bits each
The MCH allows programmable memory attributes on 13 legacy memory segments of various
sizes in the 640 KB to 1 MB address range. Seven Programmable Attribute Map (PAM) Registers
support these features. However, not all seven of these registers are identical. PAM 0 controls only
one segment (high), while PAM 1:6 controls two segments (high and low) each. Cacheability of
these areas is controlled via the MTRR Registers in the processor. Two bits are used to specify
memory attributes for each memory segment. These bits only apply to host initiator access to the
PAM areas. The MCH forwards to main memory any Hub Interface_A–D initiated accesses to the
PAM areas. At the time that hub interface accesses to the PAM region may occur, the targeted PAM
segment must be programmed to be both readable and writeable. It is illegal to issue a hub initiated
transaction to a PAM region with the associated PAM register not set to 11. Each of these regions
has a 2-bit field. The two bits that control each region have the same encoding.
As an example, consider BIOS that is implemented on the expansion bus. During the initialization
process, BIOS can be shadowed in main memory to increase the system performance. When BIOS
is shadowed in main memory, it should be copied to the same address location. To shadow the
BIOS, the attributes for that address range should be set to write only. The BIOS is shadowed by
first doing a read of that address. This read is forwarded to the expansion bus. The host then does a
write of the same address, which is directed to main memory. After the BIOS is shadowed, the
attributes for that memory area are set to read only so that all writes are forwarded to the expansion
bus. Table 3-3and Figure 3-1 show the PAM Registers and the associated attribute bits:
Bits
Default,
Access
7:6
00b
Description
Reserved
Attribute Register (HIENABLE). This field controls the steering of read and write cycles
that address the BIOS.
5:4
00b
00 = DRAM Disabled - All accesses are directed to HI_A
R/W
01 = Read Only - All Reads are serviced by DRAM. All Writes are forwarded to HI_A.
10 = Write Only - All writes are sent to DRAM. Reads are serviced by HI_A.
11 = Normal DRAM operation - All reads and writes are serviced by DRAM
3:2
0h
Reserved
Attribute Register (LOENABLE). This field controls the steering of read and write cycles
that address the BIOS.
00 =DRAM Disabled - All accesses are directed to HI_A
1:0
00b
01 =Read Only - All Reads are serviced by DRAM. All Writes are forwarded to HI_A.
R/W
10 =Write Only - All writes are sent to DRAM. Reads are serviced by HI_A.
1 1 =Normal DRAM operation - All reads and writes are serviced by DRAM
NOTE: The LO Segment for PAM0 is reserved as shown in Figure 3-1.
Datasheet
47
Register Description
Figure 3-1. PAM Registers
H I S eg m en t
O ffse t
L O S e g m en t
PAM6
5Fh
PAM5
5Eh
PAM4
5D h
PAM3
5C h
PAM2
5B h
5A h
PAM1
R e se rve d
PAM0
59 h
7
6
5
4
3
2
1
0
R
R
WE
RE
R
R
WE
RE
R e se rve d
R ea d E n a b le (R /W )
1 = E n ab le
0 = D is ab le
R e se rved
W rite E na b le (R /W )
1 = E n ab le
0 = D is ab le
W rite E na b le (R /W )
1 = E n ab le
0 = D is ab le
R ea d E n a b le (R /W )
1 = E n a b le
0 = D is a b le
R e se rve d
R e se rve d
Table 3-3. PAM Associated Attribute Bits
48
PAM Reg
Attribute Bits
Memory Segment
Comments
Offset
PAM0 3:0, 7:6
Reserved
—
—
59h
PAM0 5:4
R
R
WE
RE
0F0000h–0FFFFFh
BIOS Area
59h
PAM1 3:2, 7:6
—
—
—
—
—
Reserved
5Ah
PAM1 1:0
R
R
WE
RE
0C0000h–0C3FFFh
BIOS Area
5Ah
PAM1 5:4
R
R
WE
RE
0C4000h–0C7FFFh
BIOS Area
5Ah
PAM2 3:2, 7:6
—
—
—
—
—
Reserved
5Bh
PAM2 1:0
R
R
WE
RE
0C8000h–0CBFFFh
BIOS Area
5Bh
PAM2 5:4
R
R
WE
RE
0CC000h–0CFFFFh
BIOS Area
5Bh
PAM3 3:2, 7:6
—
—
—
—
—
Reserved
5Ch
PAM3 1:0
R
R
WE
RE
0D0000h–0D3FFFh
BIOS Area
5Ch
PAM3 5:4
R
R
WE
RE
0D4000h–0D7FFFh
BIOS Area
5Ch
PAM4 3:2, 7:6
—
—
—
—
—
Reserved
5Dh
PAM4 1:0
R
R
WE
RE
0D8000h–0DBFFFh
BIOS Area
5Dh
PAM4 5:4
R
R
WE
RE
0DC000h–0DFFFFh
BIOS Area
5Dh
PAM5 3:2, 7:6
—
—
—
—
—
Reserved
5Eh
PAM5 1:0
R
R
WE
RE
0E0000h–0E3FFFh
BIOS Extension
5Eh
PAM5 5:4
R
R
WE
RE
0E4000h–0E7FFFh
BIOS Extension
5Eh
PAM6 3:2, 7:6
—
—
—
—
—
Reserved
5Fh
PAM6 1:0
R
R
WE
RE
0E8000h–0EBFFFh
BIOS Extension
5Fh
PAM6 5:4
R
R
WE
RE
0EC000h–0EFFFFh
BIOS Extension
5Fh
Datasheet
Register Description
3.6.16
DRB—DRAM Row Boundary Register (D0:F0)
Address Offset:
Default:
Access:
Size:
60–6Fh
00h
R/W
8 Bits
The DRAM Row Boundary Register defines the upper boundary address of each DRAM row with
a granularity of 64 MB. A row is 144 bits wide (72 bits per channel). Each row has its own singlebyte DRB Register. For example, a value of 1 in DRB0 indicates that 64 MB of DRAM has been
populated in the first row.
Note:
The MCH DRAM Row Boundary Registers (DRB Registers) are 8-bits wide, and define the upper
boundary address for each DRAM row with a granularity of 64 MB. The DRB Registers are
cumulative; therefore, DRB7 will contain the total memory contained in all eight DRAM rows. By
this definition, the system is only allowed to report 16 GB–64 MB of memory populated.
Bits
7:0
Default,
Access
00h
R/W
Description
DRAM Row Boundary Address. This 8-bit value defines the upper and lower addresses
for each row of DRAM. This 8-bit value is compared against a set of address lines to
determine the upper address limit of a particular row.
Row 0 = 60h
Row 1 = 61h
Row 2 = 62h
Row 3 = 63h
Row 4 = 64h
Row 5 = 65h
Row 6 = 66h
Row 7 = 67h
68h to 6Fh are reserved
DRB0 = Total memory in row 0 (in 64 MB increments)
DRB1 = Total memory in row 0 + row 1 (in 64 MB increments)
DRB3 = Total memory in row 0 + row 1 + row 2 + row 3 (in 64 MB increments)
The row referred to by this register is defined by the DIMM chip select used. Double-sided DIMMs
use both Row 0 and Row 1 (for CS0# and CS1#), even though there is one physical slot for the
DIMM. Single-sided DIMMs use only the even row number, since single-sided DIMMs only
support CS0#. For single-sided DIMMs, the value BIOS places in the odd row should equal the
same value as what was placed in the even row field. A row is defined as 128-bit (144 bit with
ECC) wide interface consisting of two identical DIMMs.
Datasheet
49
Register Description
3.6.17
DRA—DRAM Row Attribute Register (D0:F0)
Address Offset:
Default:
Size:
Default:
70–77h
R/W
8 Bits
00h
The DRAM Row Attribute Register defines the page sizes to be used for each row of memory.
Each nibble of information in the DRA registers describes the page size and device width of a row.
For this register, a row is defined by the chip select used by the DIMM, so that a double-sided
DIMM would have both an even and an odd entry. For single-sided DIMMs, only the even side is
used.
Row 0, 1 = 70h
Row 2, 3 = 71h
Row 4, 5 = 72h
Row 6, 7 = 73h
Bits
7
Default,
Access
0b
R/W
Description
Device Width for Odd-numbered Row. This bit defines whether the DDR-SDRAM
devices populated in this row are 4 bits wide (x4) or 8 bits wide.
0 =8 bits wide.
1 =4 bits wide (x4).
Row Attribute for Odd-numbered Row. This 3-bit field defines the page size of the
corresponding row.
010 = 8 KB
6:4
000b
R/W
011 = 16 KB
100 = 32 KB
101 = 64 KB
Others = Reserved
3
0b
R/W
Device Width for Even-numbered Row. This bit defines whether the DDR-SDRAM
devices populated in this row are 4 bits wide (x4) or 8 bits wide.
0 =8 bits wide.
1 =4 bits wide (x4).
Row Attribute for Even-numbered Row. This 3-bit field defines the page size of the
corresponding row.
010 = 8 KB
2:0
000b
R/W
011 = 16 KB
100 = 32 KB
101 = 64 KB
Others = Reserved
50
Datasheet
Register Description
3.6.18
DRT—DRAM Timing Register (D0:F0)
Address Offset:
Access:
Size:
Default:
78–7Bh
R/W
32 Bits
00000010h
This register controls the timing of the DRAM Interface.
Bits
Default,
Access
31:30
00b
29
0b
R/W
Description
Reserved
Back to Back Write-Read Turn Around. This field determines the minimum number of
CMDCLK (command clocks, at 100 MHz) between Write-Read commands. It applies to
WR-RD pairs to different rows. The WR-RD pair to the same row has sufficient turnaround
due to the tWTR timing parameter. The purpose of this bit is to control the turnaround time
on the DQ bus.
0 = 3 clocks between WR-RD commands (2 turnaround clocks on DQ)
1 = 2 clocks between WR-RD commands (1 turnaround clock on DQ)
28
0b
R/W
Back to Back Read-Write Turn Around. This field determines the minimum number of
CMDCLK (command clocks, at 100 MHz) between Read-Write commands. It applies to
RD-WR pairs to any destination, in same or different rows. The purpose of this bit is to
control the turnaround time on the DQ bus.
0 = 5 clocks between RD-WR commands (2 turnaround clocks on DQ)
1 = 4 clocks between RD-WR commands (1 turnaround clock on DQ)
27
26:24
23:11
0b
R/W
000b
R/W
00000b
Back to Back Read Turn Around. This field determines the minimum number of
CMDCLK (command clocks, at 100 MHz) between two reads destined to different rows.
The purpose of this bit is to control the turnaround time on the DQ bus.
0 = 4 clocks between RD commands to different rows (2 turnaround clocks on DQ)
1 = 3 clocks between RD commands to different rows (1 turnaround clock on DQ)
Read Delay (tRD). This field controls the number of 100 MHz clocks elapsed from the
Read Command latched on the system bus until the returned data is set to be driven on
the system bus. The following tRD values are supported.
000 = 7 clocks
001 = 6 clocks
010 = 5 clocks
Others = Reserved
Reserved
Activate to Precharge delay (tRAS). This bit controls the number of DRAM clocks for
tRAS.
10:9
00b
00 = 7 Clocks
R/W
01 = 6 Clocks
10 = 5 Clocks
11 = Reserved
8:6
0000b
Reserved
CAS# Latency (tCL). The number of clocks between the rising edge used by DRAM to
sample the Read Command and the rising edge used by the DRAM to drive read data.
5:4
01b
00 = 2.5 Clocks
R/W
01 = 2 Clocks
10 = 1.5 Clocks
11 = Reserved
Datasheet
51
Register Description
Bits
3
2
1
0
3.6.19
Default,
Access
0b
R/W
0b
0b
R/W
0b
R/W
Description
Write RAS# to CAS# Delay (tRCD). This bit controls the number of clocks inserted
between a row activate command and write command to that row.
0 = 3 DRAM Clocks
1 = 2 DRAM Clocks
Reserved
Read RAS# to CAS# Delay (tRCD). This bit controls the number of clocks inserted
between a row activate command and a read command to that row.
0 = 3 DRAM Clocks
1 = 2 DRAM Clocks
DRAM RAS# Precharge (tRP). This bit controls the number of clocks that are inserted
between a row precharge command and an activate command to the same row.
0 = 3 DRAM Clocks
1 = 2 DRAM Clocks
DRC—DRAM Controller Mode Register (D0:F0)
Address Offset:
Default:
Access:
Size:
7C–7Fh
0044_0009h
R/W
32 Bits
This register controls the mode of the DRAM Controller.
Bits
Default,
Access
31:30
00b
29
28:22
0b
R/W
00h
Description
Reserved
Initialization Complete (IC). This bit is used for communicating the software state
between the memory controller and the BIOS. It indicates that the DRAM interface has
been initialized. This bit must be set and the refresh mode select (DRC[9:8]) must be set
to enable refresh. If this bit is clear, no refresh will occur regardless of the RMS (DRC[9:8])
setting.
Reserved
DRAM Data Integrity Mode (DDIM). These bits select one of two DRAM data integrity
modes.
21:20
R/W
00 =Disable. No ECC correction is performed and no errors are flagged in DRAM_FERR
or DRAM_NERR.
01 =Reserved
10 =Error checking, using chip-kill, with correction
11 =Reserved
19:18
01b
Reserved
17
0b
Reserved
0b
Command Per Clock – Address/Control Assertion Rule (CPC). This bit defines the
number of clock cycles the MA, RAS#, CAS#, WE# are asserted.
16
15:10
52
00b
R/W
0 = 2n rule: (MA [12:0]}, RAS#, CAS#, WE# asserted for 2 clock cycles)
1 = 1n Rule (MA [12:0]}, RAS#, CAS#, WE# asserted for 1 clock cycle)
00b
Reserved
Datasheet
Register Description
Bits
Default,
Access
Description
Refresh Mode Select (RMS). This field determines whether refresh is enabled and, if so,
at what rate refreshes will be executed.
9:8
00b
00 = Refresh Disabled
R/W
01 = Refresh Enabled. Refresh interval 15.6 µsec
10 = Refresh Enabled. Refresh interval 7.8 µsec
11 = Refresh Enabled. Refresh interval 64 µsec
7
0b
Reserved
Mode Select (SMS). These bits select the special operational mode of the DRAM
interface. The special modes are intended for initialization at power up.
000 =Self refresh. In this mode CKEs are deasserted and the DRAMS are in self-refresh
mode. All other combinations of SMS bits result in assertion of one or more CKEs,
except when the device is in C3 or S1 state, where all devices are in self-refresh,
without regard to the value in SMS.
001 =NOP Command Enable. All processor cycles to DRAM result in a NOP command on
the DRAM interface.
010 =All Banks Precharge Enable. All processor cycles to DRAM result in an “all banks
precharge” command on the DRAM interface.
6:4
000b
R/W
011 =Mode register Set Enable. All processor cycles to DRAM result in a “mode register”
set command on the DRAM interface. Host address lines are mapped to SDRAM
address lines in order to specify the command sent. Host address lines 15:3 are
typically mapped to MA[12:0].
100 = Extended Mode Register Set Enable. All processor cycles to SDRAM result in an
“extended mode register set” command on the DRAM interface (DDR only). Host
address lines are mapped to SDRAM address lines in order to specify the command
sent. Host address lines 15:3 are typically mapped to MA[12:0].
101 =Reserved.
110 =CBR Refresh Enable. In this mode all processor cycles to DRAM result in a CBR
cycle on the SDRAM interface
111 =Normal operation
3:0
3.6.20
0000b
Reserved
CLOCK_DIS—CK/CK# Disable Register (D0:F0)
Address Offset:
Default:
Sticky:
Access:
Size:
8Ch
00h
No
R/W
8 Bits
This register controls the DDR clocks for each DIMM.
Bit
Default,
Access
7:4
0h
3:0
Datasheet
0h
R/W
Description
Reserved
CK/CK# Disable. Each bit of this four bit field corresponds to a pair of ck/ck# pins on
both channels. Bit 0 corresponds to CK0 and CK0# while bit 3 corresponds to CK3 and
CK3#.
1 = These bits turn off the corresponding CK/CK# pair. CK is driven low and CK# is
driven high. This feature is intended to reduce EMI due to clocks toggling to DIMMs
which are not populated.
53
Register Description
3.6.21
SMRAM—System Management RAM Control Register
(D0:F0)
Address Offset:
Default:
Access:
Size:
9Dh
02h
RO, R/W, L
8 Bits
The SMRAMC Register controls how accesses to Compatible and Extended SMRAM spaces are
treated. The Open, Close, and Lock bits function only when G_SMRAME bit is set to 1. The Open
bit must be reset before the Lock bit is set.
Bits
Default,
Access
7
0b
6
5
4
3
2:0
54
0b
R/W
0b
R/W
0b
R/W
0b
L
010b
RO
Description
Reserved
SMM Space Open (D_OPEN). When D_OPEN=1 and D_LCK=0, the SMM space DRAM
is made visible even when SMM decode is not active. This is intended to help BIOS
initialize SMM space. Software should ensure that D_OPEN=1 and D_CLS=1 are not set
at the same time.
SMM Space Closed (D_CLS). When D_CLS = 1 SMM space DRAM is not accessible to
data references, even if SMM decode is active. Code references may still access SMM
space DRAM. This will allow SMM software to reference through SMM space to update
the display even when SMM is mapped over the VGA range. Software should ensure that
D_OPEN=1 and D_CLS=1 are not set at the same time. Note that the D_CLS bit only
applies to Compatible SMM space.
SMM Space Locked (D_LCK). When D_LCK is set to 1, D_OPEN is reset to 0 and
D_LCK, D_OPEN, C_BASE_SEG, H_SMRAM_EN, TSEG_SZ and TSEG_EN become
read only. D_LCK can be set to 1 via a normal configuration space write but can only be
cleared by a Full Reset. The combination of D_LCK and D_OPEN provide convenience
and security. The BIOS can use the D_OPEN function to initialize SMM space and then
use D_LCK to “lock down” SMM space in the future so that no application software (or the
BIOS itself) can violate the integrity of SMM space, even if the program has knowledge of
the D_OPEN function.
Global SMRAM Enable (G_SMRAME). If set to 1, then Compatible SMRAM functions
are enabled, providing 128 KB of DRAM accessible at the A0000h address while in SMM
(ADS# with SMM decode). To enable Extended SMRAM function this bit must be set to 1.
Refer to Section 4.3, “SMM Space” on page 4-117 for more details regarding SMM. Once
D_LCK is set, this bit becomes read only.
Compatible SMM Space Base Segment (C_BASE_SEG). This field indicates the
location of SMM space. SMM DRAM is not remapped. It is simply made visible if the
conditions are right to access SMM space, otherwise the access is forwarded to the hub
interface. Since the MCH supports only the SMM space between A0000h and BFFFFh,
this field is hardwired to 010.
Datasheet
Register Description
3.6.22
ESMRAMC—Extended System Management RAM Control
Register (D0:F0)
Address Offset:
Default:
Access:
Size:
9Eh
38h
R/W, R/WC, R/W/L
8 Bits
The Extended SMRAM Register controls the configuration of Extended SMRAM space. The
Extended SMRAM (E_SMRAM) memory provides a write-back cacheable SMRAM memory
space that is above 1 MB.
Bits
7
Default,
Access
0b
R/W/L
Description
Enable High SMRAM (H_SMRAME). Controls the SMM memory space location
(i.e., above 1 MB or below 1 MB) When G_SMRAME is 1 and H_SMRAME is set to 1, the
high SMRAM memory space is enabled. SMRAM accesses within the range 0FFEA0000h
to 0FFEAFFFFh are remapped to DRAM addresses within the range 000A0000h to
000BFFFFh. Once D_LCK has been set, this bit becomes read only.
Invalid SMRAM Access (E_SMERR).
6
0b
R/WC
1 =This bit is set when the processor has accessed the defined memory ranges in
Extended SMRAM (High Memory and T-segment) while not in SMM space and with
the D-OPEN bit = 0. It is software’s responsibility to clear this bit.
Note: Software must write a 1 to this bit to clear it.
5:3
2:1
111b
00b
R/W
Reserved
TSEG Size (TSEG_SZ). Selects the size of the TSEG memory block if enabled. Memory
from the top of main memory space (TOLM - TSEG_SZ) to TOLM is partitioned away so
that it may only be accessed by the processor interface and only then when the SMM bit is
set in the request packet. Non-SMM accesses to this memory region are sent to the hub
interface when the TSEG memory block is enabled.
EncodingDescription
00 (TOLM–128 KB) to TOLM
01 (TOLM–256 KB) to TOLM
10 (TOLM–512 KB) to TOLM
11 (TOLM–-1 MB) to TOLM
0
Datasheet
0b
R/W/L
TSEG Enable (TSEG_EN). Enables SMRAM memory for Extended SMRAM space only.
When G_SMRAME =1 and TSEG_EN = 1, the TSEG is enabled to appear in the
appropriate physical address space. Note that once D_LCK is set, this bit becomes read
only.
55
Register Description
3.6.23
TOLM—Top of Low Memory Register (D0:F0)
Address Offset:
Default:
Access:
Size:
C4–C5h
0800h
R/W
16 Bits
This register contains the maximum address below 4 GB that should be treated as main memory,
and is defined on a 128-MB boundary. Normally, it is set below the areas configured for the hub
interface and PCI memory. Note that the memory address found in DRB7 reflects the top of total
memory. In the event that the total of PCI space to main memory combined is less than 4 GB, these
two registers will be set the same.
Bits
15:11
10:0
3.6.24
Default,
Access
00001b
Description
R/W
Top of Low Memory (TOLM). This register contains the address that corresponds to bits
31:27 of the maximum DRAM memory address that lies below 4 GB.
000h
Reserved
REMAPBASE—Remap Base Address Register (D0:F0)
Address Offset:
Default:
Access:
Size:
C6–C7h
03FFh
R/W
16 Bits
This register specifies the lower boundary of the remap window. Refer to Section 4.4 for more
information.
Bits
Default,
Access
15:10
000000b
9:0
3FFh
R/W
Description
Reserved
Remap Base Address [35:26]. The value in this register defines the lower boundary of
the remap window. The remap window is inclusive of this address. A[25:0] of the remap
Base Address are assumed to be 0s. Thus, the bottom of the defined memory range will
be aligned to a 64-MB boundary.
When the value in this register is greater than the value programmed into the Remap Limit
Register, the Remap window is disabled. This field defaults to FFh.
56
Datasheet
Register Description
3.6.25
REMAPLIMIT—Remap Limit Address Register (D0:F0)
Address Offset:
Default:
Access:
Size:
C8–C9h
0000h
R/W
16 Bits
This register specifies the upper boundary of the remap window
Bits
Default,
Access
15:10
000000b
9:0
000h
R/W
Description
Reserved
Remap Base Address [35:26]. The value in this register defines the upper boundary of
the remap window. The remap window is inclusive of this address. A[25:0] of the Remap
Limit Address are assumed to be Fs. Thus, the top of the defined memory range will be
one less than a 64-MB boundary.
When the value in this register is less than the value programmed into the Remap Base
Register, the remap window is disabled.
3.6.26
SKPD—Scratchpad Data Register (D0:F0)
Address Offset:
Default:
Access:
Size:
DE–DFh
0000h
R/W
16 Bits
This register contains bits that can be used for general purpose storage.
Bits
15:0
Datasheet
Default,
Access
0000h
R/W
Description
Scratchpad (SCRTCH). These bits are R/W storage bits that have no effect on the MCH
functionality.
57
Register Description
3.6.27
DVNP—Device Not Present Register (D0:F0)
Address Offset:
Default:
Access:
Size:
E0–E1h
1D1Fh
R/W
16 Bits
This register is used to control whether the Function 1 portions of the PCI configuration space for
Devices 0, 2, 3, and 4 is visible to software. If a device’s Function 1 is disabled, that device will
appear to have only 1 function (Function 0).
Bits
Default,
Access
15:5
0E8h
4
3
2
1
0
58
1b
R/W
1b
R/W
1b
R/W
1b
1b
R/W
Description
Reserved
Device 4, Function 1 Present.
0 = Present
1 = Not present
Device 3, Function 1 Present.
0 = Present
1 = Not present
Device 2, Function 1 Present.
0 = Present
1 = Not present
Reserved
Device 0, Function 1 Present.
0 = Present
1 = Not present
Datasheet
Register Description
3.7
DRAM Controller Error Reporting Registers
(Device 0, Function 1)
This section describes the DRAM Controller registers for Device 0 (D0), Function 1 (F1).
Table 3-4 provides the register address map for this device, function.
Warning:
Address locations that are not listed in the table are considered reserved register locations. Writes
to “Reserved” registers may cause system failure. Reads to “Reserved” registers may return a nonzero value.
Table 3-4. DRAM Controller Register Map (HI_A—D0:F1)
Offset
Datasheet
Mnemonic
Register Name
Default
Type
00–01h
VID
Vendor ID
8086h
RO
02–03h
DID
Device ID
2541h
RO
04–05h
PCICMD
PCI Command
0000h
R/W
06–07h
PCISTS
PCI Status
0000h
R/WC
08h
RID
Revision ID
02h
RO
0Ah
SUBC
Sub Class Code
00h
RO
0Bh
BCC
Base Class Code
FFh
RO
0Dh
MLT
Master Latency Timer
00h
—
0Eh
HDR
Header Type
00h or 80h
RO
2C–2Dh
SVID
Subsystem Vendor Identification
0000h
R/WO
2E–2Fh
SID
Subsystem Identification
0000h
R/WO
40–43h
FERR_GLOBAL
Global Error
00000000h
R/WC
44–47h
NERR_GLOBAL
Global Error
00000000h
R/WC
50h
HIA_FERR
Hub Interface_A First Error
00h
R/WC
52h
HIA_NERR
Hub Interface_A Next Error
00h
R/WC
58h
SCICMD_HIA
SCI Command
00h
R/W
5Ah
SMICMD_HIA
SMI Command
00h
R/W
5Ch
SERRCMD_HIA
SERR Command
00h
R/W
60h
SYSBUS_FERR
System Bus First Error
00h
R/WC
62h
SYSBUS_NERR
System Bus Next Error
00h
R/WC
68h
SCICMD_SYSBUS
SCI Command
00h
R/W
6Ah
SMICMD_SYSBUS
SMI Command
00h
R/W
6Ch
SERRCMD_SYSBUS
SERR Command
00h
R/W
80h
DRAM_FERR
DRAM First Error
00h
R/WC
82h
DRAM_NERR
DRAM Next Error
00h
R/WC
88h
SCICMD_DRAM
SCI Command
00h
R/W
8Ah
SMICMD_DRAM
SMI Command
00h
R/W
8Ch
SERRCMD_DRAM
SERR Command
00h
R/W
59
Register Description
Table 3-4. DRAM Controller Register Map (HI_A—D0:F1) (Continued)
3.7.1
Offset
Mnemonic
A0–A3h
DRAM_CELOG_ADD
B0–B3h
DRAM_UELOG_ADD
D0–D1h
DRAM_CELOG_
SYNDROME
Register Name
Default
Type
DRAM Firs Correctable Memory
Error Address
00000000h
RO
DRAM Firs Uncorrectable Memory
Error Address
00000000h
RO
0000h
RO
DRAM First Correctable Memory
Error
VID—Vendor Identification Register (D0:F1)
Address Offset:
Default:
Sticky
Access:
Size:
00–01h
8086h
No
RO
16 Bits
The VID Register contains the vendor identification number. This 16-bit register combined with
the Device Identification Register uniquely identify any PCI device.
Bits
15:0
3.7.2
Default,
Access
8086h
RO
Description
Vendor Identification Device (VID). This register field contains the PCI standard
identification for Intel (VID=8086h).
DID—Device Identification Register (D0:F1)
Address Offset:
Default:
Sticky:
Access:
Size:
02–03h
2541h
No
RO
16 Bits
This 16-bit register combined with the Vendor Identification register uniquely identifies any PCI
device.
Bits
15:0
60
Default,
Access
2541h
RO
Description
Device Identification Number (DID). This is a 16-bit value assigned to the MCH Host-HI
Bridge.
Datasheet
Register Description
3.7.3
PCICMD—PCI Command Register (D0:F1)
Address Offset:
Default:
Sticky:
Access:
Size:
04-05h
0000h
No
R/W
16 Bits
Since MCH Device 0 does not physically reside on a physical PCI bus portions of this register are
not implemented.
Bits
Default,
Access
15:9
00h
Description
Reserved
SERR Enable (SERRE). This bit is a global enable bit for Device 0 SERR generations.
8
7:0
3.7.4
0b
0 =Disable. SERR is not generated by the MCH for Device 0.
R/W
1 =Enable. The MCH is enabled to generate an SERR for specific Device 0 error
conditions that are individually enabled in the SERRCMD register.
00h
Reserved
PCISTS—PCI Status Register (D0:F1)
Address Offset:
Default:
Sticky:
Access:
Size:
06-07h
0000h
No
R/WC
16 Bits
PCISTS is a 16-bit status register that reports the occurrence of error events on Device 0s PCI
interface. Since MCH Device 0 does not physically reside on a PCI bus, this register is not
implemented.
Bits
Default,
Access
15
0b
Description
Reserved
Signaled System Error (SSE).
14
0b
R/WC
0 = SERR Not generated by MCH Device 0
1 = MCH Device 0 generated a SERR.
Note: Software sets this bit to 0 by writing a 1 to it.
13:0
Datasheet
0000h
Reserved
61
Register Description
3.7.5
RID—Revision Identification Register (D0:F1)
Address Offset:
Default:
Sticky:
Access:
Size:
08h
See table below
No
RO
8 Bits
This register contains the revision number of the MCH Device 0.
Bits
7:0
Default,
Access
Description
02h
Revision Identification Number (RID). This is an 8-bit value that indicates the revision
identification number for the MCH Device 0. This number should always be the same as
the RID for device 0, function 0.
RO
02h = A2 stepping
3.7.6
SUBC—Sub-Class Code Register (D0:F1)
Address Offset:
Default:
Sticky:
Access:
Size:
0Ah
00h
No
RO
8 Bits
This register contains the Sub-Class Code for the MCH Device 0, Function 1.
Bits
7:0
62
Default,
Access
00h
RO
Description
Sub-Class Code (SUBC). This is an 8-bit value that indicates sub-class code for the
MCH Device 0, Function 1. The code is 00h.
Datasheet
Register Description
3.7.7
BCC—Base Class Code Register (D0:F1)
Address Offset:
Default:
Sticky:
Access:
Size:
0Bh
FFh
No
RO
8 Bits
This register contains the Base Class Code of the MCH Device 0, Function 1.
Bits
7:0
3.7.8
Default,
Access
FFh
RO
Description
Base Class Code (BASEC). This is an 8-bit value that indicates the Base Class Code for
the MCH.
FFh =Non-defined device. Since this function is used for error conditions, it does not fall
into any other class.
MLT—Master Latency Timer Register (D0:F1)
Address Offset:
Default:
Sticky:
Access:
Size:
0Dh
00h
No
Reserved
8 Bits
Device 0 in the MCH is not a PCI master. Therefore, this register is not implemented.
Datasheet
Bits
Default,
Access
7:0
00h
Description
Reserved
63
Register Description
3.7.9
HDR—Header Type (D0:F1)
Address Offset:
Default:
Sticky:
Access:
Size:
0Eh
00h or 80h
No
RO
8 Bits
This register identifies the header layout of the configuration space. It is hardwired to 80h to
indicate a multi-function device.
Bits
7:0
Default,
Access
00h or
80h
RO
64
Description
PCI Header (HDR). This read only field always returns 00h or 80h (value depends on
Device Not Present Register) to indicate that the MCH is a multi-function device with
standard header layout.
Datasheet
Register Description
3.7.10
SVID—Subsystem Vendor Identification Register (D0:F1)
Address Offset:
Default:
Sticky:
Access:
Size:
2Ch
0000h
No
R/WO
16 Bits
This value is used to identify the vendor of the subsystem.
Bits
15:0
3.7.11
Default,
Access
0000h
R/WO
Description
Subsystem Vendor ID (SUBVID). This field should be programmed during boot-up to
indicate the vendor of the system board. After it has been written once, it becomes read
only.
SID—Subsystem Identification Register (D0:F1)
Address Offset:
Default:
Sticky:
Access:
Size:
2Eh
0000h
No
R/WO
16 Bits
This value is used to identify a particular subsystem.
Bits
15:0
Datasheet
Default,
Access
0000h
R/WO
Description
Subsystem ID (SUBID). This field should be programmed during BIOS initialization. After
it has been written once, it becomes read only.
65
Register Description
3.7.12
FERR_GLOBAL—Global Error Register (D0:F1)
Address Offset:
Default:
Sticky:
Access:
Size:
40–43h
0000_0000h
Yes
R/WC
32 Bits
This register is used to report various error conditions. An SERR is generated on a 0-to-1 transition
of any of these flags (if enabled by the ERRCMD and PCICMD registers). These bits are set
regardless of whether or not the SERR is enabled and generated.
This register stores the FIRST global error. Any future errors (NEXT errors) will be set in the
NERR_Global Register. No further error bits in this register will be set until the existing error bit is
cleared.
Note:
To prevent the same error from being logged twice in FERR_GLOBAL and NERR_GLOBAL, a
FERR_GLOBAL bit being set blocks the respective bit in the NERR_GLOBAL Register from
being set. In addition, bits [18:16] are grouped such that if any of these bits are set in the
FERR_GLOBAL Register, none of the bits [18:16] can be set in the NERR_GLOBAL Register.
For example, if HI_A causes its respective FERR_GLOBAL bit to be set, any subsequent DDR,
FSB, or HI_A error will not be logged in the NERR_GLOBAL Register. Each of these three bits
are part of Device 0 status and having any one of them set in FERR_GLOBAL represents a
"Device 0 First Error" occurred. This implementation blocks logging in NERR_GLOBAL of any
subsequent "Device 0" errors, and allows only logging of subsequent errors that are from other
devices.
Note:
Software must write a 1 to clear bits that are set.
Bits
Default,
Access
31:19
0000h
18
17
16
15:5
4
3
2
1:0
66
0b
R/WC
0b
R/WC
0b
R/WC
000h
0b
R/WC
0b
R/WC
0b
R/WC
00b
Description
Reserved
DRAM Interface Error Detected.
0 = No DRAM interface error.
1 = MCH detected an error on the DRAM interface.
HI_A Error Detected.
0 = No HI_A interface error.
1 = MCH detected an error on the HI_A.
System Bus Error Detected.
0 = No system bus interface error.
1 = MCH detected an error on the System Bus.
Reserved
HI_D Error Detected.
0 = No HI_D interface error.
1 = MCH detected an error on HI_D.
HI_C Error Detected.
0 = No HI_C interface error.
1 = MCH detected an error on HI_C.
HI_B Error Detected.
0 = No HI_B interface error.
1 = MCH detected an error on HI_B.
Reserved
Datasheet
Register Description
3.7.13
NERR_GLOBAL—Global Error Register (D0:F1)
Address Offset:
Default:
Sticky:
Access:
Size:
44–47h
0000_0000h
Yes
R/WC
32 Bits
The FIRST global error will be stored in FERR_GLOBAL. This register stores all future global
errors. Multiple bits in this register may be set.
Note:
To prevent the same error from being logged twice in FERR_GLOBAL and NERR_GLOBAL, a
FERR_GLOBAL bit being set blocks the respective bit in the NERR_GLOBAL Register from
being set. In addition, bits [18:16] are grouped such that if any of these bits are set in the
FERR_GLOBAL Register, none of the bits [18:16] can be set in the NERR_GLOBAL Register.
For example, if HI_A causes its respective FERR_GLOBAL bit to be set, any subsequent DDR,
FSB, or HI_A error will not be logged in the NERR_GLOBAL Register. Each of these three bits
are part of Device 0 status and having any one of them set in FERR_GLOBAL represents a
"Device 0 First Error" occurred. This implementation blocks logging in NERR_GLOBAL of any
subsequent "Device 0" errors, and allows only logging of subsequent errors that are from other
devices.
Note:
Software must write a 1 to clear bits that are set.
Bits
Default,
Access
31:19
0000h
18
17
16
15:5
4
3
2
1:0
Datasheet
0b
R/WC
0b
R/WC
0b
R/WC
000h
0b
R/WC
0b
R/WC
0b
R/WC
00b
Description
Reserved
DRAM Interface Error Detected.
0 = No DRAM interface error detected.
1 = The MCH has detected an error on the DRAM interface.
HI_A Error Detected.
0 = No HI_A interface error detected.
1 = The MCH has detected an error on the HI_A.
System Bus Error Detected.
0 = No system bus interface error detected.
1 = The MCH has detected an error on the System Bus.
Reserved
HI_D Error Detected.
0 = No HI_D interface error detected.
1 = The MCH has detected an error on HI_D.
HI_C Error Detected.
0 = No HI_C interface error detected.
1 = The MCH has detected an error on HI_C.
HI_B Error Detected.
0 = No HI_B interface error detected.
1 = The MCH has detected an error on HI_B.
Reserved
67
Register Description
3.7.14
HIA_FERR—Hub Interface_A First Error Register (D0:F1)
Address Offset:
Default:
Sticky:
Access:
Size:
50h
00h
Yes
R/WC
8 Bits
This register stores the first error related to the HI_A. Only 1 error bit will be set in this register.
Any future errors (NEXT errors) will be set the HIA_NERR Register. No further error bits in this
register will be set until the existing error bit is cleared.
Note:
Software must write a 1 to clear bits that are set.
Bits
Default,
Access
7
0b
6
5
4
3:1
0
68
0b
R/WC
0b
0b
R/WC
000b
0b
R/WC
Description
Reserved
HI_A Target Abort.
0 = No Target Abort on MCH originated HI_A cycle detected.
1 = MCH detected that an MCH originated HI_A cycle was terminated with a Target
Abort.
Reserved
HI_A Data Parity Error Detected.
0 = No data parity error detected.
1 = MCH detected a parity error on a HI_A data transfer.
Reserved
HI_A Address/Command Error Detected.
0 = No address or command parity error detected.
1 = MCH detected a parity error on a HI_A address or command.
Datasheet
Register Description
3.7.15
HIA_NERR—Hub Interface_A Next Error Register (D0:F1)
Address Offset:
Default:
Sticky:
Access:
Size:
52h
00h
Yes
R/WC
8 Bits
The first HI_A error will be stored in the HIA_FERR Register. This register stores all future HI_A
errors. Multiple bits in this register may be set.
Note:
Software must write a 1 to clear bits that are set.
Bits
Default,
Access
7
0b
6
5
4
3:1
0
Datasheet
0b
R/WC
0b
Description
Reserved
HI_A Target Abort.
0 = No Target Abort on MCH originated HI_A cycle terminated.
1 = MCH originated HI_A cycle was terminated with a Target Abort.
Reserved
R/WC
HI_A Data Parity Error Detected.
0 = No data parity error detected.
1 = Parity error on a HI_A data transfer.
000b
Reserved
0b
0b
R/WC
HI_A Data Address/Command Error Detected.
0 = No address or command parity error detected.
1 = Parity error on a HI_A address or command.
69
Register Description
3.7.16
SCICMD_HIA—SCI Command Register (D0:F1)
Address Offset:
Default:
Sticky:
Access:
Size:
58h
00h
No
R/W
8 Bits
This register determines whether SCI will be generated when the associated flag is set in the
HIA_FERR or HIA_NERR Register. When an error flag is set in the HIA_FERR or HIA_NERR
Register, it can generate an SERR, SMI, or SCI when enabled in the SERRCMD, SMICMD, or
SCICMD Registers, respectively. Only one message type can be enabled.
Bits
Default,
Access
7
0b
6
5
4
3:1
0
70
0b
R/W
0b
0b
Description
Reserved
SCI on HI_A Target Abort Enable.
0 = No SCI generation
1 = Generate SCI if bit 6 is set in HIA_FERR or HIA_NERR
Reserved
SCI on HI_A Data Parity Error Detected Enable.
R/W
0 = No SCI generation
1 = Generate SCI if bit 4 is set in HIA_FERR or HIA_NERR
000b
Reserved
0b
R/W
SCI on HI_A Data Address/Comment Error Detected Enable.
0 = No SCI generation
1 = Generate SCI if bit 0 is set in HIA_FERR or HIA_NERR
Datasheet
Register Description
3.7.17
SMICMD_HIA—SMI Command Register (D0:F1)
Address Offset:
Default:
Sticky:
Access:
Size:
5Ah
00h
No
R/W
8 Bits
This register determine whether SMI will be generated when the associated flag is set in either the
HIA_FERR or HIA_NERR Register. When an error flag is set in the HIA_FERR or HIA_NERR
Register, it can generate an SERR, SMI, or SCI when enabled in the SERRCMD, SMICMD, or
SCICMD Registers, respectively. Only one message type can be enabled.
Bits
Default,
Access
7
0b
6
5
4
3:1
0
Datasheet
0b
R/W
0b
0b
R/W
000b
0b
R/W
Description
Reserved
SMI on HI_A Target Abort Enable.
0 = No SMI generation
1 = Generate SMI if bit 6 is set in HIA_FERR or HIA_NERR
Reserved
SMI on HI_A Data Parity Error Detected Enable.
0 = No SMI generation
1 = Generate SMI if bit 4 is set in HIA_FERR or HIA_NERR
Reserved
SMI on HI_A Data Address/Comment Error Detected Enable.
0 = No SMI generation
1 = Generate SMI if bit 0 is set in HIA_FERR or HIA_NERR
71
Register Description
3.7.18
SERRCMD_HIA—SERR Command Register (D0:F1)
Address Offset:
Default:
Sticky:
Access:
Size:
5Ch
00h
No
R/W
8 Bits
This register determine whether SERR will be generated when the associated flag is set in either
the HIA_FERR or HIA_NERR Register. When an error flag is set in the HIA_FERR or
HIA_NERR Register, it can generate an SERR, SMI, or SCI when enabled in the SERRCMD,
SMICMD, or SCICMD Registers, respectively. Only one message type can be enabled.
Bits
Default,
Access
7
0b
6
5
4
3:1
0
72
0b
R/W
0b
0b
R/W
000b
0b
R/W
Description
Reserved
SERR on HI_A Target Abort Enable.
0 = No SERR generation
1 = Generate SERR if bit 6 is set in HIA_FERR or HIA_NERR
Reserved
SERR on HI_A Data Parity Error Detected Enable.
0 = No SERR generation
1 = Generate SERR if bit 4 is set in HIA_FERR or HIA_NERR
Reserved
SEER on HI_A Data Address/Comment Error Detected Enable.
0 = No SERR generation
1 = Generate SERR if bit 0 is set in HIA_FERR or HIA_NERR
Datasheet
Register Description
3.7.19
SYSBUS_FERR—System Bus First Error Register (D0:F1)
Address Offset:
Default:
Sticky:
Access:
Size:
60h
00h
Yes
R/WC
8 Bits
This register stores the FIRST error related to the system bus interface. Any future errors (NEXT
errors) will be set in the SYSBUS_NERR Register. No further error bits in this register will be set
until the existing error bit is cleared.
Note:
Software must write a 1 to clear bits that are set.
Bits
7
Default,
Access
0b
R/WC
Description
System Bus BINIT# Detected.
0 = No system bus BINT# detected.
1 = This bit is set on an electrical high-to-low transition (0-to-1) of BINIT#.
System Bus XERR# Detected.
6
5
4
3
2
1
0b
R/WC
0b
R/WC
0b
R/WC
0b
R/WC
0b
R/WC
0b
R/WC
0 = No system bus XERR# detected.
1 = This bit is set on an electrical high-to-low transition (0 to 1) of XERR# on the system
bus.
Non-DRAM Lock Error (NDLOCK).
0 = No DRAM lock error detected.
1 = MCH detected a lock operation to memory space that did not map into DRAM.
System Bus Address Above TOM (SBATOM).
0 = No system bus address above TOM detected.
1 = MCH detected an address above DRB7, which is the Top of Memory and above 4 GB.
System Bus Data Parity Error (SBDPAR).
0 = No system bus data parity error detected.
1 = The MCH has detected a data parity error on the system bus.
System Bus Address Strobe Glitch Detected (SBAGL).
0 = No system bus address strobe glitch detected.
1 = The MCH has detected a glitch on one of the system bus address strobes.
System Bus Data Strobe Glitch Detected (SBDGL).
0 = No system bus data strobe glitch detected.
1 = The MCH has detected a glitch on one of the system bus data strobes.
System Bus Request/Address Parity Error (SBRPAR).
0
Datasheet
0b
R/WC
0 = No system bus request/address parity error detected.
1 = MCH detected a parity error on either the address or request signals of the system
bus.
73
Register Description
3.7.20
SYSBUS_NERR—System Bus Next Error Register (D0:F1)
Address Offset:
Default:
Sticky:
Access:
Size:
62h
00h
Yes
R/WC
8 Bits
The FIRST system bus error will be stored in the SYSBUS_FERR Register. This register stores all
future system bus errors. Multiple bits in this register may be set.
Note:
Software must write a 1 to clear bits that are set.
Bits
7
Default,
Access
0b
R/WC
Description
System Bus BINIT# Detected.
0 = No system bus BINIT# detected.
1 = This bit is set on an electrical high-to-low transition (0 to 1) of BINIT#.
System Bus XERR# Detected.
6
0b
R/WC
0 = No system bus XERR# detected.
1 = This bit is set on an electrical high-to-low transition (0 to 1) of XERR# on the system
bus.
Non-DRAM Lock Error (NDLOCK).
5
4
3
2
1
0b
R/WC
0b
R/WC
0b
R/WC
0b
R/WC
0b
R/WC
0 = No non-DRAM lock error detected.
1 = The MCH has detected a lock operation to memory space that did not map into
DRAM.
System Bus Address Above TOM (SBATOM).
0 = No system bus address above TOM detected.
1 = MCH detected an address above DRB7, which is the Top of Memory and above 4 GB.
System Bus Data Parity Error (SBDPAR).
0 = No system bus data parity error detected.
1 = MCH detected a data parity error on the system bus.
System Bus Address Strobe Glitch Detected (SBAGL).
0 = No system bus address strobe glitch detected.
1 = MCH detected a glitch on one of the system bus address strobes.
System Bus Data Strobe Glitch Detected (SBDGL).
0 = No System Bus Data Strobe Glitch detected.
1 = MCH detected a glitch on one of the system bus data strobes.
System Bus Request/Address Parity Error (SBRPAR).
0
74
0b
R/WC
0 = No system bus request/address parity error detected.
1 = MCH detected a parity error on either the address or request signals of the system
bus.
Datasheet
Register Description
3.7.21
SCICMD_SYSBUS—SCI Command Register (D0:F1)
Address Offset:
Default:
Sticky:
Access:
Size:
68h
00h
No
R/W
8 Bits
This register determine whether SCI will be generated when the associated flag is set in either the
SYSBUS_FERR or SYSBUS_NERR Register. When an error flag is set in the SYSBUS_FERR or
SYSBUS_NERR Register, it can generate an SERR, SMI, or SCI when enabled in the SERRCMD,
SMICMD, or SCICMD Registers, respectively. Only one message type can be enabled.
Bits
7
6
5
4
3
2
1
0
Datasheet
Default,
Access
0b
R/W
0b
R/W
0b
R/W
0b
R/W
0b
R/W
0b
R/W
0b
R/W
0b
R/W
Description
SCI on System Bus BINIT# Detected Enable.
0 = No SCI generation
1 = Generate SCI if bit 7 is set in SYSBUS_FERR or SYSBUS_NERR
SCI on System Bus xERR# Detected Enable.
0 = No SCI generation
1 = Generate SCI if bit 6 is set in SYSBUS_FERR or SYSBUS_NERR
SCI on Non-DRAM Lock Error Enable.
0 = No SCI generation
1 = Generate SCI if bit 5 is set in SYSBUS_FERR or SYSBUS_NERR
SCI on System Bus Address Above TOM Enable.
0 = No SCI generation
1 = Generate SCI if bit 4 is set in SYSBUS_FERR or SYSBUS_NERR
SCI on System Bus Data Parity Error Enable.
0 = No SCI generation
1 = Generate SCI if bit 3 is set in SYSBUS_FERR or SYSBUS_NERR
SCI on System Bus Address Strobe Glitch Detected Enable.
0 = No SCI generation
1 = Generate SCI if bit 2 is set in SYSBUS_FERR or SYSBUS_NERR
SCI on System Bus Data Strobe Glitch Detected Enable.
0 = No SCI generation
1 = Generate SCI if bit 1 is set in SYSBUS_FERR or SYSBUS_NERR
SCI on System Bus Request/Address Parity Error Enable.
0 = No SCI generation
1 = Generate SCI if bit 0 is set in SYSBUS_FERR or SYSBUS_NERR
75
Register Description
3.7.22
SMICMD_SYSBUS—SMI Command Register (D0:F1)
Address Offset:
Default:
Sticky:
Access:
Size:
6Ah
00h
No
R/W
8 Bits
This register determines whether SMI will be generated when the associated flag is set in either the
SYSBUS_FERR or SYSBUS_NERR Register. When an error flag is set in the SYSBUS_FERR or
SYSBUS_NERR Register, it can generate an SERR, SMI, or SCI when enabled in the SERRCMD,
SMICMD, or SCICMD Registers, respectively. Only one message type can be enabled.
Bits
7
6
5
4
3
2
1
0
76
Default,
Access
0b
R/W
0b
R/W
0b
R/W
0b
R/W
0b
R/W
0b
R/W
0b
R/W
0b
R/W
Description
SMI on System Bus BINIT# Detected Enable.
0 = No SMI generation
1 = Generate SMI if bit 7 is set in SYSBUS_FERR or SYSBUS_NERR
SMI on System Bus xERR# Detected Enable.
0 = No SMI generation
1 = Generate SMI if bit 6 is set in SYSBUS_FERR or SYSBUS_NERR
SMI on Non-DRAM Lock Error Enable.
0 = No SMI generation
1 = Generate SMI if bit 5 is set in SYSBUS_FERR or SYSBUS_NERR
SMI on System Bus Address Above TOM Enable.
0 = No SMI generation
1 = Generate SMI if bit 4 is set in SYSBUS_FERR or SYSBUS_NERR
SMI on System Bus Data Parity Error Enable.
0 = No SMI generation
1 = Generate SMI if bit 3 is set in SYSBUS_FERR or SYSBUS_NERR
SMI on System Bus Address Strobe Glitch Detected Enable.
0 = No SMI generation
1 = Generate SMI if bit 2 is set in SYSBUS_FERR or SYSBUS_NERR
SMI on System Bus Data Strobe Glitch Detected Enable.
0 = No SMI generation
1 = Generate SMI if bit 1 is set in SYSBUS_FERR or SYSBUS_NERR
SMI on System Bus Request/Address Parity Error Enable.
0 = No SMI generation
1 = Generate SMI if bit 0 is set in SYSBUS_FERR or SYSBUS_NERR
Datasheet
Register Description
3.7.23
SERRCMD_SYSBUS—SERR Command Register (D0:F1)
Address Offset:
Default:
Sticky:
Access:
Size:
6Ch
00h
No
R/W
8 Bits
This register determines whether SERR will be generated when the associated flag is set in either
the SYSBUS_FERR or SYSBUS_NERR Register. When an error flag is set in the
SYSBUS_FERR or SYSBUS_NERR Register, it can generate an SERR, SMI, or SCI when
enabled in the SERRCMD, SMICMD, or SCICMD Registers, respectively. Only one message type
can be enabled.
Bits
7
6
5
4
3
2
1
0
Datasheet
Default,
Access
0b
R/W
0b
R/W
0b
R/W
0b
R/W
0b
R/W
0b
R/W
0b
R/W
0b
R/W
Description
SERR on System Bus BINIT# Detected Enable.
0 = No SERR generation
1 = Generate SERR if bit 7 is set in SYSBUS_FERR or SYSBUS_NERR
SERR on System Bus xERR# Detected Enable.
0 = No SERR generation
1 = Generate SERR if bit 6 is set in SYSBUS_FERR or SYSBUS_NERR
SERR on Non-DRAM Lock Error Enable.
0 = No SERR generation
1 = Generate SERR if bit 5 is set in SYSBUS_FERR or SYSBUS_NERR
SERR on System Bus Address Above TOM Enable.
0 = No SERR generation
1 = Generate SERR if bit 4 is set in SYSBUS_FERR or SYSBUS_NERR
SERR on System Bus Data Parity Error Enable.
0 = No SERR generation
1 = Generate SERR if bit 3 is set in SYSBUS_FERR or SYSBUS_NERR
SERR on System Bus Address Strobe Glitch Detected Enable.
0 = No SERR generation
1 = Generate SERR if bit 2 is set in SYSBUS_FERR or SYSBUS_NERR
SERR on System Bus Data Strobe Glitch Detected Enable.
0 = No SERR generation
1 = Generate SERR if bit 1 is set in SYSBUS_FERR or SYSBUS_NERR
SERR on System Bus Request/Address Parity Error Enable.
0 = No SERR generation
1 = Generate SERR if bit 0 is set in SYSBUS_FERR or SYSBUS_NERR
77
Register Description
3.7.24
DRAM_FERR—DRAM First Error Register (D0:F1)
Address Offset:
Default:
Sticky:
Access:
Size:
80h
00h
Yes
R/WC
8 Bits
This register stores the FIRST ECC error on the DRAM interface. Only 1 error bit will be set in this
register. Any future errors (NEXT errors) will be set in the DRAM_NERR Register. No further
error bits in this register will be set until the existing error bit is cleared.
Note:
Software must write a 1 to clear bits that are set.
Bits
Default,
Access
7:2
00h
0b
1
R/WC
0b
0
3.7.25
R/WC
Description
Reserved
Uncorrectable Memory Error Detected.
0 = No uncorrectable memory error detected.
1 = MCH detected an ECC error on the memory interface that is not correctable.
Correctable Memory Error Detected.
0 = No correctable memory error detected.
1 = MCH detected and corrected an ECC error on the memory interface.
DRAM_NERR—DRAM Next Error Register (D0:F1)
Address Offset:
82h
Default:
00h
Sticky:
Access:
Size:
Yes
R/WC
8 Bits
The FIRST memory ECC error will be stored in the DRAM_FERR Register. This register stores all
future memory ECC errors. Multiple bits in this register may be set.
Note:
Software must write a 1 to clear bits that are set.
Bits
Default,
Access
7:2
00h
1
0
78
0b
R/WC
0b
R/WC
Description
Reserved
Uncorrectable Memory Error Detected.
0 = No uncorrectable memory error detected.
1 = The MCH has detected an ECC error on the memory interface that is not correctable.
Correctable Memory Error Detected.
0 = No correctable memory error detected.
1 = The MCH has detected and corrected an ECC error on the memory interface.
Datasheet
Register Description
3.7.26
SCICMD_DRAM—SCI Command Register (D0:F1)
Address Offset:
Default:
Sticky:
Access:
Size:
88h
00h
No
R/W
8 Bits
This register determines whether SCI will be generated when the associated flag is set in either the
DRAM_FERR or DRAM_NERR Register. When an error flag is set in the DRAM_FERR or
DRAM_NERR Register, it can generate an SERR, SMI, or SCI when enabled in the SERRCMD,
SMICMD, or SCICMD Registers, respectively. Only one message type can be enabled.
Bits
Default,
Access
7:2
000000b
Description
Reserved
SCI on Multiple-Bit DRAM ECC Error (DMERR).
1
0b
R/W
0 = Disable.
1 = Enable. The MCH generates an SCI when it detects a multiple-bit error reported by
the DRAM controller.
SCI on Single-Bit DRAM ECC Error (DSERR).
0
3.7.27
0b
R/W
0 = Disable.
1 = Enable. The MCH generates an SCI when the DRAM controller detects a single-bit
error.
SMICMD_DRAM—SMI Command Register (D0:F1)
Address Offset:
Default:
Sticky:
Access:
Size:
8Ah
00h
No
R/W
8 Bits
This register determines whether SMI will be generated when the associated flag is set in the
DRAM_FERR or DRAM_NERR Register. When an error flag is set in the DRAM_FERR or
DRAM_NERR Register, it can generate an SERR, SMI, or SCI when enabled in the SERRCMD,
SMICMD, or SCICMD Registers, respectively. Only one message type can be enabled.
Bits
Default,
Access
7:2
000000b
Description
Reserved
SMI on Multiple-Bit DRAM ECC Error (DMERR).
1
0b
R/W
0 = Disable.
1 = Enable. The MCH generates an SMI when it detects a multiple-bit error reported by
the DRAM controller.
SMI on Single-Bit DRAM ECC Error (DSERR).
0
Datasheet
0b
R/W
0 = Disable.
1 = Enable. The MCH generates an SMI when the DRAM controller detects a single-bit
error.
79
Register Description
3.7.28
SERRCMD_DRAM—SERR Command Register (D0:F1)
Address Offset:
Default:
Sticky:
Access:
Size:
8Ch
00h
No
R/W
8 Bits
This register determines whether SERR will be generated when the associated flag is set in either
the DRAM_FERR or DRAM_NERR Register. When an error flag is set in the DRAM_FERR or
DRAM_NERR Register, it can generate an SERR, SMI, or SCI when enabled in the SERRCMD,
SMICMD, or SCICMD Registers, respectively. Only one message type can be enabled.
Bits
Default,
Access
7:2
000000b
Description
Reserved
SERR on Multiple-Bit DRAM ECC Error (DMERR).
1
0b
R/W
0 = Disable.
1 = Enable. The MCH generates an SERR when it detects a multiple-bit error reported by
the DRAM controller.
SERR on Single-Bit DRAM ECC Error (DSERR).
0
3.7.29
0b
R/W
0 = Disable.
1 = Enable. The MCH generates an SERR when the DRAM controller detects a single-bit
error.
DRAM_CELOG_ADD—DRAM First Correctable Memory
Error Address Register (D0:F1)
Address Offset:
Default:
Sticky:
Access:
Size:
A0–A3h
0000_0000h
Yes
RO
32 Bits
This register contains the address of the first correctable memory error. This register is locked
when bits in either the DRAM_FERR or DRAM_NERR Registers are set. If the bits in both
registers are set to 0, the DRAM_CELOG_ADD can be updated; however, if a bit in either register
is set to 1, then DRAM_CELOG_ADD will retain its value for logging purposes. This register is
only valid if a bit in either the DRAM_FERR or DRAM_NERR Register is set.
Bits
Default,
Access
31:28
0h
27:6
5:0
80
000000h
Description
Reserved
RO
CE Address. This field contains address bits 33:12 of the first correctable memory error.
The address bits are a physical address.
00h
Reserved
Datasheet
Register Description
3.7.30
DRAM_UELOG_ADD—DRAM First Uncorrectable Memory
Error Address Register (D0:F1)
Address Offset:
Default:
Sticky:
Access:
Size:
B0–B3h
0000_0000h
Yes
RO
32 Bits
This register contains the address of the first uncorrectable memory error. When a bit in either the
DRAM_FERR or DRAM_NERR Register is set, this register is locked. This register is only valid
if a bit in either the DRAM_FERR or DRAM_NERR Register is set.
Bits
Default,
Access
31:28
0h
27:6
5:0
3.7.31
000000h
Description
Reserved
RO
UE Address. This field contains address bits 33:12 of the first uncorrectable memory
error. The address bits are a physical address.
00h
Reserved
DRAM_CELOG_SYNDROME—DRAM First Correctable
Memory Error Register (D0:F1)
Address Offset:
Default:
Sticky:
Access:
Size:
D0–D1h
0000h
Yes
RO
16 Bits
This register contains the syndrome of the first correctable memory error. This register is locked
when a bit in either the DRAM_FERR or DRAM_NERR Register is set. If the bits in both registers
are set to 0, the DRAM_CELOG_SYNDROME can be updated; however, if a bit in either register
is set to 1, then DRAM_CELOG_SYNDROME will retain its value for logging purposes. This
register is only valid if a bit in either the DRAM_FERR or DRAM_NERR Register is set.
Bits
15:0
Datasheet
Default,
Access
0000h
RO
Description
ECC Syndrome for Correctable Errors.
81
Register Description
3.8
HI_B Virtual PCI-to-PCI Bridge Registers
(Device 2, Function 0)
This section provides the register descriptions for the HI_B virtual PCI-to-PCI bridge (Device 2,
Function 0). Table 3-5 provides the register address map for this device, function.
Warning:
Address locations that are not listed the table are considered reserved register locations. Writes to
“Reserved” registers may cause system failure. Reads to “Reserved” registers may return a nonzero value.
Table 3-5. HI_B Virtual PCI-to-PCI Bridge Register Map (HI_A—D2:F0)
Offset
82
Mnemonic
Register Name
Default
Type
00–01h
VID2
Vendor ID
8086h
RO
02–03h
DID2
Device ID
2543h
RO
04–05h
PCICMD2
PCI Command
0000h
RO, R/W
06–07h
PCISTS2
PCI Status
00A0h
RO, R/WC
08h
RID2
Revision ID
02h
RO
0Ah
SUBC2
Sub Class Code
04h
RO
0Bh
BCC2
Base Class Code
06h
RO
0Dh
MLT2
Master Latency Timer
00h
R/W
0Eh
HDR2
Header Type
18h
PBUSN2
19h
BUSN2
1Ah
SUBUSN2
01h or 81h
RO
Primary Bus Number
00h
RO
Secondary Bus Number
00h
R/W
Subordinate Bus Number
00h
R/W
1Bh
SMLT2
Secondary Bus Master Latency Timer
00h
Reserved
1Ch
IOBASE2
I/O Base Address
F0h
R/W
1Dh
IOLIMIT2
I/O Limit Address
00h
R/W
1E–1Fh
SEC_STS2
Secondary Status
0160
RO, R/WC
20–21h
MBASE2
Memory Base Address
FFF0h
R/W
22–23h
MLIMIT2
Memory Limit Address
0000h
R/W
24–25h
PMBASE2
Prefetchable Memory Base Address
FFF0h
RO, R/W
26–27h
PMLIMIT2
Prefetchable Memory Limit Address
0000h
RO, R/W
3Eh
BCTRL2
00h
RO, R/W
Bridge Control
Datasheet
Register Description
3.8.1
VID2—Vendor Identification Register (D2:F0)
Address Offset:
Default:
Sticky:
Access:
Size:
00–01h
8086h
No
RO
16 Bits
The VID Register contains the vendor identification number. This 16-bit register combined with
the Device Identification Register uniquely identify any PCI device.
Bits
15:0
3.8.2
Default,
Access
8086h
RO
Description
Vendor Identification Device 2 (VID2). This register field contains the PCI standard
identification for Intel (VID=8086h).
DID2—Device Identification Register (D2:F0)
Address Offset:
Default:
Sticky:
Access:
Size:
02–03h
2543h
No
RO
16 Bits
This 16-bit register combined with the Vendor Identification register uniquely identifies any PCI
device.
Bits
15:0
Datasheet
Default,
Access
2543h
RO
Description
Device Identification Number (DID). This is a 16-bit value assigned to the MCH
device 2.
83
Register Description
3.8.3
PCICMD2—PCI Command Register (D2:F0)
Address Offset:
Default:
Sticky:
Access:
Size:
04–05h
0000h
No
RO R/W
16 Bits
Since MCH Device 0 does not physically reside on a physical PCI bus, portions of this register are
not implemented.
Bits
Default,
Access
15:10
00h
9
8
7
6
5
4
3
2
0b
RO
0b
R/W
0b
RO
0b
Description
Reserved
Fast Back-to-Back Enable (FB2B). Not Applicable; hardwired to 0.
SERR Message Enable (SERRE). This bit is a global enable bit for Device 2 SERR
messaging. The MCH does not have an SERR# signal. The MCH communicates the
SERR# condition by sending an SERR message to the ICH3-S.
0 = SERR message is not generated by the MCH for Device 2.
1 = The MCH is enabled to generate SERR messages over HI_A for specific Device 2
error conditions.
Address/Data Stepping (ADSTEP). Not applicable; this bit is hardwired to 0.
RO
Parity Error Enable (PERRE). Hardwired to 0. Parity checking is not supported on the
primary side of this device.
0b
Reserved
0b
RO
0b
RO
0b
R/W
Memory Write and Invalidate Enable (MWIE). Not applicable; hardwired to 0.
Special Cycle Enable (SCE). Not applicable; hardwired to 0.
Bus Master Enable (BME). This bit is not functional. It is a R/W bit for compatibility with
compliance testing software.
Memory Access Enable (MAE).
1
0b
R/W
0 = Disable. All of device 2’s memory space is disabled.
1 = Enable. This bit must be set to 1 to enable the Memory and Prefetchable memory
address ranges defined in the MBASE2, MLIMIT2, PMBASE2, and PMLIMIT2
Registers.
IO Access Enable (IOAE).
0
84
0b
R/W
0 = Disable. All of device 2’s I/O space is disabled.
1 = Enable. This bit must be set to 1 to enable the I/O address range defined in the
IOBASE2 and IOLIMIT2 Registers.
Datasheet
Register Description
3.8.4
PCISTS2—PCI Status Register (D2:F0)
Address Offset:
Default:
Sticky:
Access:
Size:
06h
00A0h
No
RO, R/WC
16 Bits
PCISTS2 is a 16-bit status register that reports the occurrence of error conditions associated with
the primary side of the “virtual” PCI-PCI bridge embedded within the MCH.
Bits
15
Default,
Access
0b
RO
Description
Detected Parity Error (DPE). Hardwired to 0. Parity is not supported on the primary side
of this device.
Signaled System Error (SSE).
14
0b
R/WC
0 =No SERR generated by MCH Device 2.
1 =MCH Device 2 generates an SERR message over HI_A for any enabled Device 2 error
condition.
Note: Software clears this bit by writing a 1 to it.
13
12
11
10:9
8
7
6
5
4:0
Datasheet
0b
RO
0b
RO
0b
RO
00b
RO
0b
RO
1b
Received Master Abort Status (RMAS). Hardwired to 0. The concept of master abort
does not exist on primary side of this device.
Received Target Abort Status (RTAS). Hardwired to 0. The concept of target abort does
not exist on primary side of this device.
Signaled Target Abort Status (STAS). Hardwired to 0. The concept of target abort does
not exist on primary side of this device.
DEVSEL# Timing (DEVT). The MCH does not support subtractive decoding devices on
bus 0. This bit field is therefore hardwired to 00 to indicate that device 2 uses the fastest
possible decode.
Master Data Parity Error Detected (DPD). Hardwired to 0. Parity is not supported on the
primary side of this device.
RO
Fast Back-to-Back (FB2B). Hardwired to 1. Fast back to back writes are always
supported on this interface.
0b
Reserved
1b
RO
00h
66/60MHz capability (CAP66). Hardwired to 1. Since HI_B is capable of delivering data
at a rate equal to that of any PCI66 device this bit is hardwired to a 1 so that configuration
software understands that downstream devices may also be effectively enabled for
66 MHz operation.
Reserved
85
Register Description
3.8.5
RID2—Revision Identification Register (D2:F0)
Address Offset:
Default:
Sticky:
Access:
Size:
08h
See table below
No
RO
8 Bits
This register contains the revision number of the MCH device 2.
Bits
7:0
3.8.6
Default,
Access
02h
RO
Description
Revision Identification Number (RID). This is an 8-bit value that indicates the revision
identification number for the MCH device 2.
02h = A2 stepping
SUBC2—Sub-Class Code Register (D2:F0)
Address Offset:
Default:
Sticky:
Access:
Size:
0Ah
04h
No
RO
8 Bits
This register contains the Sub-Class Code for the MCH device 2.
Bits
7:0
86
Default,
Access
Description
04h
Sub-Class Code (SUBC). This is an 8-bit value that indicates the category of Bridge into
which device 2 of the MCH falls.
RO
04h = PCI-to-PCI Bridge.
Datasheet
Register Description
3.8.7
BCC2—Base Class Code Register (D2:F0)
Address Offset:
Default:
Sticky:
Access:
Size
0Bh
06h
No
RO
8 Bits
This register contains the Base Class Code of the MCH device 2.
Bits
7:0
3.8.8
Default,
Access
Description
06h
Base Class Code (BASEC). This is an 8-bit value that indicates the Base Class Code for
the MCH device 2.
RO
06h = Bridge device
MLT2—Master Latency Timer Register (D2:F0)
Address Offset:
Default:
Sticky:
Access:
Size:
0Dh
00h
No
R/W
8 Bits
This functionality is not applicable. It is described here since these bits should be implemented as
read/write to ensue proper execution of standard PCI-to-PCI bridge configuration software.
Bits
7:3
2:0
Datasheet
Default,
Access
00h
Description
R/W
Scratchpad MLT (NA7.3). These bits return the value with which they are written;
however, they have no internal function and are implemented as a scratchpad.
000b
Reserved
87
Register Description
3.8.9
HDR2—Header Type Register (D2:F0)
Address Offset:
Default:
Sticky:
Access:
Size:
0Eh
01h or 81h
No
RO
8 Bits
This register identifies the header layout of the configuration space.
Bits
7:0
Default,
Access
01h or
81h
RO
3.8.10
Description
Header Type Register (HDR). When Function 1 is enabled, this read only field returns
81h to indicate that MCH device 2 is a multi-function device with bridge header layout.
When Function 1 is disabled, 01h is returned to indicate that MCH device 2 is a singlefunction device with bridge layout. Writes to this location have no effect.
PBUSN2—Primary Bus Number Register (D2:F0)
Address Offset:
Default:
Sticky:
Access:
Size:
18h
00h
No
RO
8 Bits
This register identifies that “virtual” PCI-PCI bridge is connected to bus 0.
Bits
7:0
88
Default,
Access
00h
RO
Description
Primary Bus Number (BUSN). Configuration software typically programs this field with
the number of the bus on the primary side of the bridge. Since device 2 is an internal
device and its primary bus is always 0, these bits are read only and are hardwired to 0.
Datasheet
Register Description
3.8.11
BUSN2—Secondary Bus Number Register (D2:F0)
Address Offset:
Default:
Sticky:
Access:
Size:
19h
00h
No
R/W
8 Bits
This register identifies the bus number assigned to the second bus side of the “virtual” PCI-PCI
bridge (the HI_B connection). This number is programmed by the PCI configuration software to
allow mapping of configuration cycles to a second bridge device connected to HI_B.
Bits
7:0
3.8.12
Default,
Access
00h
R/W
Description
Secondary Bus Number (BUSN). This field is programmed by configuration software
with the lowest bus number of the busses connected to HI_B. Since both bus 0, device 2
and the PCI to PCI bridge on the other end of the HI are considered by configuration
software to be PCI bridges, this bus number will always correspond to the bus number
assigned to HI_B.
SUBUSN2—Subordinate Bus Number Register (D2:F0)
Address Offset:
Default:
Sticky:
Access:
Size:
1Ah
00h
No
R/W
8 Bits
This register identifies the subordinate bus (if any) that resides at the level below the secondary HI.
This number is programmed by the PCI configuration software to allow mapping of configuration
cycles to devices subordinate to the secondary HI.
Bits
7:0
Datasheet
Default,
Access
00h
R/W
Description
Subordinate Bus Number (BUSN). This register is programmed by configuration
software with the number of the highest subordinate bus that lies behind the device 2
bridge.
89
Register Description
3.8.13
SMLT2—Secondary Bus Master Latency Timer Register
(D2:F0)
Address Offset:
Default:
Sticky:
Access:
Size:
1Bh
00h
no
Reserved
8 Bits
This register is not implemented.
90
Bits
Default,
Access
7:0
00h
Description
Reserved
Datasheet
Register Description
3.8.14
IOBASE2—I/O Base Address Register (D2:F0)
Address Offset:
Default:
Sticky:
Access:
Size:
1Ch
F0h
No
R/W
8 Bits
This register controls the processor-to-HI_B I/O access routing based on the following formula:
IO_BASE < address < IO_LIMIT
Only the upper 4 bits are programmable. For the purpose of address decode, address bits A[11:0]
are treated as 0. Thus, the bottom of the defined I/O address range will be aligned to a 4-KB
boundary.
Bits
7:4
3:0
3.8.15
Default,
Access
0Fh
Description
R/W
I/O Address Base (IOBASE). This field corresponds to A[15:12] of the I/O addresses
passed by the device 2 bridge to HI_B.
0h
Reserved
IOLIMIT2—I/O Limit Address Register (D2:F0)
Address Offset:
Default:
Sticky:
Access:
Size:
1Dh
00h
No
R/W
8 Bits
This register controls the processor to HI_B I/O access routing based on the following formula:
IO_BASE< address <IO_LIMIT
Only the upper 4 bits are programmable. For the purpose of address decode, address bits A[11:0]
are assumed to be FFFh. Thus, the top of the defined I/O address range will be at the top of a 4 KB
aligned address block.
Bits
7:4
3:0
Datasheet
Default,
Access
0h
Description
R/W
I/O Address Limit (IOLIMIT). This field corresponds to A[15:12] of the I/O address limit of
device 2. Devices between this upper limit and IOBASE2 will be passed to HI_B.
0h
Reserved
91
Register Description
3.8.16
SEC_STS2—Secondary Status Register (D2:F0)
Address Offset:
Default:
Sticky:
Access:
Size:
1E–1Fh
0160h
No
RO, R/WC
16 Bits
SSTS2 is a 16-bit status register that reports the occurrence of error conditions associated with
secondary side (i.e., HI_B side) of the “virtual” PCI-PCI bridge embedded within the MCH.
Note:
Software must write a 1 to clear bits that are set.
Bits
15
14
13
12
11
10:9
8
7
6
5
4:0
92
Default,
Access
0b
R/WC
0b
R/WC
0b
R/WC
0b
R/WC
0b
RO
01b
RO
0b
RO
1b
RO
0b
1b
RO
00h
Description
Detected Parity Error (2DPE).
0 = No parity error detected.
1 = MCH detected a parity error in the address or data phase of HI_B bus transactions.
Received System Error (2RSE).
0 = No system error received.
1 = This bit is set to 1 when the MCH receives an SERR message on HI_B.
Received Master Abort Status (2RMAS).
0 = No Master Abort received.
1 = The MCH received a Master Abort completion packet on HI_B.
Received Target Abort Status (2RTAS).
0 = No Target Abort received.
1 = The MCH received a Target Abort completion packet on HI_B.
Signaled Target Abort Status (STAS). Hardwired to 0. The MCH does not generate
target aborts on HI_B.
DEVSEL# Timing (DEVT). Hardwired to 01. This concept is not supported on HI_B.
Master Data Parity Error Detected (DPD). Hardwired to 0. The MCH does not implement
PERR messaging on HI_B.
Fast Back-to-Back (FB2B). Hardwired to 1. This function is not supported on HI_B.
Reserved
66/60 MHz capability (CAP66). Hardwired to 1. HI_B is enabled for 66 MHz operation.
Reserved
Datasheet
Register Description
3.8.17
MBASE2—Memory Base Address Register (D2:F0)
Address Offset:
Default:
Sticky:
Access:
Size:
20–21h
FFF0h
No
R/W
16 Bits
This register controls the processor to HI_B non-prefetchable memory access routing based on the
following formula:
MEMORY_BASE < address < MEMORY_LIMIT
The upper 12 bits of the register are read/write and correspond to the upper 12 address bits
A[31:20] of the 32 bit address. The bottom 4 bits of this register are read-only and return 0s when
read. This register must be initialized by the configuration software. For the purpose of address
decode, address bits A[19:0] are assumed to be 0. The bottom of the defined memory address range
will be aligned to a 1-MB boundary.
Bits
15:4
3:0
Datasheet
Default,
Access
FFFh
R/W
0h
Description
Memory Address Base (MBASE). This field corresponds to A[31:20] of the lower limit of
the memory range that will be passed by the device 2 bridge to HI_B.
Reserved
93
Register Description
3.8.18
MLIMIT2—Memory Limit Address Register (D2:F0)
Address Offset:
Default:
Sticky:
Access:
Size:
22–23h
0000h
No
R/W
16 Bits
This register controls the processor to HI_B non-prefetchable memory access routing based on the
following formula:
MEMORY_BASE < address < MEMORY_LIMIT
The upper 12 bits of the register are read/write and correspond to the upper 12 address bits
A[31:20] of the 32-bit address. The bottom four bits of this register are read-only and return 0s
when read. This register must be initialized by the configuration software. For the purpose of
address decode, address bits A[19:0] are assumed to be FFFFFh. Thus, the top of the defined
memory address range will be at the top of a 1-MB aligned memory block.
Note:
The memory range covered by the MBASE and MLIMIT Registers are used to map nonprefetchable HI_B address ranges (typically where control/status memory-mapped I/O data
structures of the graphics controller will reside) and PMBASE and PMLIMIT are used to map
prefetchable address ranges (typically graphics local memory). This segregation allows application
of USWC space attribute to be performed in a true plug-and-play manner to the prefetchable
address range for improved HI memory access performance.
Configuration software is responsible for programming all address range registers (prefetchable,
non-prefetchable) with the values that provide exclusive address ranges (i.e., prevent overlap with
each other and/or with the ranges covered with the main memory). There is no provision in the
MCH hardware to enforce prevention of overlap and operations of the system in the case of overlap
are not guaranteed.
Bits
15:4
3:0
94
Default,
Access
000h
R/W
0h
Description
Memory Address Limit (MILIMIT). This field corresponds to A[31:20] of the memory
address that corresponds to the upper limit of the range of memory accesses that will be
passed by the device 2 bridge to HI_B
Reserved
Datasheet
Register Description
3.8.19
PMBASE2—Prefetchable Memory Base Address Register
(D2:F0)
Address Offset:
Default:
Sticky:
Access:
Size:
24–25h
FFF0h
No
RO, R/W
16 Bits
This register controls the processor to HI_B prefetchable memory accesses. See PM64BASE2 for
usage. The upper 12 bits of the register are read/write and correspond to the upper 12 address bits
A[31:20] of the 36-bit address. For the purpose of address decode, bits A[19:0] are assumed to be
0. Thus, the bottom of the defined memory address range will be aligned to a 1-MB boundary.
Bits
15:4
3:0
3.8.20
Default,
Access
FFFh
R/W
0h
RO
Description
Prefetchable Memory Address Base (PMBASE). This field corresponds to A[31:20] of
the lower limit of the address range passed by bridge device 2 across HI_B.
64-bit Addressing Support. Hardwired to 0. The MCH does not support Outbound 64-bit
addressing.
PMLIMIT2—Prefetchable Memory Limit Address Register
(D2:F0)
Address Offset:
Default:
Sticky:
Access:
Size:
26h
0000h
No
RO, R/W
16 Bits
This register controls the processor to HI_B prefetchable memory accesses. See PM64BASE2 for
usage. The upper 12 bits of the register are read/write and correspond to the upper 12 address bits
A[31:20] of the 36-bit address. For the purpose of address decode, bits A[19:0] are assumed to be
FFFFh. Thus, the top of the defined memory address range will be at the top of a 1-MB aligned
memory block.
Bits
15:4
3:0
Datasheet
Default,
Access
000h
R/W
0h
RO
Description
Prefetchable Memory Address Limit (PMLIMIT). This field corresponds to A[31:20] of
the upper limit of the address range passed by bridge device 2 across HI_B.
64-bit Addressing Support. Hardwired to 0. The MCH does not support Outbound 64-bit
addressing.
95
Register Description
3.8.21
BCTRL2—Bridge Control Register (D2:F0)
Address Offset:
Default:
Sticky:
Access:
Size:
3Eh
00h
No
RO, R/W
8 Bits
This register provides extensions to the PCICMD2 register that are specific to PCI-PCI bridges.
The BCTRL provides additional control for the secondary interface (i.e., HI_B) as well as some
bits that affect the overall behavior of the “virtual” PCI-PCI bridge in the MCH
(e.g., VGA compatible address range mapping).
Bits
7
6
5
4
3
Default,
Access
0b
RO
0b
RO
Description
Fast Back-to-Back Enable (FB2BEN). Hardwired to 0. The MCH does not generate fast
back-to-back cycles as a master on HI_B.
Secondary Bus Reset (SRESET). Hardwired to 0. The MCH does not support generation
of reset via this bit on the HI_B.
RO
Master Abort Mode (MAMODE). Hardwired to 0. Thus, when acting as a master on
HI_B, the MCH will drop writes on the floor and return all 1s during reads when a Master
Abort occurs.
0b
Reserved
0b
0b
R/W
VGA Enable (VGAEN). This bit controls the routing of processor-initiated transactions
targeting VGA compatible I/O and memory address ranges. The following must be
enforced via software.
0 = This bit is set to 0 if the video device is not present behind the bridge.
1 = If video device is behind the bridge, this bit is set to 1.
NOTE: Only one of device 2–4’s VGAEN bits are allowed to be set.
ISA Enable (ISAEN). Modifies the response by the MCH to an I/O access issued by the
processor that target ISA I/O addresses. This applies only to I/O addresses that are
enabled by the IOBASE and IOLIMIT Registers.
2
1
0b
R/W
0b
R/W
0 = All addresses defined by the IOBASE and IOLIMIT for processor I/O transactions will
be mapped to HI_B.
1 = MCH does not forward to HI_B any I/O transactions addressing the last 768 bytes in
each 1 KB block, even if the addresses are within the range defined by the IOBASE
and IOLIMIT Registers. Instead of going to HI_B, these cycles are forwarded to HI_A
where they can be subtractively or positively claimed by the ISA bridge.
SERR Enable (2SERREN). This bit enables or disables forwarding of SERR messages
from HI_B to HI_A, where they can be converted into interrupts that are eventually
delivered to the processor.
0 = Disable
1 = Enable
Parity Error Response Enable (2PEREN). Controls the MCH’s response to data phase
parity errors on HI_B.
0
0b
R/W
0 = Address and data parity errors on HI_B are not reported via the MCH HI_A SERR
messaging mechanism.
1 = Address and data parity errors on HI_B are reported via the HI_A SERR messaging
mechanism, if further enabled by 2SERREN.
NOTE: Other types of error conditions can still be signaled via SERR messaging
independent of this bit’s state.
96
Datasheet
Register Description
3.9
HI_B Virtual PCI-to-PCI Bridge Registers
(Device 2, Function 1)
This section provides the register descriptions for the HI_B virtual PCI-to-PCI bridge (Device 2,
Function 1). Table 3-6 provides the register address map for this device, function.
Warning:
Address locations that are not listed in the table are considered reserved register locations. Writes
to “Reserved” registers may cause system failure. Reads to “Reserved” registers may return a nonzero value.
Table 3-6. HI_B Virtual PCI-to-PCI Bridge Register Map (HI_A—D2:F1)
Offset
Datasheet
Mnemonic
Register Name
Default
Type
00–01h
VID
Vendor ID
8086h
RO
02–03h
DID
Device ID
2544h
RO
04–05h
PCICMD
PCI Command
0000h
RO, R/W
06–07h
PCISTS
PCI Status
0000h
R/WC
08h
RID
Revision ID
02h
RO
0Ah
SUBC
Sub Class Code
00h
RO
0Bh
BCC
Base Class Code
FFh
RO
0Eh
HDR
Header Type
00h or 80h
RO
2C–2Dh
SVID
Subsystem Vendor Identification
0000h
R/WO
2E–2Fh
SID
Subsystem Identification
0000h
R/WO
80h
HIB_FERR
Hub Interface_B First Error
00h
R/WC
82h
HIB_NERR
Hub Interface_B Next Error
00h
R/WC
A0h
SERRCMD2
SERR Command
00h
R/W
A2h
SMICMD2
SMI Command
00h
R/W
A4h
SCICMD2
SCI Command
00h
R/W
97
Register Description
3.9.1
VID—Vendor Identification Register (D2:F1)
Address Offset:
Default:
Sticky:
SMB Shadowed:
Access:
Size:
00h
8086h
No
Yes
RO
16 Bits
The VID Register contains the vendor identification number. This 16-bit register combined with
the Device Identification Register uniquely identifies any PCI device.
Bits
15:0
3.9.2
Default,
Access
8086h
RO
Description
Vendor Identification (VID). This register field contains the PCI standard identification for
Intel (VID=8086h).
DID—Device Identification Register (D2:F1)
Address Offset:
Default:
Sticky:
SMB Shadowed:
Access:
Size:
02h
2544h
No
Yes
RO
16 Bits
.
Bits
15:0
98
Default,
Access
2544h
RO
Description
Device Identification Number (DID). This is a 16-bit value assigned to the MCH Host-HI
Bridge Function 1. The value is 2544h.
Datasheet
Register Description
3.9.3
PCICMD—PCI Command Register (D2:F1)
Address Offset:
Default:
Sticky:
SMB Shadowed:
Access:
Size:
04h
0000h
No
Yes
R/W
16 Bits
Since MCH Device 0 does not physically reside on a physical PCI bus portions of this register are
not implemented.
Bits
Default,
Access
15:9
00h
Description
Reserved
SERR Enable (SERRE). This bit is global enable bit for Device 2 SERR messaging.
8
7:0
3.9.4
R/W
0 = Disable. SERR is not generated by the MCH for Device 2.
1 = Enable. The MCH is enabled to generate SERR over HI_A for specific Device 2 error
conditions that are individually enabled in the ERRCMD register. The error status is
reported in the ERRSTAT and PCISTS Registers.
00h
Reserved
0b
PCISTS—PCI Status Register (D2:F1)
Address Offset:
Default:
Sticky:
SMB Shadowed:
Access:
Size:
06h
0000h
No
Yes
R/WC
16 Bits
PCISTS is a 16-bit status register that reports the occurrence of error events on Device 0’s PCI
interface. Bit 14 is read/write clear. All other bits are Read Only. Since MCH Device 0 does not
physically reside on PCI_A many of the bits are not implemented.
Bits
Default,
Access
15
0b
Description
Reserved
Signaled System Error (SSE).
14
0b
R/WC
0 = No signaled system error generated.
1 = MCH Device 2 generated an SERR over HI_A for any enabled Device 2 error
condition. Device 2 error conditions are enabled in the PCICMD and ERRCMD
Registers. Device 2 error flags are read/reset from the PCISTS or ERRSTAT
Registers.
Note: Software sets this bit to 0 by writing a 1 to it.
13:0
Datasheet
000h
Reserved
99
Register Description
3.9.5
RID—Revision Identification Register (D2:F1)
Address Offset:
Default:
Sticky:
SMB Shadowed:
Access:
Size:
08h
See table below
No
Yes
RO
8 Bits
This register contains the revision number of the MCH Device 0.
Bits
7:0
Default,
Access
Description
02h
Revision Identification Number (RID). This is an 8-bit value that indicates the revision
identification number for the MCH Device 0. This value should always be the same as the
RID for device0, function 0.
RO
02h = A2 stepping
3.9.6
SUBC—Sub-Class Code Register (D2:F1)
Address Offset:
Default:
Sticky:
SMB Shadowed:
Access:
Size:
0Ah
00h
No
Yes
RO
8 Bits
This register contains the Sub-Class Code for the MCH Device 0.
Bits
7:0
100
Default,
Access
Description
00h
Sub-Class Code (SUBC). This is an 8-bit value that indicates the category of undefined.
RO
00h = Undefined device.
Datasheet
Register Description
3.9.7
BCC—Base Class Code Register (D2:F1)
Address Offset:
Default:
Sticky:
SMB Shadowed:
Access:
Size:
0Bh
FFh
No
Yes
RO
8 Bits
This register contains the Base Class Code of the MCH Device 2.
Bits
7:0
3.9.8
Default,
Access
FFh
RO
Description
Base Class Code (BASEC). This is an 8-bit value that indicates the Base Class Code for
the MCH.
FFh =Non-defined device. Since this function is used for error conditions, it does not fall
into any other class.
HDR—Header Type Register (D2:F1)
Address Offset:
Default:
Sticky:
SMB Shadowed:
Access:
Size:
0Eh
00h or 80h
No
Yes
RO
8 Bits
This register identifies the header layout of the configuration space. No physical register exists at
this location.
Bits
7:0
Default,
Access
00h or
80h
RO
Datasheet
Description
PCI Header (HDR). This read only field always returns 00h or 80h to indicate that the MCH
is a multi-function device with standard header layout.
101
Register Description
3.9.9
SVID—Subsystem Vendor Identification Register (D2:F1)
Address Offset:
Default:
Sticky:
SMB Shadowed:
Access:
Size:
2C–2Dh
0000h
No
Yes
R/WO
16 Bits
This value is used to identify the vendor of the subsystem.
Bits
15:0
3.9.10
Default,
Access
0000h
R/WO
Description
Subsystem Vendor ID (SUBVID). This field should be programmed during boot-up to
indicate the vendor of the system board. After it has been written once, it becomes read
only.
SID—Subsystem Identification Register (D2:F1)
Address Offset:
Default:
Sticky:
SMB Shadowed:
Access:
Size:
2E–2Fh
0000h
No
Yes
R/WO
16 Bits
This value is used to identify a particular subsystem.
Bits
15:0
102
Default,
Access
0000h
R/WO
Description
Subsystem ID (SUBID). This field should be programmed during BIOS initialization. After
it has been written once, it becomes read only.
Datasheet
Register Description
3.9.11
HIB_FERR—Hub Interface_B First Error Register (D2:F1)
Address Offset:
Default:
Sticky:
SMB Shadowed:
Access:
Size:
80h
00h
Yes
Yes
R/WC
8 Bits
This register store the FIRST error related to HI_B. Only one error bit will be set in this register.
Any future errors (NEXT Errors) will be set. No further error bits in this register will be set until
the existing error bit is cleared.
Note:
Software must write a 1 to clear bits that are set.
Bits
Default,
Access
7
0b
6
0b
R/WC
Description
Reserved
MCH Received SERR From HI_B.
0 = No SERR from HI_B detected.
1 = MCH detected a SERR on Hub Interface_B.
MCH Master Abort on HI_B (HIBMA). MCH did a master abort to a HI_B request.
5
0b
R/WC
0 = No Master Abort on HI_B detected.
1 = MCH detected an invalid address that will be master aborted. This bit is set even when
the MCH does not respond with the Master Abort completion packet.
Received Target Abort on HI_B.
4
0b
R/WC
0 = No Target Abort on HI_B detected.
1 = MCH detected that an MCH originated cycle was terminated with a Target Abort
completion packet.
Correctable Error on Header/Address from HI_B.
3
0b
R/WC
0 = No correctable error on header/address from HI_B detected.
1 = Even when error correction is turned off, this bit may be set if a packet is received that
has a single bit correctable error.
Correctable Error on Data from HI_B.
2
0b
R/WC
0 = No correctable error on data from HI_B detected.
1 = Even when error correction is turned off, this bit may be set if a packet is received that
has a single bit correctable error.
Uncorrectable Error on Header/Address from HI_B.
1
0b
R/WC
0 = No uncorrectable error on header/address from HI_B detected.
1 = Even when error correction is turned off, this bit may be set if a packet is received that
has a multi-bit uncorrectable error.
Uncorrectable Error on Data Transfer from HI_B.
0
Datasheet
0b
R/WC
0 = No uncorrectable error on data from HI_B detected.
1 = Even when error correction is turned off, this bit may be set if a packet is received that
has a multi-bit uncorrectable error.
103
Register Description
3.9.12
HIB_NERR—Hub Interface_B Next Error Register (D2:F1)
Address Offset:
Default:
Sticky:
SMB Shadowed:
Access:
Size:
82h
00h
Yes
Yes
R/WC
8 Bits
The FIRST error related to HI_B will be stored in the HIB_FERR Register. This register store all
future errors related to the HI_B. Multiple bits in this register may be set.
Note:
Software must write a 1 to clear bits that are set.
Bits
Default,
Access
7
0b
6
0b
R/WC
Description
Reserved
MCH Received SERR from HI_B.
0 = No SERR from HI_B received.
1 = MCH received SERR from HI_B.
MCH Master Abort on HI_B (HIBMA). MCH did a Master Abort to a HI_B Request.
5
0b
R/WC
0 = No Master Abort on HI_B detected.
1 = The MCH detected an invalid address that will be master aborted. This bit is set even
when the MCH does not respond with the Master Abort completion packet.
Received Target Abort on HI_B.
4
0b
R/WC
0 = No Target Abort detected.
1 = The MCH has detected that an MCH originated cycle was terminated with a Target
Abort completion packet.
Correctable Error on Header/Address from HI_B.
3
0b
R/WC
0 = No correctable error on header/address from HI_B detected.
1 = Even when error correction is turned off, this bit may be set if a packet is received
that has a single bit correctable error.
Correctable Error on Data from HI_B.
2
0b
R/WC
0 = No correctable error on data from HI_B detected.
1 = Even when error correction is turned off, this bit may be set if a packet is received
that has a single bit correctable error.
Uncorrectable Error on Header/Address from HI_B.
1
0b
R/WC
0 = No uncorrectable error on header/address from HI_B detected.
1 = Even when error correction is turned off, this bit may be set if a packet is received
that has a multi-bit uncorrectable error.
Uncorrectable Error on Data Transfer from HI_B.
0
104
0b
R/WC
0 = No uncorrectable error on data from HI_B detected.
1 = Even when error correction is turned off, this bit may be set if a packet is received
that has a multi-bit uncorrectable error.
Datasheet
Register Description
3.9.13
SERRCMD2—SERR Command Register (D2:F1)
Address Offset:
Default:
Sticky:
Access:
Size:
A0h
00h
No
R/W
8 Bits
This register determines whether SERR will be generated when the associated flag is set in the
FERR or NERR Register. When an error flag is set in the FERR or NERR Register, it can generate
an SERR, SMI, or SCI when enabled in the SERRCMD, SMICMD, or SCICMD Registers,
respectively. Only one message type can be enabled.
Bits
Default,
Access
7:6
00b
5
4
3
2
1
0
Datasheet
0b
R/W
0b
R/W
0b
R/W
0b
R/W
0b
R/W
0b
R/W
Description
Reserved
SERR on MCH Master Abort to a HI_B Request Enable.
0 = No SERR generation
1 = Generate SERR if bit 5 is set in HIB_FERR or HIB_NERR
SERR on Received Target Abort on HI_B Enable.
0 = No SERR generation
1 = Generate SERR if bit 4 is set in HIB_FERR or HIB_NERR
SERR on Correctable Error on Header/Address from HI_B Enable.
0 = No SERR generation
1 = Generate SERR if bit 3 is set in HIB_FERR or HIB_NERR
SERR on Correctable Error on Data from HI_B Enable.
0 = No SERR generation
1 = Generate SERR if bit 2 is set in HIB_FERR or HIB_NERR
SERR on Uncorrectable Error on Header/Address from HI_B Enable.
0 = No SERR generation
1 = Generate SERR if bit 1is set in HIB_FERR or HIB_NERR
SERR on Uncorrectable Error on Data Transfer from HI_B Enable.
0 = No SERR generation
1 = Generate SERR if bit 0 is set in HIB_FERR or HIB_NERR
105
Register Description
3.9.14
SMICMD2—SMI Command Register (D2:F1)
Address Offset:
Default:
Sticky:
Access:
Size:
A2h
00h
No
R/W
8 Bits
This register determines whether SMI will be generated when the associated flag is set in the FERR
or NERR Register. When an error flag is set in the FERR or NERR Register, it can generate an
SERR, SMI, or SCI when enabled in the SERRCMD, SMICMD, or SCICMD Registers,
respectively. Only one message type can be enabled.
Bits
Default,
Access
7
0b
6
5
4
3
2
1
0
106
0b
R/W
0b
R/W
0b
R/W
0b
R/W
0b
R/W
0b
R/W
0b
R/W
Description
Reserved
SMI on MCH Received SERR from HI_B Enable.
0 = No SMI generation
1 = Generate SMI if bit 6 is set in HIB_FERR or HIB_NERR
SMI on MCH Master Abort to a HI_B Request Enable.
0 = No SMI generation
1 = Generate SMI if bit 5 is set in HIB_FERR or HIB_NERR
SMI on Received Target Abort on HI_B Enable.
0 = No SMI generation
1 = Generate SERR if bit 4 is set in HIB_FERR or HIB_NERR
SMI on Correctable Error on Header/Address from HI_B Enable.
0 = No SMI generation
1 = Generate SMI if bit 3 is set in HIB_FERR or HIB_NERR
SMI on Correctable Error on Data from HI_B Enable.
0 = No SMI generation
1 = Generate SMI if bit 2 is set in HIB_FERR or HIB_NERR
SMI on Uncorrectable Error on Header/Address from HI_B Enable.
0 = No SMI generation
1 = Generate SMI if bit 1is set in HIB_FERR or HIB_NERR
SMI on Uncorrectable Error on Data Transfer from HI_B Enable.
0 = No SMI generation
1 = Generate SMI if bit 0 is set in HIB_FERR or HIB_NERR
Datasheet
Register Description
3.9.15
SCICMD2—SCI Command Register (D2:F1)
Address Offset:
Default:
Sticky:
Access:
Size:
A4h
00h
Yes
R/W
8 Bits
This register determines whether SCI will be generated when the associated flag is set in the FERR
or NERR Register. When an error flag is set in the FERR or NERR Register, it can generate an
SERR, SMI, or SCI when enabled in the ERRCMD, SMICMD, or SCICMD Registers,
respectively. Only one message type can be enabled.
Bits
Default,
Access
7
0b
6
5
4
3
2
1
0
Datasheet
0b
R/W
0b
R/W
0b
R/W
0b
R/W
0b
R/W
0b
R/W
0b
R/W
Description
Reserved
SCI on MCH Received SERR from HI_B Enable.
0 = No SCI generation
1 = Generate SCI if bit 6 is set in HIB_FERR or HIB_NERR
SCI on MCH Master Abort to a HI_B Request Enable.
0 = No SCI generation
1 = Generate SCI if bit 5 is set in HIB_FERR or HIB_NERR
SCI on Received Target Abort on HI_B Enable.
0 = No SCI generation
1 = Generate SCI if bit 4 is set in HIB_FERR or HIB_NERR
SCI on Correctable Error on Header/Address from HI_B Enable.
0 = No SCI generation
1 = Generate SCI if bit 3 is set in HIB_FERR or HIB_NERR
SCI on Correctable Error on Data from HI_B Enable.
0 = No SCI generation
1 = Generate SCI if bit 2 is set in HIB_FERR or HIB_NERR
SCI on Uncorrectable Error on Header/Address from HI_B Enable.
0 = No SCI generation
1 = Generate SCI if bit 1is set in HIB_FERR or HIB_NERR
SCI on Uncorrectable Error on Data Transfer from HI_B Enable.
0 = No SCI generation
1 = Generate SCI if bit 0 is set in HIB_FERR or HIB_NERR
107
Register Description
3.10
HI_C Virtual PCI-to-PCI Bridge Registers
(Device 3, Function 0,1)
Device 3 is the HI_C virtual PCI-to-PCI bridge. The register descriptions for Device 3 are the same
as Device 2 (except for the DID Registers). This section contains the DID Register descriptions for
Device 3, Function 0,1. For other register descriptions, refer to Section 3.8 and Section 3.9.
3.10.1
DID—Device Identification Register (D3:F0)
Address Offset:
Default:
Access:
Size:
02–03h
2545h
RO
16 Bits
This 16-bit register combined with the Vendor Identification register uniquely identifies any PCI
device.
Bits
15:0
3.10.2
Default,
Access
2545h
RO
Description
Device Identification Number (DID). This is a 16-bit value assigned to the MCH device 3.
DID—Device Identification Register (D3:F1)
Address Offset:
Default:
Access:
Size:
02–03h
2546h
RO
16 Bits
This 16-bit register combined with the Vendor Identification register uniquely identifies any PCI
device.
Bits
15:0
108
Default,
Access
2546h
RO
Description
Device Identification Number (DID). This is a 16-bit value assigned to the MCH device 3.
Datasheet
Register Description
3.11
HI_D Virtual PCI-to-PCI Bridge Registers
(Device 4, Function 0,1)
Device 4 is the HI_D virtual PCI-to-PCI bridge. The register descriptions for Device 4 are the same
as Device 2 (except for the DID Registers). This section contains the DID Register descriptions for
Device 4, Function 0,1. For other register descriptions, refer to Section 3.8 and Section 3.9.
3.11.1
DID—Device Identification Register (D4:F0)
Address Offset:
Default:
Access:
Size:
02–03h
2547h
RO
16 Bits
This 16-bit register combined with the Vendor Identification Register uniquely identifies any PCI
device.
Bits
15:0
3.11.2
Default,
Access
2547h
RO
Description
Device Identification Number (DID). This is a 16-bit value assigned to the MCH
device 4.
DID—Device Identification Register (D4:F1)
Address Offset:
Default:
Access:
Size:
02–03h
2548h
RO
16 Bits
This 16-bit register combined with the Vendor Identification Register uniquely identifies any PCI
device. Writes to this register have no effect.
Bits
15:0
Datasheet
Default,
Access
2548h
RO
Description
Device Identification Number (DID). This is a 16-bit value assigned to the MCH
device 4.
109
Register Description
This page is intentionally left blank.
110
Datasheet
System Address Map
4
System Address Map
A system based on the E7500 chipset supports 16 GB of host-addressable memory space and
64 KB + 3 bytes of host-addressable I/O space. The I/O and memory spaces are divided by system
configuration software into regions. The memory ranges are useful either as system memory or as
specialized memory, while the I/O regions are used solely to control the operation of devices in the
system.
4.1
System Memory Spaces
There are four basic regions of memory in the system:
• High Memory Range. Memory above 4 GB. This memory range is for additional main
memory (1_0000_0000h to 3_FFFF_FFFFh).
• Memory between 1 MB and the Top of Low Memory (TOLM) Register. This is a main
memory address range (0_0100_0000h to TOLM).
• Memory between the TOLM Register and 4 GB. This range is used for mapping APIC and
Hub Interface_A–D. Programmable non-overlapping I/O windows can be mapped to this area.
• DOS Compatible memory area. Memory below 1 MB (0_0000_0000h to 0_0009_FFFFh).
Figure 4-1. System Address Map
16 GB
Additional Main
Memory Address
Range
4 GB
PCI Memory Address
Range
Main Memory
Address Range
Hub Interface_A–D
I/O
Aperture
APICs
Top of Low
Memory
1 MB
DOS Legacy Address
Range
Independently Programmable
Non-overlapping Windows
These address ranges are always mapped to system memory, regardless of the system
configuration. Memory may be allocated from the main memory segment 0_0100_0000h to TOLM
for use by System Management Mode (SMM) hardware and software. The top of main memory is
defined by the Top of Low Memory (TOLM) Register. Note that the address of the highest 64 MB
quantity of valid memory in the system is placed into the DRB7 Register. For systems with a total
DRAM space and PCI memory-mapped space of less than 4 GB, this value will be the same as the
one programmed into the TOLM Register. For other memory configurations, the two are unlikely
to be the same, since the PCI configuration portion of the BIOS software will program the TOLM
Datasheet
111
System Address Map
Register to the maximum value that is less than 4 GB and also allows enough room for all
populated PCI devices. Figure 4-2 shows the segments within the extended memory segment
(1 MB to 4 GB).
Figure 4-2. Detailed Extended Memory Range Address Map
1_0000_0000 (4 GB)
High BIOS, Optional
extended SMRAM
FF00_0000
Hub Interface_A
(always)
FEF0_0000
Local APIC Space
FEE0_0000
Hub Interface_A
(always)
FED0_0000
Hub Interface_B–D,
I/O APIC Space
FEC8_0000
Hub interface_A,
I/O APIC Space
FEC0_0000
Hub Interface_B–D
Windows
Top of Low Memory (TOLM)
Extended SMRAM
Space
TEM - TSEG
100C_0000
100A_0000
0100_0000 (16 MB)
ISA Hole (optional)
= Main Memory Region
00F0_0000 (15 MB)
= Optional Main Memory Region
0010_0000 (1 MB)
dd
112
3
Datasheet
System Address Map
4.1.1
VGA and MDA Memory Spaces
Video cards use these legacy address ranges to map a frame buffer or a character-based video
buffer. The address ranges in this memory space are:
• VGAA
• MDA
• VGAB
0_000A_0000h to 0_000A_FFFFh
0_000B_0000h to 0_000B_7FFFh
0_000B_8000h to 0_000B_FFFFh
By default, accesses to these ranges are forwarded to Hub Interface_A. However, if the VGA_EN
bit is set in the BCTRL 2–4 configuration registers, then transactions within the VGA and MDA
spaces are sent to Hub Interface_B, C, D, respectively.
Note:
The VGA_EN bit may be set in one and only one of the BCTRL Registers. Software must not set
more than one of the VGA_EN bits.
If the configuration bit MCHCFG.MDAP is set, accesses that fall within the MDA range will be
sent to Hub Interface_A without regard for the VGAEN bits. Legacy support requires the ability to
have a second graphics controller (monochrome) in the system. In a E7500 chipset system,
accesses in the standard VGA range are forwarded to Hub Interface_B, C, D (depending on
configuration bits). Since the monochrome adapter may be on the HI_A/PCI (or ISA) bus, the
MCH must decode cycles in the MDA range and forward them to Hub Interface_A. This capability
is controlled by a configuration bit (MDAP bit). In addition to the memory range B0000h to
B7FFFh, the MCH decodes I/O cycles at 3B4h, 3B5h, 3B8h, 3B9h, 3BAh and 3BFh and forwards
them to Hub Interface_A.
An optimization allows the system to reclaim the memory displaced by these regions. When SMM
memory space is enabled by SMRAM.G_SMRAME and either the SMRAM.D_OPEN bit is set or
the system bus receives an SMM-encoded request for code (not data), the transaction is steered to
system memory rather than HI_A. Under these conditions, both of the VGAEN bits and the MDAP
bit are ignored.
Datasheet
113
System Address Map
4.1.2
PAM Memory Spaces
The address ranges in this space are:
•
•
•
•
•
•
•
•
•
•
•
•
•
PAMC0
0_000C_0000 to 0_000C_3FFF
PAMC4
0_000C_4000 to 0_000C_7FFF
PAMC8
0_000C_8000 to 0_000C_BFFF
PAMCC
0_000C_C000 to 0_000C_FFFF
PAMD0
0_000D_0000 to 0_000D_3FFF
PAMD4
0_000D_4000 to 0_000D_7FFF
PAMD8
0_000D_8000 to 0_000D_BFFF
PAMDC
0_000D_C000 to 0_000D_FFFF
PAME0
0_000E_0000 to 0_000E_3FFF
PAME4
0_000E_4000 to 0_000E_7FFF
PAME8
0_000E_8000 to 0_000E_BFFF
PAMEC
0_000E_C000 to 0_000E_FFFF
PAMF0
0_000F_0000 to 0_000F_FFFF
The 256 KB PAM region is divided into three parts:
• ISA expansion region: 128 KB area between 0_000C_0000h and 0_000D_FFFFh
• Extended BIOS region: 64 KB area between 0_000E_0000h and 0_000E_FFFFh,
• System BIOS region: 64 KB area between 0_000F_0000h and 0_000F_FFFFh.
The ISA expansion region is divided into eight, 16-KB segments. Each segment can be assigned
one of four read/write states: read-only, write-only, read/write, or disabled. Typically, these blocks
are mapped through the MCH and are subtractively decoded to ISA space.
The extended system BIOS region is divided into four, 16-KB segments. Each segment can be
assigned independent read and write attributes so it can be mapped either to main memory or to
Hub Interface_A. Typically, this area is used for RAM or ROM.
The system BIOS region is a single, 64-KB segment. This segment can be assigned read and write
attributes. It is by default (after reset) read/write disabled and cycles are forwarded to Hub
Interface_A. By manipulating the read/write attributes, the MCH can shadow BIOS into the main
memory.
Note that the PAM region can be accessed by Hub Interface_A–D. All reads or writes from any
Hub Interface that hits the PAM area is sent to main memory. If the system is setup so that there are
Hub Interface accesses to the PAM regions, then the PAM region being accessed must be
programmed to be both readable and writable by the processor. If the accessed PAM region is
programmed for either reads or writes to be forwarded to Hub Interface_A, and there are Hub
Interface accesses to that PAM, the system may fault.
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Datasheet
System Address Map
4.1.3
ISA Hole Memory Space
BIOS software may optionally open a “window” between 15 MB and 16 MB (0_00F0_0000 to
0_00FF_FFFF) that relays transactions to Hub Interface_A instead of completing them with a
system memory access. This window is opened with the FDHC.HEN configuration field.
4.1.4
I/O APIC Memory Space
The I/O APIC spaces are used to communicate with I/O APIC interrupt controllers that may be
populated on Hub Interface_A through Hub Interface_D. Since it is difficult to relocate an interrupt
controller using plug-and-play software, fixed address decode regions have been allocated for
them. The address ranges are:
•
•
•
•
I/OAPIC0 (HI_A)
0_FEC0_0000h to 0_FEC7_FFFFh
I/OAPIC1 (HI_B)
0_FEC8_0000h to 0_FEC8_0FFFh
I/OAPIC2 (HI_C)
0_FEC8_1000h to 0_FEC8_1FFFh
I/OAPIC3 (HI_D)
0_FEC8_2000h to 0_FEC8_2FFFh
Processor accesses to the I/OAPIC0 region are always sent to Hub Interface_A. Processor accesses
to the I/OAPIC1 region are always sent to Hub Interface_B and so on.
4.1.5
System Bus Interrupt Memory Space
The system bus interrupt space (0_FEE0_0000h to 0_FEEF_FFFFh) is the address used to deliver
interrupts to the system bus. Any device on Hub Interface_A–D may issue a double-word memory
write to 0FEEx_xxxxh. The MCH will forward this memory write along with the data to the system
bus as an Interrupt Message Transaction. The MCH terminates the system bus transaction by
providing the response and asserting TRDY#. This memory write cycle does not go to DRAM.
The processors may also use this region to send inter-processor interrupts (IPI) from one processor
to another.
4.1.6
Device 2 Memory and Prefetchable Memory
Plug-and-play software configures the HI_B memory window to provide enough memory space
for the devices behind this PCI-to-PCI Bridge. Accesses that have addresses that fall within this
window are decoded and forwarded to Hub Interface_B for completion. The address ranges are:
• M2
• PM2
MBASE2 to MLIMIT2
PMBASE2 to PMLIMIT2
Note that these registers must be programmed with values that place the Hub Interface_B memory
space window between the value in the TOLM Register and 4 GB. In addition, neither region
should overlap with any other fixed or relocatable area of memory.
Datasheet
115
System Address Map
4.1.7
Device 3 Memory and Prefetchable Memory
Plug-and-play software configures the Hub Interface_C memory window to provide enough
memory space for the devices behind this PCI-to-PCI Bridge. Accesses that have addresses that fall
within this window are decoded and forwarded to Hub Interface_C for completion.
• M3
• PM3
MBASE3 to MLIMIT3
PMBASE3 to PMLIMIT3
Note that these registers must be programmed with values that place the Hub Interface_C memory
space window between the value in the TOLM Register and 4 GB. In addition, neither region
should overlap with any other fixed or relocatable area of memory.
4.1.8
Device 4 Memory and Prefetchable Memory
Plug-and-play software configures the Hub Interface_D memory window to provide enough
memory space for the devices behind this PCI-to-PCI Bridge. Accesses that have addresses that fall
within this window are decoded and forwarded to Hub Interface_D for completion.
• M4
• PM4
MBASE4 to MLIMIT4
PMBASE4 to PMLIMIT4
Note that these registers must be programmed with values that place the Hub Interface_D memory
space window between the value in the TOLM Register and 4 GB. In addition, neither region
should overlap with any other fixed or relocatable area of memory.
4.1.9
HI_A Subtractive Decode
All accesses that fall between the value programmed into the TOLM Register and 4 GB
(i.e., TOLM and 4 GB) are subtractively decoded and forwarded to Hub Interface_A if they do not
decode to a space that corresponds to another device.
4.1.10
Main Memory Addresses
The high memory and extended memory address regions are together called main memory. Main
memory is composed of address segments that refer to SDRAM system memory. Main memory
addresses are mapped to SDRAM channels, devices, banks, rows, and columns in different ways
depending upon the type of memory being used and the density or organization of the memory.
Refer to Section 1.4.2 for supported DIMM configurations.
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Datasheet
System Address Map
4.2
I/O Address Space
The MCH does not support the existence of any other I/O devices on the system bus. The MCH
generates Hub Interface_A–D bus cycles for all processor I/O accesses. The MCH contains two
internal registers in the processor I/O space, Configuration Address Register (CONF_ADDR) and
the Configuration Data Register (CONF_DATA). These locations are used to implement the
configuration space access mechanism and are described in Device Configuration Registers
section.
The processor allows 64 KB + 3 bytes to be addressed within the I/O space. The MCH propagates
the processor I/O address without any translation to the targeted destination bus. Note that the
upper three locations can be accessed only during I/O address wrap-around when signal A16# is
asserted on the system bus. A16# is asserted on the system bus whenever a DWord I/O access is
made from address 0FFFDh, 0FFFEh, or 0FFFFh. In addition, A16# is asserted when software
attempts a two bytes I/O access from address 0FFFFh.
The I/O accesses (other than ones used for configuration space access) are forwarded normally to
Hub Interface_A–D. All I/O cycles receive a Defer Response. The MCH never posts an I/O write.
The MCH never responds to I/O or configuration cycles initiated on any of the hub interfaces. Hub
interface transactions requiring completion are terminated with “master abort” completion packets
on the hub interfaces. Hub interface I/O write transactions not requiring completion are dropped.
4.3
SMM Space
4.3.1
System Management Mode (SMM) Memory Range
The E7500 chipset supports the use of main memory as System Management RAM (SMM RAM),
which enables the use of System Management Mode. The MCH supports three SMM options:
• Compatible SMRAM (C_SMRAM)
• High Segment (HSEG)
• Top of Memory Segment (TSEG).
System Management RAM space provides a memory area that is available for the SMI handlers
and code and data storage. This memory resource is normally hidden from the system operating
system so the processor has immediate access to this memory space upon entry to SMM. The MCH
provides three SMRAM options:
• Below 1-MB option that supports compatible SMI handlers.
• Above 1-MB option that allows new SMI handlers to execute with write-back cacheable
SMRAM.
• Optional larger write-back cacheable TSEG area from 128 KB to 1 MB in size above 1 MB
that is reserved below the 4 GB in system DRAM memory space. The above 1-MB solutions
require changes to compatible SMRAM handler code to properly execute above 1 MB.
Datasheet
117
System Address Map
4.3.2
TSEG SMM Memory Space
The TSEG SMM space (TOLM – TSEG to TOLM) allows system management software to
partition a region of main memory just below the top of low memory (TOLM) that is accessible
only by system management software. This region may be 128 KB, 256 KB, 512 KB, or 1 MB in
size, depending upon the ESMRAMC.TSEG_SZ field. This space must be below 4 GB, so it is
below TOLM and not the top of physical memory, SMM memory is globally enabled by
SMRAM.G_SMRAME. Requests may access SMM system memory when either SMM space is
open (SMRAM.D_OPEN) or the MCH receives an SMM code request on its system bus. To access
the TSEG SMM space, TSEG must be enabled by ESMRAMC.T_EN. When all of these
conditions are met, a system bus access to the TSEG space (between TOLM–TSEG and TOLM) is
sent to system memory. When the high SMRAM is not enabled or if the TSEG is not enabled,
memory requests from all interfaces are forwarded to system memory. When the TSEG SMM
space is enabled, and an agent attempts a non-SMM access to TSEG space, then the transaction is
specially terminated.
Hub interface originated accesses are not allowed to SMM space.
4.3.3
High SMM Memory Space
The HIGHSMM space (0_FEDA_0000h to 0_FEDB_FFFFh) allows cacheable access to the
compatible SMM space by remapping valid SMM accesses between 0_FEDA_0000h and
0_FEDB_FFFFh to accesses between 0_000A_0000h and 0_000B_FFFFh. The accesses are
remapped when SMRAM space is enabled; an appropriate access is detected on the system bus,
and when ESMRAMC.H_SMRAME allows access to high SMRAM space. SMM memory
accesses from any hub interface are specially terminated: reads are provided with the value from
address 0 while writes are ignored entirely.
4.3.4
SMM Space Restrictions
When any of the following conditions are violated, the results of SMM accesses are unpredictable
and may cause undesirable system behavior:
1. The Compatible SMM space must not be setup as cacheable.
2. Both D_OPEN and D_CLOSE must not be set to 1 at the same time.
3. When TSEG SMM space is enabled, the TSEG space must not be reported to the operating
system as available DRAM. This is a BIOS responsibility.
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Datasheet
System Address Map
4.3.5
SMM Space Definition
SMM space is defined by its addressed SMM space and its DRAM SMM space. The addressed
SMM space is defined as the range of bus addresses used by the processor to access SMM space.
DRAM SMM space is defined as the range of physical DRAM memory locations containing the
SMM code. SMM space can be accessed at one of three transaction address ranges: Compatible,
High, and TSEG. The Compatible and TSEG SMM space is not remapped and, therefore, the
addressed and DRAM SMM space is the same address range. Since the High SMM space is
remapped, the addressed and DRAM SMM space is a different address range. Note that the High
DRAM space is the same as the Compatible Transaction Address space. Table 4-1 describes three
unique address ranges:
• Compatible Transaction Address
• High Transaction Address
• TSEG Transaction Address
Table 4-1. SMM Address Range
SMM Space Enabled
Compatible
High
TSEG
Transaction Address Space
DRAM Space
A0000h to BFFFFh
A0000h to BFFFFh
0FEDA0000h to 0FEDBFFFFh
A0000h to BFFFFh
(TOLM–TSEG_SZ) to TOLM
(TOLM–TSEG_SZ) to TOLM
NOTES:
1. High SMM: This is different than in previous chipsets. In previous chipsets the High segment was the 384 KB
region from A_0000h to F_FFFFh. However, C_0000h to F_FFFFh was not practically useful so it is deleted
in the MCH.
2. TSEG SMM: This is different than in previous chipsets. In previous chipsets the TSEG address space was
offset by 256 MB to allow for simpler decoding and the TSEG was remapped to just under the TOLM. In the
MCH the TSEG region is not offset by 256 MB and it is not remapped.
Datasheet
119
System Address Map
4.4
Memory Reclaim Background
The following memory-mapped I/O devices are typically located below 4 GB:
•
•
•
•
•
•
High BIOS
HSEG
XAPIC
Local APIC
System Bus Interrupts
HI_B, HI_C, HI_D BARs
In previous generation MCHs, the physical main memory overlapped by the logical address space
allocated to these memory-mapped I/O devices was unusable. In server systems the memory
allocated to memory-mapped I/O devices could easily exceed 1 GB. The result is that a large
amount of physical memory would not be usable.
The MCH provides the capability to re-claim the physical memory overlapped by the memory
mapped I/O logical address space. The MCH re-maps physical memory from the Top of Low
Memory (TOLM) boundary up to the 4 GB boundary (or DRB7 if less than 4 GB) to an equivalent
sized logical address range located just above the top of physical memory
4.4.1
Memory Re-Mapping
An incoming address (referred to as a logical address) is checked to see if it falls in the memory remap window. The bottom of the re-map window is defined by the value in the REMAPBASE
Register. The top of the re-map window is defined by the value in the REMAPLIMIT Register. An
address that falls within this window is remapped to the physical memory starting at the address
defined by the TOLM Register.
120
Datasheet
Reliability, Availability, Serviceability, Usability, and Manageability (RASUM)
Reliability, Availability, Serviceability,
Usability, and Manageability (RASUM) 5
The E7500 chipset-based platforms provide the RASUM (Reliability, Availability, Serviceability,
Usability, and Manageability) features required for entry-level and mid-range servers. These
features include: Chipkill technology ECC for memory, ECC for all high-performance I/O, out-ofband manageability through SMBus target interfaces on all major components, memory scrubbing
and auto-initialization, processor thermal monitoring, and hot-plug PCI.
5.1
DRAM ECC
The ECC used for DRAM provides chipkill technology protection for x4 SDRAMs. DRAMS that
are x8 use the same algorithm but will not have chipkill technology protection, since at most only
four bits can be corrected with this ECC.
5.2
DRAM Scrubbing
A special DRAM scrub algorithm will walk through all of main memory doing reads followed by
writes back to the same location. Correctable errors found by the read are corrected and then the
good data is written back to DRAM. A write is done in all cases, whether there were errors or not.
This looks like a read-modify-write of 0 bytes to the system. The scrub unit starts at address 0 upon
reset. Periodically, the unit will scrub one line and then increment the address counter by 64 bytes
or one line. A 16-GB memory array would be completely scrubbed in approximately one day.
5.3
DRAM Auto-Initialization
The DRAM Auto-initialization algorithms initialize memory at reset to ensure that all lines have
valid ECC.
5.4
SMBus Access
The processor will be able to access all configuration registers through host configuration cycles.
Access via SMBus will be R/W to a shadowed set of the RASUM registers in the MCH, and readonly to all non-RASUM registers in the MCH. The SMBus can not use the MCH’s SM-port to
access any registers outside the MCH. The P64H2 and ICH3-S each have their own SMBus target
port. A test mode will be provided to allow the processor to access the shadowed register set.
Shadowing the RASUM registers ensures that BIOS code and system management ASIC firmware
code can execute independently, without interference or synchronization efforts. PCI legacy
registers associated with error reporting will not deviate from prior implementations. SMBus will
have read-only access to the PCI legacy registers.
Datasheet
121
Reliability, Availability, Serviceability, Usability, and Manageability (RASUM)
This page is intentionally left blank.
122
Datasheet
Electrical Characteristics
6
Electrical Characteristics
This chapter provides the absolute maximum ratings, thermal characteristics, and DC
characteristics for the MCH.
6.1
Warning:
Absolute Maximum Ratings
Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage.
These are stress ratings only. Operating beyond the “operating conditions” is not recommended and
extended exposure beyond “operating conditions” may affect reliability.
Table 6-1. Absolute Maximum Ratings
Symbol
6.2
Parameter
Min
Max
Unit
-55
150
°C
Tstorage
Storage Temperature
VCC_MCH
1.2 V Supply Voltage with respect to VSS
-0.38
2.1
V
VTT_AGTL
Supply Voltage input with respect to VSS
-0.38
2.1
V
VDD_DDR
DDR Buffer Supply Voltage
2
3
V
Notes
Thermal Characteristics
The MCH is designed for operation at die temperatures between 0 °C and 110 °C. The thermal
resistance of the package is given in Table 6-2.
Table 6-2. MCH Package Thermal Resistance
Air Flow
Parameter
No Air Flow (0 Meter/Second)
1.0 Meter/Second 2
Psijt (°C/Watt) 1
0.5
1.0
Thetaja (°C/Watt) 1
13.0
11.2
NOTES:
1. Typical value measured in accordance with EIA/JESD 51-2 testing standard.
2. 1 meter/second is equivalent to 196.9 linear feet/minute
Datasheet
123
Electrical Characteristics
6.3
Power Characteristics
Table 6-3. Thermal Power Dissipation (VCC1_2 = 1.2 V ±5%)
Symbol
PMCH
Parameter
Min
Thermal Power Dissipation for MCH
Typ
Max
Unit
Notes
11.6
15.6
W
1
NOTES:
1. TDP Typ is the Thermal Design Power (11.6 W) and it is the estimated maximum possible expected power
generated in a component by a realistic application. It is based on extrapolations in both hardware and
software technology over the life of the component. It does not represent the expected power generated by a
power virus. Studies by Intel indicate that no useful application will cause thermally significant power
dissipation exceeding the TDP Typ specification, although it is possible to concoct higher power synthetic
workloads as reflected in the TDP Max specification.
Table 6-4. DC Characteristics Functional Operating Range (VCC1_2 = 1.2 V ±5%)
Symbol
124
Parameter
Min
Typ
Max
Unit
ICC
1.2 V Plumas Core and HI
3.1
A
IVTT
1.55 V AGTL
2.0
A
Idd_DDR
2.5 V VDD DDR (2 channel)
7
A
Notes
Datasheet
Electrical Characteristics
6.4
I/O Interface Signal Groupings
The signal description includes the type of buffer used for the particular signal:
• AGTL+
Open Drain AGTL+ interface signal. Refer to the AGTL+ I/O Specification for
complete details. The MCH integrates AGTL+ termination resistors.
• CMOS
• DDR
1.2 V CMOS buffers.
DDR SDRAM signaling Interface
Table 6-5. Signal Groups System Bus Interface
Signal
Group
Signal Type
Signals
(a)
AGTL+ I/O
AP[1:0]#, ADS#, BNR#, DBSY#, DP[3:0]#, DRDY#,
HA[35:3]#, HADSTB[1:0] #, HD[63:0] #,
HDSTBP[3:0]#, HDSTBN[3:0]#, HIT#, HITM#,
HREQ[4:0]#, BREQ0#, DBI[3;0]#
(b)
AGTL+ Output
BPRI#, CPURST#, DEFER#, HTRDY#, RS [2:0]#,
RSP#
(c)
AGTL+ Input
HLOCK#, XERR#
(d)
Host Reference Voltage
HDVREF[3:0], HAVREF[1:0], HCCVREF
(e)
Host Voltage Swing
HXSWING, HYSWING
(f)
Host Compensation
HXRCOMP, HYRCOMP
(g)
CLK Inputs
HCLKINN, HCLKINP
(h)
AGTL + Termination Voltage
VTT
Notes
Table 6-6. Signal Groups DDR Interface
Signal
Group
Signal Type
Signals
Notes
(i)
DDR I/O
DQ_x [63:0], CB_x [7:0], DQS_x [17:0]
1
(j)
DDR Output
CMDCLK_x [3:0], CMDCLK_x#[3:0], MA_x [12:0],
BA_x [1:0], RAS_x#, CAS_x#, WE_x#, CS_x
[7:0]#, CKE_x, RCVENOUT_x#
1
(k)
DDR Input
RCVENIN_x#
1
(l)
DDR Compensation CMOS I/O
DDRCOMP_x
1
(m)
DDR Compensation for
impedance control
DDRCVOH_x, DDRCVOL_x
1
(n)
DDR Reference Voltage
DDRVREF_x [5:0]
1
NOTES:
1. x = A, B DDR channel
Datasheet
125
Electrical Characteristics
Table 6-7. Signal Groups Hub Interface 2.0 (HI_B–D)
Signal
Group
(o)
Signal Type
Signals
Notes
Hub Interface CMOS I/O
HI_x [21:0], PSTRBF_x, PSTRBS_x
1
(p)
Hub Interface CMOS Input Clock
CLK66
2
(q)
Hub Interface Reference Voltage
Input
HIVREF_x
1
(r)
Hub Interface Voltage Swing
HISWNG_x
1
(s)
Hub Interface Compensation
CMOS I/O
HIRCOMP_x
1
NOTES:
1. x = B, C, D (referencing Hub Interface_B–D).
2. CLK66 is shared on HI 1.5 and HI 2.0
Table 6-8. Signal Groups Hub Interface 1.5 (HI_A)
Signal
Group
Signal Type
Signals
(t)
Hub Interface CMOS I/O
HI_A [11:0], HI_STBF, HI_STBS
(u)
Hub Interface CMOS Input Clock
CLK66
(v)
Hub Interface Reference Voltage
Input
HIVREF_A
(w)
Hub Interface Voltage Swing
HISWNG_A
(x)
Hub Interface Compensation
CMOS I/O
HIRCOMP_A
Notes
1
NOTES:
1. CLK66 is shared on HI 1.5 and HI 2.0
Table 6-9. Signal Groups SMBus
Signal
Group
(y)
Signal Type
SMBus I/O Buffer
Signals
Notes
SMB_CLK, SMB_DATA
Table 6-10. Signal Groups Reset and Miscellaneous
Signal
Group
(z)
126
Signal Type
Miscellaneous CMOS Input
Signals
Notes
RSTIN#, PWRGOOD, XORMODE#
Datasheet
Electrical Characteristics
6.5
DC Characteristics
Table 6-11. Operating Condition Supply Voltage (VCC1_2 = 1.2 V ±5%)
Symbol
VTT
Signal
Group
(h)
Parameter
Min
Nom
Max
Unit
Host AGTL+ Termination Voltage
1.15
1.3
1.45
V
VDD_DDR
DDR Buffer Voltage
2.3
2.5
2.7
V
VCC_MCH
1.2 V Supply voltage
1.14
1.2
1.26
V
Notes
Table 6-12. System Bus Interface (VCC1_2 = 1.2 V ±5%)
Symbol
Signal
Group
Parameter
VIL_H
(a), (c)
Host AGTL+ Input Low Voltage
VIH_H
(a), (c)
Host AGTL+ Input High Voltage
VOL_H
(a), (b)
Host AGTL+ Output Low Voltage
VOH_H
(a), (b)
Host AGTL+ Output High Voltage
RTT
Host termination Resistance
Min
Nom
Max
Unit
(2/3 x VTT)
– 0.1GTLREF
V
(2/3 x VTT)
+ 0.1GTLREF
V
1/3 x VTT
VTT–0.1
VTT
46
50
(1/3 x VTT)
+ 0.1GTLREF
V
V
54
W
(2/3 x VTTmax) /
RTT min
A
IOL_H
(a), (b)
Host AGTL+ Output Low Leakage
IL_H
(a), (c)
Host AGTL+ Input Leakage
Current
10
CPAD
(a), (c)
Host AGTL+ Input Capacitance
1
CCVREF
(d)
Host Common clock Reference
Voltage
2/3 x VTT
V
HxVREF
(d)
Host Address and Data
Reference Voltage
2/3 x VTT
V
HXSWNG,
HYSWNG
(e)
Host Compensation Reference
Voltage
1/3 x VTT
V
Datasheet
Notes
µA
3.5
pF
127
Electrical Characteristics
Table 6-13. DDR Interface (VCC1_2 = 1.2 V ±5%)
Symbol
Parameter
Min
Nom
Max
DDRVREF
– 0.150
Unit
VIL (DC)
(i), (k)
DDR Input Low Voltage
VIH (DC)
(i), (k)
DDR Input High Voltage
VIL (AC)
(i), (k)
DDR Input Low Voltage
VIH (AC)
(i), (k)
DDR Input High Voltage
DDRVREF
+0.310
VOL
(i), (j)
DDR Output Low Voltage
0
0.7
V
VOH
(i), (j)
DDR Output High Voltage
1.7
VDD_DDR
V
C Out
(i), (k)
DDR Input Pin Capacitance
2.5
5
pF
I OL (DC)
(i), (j)
DDR Output Low Current
-50
mA
I OH
(i), (j)
DDR Output High Current
50
mA
I OL (AC)
(i), (j)
DDR Output Low Current
50
mA
I OH (AC)
(i), (j)
DDR Output High Current
50
mA
I Leak
(i), (k)
Input Leakage Current
50
µA
CIN
(i), (k)
Input Pin Capacitance
5
pF
DDRVREF
128
Signal
Group
(n)
DDR Reference Voltage
Notes
V
DDRVREF
+ 0.150
V
DDRVREF
–0.310
2.5
VDD_DDR/2
V
Datasheet
Electrical Characteristics
Table 6-14. Hub Interface 2.0 Configured for 50 Ω (VCC1_2 = 1.2 V ±5%)
Signal
Group
Symbol
Parameter
Min
Nom
Max
Unit
0
HIVREF–0.1
V
Notes
VIL_HI
(o)
Hub Interface Input Low Voltage
VIH_HI
(o)
Hub Interface Input High Voltage
HIVREF
+0.1
0.7
—
V
VOL_HI
(o)
Hub Interface Output Low Voltage
-0.03
0
0.05
V
1
VOHT_HI
(o)
Hub Interface Terminator High
Voltage
HISWNG
–0.50
HISWNG
+0.50
V
2
VOHD_HI
(o)
Hub Interface Output High Voltage
HISWNG
–0.50
HISWNG
+0.50
V
2
IIL_HI
(o)
Hub Interface Input Leakage Current
25
µA
CIN_HI
(o)
Hub Interface Input Pin Capacitance
3.5
pF
0.50
pF
5
nH
∆CIN
Strobe to Data Pin Capacitance
Delta
LPIN
Pin Inductance (Signal)
ZPD
Pull-Down Impedance
ZPU
Pull-Up Impedance
VCCP
-0.50
45
50
55
Ω
22.5
25
27.5
Ω
I/O Supply Voltage
CClk
(p)
CLK66 Pin Capacitance
HIVREF_x
(q)
Hub Interface Reference Voltage
HISWNG_x
(r)
Hub Interface Swing Reference
Voltage
HIRCOMP_x
(s)
Hub Interface Compensation
Resistance
1.2
0.343
0.35
V
0.025
V
0.357
V
0.8
24.75
25
V
25.25
Ω
NOTES:
1. VOL is measured at IOUT = 1.0 mA
2. There are two VOH specifications. VOHT applies when the pin is in receive (terminating) mode and tests the
strength of the terminator / pull-down device. VOHT is measured with the specified pull-up resistor tied to
VDDHI. VOHD applies when the pin is driving a high level and tests the strength of the pull-up device. VOHD is
measured into a standard resistive load to ground representing the target impedance of the receiver
terminator (ZTARG). The output driver is also responsible for not driving the receiver higher than the maximum
VIH. This represents the absolute maximum allowed voltage allowed on the receiver pin (i.e., VOH due to
incomplete impedance updates on the drivers and terminator). This specification allows inter-operation
between devices over many process generations. A given platform where the devices have higher voltage
tolerances may specify a higher VIH (max).
Datasheet
129
Electrical Characteristics
Table 6-15. Hub Interface 1.5 with Parallel Buffer Mode Configured for 50 Ω
(VCC1_2 = 1.2 V ±5%)
Signal
Group
Symbol
Parameter
Min
Nom
Max
Unit
0
HIVREF–0.1
V
HIVREF+0.1
0.7
—
V
0
Notes
VIL_HI
(t)
Hub Interface Input Low Voltage
VIH_HI
(t)
Hub Interface Input High Voltage
VOL_HI
(t)
Hub Interface Output Low Voltage
-0.03
0.05
V
1
VOHT_HI
(t)
Hub Interface Terminator Voltage
HISWNG–0.50
HISWNG+0.50
V
2
VOHD_HI
(t)
Hub Interface Output High Voltage
HISWNG–0.50
HISWNG+0.50
V
2
IIL_HI
(t)
Hub Interface Input Leakage
Current
25
µA
CIN_HI
(t)
Hub Interface Input Pin
Capacitance
3.5
pF
0.50
pF
5
nH
∆CIN
Strobe to Data Pin Capacitance
delta
LPIN
Pin Inductance (Signal)
ZPD
Pull-down Impedance
ZPU
Pull-up Impedance
VCCP
I/O Supply Voltage
CClk
(u)
HIVREF_A
(v)
Hub Interface Reference Voltage
HISWNG_A
(w)
Hub Interface Swing Reference
Voltage
HIRCOMP_A
(x)
Hub Interface Compensation
Resistance
-0.50
45
50
55
Ω
22.5
25
27.5
Ω
1.2
CLK66 Pin Capacitance
0.343
0.35
V
0.025
V
0.357
V
0.8
24.75
25
V
25.25
3
Ω
NOTES:
1. VOL is measured at IOUT = 1.0 mA
2. There are two VOH specifications. VOHT applies when the pin is in receive (terminating) mode and tests the
strength of the terminator / pull-down device. VOHT is measured with the specified pull-up resistor tied to
VDDHI. VOHD applies when the pin is driving a high level and tests the strength of the pull-up device. VOHD is
measured into a standard resistive load to ground representing the target impedance of the receiver
terminator (ZTARG). The output driver is also responsible for not driving the receiver higher than the maximum
VIH. This represents the absolute maximum allowed voltage allowed on the receiver pin (i.e., VOH due to
incomplete impedance updates on the drivers and terminator). This specification allows inter-operation
between devices over many process generations. A given platform where the devices have higher voltage
tolerances may specify a higher VIH (max).
3. For Hub Interface 1.5, a HISWNG of 0.8 V is recommended, but a value of 0.7 V is allowed as long as
system validation is performed.
130
Datasheet
Ballout and Package Specifications
7
Ballout and Package Specifications
This chapter provides the ballout and package dimensions for the E7500 MCH. In addition,
internal component package trace lengths to enable trace length compensation are listed.
7.1
Ballout
Figure 7-1 shows a top view of the ballout footprint. Figure 7-2 and Figure 7-3 expand the detail of
the ballout footprint to list the signal names for each ball. Table 7-1 lists the MCH ballout with the
listing organized alphabetically by signal name.
Figure 7-1. Intel® E7500 MCH Ballout (Top View)
AN
AM
AL
AK
AJ
AH
AG
AF
AE
AD
AC
AB
AA
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
E
C
B
A
33
Datasheet
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
131
Ballout and Package Specifications
Intel® E7500 MCH Ballout (Left Half of Top View)
Figure 7-2.
33
32
31
30
29
VSS
VCC2_5
DQ4_A
VCC2_5
MA12_A
MA9_A
VSS
AN
AM
28
27
26
25
24
DQ1_A
VSS
DQ5_A
DQS0_A
VCC2_5
DQ8_A
RAS_A#
VSS
DQ12_A
DQ9_A
23
22
21
20
VSS
VCC2_5
DQ30_A
DQ20_A
VSS
RCVENIN
_A#
DQ26_A
VSS
19
18
17
VSS
VCC2_5
DQ18_A
DQ21_A
Reserved
VSS
AL
VSS
DQ60_B
BA0_A
VSS
MA7_A
MA6_A
VSS
DQ6_A
DQ7_A
VCC2_5
DQS1_A
DQ14_A
VSS
DQ27_A
DQ17_A
VSS
DQ22_A
AK
VCC2_5
CS1_B#
VSS
MA11_A
MA8_A
VSS
DDRVREF
4_A
MA1_A
VSS
DQ13_A
DQS10_A
VSS
DDRV
REF3_A
DQS12_A
DQ16_A
DQS11_A
DDRC
VOH_A
AJ
VSS
VSS
DQ61_B
DQ56_B
VCC2_5
DDRVREF
5_A
MA3_A
VCC2_5
CMDCLK1
MA10_A
_A
VCC2_5
DQ15_A
DQ29_A
VCC2_5
DQ31_A
DQ23_A
VCC2_5
AH
DQ55_B
DQ50_B
DQ51_B
VSS
CS0_B#
MA5_A
VSS
MA2_A
CMDCLK1
_A#
BA1_A
DQ3_A
VSS
DQ28_A
DQ25_A
VSS
DDRCOM
P_A
AG
DQ38_B
DDRV
REF1_B
VSS
DQ54_B
DQ57_B
VCC2_5
MA4_A
CMDCLK2
_A
VSS
VCC2_5
DQ10_A
RCVEN
OUT_A#
VCC2_5
DQS2_A
CB5_A
AF
VCC2_5
VSS
DQ34_B
CS2_B#
VSS
DQS16_B
CS3_B#
VSS
CMDCLK2
_A#
VCC2_5
DQ0_A
DQS9_A
VSS
DQ24_A
DQ19_A
VSS
AE
DQ33_B
DQS4_B
CS4_B#
VCC2_5
VSS
DQS6_B
DQS7_B
CS5_B#
WE_A#
CAS_A#
DQ2_A
DQ11_A
CKE_A
DQS3_A
CB4_A
AD
VCC2_5
DQ37_B
DQ43_B
VSS
VCC2_5
CS6_B#
DQS15_B
VSS
VCC2_5
VCC2_5
VSS
VCC2_5
VSS
VCC2_5
VSS
VCC2_5
VSS
AC
VSS
VSS
DQS5_B
DQS13_B
VSS
DQ52_B
DQ62_B
VSS
DDR
VREF0_B
VSS
VCC2_5
VSS
VCC2_5
VSS
VCC2_5
VSS
VCC2_5
AB
DQ41_B
DQ45_B
VCC2_5
DQS14_B
DQ46_B
VSS
DQ49_B
DQ63_ B
DQ58_B
VCC2_5
VSS
AA
CB3_B
CB7_B
CB6_B
VSS
DQ40_B
DQ36_B
VCC2_5
DQ53_B
DQ59_B
VSS
VCC2_5
Y
VCC2_5
VSS
CB2_B
DQS17_B
VCC2_5
DQ44_B
CS7_B#
VSS
DQ48_B
VCC2_5
VSS
VCCA1_2
VSS
VCCA1_2
VSS
W
VSS
DDR
CVOH_B
VSS
DDR
COMP_B
DQS8_B
VSS
DQ32_B
DQ39_B
DQ35_B
VSS
VCC2_5
VSS
VCC1_2
VSS
VCC1_2
V
DQ22_B
RAS_B#
DQ23_B
VSS
DDRC
VOL_B
CB0_B
VSS
DQ42_B
DQ47_B
VCC2_5
VSS
VCCA1_2
VSS
VCC1_2
VSS
U
DQS2_B
VSS
DQS11_B
DQ18_B
VCC2_5
CB4_B
CB5_B
DDR
VREF2_B
CB1_B
VSS
VCC2_5
VSS
VCC1_2
VSS
VCC1_2
VSS
CMDCLK0 CMDCLK0
_A
_A#
MA0_A
CMDCLK3 CMDCLK3
_A
_A#
T
VCC2_5
DQ27_B
VCC2_5
DQ17_B
DQ16_B
VSS
DQ21_B
DQ19_B
DQ31_B
VCC2_5
VSS
VCCA1_2
VSS
VCC1_2
VSS
R
VSS
DQ20_B
DQS12_B
VSS
DQS3_B
DQ30_B
VSS
DQ26_B
RCVEN
OUT_B#
VSS
VCC2_5
VSS
VCC1_2
VSS
VCC1_2
P
DQ25_B
VSS
DQ29_B
DQ24_B
VCC2_5
DQ15_B
DQ10_B
DQ14_B
DQ11_B
VCC2_5
VSS
VCCA1_2
VSS
VCC1_2
VSS
N
DDR
VREF3_B
DQ28_B
VSS
VSS
DQ4_B
DQ7_B
DQ3_B
VSS
VCC2_5
M
VCC2_5
CKE_B
DQS1_B
VSS
DQ6_B
CMDCLK1
_B#
VSS
MA0_B
DDR
VREF4_B
VCC2_5
VSS
L
VSS
VSS
DQ13_B
DQS0_B
VCC2_5
CMDCLK1 CMDCLK3
_B
_B#
VCC2_5
MA10_B
VSS
VCC2_5
VCC1_2
VSS
VCC1_2
VSS
VCC1_2
VSS
K
Reserved
DQ9_B
VCC2_5
DQ1_B
MA1_B
VCC1_2
VSS
VCC1_2
VSS
VCC1_2
VSS
VCC1_2
J
DQ8_B
DQ2_B
DQ12_B
VSS
VSS
VSS
HI
VREF_D
VSS
VSS
VSS
VSS
VSS
H
VCC2_5
VSS
DQS9_B
MA2_B
VCC2_5
CAS_B#
BA1_B
VSS
HI17_D
HI6_D
HI16_D
VSS
HI21_D
VCC1_2
VCC1_2
HI20_C
HISWNG
_C
G
VSS
DQ5_B
VSS
MA3_B
MA5_B
VSS
VCC2_5
HI2_D
HI1_D
HI4_D
VSS
HI8_D
HIRCOMP
_D
VSS
VSS
HI2_C
VSS
F
DQ0_B
MA4_B
MA6_B
VSS
MA9_B
VSS
VSS
HI3_D
HI18_D
HISWNG
_D
HI14_D
HI15_D
VSS
HI18_C
HI5_C
VSS
HI15_C
E
MA7_B
VSS
MA8_B
DDR
VREF5_B
VCC2_5
RSTIN#
HI20_D
VCC1_2
VSS
HI9_D
HI13_D
VCC1_2
HI7_C
HI4_C
VCC1_2
HI14_C
PUSTRBS
_C
D
VCC2_5
WE_B#
VSS
VSS
Reserved
HI0_D
PSTRBF
_D
PSTRBS
_D
VSS
HI11_D
VSS
HI0_C
HI6_C
VSS
HI8_C
PUSTRBF
_C
VSS
C
VSS
MA12_B
MA11_B
VSS
XOR
MODE#
VSS
VSS
HI7_D
PUSTRBS
_D
HI17_C
PSTRBF
_C
HI3_C
VSS
HIRCOMP
_C
HI11_C
HI13_C
HI2_B
VCC2_5
SMB
_DATA
Reserved
VSS
VCC1_2
VSS
VSS
PUSTRBF
_D
HI1_C
PSTRBS
_C
VSS
HI16_C
HI10_C
VSS
HI12_C
HI17_B
VSS
VCC1_2
VSS
PWR
GOOD
HI5_D
VCC1_2
HI10_D
HI12_D
VSS
VCC1_2
HIVREF
_C
HI9_C
VSS
VCC1_2
HI4_B
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
B
A
33
132
32
RCVENIN
DQS10_B
_B#
VSS
CMDCLK0 CMDCLK0
_B
_B#
CMDCLK3
_B
VSS
BA0_B
CMDCLK2
VCC2_5
_B#
CMDCLK2
SMB_CLK
_B
Datasheet
Ballout and Package Specifications
Figure 7-3.
Intel® E7500 MCH Ballout (Right Half of Top View)
16
15
14
13
12
11
10
9
8
7
6
5
4
3
DDRCVOL
_A
2
1
VSS
VCC2_5
DQ37_A
DQ42_A
VSS
VCC2_5
VSS
CS4_A#
VCC2_5
VSS
DQ51_A
VCC2_5
VSS
DDR
VREF2_A
CB6_A
VSS
DQ33_A
DQS5_A
VSS
DQ47_A
DQ54_A
VSS
DQS15_A
DQ55_A
VSS
DQ63_A
DQ58_A
DQ59_A
CB2_A
VCC2_5
DQ32_A
DQS4_A
VSS
DQ43_A
CS2_A#
DDR
VREF1_A
DQS6_A
VSS
DQS7_A
DQ62_A
VSS
CS6_A#
CS7_A#
VCC2_5
AL
VSS
CB3_A
DQ36_A
VSS
DQS14_A
CS1_A#
VCC2_5
VSS
VCC2_5
CS5_A#
VSS
AP1#
RSP#
VSS
xERR#
VSS
AK
DQS8_A
DQ34_A
VCC2_5
DQS13_A
DQ46_A
VCC2_5
VSS
DQ57_A
VSS
DDR
VREF0_A
AP0#
VCC_CPU
HA27#
HAVREF1
VSS
HA34#
AJ
CB1_A
VSS
DQ38_A
DQ41_A
VSS
DQ49_A
DQ60_A
DQS16_A
CS3_A#
VSS
HA33#
HA31#
VSS
HA21#
HA20#
VCC_CPU
AH
VSS
CB7_A
DQ39_A
VCC2_5
DQ52_A
DQ50_A
DQ56_A
VSS
BINIT#
HA32#
VSS
HA35#
HA26#
VCC_CPU
HA22#
VSS
AG
HA25#
AF
AN
AM
DQS17_A
DQ35_A
VSS
DQ45_A
DQ53_A
VSS
VSS
BREQ0#
VSS
HA30#
HA23#
VCC_CPU
HAVREF0
HA29#
VSS
CB0_A
DQ44_A
DQ40_A
CS0_A#
DQ48_A
DQ61_A
VCC2_5
VSS
HA28#
VCC_CPU
HA14#
HA10#
VSS
HA15#
HA11#
HADSTB0# AE
VCC2_5
VSS
VCC2_5
VSS
VCC2_5
VSS
VSS
VSS
HA24#
HADSTB1#
VSS
HA16#
HA9#
VSS
HA6#
VCC_CPU
AD
VSS
VCC2_5
VSS
VCC2_5
VSS
VSS
VCC_CPU
HA19#
VSS
HA18#
HA12#
VCC_CPU
HA8#
HA5#
VSS
VSS
AC
VCC_CPU
VSS
HA13#
HA17#
VSS
HA7#
VSS
VSS
HREQ3#
HREQ0#
HA4#
AB
VSS
VCC_CPU
VSS
HA3#
HREQ2#
VSS
DP2#
DP3#
VSS
DP1#
HREQ1#
AA
VSS
HREQ4#
VSS
ADS#
DP0#
DRDY#
VSS
VCC_CPU
Y
DEFER#
VCC_CPU
DBSY#
HITM#
VSS
HTRDY#
VSS
VSS
W
VCCA1_2
VSS
VCCA1_2
VCC_CPU
VSS
VCC1_2
VSS
VSS
VCC1_2
VSS
VCC1_2
VCC_CPU
VSS
VSS
HXSWING
HLOCK#
VSS
RS1#
HXRCOMP
VSS
RS0#
BNR#
V
VSS
VCCA
CPU1_2
VSS
VSS
VCC_CPU
VSS
VSS
HD59#
BPRI#
VCC_CPU
RS2#
HCLKINN
VSS
HIT#
U
VCC1_2
VSS
VCC1_2
VCC_CPU
VSS
HD60#
HD63#
HDVREF3
HD57#
HD61#
VSS
HD58#
HCLKINP
VCC_CPU
T
VSS
VCC1_2
VSS
VSS
VCC_CPU
VSS
HD47#
HD46#
VSS
HD62#
HD56#
VSS
R
VCCAHI1
_2
VSS
VCC1_2
VCC_CPU
VSS
HD42#
VSS
HD44#
VSS
VCC_CPU
VSS
HDVREF1
HD45#
VCC_CPU CPURST#
HCCVREF VCC_CPU
HDVREF2 VCC_CPU
HD40#
HDSTBN3# VCC_CPU
HD50#
HDSTBP3#
VSS
DBI3#
P
VSS
HD49#
HD54#
HD53#
HD55#
N
VCC_CPU
VSS
VSS
HD24#
HD31#
VSS
VSS
HD43#
VSS
HD51#
VCC_CPU
M
VCC1_2
VSS
VCC1_2
VSS
VCC1_2
VSS
VCC_CPU
VSS
VSS
HD17#
HD18#
VCC_CPU
DBI2#
HD48#
HD52#
VSS
L
VSS
VCC1_2
VSS
VCC1_2
VSS
VCC1_2
VSS
VCC_CPU
VSS
VSS
HD35#
HD38#
HD39#
K
CLK66
VSS
HI15_B
HI8_A
VSS
HI6_A
HI9_A
VSS
HD14#
HD15#
HDSTBP2#
VSS
HDSTBN2#
HD37#
J
VSS
PSTRBS_B
HI16_B
VSS
HISWNG
_A
HIRCOMP
_A
VSS
HI7_A
VSS
HD12#
HD32#
HD33#
VSS
VCC_CPU
H
VCC_CPU HDSTBN1# HYSWING
VSS
HD41#
HDSTBP1# VCC_CPU
HI1_B
PSTRBF_B
VSS
HI21_B
HI11_A
VSS
HI2_A
HIVREF_A
VSS
VSS
HD20#
HYRCOMP
VSS
HD36#
HD34#
VSS
G
HI21_C
VSS
HI20_B
HI9_B
VSS
HI10_A
HI3_A
VSS
DBI0#
HD16#
VSS
HD22#
HD26#
VCC_CPU
HD28#
HD30#
F
VCC1_2
HIRCOMP
_B
HI18_B
VCC1_2
HI13_B
HI0_A
VCC1_2
HI5_A
HD4#
VCC_CPU
HD19#
VSS
HD23#
HD29#
VSS
HD25#
E
HI0_B
HI7_B
VSS
HIVREF_B
HI12_B
VSS
HI_STBS
HI4_A
VSS
HD11#
HD21#
VCC_CPU
VSS
HD27#
DBI1#
VCC_CPU
D
HI3_B
VSS
HI8_B
HI11_B
VSS
HI14_B
HI_STBF
VSS
HD7#
HD10#
VSS
HDVREF0
HD9#
VCC_CPU
HD13#
VSS
C
VSS
HISWNG
_B
HI6_B
VSS
PUSTRBS
_B
HI1_A
VSS
HD0#
HDSTBP0#
VSS
HDSTBN0#
HD3#
VSS
HD5#
VSS
HI5_B
VSS
VCC1_2
HI10_B
PUSTRBF
_B
VSS
VCC1_2
HD1#
HD8#
VSS
VCC_CPU
HD6#
HD2#
VSS
16
15
14
13
12
11
10
9
8
7
6
5
4
3
Datasheet
B
A
2
1
133
Ballout and Package Specifications
Table 7-1. MCH Signal List
134
Table 7-1. MCH Signal List
Table 7-1. MCH Signal List
Signal Name
Ball #
Signal Name
Ball #
Signal Name
Ball #
ADS#
AP0#
AP1#
BA0_A
BA0_B
BA1_A
BA1_B
BINIT#
BNR#
BPRI#
BREQ0#
CAS_A#
CAS_B#
CB0_A
CB0_B
CB1_A
CB1_B
CB2_A
CB2_B
CB3_A
CB3_B
CB4_A
CB4_B
CB5_A
CB5_B
CB6_A
CB6_B
CB7_A
CB7_B
CKE_A
CKE_B
CLK66
CMDCLK0_A
CMDCLK0_A#
CMDCLK0_B
CMDCLK0_B#
CMDCLK1_A
CMDCLK1_A#
CMDCLK1_B
CMDCLK1_B#
CMDCLK2_A
CMDCLK2_A#
CMDCLK2_B
CMDCLK2_B#
CMDCLK3_A
CMDCLK3_A#
CMDCLK3_B
CMDCLK3_B#
CPURST#
CS0_A#
CS0_B#
Y7
AJ6
AK5
AL31
K26
AH23
H27
AG8
V1
U6
AF9
AE22
H28
AE16
V28
AH16
U25
AL16
Y31
AK15
AA33
AE17
U28
AG17
U27
AM15
AA31
AG15
AA32
AE19
M32
J16
AG24
AG23
J29
J28
AJ25
AH25
L28
M28
AG26
AF25
J26
K25
AE25
AE24
K27
L27
W9
AE13
AH29
CS1_A#
CS1_B#
CS2_A#
CS2_B#
CS3_A#
CS3_B#
CS4_A#
CS4_B#
CS5_A#
CS5_B#
CS6_A#
CS6_B#
CS7_A#
CS7_B#
DBI0#
DBI1#
DBI2#
DBI3#
DBSY#
DDRCOMP_A
DDRCOMP_B
DDRCVOH_A
DDRCVOH_B
DDRCVOL_A
DDRCVOL_B
DDRVREF0_A
DDRVREF0_B
DDRVREF1_A
DDRVREF1_B
DDRVREF2_A
DDRVREF2_B
DDRVREF3_A
DDRVREF3_B
DDRVREF4_A
DDRVREF4_B
DDRVREF5_A
DDRVREF5_B
DEFER#
DP0#
DP1#
DP2#
DP3#
DQ0_A
DQ0_B
DQ1_A
DQ1_B
DQ2_A
DQ2_B
DQ3_A
DQ3_B
DQ4_A
AK11
AK32
AL10
AF30
AH8
AF27
AN8
AE31
AK7
AE26
AL3
AD28
AL2
Y27
F8
D2
L4
P1
W6
AH17
W30
AK17
W32
AN16
V29
AJ7
AC25
AL9
AG32
AM16
U26
AK21
N33
AK27
M25
AJ28
E30
W8
Y4
AA2
AA5
AA4
AF22
F33
AN28
K30
AE21
J32
AH22
N25
AN29
DQ4_B
DQ5_A
DQ5_B
DQ6_A
DQ6_B
DQ7_A
DQ7_B
DQ8_A
DQ8_B
DQ9_A
DQ9_B
DQ10_A
DQ10_B
DQ11_A
DQ11_B
DQ12_A
DQ12_B
DQ13_A
DQ13_B
DQ14_A
DQ14_B
DQ15_A
DQ15_B
DQ16_A
DQ16_B
DQ17_A
DQ17_B
DQ18_A
DQ18_B
DQ19_A
DQ19_B
DQ20_A
DQ20_B
DQ21_A
DQ21_B
DQ22_A
DQ22_B
DQ23_A
DQ23_B
DQ24_A
DQ24_B
DQ25_A
DQ25_B
DQ26_A
DQ26_B
DQ27_A
DQ27_B
DQ28_A
DQ28_B
DQ29_A
DQ29_B
N27
AM28
G32
AL26
M29
AL25
N26
AN25
J33
AM24
K32
AG21
P27
AE20
P25
AM25
J31
AK24
L31
AL22
P26
AJ22
P28
AK19
T29
AL19
T30
AN17
U30
AF18
T26
AN20
R32
AM19
T27
AL17
V33
AJ18
V31
AF19
P30
AH19
P33
AM21
R26
AL20
T32
AH20
N32
AJ21
P31
Datasheet
Ballout and Package Specifications
Table 7-1. MCH Signal List
Datasheet
Table 7-1. MCH Signal List
Table 7-1. MCH Signal List
Signal Name
Ball #
Signal Name
Ball #
Signal Name
Ball #
DQ30_A
DQ30_B
DQ31_A
DQ31_B
DQ32_A
DQ32_B
DQ33_A
DQ33_B
DQ34_A
DQ34_B
DQ35_A
DQ35_B
DQ36_A
DQ36_B
DQ37_A
DQ37_B
DQ38_A
DQ38_B
DQ39_A
DQ39_B
DQ40_A
DQ40_B
DQ41_A
DQ41_B
DQ42_A
DQ42_B
DQ43_A
DQ43_B
DQ44_A
DQ44_B
DQ45_A
DQ45_B
DQ46_A
DQ46_B
DQ47_A
DQ47_B
DQ48_A
DQ48_B
DQ49_A
DQ49_B
DQ50_A
DQ50_B
DQ51_A
DQ51_B
DQ52_A
DQ52_B
DQ53_A
DQ53_B
DQ54_A
DQ54_B
DQ55_A
AN21
R28
AJ19
T25
AL14
W27
AM13
AE33
AJ15
AF31
AF15
W25
AK14
AA28
AN13
AD32
AH14
AG33
AG14
W26
AE14
AA29
AH13
AB33
AN12
V26
AL11
AD31
AE15
Y28
AF13
AB32
AJ12
AB29
AM10
V25
AE12
Y25
AH11
AB27
AG11
AH32
AN5
AH31
AG12
AC28
AF12
AA26
AM9
AG30
AM6
DQ55_B
DQ56_A
DQ56_B
DQ57_A
DQ57_B
DQ58_A
DQ58_B
DQ59_A
DQ59_B
DQ60_A
DQ60_B
DQ61_A
DQ61_B
DQ62_A
DQ62_B
DQ63_A
DQ63_B
DQS0_A
DQS0_B
DQS1_A
DQS1_B
DQS2_A
DQS2_B
DQS3_A
DQS3_B
DQS4_A
DQS4_B
DQS5_A
DQS5_B
DQS6_A
DQS6_B
DQS7_A
DQS7_B
DQS8_A
DQS8_B
DQS9_A
DQS9_B
DQS10_A
DQS10_B
DQS11_A
DQS11_B
DQS12_A
DQS12_B
DQS13_A
DQS13_B
DQS14_A
DQS14_B
DQS15_A
DQS15_B
DQS16_A
DQS16_B
AH33
AG10
AJ30
AJ9
AG29
AM3
AB25
AM2
AA25
AH10
AL32
AE11
AJ31
AL5
AC27
AM4
AB26
AM27
L30
AL23
M31
AG18
U33
AE18
R29
AL13
AE32
AM12
AC31
AL8
AE28
AL6
AE27
AJ16
W29
AF21
H31
AK23
N29
AK18
U31
AK20
R31
AJ13
AC30
AK12
AB30
AM7
AD27
AH9
AF28
DQS17_A
DQS17_B
DRDY#
HA3#
HA4#
HA5#
HA6#
HA7#
HA8#
HA9#
HA10#
HA11#
HA12#
HA13#
HA14#
HA15#
HA16#
HA17#
HA18#
HA19#
HA20#
HA21#
HA22#
HA23#
HA24#
HA25#
HA26#
HA27#
HA28#
HA29#
HA30#
HA31#
HA32#
HA33#
HA34#
HA35#
HADSTB0#
HADSTB1#
HAVREF0
HAVREF1
HCCVREF
HCLKINN
HCLKINP
HD0#
HD1#
HD2#
HD3#
HD4#
HD5#
HD6#
HD7#
AF16
Y30
Y3
AA8
AB1
AC3
AD2
AB6
AC4
AD4
AE5
AE2
AC6
AB9
AE6
AE3
AD5
AB8
AC7
AC9
AH2
AH3
AG2
AF6
AD8
AF1
AG4
AJ4
AE8
AF3
AF7
AH5
AG7
AH6
AJ1
AG5
AE1
AD7
AF4
AJ3
Y6
U3
T2
B9
A9
A4
B5
E8
B3
A5
C8
135
Ballout and Package Specifications
Table 7-1. MCH Signal List
136
Table 7-1. MCH Signal List
Table 7-1. MCH Signal List
Signal Name
Ball #
Signal Name
Ball #
Signal Name
Ball #
HD8#
HD9#
HD10#
HD11#
HD12#
HD13#
HD14#
HD15#
HD16#
HD17#
HD18#
HD19#
HD20#
HD21#
HD22#
HD23#
HD24#
HD25#
HD26#
HD27#
HD28#
HD29#
HD30#
HD31#
HD32#
HD33#
HD34#
HD35#
HD36#
HD37#
HD38#
HD39#
HD40#
HD41#
HD42#
HD43#
HD44#
HD45#
HD46#
HD47#
HD48#
HD49#
HD50#
HD51#
HD52#
HD53#
HD54#
HD55#
HD56#
HD57#
HD58#
A8
C4
C7
D7
H7
C2
J8
J7
F7
L7
L6
E6
G6
D6
F5
E4
M8
E1
F4
D3
F2
E3
F1
M7
H4
H3
G2
K3
G3
J1
K2
K1
N6
J5
P9
M4
P7
N7
R7
R8
L3
N4
P4
M2
L2
N2
N3
N1
R2
T6
T3
HD59#
HD60#
HD61#
HD62#
HD63#
HDSTBN0#
HDSTBN1#
HDSTBN2#
HDSTBN3#
HDSTBP0#
HDSTBP1#
HDSTBP2#
HDSTBP3#
HDVREF0
HDVREF1
HDVREF2
HDVREF3
HI_STBF
HI_STBS
HI0_A
HI0_B
HI0_C
HI0_D
HI1_A
HI1_B
HI1_C
HI1_D
HI2_A
HI2_B
HI2_C
HI2_D
HI3_A
HI3_B
HI3_C
HI3_D
HI4_A
HI4_B
HI4_C
HI4_D
HI5_A
HI5_B
HI5_C
HI5_D
HI6_A
HI6_B
HI6_C
HI6_D
HI7_A
HI7_B
HI7_C
HI7_D
U7
T9
T5
R5
T8
B6
K6
J2
R4
B8
H6
J4
P3
C5
N8
P6
T7
C10
D10
E11
D16
D22
D28
B11
G16
B24
G25
G10
C17
G18
G26
F10
C16
C22
F26
D9
A17
E20
G24
E9
A16
F19
A27
J11
B14
D21
H24
H9
D15
E21
C26
HI8_A
HI8_B
HI8_C
HI8_D
HI9_A
HI9_B
HI9_C
HI9_D
HI10_A
HI10_B
HI10_C
HI10_D
HI11_A
HI11_B
HI11_C
HI11_D
HI12_B
HI12_C
HI12_D
HI13_B
HI13_C
HI13_D
HI14_B
HI14_C
HI14_D
HI15_B
HI15_C
HI15_D
HI16_B
HI16_C
HI16_D
HI17_B
HI17_C
HI17_D
HI18_B
HI18_C
HI18_D
HI20_B
HI20_C
HI20_D
HI21_B
HI21_C
HI21_D
HIRCOMP_A
HIRCOMP_B
HIRCOMP_C
HIRCOMP_D
HISWNG_A
HISWNG_B
HISWNG_C
HISWNG_D
J13
C14
D19
G22
J10
F13
A20
E24
F11
A13
B20
A25
G12
C13
C19
D24
D12
B18
A24
E12
C18
E23
C11
E18
F23
J14
F17
F22
H14
B21
H23
B17
C24
H25
E14
F20
F25
F14
H18
E27
G13
F16
H21
H11
E15
C20
G21
H12
B15
H17
F24
Datasheet
Ballout and Package Specifications
Table 7-1. MCH Signal List
Datasheet
Table 7-1. MCH Signal List
Table 7-1. MCH Signal List
Signal Name
Ball #
Signal Name
Ball #
Signal Name
Ball #
HIT#
HITM#
HIVREF_A
HIVREF_B
HIVREF_C
HIVREF_D
HLOCK#
HREQ0#
HREQ1#
HREQ2#
HREQ3#
HREQ4#
HTRDY#
HXRCOMP
HXSWING
HYRCOMP
HYSWING
MA0_A
MA0_B
MA1_A
MA1_B
MA2_A
MA2_B
MA3_A
MA3_B
MA4_A
MA4_B
MA5_A
MA5_B
MA6_A
MA6_B
MA7_A
MA7_B
MA8_A
MA8_B
MA9_A
MA9_B
MA10_A
MA10_B
MA11_A
MA11_B
MA12_A
MA12_B
PSTRBF_B
PSTRBF_C
PSTRBF_D
PSTRBS_B
PSTRBS_C
PSTRBS_D
PUSTRBF_B
PUSTRBF_C
U1
W5
G9
D13
A21
J22
V7
AB2
AA1
AA7
AB3
Y9
W3
V4
V8
G5
K5
AF24
M26
AK26
K29
AH26
H30
AJ27
G30
AG27
F32
AH28
G29
AL28
F31
AL29
E33
AK29
E31
AM30
F29
AJ24
L25
AK30
C31
AM31
C32
G15
C23
D27
H15
B23
D26
A12
D18
PUSTRBF_D
PUSTRBS_B
PUSTRBS_C
PUSTRBS_D
PWRGOOD
RAS_A#
RAS_B#
RCVENIN_A#
RCVENIN_B#
RCVENOUT_A#
RCVENOUT_B#
Reserved
Reserved
Reserved
Reserved
RS0#
RS1#
RS2#
RSP#
RSTIN#
SMB_CLK
SMB_DATA
VCC_CPU
VCC_CPU
VCC_CPU
VCC_CPU
VCC_CPU
VCC_CPU
VCC_CPU
VCC_CPU
VCC_CPU
VCC_CPU
VCC_CPU
VCC_CPU
VCC_CPU
VCC_CPU
VCC_CPU
VCC_CPU
VCC_CPU
VCC_CPU
VCC_CPU
VCC_CPU
VCC_CPU
VCC_CPU
VCC_CPU
VCC_CPU
VCC_CPU
VCC_CPU
VCC_CPU
VCC_CPU
VCC_CPU
B25
B12
E17
C25
A28
AN24
V32
AM22
N30
AG20
R25
B30
AM18
K33
D29
V2
V5
U4
AK4
E28
J25
B31
AC5
AG3
AJ5
AF5
AH1
K7
F3
P5
R3
W7
H5
L5
U5
Y5
AE7
K9
AD1
D1
H1
M1
T1
Y1
A6
E7
AA10
AB11
AC10
C3
D5
VCC_CPU
VCC_CPU
VCC_CPU
VCC_CPU
VCC_CPU
VCC_CPU
VCC_CPU
VCC_CPU
VCC_CPU
VCC_CPU
VCC1_2
VCC1_2
VCC1_2
VCC1_2
VCC1_2
VCC1_2
VCC1_2
VCC1_2
VCC1_2
VCC1_2
VCC1_2
VCC1_2
VCC1_2
VCC1_2
VCC1_2
VCC1_2
VCC1_2
VCC1_2
VCC1_2
VCC1_2
VCC1_2
VCC1_2
VCC1_2
VCC1_2
VCC1_2
VCC1_2
VCC1_2
VCC1_2
VCC1_2
VCC1_2
VCC1_2
VCC1_2
VCC1_2
VCC1_2
VCC1_2
VCC1_2
VCC1_2
VCC1_2
VCC1_2
VCC1_2
VCC1_2
L10
M11
N10
P11
R10
T11
U10
V11
W10
Y11
L18
L20
L22
B28
H20
A10
A14
A18
A22
E10
E13
E16
E19
E22
K13
K15
K17
K19
K21
K23
P14
P18
R17
R19
T14
T16
T18
U17
U19
V16
V18
W15
W17
W19
A26
A30
R15
V14
E26
H19
K11
137
Ballout and Package Specifications
Table 7-1. MCH Signal List
138
Table 7-1. MCH Signal List
Table 7-1. MCH Signal List
Signal Name
Ball #
Signal Name
Ball #
Signal Name
Ball #
VCC1_2
VCC1_2
VCC1_2
VCC2_5
VCC2_5
VCC2_5
VCC2_5
VCC2_5
VCC2_5
VCC2_5
VCC2_5
VCC2_5
VCC2_5
VCC2_5
VCC2_5
VCC2_5
VCC2_5
VCC2_5
VCC2_5
VCC2_5
VCC2_5
VCC2_5
VCC2_5
VCC2_5
VCC2_5
VCC2_5
VCC2_5
VCC2_5
VCC2_5
VCC2_5
VCC2_5
VCC2_5
VCC2_5
VCC2_5
VCC2_5
VCC2_5
VCC2_5
VCC2_5
VCC2_5
VCC2_5
VCC2_5
VCC2_5
VCC2_5
VCC2_5
VCC2_5
VCC2_5
VCC2_5
VCC2_5
VCC2_5
VCC2_5
VCC2_5
L12
L14
L16
R23
AN4
AN7
AA23
AC13
AC15
AC17
AC19
U23
W23
AB24
AD12
AD14
AD16
AD18
AD20
AD25
AD29
AD33
AE10
AE30
AF33
AJ11
AJ14
AJ17
AJ20
AJ23
AK33
AN10
AN14
AN18
AN22
AN26
H33
L29
M33
P24
P29
T24
T33
U29
V24
Y24
Y29
Y33
AA27
AG13
AG19
VCC2_5
VCC2_5
VCC2_5
VCC2_5
VCC2_5
VCC2_5
VCC2_5
VCC2_5
VCC2_5
VCC2_5
VCC2_5
VCC2_5
VCC2_5
VCC2_5
VCC2_5
VCC2_5
VCC2_5
VCC2_5
VCC2_5
VCC2_5
VCC2_5
VCC2_5
VCC2_5
VCC2_5
VCC2_5
VCC2_5
VCC2_5
VCC2_5
VCC2_5
VCCA1_2
VCCA1_2
VCCA1_2
VCCA1_2
VCCA1_2
VCCA1_2
VCCA1_2
VCCACPU1_2
VCCAHI1_2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AG22
AK10
AK8
AL1
AL15
AL24
G27
AC21
AC23
L23
N23
AD22
AD24
AJ26
AJ29
AN30
D33
E29
H29
K24
M24
AF23
AG28
AM32
B32
L26
AB31
K31
T31
P20
T20
V20
Y14
Y16
Y18
Y20
U15
P16
AD11
AD13
AD15
AD17
AD19
AD21
AD23
AD26
AD30
AE29
AE9
AF10
AF11
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AF14
AF17
AF20
AF26
AF29
AF32
AG16
AG25
AG31
AH12
AH15
AH18
AH21
AH24
AH27
AH30
AJ32
AJ33
AK13
AK16
AK22
AK25
AK28
AK31
AL12
AL18
AL21
AL27
AL30
AL33
AM11
AM14
AM17
AM20
AM23
AM26
AM29
AN11
AK9
AM8
AC8
G7
D30
AF8
AA9
J6
V3
F28
AG6
AH7
AH4
Datasheet
Ballout and Package Specifications
Table 7-1. MCH Signal List
Datasheet
Table 7-1. MCH Signal List
Table 7-1. MCH Signal List
Signal Name
Ball #
Signal Name
Ball #
Signal Name
Ball #
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AN15
AN19
AN23
AN27
AN3
AN31
AN6
B10
B13
B16
B19
B22
B26
B29
B4
B7
C1
C12
C15
C21
C27
C30
C33
C6
C9
D11
D14
D17
D20
D23
D31
D8
E25
E32
F12
F15
F18
F21
F27
F30
F6
F9
G1
G11
G14
G17
G20
G23
G28
G31
G33
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AL4
AJ2
AK3
AD6
AK6
AL7
AM5
AF2
AD3
AG1
AK1
U9
E2
H2
K4
J3
K8
L8
G4
M6
P2
M3
M9
P8
N9
U2
R6
T4
V6
W4
W2
Y2
AA3
AA6
Y8
J19
J20
G19
E5
J23
AB5
D4
AE4
AC2
AG9
L9
C28
B27
AB4
AB7
AD9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
G8
H10
H13
H16
H22
H26
H32
H8
J12
J15
J18
J21
J24
J27
J30
J9
K12
K14
K16
K18
K20
K22
K28
L1
L24
L32
L33
M23
M27
M30
N5
N24
N28
N31
P15
P17
P19
P23
P32
R1
R14
R18
R20
R24
R27
R30
R33
R9
T15
T17
T19
139
Ballout and Package Specifications
Table 7-1. MCH Signal List
140
Table 7-1. MCH Signal List
Table 7-1. MCH Signal List
Signal Name
Ball #
Signal Name
Ball #
Signal Name
Ball #
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AA11
AB10
AC11
AD10
AN9
M10
M5
N11
P10
R11
T10
U11
V10
W11
Y10
B2
J17
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
K10
L11
L13
L15
L17
L19
L21
R16
AC29
AJ10
D25
A11
A15
A19
A23
A29
A3
A31
A7
AA24
AA30
AB23
AB28
AC1
AC12
AC14
AC16
AC18
AC20
AC22
AC24
AC26
AC32
AC33
T23
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
WE_A#
WE_B#
xERR#
XORMODE#
T28
U14
U16
U18
U20
U24
U32
U8
V15
V17
V19
V23
V27
V30
V9
W1
W14
W16
W18
W20
W24
W28
W31
W33
Y15
Y17
Y19
Y23
Y26
Y32
AJ8
AE23
D32
AK2
C29
Datasheet
Ballout and Package Specifications
7.2
Package Specifications
Figure 7-4 and Figure 7-5 provide the package specifications for the MCH.
Figure 7-4. MCH Package Dimensions (Top View)
AN
AM
Detail A
AL
AK
AJ
AH
AG
AF
AE
AD
AC
AB
AA
Y
W
V
U
T
R
P
N
M
L
K
21.250
J
H
G
F
E
E
C
B
1.270
A
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
1.270
20.320
40.640
2x 42.500 ±0.100
0.200 A B
Detail A
Solder Resist Opening
(n)x 0.650 ± 0.040
∅ 00.200 L C A S B
∅ 00.071 L C
Metal Edge
(n)x ∅ 0.790 ± 0.025
(n)x 0.025 Min
NOTE:
1. All dimensions are in millimeters.
2. All dimensions and tolerances conform to ANSI Y14.5M-1982.
Datasheet
141
Ballout and Package Specifications
Figure 7-5. MCH Package Dimensions (Side View)
1.940 ± 0.150 mm
Die
Substrate
1.10 ± 0.10 mm
0.20
–C–
Seating Plane
0.60 ± 0.10 mm
See note 3.
NOTES:
1. All dimensions are in millimeters.
2. Substrate thickness and package overall height are thicker than standard 492-L-PBGA
3. Primary datum —C— and seating plane are defined by the spherical crowns of the solder balls.
4. All dimensions and tolerances conform to ANSI Y14.5M-1982.
142
Datasheet
Ballout and Package Specifications
7.3
Chipset Interface Trace Length Compensation
In this section, detailed information is given about the internal component package trace lengths to
enable trace length compensation. Trace length compensation is required for platform design.
These lengths must be considered when matching trace lengths as described in the Intel® Xeon™
Processor with 512-KB L2 Cache and Intel® E7500 Chipset Platform Design Guide. Note that
these lengths represent the actual lengths from pad to ball.
The data given can be normalized from a particular reference ball to simplify routing. If the longest
trace is used as the reference for normalization, use Equation 7-1.
Equation 7-1.
∆LPKG = LREF − LPKG
LREF is the nominal package length of the reference signal used for normalization.
∆LPKG is the nominal ∆ package trace length of the MCH from the reference trace.
To calculate the ∆LPCB for signals from the MCH to the device, use Equation 7-2.
Equation 7-2.
∆LPCB =
∆LPKG × VPKG
VPCB
∆LPCB is the nominal ∆ PCB trace length to be added on the PCB.
∆LPKG is the nominal ∆ package trace length of the MCH (refer to Equation 1).
VPKG is the MCH package trace delay due to signal velocity. The nominal value is
150 ps/in.
VPCB is the PCB trace delay due to signal velocity. The nominal value is 175 ps/in on
the recommended stackup.
Note:
Use care when converting delays and velocities (x ps/in is a delay, y in/ps is a velocity).
Table 7-2 shows example values when signal MEMORY1 trace length is used for normalization.
Table 7-2. Example Normalization Table
LPKG (mils)
∆LPKG (mils)
∆LPCB (mils)
Target LPCB (mils)
MEMORY1
175.984
0.000
0.000
3500.000
MEMORY2
152.364
23.620
20.246
3520.246
MEMORY3
130.315
45.669
39.145
3539.145
MEMORY4
118.897
57.087
48.932
3548.932
•
•
•
MEMORYN
Datasheet
•
•
•
102.756
•
•
•
73.228
•
•
•
62.767
•
•
•
3562.767
143
Ballout and Package Specifications
7.3.1
MCH System Bus Signal Package Trace Length Data
Table 7-3 is the MCH package trace length information for the system bus.
Table 7-3. MCH LPKG Data for the System Bus (Sheet 1 of 2)
144
Signal
Ball No.
LPKG (mils)
Signal
Ball No.
LPKG (mils)
HADSTB0#
HA3#
HA4#
HA5#
HA6#
HA7#
HA8#
HA9#
HA10#
HA11#
HA12#
HA13#
HA14#
HA15#
HA16#
HREQ0#
HREQ1#
HREQ2#
HREQ3#
HREQ4#
AE1
AA8
AB1
AC3
AD2
AB6
AC4
AD4
AE5
AE2
AC6
AB9
AE6
AE3
AD5
AB2
AA1
AA7
AB3
Y9
797.99
296.14
692.09
602.24
761.50
469.09
569.02
631.65
612.17
781.97
469.44
578.15
576.69
702.60
512.91
665.47
684.80
397.91
591.46
308.86
HDSTBN0#
HDSTBP0#
HD0#
HD1#
HD2#
HD3#
HD4#
HD5#
HD6#
HD7#
HD8#
HD9#
HD10#
HD11#
HD12#
HD13#
HD14#
HD15#
DBI0#
B6
B8
B9
A9
A4
B5
E8
B3
A5
C8
A8
C4
C7
D7
H7
C2
J8
J7
F8
842.99
739.72
682.48
775.98
955.20
933.07
648.77
1044.33
930.87
732.77
763.54
909.13
779.65
765.00
535.59
1059.96
398.46
457.64
596.13
HADSTB1#
HA17#
HA18#
HA19#
HA20#
HA21#
HA22#
HA23#
HA24#
HA25#
HA26#
HA27#
HA28#
HA29#
HA30#
HA31#
HA32#
HA33#
HA34#
HA35#
AD7
AB8
AC7
AC9
AH2
AH3
AG2
AF6
AD8
AF1
AG4
AJ4
AE8
AF3
AF7
AH5
AG7
AH6
AJ1
AG5
430.11
334.72
390.55
379.57
860.71
732.09
772.17
567.76
403.50
798.46
690.75
695.39
413.27
736.10
521.58
619.72
497.28
601.73
877.87
611.77
HDSTBN1#
HDSTBP1#
HD16#
HD17#
HD18#
HD19#
HD20#
HD21#
HD22#
HD23#
HD24#
HD25#
HD26#
HD27#
HD28#
HD29#
HD30#
HD31#
DBI1#
K6
H6
F7
L7
L6
E6
G6
D6
F5
E4
M8
E1
F4
D3
F2
E3
F1
M7
D2
480.24
562.32
617.72
378.98
450.04
762.64
680.20
771.73
809.84
859.72
334.68
1030.20
851.54
892.64
945.08
905.20
1031.89
400.67
981.89
HCLKINN
HCLKINP
U3
T2
639.53
639.61
Datasheet
Ballout and Package Specifications
Table 7-3. MCH LPKG Data for the System Bus (Sheet 2 of 2)
7.3.1.1
Signal
Ball No.
LPKG (mils)
Signal
Ball No.
LPKG (mils)
HDSTBN2#
HDSTBP2#
HD32#
HD33#
HD34#
HD35#
HD36#
HD37#
HD38#
HD39#
HD40#
HD41#
HD42#
HD43#
HD44#
HD45#
HD46#
HD47#
DBI2#
J2
J4
H4
H3
G2
K3
G3
J1
K2
K1
N6
J5
P9
M4
P7
N7
R7
R8
L4
783.19
726.26
715.47
803.03
865.59
723.94
818.54
803.50
740.32
821.65
419.37
720.87
315.91
622.60
373.34
351.31
332.80
306.89
649.69
HDSTBN3#
HDSTBP3#
HD48#
HD49#
HD50#
HD51#
HD52#
HD53#
HD54#
HD55#
HD56#
HD57#
HD58#
HD59#
HD60#
HD61#
HD62#
HD63#
DBI3#
R4
P3
L3
N4
P4
M2
L2
N2
N3
N1
R2
T6
T3
U7
T9
T5
R5
T8
P1
529.41
605.71
669.41
596.42
584.80
723.07
729.17
707.44
605.91
760.00
613.43
534.25
580.20
367.72
271.46
479.33
451.46
312.87
686.77
MCH DDR Channel A Signal Package Trace Length Data
Table 7-4 is the MCH package trace length information for channel A of the DDR memory
interface.
Table 7-4. MCH LPKG Data for DDR Channel A (Sheet 1 of 3)
Datasheet
Signal
Ball No.
LPKG (mils)
Signal
Ball No.
LPKG (mils)
DQS0_A
DQS9_A
DQ0_A
DQ1_A
DQ2_A
DQ3_A
DQ4_A
DQ5_A
DQ6_A
DQ7_A
AM27
AF21
AF22
AN28
AE21
AH22
AN29
AM28
AL26
AL25
760.59
291.45
345.91
853.78
284.59
447.83
867.36
817.76
707.24
642.13
DQS2_A
DQS11_A
DQ16_A
DQ17_A
DQ18_A
DQ19_A
DQ20_A
DQ21_A
DQ22_A
DQ23_A
AG18
AK18
AK19
AL19
AN17
AF18
AN20
AM19
AL17
AJ18
338.67
477.64
499.02
583.11
674.17
297.50
697.09
630.75
534.80
455.77
DQS1_A
DQS10_A
DQ8_A
DQ9_A
DQ10_A
DQ11_A
DQ12_A
DQ13_A
DQ14_A
DQ15_A
AL23
AK23
AN25
AM24
AG21
AE20
AM25
AK24
AL22
AJ22
602.87
552.99
761.06
712.95
371.89
273.13
737.68
607.13
578.43
475.71
DQS3_A
DQS12_A
DQ24_A
DQ25_A
DQ26_A
DQ27_A
DQ28_A
DQ29_A
DQ30_A
DQ31_A
AE18
AK20
AF19
AH19
AM21
AL20
AH20
AJ21
AN21
AJ19
226.03
500.71
300.32
423.19
625.04
578.15
440.20
503.66
703.07
438.58
145
Ballout and Package Specifications
Table 7-4. MCH LPKG Data for DDR Channel A (Sheet 2 of 3)
146
Signal
Ball No.
LPKG (mils)
Signal
Ball No.
LPKG (mils)
DQS4_A
DQS13_A
DQ32_A
DQ33_A
DQ34_A
DQ35_A
DQ36_A
DQ37_A
DQ38_A
DQ39_A
AL13
AJ13
AL14
AM13
AJ15
AF15
AK14
AN13
AH14
AG14
595.67
473.62
586.58
662.60
512.60
350.43
516.50
730.83
447.76
358.19
DQS7_A
DQS16_A
DQ56_A
DQ57_A
DQ58_A
DQ59_A
DQ60_A
DQ61_A
DQ62_A
DQ63_A
AL6
AH9
AG10
AJ9
AM3
AM2
AH10
AE11
AL5
AM4
733.15
483.27
446.54
572.13
957.28
990.51
527.88
337.46
779.02
882.36
DQS5_A
DQS14_A
DQ40_A
DQ41_A
DQ42_A
DQ43_A
DQ44_A
DQ45_A
DQ46_A
DQ47_A
AM12
AK12
AE14
AH13
AN12
AL11
AE15
AF13
AJ12
AM10
693.27
531.46
402.72
453.46
704.45
666.30
270.32
344.49
506.22
703.35
DQS8_A
DQS17_A
CB0_A
CB1_A
CB2_A
CB3_A
CB4_A
CB5_A
CB6_A
CB7_A
AJ16
AF16
AE16
AH16
AL16
AK15
AE17
AG17
AM15
AG15
432.48
281.57
256.61
412.22
559.57
560.08
375.28
359.80
656.14
371.50
DQS6_A
DQS15_A
DQ48_A
DQ49_A
DQ50_A
DQ51_A
DQ52_A
DQ53_A
DQ54_A
DQ55_A
AL8
AM7
AE12
AH11
AG11
AN5
AG12
AF12
AM9
AM6
676.58
755.79
278.66
463.74
441.73
898.50
412.05
377.68
742.17
855.47
Datasheet
Ballout and Package Specifications
Table 7-4. MCH LPKG Data for DDR Channel A (Sheet 3 of 3)
Datasheet
Signal
Ball No.
LPKG (mils)
Signal
Ball No.
LPKG (mils)
CMDCLK0_A
CMDCLK0_A#
BA0_A
BA1_A
CAS_A#
CKE_A
CS0_A#
CS1_A#
MA0_A
MA1_A
MA2_A
MA3_A
MA4_A
MA5_A
MA6_A
MA7_A
MA8_A
MA9_A
MA10_A
MA11_A
MA12_A
RAS_A#
WE_A#
AG24
AG23
AL31
AH23
AE22
AE19
AE13
AK11
AF24
AK26
AH26
AJ27
AG27
AH28
AL28
AL29
AK29
AM30
AJ24
AK30
AM31
AN24
AE23
447.35
405.28
789.29
427.72
411.22
249.80
434.96
594.41
340.16
640.55
512.01
568.58
466.97
595.79
791.89
735.71
698.35
827.80
572.17
712.64
865.00
757.84
298.19
CMDCLK2_A
CMDCLK2_A#
BA0_A
BA1_A
CAS_A#
CKE_A
CS4_A#
CS5_A#
MA0_A
MA1_A
MA2_A
MA3_A
MA4_A
MA5_A
MA6_A
MA7_A
MA8_A
MA9_A
MA10_A
MA11_A
MA12_A
RAS_A#
WE_A#
AG26
AF25
AL31
AH23
AE22
AE19
AN8
AK7
AF24
AK26
AH26
AJ27
AG27
AH28
AL28
AL29
AK29
AM30
AJ24
AK30
AM31
AN24
AE23
459.06
367.24
789.29
427.72
411.22
249.80
805.28
716.34
340.16
640.55
512.01
568.58
466.97
595.79
791.89
735.71
698.35
827.80
572.17
712.64
865.00
757.84
298.19
CMDCLK1_A
CMDCLK1_A#
BA0_A
BA1_A
CAS_A#
CKE_A
CS2_A#
CS3_A#
MA0_A
MA1_A
MA2_A
MA3_A
MA4_A
MA5_A
MA6_A
MA7_A
MA8_A
MA9_A
MA10_A
MA11_A
MA12_A
RAS_A#
WE_A#
AJ25
AH25
AL31
AH23
AE22
AE19
AL10
AH8
AF24
AK26
AH26
AJ27
AG27
AH28
AL28
AL29
AK29
AM30
AJ24
AK30
AM31
AN24
AE23
544.88
473.52
789.29
427.72
411.22
249.80
641.10
622.17
340.16
640.55
512.01
568.58
466.97
595.79
791.89
735.71
698.35
827.80
572.17
712.64
865.00
757.84
298.19
CMDCLK3_A
CMDCLK3_A#
BA0_A
BA1_A
CAS_A#
CKE_A
CS6_A#
CS7_A#
MA0_A
MA1_A
MA2_A
MA3_A
MA4_A
MA5_A
MA6_A
MA7_A
MA8_A
MA9_A
MA10_A
MA11_A
MA12_A
RAS_A#
WE_A#
AE25
AE24
AL31
AH23
AE22
AE19
AL3
AL2
AF24
AK26
AH26
AJ27
AG27
AH28
AL28
AL29
AK29
AM30
AJ24
AK30
AM31
AN24
AE23
359.80
322.68
789.29
427.72
411.22
249.80
892.80
917.36
340.16
640.55
512.01
568.58
466.97
595.79
791.89
735.71
698.35
827.80
572.17
712.64
865.00
757.84
298.19
147
Ballout and Package Specifications
7.3.1.2
MCH DDR Channel B Signal Package Trace Length Data
Table 7-5 is the MCH package trace length information for channel B of the DDR memory
interface.
f
Table 7-5. MCH LPKG Data for DDR Channel B (Sheet 1 of 3)
148
Signal
Ball No.
LPKG (mils)
Signal
Ball No.
LPKG (mils)
DQS0_B
DQS9_B
DQ0_B
DQ1_B
DQ2_B
DQ3_B
DQ4_B
DQ5_B
DQ6_B
DQ7_B
L30
H31
F33
K30
J32
N25
N27
G32
M29
N26
545.94
698.39
870.43
639.33
695.67
275.85
344.82
796.61
488.98
329.65
DQS3_B
DQS12_B
DQ24_B
DQ25_B
DQ26_B
DQ27_B
DQ28_B
DQ29_B
DQ30_B
DQ31_B
R29
R31
P30
P33
R26
T32
N32
P31
R28
T25
445.98
541.50
523.82
694.80
287.40
586.46
655.83
587.64
415.72
307.72
DQS1_B
DQS10_B
DQ8_B
DQ9_B
DQ10_B
DQ11_B
DQ12_B
DQ13_B
DQ14_B
DQ15_B
M31
N29
J33
K32
P27
P25
J31
L31
P26
P28
586.65
459.05
765.35
724.84
361.38
246.21
710.35
635.83
322.21
423.86
DQS4_B
DQS13_B
DQ32_B
DQ33_B
DQ34_B
DQ35_B
DQ36_B
DQ37_B
DQ38_B
DQ39_B
AE32
AC30
W27
AE33
AF31
W25
AA28
AD32
AG33
W26
756.46
609.57
375.75
825.12
780.55
627.56
499.10
766.85
863.70
328.87
DQS2_B
DQS11_B
DQ16_B
DQ17_B
DQ18_B
DQ19_B
DQ20_B
DQ21_B
DQ22_B
DQ23_B
U33
U31
T29
T30
U30
T26
R32
T27
V33
V31
660.43
545.16
441.22
511.14
523.03
318.23
631.77
366.58
697.36
556.89
DQS5_B
DQS14_B
DQ40_B
DQ41_B
DQ42_B
DQ43_B
DQ44_B
DQ45_B
DQ46_B
DQ47_B
AC31
AB30
AA29
AB33
V26
AD31
Y28
AB32
AB29
V25
692.56
598.03
567.36
769.02
288.03
746.26
421.18
743.46
590.71
633.50
Datasheet
Ballout and Package Specifications
Table 7-5. MCH LPKG Data for DDR Channel B (Sheet 2 of 3)
Datasheet
Signal
Ball No.
LPKG (mils)
Signal
Ball No.
LPKG (mils)
DQS6_B
DQS15_B
DQ48_B
DQ49_B
DQ50_B
DQ51_B
DQ52_B
DQ53_B
DQ54_B
DQ55_B
AE28
AD27
Y25
AB27
AH32
AH31
AC28
AA26
AG30
AH33
569.17
502.05
247.68
417.01
865.47
860.08
547.40
339.80
780.12
946.54
DQS8_B
DQS17_B
CB0_B
CB1_B
CB2_B
CB3_B
CB4_B
CB5_B
CB6_B
CB7_B
W29
Y30
V28
U25
Y31
AA33
U28
U27
AA31
AA32
470.79
551.26
422.40
262.04
639.37
724.06
421.42
356.31
605.00
701.69
DQS7_B
DQS16_B
DQ56_B
DQ57_B
DQ58_B
DQ59_B
DQ60_B
DQ61_B
DQ62_B
DQ63_B
AE27
AF28
AJ30
AG29
AB25
AA25
AL32
AJ31
AC27
AB26
488.39
548.74
741.93
692.99
480.35
260.73
924.06
816.65
478.39
360.59
149
Ballout and Package Specifications
Table 7-5. MCH LPKG Data for DDR Channel B (Sheet 3 of 3)
150
Signal
Ball No.
LPKG (mils)
Signal
Ball No.
LPKG (mils)
CMDCLK0_B
CMDCLK0_B#
BA0_B
BA1_B
CAS_B#
CKE_B
CS0_B#
CS1_B#
MA0_B
MA1_B
MA2_B
MA3_B
MA4_B
MA5_B
MA6_B
MA7_B
MA8_B
MA9_B
MA10_B
MA11_B
MA12_B
RAS_B#
WE_B#
J29
J28
K26
H27
H28
M32
AH29
AK32
M26
K29
H30
G30
F32
G29
F31
E33
E31
F29
L25
C31
C32
V32
D32
595.43
539.65
370.75
430.16
542.21
660.59
693.82
899.92
333.74
540.43
659.69
705.39
793.19
612.68
747.72
892.05
728.54
603.94
435.71
794.25
813.07
651.06
818.43
CMDCLK2_B
CMDCLK2_B#
BA0_B
BA1_B
CAS_B#
CKE_B
CS4_B#
CS5_B#
MA0_B
MA1_B
MA2_B
MA3_B
MA4_B
MA5_B
MA6_B
MA7_B
MA8_B
MA9_B
MA10_B
MA11_B
MA12_B
RAS_B#
WE_B#
J26
K25
K26
H27
H28
M32
AE31
AE26
M26
K29
H30
G30
F32
G29
F31
E33
E31
F29
L25
C31
C32
V32
D32
397.24
313.50
370.75
430.16
542.21
660.59
739.72
463.94
333.74
540.43
659.69
705.39
793.19
612.68
747.72
892.05
728.54
603.94
435.71
794.25
813.07
651.06
818.43
CMDCLK1_B
CMDCLK1_B#
BA0_B
BA1_B
CAS_B#
CKE_B
CS2_B#
CS3_B#
MA0_B
MA1_B
MA2_B
MA3_B
MA4_B
MA5_B
MA6_B
MA7_B
MA8_B
MA9_B
MA10_B
MA11_B
MA12_B
RAS_B#
WE_B#
L28
M28
K26
H27
H28
M32
AF30
AF27
M26
K29
H30
G30
F32
G29
F31
E33
E31
F29
L25
C31
C32
V32
D32
417.28
405.28
370.75
430.16
542.21
660.59
739.06
515.04
333.74
540.43
659.69
705.39
793.19
612.68
747.72
892.05
728.54
603.94
435.71
794.25
813.07
651.06
818.43
CMDCLK3_B
CMDCLK3_B#
BA0_B
BA1_B
CAS_B#
CKE_B
CS6_B#
CS7_B#
MA0_B
MA1_B
MA2_B
MA3_B
MA4_B
MA5_B
MA6_B
MA7_B
MA8_B
MA9_B
MA10_B
MA11_B
MA12_B
RAS_B#
WE_B#
K27
L27
K26
H27
H28
M32
AD28
Y27
M26
K29
H30
G30
F32
G29
F31
E33
E31
F29
L25
C31
C32
V32
D32
423.70
400.43
370.75
430.16
542.21
660.59
575.79
353.35
333.74
540.43
659.69
705.39
793.19
612.68
747.72
892.05
728.54
603.94
435.71
794.25
813.07
651.06
818.43
Datasheet
Ballout and Package Specifications
7.3.1.3
MCH Hub Interface_A Signal Package Trace Length Data
Table 7-6 is the MCH package trace length information for Hub Interface_A.
Table 7-6. MCH LPKG Data for Hub Interface_A
7.3.1.4
Signal
Ball No.
LPKG (mils)
HI_STBF
C10
659.09
HI_STBS
D10
623.43
HI0_A
E11
519.92
HI1_A
B11
743.78
HI2_A
G10
468.03
HI3_A
F10
501.54
HI4_A
D9
633.62
HI5_A
E9
543.11
HI6_A
J11
317.83
HI7_A
H9
426.55
MCH Hub Interface_B Signal Package Trace Length Data
Table 7-7 is the MCH package trace length information for Hub Interface_B.
Table 7-7. MCH LPKG Data for Hub Interface_B
Datasheet
Signal
Ball No.
LPKG (mils)
Signal
Ball No.
LPKG (mils)
PSTRBF_B
G15
333.78
PUSTRBF_B
A12
678.70
PSTRBS_B
H15
300.32
PUSTRBS_B
B12
645.75
HI0_B
D16
482.83
HI8_B
C14
591.54
HI1_B
G16
478.27
HI9_B
F13
433.19
HI2_B
C17
544.45
HI10_B
A13
702.76
HI3_B
C16
571.54
HI11_B
C13
568.78
HI4_B
A17
677.56
HI12_B
D12
518.46
HI5_B
A16
679.33
HI13_B
E12
504.53
HI6_B
B14
597.40
HI14_B
C11
611.77
HI7_B
D15
531.18
HI15_B
J14
272.14
HI20_B
F14
414.53
HI21_B
G13
386.58
151
Ballout and Package Specifications
7.3.1.5
MCH Hub Interface_C Signal Package Trace Length Data
Table 7-8 is the MCH package trace length information for Hub Interface_C.
Table 7-8. MCH LPKG Data for Hub Interface_C
7.3.1.6
Signal
Ball No.
LPKG (mils)
Signal
Ball No.
LPKG (mils)
PSTRBF_C
C23
681.10
PUSTRBF_C
D18
514.80
PSTRBS_C
B23
732.52
PUSTRBS_C
E17
464.80
HI0_C
D22
635.32
HI8_C
D19
557.40
HI1_C
B24
757.96
HI9_C
A20
728.98
HI2_C
G18
360.95
HI10_C
B20
665.71
HI3_C
C22
696.42
HI11_C
C19
616.69
HI4_C
E20
495.43
HI12_C
B18
650.47
HI5_C
F19
394.84
HI13_C
C18
561.77
HI6_C
D21
609.57
HI14_C
E18
453.94
HI7_C
E21
516.69
HI15_C
F17
379.61
HI20_C
H18
294.76
HI21_C
F16
416.61
MCH Hub Interface_D Signal Package Trace Length Data
Table 7-9 is the MCH package trace length information for Hub Interface_D.
Table 7-9. MCH LPKG Data for Hub Interface_D
Signal
152
Ball No.
LPKG (mils)
Signal
Ball No.
LPKG (mils)
PSTRBF_D
D27
720.08
PUSTRBF_D
B25
760.04
PSTRBS_D
D26
731.54
PUSTRBS_D
C25
716.14
HI0_D
D28
772.84
HI8_D
G22
496.18
HI1_D
G25
565.51
HI9_D
E24
588.62
HI2_D
G26
538.23
HI10_D
A25
816.22
HI3_D
F26
592.94
HI11_D
D24
618.90
HI4_D
G24
517.40
HI12_D
A24
808.66
HI5_D
A27
902.48
HI13_D
E23
526.58
HI6_D
H24
416.58
HI14_D
F23
494.53
HI7_D
C26
745.28
HI15_D
F22
497.05
HI20_D
E27
700.00
HI21_D
H21
502.40
Datasheet
Testability
Testability
8
In the MCH, the ability for Automated Test Equipment (ATE) board-level testing has been
implemented as an XOR chain. An XOR chain is a chain of XOR gates, each with one input pin
connected to it.
The MCH uses the XORMODE# pin to activate the XOR test mode. The method to put the MCH
in XOR test is to assert the XORMODE# signal. When the following conditions are met, the chip
will be in XOR test mode. If any of the following are not met, then XOR test will not be enabled.
1. Assert PWRGOOD
2. Assert RSTIN# for 128 clocks beyond the assertion of PWRGOOD (RSTIN# may be held
asserted before PWRGOOD is asserted).
3. Deassert RSTIN#
4. Assert XORMODE# and hold asserted.
5. The clocks may be held at the 0 or 1 state; or be fully running. Since HCLKINP/HCLKINN is
a differential pair, the 2 clock inputs should be held in opposite states.
6. As long as XORMODE# is asserted the MCH is in XOR test. As soon as XORMODE# is
asserted and 2 HCLKINP/HCLKINN cycles have occurred, all the XOR chains are functional.
7. After deasserting XORMODE#, the MCH should be reset before any other testing is done.
There are eight chains of XORs divided up functionally.
Note:
Datasheet
For all test modes except Asynchronous XOR mode, input pin XORMODE# should be driven
high.
153
Testability
8.1
XOR Chains
The XOR chain outputs (XOR chains 8 through 1) are visible on HI_A[7:0]. In Long XOR chain
mode the delay through the 4 pad ring chains (chains 1, 2, 3, 4) may be observed on HI4_A.
RSTIN# is not part of any XOR chain. This is in addition to HI_A[7:0]. The chain partitioning is
listed in Table 8-1. When signals are grouped in Table 8-1 (e.g., DQ_A[63:0]), the chain order is
the same as the ascending numerical name of the pin name (i.e., the chain order for DQ_A[63:0] is
DQ_A0, DQ_A1, DQ_A2, ... DQ_A63).
Table 8-1. XOR Chains
Chain #1
Chain #2
Chain #3
Chain #4
Chain #5
Chain #6
Chain #7
Chain #8
DQ_A[63:0]
DQS_A[17:0]
DQ_B[63:0]
DQS_B[17:0]
HI_STBF
HI_B[17:0]
HD[63:0]#
ADS#
CB_A[7:0]
CMDCLK_A
[3:0]
CB_B[7:0]
CMDCLK_B
[3:0]
HI_STBS
PSTRBF_B
DP[3:0]#
AP[1:0]#
CMDCLK_A
[3:0]#
CMDCLK_B
[3:0]#
HI10_A
PSTRBS_B
MA_A[12:0]
MA_B[12:0]
HI8_A
PUSTRBF_B
BNR#
BA_A[1:0]
BA_B[1:0]
HI9_A
PUSTRBS_B
BPRI#
RAS_A#
RAS_B#
HI11_A
HI18_B
BREQ0#
CAS_A#
CAS_B#
SMB_CLK
HI16_B
CPURST#
SMB_DATA
BINIT#
WE_A#
WE_B#
HI17_B
DBSY#
CS_A[7:0]#
CS_B[7:0]#
HI_C[17:0]
DEFER#
CKE_A[1:0]
CKE_B[1:0]
PSTRBF_C
DBI[3:0]#
RCVENINS
_A#
RCVENIN
_B#
PSTRBS_C
DRDY#
RCVENOUT
_A#
RCVENOUT
_B#
PUSTRBF_C
HA[35:3]#
PUSTRBS_C
HADSTB
[1:0]#
HI18_C
HREQ[4:0]#
HI16_C
HDSTBP
[3:0]#
HI17_C
HDSTBN
[3:0]#
HI_D[17:0]
HIT#
PSTRBF_D
HITM#
PSTRBS_D
HLOCK#
PUSTRBF_D
HTRDY#
PUSTRBS_D
XERR#
HI18_D
RS[2:0]#
HI16_D
RSP#
HI17_D
Out = HI1_A
154
Out = HI2_A
Out = HI3_A
Out = HI4_A
Out = HI5_A
Out = HI6_A
Out = HI7_A
Out = HI8_A
Datasheet