INTEL 82G35

Intel® G35 Express Chipset
Datasheet
— For the 82G35 Graphics and Memory Controller Hub (GMCH)
August 2007
Document Number: 317607-001
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IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT
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Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel
reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from
future changes to them.
The Intel 82G35 GMCH may contain design defects or errors known as errata, which may cause the product to deviate from
published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Hyper-Threading Technology requires a computer system with an Intel® Pentium® 4 processor supporting Hyper-Threading
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hardware and software you use. See http://www.intel.com/info/hyperthreading/ for more information including details on which
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Copyright© 2007, Intel Corporation
2
Datasheet
Contents
1
Introduction ...................................................................................................18
1.1
1.2
1.3
2
Signal Description ...........................................................................................30
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
3
Host Interface Signals ...........................................................................31
DDR2 DRAM Channel A Interface ............................................................34
DDR2 DRAM Channel B Interface ............................................................35
DDR2 DRAM Reference and Compensation ...............................................36
PCI Express* Interface Signals ...............................................................36
Analog Display Signals ..........................................................................36
Clocks, Reset, and Miscellaneous ............................................................37
Direct Media Interface (DMI)..................................................................38
Controller Link (CL) ..............................................................................39
Intel® Serial DVO (SDVO) Interface ........................................................39
2.10.1 SDVO/PCI Express* Signal Mapping ...........................................41
Power, Ground .....................................................................................42
System Address Map .......................................................................................44
3.1
3.2
3.3
Datasheet
Terminology ........................................................................................20
Reference Documents ...........................................................................22
GMCH Overview ...................................................................................23
1.3.1
Host Interface.........................................................................23
1.3.2
System Memory Interface.........................................................24
1.3.3
Direct Media Interface (DMI).....................................................25
1.3.4
PCI Express* Interface.............................................................25
1.3.5
Graphics Features ...................................................................26
1.3.6
SDVO and Analog Display Features ............................................26
1.3.7
GMCH Clocking .......................................................................27
1.3.8
Power Management .................................................................28
1.3.9
Thermal Sensor ......................................................................28
Legacy Address Range ..........................................................................46
3.1.1
DOS Range (0h – 9_FFFFh).......................................................48
3.1.2
Legacy Video Area (A_0000h–B_FFFFh) ......................................48
3.1.3
Expansion Area (C_0000h–D_FFFFh)..........................................48
3.1.4
Extended System BIOS Area (E_0000h-E_FFFFh).........................49
3.1.5
System BIOS Area (F_0000h – F_FFFFh) ....................................49
3.1.6
PAM Memory Area Details.........................................................50
3.1.7
Legacy Interrupt Routing ..........................................................50
Main Memory Address Range (1MB – TOLUD) ...........................................50
3.2.1
ISA Hole (15MB-16MB) ............................................................51
3.2.2
TSEG.....................................................................................51
3.2.3
Pre-allocated Memory ..............................................................52
PCI Memory Address Range (TOLUD – 4GB) .............................................52
3.3.1
APIC Configuration Space (FEC0_0000h–FECF_FFFFh) ..................54
3.3.2
HSEG (FEDA_0000h–FEDB_FFFFh).............................................54
3.3.3
FSB Interrupt Memory Space (FEE0_0000–FEEF_FFFFh) ............... 54
3
3.4
3.5
3.6
3.7
3.8
3.9
3.10
3.11
4
GMCH Register Description ...............................................................................66
4.1
4.2
4.3
4.4
4.5
5
Register Terminology ............................................................................67
Configuration Process and Registers ........................................................68
4.2.1
Platform Configuration Structure ...............................................68
Configuration Mechanisms .....................................................................69
4.3.1
Standard PCI Configuration Mechanism ......................................69
4.3.2
PCI Express* Enhanced Configuration Mechanism ........................70
Routing Configuration Accesses ..............................................................71
4.4.1
Internal Device Configuration Accesses.......................................72
4.4.2
Bridge Related Configuration Accesses........................................73
I/O Mapped Registers ...........................................................................74
4.5.1
CONFIG_ADDRESS—Configuration Address Register ..................... 74
4.5.2
CONFIG_DATA—Configuration Data Register ............................... 76
DRAM Controller Registers (D0:F0)....................................................................78
5.1
4
3.3.4
High BIOS Area.......................................................................54
Main Memory Address Space (4 GB to TOUUD) .........................................55
3.4.1
Memory Re-claim Background ...................................................56
3.4.2
Memory Reclaiming .................................................................56
PCI Express* Configuration Address Space...............................................56
PCI Express* Graphics Attach (PEG)........................................................57
Graphics Memory Address Ranges...........................................................58
System Management Mode (SMM) ..........................................................58
3.8.1
SMM Space Definition ..............................................................59
3.8.2
SMM Space Restrictions............................................................59
3.8.3
SMM Space Combinations .........................................................60
3.8.4
SMM Control Combinations .......................................................60
3.8.5
SMM Space Decode and Transaction Handling..............................61
3.8.6
Processor WB Transaction to an Enabled SMM Address Space ........61
3.8.7
SMM Access Through GTT TLB ...................................................61
Memory Shadowing ..............................................................................62
I/O Address Space................................................................................62
3.10.1 PCI Express* I/O Address Mapping ............................................63
MCH Decode Rules and Cross-Bridge Address Mapping...............................63
3.11.1 Legacy VGA and I/O Range Decode Rules ...................................64
DRAM Controller (D0:F0).......................................................................78
5.1.1
VID—Vendor Identification........................................................80
5.1.2
DID—Device Identification ........................................................80
5.1.3
PCICMD—PCI Command ...........................................................81
5.1.4
PCISTS—PCI Status .................................................................82
5.1.5
RID—Revision Identification ......................................................83
5.1.6
CC—Class Code.......................................................................84
5.1.7
MLT—Master Latency Timer ......................................................84
5.1.8
HDR—Header Type ..................................................................85
5.1.9
SVID—Subsystem Vendor Identification......................................85
5.1.10 SID—Subsystem Identification ..................................................85
5.1.11 CAPPTR—Capabilities Pointer ....................................................86
5.1.12 PXPEPBAR—PCI Express* Egress Port Base Address .....................86
5.1.13 MCHBAR—GMCH Memory Mapped Register Range Base ................87
5.1.14 GGC—GMCH Graphics Control ...................................................88
5.1.15 DEVEN—Device Enable.............................................................89
5.1.16 PCIEXBAR—PCI Express* Register Range Base Address ................90
Datasheet
5.2
Datasheet
5.1.17 DMIBAR—Root Complex Register Range Base Address ..................92
5.1.18 PAM0—Programmable Attribute Map 0........................................93
5.1.19 PAM1—Programmable Attribute Map 1........................................95
5.1.20 PAM2—Programmable Attribute Map 2........................................96
5.1.21 PAM3—Programmable Attribute Map 3........................................97
5.1.22 PAM4—Programmable Attribute Map 4........................................98
5.1.23 PAM5—Programmable Attribute Map 5........................................99
5.1.24 PAM6—Programmable Attribute Map 6...................................... 100
5.1.25 LAC—Legacy Access Control.................................................... 101
5.1.26 REMAPBASE—Remap Base Address Register.............................. 102
5.1.27 REMAPLIMIT—Remap Limit Address Register ............................. 102
5.1.28 SMRAM—System Management RAM Control .............................. 103
5.1.29 ESMRAMC—Extended System Management RAM Control ............. 104
5.1.30 TOM—Top of Memory............................................................. 105
5.1.31 TOUUD—Top of Upper Usable Dram ......................................... 106
5.1.32 GBSM—Graphics Base of Stolen Memory................................... 107
5.1.33 TSEGMB—TSEG Memory Base ................................................. 107
5.1.34 TOLUD—Top of Low Usable DRAM ............................................ 108
5.1.35 ERRSTS—Error Status ............................................................ 109
5.1.36 ERRCMD—Error Command ...................................................... 110
5.1.37 SMICMD—SMI Command........................................................ 111
5.1.38 SKPD—Scratchpad Data ......................................................... 111
5.1.39 CAPID0—Capability Identifier .................................................. 112
MCHBAR ........................................................................................... 113
5.2.1
CHDECMISC—Channel Decode Miscellaneous............................. 116
5.2.2
C0DRB0—Channel 0 DRAM Rank Boundary Address 0 ................. 117
5.2.3
C0DRB1—Channel 0 DRAM Rank Boundary Address 1 ................. 118
5.2.4
C0DRB2—Channel 0 DRAM Rank Boundary Address 2 ................. 119
5.2.5
C0DRB3—Channel 0 DRAM Rank Boundary Address 3 ................. 119
5.2.6
C0DRA01—Channel 0 DRAM Rank 0,1 Attribute ......................... 120
5.2.7
C0DRA23—Channel 0 DRAM Rank 2,3 Attribute ......................... 121
5.2.8
C0CYCTRKPCHG—Channel 0 CYCTRK PCHG............................... 121
5.2.9
C0CYCTRKACT—Channel 0 CYCTRK ACT ................................... 122
5.2.10 C0CYCTRKWR—Channel 0 CYCTRK WR ..................................... 123
5.2.11 C0CYCTRKRD—Channel 0 CYCTRK READ................................... 124
5.2.12 C0CYCTRKREFR—Channel 0 CYCTRK REFR ................................ 124
5.2.13 C0CKECTRL—Channel 0 CKE Control ........................................ 125
5.2.14 C0REFRCTRL—Channel 0 DRAM Refresh Control......................... 126
5.2.15 C0ODTCTRL—Channel 0 ODT Control ....................................... 128
5.2.16 C1DRB0—Channel 1 DRAM Rank Boundary Address 0 ................. 129
5.2.17 C1DRB1—Channel 1 DRAM Rank Boundary Address 1 ................. 129
5.2.18 C1DRB2—Channel 1 DRAM Rank Boundary Address 2 ................. 130
5.2.19 C1DRB3—Channel 1 DRAM Rank Boundary Address 3 ................. 130
5.2.20 C1DRA01—Channel 1 DRAM Rank 0,1 Attributes ........................ 131
5.2.21 C1DRA23—Channel 1 DRAM Rank 2,3 Attributes ........................ 131
5.2.22 C1CYCTRKPCHG—Channel 1 CYCTRK PCHG............................... 132
5.2.23 C1CYCTRKACT—Channel 1 CYCTRK ACT ................................... 133
5.2.24 C1CYCTRKWR—Channel 1 CYCTRK WR ..................................... 134
5.2.25 C1CYCTRKRD—Channel 1 CYCTRK READ................................... 135
5.2.26 C1CKECTRL—Channel 1 CKE Control ........................................ 136
5.2.27 C1REFRCTRL—Channel 1 DRAM Refresh Control......................... 137
5.2.28 C1ODTCTRL—Channel 1 ODT Control ....................................... 139
5.2.29 EPC0DRB0—ME Channel 0 DRAM Rank Boundary Address 0........ 140
5.2.30 EPC0DRB1—ME Channel 0 DRAM Rank Boundary Address 1 ........ 140
5.2.31 EPC0DRB2— ME Channel 0 DRAM Rank Boundary Address 2........ 141
5
5.3
6
PCI Express* Registers (D1:F0) ...................................................................... 162
6.1
6
5.2.32 EPC0DRB3— ME Channel 0 DRAM Rank Boundary Address 3........ 141
5.2.33 EPC0DRA01—ME Channel 0 DRAM Rank 0,1 Attribute ................. 142
5.2.34 EPC0DRA23—ME Channel 0 DRAM Rank 2,3 Attribute ................. 142
5.2.35 EPDCYCTRKWRTPRE—EPD CYCTRK WRT PRE............................. 143
5.2.36 EPDCYCTRKWRTACT—EPD CYCTRK WRT ACT ............................ 143
5.2.37 EPDCYCTRKWRTWR—EPD CYCTRK WRT WR .............................. 144
5.2.38 EPDCYCTRKWRTRD—EPD CYCTRK WRT READ............................ 144
5.2.39 EPDCKECONFIGREG—EPD CKE Related Configuration Register ..... 145
5.2.40 MEMEMSPACE—ME Memory Space Configuration ....................... 147
5.2.41 EPDREFCONFIG—EP DRAM Refresh Configuration....................... 148
5.2.42 TSC1—Thermal Sensor Control 1 ............................................. 150
5.2.43 TSC2—Thermal Sensor Control 2 ............................................. 151
5.2.44 TSS—Thermal Sensor Status................................................... 152
5.2.45 TSTTP—Thermal Sensor Temperature Trip Point......................... 152
5.2.46 TCO—Thermal Calibration Offset.............................................. 153
5.2.47 THERM1—Hardware Throttle Control ........................................ 154
5.2.48 TIS—Thermal Interrupt Status ................................................ 154
5.2.49 TSMICMD—Thermal SMI Command.......................................... 156
5.2.50 PMSTS—Power Management Status ......................................... 157
MPBAR.............................................................................................. 158
5.3.1
EPESD—EP Element Self Description ........................................ 158
5.3.2
EPLE1D—Controller Link Entry 1 Description.............................. 159
5.3.3
EPLE1A— Controller Link Entry 1 Address ................................. 159
5.3.4
EPLE2D— Controller Link Entry 2 Description............................. 160
5.3.5
EPLE2A—EP Link Entry 2 Address ............................................ 161
PCI Express* Configuration Register Details (D1:F0) ............................... 165
6.1.1
VID1—Vendor Identification .................................................... 165
6.1.2
DID1—Device Identification .................................................... 165
6.1.3
PCICMD1—PCI Command ....................................................... 166
6.1.4
PCISTS1—PCI Status ............................................................. 168
6.1.5
RID1—Revision Identification .................................................. 169
6.1.6
CC1—Class Code ................................................................... 169
6.1.7
CL1—Cache Line Size............................................................. 170
6.1.8
HDR1—Header Type .............................................................. 170
6.1.9
PBUSN1—Primary Bus Number ................................................ 170
6.1.10 SBUSN1—Secondary Bus Number ............................................ 171
6.1.11 SUBUSN1—Subordinate Bus Number........................................ 171
6.1.12 IOBASE1—I/O Base Address ................................................... 172
6.1.13 IOLIMIT1—I/O Limit Address................................................... 172
6.1.14 SSTS1—Secondary Status ...................................................... 173
6.1.15 MBASE1—Memory Base Address.............................................. 174
6.1.16 MLIMIT1—Memory Limit Address ............................................. 175
6.1.17 PMBASE1—Prefetchable Memory Base Address .......................... 176
6.1.18 PMLIMIT1—Prefetchable Memory Limit Address.......................... 177
6.1.19 PMBASEU1—Prefetchable Memory Base Address ........................ 178
6.1.20 PMLIMITU1—Prefetchable Memory Limit Address........................ 179
6.1.21 CAPPTR1—Capabilities Pointer................................................. 180
6.1.22 INTRLINE1—Interrupt Line...................................................... 180
6.1.23 INTRPIN1—Interrupt Pin......................................................... 180
6.1.24 BCTRL1—Bridge Control ......................................................... 181
6.1.25 PM_CAPID1—Power Management Capabilities............................ 183
6.1.26 PM_CS1—Power Management Control/Status ............................ 184
6.1.27 SS_CAPID—Subsystem ID and Vendor ID Capabilities ................ 185
Datasheet
6.1.28
6.1.29
6.1.30
6.1.31
6.1.32
6.1.33
6.1.34
6.1.35
6.1.36
6.1.37
6.1.38
6.1.39
6.1.40
6.1.41
6.1.42
6.1.43
6.1.44
6.1.45
6.1.46
6.1.47
6.1.48
6.1.49
6.1.50
6.1.51
6.1.52
6.1.53
6.1.54
6.1.55
6.1.56
6.1.57
6.1.58
7
Direct Memory Interface (DMI) Registers.......................................................... 214
7.1
8
Direct Memory Interface (DMI) Configuration Register Details ................... 215
7.1.1
DMIVCECH—DMI Virtual Channel Enhanced Capability ................ 215
7.1.2
DMIPVCCAP1—DMI Port VC Capability Register 1 ....................... 216
7.1.3
DMIPVCCAP2—DMI Port VC Capability Register 2 ....................... 216
7.1.4
DMIPVCCTL—DMI Port VC Control............................................ 217
7.1.5
DMIVC0RCAP—DMI VC0 Resource Capability ............................. 217
7.1.6
DMIVC0RCTL0—DMI VC0 Resource Control ............................... 218
7.1.7
DMIVC0RSTS—DMI VC0 Resource Status .................................. 219
7.1.8
DMIVC1RCAP—DMI VC1 Resource Capability ............................. 219
7.1.9
DMIVC1RCTL1—DMI VC1 Resource Control ............................... 220
7.1.10 DMIVC1RSTS—DMI VC1 Resource Status .................................. 221
7.1.11 DMILCAP—DMI Link Capabilities .............................................. 221
7.1.12 DMILCTL—DMI Link Control .................................................... 222
7.1.13 DMILSTS—DMI Link Status ..................................................... 223
Integrated Graphics Device Registers (D2:F0,F1)............................................... 224
8.1
Datasheet
SS—Subsystem ID and Subsystem Vendor ID ........................... 185
MSI_CAPID—Message Signaled Interrupts Capability ID .............. 186
MC—Message Control............................................................. 186
MA—Message Address............................................................ 187
MD—Message Data ................................................................ 187
PEG_CAPL—PCI Express*-G Capability List................................ 188
PEG_CAP—PCI Express*-G Capabilities..................................... 188
DCAP—Device Capabilities ...................................................... 189
DCTL—Device Control ............................................................ 190
DSTS—Device Status ............................................................. 191
LCAP—Link Capabilities .......................................................... 192
LCTL—Link Control ................................................................ 194
LSTS—Link Status ................................................................. 196
SLOTCAP—Slot Capabilities..................................................... 197
SLOTCTL—Slot Control ........................................................... 198
SLOTSTS—Slot Status............................................................ 201
RCTL—Root Control ............................................................... 202
RSTS—Root Status ................................................................ 203
PEGLC—PCI Express*-G Legacy Control .................................... 204
VCECH—Virtual Channel Enhanced Capability Header ................. 205
PVCCAP1—Port VC Capability Register 1 ................................... 205
PVCCAP2—Port VC Capability Register 2 ................................... 206
PVCCTL—Port VC Control........................................................ 206
VC0RCAP—VC0 Resource Capability ......................................... 207
VC0RCTL—VC0 Resource Control ............................................. 208
VC0RSTS—VC0 Resource Status .............................................. 209
RCLDECH—Root Complex Link Declaration Enhanced .................. 210
ESD—Element Self Description ................................................ 210
LE1D—Link Entry 1 Description ............................................... 211
LE1A—Link Entry 1 Address .................................................... 211
PEGSSTS—PCI Express*-G Sequence Status ............................. 212
Integrated Graphics Register Details (D2:F0).......................................... 224
8.1.1
VID2—Vendor Identification .................................................... 225
8.1.2
DID—Device Identification ...................................................... 226
8.1.3
PCICMD2—PCI Command ....................................................... 226
8.1.4
PCISTS2—PCI Status ............................................................. 228
8.1.5
RID2—Revision Identification .................................................. 229
7
8.2
8
8.1.6
CC—Class Code..................................................................... 229
8.1.7
CLS—Cache Line Size............................................................. 230
8.1.8
MLT2—Master Latency Timer................................................... 230
8.1.9
HDR2—Header Type .............................................................. 231
8.1.10 GMADR—Graphics Memory Range Address ................................ 231
8.1.11 IOBAR—I/O Base Address....................................................... 232
8.1.12 SVID2—Subsystem Vendor Identification .................................. 232
8.1.13 SID2—Subsystem Identification .............................................. 233
8.1.14 ROMADR—Video BIOS ROM Base Address ................................. 233
8.1.15 CAPPOINT—Capabilities Pointer ............................................... 234
8.1.16 INTRLINE—Interrupt Line ....................................................... 234
8.1.17 INTRPIN—Interrupt Pin .......................................................... 234
8.1.18 MINGNT—Minimum Grant ....................................................... 235
8.1.19 MAXLAT—Maximum Latency ................................................... 235
8.1.20 MCAPPTR—Mirror of Dev 0 Capabilities Pointer .......................... 236
8.1.21 CAPID0—Mirror of Dev0 Capability Identifier ............................. 236
8.1.22 MGGC— Mirror of Dev0 GMCH Graphics Control Register ............. 237
8.1.23 DEVEN—Mirror of Dev0 Device Enable ...................................... 238
8.1.24 SSRW—Software Scratch Read Write........................................ 239
8.1.25 BSM—Base of Stolen Memory.................................................. 239
8.1.26 HSRW—Hardware Scratch Read Write ...................................... 240
8.1.27 MSI_CAPID— Message Signaled Interrupts Capability ID ............. 240
8.1.28 MC—Message Control............................................................. 241
8.1.29 MA—Message Address............................................................ 242
8.1.30 MD—Message Data ................................................................ 242
8.1.31 GDRST—Graphics Debug Reset ............................................... 243
8.1.32 PMCAPID—Power Management Capabilities ID ........................... 244
8.1.33 PMCAP—Power Management Capabilities .................................. 244
8.1.34 PMCS—Power Management Control/Status ................................ 245
8.1.35 SWSMI—Software SMI ........................................................... 246
IGD Configuration Register Details (D2:F1) ............................................ 247
8.2.1
VID2—Vendor Identification .................................................... 249
8.2.2
DID2—Device Identification .................................................... 249
8.2.3
PCICMD2—PCI Command ....................................................... 250
8.2.4
PCISTS2—PCI Status ............................................................. 251
8.2.5
RID2—Revision Identification .................................................. 252
8.2.6
CC—Class Code Register ........................................................ 252
8.2.7
CLS—Cache Line Size............................................................. 253
8.2.8
MLT2—Master Latency Timer................................................... 253
8.2.9
HDR2—Header Type .............................................................. 254
8.2.10 MMADR—Memory Mapped Range Address ................................. 254
8.2.11 SVID2—Subsystem Vendor Identification .................................. 255
8.2.12 SID2—Subsystem Identification .............................................. 255
8.2.13 ROMADR—Video BIOS ROM Base Address ................................. 256
8.2.14 CAPPOINT—Capabilities Pointer ............................................... 256
8.2.15 MINGNT—Minimum Grant ....................................................... 257
8.2.16 MAXLAT—Maximum Latency ................................................... 257
8.2.17 MCAPPTR—Mirror of Dev 0 Capabilities Pointer .......................... 257
8.2.18 CAPID0—Capability Identifier .................................................. 258
8.2.19 MGGC—Mirror of Dev 0 GMCH Graphics Control Register ............. 259
8.2.20 DEVEN—Device Enable........................................................... 260
8.2.21 SSRW—Mirror of Func0 Software Scratch Read Write.................. 261
8.2.22 BSM—Mirror of Func0 Base of Stolen Memory............................ 262
8.2.23 HSRW—Mirror of Dev2 Func0 Hardware Scratch Read Write ........ 262
8.2.24 GDRST—Mirror of Dev2 Func0 Graphics Reset ........................... 263
Datasheet
8.2.25
8.2.26
8.2.27
8.2.28
9
Manageability Engine (ME) Registers (D3:F0) ................................................... 268
9.1
10
Host Embedded Controller Interface (HECI1) Configuration
Register Details (D3:F0) ...................................................................... 268
9.1.1
ID—Identifiers ...................................................................... 269
9.1.2
CMD—Command ................................................................... 269
9.1.3
STS—Device Status ............................................................... 271
9.1.4
RID—Revision ID................................................................... 272
9.1.5
CC—Class Code..................................................................... 272
9.1.6
CLS—Cache Line Size............................................................. 272
9.1.7
MLT—Master Latency Timer .................................................... 273
9.1.8
HTYPE—Header Type ............................................................. 273
9.1.9
HECI_MBAR—HECI MMIO Base Address .................................... 274
9.1.10 SS—Sub System Identifiers .................................................... 274
9.1.11 CAP—Capabilities Pointer........................................................ 275
9.1.12 INTR—Interrupt Information ................................................... 275
9.1.13 MGNT—Minimum Grant .......................................................... 275
9.1.14 MLAT—Maximum Latency ....................................................... 276
9.1.15 HFS—Host Firmware Status .................................................... 276
9.1.16 PID—PCI Power Management Capability ID ............................... 276
9.1.17 PC—PCI Power Management Capabilities................................... 277
9.1.18 PMCS—PCI Power Management Control And Status .................... 278
9.1.19 MID—Message Signaled Interrupt Identifiers ............................. 279
9.1.20 MC—Message Signaled Interrupt Message Control ...................... 279
9.1.21 MA—Message Signaled Interrupt Message Address ..................... 280
9.1.22 MD—Message Signaled Interrupt Message Data ......................... 280
9.1.23 HIDM—HECI Interrupt Delivery Mode ....................................... 281
Functional Description ................................................................................... 282
10.1
10.2
10.3
10.4
10.5
Datasheet
PMCAPID—Mirror of Fun 0 Power Management Capabilities ID...... 263
PMCAP—Mirror of Fun 0 Power Management Capabilities ............. 264
PMCS—Power Management Control/Status ................................ 265
SWSMI—Mirror of Func0 Software SMI ..................................... 266
Host Interface.................................................................................... 282
10.1.1 FSB IOQ Depth ..................................................................... 282
10.1.2 FSB OOQ Depth .................................................................... 282
10.1.3 FSB GTL+ Termination ........................................................... 282
10.1.4 FSB Dynamic Bus Inversion .................................................... 283
10.1.5 APIC Cluster Mode Support ..................................................... 283
System Memory Controller................................................................... 284
10.2.1 Memory Organization Modes ................................................... 284
10.2.2 DRAM Technologies and Organization ....................................... 286
10.2.3 Main Memory DRAM Address Translation and Decoding ............... 288
10.2.4 DRAM Clock Generation.......................................................... 291
10.2.5 Suspend to RAM and Resume.................................................. 291
10.2.6 DDR2 On-Die Termination ...................................................... 291
PCI Express* ..................................................................................... 291
10.3.1 PCI Express* Architecture....................................................... 291
10.3.2 Intel® Serial Digital Video Output (SDVO) ................................. 292
Integrated Graphics Controller ............................................................. 296
10.4.1 Integrated Graphics Device Overview ....................................... 296
Display Interfaces .............................................................................. 297
10.5.1 Analog Display Port Characteristics .......................................... 299
10.5.2 Digital Display Interface ......................................................... 300
9
10.6
10.7
10.8
11
Electrical Characteristics ................................................................................ 310
11.1
11.2
11.3
12
Ballout.............................................................................................. 322
Package ............................................................................................ 337
Testability.................................................................................................... 339
13.1
13.2
13.3
13.4
10
Absolute Minimum and Maximum Ratings .............................................. 310
11.1.1 Current Consumption ............................................................. 311
Signal Groups .................................................................................... 313
Buffer Supply and DC Characteristics .................................................... 316
11.3.1 I/O Buffer Supply Voltages ..................................................... 316
11.3.2 General DC Characteristics ..................................................... 317
11.3.3 R, G, B / CRT DAC Display DC Characteristics............................ 321
Ballout and Package Information ..................................................................... 322
12.1
12.2
13
10.5.3 Multiple Display Configurations................................................ 303
Power Management ............................................................................ 303
Thermal Sensor.................................................................................. 304
10.7.1 PCI Device 0, Function 0 ........................................................ 304
10.7.2 MCHBAR Thermal Sensor Registers .......................................... 304
10.7.3 Programming Sequence ......................................................... 305
10.7.4 Trip Point Temperature Programming ....................................... 305
Clocking............................................................................................ 307
XOR Test Mode Initialization ................................................................ 340
XOR Chain Definition .......................................................................... 342
XOR Chains ....................................................................................... 343
PADs Excluded from XOR Mode(s)......................................................... 351
Datasheet
Figures
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
1-1. Intel® G35 Express Chipset System Block Diagram Example ..................19
3-1. System Address Ranges...................................................................46
3-2. DOS Legacy Address Range..............................................................47
3-3. Main Memory Address Range ............................................................51
3-4. PCI Memory Address Range..............................................................53
4-1. Conceptual G Platform PCI Configuration Diagram ...............................68
4-2. Memory Map to PCI Express* Device Configuration Space.....................70
4-3. GMCH Configuration Cycle Flow Chart ................................................72
9-1. System Memory Styles .................................................................. 285
9-2. SDVO Conceptual Block Diagram..................................................... 293
9-3. Concurrent sDVO / PCI Express* Non-Reversed Configurations............ 295
9-4. Concurrent sDVO / PCI Express* Reversed Configurations .................. 295
9-5. Intel® G35 Express Chipset System Clock Diagram ............................ 308
11-1. GMCH Ballout Diagram (Top View Left – Columns 43–30) ................. 323
11-2. GMCH Ballout Diagram (Top View Middle– Columns 29–15)............... 324
11-3. GMCH Ballout Diagram (Top View Right – Columns 14–0) ................. 325
11-4. GMCH Package Drawing ............................................................... 338
12-1. XOR Test Mode Initialization Cycles ............................................... 340
Tables
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Datasheet
3-1.
3-2.
3-3.
3-4.
3-5.
Expansion Area Memory Segments .....................................................49
Extended System BIOS Area Memory Segments ...................................49
System BIOS Area Memory Segments.................................................49
Specifics of Legacy Interrupt Routing ..................................................50
Pre-allocated Memory Example for 64 MB DRAM, 1-MB VGA and
1-MB TSEG......................................................................................52
3-6. Pre-Allocated Memory Example for 64-MB DRAM, 1-MB VGA and
1-MB TSEG......................................................................................59
3-7. SMM Space Table.............................................................................60
3-8. SMM Control ...................................................................................60
5-1. DRAM Controller Register Address Map (D0:F0)....................................78
5-2. MCHBAR Register Address Map ........................................................ 113
5-3. DRAM Rank Attribute Register Programming ...................................... 120
5-4. EPBAR Register Address Map ........................................................... 158
6-1. PCI Express* Register Address Map (D1:F0) ...................................... 162
7-1. DMI Register Address Map............................................................... 214
8-1. Integrated Graphics Device Register Address Map (D2:F0) ................... 224
8-2. Integrated Graphics Device Register Address Map (D2:F1) ................... 247
9-1. HECI1 Register Address Map (D3:F0) ................................................ 268
9-1. Sample System Memory Organization with Interleaved Channels .......... 284
9-2. Sample System Memory Organization with Asymmetric Channels.......... 284
9-3. DDR2 DIMM Supported Configurations .............................................. 288
9-4. DRAM Address Translation (Single Channel/Dual Asymmetric Mode)...... 289
9-5. DRAM Address Translation (Dual Channel Symmetric Mode) ................. 290
9-6. Concurrent sDVO / PCI Express* Configuration Strap Controls.............. 294
11
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
12
9-7. Display Port Characteristics ............................................................. 298
9-8. Analog Port Characteristics.............................................................. 299
10-1. Absolute Minimum and Maximum Ratings ........................................ 310
10-2. Current Consumption in S0............................................................ 312
10-3. Signal Groups .............................................................................. 314
10-4. I/O Buffer Supply Voltage.............................................................. 316
10-5. DC Characteristics ........................................................................ 317
10-6. R, G, B / CRT DAC Display DC Characteristics: Functional Operating
Range (VCCA_DAC = 3.3 V ± 5%) .................................................. 321
11-1. GMCH Ballout Sorted by Signal Name.............................................. 326
12-1. XOR Chain Outputs....................................................................... 342
12-2. XOR Chain 0................................................................................ 343
12-3. XOR Chain 1................................................................................ 344
12-4. XOR Chain 2................................................................................ 344
12-5. XOR Chain 3................................................................................ 344
12-6. XOR Chain 4................................................................................ 345
12-7. XOR Chain 5................................................................................ 345
12-8. XOR Chain 6................................................................................ 345
12-9. XOR Chain 7................................................................................ 347
12-10. XOR Chain 8 .............................................................................. 347
12-11. XOR Chain 9 .............................................................................. 347
12-12. XOR Chain 10 ............................................................................ 348
12-13. XOR Chain 11 ............................................................................ 349
12-14. XOR Chain 12 ............................................................................ 349
12-15. XOR Chain 13 ............................................................................ 349
12-16. XOR Chain 14 ............................................................................ 349
12-17. XOR Pad Exclusion List ................................................................ 351
Datasheet
Revision History
Revision
Number
-001
Datasheet
Description
• Initial release.
Date
August 2007
13
14
Datasheet
Intel® 82G35 GMCH Features
• Processor/Host Interface (FSB)
• Integrated Graphics Device
⎯
Supports Intel® Core™2 Duo desktop processor
⎯
Core frequency of 400 MHz
⎯
Supports Intel® Core™2 Quad desktop processor
⎯
1.6 GP/s pixel rate
⎯
800/1067 MT/s (200/266 MHz) FSB
⎯
Hyper-Threading Technology (HT Technology)
⎯
FSB Dynamic Bus Inversion (DBI)
⎯
36-bit host bus addressing
⎯
12-deep In-Order Queue
⎯
1-deep Defer Queue
⎯
resistors
⎯
⎯
Engine
GTL+ bus driver with integrated GTL termination
Supports cache Line Size of 64 bytes
High-Quality 3D Setup and Render
⎯
High-Quality Texture Engine
⎯
3D Graphics Rendering Enhancements
⎯
2D Graphics
⎯
Video Overlay
⎯
Multiple Overlay Functionality
• Analog Display
⎯
350 MHz Integrated 24-bit RAMDAC
• System Memory Interface
⎯
Up to 2048x1536 @ 75 Hz refresh
⎯
One or two channels (each channel consisting of
64 data lines)
⎯
Hardware Color Cursor Support
⎯
DDC2B Compliant Interface
⎯
Single or Dual Channel memory organization
⎯
DDR2-800/667 frequencies
⎯
Unbuffered, non-ECC DIMMs only
⎯
Supports 1-Gb, 512-Mb DDR2 technologies for x8
and x16 devices
⎯
4 GB maximum memory
• Direct Media Interface (DMI)
⎯
⎯
direction)
Chip-to-chip connection interface to Intel ICH7
2 GB/s point-to-point DMI to ICH9 (1 GB/s each
⎯
100 MHz reference clock (shared with PCI Express
graphics attach)
⎯
32-bit downstream addressing
⎯
Messaging and Error Handling
• PCI Express* Interface
⎯
• Digital Display
⎯
⎯
interface
225 MHz dot clock on each 12-bit
⎯
Flat panels up to 2048x1536 @ 60 Hz or
digital CRT/HDTV at 1400x1050 @ 85Hz
⎯
Dual independent display options with
digital display
⎯
Multiplexed digital display channels
(supported with ADD2 Card).
⎯
encoders
Supports TMDS transmitters or TV-Out
⎯
ADD2/MEC card uses PCI Express
graphics x16 connector
⎯
Two channels multiplexed with PCI
Express* Graphics port
One x16 PCI Express port
⎯
Compatible with the PCI Express Base
Specification, Revision 1.1
SDVO ports in single mode supported
⎯
Supports Hot-Plug and Display
• Thermal Sensor
⎯
Raw bit rate on data pins of 2.5 Gb/s resulting in
a real bandwidth per pair of 250 MB/s
⎯
Catastrophic Trip Point support
⎯
Hot Trip Point support for SMI generation
• Power Management
⎯
PC99 suspend to DRAM support (“STR”,
mapped to ACPI state S3)
⎯
ACPI Revision 2.0 compatible power
management
S5
2
Datasheet
⎯
Supports processor states: C0, C1, C2
⎯
Supports System states: S0, S1, S3, and
⎯
Supports processor Thermal Management
15
• Package
⎯
FC-BGA. 34 mm × 34 mm. The 1226
balls are located in a non-grid pattern
§
16
Datasheet
Datasheet
17
Introduction
1
Introduction
The Intel® G35 Express Chipset is designed for use with the Intel® Core™2 Duo
desktop processor / Intel® Core™2 Quad desktop processor based platforms. The
chipset contains two components: 82G35 GMCH for the host bridge and I/O Controller
Hub 8 (ICH8) for the I/O subsystem. The 82G35 GMCH is part of the Intel® G35
Express Chipset. The ICH8 is the eight generation I/O Controller Hub and provides a
multitude of I/O related functions. Figure 1-1 shows an example system block diagram
for the Intel® G35 Express Chipset.
This document is the datasheet for the Intel® 82G35 Graphics and Memory Controller
Hub (GMCH). Topics covered include; signal description, system memory map, PCI
register description, a description of the GMCH interfaces and major functional units,
electrical characteristics, ballout definitions, and package characteristics.
Note: Unless otherwise specified, ICH8 refers to the Intel® 82801HB ICH8, 82801HR ICH8R,
82801HDH ICH8DH, 82801HDO ICH8DO, 82801HBM ICH8M, and 82801HEM ICH8M-E
I/O Controller Hub components.
18
Datasheet
Introduction
Figure 1-1. Intel® G35 Express Chipset System Block Diagram Example
Datasheet
19
Introduction
1.1
Terminology
Term
20
Description
ADD Card
Advanced Digital Display Card. Provides digital display options for an Intel
Graphics Controller that supports ADD cards (have DVOs multiplexed with
AGP interface). Keyed like an AGP 4x card and plugs into an AGP connector.
Will not work with an Intel Graphics Controller that implements Intel®
SDVO.
ADD2 Card
Advanced Digital Display Card – 2nd Generation. Provides digital display
options for an Intel graphics controller that supports ADD2 cards. Plugs into
an x16 PCI Express* connector but utilizes the multiplexed SDVO interface.
Will not work with an Intel Graphics Controller that supports Intel® DVO and
ADD cards.
Media
Expansion
Card
(MEC)
Media Expansion Card –. Provides digital display options for an Intel
Graphics Controller that supports MEC cards. Plugs into an x16 PCI Express
connector but utilizes the multiplexed SDVO interface. Adds Video In
capabilities to platform. Will not work with an Intel Graphics Controller that
supports DVO and ADD cards. Will function as an ADD2 card in an ADD2
supported system, but Video In capabilities will not work.
Core
The internal base logic in the GMCH
Processor
Refers to the Intel CoreTM2 Duo processors and Intel CoreTM2 Quad
processors
CRT
Cathode Ray Tube
DBI
Dynamic Bus Inversion
DDR2
A second generation Double Data Rate SDRAM memory technology
DMI
GMCH-Intel® ICH8 Direct Media Interface
DVI
Digital Video Interface. Specification that defines the connector and interface
for digital displays.
FSB
Front Side Bus, synonymous with Host or processor bus
Full Reset
Full reset is when PWROK is de-asserted. Warm reset is when both RSTIN#
and PWROK are asserted.
GMCH
Graphics Memory Controller Hub component that contains the processor
interface, DRAM controller, and x16 PCI Express port (typically the external
graphics interface). It communicates with the I/O controller hub (Intel®
ICH8*) over the DMI interconnect. Throughout this document, GMCH
refers to the G35 GMCH, unless otherwise specified.
HDMI
High Definition Multimedia Interface – HDMI supports standard, enhanced,
or high-definition video, plus multi-channel digital audio on a single cable. It
transmits all ATSC HDTV standards and supports 8-channel digital audio,
with bandwidth to spare for future requirements and enhancements
(additional details available through http://www.hdmi.org/)
Host
This term is used synonymously with processor
INTx
An interrupt request signal where X stands for interrupts A, B, C and D
IOQ
In Order Queue
Datasheet
Introduction
Term
Datasheet
Description
Intel® ICH8
Eighth generation I/O Controller Hub component that contains additional
functionality compared to previous Intel® ICHs, The Intel® I/O Controller
Hub component contains the primary PCI interface, LPC interface, USB2,
SATA, and other I/O functions. It communicates with the GMCH over a
proprietary interconnect called DMI. For this GMCH, the term Intel® ICH
refers to Intel® ICH8.
IGD
Internal Graphics Device
LCD
Liquid Crystal Display
LVDS
Low Voltage Differential Signaling. A high speed, low power data
transmission standard used for display connections to LCD panels.
OOQ
Out of Order Queuing:
MSI
Message Signaled Interrupt. A transaction initiated outside the host,
conveying interrupt information to the receiving agent through the same
path that normally carries read and write commands.
PCI Express*
Third Generation Input Output (PCI Express) Graphics Attach called PCI
Express Graphics. A high-speed serial interface whose configuration is
software compatible with the existing PCI specifications. The specific PCI
Express implementation intended for connecting the GMCH to an external
Graphics Controller is an x16 link and replaces AGP.
Primary PCI
The physical PCI bus that is driven directly by the Intel® ICH8 component.
Communication between Primary PCI and the GMCH occurs over DMI. Note
that the Primary PCI bus is not PCI Bus 0 from a configuration standpoint.
SCI
System Control Interrupt. Used in ACPI protocol.
SDVO
Serial Digital Video Out (SDVO). Digital display channel that serially
transmits digital display data to an external SDVO device. The SDVO device
accepts this serialized format and then translates the data into the
appropriate display format (i.e. TMDS, LVDS, and TV-Out). This interface is
not electrically compatible with the previous digital display channel - DVO.
For G35, it will be multiplexed on a portion of the x16 graphics PCI Express
interface.
SDVO Device
Third party codec that utilizes SDVO as an input. May have a variety of
output formats, including DVI, LVDS, HDMI, TV-out, etc.
SERR
An indication that an unrecoverable error has occurred on an I/O bus.
SMI
System Management Interrupt. Used to indicate any of several system
conditions such as thermal sensor events, throttling activated, access to
System Management RAM, chassis open, or other system state related
activity.
Rank
A unit of DRAM corresponding to eight x8 SDRAM devices in parallel or four
x16 SDRAM devices in parallel, ignoring ECC. These devices are usually, but
not always, mounted on a single side of a DIMM.
TMDS
Transition Minimized Differential Signaling. Signaling interface from Silicon
Image that is used in DVI and HDMI.
VCO
Voltage Controlled Oscillator
UMA
Unified Memory Architecture. Describes an IGD using system memory for its
frame buffers.
21
Introduction
1.2
22
Reference Documents
Document Name
Location
Intel® G35 Express Chipset Specification Update
http://www.intel.com
/design/chipsets/specupdt/
317608.htm
Intel® G35 Express Chipset Family Thermal and Mechanical
Design Guide.
http://www.intel.com
/design/chipsets/designex/
317609.htm
Intel® Core™2 Duo Desktop Processor, Intel® Pentium® Dual
Core Processor, and Intel® Pentium® 4 Processor 6x1 Δ
Sequence Thermal and Mechanical Design Guide
http://www.intel.com/desig
n/ processor/designex/
313685.htm
Intel® I/O Controller Hub 8 (ICH8) Family Datasheet
http://www.intel.com/desig
n/chipsets/datashts/31305
6.htm
Designing for Energy Efficiency White Paper
http://www.intel.com/desig
n/chipsets/applnots/316970
.htm
Intel® P35/G33 Express Chipset Memory Technology and
Configuration Guide White Paper
http://www.intel.com/desig
n/chipsets/applnots/316971
.htm
Advanced Configuration and Power Interface Specification,
Version 2.0
http://www.acpi.info/
Advanced Configuration and Power Interface Specification,
Version 1.0b
http://www.acpi.info/
The PCI Local Bus Specification, Version 2.3
http://www.pcisig.com/spe
cifications
PCI Express* Specification, Version 1.1
http://www.pcisig.com/spe
cifications
Datasheet
Introduction
1.3
GMCH Overview
The 82G35 Graphics and Memory Controller Hub (GMCH) is designed for use with the
Intel® CoreTM2 Duo processors and Intel® CoreTM2 Quad processors in desktop
platforms. The role of a GMCH in a system is to manage the flow of information
between its four interfaces: the processor interface (FSB), the System Memory
interface (DRAM controller), the External Graphics interface, and the I/O Controller
through DMI interface. This includes arbitrating between the four interfaces when each
initiates transactions. The GMCH is optimized for the Intel® CoreTM2 Duo processor
and Intel® CoreTM2 Quad processor in an LGA775 socket. It supports one or two
channels of DDR2 SDRAM. It also supports the PCI Express* based external graphics
attach. The G35 chipset platform supports the eighth generation I/O Controller Hub
(Intel ICH8) to provide a multitude of I/O related features.
1.3.1
Host Interface
The GMCH can use a single LGA775 socket processor. The GMCH supports a FSB
frequencies of 800/1066/1333 MHz using a scalable FSB Vcc_CPU. It supports 36-bit
host addressing, decoding up to 8 GB of the processor’s memory address space. Hostinitiated I/O cycles are decoded to PCI Express, DMI, or the GMCH configuration
space. Host-initiated memory cycles are decoded to PCI Express, DMI or system DDR.
PCI Express device accesses to non-cacheable system memory are not snooped on the
host bus. Memory accesses initiated from PCI Express using PCI semantics and from
DMI to system SDRAM will be snooped on the host bus.
Processor/Host Interface (FSB) Details
Datasheet
•
Supports a single Intel® CoreTM2 Duo processors and Intel® CoreTM2 Quad
processors
•
Supports Front Side Bus (FSB) at 800/1066/1333 MT/s (200/266/333 MHz)
•
Supports FSB Dynamic Bus Inversion (DBI)
•
Supports 36-bit host bus addressing, allowing the processor to access the entire
64 GB of the host address space.
•
Has a 12-deep In-Order Queue to support up to twelve outstanding pipelined
address requests on the host bus
•
Has a 1-deep Defer Queue
•
Uses GTL+ bus driver with integrated GTL termination resistors
•
Supports a Cache Line Size of 64 bytes
23
Introduction
1.3.2
System Memory Interface
The GMCH integrates a system memory DDR2 controller with two, 64-bit wide
interfaces. Only Double Data Rate (DDR2) memory is supported; consequently, the
buffers support only SSTL_1.8 V signal interfaces. The memory controller interface is
fully configurable through a set of control registers.
System Memory Interface Details
•
⎯
⎯
24
The GMCH System Memory Controller directly supports one or two channels of
memory (each channel consisting of 64 data lines)
The memory channels are asymmetric: "Flex Memory" channels are assigned
addresses serially. Channel B addresses are assigned after all Channel A
addresses
The memory channels are interleaved: Addresses are ping-ponged between
the channels after each cache line (64-B boundary)
•
Supports DDR2 memory DIMM frequencies of 533, 667 and 800 MHz. The speed
used in all channels is the speed of the slowest DIMM in the system
•
I/O Voltage of 1.8 V for DDR2
•
Supports only unbuffered DIMMs
•
Supports maximum memory bandwidth of 6.4 GB/s in single-channel or dualchannel asymmetric mode, or 12.8 GB/s in dual-channel interleaved mode
assuming DDR2 800MHz
•
Supports 256-Mb, 512-Mb, and 1-Gb technologies for x8 and x16 devices
•
Supports four banks for all DDR2 devices up to 512-Mbit density. Supports eight
banks for 1-Gbit DDR2 devices
•
Using 256 Mb technologies, the smallest memory capacity possible is 128 MB,
assuming Single-Channel Mode. (8 K rows * 512 columns * 1 cell/(row * column)
* 16 b/cell * 4 banks/devices * 4 devices/DIMM-side * 1 DIMM-side/channel * 1
channel * 1 B/8 b * 1 M/1024 K = 128 MB)
•
By using 1 Gb technology in Dual Channel Interleaved Mode, the largest memory
capacity possible is 8 GB. (16 K rows * 1 K columns * 1 cell/(row * column) * 8
b/cell * 8 banks/device * 8 devices/DIMM-side * 4 DIMM-sides/channel * 2
channels * 1 B/8 b * 1 G/1024 M * 1 M/(K*K) = 8 GB)
•
Maximum DRAM address decode space is 8 GB (assuming 36-bit addressing)
•
Supports up to 32 simultaneous open pages per channel (assuming 4 ranks of 8
bank devices)
•
Supports opportunistic refresh scheme
•
Supports Partial Writes to memory using Data Mask (DM) signals
•
Supports page sizes of 4 KB, 8 KB, and 16 KB
•
Supports a burst length of 8 for single-channel and dual-channel interleaved and
asymmetric operating modes
•
Improved flexible memory architecture
Datasheet
Introduction
1.3.3
Direct Media Interface (DMI)
Direct Media Interface (DMI) is the chip-to-chip connection between the GMCH and
ICH8. This high-speed interface integrates advanced priority-based servicing allowing
for concurrent traffic and true isochronous transfer capabilities. Base functionality is
completely software transparent permitting current and legacy software to operate
normally.
To provide for true isochronous transfers and configurable Quality of Service (QoS)
transactions, the ICH8 supports two virtual channels on DMI: VC0 and VC1. These two
channels provide a fixed arbitration scheme where VC1 is always the highest priority.
VC0 is the default conduit of traffic for DMI and is always enabled. VC1 must be
specifically enabled and configured at both ends of the DMI link (i.e., the ICH8 and
GMCH).
1.3.4
•
A chip-to-chip connection interface to Intel ICH8
•
2 GB/s point-to-point DMI to ICH8 (1 GB/s each direction)
•
100 MHz reference clock (shared with PCI Express* Graphics Attach)
•
32-bit downstream addressing
•
APIC and MSI interrupt messaging support. Will send Intel-defined “End Of
Interrupt” broadcast message when initiated by the processor.
•
Message Signaled Interrupt (MSI) messages
•
SMI, SCI and SERR error indication
•
Legacy support for ISA regime protocol (PHOLD/PHOLDA) required for parallel port
DMA, floppy drive, and LPC bus masters
PCI Express* Interface
The GMCH contains one 16-lane (x16) PCI Express port intended for an external PCI
Express graphics card. The PCI Express port is compliant to the PCI Express* Base
Specification revision 1.1. The x16 port operates at a frequency of 2.5 Gb/s on each
lane while employing 8b/10b encoding, and supports a maximum theoretical
bandwidth of 40 Gb/s in each direction.
Datasheet
•
One, 16-lane PCI Express port intended for Graphics Attach, compatible to the PCI
Express* Base Specification revision 1.1.
•
PCI Express frequency of 1.25GHz resulting in 2.5 Gb/s each direction
•
Raw bit-rate on the data pins of 2.5 Gb/s, resulting in a real bandwidth per pair of
250 MB/s given the 8b/10b encoding used to transmit data across this interface
•
Maximum theoretical realized bandwidth on the interface of 4 GB/s in each
direction simultaneously, for an aggregate of 8 GB/s when x16.
•
PCI Express* Graphics Extended Configuration Space. The first 256 bytes of
configuration space alias directly to the PCI Compatibility configuration space. The
remaining portion of the fixed 4-KB block of memory-mapped space above that
(starting at 100h) is known as extended configuration space.
•
PCI Express Enhanced Addressing Mechanism. Accessing the device configuration
space in a flat memory mapped fashion.
25
Introduction
1.3.5
•
Automatic discovery, negotiation, and training of link out of reset
•
Supports traditional PCI style traffic (asynchronous snooped, PCI ordering)
•
Supports traditional AGP style traffic (asynchronous non-snooped, PCI Expressrelaxed ordering)
•
Hierarchical PCI-compliant configuration mechanism for downstream devices (i.e.,
normal PCI 2.3 Configuration space as a PCI-to-PCI bridge)
•
Supports “static” lane numbering reversal. This method of lane reversal is
controlled by a Hardware Reset strap, and reverses both the receivers and
transmitters for all lanes (e.g., TX[15]->TX[0], RX[15]->RX[0]). This method is
transparent to all external devices and is different than lane reversal as defined in
the PCI Express Specification. In particular, link initialization is not affected by
static lane reversal.
Graphics Features
The GMCH provides an integrated graphics device (IGD) delivering cost competitive
3D, 2D and video capabilities. The GMCH contains an extensive set of instructions for
3D operations, 2D operations, motion compensation, overlay, and display control. The
GMCH’s video engines support video conferencing and other video applications. The
GMCH uses a UMA configuration with up to 256MB of DVMT for graphics memory. The
GMCH also has the capability to support external graphics accelerators via the PCI
Express Graphics (PEG) port but cannot work concurrently with the integrated
graphics device. High bandwidth access to data is provided through the system
memory port.
1.3.6
SDVO and Analog Display Features
The GMCH provides interfaces to a progressive scan analog monitor and two SDVO
ports. For the GMCH, the SDVO ports are multiplexed with PCI Express x16 graphics
port signals. The GMCH supports two multiplexed SDVO ports that each drive pixel
clocks up to 270 MHz. The SDVO ports can each support a single-channel SDVO
device. If both ports are active in single-channel mode, they can have different display
timing and data.
The digital display channels are capable of driving a variety of SDVO devices (e.g.,
TMDS, TV-Out). Note that SDVO only works with the Integrated Graphics Device
(IGD). The GMCH is capable of driving an Advanced Digital Display (ADD2) card or
Media Expansion Card. The Media Expansion Card adds video-in capabilities. The
GMCH is compliant with DVI Specification 1.0. When combined with a DVI compliant
external device and connector, the GMCH has a high-speed interface to a digital
display (e.g., flat panel or digital CRT).
The GMCH is compliant with HDMI specification 1.1. When combined with a HDMI
compliant external device and connector, the external HDMI device can support
standard, enhanced, or high-definition video, plus multi-channel digital audio on a
single cable.
26
Datasheet
Introduction
Capabilities of the SDVO and Analog Display interfaces include:
•
⎯
⎯
⎯
⎯
⎯
⎯
⎯
SDVO Support
SDVO ports in either single modes supported
3x3 Built In full panel scalar
180 degree Hardware screen rotation
Multiplexed Digital Display Channels (Supported with ADD2/MEC)
Two channels multiplexed with PCI Express* Graphics port
270 MHz dot clock on each 12-bit interface
Supports flat panels up to 2048 x 1536 @ 60 Hz or digital CRT/HDTV at
1920 x1080 @ 85 Hz
⎯
Supports Hot-Plug and Display
⎯
Supports TMDS transmitters or TV-out encoders
⎯
ADD2/Media Expansion card utilizes PCI Express Graphics x16 connector
1.3.7
Datasheet
•
⎯
⎯
⎯
⎯
Analog Display Support
400 MHz Integrated 24-bit RAMDAC
Up to 2048x1536 @ 75 Hz refresh
Hardware Color Cursor Support
DDC2B Compliant Interface
•
Dual Independent Display options with digital display
GMCH Clocking
•
Differential Host clock of 200/266/333 MHz (HCLKP/HCLKN). These frequencies
Support transfer rates of 800/1066/1333 MT/s. The Host PLL generates 2x, 4x,
and 8x versions of the host clock for internal optimizations.
•
Chipset core clock synchronized to host clock
•
Internal and External Memory clocks of 266, 333 and 400 MHz generated from
one of two GMCH PLLs that use the Host clock as a reference. Includes 2x and 4x
for internal optimizations.
•
The PCI Express* PLL of 100 MHz Serial Reference Clock (GCLKP/GCLKN)
generates the PCI Express core clock of 250 MHz
•
Display timings are generated from display PLLs that use a 96 MHz differential
non-spread spectrum clock as a reference. Display PLLs can also use the
SDVO_TVCLKIN[+/-] from an SDVO device as a reference.
•
All of the above clocks are capable of tolerating Spread Spectrum clocking as
defined in the Clock Generator specification.
•
Host, Memory, and PCI Express Graphics PLLs and all associated internal clocks
are disabled until PWROK is asserted.
27
Introduction
1.3.8
Power Management
GMCH Power Management support includes:
1.3.9
•
PC99 suspend to DRAM support (“STR”, mapped to ACPI state S3)
•
SMRAM space remapping to A0000h (128 KB)
•
Supports extended SMRAM space above 256 MB, additional 1-MB TSEG from the
Base of graphics stolen memory (BSM) when enabled, and cacheable (cacheability
controlled by processor)
•
ACPI Rev 1.0 compatible power management
•
Supports processor states: C0 and C1
•
Supports System states: S0, S1D, S3, S4, and S5
•
Supports processor Thermal Management 2 (TM2)
Thermal Sensor
GMCH Thermal Sensor support includes:
•
Catastrophic Trip Point support for emergency clock gating for the GMCH at
115 °C
•
Hot Trip Point support for SMI generation between 85 °C and 105 °C
§
28
Datasheet
Introduction
Datasheet
29
Signal Description
2
Signal Description
This section provides a detailed description of GMCH signals. The signals are arranged
in functional groups according to their associated interface.
The following notations are used to describe the signal type.
PCI
Express*
PCI-Express interface signals. These signals are compatible with PCI Express
1.1 Signaling Environment AC Specifications and are AC coupled. The buffers
are not 3.3 V tolerant. Differential voltage spec = (|D+ - D-|) * 2 = 1.2 Vmax.
Single-ended maximum = 1.25 V. Single-ended minimum = 0 V.
DMI
Direct Media Interface signals. These signals are compatible with PCI Express
1.0 Signaling Environment AC Specifications, but are DC coupled. The buffers
are not 3.3 V tolerant. Differential voltage spec = (|D+ - D-|) * 2 = 1.2 Vmax.
Single-ended maximum = 1.25 V. Single-ended minimum = 0 V.
CMOS
COD
CMOS Open Drain buffers. 3.3 V tolerant.
HCSL
Host Clock Signal Level buffers. Current mode differential pair. Differential
typical swing = (|D+ - D-|) * 2 = 1.4V. Single ended input tolerant from
-0.35 V to 1.2 V. Typical crossing voltage 0.35 V.
HVCMOS
HVIN
High Voltage CMOS buffers. 3.3 V tolerant.
High Voltage CMOS input-only buffers. 3.3 V tolerant.
SSTL-1.8
Stub Series Termination Logic. These are 1.8 V output capable buffers. 1.8 V
tolerant.
A
Analog reference or output. May be used as a threshold voltage or for buffer
compensation.
GTL+
30
CMOS buffers. 1.5 V tolerant.
Gunning Transceiver Logic signaling technology. Implements a voltage level as
defined by VTT of 1.2V.
Datasheet
Signal Description
2.1
Host Interface Signals
Note: Unless otherwise noted, the voltage level for all signals in this interface is tied to the
termination voltage of the Host Bus (VTT).
Signal Name
HADS#
Type
Description
I/O
Address Strobe: The processor bus owner asserts HADS# to
indicate the first of two cycles of a request phase. The GMCH can
assert this signal for snoop cycles and interrupt messages.
GTL+
HBNR#
I/O
GTL+
HBPRI#
O
GTL+
HBREQ0#
I/O
GTL+
HCPURST#
O
GTL+
Block Next Request: Used to block the current request bus
owner from issuing new requests. This signal is used to
dynamically control the processor bus pipeline depth.
Priority Agent Bus Request: The GMCH is the only Priority
Agent on the processor bus. It asserts this signal to obtain the
ownership of the address bus. This signal has priority over
symmetric bus requests and will cause the current symmetric
owner to stop issuing new transactions unless the HLOCK#
signal was asserted.
Bus Request 0: The GMCH pulls the processor’s bus HBREQ0#
signal low during HCPURST#. The processor samples this signal
on the active-to-inactive transition of HCPURST#. The minimum
setup time for this signal is 4 HCLKs. The minimum hold time is
2 clocks and the maximum hold time is 20 HCLKs. HBREQ0#
should be tri-stated after the hold time requirement has been
satisfied.
CPU Reset: The HCPURST# pin is an output from the GMCH.
The GMCH asserts HCPURST# while RSTIN# is asserted and for
approximately 1 ms after RSTIN# is de-asserted. The
HCPURST# allows the processors to begin execution in a known
state.
Note that the Intel® ICH8 must provide processor frequency
select strap set-up and hold times around HCPURST#. This
requires strict synchronization between GMCH HCPURST# deassertion and the Intel® ICH8 driving the straps.
HDBSY#
I/O
GTL+
HDEFER#
O
GTL+
Datasheet
Data Bus Busy: Used by the data bus owner to hold the data
bus for transfers requiring more than one cycle.
Defer: Signals that the GMCH will terminate the transaction
currently being snooped with either a deferred response or with
a retry response.
31
Signal Description
Signal Name
HDINV[3:0]#
Type
Description
I/O
Dynamic Bus Inversion: Driven along with the HD[63:0]#
signals. Indicates if the associated signals are inverted or not.
HDINV[3:0]# are asserted such that the number of data bits
driven electrically low (low voltage) within the corresponding 16
bit group never exceeds 8.
GTL+
HDINV[x]# Data Bits
HA[35:3]#
I/O
GTL+
HADSTB[1:0]#
I/O
GTL+
HD[63:0]#
I/O
GTL+
HDSTBP[3:0]#
I/O
HDSTBN[3:0]#
GTL+
HDINV[3]#
HD[63:48]#
HDINV[2]#
HD[47:32]#
HDINV[1]#
HD[31:16]#
HDINV[0]#
HD[15:0]#
Host Address Bus: HA[35:3]# connect to the processor
address bus. During processor cycles, the HA[35:3]# are inputs.
The GMCH drives HA[35:3]# during snoop cycles on behalf of
DMI and PCI Express* Graphics initiators. HA[35:3]# are
transferred at 2x rate.
Host Address Strobe: The source synchronous strobes used to
transfer HA[35:3]# and HREQ[4:0] at the 2x transfer rate.
Host Data: These signals are connected to the processor data
bus. Data on HD[63:0] is transferred at 4x rate. Note that the
data signals may be inverted on the processor bus, depending
on the HDINV[3:0]# signals.
Differential Host Data Strobes: The differential source
synchronous strobes used to transfer HD[63:0]# and
HDINV[3:0]# at 4x transfer rate.
Named this way because they are not level sensitive. Data is
captured on the falling edge of both strobes. Hence, they are
pseudo-differential, and not true differential.
HHIT#
I/O
GTL+
HHITM#
I/O
GTL+
32
Strobes
Bits
Data
HDSTBP3#,
HDSTBN3#
HDINV3#
HD[63:48]#
HDSTBP2#,
HDSTBN2#
HDINV2#
HD[47:32]#
HDSTBP1#,
HDSTBN1#
HDINV1#
HD[31:16]#
HDSTBP0#,
HDSTBN0#
HDINV0#
HD[15:0]#
Hit: Indicates that a caching agent holds an unmodified version
of the requested line. Also, driven in conjunction with HHITM#
by the target to extend the snoop window.
Hit Modified: Indicates that a caching agent holds a modified
version of the requested line and that this agent assumes
responsibility for providing the line. Also, driven in conjunction
with HHIT# to extend the snoop window.
Datasheet
Signal Description
Signal Name
Type
Description
HLOCK#
I/O
GTL+
Host Lock: All processor bus cycles sampled with the assertion
of HLOCK# and HADS#, until the negation of HLOCK#, must be
atomic, i.e. no DMI or PCI Express* Graphics accesses to DRAM
are allowed when HLOCK# is asserted by the processor.
HREQ[4:0]#
I/O
GTL+
Host Request Command: Defines the attributes of the
request. HREQ[4:0]# are transferred at 2x rate. Asserted by the
requesting agent during both halves of Request Phase. In the
first half, the signals define the transaction type to a level of
detail that is sufficient to begin a snoop request. In the second
half, the signals carry additional information to define the
complete transaction type.
HTRDY#
O
GTL+
Host Target Ready: Indicates that the target of the processor
transaction is able to enter the data transfer phase.
HRS[2:0]#
O
GTL+
Response Signals: These signals indicate the type of response
according to the following table.
Encoding
000
Idle state
001
Retry response
010
Deferred response
011
Reserved(not driven by GMCH)
100
Hard Failure(not driven by GMCH)
101
No data response
110
Implicit Writeback
111
Normal data response
BSEL[2:0]
I
CMOS
Bus Speed Select: At the de-assertion of RSTIN#, the value
sampled on these pins determines the expected frequency of the
bus.
HRCOMP
I/O
CMOS
Host RCOMP: Used to calibrate the Host GTL+ I/O buffers.
I/O
CMOS
Slew Rate Compensation: Compensation for the Host
Interface.
I/O
A
Slew Rate Compensation: Compensation for the Host
Interface for falling edges.
HSCOMP
HSCOMP#
Datasheet
Response Type
This signal is powered by the Host Interface termination rail
(VTT).
HSWING
I
A
Host Voltage Swing: This signal provides the reference voltage
used by FSB RCOMP circuits. HSWING is used for the signals
handled by HRCOMP.
HDVREF
I
A
Host Reference Voltage: Voltage input for the Data signals of
the Host GTL interface.
HACCVREF
I
A
Host Reference Voltage: Voltage input for the Address signals
of the Host GTL interface.
33
Signal Description
2.2
DDR2 DRAM Channel A Interface
Signal Name
Type
Description
SCLK_A[5:0]
O
SSTL-1.8
SDRAM Differential Clock: (3 per DIMM), SCLK_A and its
complement, SCLK_A# make a differential clock pair output.
The crossing of the positive edge of SCLK_A and the
negative edge of its complement SCLK_A# are used to
sample the command and control signals on the SDRAM.
SCLK_A[5:0]#
O
SSTL-1.8
SDRAM Complementary Differential Clock: (3 per
DIMM) These are the complementary differential DDR2
Clock signals.
SCS_A[3:0]#
O
SSTL-1.8
Chip Select: (1 per Rank) These signals select particular
SDRAM components during the active state. There is one
Chip Select for each SDRAM rank.
SMA_A[14:0]
O
SSTL-1.8
Memory Address: These signals are used to provide the
multiplexed row and column address to the SDRAM.
SBS_A[2:0]
O
SSTL-1.8
Bank Select: These signals define which banks are selected
within each SDRAM rank.
DDR2: 1-Gb technology uses 8 banks.
34
SRAS_A#
O
SSTL-1.8
Row Address Strobe: Used with SCAS_A# and SWE_A#
(along with SCS_A#) to define the SDRAM commands.
SCAS_A#
O
SSTL-1.8
Column Address Strobe: Used with SRAS_A# and
SWE_A# (along with SCS_A#) to define the SDRAM
commands.
SWE_A#
O
SSTL-1.8
Write Enable: Used with SCAS_A# and SRAS_A# (along
with SCS_A#) to define the SDRAM commands.
SDQ_A[63:0]
I/O
SSTL-1.8
Data Lines: SDQ_A signals interface to the SDRAM data
bus.
SDM_A[7:0]
O
SSTL-1.8
Data Mask: When activated during writes, the
corresponding data groups in the SDRAM are masked. There
is one SDM_A bit for every data byte lane.
SDQS_A[7:0]
I/O
SSTL-1.8
Data Strobes: For DDR2, SDQS_A, and its complement
SDQS_A# make up a differential strobe pair. The data is
captured at the crossing point of SDQS_A and its
complement SDQS_A# during read and write transactions.
SDQS_A[7:0]#
I/O
SSTL-1.8
Data Strobe Complements: These are the complementary
DDR2 strobe signals.
SCKE_A[3:0]
O
SSTL-1.8
Clock Enable: (1 per Rank) SCKE_A is used to initialize the
SDRAMs during power-up, to power-down SDRAM ranks,
and to place all SDRAM ranks into and out of self-refresh
during Suspend-to-RAM.
SODT_A[3:0]
O
SSTL-1.8
On Die Termination: Active On-die Termination Control
signals for DDR2 devices.
Datasheet
Signal Description
2.3
DDR2 DRAM Channel B Interface
Signal Name
Type
Description
SCLK_B[5:0]
O
SSTL-1.8
SDRAM Differential Clock: (3 per DIMM) SCLK_B and its
complement, SCLK_B#, make a differential clock pair output.
The crossing of the positive edge of SCLK_B and the negative
edge of its complement SCLK_B# are used to sample the
command and control signals on the SDRAM.
SCLK_B[5:0]#
O
SSTL-1.8
SDRAM Complementary Differential Clock: (3 per DIMM)
These are the complementary differential DDR2 Clock signals.
SCS_B[3:0]#
O
SSTL-1.8
Chip Select: (1 per Rank) These signals select particular
SDRAM components during the active state. There is one Chip
Select for each SDRAM rank
SMA_B[14:0]
O
SSTL-1.8
Memory Address: These signals are used to provide the
multiplexed row and column address to the SDRAM.
SBS_B[2:0]
O
SSTL-1.8
Bank Select: These signals define which banks are selected
within each SDRAM rank
DDR2: 1-Gb technology uses 8 banks.
Datasheet
SRAS_B#
O
SSTL-1.8
Row Address Strobe: Used with SCAS_B# and SWE_B#
(along with SCS_B#) to define the SDRAM commands
SCAS_B#
O
SSTL-1.8
Column Address Strobe: Used with SRAS_B# and SWE_B#
(along with SCS_B#) to define the SDRAM commands.
SWE_B#
O
SSTL-1.8
Write Enable: Used with SCAS_B# and SRAS_B# (along
with SCS_B#) to define the SDRAM commands.
SDQ_B[63:0]
I/O
SSTL-1.8
Data Lines: SDQ_B signals interface to the SDRAM data bus.
SDM_B[7:0]
O
SSTL-1.8
Data Mask: When activated during writes, the corresponding
data groups in the SDRAM are masked. There is one SBDM for
every data byte lane.
SDQS_B[7:0]
I/O
SSTL-1.8
Data Strobes: For DDR2, SDQS_B, and its complement
,SDQS_B#, make up a differential strobe pair. The data is
captured at the crossing point of SDQS_B and its complement
SDQS_B# during read and write transactions.
SDQS_B[7:0]#
I/O
SSTL-1.8
Data Strobe Complements: These are the complementary
DDR2 strobe signals.
SCKE_B[3:0]
O
SSTL-1.8
Clock Enable: (1 per Rank) SCKE_B is used to initialize the
SDRAMs during power-up, to power-down SDRAM ranks, and
to place all SDRAM ranks into and out of self-refresh during
Suspend-to-RAM.
SODT_B[3:0]
O
SSTL-1.8
On Die Termination: Active On-die Termination Control
signals for DDR2 devices.
35
Signal Description
2.4
DDR2 DRAM Reference and Compensation
Signal Name
SRCOMP[3:0]
Type
Description
I
System Memory RCOMP
A
SVREF
I
SDRAM Reference Voltage: Reference voltage input for DQ,
DQS, and DQS# input signals.
A
SMRCOMPVOL
I
System Memory RCOMP reference
A
SMRCOMPVOH
I
System Memory RCOMP reference
A
2.5
PCI Express* Interface Signals
Signal Name
Type
EXP_RXN[15:0]
I
EXP_RXP[15:0]
PCI
EXPRESS
EXP_TXN[15:0]
O
EXP_TXP[15:0]
PCI
EXPRESS
EXP_COMPO
I
Description
PCI Express Receive Differential Pair (RX)
PCI Express Graphics Transmit Differential Pair (TX)
PCI Express Graphics Output Current Compensation
A
EXP_COMPI
I
PCI Express Graphics Input Current Compensation
A
2.6
Analog Display Signals
Signal Name
RED
Type
O
A
RED#
O
A
36
Description
RED Analog Video Output: This signal is a CRT Analog video
output from the internal color palette DAC. The DAC is designed
for a 37.5 ohm routing impedance, but the terminating resistor
to ground will be 75 ohms (e.g., 75 ohm resistor on the board,
in parallel with a 75 ohm CRT load).
RED# Analog Output: This signal is an analog video output
from the internal color palette DAC. It should be shorted to the
ground plane.
Datasheet
Signal Description
Signal Name
GREEN
Type
Description
O
GREEN Analog Video Output: This signal is a CRT Analog
video output from the internal color palette DAC. The DAC is
designed for a 37.5 ohm routing impedance, but the terminating
resistor to ground will be 75 ohms (e.g., 75 ohm resistor on the
board, in parallel with a 75 ohm CRT load).
A
GREEN#
O
GREEN# Analog Output: This signal is an analog video output
from the internal color palette DAC. It should be shorted to the
ground plane.
A
BLUE
O
BLUE Analog Video Output: This signal is a CRT Analog video
output from the internal color palette DAC. The DAC is designed
for a 37.5 ohm routing impedance, but the terminating resistor
to ground will be 75 ohms (e.g., 75 ohm resistor on the board,
in parallel with a 75 ohm CRT load).
A
BLUE#
O
BLUE# Analog Output: This signal is an analog video output
from the internal color palette DAC. It should be shorted to the
ground plane.
A
REFSET
O
Resistor Set: Set point resistor for the internal color palette
DAC. A 255 ohm 1% resistor is required between REFSET and
motherboard ground.
A
2.7
HSYNC
O
3.3V
CMOS
CRT Horizontal Synchronization: This signal is used as the
horizontal sync (polarity is programmable) or “sync interval”, 3.3
V output
VSYNC
O
3.3V
CMOS
CRT Vertical Synchronization: This signal is used as the
vertical sync (polarity is programmable) 3.3V output.
DDC_CLK
I/O
3.3V
CMOS
Monitor Control Clock
DDC_DATA
I/O
3.3V
CMOS
Monitor Control Data
Clocks, Reset, and Miscellaneous
Signal Name
Datasheet
Type
HCLKP
I
HCLKN
HCSL
GCLKP
I
GCLKN
HCSL
DREFCLKN
I
DREFCLKP
HCSL
Description
Differential Host Clock In: These pins receive a differential
host clock from the external clock synthesizer. This clock is
used by all of the GMCH logic that is in the Host clock domain.
Memory domain clocks are also derived from this source.
Differential PCI Express* Graphics Clock In: These pins
receive a differential 100 MHz Serial Reference clock from the
external clock synthesizer. This clock is used to generate the
clocks necessary for the support of PCI Express.
Display PLL Differential Clock In
37
Signal Description
Signal Name
RSTIN#
Type
Description
I
Reset In: When asserted, this signal will asynchronously reset
the GMCH logic. This signal is connected to the PCIRST#
output of the Intel® ICH8. All PCI Express Graphics Attach
output signals will also tri-state compliant to PCI Express*
Specification Rev 1.1.
HVIN
This input should have a Schmitt trigger to avoid spurious
resets.
This signal is required to be 3.3V tolerant.
PWROK
I
HVIN
EXP_EN
Power OK: When asserted, PWROK is an indication to the
GMCH that core power has been stable for at least 10us.
I
PCI Express* SDVO Concurrent Select
CMOS
0 = Only SDVO or PCI Express Operational
1 = SDVO and PCI Express operating simultaneously via PCI
Express* Graphics port
EXP_SLR
I
CMOS
PCI Express* Static Lane Reversal/Form Factor
Selection: GMCH’s PCI Express lane numbers are reversed to
differentiate BTX or ATX form factors.
0 = GMCH’s PCI Express lane numbers are reversed (BTX
Platforms)
1 = Normal operation (ATX Platforms)
ICH_SYNC#
O
ICH Sync: See Design Guide for Implementation.
HVCMO
S
TEST[2:0]
2.8
In Circuit Test: These pins should be connected to test points
on the mother board. They are internally shorted to the
package ground and can be used to determine if the corner
balls on the GMCH are correctly soldered down to the
motherboard. These pins should NOT connect to ground on the
motherboard. If TEST[2:0] are not going to be used they
should be left as no connects
Direct Media Interface (DMI)
Signal Name
38
I/O
Type
DMI_RXP[3:0]
I
DMI_RXN[3:0]
DMI
DMI_TXP[3:0]
O
DMI_TXN[3:0]
DMI
Description
Direct Media Interface: Receive differential pair (Rx)
Direct Media Interface: Transmit differential pair (Tx)
Datasheet
Signal Description
2.9
Controller Link (CL)
Signal Name
CL_DATA
Type
I/O
Description
Controller Link DATA
CMOS
CL_CLK
I/O
Controller Link Clock
CMOS
CL_VREF
I
Controller Link VREF
CMOS
CL_RST#
I
Controller Link RESET
CMOS
CL_PWROK
I
Controller Link Power OK
CMOS
2.10
Intel® Serial DVO (SDVO) Interface
All but the last two of the pins in this section are multiplexed with the lower 8 lanes of
the PCI Express* interface.
Signal Name
SDVOB_CLKN
Type
O
Description
Serial Digital Video Channel B Clock Complement
PCI
Express*
SDVOB_CLKP
O
Serial Digital Video Channel B Clock
PCI Express
SDVOB_RED#
O
Serial Digital Video Channel C Red Complement
PCI Express
SDVOB_RED
O
Serial Digital Video Channel C Red
PCI Express
SDVOB_GREEN#
O
Serial Digital Video Channel B Green Complement
PCI Express
SDVOB_GREEN
O
Serial Digital Video Channel B Green
PCI Express
SDVOB_BLUE#
O
Serial Digital Video Channel B Blue Complement
PCI Express
SDVOB_BLUE
O
Serial Digital Video Channel B Blue
PCI Express
Datasheet
39
Signal Description
Signal Name
SDVOC_RED#
Type
O
Description
Serial Digital Video Channel C Red Complement
PCI Express
SDVOC_RED
O
PCI Express
SDVOC_GREEN#
O
Serial Digital Video Channel C Red Channel B
Alpha
Serial Digital Video Channel C Green Complement
PCI Express
SDVOC_GREEN
O
Serial Digital Video Channel C Green
PCI Express
SDVOC_BLUE#
O
Serial Digital Video Channel C Blue Complement
PCI Express
SDVOC_BLUE
O
Serial Digital Video Channel C Blue
PCI Express
SDVOC_CLKN
O
Serial Digital Video Channel C Clock Complement
PCI Express
SDVOC_CLKP
O
Serial Digital Video Channel C Clock
PCI Express
40
SDVO_TVCLKIN#
I
PCI Express
Serial Digital Video TVOUT Synchronization Clock
Complement
SDVO_TVCLKIN
I
PCI Express
Serial Digital Video TVOUT Synchronization Clock
SDVOB_INT#
I
PCI Express
Serial Digital Video Input Interrupt Complement
SDVOB_INT
I
PCI Express
Serial Digital Video Input Interrupt
SDVOC_INT#
I
PCI Express
Serial Digital Video Input Interrupt Complement
SDVOC_INT
I
PCI Express
Serial Digital Video Input Interrupt
SDVO_FLDSTALL#
I
PCI Express
Serial Digital Video Field Stall Complement.
SDVO_FLDSTALL
I
PCI Express
Serial Digital Video Field Stall
SDVO_CTRLCLK
I/O
COD
Serial Digital Video Device Control Clock
SDVO_CTRLDATA
I/O
COD
Serial Digital Video Device Control Data
Datasheet
Signal Description
2.10.1
SDVO/PCI Express* Signal Mapping
The following table shows the mapping of SDVO signals to the PCI Express* lanes in
the various possible configurations as determined by the strapping configuration. Note
that slot-reversed configurations do not apply to the Integrated-graphics only
variants.
Configuration-wise Mapping
SDVO Signal
SDVO Only –
Normal
SDVO Only –
Reversed
Concurrent
SDVO and PCI
Express* –
Normal
Concurrent
SDVO and PCI
Express* –
Reversed
SDVOB_RED#
EXP_TXN0
EXP_TXN15
EXP_TXN15
EXP_TXN0
SDVOB_RED
EXP_TXP0
EXP_TXP15
EXP_TXP15
EXP_TXP0
SDVOB_GREEN#
EXP_TXN1
EXP_TXN14
EXP_TXN14
EXP_TXN1
SDVOB_GREEN
EXP_TXP1
EXP_TXP14
EXP_TXP14
EXP_TXP1
SDVOB_BLUE#
EXP_TXN2
EXP_TXN13
EXP_TXN13
EXP_TXN2
SDVOB_BLUE
EXP_TXP2
EXP_TXP13
EXP_TXP13
EXP_TXP2
SDVOB_CLKN
EXP_TXN3
EXP_TXN12
EXP_TXN12
EXP_TXN3
SDVOB_CLKP
EXP_TXP3
EXP_TXP12
EXP_TXP12
EXP_TXP3
SDVOC_RED#
EXP_TXN4
EXP_TXN11
EXP_TXN11
EXP_TXN4
SDVOC_RED
EXP_TXP4
EXP_TXP11
EXP_TXP11
EXP_TXP4
SDVOC_GREEN#
EXP_TXN5
EXP_TXN10
EXP_TXN10
EXP_TXN5
SDVOC_GREEN
EXP_TXP5
EXP_TXP10
EXP_TXP10
EXP_TXP5
SDVOC_BLUE#
EXP_TXN6
EXP_TXN9
EXP_TXN9
EXP_TXN6
SDVOC_BLUE
EXP_TXP6
EXP_TXP9
EXP_TXP9
EXP_TXP6
SDVOC_CLKN
EXP_TXN7
EXP_TXN8
EXP_TXN8
EXP_TXN7
SDVOC_CLKP
EXP_TXP7
EXP_TXP8
EXP_TXP8
EXP_TXP7
SDVO_TVCLKIN#
EXP_RXN0
EXP_RXN15
EXP_RXN15
EXP_RXN0
SDVO_TVCLKIN
EXP_RXP0
EXP_RXP15
EXP_RXP15
EXP_RXP0
SDVOB_INT#
EXP_RXN1
EXP_RXN14
EXP_RXN14
EXP_RXN1
SDVOB_INT
EXP_RXP1
EXP_RXP14
EXP_RXP14
EXP_RXP1
SDVOC_INT#
EXP_RXN5
EXP_RXN10
EXP_RXN10
EXP_RXN5
SDVOC_INT
EXP_RXP5
EXP_RXP10
EXP_RXP10
EXP_RXP5
SDVO_FLDSTALL#
EXP_RXN2
EXP_RXN13
EXP_RXN13
EXP_RXN2
SDVO_FLDSTALL
EXP_RXP2
EXP_RXP13
EXP_RXP13
EXP_RXP2
Datasheet
41
Signal Description
2.11
Power, Ground
Name
Voltage
Description
VCC
1.25 V
VTT
1.05 V/1.2 V
Processor System Bus Power
1.25 V
PCI Express* and DMI Power
VCC_EXP
Core Power
VCCSM
1.8 V
System Memory Power
VCC_SMCLK
1.8V
System Clock Memory Power
VCC3_3
3.3 V
3.3 V CMOS Power
VCCA_EXPPLL
1.25 V
PCI Express PLL Analog Power
VCCA_DPLLA
1.25 V
Display PLL A Analog Power
VCCA_DPLLB
1.25 V
Display PLL B Analog Power
VCCA_HPLL
1.25 V
Host PLL Analog Power
VCCA_MPLL
1.25 V
System Memory PLL Analog Power
VCCA_DAC
3.3 V
Display DAC Analog Power
VCCA_EXP
3.3 V
PCI Express Analog Power
VCCDQ_CRT
1.5/1.8 V
Display Digital Quiet Supply Power
VCCD_CRT
1.5/1.8 V
Display Digital Supply Power
VCC_CL
1.25 V
Controller Link Aux Power
VCC_CL_PLL
1.25V
Controller Link PLL Analog Power
VSS
0V
Ground
§
42
Datasheet
Signal Description
Datasheet
43
System Address Map
3
System Address Map
The 82G35 GMCH supports 64GB or 4 GB of addressable memory space and 64 KB+3
of addressable I/O space. There is a programmable memory address space under the
1 MB region which is divided into regions which can be individually controlled with
programmable attributes such as Disable, Read/Write, Write Only, or Read Only.
Attribute programming is described in the Register Description section. This section
focuses on how the memory space is partitioned and what the separate memory
regions are used for. I/O address space has simpler mapping and is explained near
the end of this section.
The HREQ[4:3] FSB pins are decoded to determine whether the access is 32 bit or 36
bit.
The G35 GMCH supports a maximum of 8GB of DRAM, no DRAM memory will be
accessible above 8 GB. DRAM capacity is limited by the number of address pins
available. There is no hardware lock to stop someone from inserting more memory
than is addressable.
In the following sections, it is assumed that all of the compatibility memory ranges
reside on the DMI Interface. The exception to this rule is VGA ranges, which may be
mapped to PCI Express*, DMI, or to the internal graphics device (IGD). In the
absence of more specific references, cycle descriptions referencing PCI should be
interpreted as the DMI Interface/PCI, while cycle descriptions referencing PCI Express
or IGD are related to the PCI Express bus or the internal graphics device respectively.
The reclaim base/reclaim limit registers remap logical accesses bound for addresses
above 4G onto physical addresses that fall within DRAM.
The Address Map includes a number of programmable ranges:
•
⎯
⎯
⎯
⎯
⎯
•
⎯
⎯
⎯
44
Device 0
PXPEPBAR – Egress port registers. Necessary for setting up VC1 as an
isochronous channel using time based weighted round robin arbitration. (4 KB
window)
MCHBAR – Memory mapped range for internal GMCH registers. For example,
memory buffer register controls. (16 KB window)
PCIEXBAR – Flat memory-mapped address spaced to access device
configuration registers. This mechanism can be used to access PCI configuration
space (0-FFh) and Extended configuration space (100h–FFFh) for PCI Express
devices.
DMIBAR –This window is used to access registers associated with the
GMCH/ICH Serial Interconnect (DMI) register memory range. (4 KB window)
GGC – GMCH graphics control register. Used to select the amount of main
memory that is pre-allocated to support the internal graphics device in VGA (nonlinear) and Native (linear) modes. (0–64 MB options).
Device 1
MBASE1/MLIMIT1 – PCI Express port non-prefetchable memory access
window.
PMUBASE1/PMULIMIT1 – PCI Express port prefetchable memory access
window.
IOBASE1/IOLIMIT1 – PCI Express port IO access window.
Datasheet
System Address Map
•
⎯
⎯
⎯
⎯
Device 2, Function 0
MMADR – IGD registers and internal graphics instruction port. (512 KB
window)
IOBAR – IO access window for internal graphics. Though this window
address/data register pair, using I/O semantics, the IGD and internal graphics
instruction port registers can be accessed. Note, this allows accessing the same
registers as MMADR. In addition, the IOBAR can be used to issue writes to the
GTTADR table.
GMADR – Internal graphics translation window (128 MB, 256 MB or 512 MB
window).
GTTADR – Internal graphics translation table location. (128 KB, 256 KB or
512 KB window).
•
⎯
Device 2, Function 1
MMADR – Function 1 IGD registers and internal graphics instruction port.
(512 KB window)
•
⎯
Device 3, Function 0:
MEHECIBAR – Function 0 HECI memory mapped registers (16B window)
The rules for the above programmable ranges are:
Datasheet
1.
ALL of these ranges MUST be unique and NON-OVERLAPPING. It is the BIOS or
system designer’s responsibility to limit memory population so that adequate PCI,
PCI Express , High BIOS, PCI Express Memory Mapped space, and APIC memory
space can be allocated.
2.
In the case of overlapping ranges with memory, the memory decode will be given
priority.
3.
There are NO Hardware Interlocks to prevent problems in the case of overlapping
ranges.
4.
Accesses to overlapped ranges may produce indeterminate results.
5.
The only peer-to-peer cycles allowed below the top of Low Usable memory
(register TOLUD) are DMI Interface to PCI Express VGA range writes. Note that
peer to peer cycles to the Internal Graphics VGA range are not supported.
45
System Address Map
Figure 3-1 represents system memory address map in a simplified form.
Figure 3-1. System Address Ranges
Host/System
View
Physical Memory
(DRAM Controller
View)
64 GB
Device
3
Device
1
Bars
PCI Memory
Address
Range
(subtractively
decoded to
DMI
Device
0
Bars
Independently Programmable
Non-Overlapping Windows
TOUUD Base
Reclaim Limit =
Reclaim Base +X
(64 MB Aligned)
TOM
Main Memory
Reclaim
Address
Range
EP Stolen Base
64 MB Aligned
EP-UMA
(1 – 64 MB)
0 – 63 MB
Unusable
Reclaim Base
(64 MB Aligned)
Main Memory
Address
Range
1 MB Aligned
64 MB Aligned
OS Visible
> 4 GB
4 GB
M HBA
Device
3
Device
2
Device
1
Bars
Device 0
GGC (GFX
Stolen
Mem)
Device
0
Bars
TOLUD
Base
(64 MB
Aligned)
Independently Programmable
Non-Overlapping Windows
PCI Memory
Address
Range
(subtractively
decoded to
DMI)
TSEG
Main Memory
Address
Range
X
OS Invisible
Reclaim
64 MB Aligned for
Reclaim
GFX Stolen
(1 – 64 MB)
TSEG
(0 – 8 MB)
1 MB Aligned
1 MB Aligned
OS Visible
< 4 GB
1 MB
0
Legacy
Address
Range
Memap_Sys_Addr_Ranges
3.1
Legacy Address Range
This area is divided into the following address regions:
• 0 - 640 KB – DOS Area
• 640 - 768 KB – Legacy Video Buffer Area
• 768 - 896 KB in 16KB sections (total of 8 sections) – Expansion Area
• 896 - 960 KB in 16KB sections (total of 4 sections) – Extended System BIOS Area
• 960 KB - 1 MB Memory – System BIOS Area
46
Datasheet
System Address Map
Figure 3-2. DOS Legacy Address Range
000F_FFFFh
000F_0000h
000E_FFFFh
000E_0000h
System BIOS (Upper)
64KB
Extended System BIOS (Lower)
64KB (16KBx4)
000D_FFFFh
1MB
960KB
896KB
Expansion Area
128KB (16KBx8)
000C_0000h
768KB
000B_FFFFh
Legacy Video Area
(SMM Memory)
128KB
000A_0000h
640KB
0009_FFFFh
DOS Area
0000_0000h
Datasheet
47
System Address Map
3.1.1
DOS Range (0h – 9_FFFFh)
The DOS area is 640 KB (0000_0000h – 0009_FFFFh) in size and is always mapped to
the main memory controlled by the GMCH.
3.1.2
Legacy Video Area (A_0000h–B_FFFFh)
The legacy 128 KB VGA memory range, frame buffer, (000A_0000h – 000B_FFFFh)
can be mapped to IGD (Device 2), to PCI Express (Device 1), and/or to the DMI
Interface. The appropriate mapping depends on which devices are enabled and the
programming of the VGA steering bits. Based on the VGA steering bits, priority for
VGA mapping is constant. The GMCH always decodes internally mapped devices first.
Internal to the GMCH, decode precedence is always given to IGD. The GMCH always
positively decodes internally mapped devices, namely the IGD and PCI-Express.
Subsequent decoding of regions mapped to PCI Express or the DMI Interface depends
on the Legacy VGA configuration bits (VGA Enable and MDAP). This region is also the
default for SMM space.
Compatible SMRAM Address Range (A_0000h–B_FFFFh)
When compatible SMM space is enabled, SMM-mode processor accesses to this range
are routed to physical system DRAM at 000A 0000h – 000B FFFFh. Non-SMM-mode
processor accesses to this range are considered to be to the Video Buffer Area as
described above. PCI Express and DMI originated cycles to enabled SMM space are not
allowed and are considered to be to the Video Buffer Area if IGD is not enabled as the
VGA device. PCI Express and DMI initiated cycles are attempted as Peer cycles, and
will master abort on PCI if no external VGA device claims them.
Monochrome Adapter (MDA) Range (B_0000h–B_7FFFh)
Legacy support requires the ability to have a second graphics controller
(monochrome) in the system. Accesses in the standard VGA range are forwarded to
IGD, PCI-Express, or the DMI Interface (depending on configuration bits). Since the
monochrome adapter may be mapped to anyone of these devices, the GMCH must
decode cycles in the MDA range (000B_0000h - 000B_7FFFh) and forward either to
IGD, PCI-Express, or the DMI Interface. This capability is controlled by a VGA steering
bits and the legacy configuration bit (MDAP bit). In addition to the memory range
B0000h to B7FFFh, the GMCH decodes IO cycles at 3B4h, 3B5h, 3B8h, 3B9h, 3BAh
and 3BFh and forwards them to the either IGD, PCI-Express, and/or the DMI
Interface.
3.1.3
Expansion Area (C_0000h–D_FFFFh)
This 128 KB ISA Expansion region (000C_0000h – 000D_FFFFh) is divided into eight
16 KB segments. Each segment can be assigned one of four Read/Write states: readonly, write-only, read/write, or disabled. Typically, these blocks are mapped through
GMCH and are subtractive decoded to ISA space. Memory that is disabled is not
remapped.
Non-snooped accesses from PCI Express or DMI to this region are always sent to
DRAM. This complies with a Colusa DCN.
48
Datasheet
System Address Map
Table 3-1. Expansion Area Memory Segments
Memory Segments
3.1.4
Attributes
Comments
0C0000h - 0C3FFFh
WE
RE
Add-on BIOS
0C4000h - 0C7FFFh
WE
RE
Add-on BIOS
0C8000h - 0CBFFFh
WE
RE
Add-on BIOS
0CC000h - 0CFFFFh
WE
RE
Add-on BIOS
0D0000h - 0D3FFFh
WE
RE
Add-on BIOS
0D4000h - 0D7FFFh
WE
RE
Add-on BIOS
0D8000h - 0DBFFFh
WE
RE
Add-on BIOS
0DC000h - 0DFFFFh
WE
RE
Add-on BIOS
Extended System BIOS Area (E_0000h-E_FFFFh)
This 64 KB area (000E_0000h – 000E_FFFFh) is divided into four 16 KB segments.
Each segment can be assigned independent read and write attributes so it can be
mapped either to main DRAM or to DMI Interface. Typically, this area is used for RAM
or ROM. Memory segments that are disabled are not remapped elsewhere.
Non-snooped accesses from PCI Express or DMI to this region are always sent to
DRAM.
Table 3-2. Extended System BIOS Area Memory Segments
Memory Segments
3.1.5
Attributes
Comments
0E0000h - 0E3FFFh
WE
RE
BIOS Extension
0E4000h - 0E7FFFh
WE
RE
BIOS Extension
0E8000h - 0EBFFFh
WE
RE
BIOS Extension
0EC000h - 0EFFFFh
WE
RE
BIOS Extension
System BIOS Area (F_0000h – F_FFFFh)
This area is a single 64 KB segment (000F_0000h – 000F_FFFFh). This segment can
be assigned read and write attributes. It is by default (after reset) Read/Write
disabled and cycles are forwarded to DMI Interface. By manipulating the Read/Write
attributes, the GMCH can “shadow” BIOS into the main DRAM. When disabled, this
segment is not remapped.
Non-snooped accesses from PCI Express or DMI to this region are always sent to
DRAM.
Table 3-3. System BIOS Area Memory Segments
Memory Segments
0F0000h – 0FFFFFh
Datasheet
Attributes
WE
RE
Comments
BIOS Area
49
System Address Map
3.1.6
PAM Memory Area Details
The 13 sections from 768 KB to 1 MB comprise what is also known as the PAM
Memory Area.
The GMCH does not handle IWB (Implicit Write-Back) cycles targeting DMI. Since all
memory residing on DMI should be set as non-cacheable, there will normally not be
IWB cycles targeting DMI.
However, DMI becomes the default target for processor and DMI originated accesses
to disabled segments of the PAM region. If the MTRRs covering the PAM regions are
set to WB or RD it is possible to get IWB cycles targeting DMI. This may occur for
processor originated cycles (in a DP system) and for DMI originated cycles to disabled
PAM regions.
For example, say that a particular PAM region is set for “Read Disabled” and the MTRR
associated with this region is set to WB. A DMI master generates a memory read
targeting the PAM region. A snoop is generated on the FSB and the result is an IWB.
Since the PAM region is “Read Disabled” the default target for the Memory Read
becomes DMI. The IWB associated with this cycle will cause the GMCH to hang.
3.1.7
Legacy Interrupt Routing
Table 3-4. Specifics of Legacy Interrupt Routing
Interrupt Source
Internal Graphics D2 F0
PEG (External Graphics Device)
3.2
Default Interrupt A/B/C/D
A
Function of what is defined in Interrupt Pin
register of the PEG device
PEG (Internally generated
Interrupt) D1 F0
A
ME (IDER) D3 F2
B
ME (HECI) D3 F0
C
ME (KT) D3 F3
A
Main Memory Address Range (1MB – TOLUD)
This address range extends from 1 MB to the top of Low Usable physical memory that
is permitted to be accessible by the GMCH (as programmed in the TOLUD register). All
accesses to addresses within this range will be forwarded by the GMCH to the DRAM
unless it falls into the optional TSEG, optional ISA Hole, or optional IGD stolen VGA
memory.
50
Datasheet
System Address Map
Figure 3-3. Main Memory Address Range
FFFF_FFFFh
FLASH
4GB Max
APIC
LT
Contains:
Dev 0, 1, 2, 3, 7
BARS
& ICH/PCI ranges
PCI Memory Range
TOLUD
IGD (1-64MB, optional)
TSEG (1MB/2MB/8MB, optional)
Main Memory
0100_0000h
16MB
ISA Hole (optional)
00F0_0000h
15MB
Main Memory
0010_0000h
1MB
DOS Compatibility Memory
0h
3.2.1
0MB
ISA Hole (15MB-16MB)
A hole can be created at 15 MB–16 MB as controlled by the fixed hole enable in Device
0 space. Accesses within this hole are forwarded to the DMI Interface. The range of
physical DRAM memory disabled by opening the hole is not remapped to the top of the
memory – that physical DRAM space is not accessible. This 15 MB – 16 MB hole is an
optionally enabled ISA hole.
Video accelerators originally used this hole. It is also used by validation and customer
SV teams for some of their test cards. That is why it is being supported. There is no
inherent BIOS request for the 15 MB – 16 MB window.
3.2.2
TSEG
TSEG is optionally 1 MB, 2 MB, or 8 MB in size. TSEG is below IGD stolen memory,
which is at the top of Low Usable physical memory (TOLUD). SMM-mode processor
accesses to enabled TSEG access the physical DRAM at the same address. Nonprocessor originated accesses are not allowed to SMM space. PCI-Express, DMI, and
Internal Graphics originated cycle to enabled SMM space are handled as invalid cycle
type with reads and writes to location 0 and byte enables turned off for writes. When
Datasheet
51
System Address Map
the extended SMRAM space is enabled, processor accesses to the TSEG range without
SMM attribute or without WB attribute are also forwarded to memory as invalid
accesses (see Table 3-5). Non-SMM-mode Write Back cycles that target TSEG space
are completed to DRAM for cache coherency. When SMM is enabled the maximum
amount of memory available to the system is equal to the amount of physical DRAM
minus the value in the TSEG register which is fixed at 1 MB, 2 MB or 8 MB.
3.2.3
Pre-allocated Memory
Voids of physical addresses that are not accessible as general system memory and
reside within system memory address range (< TOLUD) are created for SMM-mode
and legacy VGA graphics compatibility. It is the responsibility of BIOS to properly
initialize these regions. The following table details the location and attributes of the
regions. Enabling/Disabling these ranges are described in the GMCH Control Register
Device 0 (GCC).
Table 3-5. Pre-allocated Memory Example for 64 MB DRAM, 1-MB VGA and 1-MB TSEG
Memory Segments
3.3
Attributes
Comments
0000_0000h –
03DF_FFFFh
R/W
Available System Memory 62 MB
03E0_0000h –
03EF_FFFFh
SMM Mode Only processor Reads
TSEG Address Range & Pre-allocated
Memory
03F0_0000h –
03FF_FFFFh
R/W
Pre-allocated Graphics VGA memory.
1 MB (or 4/8/16/32/64 MB) when IGD is
enabled.
PCI Memory Address Range (TOLUD – 4GB)
This address range, from the top of low usable DRAM (TOLUD) to 4 GB is normally
mapped to the DMI Interface.
With PCI Express* port, there are two exceptions to this rule.
•
Addresses decoded to the PCI Express Memory Window defined by the MBASE1,
MLIMIT1, registers are mapped to PCI Express .
Note: AGP Aperture no longer exists with PCI Express.
In a Manageability Engine configuration, there are exceptions to this rule.
•
Addresses decoded to the ME Keyboard and Text MMIO range (EPKTBAR)
There are other MMIO Bars that may be mapped to this range or to the range above
TOUUD.
There are sub-ranges within the PCI Memory address range defined as APIC
Configuration Space, FSB Interrupt Space, and High BIOS Address Range. The
exceptions listed above for internal graphics and the PCI Express ports MUST NOT
overlap with these ranges.
52
Datasheet
System Address Map
Figure 3-4. PCI Memory Address Range
FFFF_FFFFh
High BIOS
4 GB
4 GB – 2 MB
FFE0_0000h
DMI Interface
(subtractive decode)
FEF0_0000h
4 GB – 17 MB
FSB Interrupts
FEE0_0000h
FED0_0000h
FEC8_0000h
DMI Interface
(subtractive decode)
Local (CPU) APIC
I/O APIC
FEC0_0000h
4 GB – 18 MB
4 GB – 19 MB
Optional HSEG
FEDA_0000h to
FEDB_FFFFh
4 GB – 20 MB
DMI Interface
(subtractive decode)
F000_0000h
4 GB – 256 MB
PCI Express Configuration
Space
E000_0000h
Possible address
range/size (not
ensured)
4 GB – 512 MB
DMI Interface
(subtractive decode)
BARs, Internal
Graphics
ranges, PCI
Express Port, .
TOLUD
Datasheet
53
System Address Map
3.3.1
APIC Configuration Space (FEC0_0000h–FECF_FFFFh)
This range is reserved for APIC configuration space. The I/O APIC(s) usually reside in
the ICH portion of the chipset, but may also exist as stand-alone components like
PXH.
The IOAPIC spaces are used to communicate with IOAPIC interrupt controllers that
may be populated in the system. Since it is difficult to relocate an interrupt controller
using plug-and-play software, fixed address decode regions have been allocated for
them. Processor accesses to the default IOAPIC region (FEC0_0000h to FEC7_FFFFh)
are always forwarded to DMI.
The GMCH optionally supports additional I/O APICs behind the PCI Express “Graphics”
port. When enabled via the PCI Express Configuration register (Device 1 Offset 200h),
the PCI Express port will positively decode a subset of the APIC configuration space –
specifically FEC8_0000h thru FECF_FFFFh. Memory request to this range would then
be forwarded to the PCI Express port. This mode is intended for the entry
Workstation/Server SKU of the GMCH, and would be disabled in typical Desktop
systems. When disabled, any access within entire APIC Configuration space
(FEC0_0000h to FECF_FFFFh) is forwarded to DMI.
3.3.2
HSEG (FEDA_0000h–FEDB_FFFFh)
This optional segment from FEDA_0000h to FEDB_FFFFh provides a remapping
window to SMM Memory. It is sometimes called the High SMM memory space. SMMmode processor accesses to the optionally enabled HSEG are remapped to 000A_0000h – 000B_FFFFh. Non-SMM-mode processor accesses to enabled HSEG are
considered invalid and are terminated immediately on the FSB. The exceptions to this
rule are Non-SMM-mode Write Back cycles which are remapped to SMM space to
maintain cache coherency. PCI Express and DMI originated cycles to enabled SMM
space are not allowed. Physical DRAM behind the HSEG transaction address is not
remapped and is not accessible. All Cacheline writes with WB attribute or Implicit
write backs to the HSEG range are completed to DRAM like an SMM cycle.
3.3.3
FSB Interrupt Memory Space (FEE0_0000–FEEF_FFFFh)
The FSB Interrupt space is the address used to deliver interrupts to the FSB. Any
device on PCI Express or DMI may issue a Memory Write to 0FEEx_xxxxh. The GMCH
will forward this Memory Write along with the data to the FSB as an Interrupt Message
Transaction. The GMCH terminates the FSB transaction by providing the response and
asserting HTRDY#. This Memory Write cycle does not go to DRAM.
3.3.4
High BIOS Area
The top 2 MB (FFE0_0000h -FFFF_FFFFh) of the PCI Memory Address Range is
reserved for System BIOS (High BIOS), extended BIOS for PCI devices, and the A20
alias of the system BIOS. The processor begins execution from the High BIOS after
reset. This region is mapped to DMI Interface so that the upper subset of this region
aliases to 16 MB-256 KB range. The actual address space required for the BIOS is less
than 2 MB but the minimum processor MTRR range for this region is 2 MB so that full
2 MB must be considered.
54
Datasheet
System Address Map
3.4
Main Memory Address Space (4 GB to TOUUD)
The G35 GMCH will support 36 bit addressing.
The maximum main memory size supported is 16 GB total DRAM memory. A hole
between TOLUD and 4 GB occurs when main memory size approaches 4 GB or larger.
As a result, TOM, and TOUUD registers and RECLAIMBASE/RECLAIMLIMIT registers
become relevant.
The new reclaim configuration registers exist to reclaim lost main memory space. The
greater than 32 bit reclaim handling will be handled similar to other GMCHs.
Upstream read and write accesses above 36-bit addressing will be treated as invalid
cycles by PEG and DMI.
Top of Memory
The “Top of Memory” (TOM) register reflects the total amount of populated physical
memory. This is NOT necessarily the highest main memory address (holes may exist
in main memory address map due to addresses allocated for memory mapped I/O
above TOM). TOM is used to allocate the Manageability Engine's stolen memory. The
Manageability Engine's (ME) stolen size register reflects the total amount of physical
memory stolen by the Manageability Engine. The ME stolen memory is located at the
top of physical memory. The ME stolen memory base is calculated by subtracting the
amount of memory stolen by the Manageability Engine from TOM.
The Top of Upper Usable Dram (TOUUD) register reflects the total amount of
addressable DRAM. If reclaim is disabled, TOUUD will reflect TOM minus Manageability
Engine's stolen size. If reclaim is enabled, then it will reflect the reclaim limit. Also,
the reclaim base will be the same as TOM minus ME stolen memory size to the nearest
64 MB alignment.
TOLUD register is restricted to 4 GB memory (A[31:20]), but G35 can support up to
16 GB, limited by DRAM pins. For physical memory greater than 4 GB, the TOUUD
register helps identify the address range in between the 4 GB boundary and the top of
physical memory. This identifies memory that can be directly accessed (including
reclaim address calculation) which is useful for memory access indication, early path
indication, and trusted read indication. When reclaim is enabled, TOLUD must be
64MB aligned, but when reclaim is disabled, TOLUD can be 1 MB aligned.
C1DRB3 cannot be used directly to determine the effective size of memory as the
values programmed in the DRBs depend on the memory mode (Flex memory mode,
interleaved). The Reclaim Base/Limit registers also can not be used because reclaim
can be disabled. The C0DRB3 register is used for memory channel identification
(channel 0 vs. channel 1) in the case of Flex memory mode operation.
Datasheet
55
System Address Map
3.4.1
Memory Re-claim Background
The following are examples of Memory Mapped IO devices are typically located below
4 GB:
•
High BIOS
•
HSEG
•
TSEG
•
GFXstolen
•
XAPIC
•
Local APIC
•
FSB Interrupts
•
Mbase/Mlimit
•
Memory Mapped I/O space that supports only 32B addressing
The GMCH provides the capability to re-claim the physical memory overlapped by the
Memory Mapped I/O logical address space. The GMCH re-maps physical memory from
the Top of Low Memory (TOLUD) boundary up to the 4 GB boundary to an equivalent
sized logical address range located just below the Manageability Engine's stolen
memory.
3.4.2
Memory Reclaiming
An incoming address (referred to as a logical address) is checked to see if it falls in
the memory re-map window. The bottom of the re-map window is defined by the
value in the RECLAIMBASE register. The top of the re-map window is defined by the
value in the RECLAIMLIMIT register. An address that falls within this window is
reclaimed to the physical memory starting at the address defined by the TOLUD
register. The TOLUD register must be 64M aligned when RECLAIM is enabled, but can
be 1M aligned when reclaim is disabled.
3.5
PCI Express* Configuration Address Space
There is a device 0 register, PCIEXBAR, that defines the base address for the
configuration space associated with all devices and functions that are potentially a
part of the PCI Express root complex hierarchy. The size of this range is
programmable for GMCH. BIOS must assign this address range such that it will not
conflict with any other address ranges.
See the configuration portion of this document for more details.
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System Address Map
3.6
PCI Express* Graphics Attach (PEG)
The GMCH can be programmed to direct memory accesses to the PCI Express
interface when addresses are within either of two ranges specified via registers in
GMCH’s Device 1 configuration space.
•
The first range is controlled via the Memory Base Register (MBASE) and Memory
Limit Register (MLIMIT) registers.
•
The second range is controlled via the Pre-fetchable Memory Base (PMBASE) and
Pre-fetchable Memory Limit (PMLIMIT) registers.
Conceptually, address decoding for each range follows the same basic concept. The
top 12 bits of the respective Memory Base and Memory Limit registers correspond to
address bits A[31:20] of a memory address . For the purpose of address decoding, the
GMCH assumes that address bits A[19:0] of the memory base are zero and that
address bits A[19:0] of the memory limit address are FFFFFh. This forces each
memory address range to be aligned to 1MB boundary and to have a size granularity
of 1 MB.
The GMCH positively decodes memory accesses to PCI Express memory address space
as defined by the following equations:
Memory_Base_Address ≤ Address ≤ Memory_Limit_Address
Prefetchable_Memory_Base_Address ≤ Address ≤ Prefetchable_Memory_Limit_Address
The window size is programmed by the plug-and-play configuration software. The
window size depends on the size of memory claimed by the PCI Express device.
Normally these ranges will reside above the Top-of-Low Usable-DRAM and below High
BIOS and APIC address ranges. They MUST reside above the top of low memory
(TOLUD) if they reside below 4 GB and MUST reside above top of upper memory
(TOUUD) if they reside above 4 GB or they will steal physical DRAM memory space.
It is essential to support a separate Pre-fetchable range in order to apply USWC
attribute (from the processor point of view ) to that range. The USWC attribute is used
by the processor for write combining.
Note that the GMCH Device 1 memory range registers described above are used to
allocate memory address space for any PCI Express devices sitting on PCI Express
that require such a window.
The PCICMD1 register can override the routing of memory accesses to PCI Express. In
other words, the memory access enable bit must be set in the device 1 PCICMD1
register to enable the memory base/limit and pre-fetchable base/limit windows.
The upper PMUBASE1/PMULIMIT1 registers have been implemented for PCI Express
Specification compliance. The GMCH 36 bit addressing locates MMIO space above 4 GB
using these registers.
Datasheet
57
System Address Map
3.7
Graphics Memory Address Ranges
The GMCH can be programmed to direct memory accesses to IGD when addresses are
within any of five ranges specified via registers in the GMCH’s Device 2 configuration
space.
1.
The Memory Map Base Register (MMADR) is used to access graphics control
registers.
2.
The Graphics Memory Aperture Base Register (GMADR) is used to access graphics
memory allocated via the graphics translation table.
3.
The Graphics Translation Table Base Register (GTTADR) is used to access the
translation table.
4.
The LT Graphics Memory Aperture Base Register (TGABAR) is used to access
protected graphics memory allocated via the graphics translation table.
5.
The LT Graphics Translation Table Base Register (TGGTT) is used to access the
protected translation table.
These ranges can reside above the Top-of-Low-DRAM and below High BIOS and APIC
address ranges or above Top of upper DRAM (TOUUD). They MUST reside above the
top of memory (TOLUD) and below 4 GB or above TOUUD so they do not steal any
physical DRAM memory space.
GMADR is a Prefetchable range in order to apply USWC attribute (from the processor
point of view) to that range. The USWC attribute is used by the processor for write
combining.
3.8
System Management Mode (SMM)
System Management Mode uses main memory for System Management RAM (SMM
RAM). The GMCH supports: Compatible SMRAM (C_SMRAM), High Segment (HSEG),
and Top of Memory Segment (TSEG). System Management RAM space provides a
memory area that is available for the SMI handlers and code and data storage. This
memory resource is normally hidden from the system OS so that the processor has
immediate access to this memory space upon entry to SMM. GMCH provides three
SMRAM options:
•
Below 1 MB option that supports compatible SMI handlers.
•
Above 1 MB option that allows new SMI handlers to execute with write-back
cacheable SMRAM.
•
Optional TSEG area of 1 MB, 2 MB, or 8 MB in size. The TSEG area lies below IGD
stolen memory.
The above 1 MB solutions require changes to compatible SMRAM handlers code to
properly execute above 1 MB.
Note: DMI Interface and PCI Express masters are not allowed to access the SMM space.
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System Address Map
3.8.1
SMM Space Definition
SMM space is defined by its addressed SMM space and its DRAM SMM space. The
addressed SMM space is defined as the range of bus addresses used by the processor
to access SMM space. DRAM SMM space is defined as the range of physical DRAM
memory locations containing the SMM code. SMM space can be accessed at one of
three transaction address ranges: Compatible, High and TSEG. The Compatible and
TSEG SMM space is not remapped and therefore the addressed and DRAM SMM space
is the same address range. Since the High SMM space is remapped the addressed and
DRAM SMM space is a different address range. Note that the High DRAM space is the
same as the Compatible Transaction Address space. Table 3-6 describes three unique
address ranges.
Table 3-6. Pre-Allocated Memory Example for 64-MB DRAM, 1-MB VGA and 1-MB TSEG
3.8.2
SMM Space
Enabled
Transaction Address Space
DRAM Space (DRAM)
Compatible
000A_0000h to 000B_FFFFh
000A_0000h to 000B_FFFFh
High
FEDA_0000h to FEDB_FFFFh
000A_0000h to 000B_FFFFh
TSEG
(TOLUD–STOLEN–TSEG) to
TOLUD–STOLEN
(TOLUD–STOLEN–TSEG) to
TOLUD–STOLEN
SMM Space Restrictions
If any of the following conditions are violated the results of SMM accesses are
unpredictable and may cause the system to hang:
Datasheet
•
The Compatible SMM space must not be set-up as cacheable.
•
High or TSEG SMM transaction address space must not overlap address space
assigned to system DRAM, or to any “PCI” devices (including DMI Interface, PCIExpress, and graphics devices). This is a BIOS responsibility.
•
Both D_OPEN and D_CLOSE must not be set to 1 at the same time.
•
When TSEG SMM space is enabled, the TSEG space must not be reported to the
OS as available DRAM. This is a BIOS responsibility.
•
Any address translated through the GMADR TLB must not target DRAM from
A_0000-F_FFFFh.
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System Address Map
3.8.3
SMM Space Combinations
When High SMM is enabled (G_SMRAME=1 and H_SMRAM_EN=1) the Compatible
SMM space is effectively disabled. Processor originated accesses to the Compatible
SMM space are forwarded to PCI Express if VGAEN=1 (also depends on MDAP),
otherwise they are forwarded to the DMI Interface. PCI Express and DMI Interface
originated accesses are never allowed to access SMM space.
Table 3-7. SMM Space Table
3.8.4
Global
Enable
G_SMRAME
High Enable
H_SMRAM_E
N
TSEG
Enable
TSEG_EN
Compatible
(C) Range
High
(H)
Range
TSEG
(T)
Range
0
X
X
Disable
Disable
Disable
1
0
0
Enable
Disable
Disable
1
0
1
Enable
Disable
Enable
1
1
0
Disabled
Enable
Disable
1
1
1
Disabled
Enable
Enable
SMM Control Combinations
The G_SMRAME bit provides a global enable for all SMM memory. The D_OPEN bit
allows software to write to the SMM ranges without being in SMM mode. BIOS
software can use this bit to initialize SMM code at power-up. The D_LCK bit limits the
SMM range access to only SMM mode accesses. The D_CLS bit causes SMM data
accesses to be forwarded to the DMI Interface or PCI Express. The SMM software can
use this bit to write to video memory while running SMM code out of DRAM.
Table 3-8. SMM Control
60
G_SMRAME
D_LCK
D_CLS
D_OPEN
Processor
in SMM
Mode
SMM
Code
Access
SMM Data
Access
0
x
X
x
x
Disable
Disable
1
0
X
0
0
Disable
Disable
1
0
0
0
1
Enable
Enable
1
0
0
1
x
Enable
Enable
1
0
1
0
1
Enable
Disable
1
0
1
1
x
Invalid
Invalid
1
1
X
x
0
Disable
Disable
1
1
0
x
1
Enable
Enable
1
1
1
x
1
Enable
Disable
Datasheet
System Address Map
3.8.5
SMM Space Decode and Transaction Handling
Only the processor is allowed to access SMM space. PCI Express and DMI Interface
originated transactions are not allowed to SMM space. The following tables indicate
the action taken by the GMCH when the accesses to the various enabled SMM space
occurs.
3.8.6
Processor WB Transaction to an Enabled SMM Address
Space
Processor Writeback transactions (REQa[1]# = 0) to enabled SMM Address Space
must be written to the associated SMM DRAM even though D_OPEN=0 and the
transaction is not performed in SMM mode. This ensures SMM space cache coherency
when cacheable extended SMM space is used.
3.8.7
SMM Access Through GTT TLB
Accesses through GTT TLB address translation to enabled SMM DRAM space are not
allowed. Writes will be routed to Memory address 000C_0000h with byte enables deasserted and reads will be routed to Memory address 000C_0000h. If a GTT TLB
translated address hits enabled SMM DRAM space, an error is recorded.
PCI Express and DMI Interface originated accesses are never allowed to access SMM
space directly or through the GTT TLB address translation. If a GTT TLB translated
address hits enabled SMM DRAM space, an error is recorded.
PCI Express and DMI Interface write accesses through GMADR range will be snooped.
Assesses to GMADR linear range (defined via fence registers) are supported. PCI
Express and DMI Interface tileY and tileX writes to GMADR are not supported. If, when
translated, the resulting physical address is to enabled SMM DRAM space, the request
will be remapped to address 000C_0000h with de-asserted byte enables.
PCI Express and DMI Interface read accesses to the GMADR range are not supported,
therefore will have no address translation concerns. PCI Express and DMI Interface
reads to GMADR will be remapped to address 000C_0000h. The read will complete
with UR (unsupported request) completion status.
GTT fetches are always decoded (at fetch time) to ensure not in SMM (actually,
anything above base of TSEG or 640 KB – 1 MB). Thus, they will be invalid and go to
address 000C_0000h, but that isn’t specific to PCI Express or DMI; it applies to
processor or internal graphics engines. Also, since the GMADR snoop would not be
directly to the SMM space, there would not be a writeback to SMM. In fact, the
writeback would also be invalid (because it uses the same translation) and go to
address 000C_0000h.
Datasheet
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System Address Map
3.9
Memory Shadowing
Any block of memory that can be designated as read-only or write-only can be
“shadowed” into GMCH DRAM memory. Typically this is done to allow ROM code to
execute more rapidly out of main DRAM. ROM is used as a read-only during the copy
process while DRAM at the same time is designated write-only. After copying, the
DRAM is designated read-only so that ROM is shadowed. Processor bus transactions
are routed accordingly.
3.10
I/O Address Space
The GMCH does not support the existence of any other I/O devices beside itself on the
processor bus. The GMCH generates either DMI Interface or PCI Express bus cycles for
all processor I/O accesses that it does not claim. Within the host bridge, the GMCH
contains two internal registers in the processor I/O space, Configuration Address
Register (CONFIG_ADDRESS) and the Configuration Data Register (CONFIG_DATA).
These locations are used to implement configuration space access mechanism.
The processor allows 64K+3 bytes to be addressed within the I/O space. The GMCH
propagates the processor I/O address without any translation on to the destination
bus and therefore provides addressability for 64K+3 byte locations. Note that the
upper 3 locations can be accessed only during I/O address wrap-around when
processor bus HA16# address signal is asserted. HA16# is asserted on the processor
bus when an I/O access is made to 4 bytes from address 0FFFDh, 0FFFEh, or 0FFFFh.
HA16# is also asserted when an I/O access is made to 2 bytes from address 0FFFFh.
A set of I/O accesses (other than ones used for configuration space access) are
consumed by the internal graphics device if it is enabled. The mechanisms for internal
graphics IO decode and the associated control is explained later.
The I/O accesses (other than ones used for configuration space access) are forwarded
normally to the DMI Interface bus unless they fall within the PCI Express I/O address
range as defined by the mechanisms explained below. I/O writes are NOT posted.
Memory writes to the ICH or PCI Express are posted. The PCICMD1 register can
disable the routing of I/O cycles to the PCI Express.
The GMCH responds to I/O cycles initiated on PCI Express or DMI with an UR status.
Upstream I/O cycles and configuration cycles should never occur. If one does occur,
the request will route as a read to Memory address 000C_0000h so a completion is
naturally generated (whether the original request was a read or write). The
transaction will complete with an UR completion status.
For Intel microprocessors, I/O reads that lie within 8-byte boundaries but cross 4-byte
boundaries are issued from the processor as 1 transaction. The GMCH will break this
into 2 separate transactions. I/O writes that lie within 8-byte boundaries but cross 4byte boundaries are assumed to be split into 2 transactions by the processor.
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System Address Map
3.10.1
PCI Express* I/O Address Mapping
The GMCH can be programmed to direct non-memory (I/O) accesses to the PCI
Express bus interface when processor initiated I/O cycle addresses are within the PCI
Express I/O address range. This range is controlled via the I/O Base Address
(IOBASE) and I/O Limit Address (IOLIMIT) registers in GMCH Device 1 configuration
space.
Address decoding for this range is based on the following concept. The top 4 bits of
the respective I/O Base and I/O Limit registers correspond to address bits A[15:12] of
an I/O address. For the purpose of address decoding, the GMCH assumes that lower
12 address bits A[11:0] of the I/O base are zero and that address bits A[11:0] of the
I/O limit address are FFFh. This forces the I/O address range alignment to 4 KB
boundary and produces a size granularity of 4 KB.
The GMCH positively decodes I/O accesses to PCI Express I/O address space as
defined by the following equation:
I/O_Base_Address ≤ Processor I/O Cycle Address ≤ I/O_Limit_Address
The effective size of the range is programmed by the plug-and-play configuration
software and it depends on the size of I/O space claimed by the PCI Express device.
The GMCH also forwards accesses to the Legacy VGA I/O ranges according to the
settings in the Device 1 configuration registers BCTRL (VGA Enable) and PCICMD1
(IOAE1), unless a second adapter (monochrome) is present on the DMI Interface/PCI
(or ISA). The presence of a second graphics adapter is determined by the MDAP
configuration bit. When MDAP is set, the GMCH will decode legacy monochrome I/O
ranges and forward them to the DMI Interface. The I/O ranges decoded for the
monochrome adapter are 3B4h, 3B5h, 3B8h, 3B9h, 3BAh, and 3BFh.
Note that the GMCH Device 1 I/O address range registers defined above are used for
all I/O space allocation for any devices requiring such a window on PCI-Express.
The PCICMD1 register can disable the routing of I/O cycles to PCI-Express.
3.11
MCH Decode Rules and Cross-Bridge Address
Mapping
VGAA = 000A_0000h – 000A_FFFFh
MDA = 000B_0000h – 000B_7FFFh
VGAB = 000B_8000h – 000B_FFFFh
MAINMEM = 0100_0000h to TOLUD
HIGHMEM = 4 GB to TOM
RECLAIMMEM = RECLAIMBASE to RECLAIMLIMIT
Datasheet
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System Address Map
3.11.1
Legacy VGA and I/O Range Decode Rules
The legacy 128 KB VGA memory range 000A_0000h-000B_FFFFh can be mapped to
IGD (Device 2), to PCI Express (Device 1), and/or to the DMI Interface depending on
the programming of the VGA steering bits. Priority for VGA mapping is constant in that
the GMCH always decodes internally mapped devices first. Internal to the GMCH,
decode precedence is always given to IGD. The GMCH always positively decodes
internally mapped devices, namely the IGD and PCI-Express. Subsequent decoding of
regions mapped to PCI Express or the DMI Interface depends on the Legacy VGA
configurations bits (VGA Enable and MDAP).
§
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System Address Map
Datasheet
65
GMCH Register Description
4
GMCH Register Description
The GMCH contains two sets of software accessible registers, accessed via the Host
processor I/O address space: Control registers and internal configuration registers.
•
Control registers are I/O mapped into the processor I/O space, which control
access to PCI and PCI Express configuration space (see section entitled I/O
Mapped Registers).
•
Internal configuration registers residing within the GMCH are partitioned into three
logical device register sets (“logical” since they reside within a single physical
device). The first register set is dedicated to Host Bridge functionality (i.e., DRAM
configuration, other chip-set operating parameters and optional features). The
second register block is dedicated to Host-PCI Express Bridge functions (controls
PCI Express interface configurations and operating parameters). The GMCH
contains a third register block for the internal graphics functions. The GMCH also
contains a fourth register block for the Manageability Engine.
The GMCH internal registers (I/O Mapped, Configuration and PCI Express Extended
Configuration registers) are accessible by the Host processor. The registers that reside
within the lower 256 bytes of each device can be accessed as Byte, Word (16-bit), or
DWord (32-bit) quantities, with the exception of CONFIG_ADDRESS, which can only
be accessed as a DWord. All multi-byte numeric fields use "little-endian" ordering
(i.e., lower addresses contain the least significant parts of the field). Registers which
reside in bytes 256 through 4095 of each device may only be accessed using memory
mapped transactions in DWord (32-bit) quantities.
Some of the GMCH registers described in this section contain reserved bits. These bits
are labeled "Reserved”. Software must deal correctly with fields that are reserved. On
reads, software must use appropriate masks to extract the defined bits and not rely
on reserved bits being any particular value. On writes, software must ensure that the
values of reserved bit positions are preserved. That is, the values of reserved bit
positions must first be read, merged with the new values for other bit positions and
then written back. Note the software does not need to perform read, merge, and write
operation for the configuration address register.
In addition to reserved bits within a register, the GMCH contains address locations in
the configuration space of the Host Bridge entity that are marked either "Reserved" or
“Intel Reserved”. The GMCH responds to accesses to “Reserved” address locations by
completing the host cycle. When a “Reserved” register location is read, a zero value is
returned. (“Reserved” registers can be 8-, 16-, or 32-bits in size). Writes to
“Reserved” registers have no effect on the GMCH. Registers that are marked as “Intel
Reserved” must not be modified by system software. Writes to “Intel Reserved”
registers may cause system failure. Reads from “Intel Reserved” registers may return
a non-zero value.
Upon a Full Reset, the GMCH sets its entire set of internal configuration registers to
predetermined default states. Some register values at reset are determined by
external strapping options. The default state represents the minimum functionality
feature set required to successfully bringing up the system. Hence, it does not
represent the optimal system configuration. It is the responsibility of the system
initialization software (usually BIOS) to properly determine the DRAM configurations,
operating parameters and optional system features that are applicable, and to
program the GMCH registers accordingly.
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Datasheet
GMCH Register Description
4.1
Register Terminology
The following table shows the register-related terminology that is used.
Item
Datasheet
Description
RO
Read Only bit(s). Writes to these bits have no effect.
RS/WC
Read Set / Write Clear bit(s). These bits are set to ‘1’ when read and then will
continue to remain set until written. A write of ‘1’ clears (sets to ‘0’) the
corresponding bit(s) and a write of ‘0’ has no effect.
R/W
Read / Write bit(s). These bits can be read and written.
R/WC
Read / Write Clear bit(s). These bits can be read. Internal events may set this
bit. A write of ‘1’ clears (sets to ‘0’) the corresponding bit(s) and a write of ‘0’
has no effect.
R/WC/S
Read / Write Clear / Sticky bit(s). These bits can be read. Internal events may
set this bit. A write of ‘1’ clears (sets to ‘0’) the corresponding bit(s) and a write
of ‘0’ has no effect. Bits are not cleared by "warm" reset, but will be reset with a
cold/complete reset (for PCI Express* related bits a cold reset is “Power Good
Reset” as defined in the PCI Express* Specification).
R/W/K
Read / Write / Key bit(s). These bits can be read and written by software.
Additionally this bit when set, prohibits some other bit field(s) from being
writeable (bit fields become Read Only).
R/W/L
Read / Write / Lockable bit(s). These bits can be read and written. Additionally
there is a bit (which may or may not be a bit marked R/W/L) that, when set,
prohibits this bit field from being writeable (bit field becomes Read Only).
R/W/S
Read / Write / Sticky bit(s). These bits can be read and written. Bits are not
cleared by "warm" reset, but will be reset with a cold/complete reset (for PCI
Express related bits a cold reset is “Power Good Reset” as defined in the PCI
Express* Specification).
R/WSC
Read / Write Self Clear bit(s). These bits can be read and written. When the bit
is ‘1’, hardware may clear the bit to ‘0’ based upon internal events, possibly
sooner than any subsequent read could retrieve a ‘1’.
R/WSC/L
Read / Write Self Clear / Lockable bit(s). These bits can be read and written.
When the bit is ‘1’, hardware may clear the bit to ‘0’ based upon internal events,
possibly sooner than any subsequent read could retrieve a ‘1’. Additionally there
is a bit (which may or may not be a bit marked R/W/L) that, when set, prohibits
this bit field from being writeable (bit field becomes Read Only).
R/WO
Write Once bit(s). Once written, bits with this attribute become Read Only.
These bits can only be cleared by a Reset.
W
Write Only. Whose bits may be written, but will always-return zeros when read.
They are used for write side effects. Any data written to these registers cannot
be retrieved.
67
GMCH Register Description
4.2
Configuration Process and Registers
4.2.1
Platform Configuration Structure
The DMI physically connects the GMCH and the Intel ICH8; so, from a configuration
standpoint, the DMI is logically PCI bus 0. As a result, all devices internal to the GMCH
and the Intel ICH8 appear to be on PCI bus 0.
Note: The ICH8 internal LAN controller does not appear on bus 0 – it appears on the
external PCI bus (whose number is configurable).
The system’s primary PCI expansion bus is physically attached to the Intel ICH8 and,
from a configuration perspective, appears to be a hierarchical PCI bus behind a PCIto-PCI bridge and therefore has a programmable PCI Bus number. The PCI Express
Graphics Attach appears to system software to be a real PCI bus behind a PCI-to-PCI
bridge that is a device resident on PCI bus 0.
Note: A physical PCI bus 0 does not exist and that DMI and the internal devices in the GMCH
and Intel ICH8 logically constitute PCI Bus 0 to configuration software. This is shown
in the Figure 4-1.
Figure 4-1. Conceptual G Platform PCI Configuration Diagram
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GMCH Register Description
The GMCH contains three PCI devices within a single physical component. The
configuration registers for the three devices are mapped as devices residing on PCI
bus 0.
4.3
•
Device 0: Host Bridge/DRAM Controller. Logically this appears as a PCI device
residing on PCI bus 0. Device 0 contains the standard PCI header registers, PCI
Express base address register, DRAM control, and configuration for the DMI and
other GMCH specific registers.
•
Device 1: Host-PCI Express Bridge. Logically this appears as a “virtual” PCI-toPCI bridge residing on PCI bus 0 and is compliant with PCI Express* Specification
Rev 1.1. Device 1 contains the standard PCI-to-PCI bridge registers and the
standard PCI Express/PCI configuration registers (including the PCI Express
memory address mapping). It also contains Isochronous and Virtual Channel
controls in the PCI Express extended configuration space.
•
Device 2: Internal Graphics Control. Logically, this appears as a PCI device
residing on PCI bus 0. Physically, device 2 contains the configuration registers for
3D, 2D, and display functions.
•
Device 3: Manageability Engine Device. Logically, this appears as a PCI device
residing on PCI bus 0. Physically, device 3.
Configuration Mechanisms
The processor is the originator of configuration cycles so the FSB is the only interface
in the platform where these mechanisms are used. Internal to the GMCH transactions
received through both configuration mechanisms are translated to the same format.
4.3.1
Standard PCI Configuration Mechanism
The following is the mechanism for translating processor I/O bus cycles to
configuration cycles.
The PCI specification defines a slot based "configuration space" that allows each
device to contain up to 8 functions with each function containing up to 256 8-bit
configuration registers. The PCI specification defines two bus cycles to access the PCI
configuration space: Configuration Read and Configuration Write. Memory and I/O
spaces are supported directly by the processor. Configuration space is supported by a
mapping mechanism implemented within the GMCH.
The configuration access mechanism makes use of the CONFIG_ADDRESS Register (at
I/O address 0CF8h though 0CFBh) and CONFIG_DATA Register (at I/O address 0CFCh
though 0CFFh). To reference a configuration register a DW I/O write cycle is used to
place a value into CONFIG_ADDRESS that specifies the PCI bus, the device on that
bus, the function within the device and a specific configuration register of the device
function being accessed. CONFIG_ADDRESS[31] must be 1 to enable a configuration
cycle. CONFIG_DATA then becomes a window into the four bytes of configuration
space specified by the contents of CONFIG_ADDRESS. Any read or write to
CONFIG_DATA will result in the GMCH translating the CONFIG_ADDRESS into the
appropriate configuration cycle.
The GMCH is responsible for translating and routing the processor’s I/O accesses to
the CONFIG_ADDRESS and CONFIG_DATA registers to internal GMCH configuration
registers, DMI or PCI Express.
Datasheet
69
GMCH Register Description
4.3.2
PCI Express* Enhanced Configuration Mechanism
PCI Express extends the configuration space to 4096 bytes per device/function as
compared to 256 bytes allowed by PCI Specification Revision 2.3. PCI Express
configuration space is divided into a PCI 2.3 compatible region, which consists of the
first 256B of a logical device’s configuration space and a PCI Express extended region
which consists of the remaining configuration space.
The PCI compatible region can be accessed using either the Standard PCI
Configuration Mechanism or using the PCI Express Enhanced Configuration Mechanism
described in this section. The extended configuration registers may only be accessed
using the PCI Express Enhanced Configuration Mechanism. To maintain compatibility
with PCI configuration addressing mechanisms, system software must access the
extended configuration space using 32-bit operations (32-bit aligned) only. These 32bit operations include byte enables allowing only appropriate bytes within the DWord
to be accessed. Locked transactions to the PCI Express memory mapped configuration
address space are not supported. All changes made using either access mechanism
are equivalent.
The PCI Express Enhanced Configuration Mechanism utilizes a flat memory-mapped
address space to access device configuration registers. This address space is reported
by the system firmware to the operating system. There is a register, PCI
EXPRESS*XBAR, that defines the base address for the block of addresses below 4GB
for the configuration space associated with busses, devices and functions that are
potentially a part of the PCI Express root complex hierarchy. In the PCI
EXPRESS*XBAR register there exists controls to limit the size of this reserved memory
mapped space. 256MB is the amount of address space required to reserve space for
every bus, device, and function that could possibly exist. Options for 128MB and 64MB
exist in order to free up those addresses for other uses. In these cases the number of
busses and all of their associated devices and functions are limited to 128 or 64
busses respectively.
The PCI Express Configuration Transaction Header includes an additional 4 bits
(ExtendedRegisterAddress[3:0]) between the Function Number and Register Address
fields to provide indexing into the 4 KB of configuration space allocated to each
potential device. For PCI Compatible Configuration Requests, the Extended Register
Address field must be all zeros.
Figure 4-2. Memory Map to PCI Express* Device Configuration Space
0xFFFFFFF
0x7FFF
0xFFFFF
Bus 255
Device 31
0xFFF
Function 7
PCI Express
Extended
Configuration
Space
0xFF
0x1FFF
0xFFFF
0x1FFFFF
Bus 1
0xFFF
0x7FFF
0xFFFFF
Bus 0
0
Function 1
Device 1
Device 0
Function 0
0x3F
PCI Compatible
Configuration
Space
PCI Compatible
Configuration
Space Header
Located by
PCI Express* Base Address
70
Datasheet
GMCH Register Description
Just the same as with PCI devices, each device is selected based on decoded address
information that is provided as a part of the address portion of Configuration Request
packets. A PCI Express device will decode all address information fields (bus, device,
function and extended address numbers) to provide access to the correct register.
To access this space (steps 1, 2, 3 are done only once by BIOS),
4.4
1.
use the PCI compatible configuration mechanism to enable the PCI Express
enhanced configuration mechanism by writing 1 to bit 0 of the PCI
EXPRESS*XBAR register.
2.
use the PCI compatible configuration mechanism to write an appropriate PCI
Express base address into the PCI EXPRESS*XBAR register
3.
calculate the host address of the register you wish to set using (PCI Express
base + (bus number * 1 MB) + (device number * 32KB) + (function number *
4 KB) + (1 B * offset within the function) = host address)
4.
use a memory write or memory read cycle to the calculated host address to
write or read that register.
Routing Configuration Accesses
The GMCH supports two PCI related interfaces: DMI and PCI Express. The GMCH is
responsible for routing PCI and PCI Express configuration cycles to the appropriate
device that is an integrated part of the GMCH or to one of these two interfaces.
Configuration cycles to the ICH8 internal devices and Primary PCI (including
downstream devices) are routed to the ICH8 via DMI. Configuration cycles to both the
PCI Express Graphics PCI compatibility configuration space and the PCI Express
Graphics extended configuration space are routed to the PCI Express Graphics port
device or associated link.
Datasheet
71
GMCH Register Description
Figure 4-3. GMCH Configuration Cycle Flow Chart
4.4.1
Internal Device Configuration Accesses
The GMCH decodes the Bus Number (bits 23:16) and the Device Number fields of the
CONFIG_ADDRESS register. If the Bus Number field of CONFIG_ADDRESS is 0, the
configuration cycle is targeting a PCI Bus 0 device.
If the targeted PCI Bus #0 device exists in the GMCH and is not disabled, the
configuration cycle is claimed by the appropriate device.
72
Datasheet
GMCH Register Description
4.4.2
Bridge Related Configuration Accesses
Configuration accesses on PCI Express or DMI are PCI Express Configuration TLPs.
•
Bus Number [7:0] is Header Byte 8 [7:0]
•
Device Number [4:0] is Header Byte 9 [7:3]
•
Function Number [2:0] is Header Byte 9 [2:0]
And special fields for this type of TLP:
•
Extended Register Number [3:0] is Header Byte 10 [3:0]
•
Register Number [5:0] is Header Byte 11 [7:2]
See the PCI Express specification for more information on both the PCI 2.3 compatible
and PCI Express Enhanced Configuration Mechanism and transaction rules.
4.4.2.1
PCI Express* Configuration Accesses
When the Bus Number of a type 1 Standard PCI Configuration cycle or PCI Express
Enhanced Configuration access matches the Device 1 Secondary Bus Number a PCI
Express Type 0 Configuration TLP is generated on the PCI Express link targeting the
device directly on the opposite side of the link. This should be Device 0 on the bus
number assigned to the PCI Express link (likely Bus 1).
The device on other side of link must be Device 0. The GMCH will Master Abort any
Type 0 Configuration access to a non-zero Device number. If there is to be more than
one device on that side of the link there must be a bridge implemented in the
downstream device.
When the Bus Number of a type 1 Standard PCI Configuration cycle or PCI Express
Enhanced Configuration access is within the claimed range (between the upper bound
of the bridge device’s Subordinate Bus Number register and the lower bound of the
bridge device’s Secondary Bus Number register) but doesn't match the Device 1
Secondary Bus Number, a PCI Express Type 1 Configuration TLP is generated on the
secondary side of the PCI Express link.
PCI Express Configuration Writes:
4.4.2.2
•
Internally the host interface unit will translate writes to PCI Express extended
configuration space to configuration writes on the backbone.
•
Writes to extended space are posted on the FSB, but non-posted on the PCI
Express or DMI (i.e., translated to configuration writes)
DMI Configuration Accesses
Accesses to disabled GMCH internal devices, bus numbers not claimed by the Host-PCI
Express bridge, or PCI Bus #0 devices not part of the GMCH will subtractively decode
to the ICH8 and consequently be forwarded over the DMI via a PCI Express
configuration TLP.
If the Bus Number is zero, the GMCH will generate a Type 0 Configuration Cycle TLP
on DMI. If the Bus Number is non-zero, and falls outside the range claimed by the
Datasheet
73
GMCH Register Description
Host-PCI Express bridge, the GMCH will generate a Type 1 Configuration Cycle TLP on
DMI.
The ICH8 routes configurations accesses in a manner similar to the GMCH. The ICH8
decodes the configuration TLP and generates a corresponding configuration access.
Accesses targeting a device on PCI Bus 0 may be claimed by an internal device. The
ICH7 compares the non-zero Bus Number with the Secondary Bus Number and
Subordinate Bus Number registers of its P2P bridges to determine if the configuration
access is meant for Primary PCI, or some other downstream PCI bus or PCI Express
link.
Configuration accesses that are forwarded to the ICH8, but remain unclaimed by any
device or bridge will result in a master abort.
4.5
I/O Mapped Registers
The GMCH contains two registers that reside in the processor I/O address space − the
Configuration Address (CONFIG_ADDRESS) Register and the Configuration Data
(CONFIG_DATA) Register. The Configuration Address Register enables/disables the
configuration space and determines what portion of configuration space is visible
through the Configuration Data window.
4.5.1
CONFIG_ADDRESS—Configuration Address Register
I/O Address:
Default Value:
Access:
Size:
0CF8h Accessed as a DW
00000000h
R/W
32 bits
CONFIG_ADDRESS is a 32-bit register that can be accessed only as a DW. A Byte or
Word reference will "pass through" the Configuration Address Register and DMI onto
the Primary PCI bus as an I/O cycle. The CONFIG_ADDRESS register contains the Bus
Number, Device Number, Function Number, and Register Number for which a
subsequent configuration access is intended.
Bit
Access &
Default
31
R/W
0b
Description
Configuration Enable (CFGE):
0 = Disable
1 = Enable
30:24
74
Reserved
Datasheet
GMCH Register Description
Bit
Access &
Default
Description
23:16
R/W
Bus Number: If the Bus Number is programmed to 00h the target of
the Configuration Cycle is a PCI Bus #0 agent. If this is the case and
the GMCH is not the target (i.e. the device number is >= 2), then a
DMI Type 0 Configuration Cycle is generated.
00h
If the Bus Number is non-zero, and does not fall within the ranges
enumerated by device 1’s Secondary Bus Number or Subordinate Bus
Number Register, then a DMI Type 1 Configuration Cycle is
generated.
If the Bus Number is non-zero and matches the value programmed
into the Secondary Bus Number Register of device 1, a Type 0 PCI
configuration cycle will be generated on PCI Express.
If the Bus Number is non-zero, greater than the value in the
Secondary Bus Number register of device 1 and less than or equal to
the value programmed into the Subordinate Bus Number Register of
device 1 a Type 1 PCI configuration cycle will be generated on PCI
Express.
This field is mapped to byte 8 [7:0] of the request header format
during PCI Express Configuration cycles and A[23:16] during the DMI
Type 1 configuration cycles.
15:11
R/W
00h
Device Number: This field selects one agent on the PCI bus selected
by the Bus Number. When the Bus Number field is “00” the GMCH
decodes the Device Number field. The GMCH is always Device
Number 0 for the Host bridge entity, Device Number 1 for the HostPCI Express entity. Therefore, when the Bus Number =0 and the
Device Number equals 0, 1, or 2 the internal GMCH devices are
selected.
This field is mapped to byte 6 [7:3] of the request header format
during PCI Express Configuration cycles and A [15:11] during the
DMI configuration cycles.
10:8
R/W
000b
Function Number: This field allows the configuration registers of a
particular function in a multi-function device to be accessed. The
GMCH ignores configuration cycles to its internal devices if the
function number is not equal to 0 or 1.
This field is mapped to byte 6 [2:0] of the request header format
during PCI Express Configuration cycles and A[10:8] during the DMI
configuration cycles.
7:2
R/W
00h
Register Number: This field selects one register within a particular
Bus, Device, and Function as specified by the other fields in the
Configuration Address Register.
This field is mapped to byte 7 [7:2] of the request header format
during PCI Express Configuration cycles and A[7:2] during the DMI
Configuration cycles.
1:0
Datasheet
Reserved
75
GMCH Register Description
4.5.2
CONFIG_DATA—Configuration Data Register
I/O Address:
Default Value:
Access:
Size:
0CFCh
00000000h
R/W
32 bits
CONFIG_DATA is a 32-bit read/write window into configuration space. The portion of
configuration space that is referenced by CONFIG_DATA is determined by the contents
of CONFIG_ADDRESS.
Bit
Access &
Default
Description
31:0
R/W
Configuration Data Window (CDW): If bit 31 of
CONFIG_ADDRESS is 1, any I/O access to the CONFIG_DATA register
will produce a configuration transaction using the contents of
CONFIG_ADDRESS to determine the bus, device, function, and offset
of the register to be accessed.
00000000h
§
76
Datasheet
GMCH Register Description
Datasheet
77
DRAM Controller Registers (D0:F0)
5
DRAM Controller Registers
(D0:F0)
5.1
DRAM Controller (D0:F0)
The DRAM Controller registers are in Device 0 (D0), Function 0 (F0).
Warning: Address locations that are not listed are considered Intel Reserved registers locations.
Reads to Reserved registers may return non-zero values. Writes to reserved locations
may cause system failures.
All registers that are defined in the PCI 2.3 specification, but are not necessary or
implemented in this component are simply not included in this document. The
reserved/unimplemented space in the PCI configuration header space is not
documented as such in this summary.
Table 5-1. DRAM Controller Register Address Map (D0:F0)
78
Address
Offset
Register
Symbol
00–01h
VID
02–03h
DID
04–05h
Register Name
Default
Value
Access
Vendor Identification
8086h
RO
Device Identification
29C0h
RO
PCICMD
PCI Command
0006h
RO, RW
06–07h
PCISTS
PCI Status
0090h
RWC, RO
08h
RID
Revision Identification
00h
RO
09–0Bh
CC
Class Code
060000h
RO
0Dh
MLT
Master Latency Timer
00h
RO
0Eh
HDR
Header Type
00h
RO
2C–2Dh
SVID
Subsystem Vendor Identification
0000h
RWO
2E–2Fh
SID
Subsystem Identification
0000h
RWO
34h
CAPPTR
E0h
RO
40–47h
PXPEPBAR
PCI Express Port Base Address
0000000000
000000h
RW, RO
48–4Fh
MCHBAR
GMCH Memory Mapped Register
Range Base
0000000000
000000h
RW, RO
52–53h
GGC
GMCH Graphics Control Register
0030h
RO, RW/L
54–57h
DEVEN
000003DBh
RO, RW/L
Capabilities Pointer
Device Enable
Datasheet
DRAM Controller Registers (D0:F0)
Datasheet
Address
Offset
Register
Symbol
Register Name
Default
Value
Access
60–67h
PCIEXBAR
PCI Express Register Range Base
Address
00000000E0
000000h
RO, RW,
RW/L,
RW/K
68–6Fh
DMIBAR
Root Complex Register Range
Base Address
0000000000
000000h
RO, RW
90h
PAM0
Programmable Attribute Map 0
00h
RO, RW
91h
PAM1
Programmable Attribute Map 1
00h
RO, RW
92h
PAM2
Programmable Attribute Map 2
00h
RO, RW
93h
PAM3
Programmable Attribute Map 3
00h
RO, RW
94h
PAM4
Programmable Attribute Map 4
00h
RO, RW
95h
PAM5
Programmable Attribute Map 5
00h
RO, RW
96h
PAM6
Programmable Attribute Map 6
00h
RO, RW
97h
LAC
Legacy Access Control
00h
RO, RW
98–99h
REMAPBASE
Remap Base Address Register
03FFh
RO, RW
9A–9Bh
REMAPLIMI
T
Remap Limit Address Register
0000h
RO, RW
9Dh
SMRAM
System Management RAM Control
02h
RO, RW/L,
RW,
RW/L/K
9Eh
ESMRAMC
Extended System Management
RAM Control
38h
RW/L,
RWC, RO
A0–A1h
TOM
Top of Memory
0001h
RO, RW/L
A2–A3h
TOUUD
Top of Upper Usable Dram
0000h
RW/L
A4–A7h
GBSM
Graphics Base of Stolen Memory
00000000h
RW/L ,RO
AC–AFh
TSEGMB
TSEG Memory Base
00000000h
RW/L, RO
B0–B1h
TOLUD
Top of Low Usable DRAM
0010h
RW/L RO
C8–C9h
ERRSTS
Error Status
0000h
RO,
RWC/S
CA–CBh
ERRCMD
Error Command
0000h
RO, RW
CC–CDh
SMICMD
SMI Command
0000h
RO, RW
DC–DFh
SKPD
00000000h
RW
E0–E9h
CAPID0
0000000000
0001090009
h
RO
Scratchpad Data
Capability Identifier
79
DRAM Controller Registers (D0:F0)
5.1.1
VID—Vendor Identification
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/PCI
0–1h
8086h
RO
16 bits
This register combined with the Device Identification register uniquely identifies any
PCI device.
5.1.2
Bit
Access &
Default
15:0
RO
8086h
Description
Vendor Identification Number (VID): PCI standard identification
for Intel.
DID—Device Identification
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/PCI
02–03h
See table below
RO
16 bits
This register combined with the Vendor Identification register uniquely identifies any
PCI device.
Bit
Access &
Default
15:0
RO
29C0h
80
Description
Device Identification Number (DID):
29C0h = Intel® 82G35 GMCH
Datasheet
DRAM Controller Registers (D0:F0)
5.1.3
PCICMD—PCI Command
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/PCI
4–5h
0006h
RO, RW
16 bits
Since GMCH Device 0 does not physically reside on PCI_A many of the bits are not
implemented.
Bit
Access &
Default
Description
15:10
RO
00h
Reserved
9
RO
0b
Fast Back-to-Back Enable (FB2B): This bit controls whether or not
the master can do fast back-to-back write. Since device 0 is strictly a
target, this bit is not implemented and is hardwired to 0.
8
RW
0b
SERR Enable (SERRE): This bit is a global enable bit for Device 0
SERR messaging. The GMCH does not have an SERR signal. The GMCH
communicates the SERR condition by sending an SERR message over
DMI to the ICH.
1= The GMCH is enabled to generate SERR messages over DMI for
specific Device 0 error conditions that are individually enabled in
the ERRCMD and DMIUEMSK registers. The error status is reported
in the ERRSTS, PCISTS, and DMIUEST registers.
0 = The SERR message is not generated by the GMCH for Device 0.
Note that this bit only controls SERR messaging for the Device 0.
Device 1 has its own SERRE bits to control error reporting for error
conditions occurring in that device. The control bits are used in a
logical OR manner to enable the SERR DMI message mechanism.
7
RO
0b
Address/Data Stepping Enable (ADSTEP): Address/data stepping
is not implemented in the GMCH, and this bit is hardwired to 0.
6
RW
0b
Parity Error Enable (PERRE): This bit controls whether or not the
Master Data Parity Error bit in the PCI Status register can bet set.
0= Master Data Parity Error bit in PCI Status register can NOT be set.
1 = Master Data Parity Error bit in PCI Status register CAN be set.
Datasheet
5
RO
0b
VGA Palette Snoop Enable (VGASNOOP): The GMCH does not
implement this bit and it is hardwired to a 0.
4
RO
0b
Memory Write and Invalidate Enable (MWIE): The GMCH will
never issue memory write and invalidate commands. This bit is
therefore hardwired to 0.
3
RO
0b
Reserved
2
RO
1b
Bus Master Enable (BME): The GMCH is always enabled as a master
on the backbone. This bit is hardwired to a 1.
1
RO
1b
Memory Access Enable (MAE): The GMCH always allows access to
main memory. This bit is not implemented and is hardwired to 1.
0
RO
0b
I/O Access Enable (IOAE): This bit is not implemented in the GMCH
and is hardwired to a 0.
81
DRAM Controller Registers (D0:F0)
5.1.4
PCISTS—PCI Status
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/PCI
6–7h
0090h
RWC, RO
16 bits
This status register reports the occurrence of error events on Device 0's PCI interface.
Since the GMCH Device 0 does not physically reside on PCI_A many of the bits are not
implemented.
Bit
Access &
Default
15
RWC
0b
Detected Parity Error (DPE):
RWC
0b
Signaled System Error (SSE): Software clears this bit by writing a 1
to it.
14
Description
1= Device received a Poisoned TLP.
1= The GMCH Device 0 generated a SERR message over DMI for any
enabled Device 0 error condition. Device 0 error conditions are
enabled in the PCICMD, ERRCMD, and DMIUEMSK registers. Device
0 error flags are read/reset from the PCISTS, ERRSTS, or DMIUEST
registers.
13
RWC
0b
Received Master Abort Status (RMAS): Software clears this bit by
writing a 1 to it.
1 = GMCH generated a DMI request that receives an Unsupported
Request completion packet.
12
RWC
0b
Received Target Abort Status (RTAS): Software clears this bit by
writing a 1 to it.
1 = GMCH generated a DMI request that receives a Completer Abort
completion packet.
11
RO
0b
Signaled Target Abort Status (STAS): The GMCH will not generate
a Target Abort DMI completion packet or Special Cycle. This bit is not
implemented in the GMCH and is hardwired to a 0.
10:9
RO
00b
DEVSEL Timing (DEVT): These bits are hardwired to "00". Writes to
these bit positions have no affect. Device 0 does not physically connect
to PCI_A. These bits are set to "00" (fast decode) so that optimum
DEVSEL timing for PCI_A is not limited by the GMCH.
8
RWC
0b
Master Data Parity Error Detected (DPD):
1 = This bit is set when DMI received a Poisoned completion from the
ICH.
NOTE: This bit can only be set when the Parity Error Enable bit in the
PCI Command register is set.
7
82
RO
1b
Fast Back-to-Back (FB2B): This bit is hardwired to 1. Device 0 does
not physically connect to PCI_A. This bit is set to 1 (indicating fast
back-to-back capability) so that the optimum setting for PCI_A is not
limited by the GMCH.
Datasheet
DRAM Controller Registers (D0:F0)
5.1.5
Bit
Access &
Default
Description
6
RO
0b
Reserved
5
RO
0b
66 MHz Capable: Does not apply to PCI Express. Hardwired to 0.
4
RO
1b
Capability List (CLIST): This bit is hardwired to 1 to indicate to the
configuration software that this device/function implements a list of
new capabilities. A list of new capabilities is accessed via register
CAPPTR at configuration address offset 34h. Register CAPPTR contains
an offset pointing to the start address within configuration space of
this device where the Capability Identification register resides.
3:0
RO
0h
Reserved
RID—Revision Identification
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/PCI
8h
00h
RO
8 bits
This register contains the revision number of the GMCH Device 0. These bits are read
only and writes to this register have no effect.
Datasheet
Bit
Access &
Default
7:0
RO
00h
Description
Revision Identification Number (RID): This is an 8-bit value that
indicates the revision identification number for the GMCH Device 0.
Refer to the Intel® G35 Express Chipset Specification Update for the
value of the Revision ID register.
83
DRAM Controller Registers (D0:F0)
5.1.6
CC—Class Code
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/PCI
09–0Bh
060000h
RO
24 bits
This register identifies the basic function of the device, a more specific sub-class, and
a register-specific programming interface.
Bit
Access &
Default
23:16
RO
06h
Description
Base Class Code (BCC): This is an 8-bit value that indicates the
base class code for the GMCH.
06h = Bridge device.
15:8
RO
00h
Sub-Class Code (SUBCC): This is an 8-bit value that indicates the
category of Bridge into which the GMCH falls.
00h = Host Bridge.
7:0
5.1.7
RO
00h
Programming Interface (PI): This is an 8-bit value that indicates
the programming interface of this device. This value does not specify
a particular register set layout and provides no practical use for this
device.
MLT—Master Latency Timer
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/PCI
0Dh
00h
RO
8 bits
Device 0 in the GMCH is not a PCI master. Therefore this register is not implemented.
84
Bit
Access &
Default
7:0
RO
00h
Description
Reserved
Datasheet
DRAM Controller Registers (D0:F0)
5.1.8
HDR—Header Type
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/PCI
Eh
00h
RO
8 bits
This register identifies the header layout of the configuration space. No physical
register exists at this location.
5.1.9
Bit
Access &
Default
7:0
RO
00h
Description
PCI Header (HDR): This field always returns 0 to indicate that the
GMCH is a single function device with standard header layout. Reads
and writes to this location have no effect.
SVID—Subsystem Vendor Identification
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/PCI
2C–2Dh
0000h
RWO
16 bits
This value is used to identify the vendor of the subsystem.
5.1.10
Bit
Access &
Default
Description
15:0
RWO
0000h
Subsystem Vendor ID (SUBVID): This field should be programmed
during boot-up to indicate the vendor of the system board. After it has
been written once, it becomes read only.
SID—Subsystem Identification
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/PCI
2E–2Fh
0000h
RWO
16 bits
This value is used to identify a particular subsystem.
Datasheet
Bit
Access &
Default
15:0
RWO
0000h
Description
Subsystem ID (SUBID): This field should be programmed during
BIOS initialization. After it has been written once, it becomes read
only.
85
DRAM Controller Registers (D0:F0)
5.1.11
CAPPTR—Capabilities Pointer
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/PCI
34h
E0h
RO
8 bits
The CAPPTR provides the offset that is the pointer to the location of the first device
capability in the capability list.
5.1.12
Bit
Access &
Default
7:0
RO
E0h
Description
Capabilities Pointer (CAPPTR): Pointer to the offset of the first
capability ID register block. In this case the first capability is the
product-specific Capability Identifier (CAPID0).
PXPEPBAR—PCI Express* Egress Port Base Address
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/PCI
40–47h
0000000000000000h
RW, RO
64 bits
This is the base address for the PCI Express Egress Port MMIO Configuration space.
There is no physical memory within this 4KB window that can be addressed. The 4 KB
reserved by this register does not alias to any PCI 2.3 compliant memory mapped
space. On reset, the Egress port MMIO configuration space is disabled and must be
enabled by writing a 1 to PXPEPBAREN [Dev 0, offset 40h, bit 0].
Bit
Access &
Default
63:36
RO
0000000h
35:12
RW
000000h
11:1
RO
000h
0
RW
0b
Description
Reserved
PCI Express Egress Port MMIO Base Address (PXPEPBAR): This
field corresponds to bits 35:12 of the base address PCI Express
Egress Port MMIO configuration space. BIOS will program this register
resulting in a base address for a 4 KB block of contiguous memory
address space. This register ensures that a naturally aligned 4 KB
space is allocated within the first 64 GB of addressable memory
space. System Software uses this base address to program the GMCH
MMIO register set.
Reserved
PXPEPBAR Enable (PXPEPBAREN):
0 = PXPEPBAR is disabled and does not claim any memory
1 = PXPEPBAR memory mapped accesses are claimed and decoded
appropriately
86
Datasheet
DRAM Controller Registers (D0:F0)
5.1.13
MCHBAR—GMCH Memory Mapped Register Range Base
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/PCI
48–4Fh
0000000000000000h
RW/L, RO
64 bits
This is the base address for the GMCH Memory Mapped Configuration space. There is
no physical memory within this 16 KB window that can be addressed. The 16 KB
reserved by this register does not alias to any PCI 2.3 compliant memory mapped
space. On reset, the GMCH MMIO Memory Mapped Configuration space is disabled and
must be enabled by writing a 1 to MCHBAREN [Dev 0, offset48h, bit 0].
Bit
Access &
Default
63:36
RO
0000000h
35:14
RW
000000h
13:1
RO
0000h
0
RW
0b
Description
Reserved
GMCH Memory Mapped Base Address (MCHBAR): This field
corresponds to bits 35:14 of the base address GMCH Memory Mapped
configuration space. BIOS will program this register resulting in a base
address for a 16 KB block of contiguous memory address space. This
register ensures that a naturally aligned 16 KB space is allocated.
System Software uses this base address to program the GMCH Memory
Mapped register set.
Reserved
MCHBAR Enable (MCHBAREN):
0= MCHBAR is disabled and does not claim any memory
1 = MCHBAR memory mapped accesses are claimed and decoded
appropriately
Datasheet
87
DRAM Controller Registers (D0:F0)
5.1.14
GGC—GMCH Graphics Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Bit
Access &
Default
15:7
RO
00h
6:4
RW/L
011b
0/0/0/PCI
52–53h
0030h
RO, RW/L
16 bits
Description
Reserved
Graphics Mode Select (GMS): This field is used to select the
amount of Main Memory that is pre-allocated to support the Internal
Graphics device in VGA (non-linear) and Native (linear) modes. The
BIOS ensures that memory is pre-allocated only when Internal
graphics is enabled.
000 =
No memory pre-allocated. Device 2 (IGD) does not claim
VGA cycles (Memory and I/O), and the Sub-Class Code field
within Device 2, function 0, Class Code register is 80h.
001 =
DVMT (UMA) mode, 1 MB of memory pre-allocated for
frame buffer.
010 =
Reserved
011 =
DVMT (UMA) mode, 8 MB of memory pre-allocated for
frame buffer.
100 =
Reserved
101 =
Reserved
110 =
Reserved
111 =
Reserved
Note:
This register is locked and becomes Read Only when the
D_LCK bit in the SMRAM register is set.
BIOS Requirement: BIOS must not set this field to 000 if IVD (bit 1
of this register) is 0.
3:2
RO
00b
1
RW/L
0b
Reserved
IGD VGA Disable (IVD):
0 = Enable. Device 2 (IGD) claims VGA memory and I/O cycles, the
Sub-Class Code within Device 2 Class Code register is 00h.
1 = Disable. Device 2 (IGD) does not claim VGA cycles (Memory and
I/O), and the Sub-Class Code field within Device 2, function 0
Class Code register is 80h.
0
88
RO
0b
Reserved
Datasheet
DRAM Controller Registers (D0:F0)
5.1.15
DEVEN—Device Enable
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/PCI
54–57h
000003DBh
RO, RW/L
32 bits
This register allows for enabling/disabling of PCI devices and functions that are within
the GMCH.
Bit
Access &
Default
31:10
RO
00000h
9
RW/L
1b
Description
Reserved
ME Function 3 (D3F3EN):
0 = Bus 0 Device 3 Function 3 is disabled and hidden
1 = Bus 0 Device 3 Function 3 is enabled and visible
If Device 3, Function 0 is disabled and hidden, then Device 3, Function
3 is also disabled and hidden independent of the state of this bit.
8
RW/L
1b
ME Function 2 (D3F2EN):
0 = Bus 0 Device 3 Function 2 is disabled and hidden
1 = Bus 0 Device 3 Function 2 is enabled and visible
If Device 3, Function 0 is disabled and hidden, then Device 3, Function
2 is also disabled and hidden independent of the state of this bit.
7
RO
1b
6
RW/L
1b
Reserved
ME Function 0 (D3F0EN):
0 = Bus 0, Device 3, Function 0 is disabled and hidden
1 = Bus 0, Device 3, Function 0 is enabled and visible.
If this GMCH does not have ME capability (CAPID0[57] = 1), then
Device 3, Function 0 is disabled and hidden independent of the state of
this bit.
5
RO
0b
4
RW/L
1b
Reserved
Internal Graphics Engine Function 1 (D2F1EN):
0 = Bus 0, Device 2, Function 1 is disabled and hidden
1 = Bus 0, Device 2, Function 1 is enabled and visible
If Device 2, Function 0 is disabled and hidden, then Device 2, Function
1 is also disabled and hidden independent of the state of this bit.
3
RW/L
1b
Internal Graphics Engine Function 0 (D2F0EN):
0 = Bus 0, Device 2, Function 0 is disabled and hidden
1 = Bus 0, Device 2, Function 0 is enabled and visible
Datasheet
89
DRAM Controller Registers (D0:F0)
Bit
Access &
Default
2
RO
0b
1
RW/L
1b
Description
Reserved
PCI Express Port (D1EN):
0 = Bus 0, Device 1, Function 0 is disabled and hidden.
1 = Bus 0, Device 1, Function 0 is enabled and visible.
0
5.1.16
RO
1b
Host Bridge (D0EN): Bus 0, Device 0, Function 0 may not be
disabled and is therefore hardwired to 1.
PCIEXBAR—PCI Express* Register Range Base Address
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/PCI
60–67h
00000000E0000000h
RO, RW/L, RW/L/K
64 bits
This is the base address for the PCI Express configuration space. This window of
addresses contains the 4 KB of configuration space for each PCI Express device that
can potentially be part of the PCI Express Hierarchy associated with the GMCH. There
is not actual physical memory within this window of up to 256 MB that can be
addressed. The actual length is determined by a field in this register. Each PCI Express
Hierarchy requires a PCI Express BASE register. The GMCH supports one PCI Express
hierarchy. The region reserved by this register does not alias to any PCI 2.3 compliant
memory mapped space. For example, MCHBAR reserves a 16 KB space and CHAPADR
reserves a 4 KB space both outside of PCIEXBAR space. They cannot be overlayed on
the space reserved by PCIEXBAR for devices 0.
On reset, this register is disabled and must be enabled by writing a 1 to the enable
field in this register. This base address shall be assigned on a boundary consistent
with the number of buses (defined by the Length field in this register), above TOLUD
and still within 64 bit addressable memory space. All other bits not decoded are read
only 0. The PCI Express Base Address cannot be less than the maximum address
written to the Top of physical memory register (TOLUD). Software must ensure that
these ranges do not overlap with known ranges located above TOLUD. Software must
ensure that the sum of Length of enhanced configuration region + TOLUD + (other
known ranges reserved above TOLUD) is not greater than the 36-bit addressable limit
of 64 GB. In general system implementation and number of PCI/PCI Express/PCI-X
buses supported in the hierarchy will dictate the length of the region.
90
Bit
Access &
Default
63:36
RO
0000000h
Description
Reserved
Datasheet
DRAM Controller Registers (D0:F0)
Bit
Access &
Default
Description
35:28
RW/L
0Eh
PCI Express Base Address (PCIEXBAR): This field corresponds to
bits 35:28 of the base address for PCI Express enhanced configuration
space. BIOS will program this register resulting in a base address for
a contiguous memory address space; size is defined by bits 2:1 of this
register.
This Base address shall be assigned on a boundary consistent with the
number of buses (defined by the Length field in this register) above
TOLUD and still within 64-bit addressable memory space. The address
bits decoded depend on the length of the region defined by this
register.
The address used to access the PCI Express configuration space for a
specific device can be determined as follows:
PCI Express Base Address + Bus Number * 1 MB + Device Number *
32 KB + Function Number * 4 KB
The address used to access the PCI Express configuration space for
Device 1 in this component would be PCI Express Base Address + 0 *
1 MB + 1 * 32 KB + 0 * 4 KB = PCI Express Base Address + 32 KB.
Remember that this address is the beginning of the 4 KB space that
contains both the PCI compatible configuration space and the PCI
Express extended configuration space.
27
RW/L
0b
128 MB Base Address Mask (128ADMSK): This bit is either part of
the PCI Express Base Address (R/W) or part of the Address Mask (RO,
read 0b), depending on the value of bits 2:1 in this register.
26
RW/L
0b
64 MB Base Address Mask (64ADMSK): This bit is either part of
the PCI Express Base Address (R/W) or part of the Address Mask (RO,
read 0b), depending on the value of bits 2:1 in this register.
25:3
RO
000000h
2:1
RW/K
00b
Reserved
Length (LENGTH): This Field describes the length of this region.
Enhanced Configuration Space Region/Buses Decoded
00 = 256 MB (buses 0–255). Bits 31:28 are decoded in the PCI
Express Base Address Field
01 = 128 MB (Buses 0–127). Bits 31:27 are decoded in the PCI
Express Base Address Field.
10 = 64 MB (Buses 0–63). Bits 31:26 are decoded in the PCI Express
Base Address Field.
11 = Reserved
0
RW
0b
PCIEXBAR Enable (PCIEXBAREN):
0 = The PCIEXBAR register is disabled. Memory read and write
transactions proceed as if there were no PCIEXBAR register.
PCIEXBAR bits 35:26 are R/W with no functionality behind
them.
1 = The PCIEXBAR register is enabled. Memory read and write
transactions whose address bits 31:26 match PCIEXBAR will
be translated to configuration reads and writes within the
GMCH.
Datasheet
91
DRAM Controller Registers (D0:F0)
5.1.17
DMIBAR—Root Complex Register Range Base Address
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/PCI
68–6Fh
0000000000000000h
RO, RW
64 bits
This is the base address for the Root Complex configuration space. This window of
addresses contains the Root Complex Register set for the PCI Express Hierarchy
associated with the GMCH. There is no physical memory within this 4 KB window that
can be addressed. The 4 KB reserved by this register does not alias to any PCI 2.3
compliant memory mapped space. On reset, the Root Complex configuration space is
disabled and must be enabled by writing a 1 to DMIBAREN [Dev 0, offset 68h, bit 0].
Bit
Access
63:36
RO
0000000h
35:12
RW
000000h
11:1
RO
000h
0
RW
0b
Description
Reserved
DMI Base Address (DMIBAR): This field corresponds to bits 35:12
of the base address DMI configuration space. BIOS will program this
register resulting in a base address for a 4KB block of contiguous
memory address space. This register ensures that a naturally aligned
4 KB space is allocated within the first 64 GB of addressable memory
space. System Software uses this base address to program the DMI
register set.
Reserved
DMIBAR Enable (DMIBAREN):
0 = DMIBAR is disabled and does not claim any memory
1 = DMIBAR memory mapped accesses are claimed and decoded
appropriately
92
Datasheet
DRAM Controller Registers (D0:F0)
5.1.18
PAM0—Programmable Attribute Map 0
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/PCI
90h
00h
RO, RW
8 bits
This register controls the read, write, and shadowing attributes of the BIOS area from
0F0000h–0FFFFFh. The GMCH allows programmable memory attributes on 13 Legacy
memory segments of various sizes in the 768 KB to 1 MB address range. Seven
Programmable Attribute Map (PAM) Registers are used to support these features.
Cacheability of these areas is controlled via the MTRR registers in the P6 processor.
Two bits are used to specify memory attributes for each memory segment. These bits
apply to both host accesses and PCI initiator accesses to the PAM areas. These
attributes are:
RE – Read Enable.
When RE = 1, the processor read accesses to the
corresponding memory segment are claimed by the GMCH and
directed to main memory. Conversely, when RE = 0, the host
read accesses are directed to PCI_A.
WE – Write Enable.
When WE = 1, the host write accesses to the corresponding
memory segment are claimed by the GMCH and directed to
main memory. Conversely, when WE = 0, the host write
accesses are directed to PCI_A.
The RE and WE attributes permit a memory segment to be Read Only, Write Only,
Read/Write, or disabled. For example, if a memory segment has RE = 1 and WE = 0,
the segment is Read Only. Each PAM Register controls two regions, typically 16 KB in
size.
Note that the GMCH may hang if a PCI Express Graphics Attach or DMI originated
access to Read Disabled or Write Disabled PAM segments occur (due to a possible IWB
to non-DRAM).
For these reasons the following critical restriction is placed on the programming of the
PAM regions: At the time that a DMI or PCI Express Graphics Attach accesses to the
PAM region may occur, the targeted PAM segment must be programmed to be both
readable and writeable.
Datasheet
93
DRAM Controller Registers (D0:F0)
Bit
Access &
Default
Description
7:6
RO
00b
Reserved
5:4
RW
00b
0F0000h–0FFFFFh Attribute (HIENABLE): This field controls the
steering of read and write cycles that address the BIOS area from
0F0000h to 0FFFFFh.
00 = DRAM Disabled: All accesses are directed to DMI.
01 = Read Only: All reads are sent to DRAM. All writes are forwarded to
DMI.
10 = Write Only: All writes are sent to DRAM. Reads are serviced by
DMI.
11 = Normal DRAM Operation: All reads and writes are serviced by
DRAM.
3:0
94
RO
0h
Reserved
Datasheet
DRAM Controller Registers (D0:F0)
5.1.19
PAM1—Programmable Attribute Map 1
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/PCI
91h
00h
RO, RW
8 bits
This register controls the read, write, and shadowing attributes of the BIOS areas from
0C0000h–0C7FFFh.
Bit
Access &
Default
Description
7:6
RO
00b
Reserved
5:4
RW
00b
0C4000h–0C7FFFh Attribute (HIENABLE): This field controls the
steering of read and write cycles that address the BIOS area from
0C4000 to 0C7FFF.
00 = DRAM Disabled: Accesses are directed to DMI.
01 = Read Only: All reads are serviced by DRAM. All writes are
forwarded to DMI.
10 = Write Only: All writes are sent to DRAM. Reads are serviced by
DMI.
11 = Normal DRAM Operation: All reads and writes are serviced by
DRAM.
3:2
RO
00b
Reserved
1:0
RW
00b
0C0000h–0C3FFFh Attribute (LOENABLE): This field controls the
steering of read and write cycles that address the BIOS area from
0C0000h to 0C3FFFh.
00 = DRAM Disabled: Accesses are directed to DMI.
01 = Read Only: All reads are serviced by DRAM. All writes are
forwarded to DMI.
10 = Write Only: All writes are sent to DRAM. Reads are serviced by
DMI.
11 = Normal DRAM Operation: All reads and writes are serviced by
DRAM.
Datasheet
95
DRAM Controller Registers (D0:F0)
5.1.20
PAM2—Programmable Attribute Map 2
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/PCI
92h
00h
RO, RW
8 bits
This register controls the read, write, and shadowing attributes of the BIOS areas from
0C8000h–0CFFFFh.
Bit
Access &
Default
Description
7:6
RO
00b
Reserved
5:4
RW
00b
0CC000h–0CFFFFh Attribute (HIENABLE):
00 = DRAM Disabled: Accesses are directed to DMI.
01 = Read Only: All reads are serviced by DRAM. All writes are
forwarded to DMI.
10 = Write Only: All writes are sent to DRAM. Reads are serviced by
DMI.
11 = Normal DRAM Operation: All reads and writes are serviced by
DRAM.
3:2
RO
00b
Reserved
1:0
RW
00b
0C8000h–0CBFFFh Attribute (LOENABLE): This field controls the
steering of read and write cycles that address the BIOS area from
0C8000h to 0CBFFFh.
00 = DRAM Disabled: Accesses are directed to DMI.
01 = Read Only: All reads are serviced by DRAM. All writes are
forwarded to DMI.
10 = Write Only: All writes are sent to DRAM. Reads are serviced by
DMI.
11 = Normal DRAM Operation: All reads and writes are serviced by
DRAM.
96
Datasheet
DRAM Controller Registers (D0:F0)
5.1.21
PAM3—Programmable Attribute Map 3
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/PCI
93h
00h
RO, RW
8 bits
This register controls the read, write, and shadowing attributes of the BIOS areas from
0D0000h–0D7FFFh.
Bit
Access &
Default
Description
7:6
RO
00b
Reserved
5:4
RW
00b
0D4000h–0D7FFFh Attribute (HIENABLE): This field controls the
steering of read and write cycles that address the BIOS area from
0D4000h to 0D7FFFh.
00 = DRAM Disabled: Accesses are directed to DMI.
01 = Read Only: All reads are serviced by DRAM. All writes are
forwarded to DMI.
10 = Write Only: All writes are sent to DRAM. Reads are serviced by
DMI.
11 = Normal DRAM Operation: All reads and writes are serviced by
DRAM.
3:2
RO
00b
Reserved
1:0
RW
00b
0D0000–0D3FFF Attribute (LOENABLE): This field controls the
steering of read and write cycles that address the BIOS area from
0D0000h to 0D3FFFh.
00 = DRAM Disabled: Accesses are directed to DMI.
01 = Read Only: All reads are serviced by DRAM. All writes are
forwarded to DMI.
10 = Write Only: All writes are sent to DRAM. Reads are serviced by
DMI.
11 = Normal DRAM Operation: All reads and writes are serviced by
DRAM.
Datasheet
97
DRAM Controller Registers (D0:F0)
5.1.22
PAM4—Programmable Attribute Map 4
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/PCI
94h
00h
RO, RW
8 bits
This register controls the read, write, and shadowing attributes of the BIOS areas from
0D8000h–0DFFFFh.
Bit
Access &
Default
Description
7:6
RO
00b
Reserved
5:4
RW
00b
0DC000h–0DFFFFh Attribute (HIENABLE): This field controls the
steering of read and write cycles that address the BIOS area from
0DC000h to 0DFFFFh.
00 = DRAM Disabled: Accesses are directed to DMI.
01 = Read Only: All reads are serviced by DRAM. All writes are
forwarded to DMI.
10 = Write Only: All writes are sent to DRAM. Reads are serviced by
DMI.
11 = Normal DRAM Operation: All reads and writes are serviced by
DRAM.
3:2
RO
00b
Reserved
1:0
RW
00b
0D8000h–0DBFFFh Attribute (LOENABLE): This field controls the
steering of read and write cycles that address the BIOS area from
0D8000h to 0DBFFFh.
00 = DRAM Disabled: Accesses are directed to DMI.
01 = Read Only: All reads are serviced by DRAM. All writes are
forwarded to DMI.
10 = Write Only: All writes are sent to DRAM. Reads are serviced by
DMI.
11 = Normal DRAM Operation: All reads and writes are serviced by
DRAM.
98
Datasheet
DRAM Controller Registers (D0:F0)
5.1.23
PAM5—Programmable Attribute Map 5
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/PCI
95h
00h
RO, RW
8 bits
This register controls the read, write, and shadowing attributes of the BIOS areas from
0E0000h–0E7FFFh.
Bit
Access &
Default
Description
7:6
RO
00b
Reserved
5:4
RW
00b
0E4000h–0E7FFFh Attribute (HIENABLE): This field controls the
steering of read and write cycles that address the BIOS area from
0E4000h to 0E7FFFh.
00 = DRAM Disabled: Accesses are directed to DMI.
01 = Read Only: All reads are serviced by DRAM. All writes are
forwarded to DMI.
10 = Write Only: All writes are sent to DRAM. Reads are serviced by
DMI.
11 = Normal DRAM Operation: All reads and writes are serviced by
DRAM.
3:2
RO
00b
Reserved
1:0
RW
00b
0E0000h–0E3FFFh Attribute (LOENABLE): This field controls the
steering of read and write cycles that address the BIOS area from
0E0000h to 0E3FFFh.
00 = DRAM Disabled: Accesses are directed to DMI.
01 = Read Only: All reads are serviced by DRAM. All writes are
forwarded to DMI.
10 = Write Only: All writes are sent to DRAM. Reads are serviced by
DMI.
11 = Normal DRAM Operation: All reads and writes are serviced by
DRAM.
Datasheet
99
DRAM Controller Registers (D0:F0)
5.1.24
PAM6—Programmable Attribute Map 6
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/PCI
96h
00h
RO, RW
8 bits
This register controls the read, write, and shadowing attributes of the BIOS areas from
0E8000h–0EFFFFh.
Bit
Access &
Default
Description
7:6
RO
00b
Reserved
5:4
RW
00b
0EC000h–0EFFFFh Attribute (HIENABLE): This field controls the
steering of read and write cycles that address the BIOS area from
0E4000h to 0E7FFFh.
00 = DRAM Disabled: Accesses are directed to DMI.
01 = Read Only: All reads are serviced by DRAM. All writes are
forwarded to DMI.
10 = Write Only: All writes are sent to DRAM. Reads are serviced by
DMI.
11 = Normal DRAM Operation: All reads and writes are serviced by
DRAM.
3:2
RO
00b
Reserved
1:0
RW
00b
0E8000h–0EBFFFh Attribute (LOENABLE): This field controls the
steering of read and write cycles that address the BIOS area from
0E0000h to 0E3FFFh.
00 = DRAM Disabled: Accesses are directed to DMI.
01 = Read Only: All reads are serviced by DRAM. All writes are
forwarded to DMI.
10 = Write Only: All writes are sent to DRAM. Reads are serviced by
DMI.
11 = Normal DRAM Operation: All reads and writes are serviced by
DRAM.
100
Datasheet
DRAM Controller Registers (D0:F0)
5.1.25
LAC—Legacy Access Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/PCI
97h
00h
RW, RO, RW
8 bits
This 8-bit register controls a fixed DRAM hole from 15–16 MB.
Bit
Access &
Default
7
RW/L
0b
Description
Hole Enable (HEN): This field enables a memory hole in DRAM space.
The DRAM that lies "behind" this space is not remapped.
0 = No memory hole.
1 = Memory hole from 15 MB to 16 MB.
6:1
RO
00000b
0
RW
0b
Reserved
MDA Present (MDAP): This bit works with the VGA Enable bits in the
BCTRL register of Device 1 to control the routing of processor initiated
transactions targeting MDA compatible I/O and memory address ranges.
This bit should not be set if device 1's VGA Enable bit is not set.
If device 1's VGA enable bit is not set, then accesses to IO address
range x3BCh–x3BFh are forwarded to DMI.
If the VGA enable bit is set and MDA is not present, then accesses to IO
address range x3BCh–x3BFh are forwarded to PCI Express if the
address is within the corresponding IOBASE and IOLIMIT, otherwise
they are forwarded to DMI.
MDA resources are defined as the following:
Memory:
0B0000h – 0B7FFFh
I/O:
3B4h, 3B5h, 3B8h, 3B9h, 3BAh, 3BFh, (including ISA
address aliases, A[15:10] are not used in decode)
Any I/O reference that includes the I/O locations listed above, or their
aliases, will be forwarded to the DMI even if the reference includes I/O
locations not listed above.
The following table shows the behavior for all combinations of MDA and
VGA:
VGAEN
0
MDAP
0
Description
All References to MDA and VGA space are routed to
DMI
0
1
Invalid combination
1
0
All VGA and MDA references are routed to PCI
Express Graphics Attach.
1
1
All VGA references are routed to PCI Express
Graphics Attach. MDA references are routed to DMI.
VGA and MDA memory cycles can only be routed across the PEG when
MAE (PCICMD1[1]) is set. VGA and MDA I/O cycles can only be routed
across the PEG if IOAE (PCICMD1[0]) is set.
Datasheet
101
DRAM Controller Registers (D0:F0)
5.1.26
REMAPBASE—Remap Base Address Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Bit
Access &
Default
15:10
RO
000000b
9:0
RW/L
3FFh
0/0/0/PCI
98–99h
03FFh
RO, RW
16 bits
Description
Reserved
Remap Base Address [35:26] (REMAPBASE): The value in this
register defines the lower boundary of the Remap window. The Remap
window is inclusive of this address. In the decoder A[25:0] of the
Remap Base Address are assumed to be 0s. Thus, the bottom of the
defined memory range will be aligned to a 64 MB boundary.
When the value in this register is greater than the value programmed
into the Remap Limit register, the Remap window is disabled.
Note: Bit 0 (Address Bit 26) must be a 0.
5.1.27
REMAPLIMIT—Remap Limit Address Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Bit
Access &
Default
15:10
RO
000000b
9:0
RW/L
000h
0/0/0/PCI
9A–9Bh
0000h
RO, RW
16 bits
Description
Reserved
Remap Limit Address [35:26] (REMAPLMT): The value in this
register defines the upper boundary of the Remap window. The Remap
window is inclusive of this address. In the decoder A[25:0] of the
remap limit address are assumed to be Fhs. Thus the top of the
defined range will be one less than a 64 MB boundary.
When the value in this register is less than the value programmed into
the Remap Base register, the Remap window is disabled.
Note: Bit 0 (Address Bit 26) must be a 0.
102
Datasheet
DRAM Controller Registers (D0:F0)
5.1.28
SMRAM—System Management RAM Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/PCI
9Dh
02h
RO, RW/L, RW, RW/L/K
8 bits
The SMRAMC register controls how accesses to Compatible and Extended SMRAM
spaces are treated. The Open, Close, and Lock bits function only when G_SMRAME bit
is set to a 1. Also, the OPEN bit must be reset before the LOCK bit is set.
Datasheet
Bit
Access &
Default
Description
7
RO
0b
6
RW/L
0b
SMM Space Open (D_OPEN): When D_OPEN=1 and D_LCK=0, the
SMM space DRAM is made visible even when SMM decode is not
active. This is intended to help BIOS initialize SMM space. Software
should ensure that D_OPEN=1 and D_CLS=1 are not set at the same
time.
5
RW
0b
SMM Space Closed (D_CLS): When D_CLS = 1 SMM space DRAM is
not accessible to data references, even if SMM decode is active. Code
references may still access SMM space DRAM. This will allow SMM
software to reference through SMM space to update the display even
when SMM is mapped over the VGA range. Software should ensure
that D_OPEN=1 and D_CLS=1 are not set at the same time.
4
RW/L/K
0b
SMM Space Locked (D_LCK): When D_LCK is set to 1 then D_OPEN
is reset to 0 and D_LCK, D_OPEN, C_BASE_SEG, H_SMRAM_EN,
TSEG_SZ and TSEG_EN become read only. D_LCK can be set to 1 via
a normal configuration space write but can only be cleared by a Full
Reset. The combination of D_LCK and D_OPEN provide convenience
with security. The BIOS can use the D_OPEN function to initialize SMM
space and then use D_LCK to "lock down" SMM space in the future so
that no application software (or BIOS itself) can violate the integrity
of SMM space, even if the program has knowledge of the D_OPEN
function.
3
RW/L
0b
Global SMRAM Enable (G_SMRAME): If set to a 1, then Compatible
SMRAM functions are enabled, providing 128 KB of DRAM accessible
at the A0000h address while in SMM (ADSB with SMM decode). To
enable Extended SMRAM function this bit has be set to 1. Refer to the
section on SMM for more details. Once D_LCK is set, this bit becomes
read only.
2:0
RO
0b
Compatible SMM Space Base Segment (C_BASE_SEG): This field
indicates the location of SMM space. SMM DRAM is not remapped. It is
simply made visible if the conditions are right to access SMM space,
otherwise the access is forwarded to DMI. Since the GMCH supports
only the SMM space between A0000 and BFFFF, this field is hardwired
to 010.
Reserved
103
DRAM Controller Registers (D0:F0)
5.1.29
ESMRAMC—Extended System Management RAM Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/PCI
9Eh
38h
RW/L, RWC, RO
8 bits
The Extended SMRAM register controls the configuration of Extended SMRAM space.
The Extended SMRAM (E_SMRAM) memory provides a write-back cacheable SMRAM
memory space that is above 1 MB.
Bit
Access &
Default
Description
7
RW/L
0b
Enable High SMRAM (H_SMRAME): This bit controls the SMM
memory space location (i.e., above 1 MB or below 1 MB) When
G_SMRAME is 1 and H_SMRAME is set to 1, the high SMRAM memory
space is enabled. SMRAM accesses within the range 0FEDA0000h to
0FEDBFFFFh are remapped to DRAM addresses within the range
000A0000h to 000BFFFFh. Once D_LCK has been set, this bit becomes
read only.
6
RWC
0b
Invalid SMRAM Access (E_SMERR): This bit is set when processor
has accessed the defined memory ranges in Extended SMRAM (High
Memory and T-segment) while not in SMM space and with the D-OPEN
bit = 0. It is software's responsibility to clear this bit. The software
must write a 1 to this bit to clear it.
5
RO
1b
SMRAM Cacheable (SM_CACHE): This bit is forced to 1 by the
GMCH.
4
RO
1b
L1 Cache Enable for SMRAM (SM_L1): This bit is forced to 1 by the
GMCH.
3
RO
1b
L2 Cache Enable for SMRAM (SM_L2): This bit is forced to 1 by the
GMCH.
2:1
RW/L
00b
TSEG Size (TSEG_SZ): Selects the size of the TSEG memory block if
enabled. Memory from the top of DRAM space is partitioned away so
that it may only be accessed by the processor interface and only then
when the SMM bit is set in the request packet. Non-SMM accesses to
this memory region are sent to DMI when the TSEG memory block is
enabled.
If Graphics stolen memory is placed above 4 GB, TSEG base is
determined as if graphics stoles memory size is 0.
00 = 1 MB TSEG. (TOLUD – GTT Graphics Memory Size – Graphics
Stolen Memory Size – 1 MB) to (TOLUD – GTT Graphics Memory
Size – Graphics Stolen Memory Size).
01 = 2 MB TSEG. (TOLUD – GTT Graphics Memory Size – Graphics
Stolen Memory Size – 2 MB) to (TOLUD – GTT Graphics Memory
Size – Graphics Stolen Memory Size).
10 = 8 MB TSEG. (TOLUD – GTT Graphics Memory Size – Graphics
Stolen Memory Size – 8 MB) to (TOLUD – GTT Graphics Memory
Size – Graphics Stolen Memory Size).
11 = Reserved.
Once D_LCK has been set, these bits becomes read only.
104
Datasheet
DRAM Controller Registers (D0:F0)
5.1.30
Bit
Access &
Default
Description
0
RW/L
0b
TSEG Enable (T_EN): Enabling of SMRAM memory for Extended
SMRAM space only. When G_SMRAME = 1 and TSEG_EN = 1, the TSEG
is enabled to appear in the appropriate physical address space. Note
that once D_LCK is set, this bit becomes read only.
TOM—Top of Memory
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/PCI
A0–A1h
0001h
RO, RW/L
16 bits
This Register contains the size of physical memory. BIOS determines the memory size
reported to the OS using this Register.
Datasheet
Bit
Access &
Default
15:10
RO
00h
9:0
RW/L
001h
Description
Reserved
Top of Memory (TOM): This register reflects the total amount of
populated physical memory. This is NOT necessarily the highest main
memory address (holes may exist in main memory address map due
to addresses allocated for memory mapped I/O). These bits
correspond to address bits 35:26 (64 MB granularity). Bits 25:0 are
assumed to be 0.
105
DRAM Controller Registers (D0:F0)
5.1.31
TOUUD—Top of Upper Usable Dram
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/PCI
A2–A3h
0000h
RW/L
16 bits
This 16 bit register defines the Top of Upper Usable DRAM.
Configuration software must set this value to TOM minus all EP stolen memory if
reclaim is disabled. If reclaim is enabled, this value must be set to (reclaim limit + 1
byte) 64 MB aligned since reclaim limit is 64 MB aligned. Address bits 19:0 are
assumed to be 000_0000h for the purposes of address comparison. The Host interface
positively decodes an address towards DRAM if the incoming address is less than the
value programmed in this register and greater than or equal to 4 GB.
106
Bit
Access &
Default
Description
15:0
RW/L
0000h
TOUUD (TOUUD): This register contains bits 35 to 20 of an address
one byte above the maximum DRAM memory above 4 GB that is
usable by the operating system. Configuration software must set this
value to TOM minus all EP stolen memory if reclaim is disabled. If
reclaim is enabled, this value must be set to (reclaim limit + 1 byte)
64 MB aligned since reclaim limit is 64 MB aligned. Address bits 19:0
are assumed to be 000_0000h for the purposes of address
comparison. The Host interface positively decodes an address towards
DRAM if the incoming address is less than the value programmed in
this register and greater than 4 GB.
Datasheet
DRAM Controller Registers (D0:F0)
5.1.32
GBSM—Graphics Base of Stolen Memory
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/PCI
A4–ABh
0000000000000000h
RW/L, RO
64 bits
This register contains the base address of graphics data stolen DRAM memory. BIOS
determines the base of graphics data stolen memory by subtracting the graphics data
stolen memory size (PCI Device 0, offset 52, bits 6:4) from TOLUD (PCI Device 0,
offset B0h, bits 15:4).
Note: This register is locked and becomes Read Only when the D_LCK bit in the SMRAM
register is set.
Bit
Access &
Default
63:32
RO
00000000h
31:20
RW/L
000h
Description
Reserved
Graphics Base of Stolen Memory (GBSM): This register contains
bits 31:20 of the base address of stolen DRAM memory. BIOS
determines the base of graphics stolen memory by subtracting the
graphics stolen memory size (PCI Device 0, offset 52h, bits 6:4) from
TOLUD (PCI Device 0, offset B0h, bits 15:4).
Note: This register is locked and becomes Read Only when the
D_LCK bit in the SMRAM register is set.
19:0
5.1.33
RO
00000h
Reserved
TSEGMB—TSEG Memory Base
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/PCI
AC–AFh
00000000h
RW/L, RO
32 bits
This register contains the base address of TSEG DRAM memory. BIOS determines the
base of TSEG memory by subtracting the TSEG size (PCI Device 0, offset 9Eh, bits
2:1) from graphics GTT stolen base (PCI Device 0, offset A8h, bits 31:20).
Once D_LCK has been set, these bits becomes read only.
Bit
Access &
Default
Description
31:20
RW/L
000h
TESG Memory base (TSEGMB): This register contains bits 31:20
of the base address of TSEG DRAM memory. BIOS determines the
base of TSEG memory by subtracting the TSEG size (PCI Device 0,
offset 9Eh, bits 2:1) and the graphics stolen memory size (PCI
Device 0 offset 52 bits 6:4) from TOLUD (PCI Device 0 offset 9C bits
07:02).
Once D_LCK has been set, these bits becomes read only.
19:0
Datasheet
RO
00000h
Reserved
107
DRAM Controller Registers (D0:F0)
5.1.34
TOLUD—Top of Low Usable DRAM
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/PCI
B0–B1h
0010h
RW/L, RO
16 bits
This 16 bit register defines the Top of Low Usable DRAM. TSEG and Graphics Stolen
Memory (if below 4GB) are within the DRAM space defined. From the top, GMCH
optionally claims 1 to 64MBs of DRAM for internal graphics if enabled and 1 MB, 2 MB,
or 8 MB of DRAM for TSEG if enabled.
Programming Example :
C1DRB3 is set to 4 GB
TSEG is enabled and TSEG size is set to 1 MB
Internal Graphics is enabled and Graphics Mode Select set to 32 MB
BIOS knows the OS requires 1 GB of PCI space.
BIOS also knows the range from FEC0_0000h to FFFF_FFFFh is not usable by the
system. This 20 MB range at the very top of addressable memory space is lost to
APIC.
According to the above equation, TOLUD is originally calculated to:
4 GB = 1_0000_0000h
The system memory requirements are: 4 GB (max addressable space) – 1 GB (PCI
space) – 20 MB (lost memory) = 3 GB – 128 MB (minimum granularity) =
B800_0000h
Since B800_0000h (PCI and other system requirements) is less than 1_0000_0000h,
TOLUD should be programmed to B80h.
Bit
Access &
Default
15:4
RW/L
001h
Description
Top of Low Usable DRAM (TOLUD): This register contains bits
31:20 of an address one byte above the maximum DRAM memory
below 4 GB that is usable by the operating system. Address bits
31:20 programmed to 01h implies a minimum memory size of 1 MB.
Configuration software must set this value to the smaller of the
following 2 choices: maximum amount memory in the system minus
ME stolen memory plus one byte or the minimum address allocated
for PCI memory. Address bits 19:0 are assumed to be 0_0000h for
the purposes of address comparison. The Host interface positively
decodes an address towards DRAM if the incoming address is less
than the value programmed in this register.
This register must be 64 MB aligned when reclaim is enabled.
3:0
108
RO
0000b
Reserved
Datasheet
DRAM Controller Registers (D0:F0)
5.1.35
ERRSTS—Error Status
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/PCI
C8–C9h
0000h
RO, RWC/S
16 bits
This register is used to report various error conditions via the SERR DMI messaging
mechanism. An SERR DMI message is generated on a zero to one transition of any of
these flags (if enabled by the ERRCMD and PCICMD registers).
These bits are set regardless of whether or not the SERR is enabled and generated.
After the error processing is complete, the error logging mechanism can be unlocked
by clearing the appropriate status bit by software writing a 1 to it.
Bit
Access &
Default
15:13
RO
0b
12
RWC/S
0b
GMCH Software Generated Event for SMI (GSGESMI): This
indicates the source of the SMI was a Device 2 Software Event.
11
RWC/S
0b
GMCH Thermal Sensor Event for SMI/SCI/SERR (GTSE): This bit
indicates that a GMCH Thermal Sensor trip has occurred and an SMI,
SCI or SERR has been generated. The status bit is set only if a
message is sent based on Thermal event enables in Error command,
SMI command and SCI command registers. A trip point can generate
one of SMI, SCI, or SERR interrupts (two or more per event is
invalid). Multiple trip points can generate the same interrupt, if
software chooses this mode, subsequent trips may be lost. If this bit
is already set, then an interrupt message will not be sent on a new
thermal sensor event.
10
RO
0b
9
RWC/S
0b
8
RO
0b
7
RWC/S
0b
Description
Reserved
Reserved
LOCK to non-DRAM Memory Flag (LCKF):
1 = GMCH has detected a lock operation to memory space that did
not map into DRAM.
Reserved
DRAM Throttle Flag (DTF):
1 = DRAM Throttling condition occurred.
0 = Software has cleared this flag since the most recent throttling
event.
6:0
Datasheet
RO
0s
Reserved
109
DRAM Controller Registers (D0:F0)
5.1.36
ERRCMD—Error Command
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/PCI
CA–CBh
0000h
RO, RW
16 bits
This register controls the GMCH responses to various system errors. Since the GMCH
does not have an SERR# signal, SERR messages are passed from the GMCH to the
ICH over DMI.
When a bit in this register is set, a SERR message will be generated on DMI whenever
the corresponding flag is set in the ERRSTS register. The actual generation of the
SERR message is globally enabled for Device 0 via the PCI Command register.
Bit
Access &
Default
15:13
RO
000b
12
RWC/S
0b
11
RW
0b
Description
Reserved
GMCH Software Generated Event for SMI (GSGESMI): This
indicates the source of the SMI was a Device 2 Software Event.
SERR on GMCH Thermal Sensor Event (TSESERR):
1 = The GMCH generates a DMI SERR special cycle when bit 11 of the
ERRSTS is set. The SERR must not be enabled at the same time
as the SMI for the same thermal sensor event.
0 = Reporting of this condition via SERR messaging is disabled.
10
RO
0b
Reserved
9
RW
0b
SERR on LOCK to non-DRAM Memory (LCKERR):
1 = The GMCH will generate a DMI SERR special cycle whenever a
processor lock cycle is detected that does not hit DRAM.
0 = Reporting of this condition via SERR messaging is disabled.
8:0
110
RW
0s
Reserved
Datasheet
DRAM Controller Registers (D0:F0)
5.1.37
SMICMD—SMI Command
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/PCI
CC–CDh
0000h
RO, RW
16 bits
This register enables various errors to generate an SMI DMI special cycle. When an
error flag is set in the ERRSTS register, it can generate an SERR, SMI, or SCI DMI
special cycle when enabled in the ERRCMD, SMICMD, or SCICMD registers,
respectively. Note that one and only one message type can be enabled.
Bit
Access &
Default
Description
15:12
RO
0h
Reserved
11
RW
0b
SMI on GMCH Thermal Sensor Trip (TSTSMI):
1 = A SMI DMI special cycle is generated by GMCH when the thermal
sensor trip requires an SMI. A thermal sensor trip point cannot
generate more than one special cycle.
0 = Reporting of this condition via SMI messaging is disabled.
10:0
5.1.38
RO
0s
Reserved
SKPD—Scratchpad Data
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/PCI
DC–DFh
00000000h
RW
32 bits
This register holds 32 writable bits with no functionality behind them. It is for the
convenience of BIOS and graphics drivers.
Datasheet
Bit
Access &
Default
31:0
RW
00000000h
Description
Scratchpad Data (SKPD): 1 DWord of data storage.
111
DRAM Controller Registers (D0:F0)
5.1.39
CAPID0—Capability Identifier
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
112
0/0/0/PCI
E0–E9h
00000000000001090009h
RO
80 bits
Bit
Access &
Default
Description
79:26
RO
0s
Reserved
27:24
RO
1h
CAPID Version (CAPIDV): This field has the value 0001b to identify
the first revision of the CAPID register definition.
23:16
RO
09h
CAPID Length (CAPIDL): This field has the value 09h to indicate the
structure length (9 bytes).
15:8
RO
00h
Next Capability Pointer (NCP): This field is hardwired to 00h
indicating the end of the capabilities linked list.
7:0
RO
09h
Capability Identifier (CAP_ID): This field has the value 1001b to
identify the CAP_ID assigned by the PCI SIG for vendor dependent
capability pointers.
Datasheet
DRAM Controller Registers (D0:F0)
5.2
MCHBAR
The MCHBAR registers are offset from the MCHBAR base address. Table 5-2 provides
an address map of the registers listed by address offset in ascending order. Detailed
register bit descriptions follow the table.
Table 5-2. MCHBAR Register Address Map
Datasheet
Address
Offset
Symbol
Register Name
Default
Value
Access
111h
CHDECMISC
Channel Decode Miscellaneous
00h
RW
200–01h
C0DRB0
Channel 0 DRAM Rank
Boundary Address 0
0000h
RO, RW
202–203h
C0DRB1
Channel 0 DRAM Rank
Boundary Address 1
0000h
RW, RO
204–205h
C0DRB2
Channel 0 DRAM Rank
Boundary Address 2
0000h
RW, RO
206–207h
C0DRB3
Channel 0 DRAM Rank
Boundary Address 3
0000h
RW, RO
208–209h
C0DRA01
Channel 0 DRAM Rank 0,1
Attribute
0000h
RW
20A–20Bh
C0DRA23
Channel 0 DRAM Rank 2,3
Attribute
0000h
RW
250–251h
C0CYCTRKPCHG
Channel 0 CYCTRK PCHG
0000h
RW, RO
252–255h
C0CYCTRKACT
Channel 0 CYCTRK ACT
00000000h
RW, RO
256–257h
C0CYCTRKWR
Channel 0 CYCTRK WR
0000h
RW
258–25Ah
C0CYCTRKRD
Channel 0 CYCTRK READ
000000h
RW, RO
25B–25Ch
C0CYCTRKREFR
Channel 0 CYCTRK REFR
0000h
RO, RW
260–263h
C0CKECTRL
Channel 0 CKE Control
00000800h
RO, RW,
RW
269–26Eh
C0REFRCTRL
Channel 0 DRAM Refresh
Control
021830000
C30h
RW, RO
29C–29Fh
C0ODTCTRL
Channel 0 ODT Control
00100000h
RO, RW
600–601h
C1DRB0
Channel 1 DRAM Rank
Boundary Address 0
0000h
RW, RO
602–603h
C1DRB1
Channel 1 DRAM Rank
Boundary Address 1
0000h
RW, RO
604–605h
C1DRB2
Channel 1 DRAM Rank
Boundary Address 2
0000h
RW, RO
606–607h
C1DRB3
Channel 1 DRAM Rank
Boundary Address 3
0000h
RW, RO
113
DRAM Controller Registers (D0:F0)
114
Address
Offset
Symbol
608–609h
C1DRA01
60A–60Bh
C1DRA23
650–651h
C1CYCTRKPCHG
652–655h
C1CYCTRKACT
656–657h
Register Name
Default
Value
Access
Channel 1 DRAM Rank 0,1
Attributes
0000h
RW,
Channel 1 DRAM Rank 2,3
Attributes
0000h
RW
Channel 1 CYCTRK PCHG
0000h
RO, RW
Channel 1 CYCTRK ACT
00000000h
RO, RW
C1CYCTRKWR
Channel 1 CYCTRK WR
0000h
RW,
658–65Ah
C1CYCTRKRD
Channel 1 CYCTRK READ
000000h
RO, RW
660–663h
C1CKECTRL
Channel 1 CKE Control
00000800h
RW,
RW, RO
669–66Eh
C1REFRCTRL
Channel 1 DRAM Refresh
Control
021830000
C30h
RW, RO
69C–69Fh
C1ODTCTRL
Channel 1 ODT Control
00100000h
RO, RW
A00– A01h
EPC0DRB0
EP Channel 0 DRAM Rank
Boundary Address 0
0000h
RW, RO
A02– A03h
EPC0DRB1
EP Channel 0 DRAM Rank
Boundary Address 1
0000h
RO, RW
A04– A05h
EPC0DRB2
EP Channel 0 DRAM Rank
Boundary Address 2
0000h
RO, RW
A06– A07h
EPC0DRB3
EP Channel 0 DRAM Rank
Boundary Address 3
0000h
RW, RO
A08– A09h
EPC0DRA01
EP Channel 0 DRAM Rank 0,1
Attribute
0000h
RW
A0A– A0Bh
EPC0DRA23
EP Channel 0 DRAM Rank 2,3
Attribute
0000h
RW
A19– A1Ah
EPDCYCTRKWRT
PRE
EPD CYCTRK WRT PRE
0000h
RW, RO
A1C– A1Fh
EPDCYCTRKWRT
ACT
EPD CYCTRK WRT ACT
00000000h
RO, RW
A20– A21h
EPDCYCTRKWRT
WR
EPD CYCTRK WRT WR
0000h
RW, RO
A22– A23h
EPDCYCTRKWRT
REF
EPD CYCTRK WRT REF
0000h
RO, RW
A24– A26h
EPDCYCTRKWRT
RD
EPD CYCTRK WRT READ
000000h
RW
A28– A33h
EPDCKECONFIG
REG
EPD CKE related configuration
registers
00E000000
0h
RW
A2Eh
MEMEMSPACE
00h
RW, RO
A30–A33h
EPDREFCONFIG
40000C30h
RO, RW
ME Memory Space
Configuration
EP DRAM Refresh Configuration
Datasheet
DRAM Controller Registers (D0:F0)
Datasheet
Address
Offset
Symbol
CD8h
TSC1
CD9h
TSC2
CDAh
TSS
CDC–CDFh
TSTTP
CE2h
TCO
CE4h
Register Name
Default
Value
Access
Thermal Sensor Control 1
00h
RW/L,
RW,
RS/WC
Thermal Sensor Control 2
00h
RW/L,
RO
Thermal Sensor Status
00h
RO
00000000h
RO, RW,
RW/L
Thermal Calibration Offset
00h
RW/L/K,
RW/L
THERM1
Hardware Throttle Control
00h
RW/L,
RO,
RW/L/K
CEA–CEBh
TIS
Thermal Interrupt Status
0000h
RO,
RWC
CF1h
TSMICMD
00h
RO, RW
F14–F17h
PMSTS
00000000h
RWC/S,
RO
Thermal Sensor Temperature
Trip Point
Thermal SMI Command
Power Management Status
115
DRAM Controller Registers (D0:F0)
5.2.1
CHDECMISC—Channel Decode Miscellaneous
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/MCHBAR
111h
00h
RW/L
8 bits
This register has Miscellaneous CHDEC/MAGEN configuration bits.
Bit
Access &
Default
Description
7
RW/L
0b
Reserved
6:5
RW/L
00b
Enhanced Mode Select (ENHMODESEL):
00 = Swap Enabled for Bank Selects and Rank Selects
01 = XOR Enabled for Bank Selects and Rank Selects
10 = Swap Enabled for Bank Selects only
11 = Reserved
4
RO
0b
Reserved
3
RW
0b
Ch1 Enhanced Mode (CH1_ENHMODE): This bit enables Enhanced
addressing mode of operation is enabled for Ch 1.
0 = Disable
1 = Enable
2
RW/L
0b
Ch0 Enhanced Mode (CH0_ENHMODE): This bit enables Enhanced
addressing mode of operation is enabled for Ch 0.
0 = Disable
1 = Enable
1
RW
0b
Flex Memory (FLXMEM): This bit disables the Flex mode memory
configuration.
0 = Enable
1 = Disable
0
RW
0b
ME Present (EPPRSNT): This bit indicates whether ME UMA is
present in the system or not.
0 = Not Present
1 = Present
116
Datasheet
DRAM Controller Registers (D0:F0)
5.2.2
C0DRB0—Channel 0 DRAM Rank Boundary Address 0
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/MCHBAR
200–201h
0000h
R/W, RO
16 bits
The DRAM Rank Boundary Registers define the upper boundary address of each DRAM
rank with a granularity of 64 MB. Each rank has its own single-word DRB register.
These registers are used to determine which chip select will be active for a given
address. Channel and rank map:
Ch
Ch
Ch
Ch
Ch
Ch
Ch
Ch
0,
0,
0,
0,
1,
1,
1,
1,
Rank
Rank
Rank
Rank
Rank
Rank
Rank
Rank
0
1
2
3
0
1
2
3
=
=
=
=
=
=
=
=
200h
202h
204h
206h
600h
602h
604h
606h
Programming Guide
If Channel 0 is empty, all of the C0DRBs are programmed with 00h.
C0DRB0 = Total memory in Ch 0, Rank 0 (in 64 MB increments)
C0DRB1 = Total memory in Ch 0, Rank 0 + Ch 0, Rank 1 (in 64 MB increments)
…
If Channel 1 is empty, all of the C1DRBs are programmed with 00h
C1DRB0= Total memory in Ch 1, Rank 0 (in 64 MB increments)
C1DRB1= Total memory in Ch 1, Rank 0 + Ch 1, Rank 1 (in 64 MB increments)
...
For Flex Memory Mode
C1DRB0, C1DRB1, and C1DRB2:
They are also programmed similar to non-Flex mode. Only exception is, the DRBs
corresponding to the top most populated rank and higher ranks in Channel 1 must be
programmed with the value of the total Channel 1 population plus the value of total
Channel 0 population (C0DRB3).
Example: If only Ranks 0 and 1 are populated in Ch1 in Flex mode, then:
C1DRB0 = Total memory in Ch 1, Rank 0 (in 64MB increments)
C1DRB1 = C0DRB3 + Total memory in Ch 1, Rank 0 + Ch 1, Rank 1 (in 64 MB
increments) (Rank 1 is the topmost populated rank)
C1DRB2 = C1DRB1
C1DRB3 = C1DRB1
C1DRB3:
C1DRB3 = C0DRB3 + Total memory in Channel 1.
Datasheet
117
DRAM Controller Registers (D0:F0)
Bit
Access &
Default
15:10
RO
000000b
9:0
R/W
000h
Description
Reserved
Channel 0 Dram Rank Boundary Address 0 (C0DRBA0): This
register defines the DRAM rank boundary for rank0 of Channel 0
(64 MB granularity)
= R0
R0 = Total Rank 0 memory size is 64 MB
R1 = Total Rank 1 memory size is 64 MB
R2 = Total Rank 2 memory size is 64 MB
R3 = Total Rank 3 memory size is 64 MB
5.2.3
C0DRB1—Channel 0 DRAM Rank Boundary Address 1
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/MCHBAR
202–203h
0000h
R/W, RO
16 bits
See C0DRB0 register for programming information.
Bit
Access &
Default
15:10
RO
000000b
9:0
R/W
000h
Description
Reserved
Channel 0 Dram Rank Boundary Address 1 (C0DRBA1): This
register defines the DRAM rank boundary for rank1 of Channel 0
(64 MB granularity)
= (R1 + R0)
R0 = Total Rank 0 memory size is 64 MB
R1 = Total Rank 1 memory size is 64 MB
R2 = Total Rank 2 memory size is 64 MB
R3 = Total Rank 3 memory size is 64 MB
118
Datasheet
DRAM Controller Registers (D0:F0)
5.2.4
C0DRB2—Channel 0 DRAM Rank Boundary Address 2
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/MCHBAR
204–205h
0000h
RO, R/W
16 bits
See C0DRB0 register for programming information.
Bit
Access &
Default
15:10
RO
000000b
9:0
R/W
000h
Description
Reserved
Channel 0 DRAM Rank Boundary Address 2 (C0DRBA2): This
register defines the DRAM rank boundary for rank2 of Channel 0
(64 MB granularity)
= (R2 + R1 + R0)
R0 = Total Rank 0 memory size is 64 MB
R1 = Total Rank 1 memory size is 64 MB
R2 = Total Rank 2 memory size is 64 MB
R3 = Total Rank 3 memory size is 64 MB
5.2.5
C0DRB3—Channel 0 DRAM Rank Boundary Address 3
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/MCHBAR
206–207h
0000h
R/W, RO
16 bits
See C0DRB0 register for programming information.
Bit
Access &
Default
15:10
RO
000000b
9:0
R/W
000h
Description
Reserved
Channel 0 DRAM Rank Boundary Address 3 (C0DRBA3): This
register defines the DRAM rank boundary for rank3 of Channel 0
(64 MB granularity)
= (R3 + R2 + R1 + R0)
R0 = Total Rank 0 memory size is 64 MB
R1 = Total Rank 1 memory size is 64 MB
R2 = Total Rank 2 memory size is 64 MB
R3 = Total Rank 3 memory size is 64 MB
Datasheet
119
DRAM Controller Registers (D0:F0)
5.2.6
C0DRA01—Channel 0 DRAM Rank 0,1 Attribute
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/MCHBAR
208–209h
0000h
R/W
16 bits
The DRAM Rank Attribute Registers define the page sizes/number of banks to be used
when accessing different ranks. These registers should be left with their default value
(all zeros) for any rank that is unpopulated, as determined by the corresponding
CxDRB registers. Each byte of information in the CxDRA registers describes the page
size of a pair of ranks. Channel and rank map:
Ch
Ch
Ch
Ch
0,
0,
1,
1,
Rank
Rank
Rank
Rank
0,
2,
0,
2,
1= 208h–209h
3 = 20Ah–20Bh
1= 608h–609h
3= 60Ah–60Bh
DRA[7:0] = "00" means Cfg 0 , DRA[7:0] ="01" means Cfg 1 .... DRA[7:0] = "09" means Cfg 9
and so on.
Table 5-3. DRAM Rank Attribute Register Programming
120
Cfg
Tech
DDRx
Depth
Width
Row
Col
Bank
Row
Size
Page
Size
0
256Mb
2
32M
8
13
10
2
256 MB
8k
1
256Mb
2
16M
16
13
9
2
128 MB
4k
2
512Mb
2
64M
8
14
10
2
512 MB
8k
3
512Mb
2
32M
16
13
10
2
256 MB
8k
4
512Mb
3
64M
8
13
10
3
512 MB
8k
5
512Mb
3
32M
16
12
10
3
256 MB
8k
6
1 Gb
2,3
128M
8
14
10
3
1 GB
8k
7
1 Gb
2,3
64M
16
13
10
3
512 MB
8k
Bit
Access &
Default
Description
15:8
R/W
00h
Channel 0 DRAM Rank-1 Attributes (C0DRA1): This field defines
DRAM pagesize/number-of-banks for rank1 for given channel. See
Table 5-3 for programming.
7:0
R/W
00h
Channel 0 DRAM Rank-0 Attributes (C0DRA0): This field defines
DRAM page size/number-of-banks for rank0 for given channel. See
Table 5-3 for programming.
Datasheet
DRAM Controller Registers (D0:F0)
5.2.7
C0DRA23—Channel 0 DRAM Rank 2,3 Attribute
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/MCHBAR
20A–20Bh
0000h
R/W
16 bits
See C0DRA01 register for programming information.
5.2.8
Bit
Access &
Default
Description
15:8
R/W
00h
Channel 0 DRAM Rank-3 Attributes (CODRA3): This register
defines DRAM pagesize/number-of-banks for rank3 for given channel.
See Table 5-3 for programming.
7:0
R/W
00h
Channel 0 DRAM Rank-2 Attributes (CODRA2): This register
defines DRAM pagesize/number-of-banks for rank2 for given channel.
See Table 5-3 for programming.
C0CYCTRKPCHG—Channel 0 CYCTRK PCHG
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/MCHBAR
250–251h
0000h
RW, RO
16 bits
This register provides Channel 0 CYCTRK Precharge.
Datasheet
Bit
Access &
Default
Description
15:11
RW
00000b
ACT To PRE Delayed (C0sd_cr_act_pchg): This configuration
register indicates the minimum allowed spacing (in DRAM clocks)
between the ACT and PRE commands to the same rank-bank. This
field corresponds to tRAS in the DDR Specification.
10:6
RW
00000b
Write To PRE Delayed (C0sd_cr_wr_pchg): This field indicates the
minimum allowed spacing (in DRAM clocks) between the WRITE and
PRE commands to the same rank-bank. This field corresponds to tWR in
the DDR Specification.
5:2
RW
0000b
READ To PRE Delayed (C0sd_cr_rd_pchg): This field indicates the
minimum allowed spacing (in DRAM clocks) between the READ and
PRE commands to the same rank-bank.
1:0
RW
00b
PRE To PRE Delayed (C0sd_cr_pchg_pchg): This field indicates
the minimum allowed spacing (in DRAM clocks) between two PRE
commands to the same rank.
121
DRAM Controller Registers (D0:F0)
5.2.9
C0CYCTRKACT—Channel 0 CYCTRK ACT
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/MCHBAR
252–255h
00000000h
RW, RO
32 bits
This register provides Channel 0 CYCTRK Activate.
122
Bit
Access &
Default
Description
31:28
RO
0h
27:22
RW
000000b
21
RW
0b
Max ACT Check Disable (C0sd_cr_maxact_dischk): This field
disenables the check which ensures that there are no more than four
activates to a particular rank in a given window.
20:17
RW
0000b
ACT to ACT Delayed (C0sd_cr_act_act[): This field indicates the
minimum allowed spacing (in DRAM clocks) between two ACT
commands to the same rank. This field corresponds to tRRD in the DDR
Specification.
16:13
RW
0000b
PRE to ACT Delayed (C0sd_cr_pre_act): This field indicates the
minimum allowed spacing (in DRAM clocks) between the PRE and ACT
commands to the same rank-bank. This field corresponds to tRP in the
DDR Specification.
12:9
RW
0h
8:0
RW
00000000
0b
Reserved
ACT Window Count (C0sd_cr_act_windowcnt): This field indicates
the window duration (in DRAM clocks) during which the controller
counts the # of activate commands which are launched to a particular
rank. If the number of activate commands launched within this window
is greater than 4, then a check is implemented to block launch of
further activates to this rank for the rest of the duration of this
window.
ALLPRE to ACT Delay (C0sd0_cr_preall_act): From the launch of a
prechargeall command wait for these many # of memory clocks before
launching a activate command. This field corresponds to tPALL_RP.
REF to ACT Delayed (C0sd_cr_rfsh_act): This configuration
register indicates the minimum allowed spacing (in DRAM clocks)
between REF and ACT commands to the same rank. This field
corresponds to tRFC in the DDR Specification.
Datasheet
DRAM Controller Registers (D0:F0)
5.2.10
C0CYCTRKWR—Channel 0 CYCTRK WR
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/MCHBAR
256–257h
0000h
RW
16 bits
This register provides Channel 0 CYCTRK WR.
Datasheet
Bit
Access &
Default
Description
15:12
RW
0h
ACT To Write Delay (C0sd_cr_act_wr): This field indicates the
minimum allowed spacing (in DRAM clocks) between the ACT and
WRITE commands to the same rank-bank. This field corresponds to
tRCD_wr in the DDR Specification.
11:8
RW
0h
Same Rank Write To Write Delay (C0sd_cr_wrsr_wr): This field
indicates the minimum allowed spacing (in DRAM clocks) between two
WRITE commands to the same rank.
7:4
RW
0h
Different Rank Write to Write Delay (C0sd_cr_wrdr_wr): This
field indicates the minimum allowed spacing (in DRAM clocks)
between two WRITE commands to different ranks. This field
corresponds to tWR_WR in the DDR Specification.
3:0
RW
0h
READ To WRTE Delay (C0sd_cr_rd_wr): This field indicates the
minimum allowed spacing (in DRAM clocks) between the READ and
WRITE commands. This field corresponds to tRD_WR.
123
DRAM Controller Registers (D0:F0)
5.2.11
C0CYCTRKRD—Channel 0 CYCTRK READ
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/MCHBAR
258–25Ah
000000h
RW, RO
24 bits
This register provides Channel 0 CYCTRK RD.
5.2.12
Bit
Access &
Default
Description
23:21
RO
000b
20:17
RW
0h
Min ACT To READ Delay (C0sd_cr_act_rd): This field indicates the
minimum allowed spacing (in DRAM clocks) between the ACT and
READ commands to the same rank-bank. This field corresponds to
tRCD_rd in the DDR Specification.
16:12
RW
00000b
Same Rank Write To READ Delay (C0sd_cr_wrsr_rd): This field
indicates the minimum allowed spacing (in DRAM clocks) between the
WRITE and READ commands to the same rank. This field corresponds
to tWTR in the DDR Specification.
11:8
RW
0000b
Different Ranks Write To READ Delay (C0sd_cr_wrdr_rd): This
field indicates the minimum allowed spacing (in DRAM clocks) between
the WRITE and READ commands to different ranks. This field
corresponds to tWR_RD in the DDR Specification.
7:4
RW
0000b
Same Rank Read To Read Delay (C0sd_cr_rdsr_rd): This field
indicates the minimum allowed spacing (in DRAM clocks) between two
READ commands to the same rank.
3:0
RW
0000b
Different Ranks Read To Read Delay (C0sd_cr_rddr_rd): This
field indicates the minimum allowed spacing (in DRAM clocks) between
two READ commands to different ranks. This field corresponds to
tRD_RD.
Reserved
C0CYCTRKREFR—Channel 0 CYCTRK REFR
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/MCHBAR
25B–25Ch
0000h
RO, RW
16 bits
This register provides Channel 0 CYCTRK Refresh.
124
Bit
Access &
Default
Description
15:13
RO
000b
12:9
RW
0000b
Same Rank PALL to REF Delay (C0sd_cr_pchgall_rfsh): This
field indicates the minimum allowed spacing (in DRAM clocks)
between the PRE-ALL and REF commands to the same rank.
8:0
RW
000000000b
Same Rank REF to REF Delay (C0sd_cr_rfsh_rfsh): This field
indicates the minimum allowed spacing (in DRAM clocks) between
two REF commands to same ranks.
Reserved
Datasheet
DRAM Controller Registers (D0:F0)
5.2.13
C0CKECTRL—Channel 0 CKE Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/MCHBAR
260–263h
00000800h
RO, RW
32 bits
This register provides CKE controls for Channel 0
Bit
Access &
Default
Description
31:30
RW
00b
Number of clocks from internal ODT command start that ODT
Read Safe will be asserted (sd0_cr_odt_rdsafe): Number of
clocks from internal ODT command start that ODT Read Safe will be
asserted
29:28
RW
00b
Number of clocks from internal ODT command start that ODT
Write Safe will be asserted (sd0_cr_odt_wrsafe): Number of
clocks from internal ODT command start that ODT Write Safe will be
asserted
27
RW
0b
start the self-refresh exit sequence (sd0_cr_srcstart): This field
indicates the request to start the self-refresh exit sequence.
26:24
RW
000b
CKE pulse width requirement in high phase
(sd0_cr_cke_pw_hl_safe): This field indicates CKE pulse width
requirement in high phase. This field corresponds to tCKE ( high ) in the
DDR Specification.
23
RW
0b
Rank 3 Population (sd0_cr_rankpop3):
1 = Rank 3 populated
0 = Rank 3 not populated
22
RW
0b
Rank 2 Population (sd0_cr_rankpop2):
1 = Rank 2 populated
0 = Rank 2 not populated
21
RW
0b
Rank 1 Population (sd0_cr_rankpop1):
1 = Rank 1 populated
0 = Rank 1 not populated
20
RW
0b
Rank 0 Population (sd0_cr_rankpop0):
1 = Rank 0 populated
0 = Rank 0 not populated
Datasheet
19:17
RW
000b
CKE pulse width requirement in low phase
(sd0_cr_cke_pw_lh_safe): This field indicates CKE pulse width
requirement in low phase. This field corresponds to tCKE (low) in the
DDR Specification.
16
RW
0b
Enable CKE toggle for PDN entry/exit (sd0_cr_pdn_enable):
This bit indicates that the toggling of CKEs (for PDN entry/exit) is
enabled.
125
DRAM Controller Registers (D0:F0)
Bit
Access &
Default
Description
15
RW
0b
Read ODT Not Always Safe (sd0_cr_rdodtnas): Internal Read
ODT to CS is not always safe. Setting this bit selects the delay
(programmable) in the ODT Read Safe register field.
14
RW
0b
Write ODT Not Always Safe (sd0_cr_wrodtnas): Internal Write
ODT to CS is not always safe. Setting this bit selects the delay
(programmable) in the ODT Write Safe register field.
13:10
RW
0010b
Minimum Power-down exit to Non-Read command spacing
(sd0_cr_txp): This field indicates the minimum number of clocks to
wait following assertion of CKE before issuing a non-read command.
0000–0001 = Reserved
0010–1001 = 2–9clocks
1010–1111 = Reserved
5.2.14
9:1
RW
00000000
0b
0
RW
0b
Self refresh exit count (sd0_cr_slfrfsh_exit_cnt): This field
indicates the Self refresh exit count. (Program to 255). This field
corresponds to tXSNR/tXSRD in the DDR Specification.
Indicates only 1 DIMM populated (sd0_cr_singledimmpop): This
bit, when set, indicates that only 1 DIMM is populated.
C0REFRCTRL—Channel 0 DRAM Refresh Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/MCHBAR
269–26Eh
021830000C30h
RW, RO
48 bits
This register provides settings to configure the DRAM refresh controller.
126
Bit
Access &
Default
Description
47:42
RO
00h
41:37
RW
10000b
Direct Rcomp Quiet Window (DIRQUIET): This field indicates the
amount of refresh_tick events to wait before the service of rcomp
request in non-default mode of independent rank refresh.
36:32
RW
11000b
Indirect Rcomp Quiet Window (INDIRQUIET): This field indicates
the amount of refresh_tick events to wait before the service of rcomp
request in non-default mode of independent rank refresh.
31:27
RW
00110b
Rcomp Wait (RCOMPWAIT): This field indicates the amount of
refresh_tick events to wait before the service of rcomp request in
non-default mode of independent rank refresh.
26
RW
0b
Reserved
Reserved
Datasheet
DRAM Controller Registers (D0:F0)
Bit
Access &
Default
25
RW
0b
Description
Refresh Counter Enable (REFCNTEN): This bit is used to enable
the refresh counter to count during times that DRAM is not in selfrefresh, but refreshes are not enabled. Such a condition may occur
due to need to reprogram DIMMs following DRAM controller switch.
This bit has no effect when Refresh is enabled (i.e., there is no mode
where Refresh is enabled but the counter does not run). Thus, in
conjunction with bit 23 REFEN, the modes are:
REFEN:REFCNTEN
Description
0:0
Normal refresh disable
0:1
Refresh disabled, but counter is accumulating
refreshes.
1:X
Normal refresh enable
24
RW
0b
All Rank Refresh (ALLRKREF): This configuration bit enables (by
default) that all the ranks are refreshed in a staggered/atomic
fashion. If set, the ranks are refreshed in an independent fashion.
23
RW
0b
Refresh Enable (REFEN):
0 = Disabled
1 = Enabled
22
RW
0b
DDR Initialization Done (INITDONE): Indicates that DDR
initialization is complete.
0 = Not Done
1 = Done
21:20
RW
00b
Reserved
19:18
RW
00b
DRAM Refresh Panic Watermark (REFPANICWM): When the
refresh count exceeds this level, a refresh request is launched to the
scheduler and the dref_panic flag is set.
00
01
10
11
17:16
RW
00b
5
6
7
8
DRAM Refresh High Watermark (REFHIGHWM): When the
refresh count exceeds this level, a refresh request is launched to the
scheduler and the dref_high flag is set.
00
01
10
11
Datasheet
=
=
=
=
=
=
=
=
3
4
5
6
127
DRAM Controller Registers (D0:F0)
Bit
Access &
Default
15:14
RW
00b
Description
DRAM Refresh Low Watermark (REFLOWWM): When the refresh
count exceeds this level, a refresh request is launched to the
scheduler and the dref_low flag is set.
00
01
10
11
13:0
RW
001100001
10000b
=
=
=
=
1
2
3
4
Refresh Counter Time Out Value (REFTIMEOUT): Program this
field with a value that will provide 7.8 us at the memory clock
frequency. At various memory clock frequencies this results in the
following values:
266 MHz -> 820h
333 MHz -> A28h
400 MHz -> C30h
5.2.15
C0ODTCTRL—Channel 0 ODT Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/MCHBAR
29C–29Fh
00100000h
RO, RW
32 bits
This register provides ODT controls.
Bit
Access &
Default
31:24
RO
00h
23:20
RW
0001b
Description
Reserved
MCH ODT Latency (sd0_cr_modtl): Delay from CS# to GMCH
ODT assertion.
0000 = Reserved
0001–1100 = 1–12 clocks
1101–1111 = Reserved
19:17
RW
0000b
CAS latency (sd0_cr_casl): (for CAS Latency)
This configuration register indicates the CAS latency of the memory
population. Also, termed as SDRAM to CAS latency.
000 = 3 memory clocks
001 = 4 memory clocks
…
111 = 10 memory clocks
16:0
128
RO
00h
Reserved
Datasheet
DRAM Controller Registers (D0:F0)
5.2.16
C1DRB0—Channel 1 DRAM Rank Boundary Address 0
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/MCHBAR
600–601h
0000h
RW, RO
16 bits
The operation of this register is detailed in the description for register C0DRB0.
5.2.17
Bit
Access &
Default
15:10
RO
000000b
9:0
RW/L
000h
Description
Reserved
Channel 1 DRAM Rank Boundary Address 0 (C1DRBA0): See
C0DRB0 register. In Flex mode this is the topmost populated rank
in Channel 1, program this value to be cumulative of Ch0 DRB3.
C1DRB1—Channel 1 DRAM Rank Boundary Address 1
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/MCHBAR
602–603h
0000h
RW, RO
16 bits
The operation of this register is detailed in the description for register C0DRB0.
Datasheet
Bit
Access &
Default
15:1
0
RO
000000b
9:0
RW/L
000h
Description
Reserved
Channel 1 DRAM Rank Boundary Address 1 (C1DRBA1): See
C0DRB1 register. In Flex mode this is the topmost populated rank in
Channel 1, program this value to be cumulative of Ch0 DRB3.
129
DRAM Controller Registers (D0:F0)
5.2.18
C1DRB2—Channel 1 DRAM Rank Boundary Address 2
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/MCHBAR
604–605h
0000h
RW, RO
16 bits
The operation of this register is detailed in the description for register C0DRB0.
5.2.19
Bit
Access &
Default
15:10
RO
000000b
9:0
RW/L
000h
Description
Reserved
Channel 1 DRAM Rank Boundary Address 2 (C1DRBA2): See
C0DRB2 register. In Flex mode this is the topmost populated rank in
Channel 1, program this value to be cumulative of Ch0 DRB3.
C1DRB3—Channel 1 DRAM Rank Boundary Address 3
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/MCHBAR
606–607h
0000h
RW, RO
16 bits
The operation of this register is detailed in the description for register C0DRB0.
130
Bit
Access &
Default
15:10
RO
000000b
9:0
RW/L
000h
Description
Reserved
Channel 1 DRAM Rank Boundary Address 3 (C1DRBA3): See
C0DRB3 register. In Flex mode this is the topmost populated rank in
Channel 1, program this value to be cumulative of Ch0 DRB3
Datasheet
DRAM Controller Registers (D0:F0)
5.2.20
C1DRA01—Channel 1 DRAM Rank 0,1 Attributes
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/MCHBAR
608–609h
0000h
RW
16 bits
The operation of this register is detailed in the description for register C0DRA01.
5.2.21
Bit
Access &
Default
Description
15:8
RW/L
00h
Channel 1 DRAM Rank-1 Attributes (C1DRA1): See C0DRA1
register.
7:0
RW/L
00h
Channel 1 DRAM Rank-0 Attributes (C1DRA0): See C0DRA0
register.
C1DRA23—Channel 1 DRAM Rank 2,3 Attributes
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/MCHBAR
60A–60Bh
0000h
RW
16 bits
The operation of this register is detailed in the description for register C0DRA01.
Datasheet
Bit
Access &
Default
Description
15:8
RW/L
00h
Channel 1 DRAM Rank-3 Attributes (C1DRA3): See C0DRA3
register.
7:0
RW/L
00h
Channel 1 DRAM Rank-2 Attributes (C1DRA2): See C0DRA2
register.
131
DRAM Controller Registers (D0:F0)
5.2.22
C1CYCTRKPCHG—Channel 1 CYCTRK PCHG
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/MCHBAR
650–651h
0000h
RO, RW
16 bits
This register provides Channel 1 CYCTRK Precharge.
132
Bit
Access &
Default
Description
15:11
RW
00000b
ACT To PRE Delayed (C1sd_cr_act_pchg): This configuration
register indicates the minimum allowed spacing (in DRAM clocks)
between the ACT and PRE commands to the same rank-bank.
10:6
RW
00000b
Write To PRE Delayed (C1sd_cr_wr_pchg): This field indicates the
minimum allowed spacing (in DRAM clocks) between the WRITE and
PRE commands to the same rank-bank. This field corresponds to tWR in
the DDR Specification.
5:2
RW
0000b
READ To PRE Delayed (C1sd_cr_rd_pchg): This field indicates the
minimum allowed spacing (in DRAM clocks) between the READ and
PRE commands to the same rank-bank
1:0
RW
00b
PRE To PRE Delayed (C1sd_cr_pchg_pchg): This field indicates
the minimum allowed spacing (in DRAM clocks) between two PRE
commands to the same rank.
Datasheet
DRAM Controller Registers (D0:F0)
5.2.23
C1CYCTRKACT—Channel 1 CYCTRK ACT
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/MCHBAR
652–655h
00000000h
RO, RW
32 bits
This register provides Channel 1 CYCTRK ACT.
Datasheet
Bit
Access &
Default
Description
31:28
RO
0h
27:22
RW
000000b
21
RW
0b
Max ACT Check Disable (C1sd_cr_maxact_dischk): This field
disenables the check which ensures that there are no more than four
activates to a particular rank in a given window.
20:17
RW
0000b
ACT to ACT Delayed (C1sd_cr_act_act[): This field indicates the
minimum allowed spacing (in DRAM clocks) between two ACT
commands to the same rank. This field corresponds to tRRD in the DDR
Specification.
16:13
RW
0000b
PRE to ACT Delayed (C1sd_cr_pre_act): This field indicates the
minimum allowed spacing (in DRAM clocks) between the PRE and ACT
commands to the same rank-bank:12:9R/W0000bPRE-ALL to ACT
Delayed (C1sd_cr_preall_act): This configuration register indicates the
minimum allowed spacing (in DRAM clocks) between the PRE-ALL and
ACT commands to the same rank. This field corresponds to tRP in the
DDR Specification.
12:9
RW
0h
ALLPRE to ACT Delay (C1sd_cr_preall_act): From the launch of a
Prechargeall command wait for these many # of memory clocks before
launching a activate command. This field corresponds to tPALL_RP.
8:0
RW
00000000
0b
REF to ACT Delayed (C1sd_cr_rfsh_act): This field indicates the
minimum allowed spacing (in DRAM clocks) between REF and ACT
commands to the same rank. This field corresponds to tRFC in the DDR
Specification.
Reserved
ACT Window Count (C1sd_cr_act_windowcnt): This field indicates
the window duration (in DRAM clocks) during which the controller
counts the # of activate commands which are launched to a particular
rank. If the number of activate commands launched within this window
is greater than 4, then a check is implemented to block launch of
further activates to this rank for the rest of the duration of this
window.
133
DRAM Controller Registers (D0:F0)
5.2.24
C1CYCTRKWR—Channel 1 CYCTRK WR
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/MCHBAR
656–657h
0000h
RW
16 bits
This register provides Channel 1 CYCTRK WR.
134
Bit
Access &
Default
Description
15:12
RW
0h
ACT To Write Delay (C1sd_cr_act_wr): This field indicates the
minimum allowed spacing (in DRAM clocks) between the ACT and
WRITE commands to the same rank-bank. This field corresponds to
tRCD_wr in the DDR Specification.
11:8
RW
0h
Same Rank Write To Write Delayed (C1sd_cr_wrsr_wr): This
field indicates the minimum allowed spacing (in DRAM clocks)
between two WRITE commands to the same rank.
7:4
RW
0h
Different Rank Write to Write Delay (C1sd_cr_wrdr_wr): This
field indicates the minimum allowed spacing (in DRAM clocks)
between two WRITE commands to different ranks. This field
corresponds to tWR_WR in the DDR Specification.
3:0
RW
0h
READ To WRTE Delay (C1sd_cr_rd_wr): This field indicates the
minimum allowed spacing (in DRAM clocks) between the READ and
WRITE commands. This field corresponds to tRD_WR.
Datasheet
DRAM Controller Registers (D0:F0)
5.2.25
C1CYCTRKRD—Channel 1 CYCTRK READ
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/MCHBAR
658–65Ah
000000h
RO, RW
24 bits
This is the Channel 1 CYCTRK READ register.
Datasheet
Bit
Access &
Default
Description
23:20
RO
0h
Reserved
19:16
RW
0h
Min ACT To READ Delayed (C1sd_cr_act_rd): This field indicates
the minimum allowed spacing (in DRAM clocks) between the ACT and
READ commands to the same rank-bank. This field corresponds to
tRCD_rd in the DDR Specification.
15:11
RW
00000b
Same Rank Write To READ Delayed (C1sd_cr_wrsr_rd): This
field indicates the minimum allowed spacing (in DRAM clocks)
between the WRITE and READ commands to the same rank. This field
corresponds to tWTR in the DDR Specification.
10:8
RW
0000b
Different Ranks Write To READ Delayed (C1sd_cr_wrdr_rd):
This field indicates the minimum allowed spacing (in DRAM clocks)
between the WRITE and READ commands to different ranks. This field
corresponds to tWR_RD in the DDR Specification.
7:4
RW
0000b
Same Rank Read To Read Delayed (C1sd_cr_rdsr_rd): This field
indicates the minimum allowed spacing (in DRAM clocks) between two
READ commands to the same rank.
3:0
RW
0000b
Different Ranks Read To Read Delayed (C1sd_cr_rddr_rd): This
configuration register indicates the minimum allowed spacing (in
DRAM clocks) between two READ commands to different ranks. This
field corresponds to tRD_RD.
135
DRAM Controller Registers (D0:F0)
5.2.26
C1CKECTRL—Channel 1 CKE Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/MCHBAR
660–663h
00000800h
RW/L, RW, RO
32 bits
This register provides Channel 1 CKE Controls.
Bit
Access &
Default
Description
31:30
RW
00b
Number of clocks from internal ODT command start that
ODT Read Safe will be asserted (sd1_cr_odt_rdsafe):
Number of clocks from internal ODT command start that ODT Read
Safe will be asserted
29:28
RW
00b
Number of clocks from internal ODT command start that
ODT Read Safe will be asserted (sd1_cr_odt_wrsafe):
Number of clocks from internal ODT command start that ODT Write
Safe will be asserted
27
RW
0b
start the self-refresh exit sequence (sd1_cr_srcstart): This
field indicates the request to start the self-refresh exit sequence.
26:24
RW
000b
CKE pulse width requirement in high phase
(sd1_cr_cke_pw_hl_safe): This field indicates CKE pulse width
requirement in high phase. This field corresponds to tCKE (high) in
the DDR Specification.
23
RW
0b
Rank 3 Population (sd1_cr_rankpop3):
1 = Rank 3 populated
0 = Rank 3 not populated.
22
RW
0b
Rank 2 Population (sd1_cr_rankpop2):
1 = Rank 2 populated
0 = Rank 2 not populated
21
RW
0b
Rank 1 Population (sd1_cr_rankpop1):
1 = Rank 1 populated
0 = Rank 1 not populated.
20
RW
0b
Rank 0 Population (sd1_cr_rankpop0):
1 = Rank 0 populated
0 = Rank 0 not populated
136
19:17
RW
000b
CKE pulse width requirement in low phase
(sd1_cr_cke_pw_lh_safe): This configuration register indicates
CKE pulse width requirement in low phase. This field corresponds
to tCKE (low) in the DDR Specification.
16
RW
0b
Enable CKE toggle for PDN entry/exit (sd1_cr_pdn_enable):
This configuration bit indicates that the toggling of CKEs (for PDN
entry/exit) is enabled.
Datasheet
DRAM Controller Registers (D0:F0)
Bit
Access &
Default
Description
15
RW
0b
Read ODT Not Always Safe (sd1_cr_rdodtnas): Internal Read
ODT to CS is not always safe. Setting this bit selects the delay
(programmable) in the ODT Read Safe register field.
14
RW
0b
Write ODT Not Always Safe (sd1_cr_wrodtnas): Internal
Write ODT to CS is not always safe. Setting this bit selects the
delay (programmable) in the ODT Write Safe register field.
13:10
RW
0010b
Minimum Powerdown Exit to Non-Read command spacing
(sd1_cr_txp): This configuration register indicates the minimum
number of clocks to wait following assertion of CKE before issuing a
non-read command.
1010–1111 = Reserved.
0010–1001 = 2-9 clocks
0000–0001 = Reserved.
5.2.27
9:1
RW
000000000b
Self refresh exit count (sd1_cr_slfrfsh_exit_cnt): This
configuration register indicates the Self refresh exit count.
(Program to 255). This field corresponds to tXSNR/tXSRD in the DDR
Specification.
0
RW
0b
indicates only 1 DIMM populated (sd1_cr_singledimmpop):
This bit, when set, indicates that only 1 DIMM is populated.
C1REFRCTRL—Channel 1 DRAM Refresh Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/MCHBAR
669–66Eh
021830000C30h
RW, RO
48 bits
This register provides settings to configure the DRAM refresh controller.
Datasheet
Bit
Access &
Default
Description
47:42
RO
00h
41:37
RW
10000b
Direct Rcomp Quiet Window (DIRQUIET): This configuration
setting indicates the amount of refresh_tick events to wait before the
service of rcomp request in non-default mode of independent rank
refresh.
36:32
RW
11000b
Indirect Rcomp Quiet Window (INDIRQUIET): This configuration
setting indicates the amount of refresh_tick events to wait before the
service of rcomp request in non-default mode of independent rank
refresh.
31:27
RW
00110b
Rcomp Wait (RCOMPWAIT): This configuration setting indicates the
amount of refresh_tick events to wait before the service of rcomp
request in non-default mode of independent rank refresh.
Reserved
137
DRAM Controller Registers (D0:F0)
Bit
Access &
Default
Description
26
RO
0b
Reserved
25
RW
0b
Refresh Counter Enable (REFCNTEN): This bit is used to enable the
refresh counter to count during times that DRAM is not in self-refresh,
but refreshes are not enabled. Such a condition may occur due to need
to reprogram DIMMs following DRAM controller switch.
This bit has no effect when Refresh is enabled (i.e., there is no mode
where Refresh is enabled but the counter does not run). Thus, in
conjunction with bit 23 REFEN, the modes are:
REFEN:REFCNTEN
Description
0:0
Normal refresh disable
0:1
Refresh disabled, but counter is accumulating
refreshes.
1:X
Normal refresh enable
24
RW
0b
All Rank Refresh (ALLRKREF): This configuration bit enables (by
default) that all the ranks are refreshed in a staggered/atomic fashion.
If set, the ranks are refreshed in an independent fashion.
23
RW
0b
Refresh Enable (REFEN): Refresh is enabled.
0 = Disabled
1 = Enabled
22
RW
0b
DDR Initialization Done (INITDONE): Indicates that DDR
initialization is complete.
0 = Not Done
1 = Done
21:20
RO
00b
Reserved
19:18
RW
00b
DRAM Refresh Panic Watermark (REFPANICWM): When the
refresh count exceeds this level, a refresh request is launched to the
scheduler and the dref_panic flag is set.
00
01
10
11
17:16
RW
00b
5
6
7
8
DRAM Refresh High Watermark (REFHIGHWM): When the refresh
count exceeds this level, a refresh request is launched to the scheduler
and the dref_high flag is set.
00
01
10
11
138
=
=
=
=
=
=
=
=
3
4
5
6
Datasheet
DRAM Controller Registers (D0:F0)
Bit
Access &
Default
Description
15:14
RW
00b
DRAM Refresh Low Watermark (REFLOWWM): When the refresh
count exceeds this level, a refresh request is launched to the scheduler
and the dref_low flag is set.
00
01
10
11
13:0
RW
00110000
110000b
=
=
=
=
1
2
3
4
Refresh Counter Time Out Value (REFTIMEOUT): Program this
field with a value that will provide 7.8 us at the memory clock
frequency. At various memory clock frequencies this results in the
following values:
266 MHz -> 820h
333 MHz -> A28h
400 MHz -> C30h
5.2.28
C1ODTCTRL—Channel 1 ODT Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/MCHBAR
69C–69Fh
00000000h
RO, RW
32 bits
This register provides ODT controls.
Bit
Access &
Default
31:24
RO
00000h
23:20
RW
0001b
Description
Reserved
MCH ODT Latency (sd1_cr_modtl): Delay from CS# to GMCH
ODT assertion.
0000 = Reserved
0001–1100 = 1–12 clocks
1101–1111 = Reserved
19:17
RW
000b
CAS latency (sd1_cr_casl): (for CAS Latency)
This configuration register indicates the CAS latency of the memory
population. Also, termed as SDRAM to CAS latency.
000 = 3 memory clocks
001 = 4 memory clocks
…
111 = 10 memory clocks
16:0
Datasheet
RW
00000000h
Reserved
139
DRAM Controller Registers (D0:F0)
5.2.29
EPC0DRB0—ME Channel 0 DRAM Rank Boundary
Address 0
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
5.2.30
Bit
Access &
Default
15:10
RO
000000b
9:0
R/W
000h
0/0/0/MCHBAR
A00–A01h
0000h
R/W, RO
16 bits
Description
Reserved
Channel 0 Dram Rank Boundary Address 0 (C0DRBA0):
EPC0DRB1—ME Channel 0 DRAM Rank Boundary Address
1
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/MCHBAR
A02–A03h
0000h
RO, RW
16 bits
See C0DRB0 register.
140
Bit
Access &
Default
15:10
RO
000000b
9:0
RW
000h
Description
Reserved
Channel 0 Dram Rank Boundary Address 1 (C0DRBA1):
Datasheet
DRAM Controller Registers (D0:F0)
5.2.31
EPC0DRB2— ME Channel 0 DRAM Rank Boundary Address
2
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/MCHBAR
A04–A05h
0000h
RO, RW
16 bits
See C0DRB0 register.
5.2.32
Bit
Access &
Default
15:10
RO
000000b
9:0
RW
000h
Description
Reserved
Channel 0 DRAM Rank Boundary Address 2 (C0DRBA2):
EPC0DRB3— ME Channel 0 DRAM Rank Boundary Address
3
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/MCHBAR
A06–A07h
0000h
RW, RO
16 bits
See C0DRB0 register.
Datasheet
Bit
Access &
Default
15:10
RO
000000b
9:0
RW
000h
Description
Reserved
Channel 0 DRAM Rank Boundary Address 3 (C0DRBA3):
141
DRAM Controller Registers (D0:F0)
5.2.33
EPC0DRA01—ME Channel 0 DRAM Rank 0,1 Attribute
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/MCHBAR
A08–A09h
0000h
RW
16 bits
The DRAM Rank Attribute Registers define the page sizes/number of banks to be used
when accessing different ranks. These registers should be left with their default value
(all zeros) for any rank that is unpopulated, as determined by the corresponding
CxDRB registers. Each byte of information in the CxDRA registers describes the page
size of a pair of ranks. Channel and rank map:
Ch0
Ch0
Ch1
Ch1
5.2.34
Rank0,
Rank2,
Rank0,
Rank2,
1:
3:
1:
3:
108h – 109h
10Ah – 10Bh
188h – 189h
18Ah – 18Bh
Bit
Access &
Default
Description
15:8
RW
00h
Channel 0 DRAM Rank-1 Attributes (C0DRA1): This field defines
DRAM pagesize/number-of-banks for rank1 for given channel.
7:0
RW
00h
Channel 0 DRAM Rank-0 Attributes (C0DRA0): This field defines
DRAM pagesize/number-of-banks for rank0 for given channel.
EPC0DRA23—ME Channel 0 DRAM Rank 2,3 Attribute
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/MCHBAR
A0A–A0Bh
0000h
RW
16 bits
See C0DRA01 register.
142
Bit
Access &
Default
Description
15:8
RW
00h
Channel 0 DRAM Rank-3 Attributes (C0DRA3): This field defines
DRAM pagesize/number-of-banks for rank3 for given channel.
7:0
RW
00h
Channel 0 DRAM Rank-2 Attributes (C0DRA2): This field defines
DRAM pagesize/number-of-banks for rank2 for given channel.
Datasheet
DRAM Controller Registers (D0:F0)
5.2.35
EPDCYCTRKWRTPRE—EPD CYCTRK WRT PRE
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/MCHBAR
A19–A1Ah
0000h
RW, RO
16 bits
This register provides EPD CYCTRK WRT PRE Status.
5.2.36
Bit
Access &
Default
Description
15:11
RW
00000b
ACT to PRE Delayed (C0sd_cr_act_pchg): This field indicates the
minimum allowed spacing (in DRAM clocks) between the ACT and PRE
commands to the same rank-bank
10:6
RW
00000b
Write to PRE Delayed (C0sd_cr_wr_pchg): This field indicates the
minimum allowed spacing (in DRAM clocks) between the WRITE and
PRE commands to the same rank-bank
5:2
RW
0000b
READ to PRE Delayed (C0sd_cr_rd_pchg): This field indicates the
minimum allowed spacing (in DRAM clocks) between the READ and
PRE commands to the same rank-bank
1:0
RO
00b
Reserved
EPDCYCTRKWRTACT—EPD CYCTRK WRT ACT
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/MCHBAR
A1C–A1Fh
00000000h
RO, RW
32 bits
This register provides EPD CYCTRK WRT ACT Status.
Bit
Access &
Default
Description
31:21
RO
000h
20:17
RW
0000b
ACT to ACT Delayed (C0sd_cr_act_act[): This field indicates the
minimum allowed spacing (in DRAM clocks) between two ACT
commands to the same rank.
16:13
RW
0000b
PRE to ACT Delayed (C0sd_cr_pre_act): This field indicates the
minimum allowed spacing (in DRAM clocks) between the PRE and ACT
commands to the same rank-bank:12:9R/W0000bPRE-ALL to ACT
Delayed (C0sd_cr_preall_act):
Reserved
This field indicates the minimum allowed spacing (in DRAM clocks)
between the PRE-ALL and ACT commands to the same rank.
Datasheet
12:9
RO
0h
8:0
RW
00000000
0b
Reserved
REF to ACT Delayed (C0sd_cr_rfsh_act): This field indicates the
minimum allowed spacing (in DRAM clocks) between REF and ACT
commands to the same rank.
143
DRAM Controller Registers (D0:F0)
5.2.37
EPDCYCTRKWRTWR—EPD CYCTRK WRT WR
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/MCHBAR
A20–A21h
0000h
RW, RO
16 bits
This register provides EPD CYCTRK WRT WR Status.
5.2.38
Bit
Access &
Default
Description
15:12
RW
0h
ACT To Write Delay (C0sd_cr_act_wr): This configuration register
indicates the minimum allowed spacing (in DRAM clocks) between the
ACT and WRITE commands to the same rank-bank.
11:8
RW
0h
Same Rank Write To Write Delayed (C0sd_cr_wrsr_wr): This
configuration register indicates the minimum allowed spacing (in
DRAM clocks) between two WRITE commands to the same rank.
7:4
RO
0h
Reserved
3:0
RW
0h
Same Rank WRITE to READ Delay (C0sd_cr_rd_wr): This
configuration register indicates the minimum allowed spacing (in
DRAM clocks) between the WRITE and READ commands to the same
rank
EPDCYCTRKWRTRD—EPD CYCTRK WRT READ
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
BIOS Optimal Default
0/0/0/MCHBAR
A24–A26h
000000h
RW
24 bits
000h
This register provides EPD CYCTRK WRT RD Status.
144
Bit
Access &
Default
Description
23:23
RO
0h
22:20
RW
000b
19:18
RO
0h
Reserved
17:14
RW
0h
Min ACT To READ Delayed (C0sd_cr_act_rd): This field indicates
the minimum allowed spacing (in DRAM clocks) between the ACT and
READ commands to the same rank-bank.
Reserved
EPDunit DQS Slave DLL Enable to Read Safe (EPDSDLL2RD):
This field provides the setting for Read command safe from the point
of enabling the slave DLLs.
Datasheet
DRAM Controller Registers (D0:F0)
5.2.39
Bit
Access &
Default
Description
13:9
RW
00000b
Same Rank READ to WRITE Delayed (C0sd_cr_wrsr_rd): This
field indicates the minimum allowed spacing (in DRAM clocks) between
the READ and WRITE commands.
8:6
RO
0h
5:3
RW
000b
2:0
RO
0h
Reserved
Same Rank Read To Read Delayed (C0sd_cr_rdsr_rd): This field
indicates the minimum allowed spacing (in DRAM clocks) between two
READ commands to the same rank.
Reserved
EPDCKECONFIGREG—EPD CKE Related Configuration
Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
BIOS Optimal Default
0/0/0/MCHBAR
A28–A2Ch
00E0000000h
RW
40 bits
0h
This register provides CKE related configuration for EPD.
Bit
Access &
Default
39:35
RW
00000b
Description
EPDunit TXPDLL Count (EPDTXPDLL): This field specifies the delay
from precharge power down exit to a command that requires the
DRAM DLL to be operational. The commands are read/write.
34:32
RW
000b
EPDunit TXP count (EPDCKETXP): This field specifies the timing
requirement for Active power down exit or fast exit pre-charge power
down exit to any command or slow exit pre-charge power down to
Non-DLL (rd/wr/odt) command.
31:29
RW
111b
Mode Select (sd0_cr_sms): This field indicates the mode in which
the controller is operating in.
111 = indicates normal mode of operation, else special mode of
operation.
28:27
RW
00b
EPDunit EMRS command select. (EPDEMRSSEL): EMRS mode to
select BANK address.
01 = EMRS
10 = EMRS2
11 = EMRS3
26:24
Datasheet
RW
000b
CKE pulse width requirement in high phase
(sd0_cr_cke_pw_hl_safe): This field indicates CKE pulse width
requirement in high phase.
145
DRAM Controller Registers (D0:F0)
Bit
Access &
Default
Description
23:20
RW
0h
one-hot active rank population (ep_scr_actrank): This field
indicates the active rank in a one hot manner
19:17
RW
000b
CKE pulse width requirement in low phase
(sd0_cr_cke_pw_lh_safe): This field indicates CKE pulse width
requirement in low phase.
16:15
RO
0h
Reserved
14
RW
0b
EPDunit MPR mode (EPDMPR): MPR Read Mode
1 = MPR mode
0 = Normal mode
13
RW
0b
EPDunit Power Down enable for ODT Rank (EPDOAPDEN):
Configuration to enable the ODT ranks to dynamically enter power
down.
1 = Enable active power down.
0 = Disable active power down.
12
RW
0b
EPDunit Power Down enable for Active Rank (EPDAAPDEN):
Configuration to enable the active rank to dynamically enter power
down.
1 = Enable active power down.
0 = Disable active power down.
146
11:10
RO
0h
9:1
RW
00000000
0b
0
RW
0b
Reserved
Self refresh exit count (sd0_cr_slfrfsh_exit_cnt): This field
indicates the Self refresh exit count. (Program to 255)
indicates only 1 rank enabled (sd0_cr_singledimmpop): This
field indicates that only 1 rank is enabled.
Datasheet
DRAM Controller Registers (D0:F0)
5.2.40
MEMEMSPACE—ME Memory Space Configuration
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/MCHBAR
A2Eh
00h
R/W, RO
8 bits
This register provides settings to enable the ME memory space and define the size of
EP memory if enabled.
Bit
Access &
Default
7:5
RO
000b
4:0
R/W
00000b
Description
Reserved
ME-UMA(Sx) Region Size (EXRS): These bits are written by
firmware to indicate the desired size of ME-UMA(Sx) memory region.
This is done prior to bring up core power and allowing BIOS to
initialize memory. Within channel 0 DDR, the physical base address
for MEUMA(Sx) will be determined by:
ME-UMA(Sx)BASE = C0DRB3 – EXRS
This forces the ME-UMA(Sx) region to always be positioned at the top
of the memory populated in channel 0. The approved sizes for MEUMA(Sx) are values between 0000b (0MB, no ME-UMA(Sx) region)
and 10000b (16 MB ME – UMA(Sx) region)
Datasheet
147
DRAM Controller Registers (D0:F0)
5.2.41
EPDREFCONFIG—EP DRAM Refresh Configuration
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/MCHBAR
A30–A33h
40000C30h
RO, RW
32 bits
This register provides settings to configure the EPD refresh controller.
Bit
Access &
Default
Description
31
RO
0b
Reserved
30:29
RW
10b
EPDunit refresh count addition for self refresh exit.
(EPDREF4SR): Configuration indicating the number of additional
refreshes that needs to be added to the refresh request count after
exiting self refresh.
Typical value is to add 2 refreshes.
00 = Add 0 Refreshes
01 = Add 1 Refreshes
10 = Add 2 Refreshes
11 = Add 3 Refreshes
28
RW
0b
Refresh Counter Enable (REFCNTEN): This bit is used to enable
the refresh counter to count during times that DRAM is not in selfrefresh, but refreshes are not enabled. Such a condition may occur
due to need to reprogram DIMMs following DRAM controller switch.
This bit has no effect when Refresh is enabled (i.e. there is no mode
where Refresh is enabled but the counter does not run). Thus, in
conjunction with bit 23 REFEN, the modes are:
REFEN:REFCNTEN
27
RW
0b
Description
0:0
Normal refresh disable
0:1
Refresh disabled, but counter is accumulating
refreshes.
1:X
Normal refresh enable
Refresh Enable (REFEN):
0 = Disabled
1 = Enabled
26
RW
0b
DDR Initialization Done (INITDONE): Indicates that DDR
initialization is complete.
0 = Not Done
1 = Done
148
Datasheet
DRAM Controller Registers (D0:F0)
Bit
Access &
Default
Description
25:22
RO
0000b
Reserved
21:18
RW
0000b
DRAM Refresh High Watermark (REFHIGHWM): When the
refresh count exceeds this level, a refresh request is launched to the
scheduler and the dref_high flag is set.
0000 = 0
0001 = 1
.......
1000 = 8
17:14
RW
0000b
DRAM Refresh Low Watermark (REFLOWWM): When the refresh
count exceeds this level, a refresh request is launched to the
scheduler and the dref_low flag is set.
0000 = 0
0001 = 1
.......
1000 = 8
13:0
RW
00110000
110000b
Refresh Counter Time Out Value (REFTIMEOUT): Program this
field with a value that will provide 7.8 us at the memory clock
frequency. At various memory clock frequencies this results in the
following values:
266 MHz -> 820h
333 MHz -> A28h
400 MHz -> C30h
Datasheet
149
DRAM Controller Registers (D0:F0)
5.2.42
TSC1—Thermal Sensor Control 1
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/MCHBAR
CD8h
00h
RW/L, RW, RS/WC
8 bits
This register controls the operation of the thermal sensor. Bits 7:1 of this register are
reset to their defaults by CL_PWROK. Bit 0 is reset to its default by PLTRST#.
Bit
Access &
Default
7
RW/L
0b
Description
Thermal Sensor Enable (TSE): This bit enables power to the
thermal sensor. Lockable via TCO bit 7.
0 = Disabled
1 = Enabled
6
RO
0b
5:2
RW
0000b
Reserved
Digital Hysteresis Amount (DHA): This bit determines whether no
offset, 1 LSB, 2... 15 is used for hysteresis for the trip points.
0000 = digital hysteresis disabled, no offset added to trip
temperature
0001 = offset is 1 LSB added to each trip temperature when tripped
...
0110 = ~3.0 °C (Recommended setting)
...
1110 = added to each trip temperature when tripped
1111 = added to each trip temperature when tripped
1
RO
0b
0
RS/WC
0b
Reserved
In Use (IU): Software semaphore bit.
After a full GMCH RESET, a read to this bit returns a 0.
After the first read, subsequent reads will return a 1.
A write of a 1 to this bit will reset the next read value to 0.
Writing a 0 to this bit has no effect.
Software can poll this bit until it reads a 0, and will then own the
usage of the thermal sensor.
This bit has no other effect on the hardware, and is only used as a
semaphore among various independent software threads that may
need to use the thermal sensor.
Software that reads this register but does not intend to claim
exclusive access of the thermal sensor must write a one to this bit if it
reads a 0, in order to allow other software threads to claim it.
150
Datasheet
DRAM Controller Registers (D0:F0)
5.2.43
TSC2—Thermal Sensor Control 2
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/MCHBAR
CD9h
00h
RW/L, RO
8 bits
This register controls the operation of the thermal sensor. All bits in this register are
reset to their defaults by CL_PWROK.
Bit
Access &
Default
7:4
RO
0h
3:0
RW/L
0h
Description
Reserved
Thermometer Mode Enable and Rate (TE): These bits enable the
thermometer mode functions and set the Thermometer controller
rate.
The trip points (Catastrophic and Hot) will all operate using the
programmed trip points and Thermometer mode rate.
Note: During boot, all other thermometer mode registers (except
lock bits) should be programmed appropriately before
enabling the Thermometer Mode.
Lockable via TCO bit 7.
0000 = Thermometer mode disabled
0100 = enabled, 2048 clock mode (normal Thermometer mode
operation)
- provides ~7.68uS settling time @ 266MHz
- provides ~6.14us settling time @ 333MHz
- provides ~5.12us settling time @ 400MHz
0101 = enabled, 3072 clock mode
0110 = enabled, 4096 clock mode
0111 = enabled, 6144 clock mode
- provides ~23.1uS settling time @ 266MHz
- provides ~18.5us settling time @ 333MHz
- provides ~15.4uS settling time @ 400MHz
all other bit encodings are reserved
NOTE: The settling time for DAC and Thermal Diode is between 2 and
5 micro-seconds. To meet this requirement the SE value must
be programmed to be 5 micro-seconds or more.
Recommendation is to use 0100 setting.
Datasheet
151
DRAM Controller Registers (D0:F0)
5.2.44
TSS—Thermal Sensor Status
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/MCHBAR
CDAh
00h
RO
8 bits
This read only register provides trip point and other status of the thermal sensor. All
bits in this register are reset to their defaults by CL_PWROK.
Bit
Access &
Default
7
RO
0b
6
5:0
5.2.45
Description
Catastrophic Trip Indicator (CTI):
1 = Internal thermal sensor temperature is above the catastrophic
setting.
RO
0b
Hot Trip Indicator (HTI):
RO
0s
Reserved
1 = Internal thermal sensor temperature is above the Hot setting.
TSTTP—Thermal Sensor Temperature Trip Point
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/MCHBAR
CDC–CDFh
00000000h
RO, RW, RW/L
32 bits
This register sets the target values for the trip points.
All bits in this register are reset to their defaults by CL_PWROK.
Bit
Access &
Default
Description
31:16
RO
0000h
Reserved
15:8
RW/L
00h
Hot Trip Point Setting (HTPS): Sets the target value for the Hot
trip point.
Lockable via TCO bit 7.
7:0
RW/L
00h
Catastrophic Trip Point Setting (CTPS): Sets the target for the
Catastrophic trip point. See also TST[Direct DAC Connect Test
Enable].
Lockable via TCO bit 7.
152
Datasheet
DRAM Controller Registers (D0:F0)
5.2.46
TCO—Thermal Calibration Offset
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/MCHBAR
CE2h
00h
RW/L/K, RW/L
8 bits
Bit 7 is reset to its default by PLTRST#. Bits 6:0 are reset to their defaults by
CL_PWROK.
Bit
Access &
Default
Description
7
RW/L/K
0b
Lock Bit for Catastrophic (LBC): This bit, when written to a 1, locks
the Catastrophic programming interface, including bits 7:0 of this
register and bits 15:0 of TSTTP, bits 1,7 of TSC 1, bits 3:0 of TSC 2,
bits 4:0 of TSC 3, and bits 0,7 of TST. This bit may only be set to a 0
by a hardware reset (PLTRST#). Writing a 0 to this bit has no effect.
6:0
RW/L
00h
Calibration Offset (CO): This field contains the current calibration
offset for the Thermal Sensor DAC inputs. The calibration offset is a
twos complement signed number which is added to the temperature
counter value to help generate the final value going to the thermal
sensor DAC. This register is loaded by the hardware from fuses that
are blown during test.
This field is Read/Write, but should be kept at its default value as
programmed by the fuses in the part.
Note for TCO operation:
While this is a seven-bit field, the 7th bit is sign extended to 9 bits for
TCO operation. The range of 00h to 3Fh corresponds to 0 0000 0000
to 0 0011 1111. The range of 41h to 7fh corresponds to 1 1100 001
(i.e., negative 3fh) to 1 1111 1111 (i.e., negative 1), respectively.
Datasheet
153
DRAM Controller Registers (D0:F0)
5.2.47
THERM1—Hardware Throttle Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/MCHBAR
CE4h
00h
RW/L, RO, RW/L/K
8 bits
All bits in this register are reset to their defaults by PLTRST#.
Bit
Access &
Default
7:4
RO
00h
3
RW/L
00h
Description
Reserved
Halt on Catastrophic (HOC):
0 = Continue to toggle clocks when the catastrophic sensor trips.
1 = All clocks are disabled when the catastrophic sensor trips. A
system reset is required to bring the system out of a halt from the
thermal sensor.
2:1
RO
00b
0
RW/L/K
00h
Reserved
Hardware Throttling Lock Bit (HTL): This bit locks bits 7:0 of this
register.
0 = The register bits are unlocked.
1 = The register bits are locked. It may only be set to a 0 by a
hardware reset.
Writing a 0 to this bit has no effect.
5.2.48
TIS—Thermal Interrupt Status
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/MCHBAR
CEA–CEBh
0000h
RO, RWC
16 bits
This register is used to report if the temperature is rising or falling past the Hot Trip
Point. After an SMI# is asserted by the Hot Trip Point, SW can examine the current
state of the thermal zones by examining the TSS.
Software must write a 1 to clear the status bits in this register.
Following scenario is possible. An interrupt is initiated on a rising temperature trip, the
appropriate DMI cycles are generated, and eventually the software services the
interrupt and sees a rising temperature trip as the cause in the status bits for the
interrupts. Assume that the software then goes and clears the local interrupt status bit
in the TIS register for that trip event. It is possible at this point that a falling
temperature trip event occurs before the software has had the time to clear the global
interrupts status bit. But since software has already looked at the status register
before this event happened, software may not clear the local status flag for this event.
154
Datasheet
DRAM Controller Registers (D0:F0)
Therefore, after the global interrupt is cleared by software, software must look at the
instantaneous status in the TSS register.
All bits in this register are reset to their defaults by PLTRST#.
Bit
Access &
Default
Description
15:10
RO
00h
Reserved
9
RWC
0b
Was Catastrophic Thermal Sensor Interrupt Event (WCTSIE):
1 = Indicates that a Catastrophic Thermal Sensor trip based on a
higher to lower temperature transition thru the trip point
0 = No trip for this event
8
RWC
0b
Was Hot Thermal Sensor Interrupt Event (WHTSIE):
1 = Indicates that a Hot Thermal Sensor trip based on a higher to
lower temperature transition thru the trip point
0 = No trip for this event
7:5
RO
00b
Reserved
4
RWC
0b
Catastrophic Thermal Sensor Interrupt Event (CTSIE):
1 = Indicates that a Catastrophic Thermal Sensor trip event occurred
based on a lower to higher temperature transition thru the trip
point.
0 = No trip for this event Software must write a 1 to clear this status
bit.
3
RWC
0b
Hot Thermal Sensor Interrupt Event (HTSIE):
1 = Indicates that a Hot Thermal Sensor trip event occurred based on
a lower to higher temperature transition thru the trip point.
0 = No trip for this event Software must write a 1 to clear this status
bit.
2:0
Datasheet
RO
00b
Reserved
155
DRAM Controller Registers (D0:F0)
5.2.49
TSMICMD—Thermal SMI Command
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/MCHBAR
CF1h
00h
RO, RW
8 bits
This register selects specific errors to generate a SMI DMI special cycle, as enabled by
the Device 0 SMI Error Command Register [SMI on GMCH Thermal Sensor Trip].
All bits in this register are reset to their defaults by PLTRST#.
Bit
Access &
Default
Description
7:2
RO
00h
Reserved
1
RW
0b
SMI on GMCH Hot Thermal Sensor Trip (SMGHTST):
1 = Does not mask the generation of an SMI DMI special cycle on a
Hot thermal sensor trip.
0 = Disable reporting of this condition via SMI messaging.
0
156
RO
0b
Reserved
Datasheet
DRAM Controller Registers (D0:F0)
5.2.50
PMSTS—Power Management Status
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/MCHBAR
F14–F17h
00000000h
RWC/S, RO
32 bits
This register is Reset by PWROK only.
Bit
Access &
Default
31:9
RO
000000h
8
RWC/S
0b
Description
Reserved
Warm Reset Occurred (WRO): Set by the PMunit whenever a Warm
Reset is received, and cleared by PWROK=0.
0 = No Warm Reset occurred.
1 = Warm Reset occurred.
BIOS Requirement: BIOS can check and clear this bit whenever
executing POST code. This way BIOS knows that if the bit is set, then
the PMSTS bits [1:0] must also be set, and if not BIOS needs to
power-cycle the platform.
7:2
RO
00h
1
RWC/S
0b
Reserved
Channel 1 in Self-Refresh (C1SR): Set by power management
hardware after Channel 1 is placed in self refresh as a result of a
Power State or a Reset Warn sequence.
Cleared by Power management hardware before starting Channel 1
self refresh exit sequence initiated by a power management exit.
Cleared by the BIOS by writing a 1 in a warm reset (Reset# asserted
while PWROK is asserted) exit sequence.
0 = Channel 1 not ensured to be in self refresh.
1 = Channel 1 in Self Refresh.
0
RWC/S
0b
Channel 0 in Self-Refresh (C0SR): Set by power management
hardware after Channel 0 is placed in self refresh as a result of a
Power State or a Reset Warn sequence.
Cleared by Power management hardware before starting Channel 0
self refresh exit sequence initiated by a power management exit.
Cleared by the BIOS by writing a 1 in a warm reset (Reset# asserted
while PWROK is asserted) exit sequence.
0 = Channel 0 not ensured to be in self refresh.
1 = Channel 0 in Self Refresh.
Datasheet
157
DRAM Controller Registers (D0:F0)
5.3
MPBAR
Table 5-4. EPBAR Register Address Map
Address
Offset
5.3.1
Symbol
Register Name
Default
Value
Access
44–47h
EPESD
ME Element Self Description
00000201h
RO,
RWO
50–53h
EPLE1D
Controller Link Entry 1 Description
01000000h
RO,
RWO
58–5Fh
EPLE1A
Controller Link Entry 1 Address
0000000000
000000h
RO,
RWO
60–63h
EPLE2D
Controller Link Entry 2 Description
02000002h
RO,
RWO
68–6Fh
EPLE2A
Controller Link Entry 2 Address
0000000000
008000h
RO
EPESD—EP Element Self Description
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/PXPEPBAR
44–47h
00000201h
RO, RWO
32 bits
This register provides information about the root complex element containing this Link
Declaration Capability.
158
Bit
Access &
Default
Description
31:24
RO
00h
Port Number (PN): This field specifies the port number associated
with this element with respect to the component that contains this
element. A value of 00h indicates to configuration software that this
is the default Express port.
23:16
RWO
00h
Component ID (CID): This field indicates identifies the physical
component that contains this Root Complex Element.
15:8
RO
0sh
Number of Link Entries (NLE): This field indicates the number of
link entries following the Element Self Description. This field reports 2
(one each for PEG and DMI).
7:4
RO
0h
Reserved
3:0
RO
1h
Element Type (ET): This field indicates the type of the Root
Complex Element. Value of 1h represents a port to system memory.
Datasheet
DRAM Controller Registers (D0:F0)
5.3.2
EPLE1D—Controller Link Entry 1 Description
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/PXPEPBAR
50–53h
01000000h
RO, RWO
32 bits
This register provides the first part of a Link Entry which declares an internal link to
another Root Complex Element.
Bit
Access &
Default
Description
31:24
RO
01h
Target Port Number (TPN): Specifies the port number associated
with the element targeted by this link entry (DMI). The target port
number is with respect to the component that contains this element as
specified by the target component ID.
23:16
RWO
00h
Target Component ID (TCID): This field indicates the physical or
logical component that is targeted by this link entry.
15:2
RO
0000h
1
RO
0b
0
RWO
0b
Reserved
Link Type (LTYP): This field indicates that the link points to memorymapped space (for RCRB). The link address specifies the 64-bit base
address of the target RCRB.
Link Valid (LV):
0 = Link Entry is not valid and will be ignored.
1 = Link Entry specifies a valid link.
5.3.3
EPLE1A— Controller Link Entry 1 Address
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/PXPEPBAR
58–5Fh
0000000000000000h
RO, RWO
64 bits
This register provides the second part of a Link Entry which declares an internal link to
another Root Complex Element.
Datasheet
Bit
Access &
Default
63:32
RO
0s
31:12
RWO
0s
11:0
RO
0s
Description
Reserved
Link Address (LA): This field contains the memory mapped base
address of the RCRB that is the target element (DMI) for this link
entry.
Reserved
159
DRAM Controller Registers (D0:F0)
5.3.4
EPLE2D— Controller Link Entry 2 Description
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/PXPEPBAR
60–63h
02000002h
RO, RWO
32 bits
This register provides the first part of a Link Entry which declares an internal link to
another Root Complex Element.
Bit
Access &
Default
Description
31:24
RO
02h
Target Port Number (TPN): This field specifies the port number
associated with the element targeted by this link entry (PEG). The
target port number is with respect to the component that contains
this element as specified by the target component ID.
23:16
RWO
00h
Target Component ID (TCID): This field indicates the physical or
logical component that is targeted by this link entry. A value of 0 is
reserved. Component IDs start at 1. This value is a mirror of the
value in the Component ID field of all elements in this component.
15:2
RO
0s
Reserved
1
RO
1b
Link Type (LTYP): This field indicates that the link points to
configuration space of the integrated device which controls the x16
root port.
The link address specifies the configuration address (segment, bus,
device, function) of the target root port.
0
RWO
0b
Link Valid (LV):
0 = Link Entry is not valid and will be ignored.
1 = Link Entry specifies a valid link.
160
Datasheet
DRAM Controller Registers (D0:F0)
5.3.5
EPLE2A—EP Link Entry 2 Address
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/PXPEPBAR
68–6Fh
0000000000008000h
RO
64 bits
This register provides the second part of a Link Entry which declares an internal link to
another Root Complex Element.
Bit
Access &
Default
Description
63:28
RO
0s
Reserved
27:20
RO
0s
Bus Number (BUSN):
19:15
RO
00001b
14:12
RO
000b
11:0
RO
0s
Device Number (DEVN): Target for this link is PCI Express x16 port
(Device 1).
Function Number (FUNN):
Reserved
§
Datasheet
161
PCI Express* Registers (D1:F0)
6
PCI Express* Registers (D1:F0)
Device 1 (D1), Function 0 (F0) contains the controls associated with the PCI Express
x16 root port that is the intended to attach as the point for external graphics. It also
functions as the virtual PCI-to-PCI bridge.
Warning: When reading the PCI Express "conceptual" registers such as this, you may not get a
valid value unless the register value is stable.
The PCI Express* Specification defines two types of reserved bits.
Reserved and Preserved:
1.
Reserved for future RW implementations; software must preserve value read
for writes to bits.
2.
Reserved and Zero: Reserved for future R/WC/S implementations; software
must use 0 for writes to bits.
Unless explicitly documented as Reserved and Zero, all bits marked as reserved are
part of the Reserved and Preserved type, which have historically been the typical
definition for Reserved.
Note: Most (if not all) control bits in this device cannot be modified unless the link is down.
Software is required to first Disable the link, then program the registers, and then reenable the link (which will cause a full-retrain with the new settings).
Table 6-1. PCI Express* Register Address Map (D1:F0)
162
Address
Offset
Register
Symbol
00–01h
VID1
02–03h
DID1
04–05h
Register Name
Default
Value
Access
Vendor Identification
8086h
RO
Device Identification
29C1h
RO
PCICMD1
PCI Command
0000h
RO, RW
06–07h
PCISTS1
PCI Status
0010h
RO, RWC
08h
RID1
Revision Identification
00h
RO
09–0Bh
CC1
Class Code
060400h
RO
0Ch
CL1
Cache Line Size
00h
RW
0Eh
HDR1
Header Type
01h
RO
18h
PBUSN1
Primary Bus Number
00h
RO
19h
SBUSN1
Secondary Bus Number
00h
RW
1Ah
SUBUSN1
Subordinate Bus Number
00h
RW
1Ch
IOBASE1
I/O Base Address
F0h
RW, RO
Datasheet
PCI Express* Registers (D1:F0)
Datasheet
Address
Offset
Register
Symbol
1D
IOLIMIT1
1E–1Fh
SSTS1
20–21h
Register Name
Default
Value
Access
I/O Limit Address
00h
RW, RO
Secondary Status
0000h
RWC, RO
MBASE1
Memory Base Address
FFF0h
RW, RO
22–23h
MLIMIT1
Memory Limit Address
0000h
RW, RO
24–25h
PMBASE1
Prefetchable Memory Base Address
FFF1h
RW, RO
26–27h
PMLIMIT1
Prefetchable Memory Limit Address
0001h
RW, RO
28–2Bh
PMBASEU1
Prefetchable Memory Base Address
00000000h
RW,
2C–2Fh
PMLIMITU1
Prefetchable Memory Limit Address
00000000h
RW
34h
CAPPTR1
Capabilities Pointer
88h
RO
3Ch
INTRLINE1
Interrupt Line
00h
RW
3Dh
INTRPIN1
Interrupt Pin
01h
RO
3E–3Fh
BCTRL1
0000h
RO, RW
80–83h
PM_CAPID1
Power Management Capabilities
C8039001h
RO
84–87h
PM_CS1
Power Management Control/Status
00000000h
RO,
RW/S,
RW
88–8Bh
SS_CAPID
Subsystem ID and Vendor ID
Capabilities
0000800Dh
RO
8C–8Fh
SS
Subsystem ID and Subsystem
Vendor ID
00008086h
RWO
90–91h
MSI_CAPID
Message Signaled Interrupts
Capability ID
A005h
RO
92–93h
MC
Message Control
0000h
RW, RO
94–97h
MA
Message Address
00000000h
RW, RO
98–99h
MD
Message Data
0000h
RW
A0–A1h
PEG_CAPL
PCI Express-G Capability List
0010h
RO
A2–A3h
PEG_CAP
PCI Express-G Capabilities
0141h
RO,
RWO
A4–A7h
DCAP
Device Capabilities
00008000h
RO
A8–A9h
DCTL
Device Control
0000h
RO, RW
AA–ABh
DSTS
Device Status
0000h
RO, RWC
AC–AFh
LCAP
Link Capabilities
02014D01h
RO,
RWO
B0–B1h
LCTL
Link Control
0000h
RO, RW,
RW/SC
B2–B3h
LSTS
Link Status
1001h
RO
Bridge Control
163
PCI Express* Registers (D1:F0)
164
Address
Offset
Register
Symbol
Register Name
Default
Value
Access
B4–B7h
SLOTCAP
Slot Capabilities
00040000h
RWO,
RO
B8–B9h
SLOTCTL
Slot Control
01C0h
RO, RW
BA–BBh
SLOTSTS
Slot Status
0000h
RO, RWC
BC–BDh
RCTL
Root Control
0000h
RO, RW
C0– C3h
RSTS
Root Status
00000000h
RO, RWC
EC– EFh
PEGLC
PCI Express-G Legacy Control
00000000h
RW, RO
100–103h
VCECH
Virtual Channel Enhanced
Capability Header
14010002h
RO
104–107h
PVCCAP1
Port VC Capability Register 1
00000000h
RO
108–10Bh
PVCCAP2
Port VC Capability Register 2
00000000h
RO
10C–10Dh
PVCCTL
0000h
RO, RW
110–113h
VC0RCAP
VC0 Resource Capability
00000000h
RO
114–117h
VC0RCTL
VC0 Resource Control
800000FFh
RO, RW
11A–11Bh
VC0RSTS
VC0 Resource Status
0002h
RO
140–143h
RCLDECH
Root Complex Link Declaration
Enhanced
00010005h
RO
144–147h
ESD
Element Self Description
02000100h
RO,
RWO
150–153h
LE1D
Link Entry 1 Description
00000000h
RO,
RWO
158–15Fh
LE1A
Link Entry 1 Address
000000000
0000000h
RO,
RWO
218–21Fh
PEGSSTS
PCI Express-G Sequence Status
000000000
0000FFFh
RO
Port VC Control
Datasheet
PCI Express* Registers (D1:F0)
6.1
PCI Express* Configuration Register Details
(D1:F0)
6.1.1
VID1—Vendor Identification
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/1/0/PCI
00–01h
8086h
RO
16 bits
This register, combined with the Device Identification register, uniquely identify any
PCI device.
6.1.2
Bit
Access &
Default
15:0
RO
8086h
Description
Vendor Identification (VID1): PCI standard identification for Intel.
DID1—Device Identification
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/1/0/PCI
02–03h
29C1h
RO
16 bits
This register, combined with the Vendor Identification register, uniquely identifies any
PCI device.
Datasheet
Bit
Access &
Default
Description
15:8
RO
29h
Device Identification Number (DID1(UB)): Identifier assigned to
the GMCH device 1 (virtual PCI-to-PCI bridge, PCI Express Graphics
port).
7:4
RO
8h
Device Identification Number (DID1(HW)): Identifier assigned to
the GMCH device 1 (virtual PCI-to-PCI bridge, PCI Express Graphics
port)
3:0
RO
1h
Device Identification Number (DID1(LB)): Identifier assigned to
the GMCH device 1 (virtual PCI-to-PCI bridge, PCI Express Graphics
port).
165
PCI Express* Registers (D1:F0)
6.1.3
PCICMD1—PCI Command
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/1/0/PCI
04–05h
0000h
RO, RW
16 bits
Bit
Access &
Default
Description
15:11
RO
00h
Reserved
10
RW
0b
INTA Assertion Disable (INTAAD): This bit 0nly affects interrupts
generated by the device (PCI INTA from a PME or Hot Plug event)
controlled by this command register. It does not affect upstream MSIs,
upstream PCI INTA–INTD assert and de-assert messages.
0 = This device is permitted to generate INTA interrupt messages.
1 = This device is prevented from generating interrupt messages. Any
INTA emulation interrupts already asserted must be de-asserted
when this bit is set.
9
RO
0b
Fast Back-to-Back Enable (FB2B): Not Applicable or Implemented.
Hardwired to 0.
8
RW
0b
SERR# Message Enable (SERRE1): Controls Device 1 SERR#
messaging. The GMCH communicates the SERR# condition by sending
an SERR message to the ICH. This bit, when set, enables reporting of
non-fatal and fatal errors detected by the device to the Root Complex.
Note that errors are reported if enabled either through this bit or
through the PCI Express specific bits in the Device Control Register.
0 = The SERR message is generated by the GMCH for Device 1 only
under conditions enabled individually through the Device Control
Register.
1 = The GMCH is enabled to generate SERR messages which will be
sent to the ICH for specific Device 1 error conditions
generated/detected on the primary side of the virtual PCI to PCI
bridge (not those received by the secondary side). The status of
SERRs generated is reported in the PCISTS1 register.
7
RO
0b
Reserved: Not Applicable or Implemented. Hardwired to 0.
6
RW
0b
Parity Error Response Enable (PERRE): This bit controls whether
or not the Master Data Parity Error bit in the PCI Status register can
bet set.
0 = Master Data Parity Error bit in PCI Status register can NOT be set.
1 = Master Data Parity Error bit in PCI Status register CAN be set.
166
5
RO
0b
VGA Palette Snoop (VGAPS): Not Applicable or Implemented.
Hardwired to 0.
4
RO
0b
Memory Write and Invalidate Enable (MWIE): Not Applicable or
Implemented. Hardwired to 0.
Datasheet
PCI Express* Registers (D1:F0)
Bit
Access &
Default
Description
3
RO
0b
Special Cycle Enable (SCE): Not Applicable or Implemented.
Hardwired to 0.
2
RW
0b
Bus Master Enable (BME): This bit controls the ability of the PEG
port to forward Memory and IO Read/Write Requests in the upstream
direction. This bit does not affect forwarding of Completions from the
primary interface to the secondary interface.
0 = This device is prevented from making memory or IO requests to its
primary bus. Note that according to PCI Specification, as MSI
interrupt messages are in-band memory writes, disabling the bus
master enable bit prevents this device from generating MSI
interrupt messages or passing them from its secondary bus to its
primary bus. Upstream memory writes/reads, I/O writes/reads,
peer writes/reads, and MSIs will all be treated as invalid cycles.
Writes are forwarded to memory address 000C_0000h with byte
enables de-asserted. Reads will be forwarded to memory address
000C_0000h and will return Unsupported Request status (or
Master abort) in its completion packet.
1 = This device is allowed to issue requests to its primary bus.
Completions for previously issued memory read requests on the
primary bus will be issued when the data is available.
1
RW
0b
Memory Access Enable (MAE):
0 = All of device 1's memory space is disabled.
1 = Enable the Memory and Pre-fetchable memory address ranges
defined in the MBASE1, MLIMIT1, PMBASE1, and PMLIMIT1
registers.
0
RW
0b
IO Access Enable (IOAE):
0 = All of device 1's I/O space is disabled.
1 = Enable the I/O address range defined in the IOBASE1, and
IOLIMIT1 registers.
Datasheet
167
PCI Express* Registers (D1:F0)
6.1.4
PCISTS1—PCI Status
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/1/0/PCI
06–07h
0010h
RO, RWC
16 bits
This register reports the occurrence of error conditions associated with primary side of
the "virtual" Host-PCI Express bridge embedded within the GMCH.
Bit
Access &
Default
Description
15
RO
0b
Detected Parity Error (DPE): Not Applicable or Implemented.
Hardwired to 0. Parity (generating poisoned TLPs) is not supported
on the primary side of this device (error forwarding is not
performed).
14
RWC
0b
Signaled System Error (SSE): This bit is set when this Device
sends an SERR due to detecting an ERR_FATAL or ERR_NONFATAL
condition and the SERR Enable bit in the Command register is 1.
Both received (if enabled by BCTRL1[1]) and internally detected
error messages affect this field.
13
RO
0b
Received Master Abort Status (RMAS): Not Applicable or
Implemented. Hardwired to 0. The concept of a master abort does
not exist on primary side of this device.
12
RO
0b
Received Target Abort Status (RTAS): Not Applicable or
Implemented. Hardwired to 0. The concept of a target abort does
not exist on primary side of this device.
11
RO
0b
Signaled Target Abort Status (STAS): Not Applicable or
Implemented. Hardwired to 0. The concept of a target abort does
not exist on primary side of this device.
10:9
RO
DEVSELB Timing (DEVT): This device is not the subtractively
decoded device on bus 0. This bit field is therefore hardwired to 00
to indicate that the device uses the fastest possible decode.
8
RO
0b
Master Data Parity Error (PMDPE): Because the primary side of
the PEG's virtual PCI-to-PCI bridge is integrated with the GMCH
functionality there is no scenario where this bit will get set. Because
hardware will never set this bit, it is impossible for software to have
an opportunity to clear this bit or otherwise test that it is
implemented. The PCI specification defines it as a RWC, but for this
implementation an RO definition behaves the same way and will
meet all Microsoft testing requirements.
This bit can only be set when the Parity Error Enable bit in the PCI
Command register is set.
168
7
RO
0b
Fast Back-to-Back (FB2B): Not Applicable or Implemented.
Hardwired to 0.
6
RO
0b
Reserved
5
RO
0b
66/60MHz capability (CAP66): Not Applicable or Implemented.
Hardwired to 0.
Datasheet
PCI Express* Registers (D1:F0)
6.1.5
Bit
Access &
Default
Description
4
RO
1b
Capabilities List (CAPL): Indicates that a capabilities list is
present. Hardwired to 1.
3
RO
0b
INTA Status (INTAS): Indicates that an interrupt message is
pending internally to the device. Only PME and Hot Plug sources feed
into this status bit (not PCI INTA-INTD assert and de-assert
messages). The INTA Assertion Disable bit, PCICMD1[10], has no
effect on this bit.
2:0
RO
000b
Reserved
RID1—Revision Identification
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/1/0/PCI
08h
00h
RO
8 bits
This register contains the revision number of the GMCH device 1. These bits are read
only and writes to this register have no effect.
6.1.6
Bit
Access &
Default
Description
7:0
RO
00h
Revision Identification Number (RID1): This is an 8-bit value that
indicates the revision identification number for the GMCH Device 1.
Refer to the Intel® G35 Express Chipset Specification Update for the
value of the Revision ID register.
CC1—Class Code
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/1/0/PCI
09–0Bh
060400h
RO
24 bits
This register identifies the basic function of the device, a more specific sub-class, and
a register- specific programming interface.
Datasheet
Bit
Access &
Default
Description
23:16
RO
06h
Base Class Code (BCC): This field indicates the base class code for
this device. This code has the value 06h, indicating a Bridge device.
15:8
RO
04h
Sub-Class Code (SUBCC): This field indicates the sub-class code for
this device. The code is 04h indicating a PCI to PCI Bridge.
7:0
RO
00h
Programming Interface (PI): This field indicates the programming
interface of this device. This value does not specify a particular
register set layout and provides no practical use for this device.
169
PCI Express* Registers (D1:F0)
6.1.7
CL1—Cache Line Size
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
6.1.8
0/1/0/PCI
0Ch
00h
RW
8 bits
Bit
Access &
Default
Description
7:0
RW
00h
Cache Line Size (Scratch pad): Implemented by PCI Express
devices as a read-write field for legacy compatibility purposes but has
no impact on any PCI Express device functionality.
HDR1—Header Type
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/1/0/PCI
0Eh
01h
RO
8 bits
This register identifies the header layout of the configuration space. No physical
register exists at this location.
6.1.9
Bit
Access &
Default
7:0
RO
01h
Description
Header Type Register (HDR): Returns 01 to indicate that this is a
single function device with bridge header layout.
PBUSN1—Primary Bus Number
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/1/0/PCI
18h
00h
RO
8 bits
This register identifies that this "virtual" Host-PCI Express bridge is connected to PCI
bus #0.
170
Bit
Access &
Default
Description
7:0
RO
00h
Primary Bus Number (BUSN): Configuration software typically
programs this field with the number of the bus on the primary side of
the bridge. Since device 1 is an internal device and its primary bus is
always 0, these bits are read only and are hardwired to 0.
Datasheet
PCI Express* Registers (D1:F0)
6.1.10
SBUSN1—Secondary Bus Number
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/1/0/PCI
19h
00h
RW
8 bits
This register identifies the bus number assigned to the second bus side of the "virtual"
bridge (i.e., to PCI Express-G). This number is programmed by the PCI configuration
software to allow mapping of configuration cycles to PCI Express-G.
6.1.11
Bit
Access &
Default
7:0
RW
00h
Description
Secondary Bus Number (BUSN): This field is programmed by
configuration software with the bus number assigned to PCI Express.
SUBUSN1—Subordinate Bus Number
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/1/0/PCI
1Ah
00h
RW
8 bits
This register identifies the subordinate bus (if any) that resides at the level below PCI
Express-G. This number is programmed by the PCI configuration software to allow
mapping of configuration cycles to PCI Express-G.
Datasheet
Bit
Access &
Default
Description
7:0
RW
00h
Subordinate Bus Number (BUSN): This register is programmed by
configuration software with the number of the highest subordinate bus
that lies behind the Device 1 bridge. When only a single PCI device
resides on the PCI Express segment, this register will contain the
same value as the SBUSN1 register.
171
PCI Express* Registers (D1:F0)
6.1.12
IOBASE1—I/O Base Address
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/1/0/PCI
1Ch
F0h
RW, RO
8 bits
This register controls the processor to PCI Express-G I/O access routing based on the
following formula:
IO_BASE ≤ address ≤ IO_LIMIT
Only the upper 4 bits are programmable. For the purpose of address decode, address
bits A[11:0] are treated as 0. Thus the bottom of the defined I/O address range will
be aligned to a 4 KB boundary.
6.1.13
Bit
Access &
Default
Description
7:4
RW
Fh
I/O Address Base (IOBASE): This field corresponds to A[15:12] of
the I/O addresses passed by bridge 1 to PCI Express.
3:0
RO
0h
Reserved
IOLIMIT1—I/O Limit Address
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/1/0/PCI
1Dh
00h
RW, RO
8 bits
This register controls the processor to PCI Express-G I/O access routing based on the
following formula:
IO_BASE ≤ address ≤ IO_LIMIT
Only the upper 4 bits are programmable. For the purpose of address decode, address
bits A[11:0] are assumed to be FFFh. Thus, the top of the defined I/O address range
will be at the top of a 4 KB aligned address block.
172
Bit
Access &
Default
Description
7:4
RW
0h
I/O Address Limit (IOLIMIT): This field corresponds to A[15:12] of
the I/O address limit of device 1. Devices between this upper limit and
IOBASE1 will be passed to the PCI Express hierarchy associated with
this device.
3:0
RO
0h
Reserved
Datasheet
PCI Express* Registers (D1:F0)
6.1.14
SSTS1—Secondary Status
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/1/0/PCI
1E–1Fh
0000h
RWC, RO
16 bits
SSTS1 is a 16-bit status register that reports the occurrence of error conditions
associated with secondary side (i.e., PCI Express side) of the "virtual" PCI-PCI bridge
embedded within GMCH.
Datasheet
Bit
Access &
Default
Description
15
RWC
0b
Detected Parity Error (DPE): This bit is set by the Secondary Side
for a Type 1 Configuration Space header device whenever it receives
a Poisoned TLP, regardless of the state of the Parity Error Response
Enable bit in the Bridge Control Register.
14
RWC
0b
Received System Error (RSE): This bit is set when the Secondary
Side for a Type 1 configuration space header device receives an
ERR_FATAL or ERR_NONFATAL.
13
RWC
0b
Received Master Abort (RMA): This bit is set when the Secondary
Side for Type 1 Configuration Space Header Device (for requests
initiated by the Type 1 Header Device itself) receives a Completion
with Unsupported Request Completion Status.
12
RWC
0b
Received Target Abort (RTA): This bit is set when the Secondary
Side for Type 1 Configuration Space Header Device (for requests
initiated by the Type 1 Header Device itself) receives a Completion
with Completer Abort Completion Status.
11
RO
0b
Signaled Target Abort (STA): Not Applicable or Implemented.
Hardwired to 0. The GMCH does not generate Target Aborts (the
GMCH will never complete a request using the Completer Abort
Completion status).
10:9
RO
00b
DEVSEL# Timing (DEVT): Not Applicable or Implemented.
Hardwired to 0.
8
RWC
0b
Master Data Parity Error (SMDPE): When set, this bit indicates
that the GMCH received across the link (upstream) a Read Data
Completion Poisoned TLP (EP=1). This bit can only be set when the
Parity Error Enable bit in the Bridge Control register is set.
7
RO
0b
Fast Back-to-Back (FB2B): Not Applicable or Implemented.
Hardwired to 0.
6
RO
0b
Reserved
5
RO
0b
66/60 MHz capability (CAP66): Not Applicable or Implemented.
Hardwired to 0.
4:0
RO
00h
Reserved
173
PCI Express* Registers (D1:F0)
6.1.15
MBASE1—Memory Base Address
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/1/0/PCI
20–21h
FFF0h
RW, RO
16 bits
This register controls the processor-to-PCI Express non-prefetchable memory access
routing based on the following formula:
MEMORY_BASE ≤ address ≤ MEMORY_LIMIT
The upper 12 bits of the register are read/write and correspond to the upper 12
address bits A[31:20] of the 32 bit address. The bottom 4 bits of this register are
read-only and return zeroes when read. This register must be initialized by the
configuration software. For the purpose of address decode, address bits A[19:0] are
assumed to be 0. Thus, the bottom of the defined memory address range will be
aligned to a 1 MB boundary.
174
Bit
Access &
Default
Description
15:4
RW
FFFh
Memory Address Base (MBASE): This field corresponds to A[31:20]
of the lower limit of the memory range that will be passed to PCI
Express.
3:0
RO
0h
Reserved
Datasheet
PCI Express* Registers (D1:F0)
6.1.16
MLIMIT1—Memory Limit Address
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/1/0/PCI
22–23h
0000h
RW, RO
16 bits
This register controls the processor to PCI Express-G non-prefetchable memory access
routing based on the following formula:
MEMORY_BASE ≤ address ≤ MEMORY_LIMIT
The upper 12 bits of the register are read/write and correspond to the upper 12
address bits A[31:20] of the 32 bit address. The bottom 4 bits of this register are
read-only and return zeroes when read. This register must be initialized by the
configuration software. For the purpose of address decode, address bits A[19:0] are
assumed to be FFFFFh. Thus, the top of the defined memory address range will be at
the top of a 1MB aligned memory block. NOTE: Memory range covered by MBASE and
MLIMIT registers are used to map non-prefetchable PCI Express address ranges
(typically where control/status memory-mapped I/O data structures of the graphics
controller will reside) and PMBASE and PMLIMIT are used to map prefetchable address
ranges (typically graphics local memory). This segregation allows application of USWC
space attribute to be performed in a true plug-and-play manner to the prefetchable
address range for improved processor - PCI Express memory access performance.
Note also that configuration software is responsible for programming all address range
registers (prefetchable, non-prefetchable) with the values that provide exclusive
address ranges i.e. prevent overlap with each other and/or with the ranges covered
with the main memory. There is no provision in the GMCH hardware to enforce
prevention of overlap and operations of the system in the case of overlap are not
ensured.
Datasheet
Bit
Access &
Default
15:4
RW
000h
3:0
RO
0h
Description
Memory Address Limit (MLIMIT): This field corresponds to
A[31:20] of the upper limit of the address range passed to PCI
Express.
Reserved
175
PCI Express* Registers (D1:F0)
6.1.17
PMBASE1—Prefetchable Memory Base Address
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/1/0/PCI
24–25h
FFF1h
RW, RO
16 bits
This register in conjunction with the corresponding Upper Base Address register
controls the processor-to-PCI Express prefetchable memory access routing based on
the following formula:
PREFETCHABLE_MEMORY_BASE ≤ address ≤
PREFETCHABLE_MEMORY_LIMIT
The upper 12 bits of this register are read/write and correspond to address bits
A[31:20] of the 40-bit address. The lower 8 bits of the Upper Base Address register
are read/write and correspond to address bits A[39:32] of the 40-bit address. This
register must be initialized by the configuration software. For the purpose of address
decode, address bits A[19:0] are assumed to be 0. Thus, the bottom of the defined
memory address range will be aligned to a 1 MB boundary.
176
Bit
Access &
Default
15:4
RW
FFFh
3:0
RO
1h
Description
Prefetchable Memory Base Address (MBASE): This field
corresponds to A[31:20] of the lower limit of the memory range that
will be passed to PCI Express.
64-bit Address Support: This field indicates that the upper 32 bits of
the prefetchable memory region base address are contained in the
Prefetchable Memory base Upper Address register at 28h.
Datasheet
PCI Express* Registers (D1:F0)
6.1.18
PMLIMIT1—Prefetchable Memory Limit Address
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/1/0/PCI
26–27h
0001h
RW, RO
16 bits
This register in conjunction with the corresponding Upper Limit Address register
controls the processor-to-PCI Express prefetchable memory access routing based on
the following formula:
PREFETCHABLE_MEMORY_BASE ≤ address ≤ PREFETCHABLE_MEMORY_LIMIT
The upper 12 bits of this register are read/write and correspond to address bits
A[31:20] of the 40-bit address. The lower 8 bits of the Upper Limit Address register
are read/write and correspond to address bits A[39:32] of the 40-bit address. This
register must be initialized by the configuration software. For the purpose of address
decode, address bits A[19:0] are assumed to be FFFFFh. Thus, the top of the defined
memory address range will be at the top of a 1MB aligned memory block. Note that
prefetchable memory range is supported to allow segregation by the configuration
software between the memory ranges that must be defined as UC and the ones that
can be designated as a USWC (i.e. prefetchable) from the processor perspective.
Datasheet
Bit
Access &
Default
Description
15:4
RW
000h
Prefetchable Memory Address Limit (PMLIMIT): This field
corresponds to A[31:20] of the upper limit of the address range passed
to PCI Express.
3:0
RO
1h
64-bit Address Support: This field indicates that the upper 32 bits of
the prefetchable memory region limit address are contained in the
Prefetchable Memory Base Limit Address register at 2Ch
177
PCI Express* Registers (D1:F0)
6.1.19
PMBASEU1—Prefetchable Memory Base Address
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/1/0/PCI
28–2Bh
00000000h
RW
32 bits
The functionality associated with this register is present in the PEG design
implementation.
This register in conjunction with the corresponding Upper Base Address register
controls the processor-to-PCI Express prefetchable memory access routing based on
the following formula:
PREFETCHABLE_MEMORY_BASE ≤ address ≤ PREFETCHABLE_MEMORY_LIMIT
The upper 12 bits of this register are read/write and correspond to address bits
A[31:20] of the 40-bit address. The lower 8 bits of the Upper Base Address register
are read/write and correspond to address bits A[39:32] of the 40-bit address. This
register must be initialized by the configuration software. For the purpose of address
decode, address bits A[19:0] are assumed to be 0. Thus, the bottom of the defined
memory address range will be aligned to a 1 MB boundary.
178
Bit
Access &
Default
31:0
RW
00000000h
Description
Prefetchable Memory Base Address (MBASEU): This field
corresponds to A[63:32] of the lower limit of the prefetchable
memory range that will be passed to PCI Express.
Datasheet
PCI Express* Registers (D1:F0)
6.1.20
PMLIMITU1—Prefetchable Memory Limit Address
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/1/0/PCI
2C–2Fh
00000000h
RW
32 bits
The functionality associated with this register is present in the PEG design
implementation.
This register in conjunction with the corresponding Upper Limit Address register
controls the processor-to-PCI Express prefetchable memory access routing based on
the following formula:
PREFETCHABLE_MEMORY_BASE ≤ address ≤ PREFETCHABLE_MEMORY_LIMIT
The upper 12 bits of this register are read/write and correspond to address bits
A[31:20] of the 40- bit address. The lower 8 bits of the Upper Limit Address register
are read/write and correspond to address bits A[39:32] of the 40-bit address. This
register must be initialized by the configuration software. For the purpose of address
decode, address bits A[19:0] are assumed to be FFFFFh. Thus, the top of the defined
memory address range will be at the top of a 1MB aligned memory block.
Note that prefetchable memory range is supported to allow segregation by the
configuration software between the memory ranges that must be defined as UC and
the ones that can be designated as a USWC (i.e., prefetchable) from the processor
perspective.
Datasheet
Bit
Access &
Default
31:0
RW
00000000h
Description
Prefetchable Memory Address Limit (MLIMITU): This field
corresponds to A[63:32] of the upper limit of the prefetchable
Memory range that will be passed to PCI Express.
179
PCI Express* Registers (D1:F0)
6.1.21
CAPPTR1—Capabilities Pointer
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/1/0/PCI
34h
88h
RO
8 bits
The capabilities pointer provides the address offset to the location of the first entry in
this device's linked list of capabilities.
6.1.22
Bit
Access &
Default
7:0
RO
88h
Description
First Capability (CAPPTR1): The first capability in the list is the
Subsystem ID and Subsystem Vendor ID Capability.
INTRLINE1—Interrupt Line
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/1/0/PCI
3Ch
00h
RW
8 bits
This register contains interrupt line routing information. The device itself does not use
this value, rather it is used by device drivers and operating systems to determine
priority and vector information.
6.1.23
Bit
Access &
Default
7:0
RW
00h
Description
Interrupt Connection (INTCON): Used to communicate interrupt
line routing information.
INTRPIN1—Interrupt Pin
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/1/0/PCI
3Dh
01h
RO
8 bits
This register specifies which interrupt pin this device uses.
180
Bit
Access &
Default
Description
7:0
RO
01h
Interrupt Pin (INTPIN): As a single function device, the PCI Express
device specifies INTA as its interrupt pin. 01h=INTA.
Datasheet
PCI Express* Registers (D1:F0)
6.1.24
BCTRL1—Bridge Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/1/0/PCI
3E–3Fh
0000h
RO, RW
16 bits
This register provides extensions to the PCICMD1 register that are specific to PCI-toPCI bridges. The BCTRL provides additional control for the secondary interface (i.e.,
PCI Express) as well as some bits that affect the overall behavior of the "virtual" HostPCI Express bridge in the GMCH (e.g., VGA compatible address ranges mapping).
Bit
Access &
Default
Description
15:12
RO
0h
Reserved
11
RO
0b
Discard Timer SERR# Enable (DTSERRE): Not Applicable or
Implemented. Hardwired to 0.
10
RO
0b
Discard Timer Status (DTSTS): Not Applicable or Implemented.
Hardwired to 0.
9
RO
0b
Secondary Discard Timer (SDT): Not Applicable or Implemented.
Hardwired to 0.
8
RO
0b
Primary Discard Timer (PDT): Not Applicable or Implemented.
Hardwired to 0.
7
RO
0b
Fast Back-to-Back Enable (FB2BEN): Not Applicable or
Implemented. Hardwired to 0.
6
RW
0b
Secondary Bus Reset (SRESET): Setting this bit triggers a hot reset
on the corresponding PCI Express Port. This will force the LTSSM to
transition to the Hot Reset state (via Recovery) from L0, L0s, or L1
states.
5
RO
0b
Master Abort Mode (MAMODE): Does not apply to PCI Express.
Hardwired to 0.
4
RW
0b
VGA 16-bit Decode (VGA16D): This bit enables the PCI-to-PCI
bridge to provide 16-bit decoding of VGA I/O address precluding the
decoding of alias addresses every 1 KB. This bit only has meaning if
bit 3 (VGA Enable) of this register is also set to 1, enabling VGA I/O
decoding and forwarding by the bridge.
0 = Execute 10-bit address decodes on VGA I/O accesses.
1 = Execute 16-bit address decodes on VGA I/O accesses.
3
Datasheet
RW
0b
VGA Enable (VGAEN): This bit controls the routing of processor
initiated transactions targeting VGA compatible I/O and memory
address ranges.
181
PCI Express* Registers (D1:F0)
Bit
Access &
Default
2
RW
0b
Description
ISA Enable (ISAEN): Needed to exclude legacy resource decode to
route ISA resources to legacy decode path. This bit modifies the
response by the GMCH to an I/O access issued by the processor that
target ISA I/O addresses. This applies only to I/O addresses that are
enabled by the IOBASE and IOLIMIT registers.
0 = All addresses defined by the IOBASE and IOLIMIT for processor
I/O transactions will be mapped to PCI Express.
1 = GMCH will not forward to PCI Express any I/O transactions
addressing the last 768 bytes in each 1 KB block even if the
addresses are within the range defined by the IOBASE and
IOLIMIT registers.
1
RW
0b
SERR Enable (SERREN):
0 = No forwarding of error messages from secondary side to primary
side that could result in an SERR.
1 = ERR_COR, ERR_NONFATAL, and ERR_FATAL messages result in
SERR message when individually enabled by the Root Control
register.
0
RW
0b
Parity Error Response Enable (PEREN): This bit controls whether
or not the Master Data Parity Error bit in the Secondary Status
register is set when the GMCH receives across the link (upstream) a
Read Data Completion Poisoned TLP.
0 = Master Data Parity Error bit in Secondary Status register can NOT
be set.
1 = Master Data Parity Error bit in Secondary Status register CAN be
set.
182
Datasheet
PCI Express* Registers (D1:F0)
6.1.25
PM_CAPID1—Power Management Capabilities
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Datasheet
0/1/0/PCI
80–83h
C8039001h
RO
32 bits
Bit
Access &
Default
Description
31:27
RO
19h
PME Support (PMES): This field indicates the power states in which
this device may indicate PME wake via PCI Express messaging. D0,
D3hot & D3cold. This device is not required to do anything to support
D3hot & D3cold, it simply must report that those states are
supported. Refer to the PCI Power Management 1.1 specification for
encoding explanation and other power management details.
26
RO
0b
D2 Power State Support (D2PSS): Hardwired to 0 to indicate that
the D2 power management state is NOT supported.
25
RO
0b
D1 Power State Support (D1PSS): Hardwired to 0 to indicate that
the D1 power management state is NOT supported.
24:22
RO
000b
Auxiliary Current (AUXC): Hardwired to 0 to indicate that there are
no 3.3Vaux auxiliary current requirements.
21
RO
0b
Device Specific Initialization (DSI): Hardwired to 0 to indicate
that special initialization of this device is NOT required before generic
class device driver is to use it.
20
RO
0b
Auxiliary Power Source (APS): Hardwired to 0.
19
RO
0b
PME Clock (PMECLK): Hardwired to 0 to indicate this device does
NOT support PME# generation.
18:16
RO
011b
15:8
RO
90h
Pointer to Next Capability (PNC): This contains a pointer to the
next item in the capabilities list. If MSICH (CAPL[0] @ 7Fh) is 0, then
the next item in the capabilities list is the Message Signaled
Interrupts (MSI) capability at 90h.
7:0
RO
01h
Capability ID (CID): Value of 01h identifies this linked list item
(capability structure) as being for PCI Power Management registers.
PCI PM CAP Version (PCIPMCV): A value of 011b indicates that this
function complies with revision 1.2 of the PCI Power Management
Interface Specification.
183
PCI Express* Registers (D1:F0)
6.1.26
PM_CS1—Power Management Control/Status
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/1/0/PCI
84–87h
00000000h
RO, RW/S, RW
32 bits
Bit
Access &
Default
Description
31:16
RO
0000h
15
RO
0b
PME Status (PMESTS): Indicates that this device does not support
PME# generation from D3cold.
14:13
RO
00b
Data Scale (DSCALE): Indicates that this device does not support
the power management data register.
12:9
RO
0h
Data Select (DSEL): Indicates that this device does not support the
power management data register.
8
RW/S
0b
Reserved: Not Applicable or Implemented. Hardwired to 0.
PME Enable (PMEE): Indicates that this device does not generate
PMEB assertion from any D-state.
0 = PME# generation not possible from any D State
1 = PME# generation enabled from any D State
The setting of this bit has no effect on hardware.
See PM_CAP[15:11]
7:2
RO
00h
Reserved
1:0
RW
00b
Power State (PS): This field indicates the current power state of this
device and can be used to set the device into a new power state. If
software attempts to write an unsupported state to this field, write
operation must complete normally on the bus, but the data is
discarded and no state change occurs.
00
01
10
11
=
=
=
=
D0
D1 (Not supported in this device.
D2 (Not supported in this device.)
D3
Support of D3cold does not require any special action.
While in the D3hot state, this device can only act as the target of PCI
configuration transactions (for power management control). This
device also cannot generate interrupts or respond to MMR cycles in
the D3 state. The device must return to the D0 state to be fullyfunctional.
When the Power State is other than D0, the bridge will Master Abort
(i.e., not claim) any downstream cycles (with exception of type 0
configuration cycles). Consequently, these unclaimed cycles will go
down DMI and come back up as Unsupported Requests, which the
GMCH logs as Master Aborts in Device 0 PCISTS[13].
There is no additional hardware functionality required to support these
Power States.
184
Datasheet
PCI Express* Registers (D1:F0)
6.1.27
SS_CAPID—Subsystem ID and Vendor ID Capabilities
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/1/0/PCI
88–8Bh
0000800Dh
RO
32 bits
This capability is used to uniquely identify the subsystem where the PCI device
resides. Because this device is an integrated part of the system and not an add-in
device, it is anticipated that this capability will never be used. However, it is necessary
because Microsoft will test for its presence.
6.1.28
Bit
Access &
Default
Description
31:16
RO
0000h
15:8
RO
80h
Pointer to Next Capability (PNC): This contains a pointer to the
next item in the capabilities list which is the PCI Power Management
capability.
7:0
RO
0Dh
Capability ID (CID): Value of 0Dh identifies this linked list item
(capability structure) as being for SSID/SSVID registers in a PCI-toPCI Bridge.
Reserved
SS—Subsystem ID and Subsystem Vendor ID
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/1/0/PCI
8C–8Fh
00008086h
RWO
32 bits
System BIOS can be used as the mechanism for loading the SSID/SVID values. These
values must be preserved through power management transitions and a hardware
reset.
Datasheet
Bit
Access &
Default
Description
31:16
RWO
0000h
Subsystem ID (SSID): Identifies the particular subsystem and is
assigned by the vendor.
15:0
RWO
8086h
Subsystem Vendor ID (SSVID): Identifies the manufacturer of the
subsystem and is the same as the vendor ID which is assigned by
the PCI Special Interest Group.
185
PCI Express* Registers (D1:F0)
6.1.29
MSI_CAPID—Message Signaled Interrupts Capability ID
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/1/0/PCI
90–91h
A005h
RO
16 bits
When a device supports MSI it can generate an interrupt request to the processor by
writing a predefined data item (a message) to a predefined memory address.
6.1.30
Bit
Access &
Default
Description
15:8
RO
A0h
Pointer to Next Capability (PNC): This contains a pointer to the
next item in the capabilities list which is the PCI Express capability.
7:0
RO
05h
Capability ID (CID): Value of 05h identifies this linked list item
(capability structure) as being for MSI registers.
MC—Message Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/1/0/PCI
92–93h
0000h
RW, RO
16 bits
System software can modify bits in this register, but the device is prohibited from
doing so.
If the device writes the same message multiple times, only one of those messages is
ensured to be serviced. If all of them must be serviced, the device must not generate
the same message again until the driver services the earlier one.
Bit
Access &
Default
Description
15:8
RO
00h
Reserved
7
RO
0b
64-bit Address Capable (64AC): Hardwired to 0 to indicate that the
function does not implement the upper 32 bits of the Message Address
register and is incapable of generating a 64-bit memory address.
6:4
RW
000b
Multiple Message Enable (MME): System software programs this
field to indicate the actual number of messages allocated to this
device. This number will be equal to or less than the number actually
requested.
The encoding is the same as for the MMC field below.
3:1
RO
000b
Multiple Message Capable (MMC): System software reads this field
to determine the number of messages being requested by this device.
000 = 1 message requested
All others are reserved.
186
Datasheet
PCI Express* Registers (D1:F0)
Bit
Access &
Default
0
RW
0b
Description
MSI Enable (MSIEN): This bit controls the ability of this device to
generate MSIs.
0 = MSI will not be generated.
1 = MSI will be generated when we receive PME or HotPlug messages.
INTA will not be generated and INTA Status (PCISTS1[3]) will not
be set.
6.1.31
MA—Message Address
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
6.1.32
0/1/0/PCI
94–97h
00000000h
RW, RO
32 bits
Bit
Access &
Default
Description
31:2
RW
00000000h
Message Address (MA): Used by system software to assign an MSI
address to the device. The device handles an MSI by writing the
padded contents of the MD register to this address.
1:0
RO
00b
Force DWord Align (FDWA): Hardwired to 0 so that addresses
assigned by system software are always aligned on a DWord address
boundary.
MD—Message Data
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Bit
Access &
Default
15:0
RW
0000h
0/1/0/PCI
98–99h
0000h
RW
16 bits
Description
Message Data (MD): Base message data pattern assigned by
system software and used to handle an MSI from the device.
When the device must generate an interrupt request, it writes a 32-bit
value to the memory address specified in the MA register. The upper
16 bits are always set to 0. The lower 16 bits are supplied by this
register.
Datasheet
187
PCI Express* Registers (D1:F0)
6.1.33
PEG_CAPL—PCI Express*-G Capability List
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/1/0/PCI
A0–A1h
0010h
RO
16 bits
This register enumerates the PCI Express capability structure.
6.1.34
Bit
Access &
Default
Description
15:8
RO
00h
Pointer to Next Capability (PNC): This value terminates the
capabilities list. The Virtual Channel capability and any other PCI
Express specific capabilities that are reported via this mechanism are
in a separate capabilities list located entirely within PCI Express
Extended Configuration Space.
7:0
RO
10h
Capability ID (CID): Identifies this linked list item (capability
structure) as being for PCI Express registers.
PEG_CAP—PCI Express*-G Capabilities
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/1/0/PCI
A2–A3h
0141h
RO, RWO
16 bits
This register indicates PCI Express device capabilities.
Bit
Access &
Default
Description
15:14
RO
00b
Reserved
13:9
RO
00h
Interrupt Message Number (IMN): Not Applicable or
Implemented. Hardwired to 0.
8
RWO
1b
Slot Implemented (SI):
0 = The PCI Express Link associated with this port is connected to an
integrated component or is disabled.
1 = The PCI Express Link associated with this port is connected to a
slot.
188
7:4
RO
4h
Device/Port Type (DPT): Hardwired to 4h to indicate root port of
PCI Express Root Complex.
3:0
RO
1h
PCI Express Capability Version (PCI EXPRESS*CV): Hardwired
to 1 as it is the first version.
Datasheet
PCI Express* Registers (D1:F0)
6.1.35
DCAP—Device Capabilities
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/1/0/PCI
A4–A7h
00008000h
RO
32 bits
This register indicates PCI Express device capabilities.
Datasheet
Bit
Access &
Default
Description
31:16
RO
0000h
15
RO
1b
14:6
RO
000h
5
RO
0b
Extended Tag Field Supported (ETFS): Hardwired to indicate
support for 5-bit Tags as a Requestor.
4:3
RO
00b
Phantom Functions Supported (PFS): Not Applicable or
Implemented. Hardwired to 0.
2:0
RO
000b
Reserved: Not Applicable or Implemented. Hardwired to 0.
Role Based Error Reporting (RBER): This bit indicates that this
device implements the functionality defined in the Error Reporting ECN
as required by the PCI Express 1.1 specification.
Reserved: Not Applicable or Implemented. Hardwired to 0.
Max Payload Size (MPS): Hardwired to indicate 128B max supported
payload for Transaction Layer Packets (TLP).
189
PCI Express* Registers (D1:F0)
6.1.36
DCTL—Device Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/1/0/PCI
A8–A9h
0000h
RO, RW
16 bits
This register provides control for PCI Express device specific capabilities.
The error reporting enable bits are in reference to errors detected by this device, not
error messages received across the link. The reporting of error messages (ERR_CORR,
ERR_NONFATAL, ERR_FATAL) received by Root Port is controlled exclusively by Root
Port Command Register.
Bit
Access &
Default
Description
15:8
RO
000h
Reserved
7:5
RW
000b
Max Payload Size (MPS):
000 = 128B max supported payload for Transaction Layer Packets
(TLP). As a receiver, the Device must handle TLPs as large as
the set value; as transmitter, the Device must not generate
TLPs exceeding the set value.
All other encodings are reserved.
Hardware will actually ignore this field. It is writeable only to support
compliance testing.
190
4
RO
0b
Reserved: For Enable Relaxed Ordering
3
RW
0b
Unsupported Request Reporting Enable (URRE): When set,
allows signaling ERR_NONFATAL, ERR_FATAL, or ERR_CORR to the
Root Control register when detecting an unmasked Unsupported
Request (UR). An ERR_CORR is signaled when an unmasked Advisory
Non-Fatal UR is received. An ERR_FATAL or ERR_NONFATAL is sent to
the Root Control register when an uncorrectable non-Advisory UR is
received with the severity bit set in the Uncorrectable Error Severity
register.
2
RW
0b
Fatal Error Reporting Enable (FERE): When set, enables signaling
of ERR_FATAL to the Root Control register due to internally detected
errors or error messages received across the link. Other bits also
control the full scope of related error reporting.
1
RW
0b
Non-Fatal Error Reporting Enable (NERE): When set, enables
signaling of ERR_NONFATAL to the Root Control register due to
internally detected errors or error messages received across the link.
Other bits also control the full scope of related error reporting.
0
RW
0b
Correctable Error Reporting Enable (CERE): When set, enables
signaling of ERR_CORR to the Root Control register due to internally
detected errors or error messages received across the link. Other bits
also control the full scope of related error reporting.
Datasheet
PCI Express* Registers (D1:F0)
6.1.37
DSTS—Device Status
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/1/0/PCI
AA–ABh
0000h
RO, RWC
16 bits
This register reflects status corresponding to controls in the Device Control register.
The error reporting bits are in reference to errors detected by this device, not errors
messages received across the link.
Bit
Access &
Default
15:6
RO
000h
5
RO
0b
Description
Reserved and Zero: For future R/WC/S implementations; software
must use 0 for writes to bits.
Transactions Pending (TP):
0 = All pending transactions (including completions for any outstanding
non-posted requests on any used virtual channel) have been
completed.
1 = Device has transaction(s) pending (including completions for any
outstanding non-posted requests for all used Traffic Classes).
4
RO
0b
3
RWC
0b
Reserved
Unsupported Request Detected (URD):
0 = Unsupported request Not detected.
1 = Device received an Unsupported Request. Errors are logged in this
register regardless of whether error reporting is enabled or not in
the Device Control Register.
Additionally, the Non-Fatal Error Detected bit or the Fatal Error
Detected bit is set according to the setting of the Unsupported Request
Error Severity bit. In production systems setting the Fatal Error
Detected bit is not an option as support for AER will not be reported.
2
RWC
0b
Fatal Error Detected (FED):
0 = Fatal error Not detected.
1 = Fatal error(s) were detected. Errors are logged in this register
regardless of whether error reporting is enabled or not in the
Device Control register.
When Advanced Error Handling is enabled, errors are logged in this
register regardless of the settings of the uncorrectable error mask
register.
Datasheet
191
PCI Express* Registers (D1:F0)
Bit
Access &
Default
1
RWC
0b
Description
Non-Fatal Error Detected (NFED):
0 = Non-Fatal error Not detected.
1 = Non-fatal error(s) were detected. Errors are logged in this register
regardless of whether error reporting is enabled or not in the
Device Control register.
When Advanced Error Handling is enabled, errors are logged in this
register regardless of the settings of the uncorrectable error mask
register.
0
RWC
0b
Correctable Error Detected (CED):
0 = Correctable error Not detected.
1 = Correctable error(s) were detected. Errors are logged in this
register regardless of whether error reporting is enabled or not in
the Device Control register.
When Advanced Error Handling is enabled, errors are logged in this
register regardless of the settings of the correctable error mask
register.
6.1.38
LCAP—Link Capabilities
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/1/0/PCI
AC–AFh
02014D01h
RO, RWO
32 bits
This register indicates PCI Express device specific capabilities.
Bit
Access &
Default
Description
31:24
RO
02h
Port Number (PN): This field indicates the PCI Express port number
for the given PCI Express link. Matches the value in Element Self
Description[31:24].
23:21
RO
000b
20
RO
0b
Reserved
Data Link Layer Link Active Reporting Capable (DLLLARC): For
a Downstream Port, this bit must be set to 1b if the component
supports the optional capability of reporting the DL_Active state of the
Data Link Control and Management State Machine. For a hot-plug
capable Downstream Port (as indicated by the Hot-Plug Capable field
of the Slot Capabilities register), this bit must be set to 1b.
For Upstream Ports and components that do not support this optional
capability, this bit must be hardwired to 0b.
19
RO
0b
Surprise Down Error Reporting Capable (SDERC): For a
Downstream Port, this bit must be set to 1b if the component
supports the optional capability of detecting and reporting a Surprise
Down error condition.
For Upstream Ports and components that do not support this optional
capability, this bit must be hardwired to 0b.
192
Datasheet
PCI Express* Registers (D1:F0)
Bit
Access &
Default
Description
18
RO
0b
Clock Power Management (CPM): A value of 1b in this bit indicates
that the component tolerates the removal of any reference clock(s)
when the link is in the L1 and L2/3 Ready link states. A value of 0b
indicates the component does not have this capability and that
reference clock(s) must not be removed in these link states.
This capability is applicable only in form factors that support “clock
request” (CLKREQ#) capability.
For a multi-function device, each function indicates its capability
independently. Power Management configuration software must only
permit reference clock removal if all functions of the multifunction
device indicate a 1b in this bit.
17:15
RWO
010b
L1 Exit Latency (L1ELAT): This field indicates the length of time
this Port requires to complete the transition from L1 to L0. The value
010 b indicates the range of 2 us to less than 4 us.
Both bytes of this register that contain a portion of this field must be
written simultaneously in order to prevent an intermediate (and
undesired) value from ever existing.
14:12
RO
100b
L0s Exit Latency (L0SELAT): Indicates the length of time this Port
requires to complete the transition from L0s to L0.
000
001
010
011
100
101
110
111
=
=
=
=
=
=
=
=
Less than 64 ns
64ns to less than 128ns
128ns to less than 256 ns
256ns to less than 512 ns
512ns to less than 1 us
1 us to less than 2 us
2 us – 4 us
More than 4 us
The actual value of this field depends on the common Clock
Configuration bit (LCTL[6]) and the Common and Non-Common clock
L0s Exit Latency values in PEGL0SLAT (Offset 22Ch)
11:10
Datasheet
RWO
11b
Active State Link PM Support (ASLPMS):
9:4
RO
10h
Max Link Width (MLW): This field indicates the maximum number
of lanes supported for this link.
3:0
RO
1h
Max Link Speed (MLS): Hardwired to indicate 2.5 Gb/s.
BIOS Requirement: Desktop chipsets do not support ASPM L1, so
BIOS should program this field to 01.
193
PCI Express* Registers (D1:F0)
6.1.39
LCTL—Link Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
BIOS Optimal Default
0/1/0/PCI
B0–B1h
0000h
RO, RW, RW/SC
16 bits
0h
This register allows control of PCI Express link.
Bit
Access &
Default
15:9
RO
0000000b
8
RO
0b
Description
Reserved
Enable Clock Power Management (ECPM): Applicable only for form
factors that support a “Clock Request” (CLKREQ#) mechanism, this
enable functions as follows
0 = Disable. Clock power management is disabled and device must
hold CLKREQ# signal low (Default)
1 = Enable. Device is permitted to use CLKREQ# signal to power
manage link clock according to protocol defined in appropriate
form factor specification.
Components that do not support Clock Power Management (as
indicated by a 0b value in the Clock Power Management bit of the Link
Capabilities Register) must hardwire this bit to 0b.
7
RW
0b
Extended Synch (ES):
0 = Standard Fast Training Sequence (FTS).
1 = Forces the transmission of additional ordered sets when exiting the
L0s state and when in the Recovery state.
This mode provides external devices (e.g., logic analyzers) monitoring
the Link time to achieve bit and symbol lock before the link enters L0
and resumes communication.
This is a test mode only and may cause other undesired side effects
such as buffer overflows or underruns.
6
RW
0b
Common Clock Configuration (CCC): The state of this bit affects
the L0s Exit Latency reported in LCAP[14:12] and the N_FTS value
advertised during link training. See PEGL0SLAT at offset 22Ch.
0 = This component and the component at the opposite end of this
Link are operating with asynchronous reference clock.
1 = This component and the component at the opposite end of this
Link are operating with a distributed common reference clock.
5
RW/SC
0b
Retrain Link (RL): This bit always returns 0 when read. This bit is
cleared automatically (no need to write a 0).
0 = Normal operation.
1 = Full Link retraining is initiated by directing the Physical Layer
LTSSM from L0, L0s, or L1 states to the Recovery state.
194
Datasheet
PCI Express* Registers (D1:F0)
Bit
Access &
Default
4
RW
0b
Description
Link Disable (LD): Writes to this bit are immediately reflected in the
value read from the bit, regardless of actual Link state.
0 = Normal operation
1 = Link is disabled. Forces the LTSSM to transition to the Disabled
state (via Recovery) from L0, L0s, or L1 states. Link retraining
happens automatically on 0 to 1 transition, just like when coming
out of reset.
3
RO
0b
Read Completion Boundary (RCB): Hardwired to 0 to indicate
64 byte.
2
RW
0b
Far-End Digital Loopback (FEDLB):
1:0
RW
00b
Active State PM (ASPM): This field controls the level of active state
power management supported on the given link.
00 = Disabled
01 = L0s Entry Supported
10 = Reserved
11 = L0s and L1 Entry Supported
Datasheet
195
PCI Express* Registers (D1:F0)
6.1.40
LSTS—Link Status
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/1/0/PCI
B2–B3h
1001h
RO
16 bits
This register indicates PCI Express link status.
“
Bit
Access &
Default
Description
15:14
RO
00b
Reserved and Zero: For future R/WC/S implementations; software
must use 0 for writes to bits.
13
RO
0b
Data Link Layer Link Active (Optional) (DLLLA): This bit
indicates the status of the Data Link Control and Management State
Machine. It returns a 1b to indicate the DL_Active state, 0b
otherwise.
This bit must be implemented if the corresponding Data Link Layer
Active Capability bit is implemented. Otherwise, this bit must be
hardwired to 0b.
12
RO
1b
Slot Clock Configuration (SCC):
0 = The device uses an independent clock irrespective of the presence
of a reference on the connector.
1 = The device uses the same physical reference clock that the
platform provides on the connector.
11
RO
0b
Link Training (LTRN): This bit indicates that the Physical Layer
LTSSM is in the Configuration or Recovery state, or that 1b was
written to the Retrain Link bit but Link training has not yet begun.
Hardware clears this bit when the LTSSM exits the
Configuration/Recovery state once Link training is complete.
10
RO
0b
Undefined: The value read from this bit is undefined. In previous
versions of this specification, this bit was used to indicate a Link
Training Error. System software must ignore the value read from this
bit. System software is permitted to write any value to this bit.
9:4
RO
00h
Negotiated Width (NW): Indicates negotiated link width. This field
is valid only when the link is in the L0, L0s, or L1 states (after link
width negotiation is successfully completed).
00h
01h
02h
04h
08h
10h
=
=
=
=
=
=
Reserved
X1
Reserved
Reserved
Reserved
X16
All other encodings are reserved.
3:0
RO
1h
Negotiated Speed (NS): Indicates negotiated link speed.
1h = 2.5 Gb/s
All other encodings are reserved.
196
Datasheet
PCI Express* Registers (D1:F0)
6.1.41
SLOTCAP—Slot Capabilities
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/1/0/PCI
B4–B7h
00040000h
RWO, RO
32 bits
PCI Express Slot related registers allow for the support of Hot Plug.
Bit
Access &
Default
31:19
RWO
0000h
18
RWO
1b
17
RO
0b
16:15
RWO
00b
Description
Physical Slot Number (PSN): Indicates the physical slot number
attached to this Port.
No Command Completed Support (NCCS):
1 = This slot does not generate software notification when an issued
command is completed by the Hot-Plug Controller. This bit is only
permitted to be set to 1b if the hotplug capable port is able to
accept writes to all fields of the Slot Control register without
delay between successive writes.
Reserved for Electromechanical Interlock Present (EIP):
Slot Power Limit Scale (SPLS): This field specifies the scale used
for the Slot Power Limit Value.
00 = 1.0x
01 = 0.1x
10 = 0.01x
11 = 0.001x
If this field is written, the link sends a Set_Slot_Power_Limit
message.
14:7
RWO
00h
Slot Power Limit Value (SPLV): In combination with the Slot
Power Limit Scale value, specifies the upper limit on power supplied
by slot. Power limit (in Watts) is calculated by multiplying the value in
this field by the value in the Slot Power Limit Scale field.
If this field is written, the link sends a Set_Slot_Power_Limit
message.
6
RO
0b
Hot-plug Capable (HPC):
0 = Not Hot-plug capable
1 = Slot is capable of supporting hot-lug operations.
5
RO
0b
Hot-plug Surprise (HPS):
0 = No Hot-plug surprise
1 = An adapter present in this slot might be removed from the
system without any prior notification. This is a form factor
specific capability. This bit is an indication to the operating
system to allow for such removal without impacting continued
software operation.
Datasheet
197
PCI Express* Registers (D1:F0)
Bit
Access &
Default
4
RO
0b
Description
Power Indicator Present (PIP):
0 = No power indicator
1 = A Power Indicator is electrically controlled by the chassis for this
slot.
3
RO
0b
Attention Indicator Present (AIP):
0 = No Attention indicator
1 = An Attention Indicator is electrically controlled by the chassis.
2
RO
0b
MRL Sensor Present (MSP):
0 = No MRL sensor
1 = MRL Sensor is implemented on the chassis for this slot.
1
RO
0b
Power Controller Present (PCP):
0 = No power controller
1 = A software programmable Power Controller is implemented for
this slot/adapter (depending on form factor).
0
RO
0b
Attention Button Present (ABP):
0 = No attention button
1 = An Attention Button for this slot is electrically controlled by the
chassis.
6.1.42
SLOTCTL—Slot Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/1/0/PCI
B8–B9h
01C0h
RO, RW
16 bits
PCI Express Slot related registers allow for the support of Hot Plug.
198
Bit
Access &
Default
Description
15:13
RO
000b
12
RO
0b
Data Link Layer State Changed Enable (DLLSCE): If the Data
Link Layer Link Active capability is implemented, when set to 1b, this
field enables software notification when Data Link Layer Link Active
field is changed.
11
RO
0b
Electromechanical Interlock Control (EIC): If an
Electromechanical Interlock is implemented, a write of 1b to this field
causes the state of the interlock to toggle. A write of 0b to this field
has no effect. A read to this register always returns a 0.
Reserved
Datasheet
PCI Express* Registers (D1:F0)
Bit
Access &
Default
10
RO
0b
Description
Power Controller Control (PCC): If a Power Controller is
implemented, this field when written sets the power state of the slot
per the defined encodings. Reads of this field must reflect the value
from the latest write, even if the corresponding hotplug command is
not complete, unless software issues a write without waiting for the
previous command to complete in which case the read value is
undefined.
Depending on the form factor, the power is turned on/off either to the
slot or within the adapter. Note that in some cases the power
controller may autonomously remove slot power or not respond to a
power-up request based on a detected fault condition, independent of
the Power Controller Control setting.
The defined encodings are:
0 = Power On
1 = Power Off
If the Power Controller Implemented field in the Slot Capabilities
register is set to 0b, then writes to this field have no effect and the
read value of this field is undefined.
9:8
RO
01b
Power Indicator Control (PIC): If a Power Indicator is
implemented, writes to this field set the Power Indicator to the
written state. Reads of this field must reflect the value from the latest
write, even if the corresponding hot-plug command is not complete,
unless software issues a write without waiting for the previous
command to complete in which case the read value is undefined.
00 = Reserved
01 = On
10 = Blink
11 = Off
7:6
RO
11b
Attention Indicator Control (AIC): If an Attention Indicator is
implemented, writes to this field set the Attention Indicator to the
written state.
Reads of this field must reflect the value from the latest write, even if
the corresponding hot-plug command is not complete, unless
software issues a write without waiting for the previous command to
complete in which case the read value is undefined. If the indicator is
electrically controlled by chassis, the indicator is controlled directly by
the downstream port through implementation specific mechanisms.
00 = Reserved
01 = On
10 = Blink
11 = Off
Datasheet
199
PCI Express* Registers (D1:F0)
Bit
Access &
Default
5
RO
0b
Description
Hot-plug Interrupt Enable (HPIE):
0 = Disable
1 = Enables generation of an interrupt on enabled hot-plug events
Default value of this field is 0b. If the Hot Plug Capable field in
the Slot Capabilities register is set to 0b, this bit is permitted to
be read-only with a value of 0b.
4
RO
0b
Command Completed Interrupt Enable (CCI): If Command
Completed notification is supported (as indicated by No Command
Completed Support field of Slot Capabilities Register), when set to 1b,
this bit enables software notification when a hot-plug command is
completed by the Hot-Plug Controller.
If Command Completed notification is not supported, this bit must be
hardwired to 0b.
3
RW
0b
Presence Detect Changed Enable (PDCE):
0 = Disable
1 = Enables software notification on a presence detect changed
event.
2
RO
0b
MRL Sensor Changed Enable (MSCE): If the MRL Sensor Present
field in the Slot Capabilities register is set to 0b, this bit is permitted
to be read-only with a value of 0b.
0 = Disable (default)
1 = Enables software notification on a MRL sensor changed event.
1
RO
0b
Power Fault Detected Enable (PFDE): If Power Fault detection is
not supported, this bit is permitted to be read-only with a value of 0b.
0 = Disable (default)
1 = Enables software notification on a power fault event.
0
RO
0b
Attention Button Pressed Enable (ABPE):
0 = Disable (default)
1 = Enables software notification on an attention button pressed
event.
200
Datasheet
PCI Express* Registers (D1:F0)
6.1.43
SLOTSTS—Slot Status
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/1/0/PCI
BA–BBh
0000h
RO, RWC
16 bits
PCI Express Slot related registers allow for the support of Hot Plug.
Bit
Access &
Default
15:7
RO
0000000b
6
RO
0b
Description
Reserved and Zero: For future R/WC/S implementations; software
must use 0 for writes to bits.
Presence Detect State (PDS): This bit indicates the presence of an
adapter in the slot, reflected by the logical "OR" of the Physical Layer
in-band presence detect mechanism and, if present, any out-of-band
presence detect mechanism defined for the slot's corresponding form
factor. Note that the in-band presence detect mechanism requires
that power be applied to an adapter for its presence to be detected.
Consequently, form factors that require a power controller for hotplug must implement a physical pin presence detect mechanism.
0 = Slot Empty
1 = Card Present in slot
This register must be implemented on all Downstream Ports that
implement slots. For Downstream Ports not connected to slots (where
the Slot Implemented bit of the PCI Express Capabilities Register is
0b), this bit must return 1b.
5
RO
0b
Reserved
4
RO
0b
Command Completed (CC): If Command Completed notification is
supported (as indicated by No Command Completed Support field of
Slot Capabilities Register), this bit is set when a hot-plug command
has completed and the Hot-Plug Controller is ready to accept a
subsequent command. The Command Completed status bit is set as
an indication to host software that the Hot-Plug Controller has
processed the previous command and is ready to receive the next
command; it provides no assurance that the action corresponding to
the command is complete.
If Command Completed notification is not supported, this bit must be
hardwired to 0b.
Datasheet
3
RWC
0b
2
RO
0b
Detect Changed (PDC): This bit is set when the value reported in
Presence Detect State is changed.
MRL Sensor Changed (MSC): If an MRL sensor is implemented, this
bit is set when a MRL Sensor state change is detected. If an MRL
sensor is not implemented, this bit must not be set.
201
PCI Express* Registers (D1:F0)
6.1.44
Bit
Access &
Default
Description
1
RO
0b
Power Fault Detected (PFD): If a Power Controller that supports
power fault detection is implemented, this bit is set when the Power
Controller detects a power fault at this slot. Note that, depending on
hardware capability, it is possible that a power fault can be detected
at any time, independent of the Power Controller Control setting or
the occupancy of the slot. If power fault detection is not supported,
this bit must not be set.
0
RO
0b
Attention Button Pressed (ABP): If an Attention Button is
implemented, this bit is set when the attention button is pressed. If an
Attention Button is not supported, this bit must not be set.
RCTL—Root Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/1/0/PCI
BC–BDh
0000h
RO, RW
16 bits
This register allows control of PCI Express Root Complex specific parameters. The
system error control bits in this register determine if corresponding SERRs are
generated when our device detects an error (reported in this device's Device Status
register) or when an error message is received across the link. Reporting of SERR as
controlled by these bits takes precedence over the SERR Enable in the PCI Command
Register.
Bit
Access &
Default
15:4
RO
000h
3
RW
0b
Description
Reserved
PME Interrupt Enable (PMEIE):
0 = No interrupts are generated as a result of receiving PME messages.
1 = Enables interrupt generation upon receipt of a PME message as
reflected in the PME Status bit of the Root Status Register. A PME
interrupt is also generated if the PME Status bit of the Root Status
Register is set when this bit is set from a cleared state.
2
RW
0b
System Error on Fatal Error Enable (SEFEE): This bit controls the
Root Complex's response to fatal errors.
0 = No SERR generated on receipt of fatal error.
1 = SERR should be generated if a fatal error is reported by any of the
devices in the hierarchy associated with this Root Port, or by the
Root Port itself.
202
Datasheet
PCI Express* Registers (D1:F0)
Bit
Access &
Default
1
RW
0b
Description
System Error on Non-Fatal Uncorrectable Error Enable
(SENFUEE): This bit controls the Root Complex's response to nonfatal errors.
0 = No SERR generated on receipt of non-fatal error.
1 = SERR should be generated if a non-fatal error is reported by any of
the devices in the hierarchy associated with this Root Port, or by
the Root Port itself.
0
RW
0b
System Error on Correctable Error Enable (SECEE): This bit
controls the Root Complex's response to correctable errors.
0 = No SERR generated on receipt of correctable error.
1 = SERR should be generated if a correctable error is reported by any
of the devices in the hierarchy associated with this Root Port, or
by the Root Port itself.
6.1.45
RSTS—Root Status
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/1/0/PCI
C0–C3h
00000000h
RO, RWC
32 bits
This register provides information about PCI Express Root Complex specific
parameters.
Bit
Access &
Default
31:18
RO
0000h
17
RO
0b
16
15:0
Datasheet
RWC
0b
RO
0000h
Description
Reserved
PME Pending (PMEP):
1 = Another PME is pending when the PME Status bit is set. When the
PME Status bit is cleared by software; the PME is delivered by
hardware by setting the PME Status bit again and updating the
Requestor ID appropriately. The PME pending bit is cleared by
hardware if no more PMEs are pending.
PME Status (PMES):
1 = PME was asserted by the requestor ID indicated in the PME
Requestor ID field. Subsequent PMEs are kept pending until the
status register is cleared by writing a 1 to this field.
PME Requestor ID (PMERID): This field indicates the PCI requestor
ID of the last PME requestor.
203
PCI Express* Registers (D1:F0)
6.1.46
PEGLC—PCI Express*-G Legacy Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/1/0/PCI
EC–EFh
00000000h
RW, RO
32 bits
This register controls functionality that is needed by Legacy (non-PCI Express aware)
operating systems during run time.
Bit
Access &
Default
31:3
RO
00000000
h
2
RW
0b
Description
Reserved
PME GPE Enable (PMEGPE):
0 = Do not generate GPE PME message when PME is received.
1 = Generate a GPE PME message when PME is received
(Assert_PMEGPE and Deassert_PMEGPE messages on DMI). This
enables the GMCH to support PMEs on the PEG port under legacy
operating systems.
1
RW
0b
Hot-Plug GPE Enable (HPGPE):
0 = Do not generate GPE Hot-Plug message when Hot-Plug event is
received.
1 = Generate a GPE Hot-Plug message when Hot-Plug Event is
received (Assert_HPGPE and Deassert_HPGPE messages on DMI).
This enables the GMCH to support Hot-Plug on the PEG port under
legacy operating systems.
0
RW
0b
General Message GPE Enable (GENGPE):
0 = Do not forward received GPE assert/de-assert messages.
1 = Forward received GPE assert/de-assert messages. These general
GPE message can be received via the PEG port from an external
Intel device (i.e., PxH) and will be subsequently forwarded to the
ICH (via Assert_GPE and Deassert_GPE messages on DMI). For
example, PxH might send this message if a PCI Express device is
hot plugged into a PxH downstream port.
204
Datasheet
PCI Express* Registers (D1:F0)
6.1.47
VCECH—Virtual Channel Enhanced Capability Header
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/1/0/MMR
100–103h
14010002h
RO
32 bits
This register indicates PCI Express device Virtual Channel capabilities. Extended
capability structures for PCI Express devices are located in PCI Express extended
configuration space and have different field definitions than standard PCI capability
structures.
6.1.48
Bit
Access &
Default
Description
31:20
RO
140h
Pointer to Next Capability (PNC): The Link Declaration Capability is
the next in the PCI Express extended capabilities list.
19:16
RO
1h
PCI Express Virtual Channel Capability Version (PCI
EXPRESS*VCCV): Hardwired to 1 to indicate compliances with the 1.1
version of the PCI Express specification.
15:0
RO
0002h
Extended Capability ID (ECID): Value of 0002 h identifies this
linked list item (capability structure) as being for PCI Express Virtual
Channel registers.
PVCCAP1—Port VC Capability Register 1
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/1/0/MMR
104–107h
00000000h
RO
32 bits
This register describes the configuration of PCI Express Virtual Channels associated
with this port.
Bit
Access &
Default
31:7
RO
0000000h
6:4
RO
000b
3
RO
0b
2:0
RO
000b
Description
Reserved
Low Priority Extended VC Count (LPEVCC): This field indicates the
number of (extended) Virtual Channels in addition to the default VC
belonging to the low-priority VC (LPVC) group that has the lowest
priority with respect to other VC resources in a strict-priority VC
Arbitration.
The value of 0 in this field implies strict VC arbitration.
Datasheet
Reserved
Extended VC Count (EVCC): This field indicates the number of
(extended) Virtual Channels in addition to the default VC supported by
the device.
205
PCI Express* Registers (D1:F0)
6.1.49
PVCCAP2—Port VC Capability Register 2
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/1/0/MMR
108–10Bh
00000000h
RO
32 bits
This register describes the configuration of PCI Express Virtual Channels associated
with this port.
6.1.50
Bit
Access &
Default
Description
31:24
RO
00h
VC Arbitration Table Offset (VCATO): This field indicates the
location of the VC Arbitration Table. This field contains the zero-based
offset of the table in DQWORDS (16 bytes) from the base address of
the Virtual Channel Capability Structure. A value of 0 indicates that
the table is not present (due to fixed VC priority).
23:0
RO
0s
Reserved
PVCCTL—Port VC Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
206
0/1/0/MMR
10C–10Dh
0000h
RO, RW
16 bits
Bit
Access &
Default
Description
15:4
RO
000h
Reserved
3:1
RW
000b
VC Arbitration Select (VCAS): This field will be programmed by
software to the only possible value as indicated in the VC Arbitration
Capability field. Since there is no other VC supported than the
default, this field is reserved.
0
RO
0b
Reserved
Datasheet
PCI Express* Registers (D1:F0)
6.1.51
VC0RCAP—VC0 Resource Capability
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Bit
Access &
Default
31:16
RO
0000h
15
RO
0b
0/1/0/MMR
110–113h
00000000h
RO
32 bits
Description
Reserved
Reject Snoop Transactions (RSNPT):
0 = Transactions with or without the No Snoop bit set within the TLP
header are allowed on this VC.
1 = Any transaction without the No Snoop bit set within the TLP
header will be rejected as an Unsupported Request.
14:0
Datasheet
RO
0000h
Reserved
207
PCI Express* Registers (D1:F0)
6.1.52
VC0RCTL—VC0 Resource Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/1/0/MMR
114–117h
800000FFh
RO, RW
32 bits
This register controls the resources associated with PCI Express Virtual Channel 0.
208
Bit
Access &
Default
Description
31
RO
1b
VC0 Enable (VC0E): For VC0, this is hardwired to 1 and read only
as VC0 can never be disabled.
30:27
RO
0h
Reserved
26:24
RO
000b
23:8
RO
0000h
7:1
RW
7Fh
TC/VC0 Map (TCVC0M): This field indicates the TCs (Traffic
Classes) that are mapped to the VC resource. Bit locations within this
field correspond to TC values. For example, when bit 7 is set in this
field, TC7 is mapped to this VC resource. When more than one bit in
this field is set, it indicates that multiple TCs are mapped to the VC
resource. To remove one or more TCs from the TC/VC Map of an
enabled VC, software must ensure that no new or outstanding
transactions with the TC labels are targeted at the given Link.
0
RO
1b
TC0/VC0 Map (TC0VC0M): Traffic Class 0 is always routed to VC0.
VC0 ID (VC0ID): Assigns a VC ID to the VC resource. For VC0, this
is hardwired to 0 and read only.
Reserved
Datasheet
PCI Express* Registers (D1:F0)
6.1.53
VC0RSTS—VC0 Resource Status
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/1/0/MMR
11A–11Bh
0002h
RO
16 bits
This register reports the Virtual Channel specific status.
Bit
Access &
Default
15:2
RO
0000h
1
RO
1b
Description
Reserved
VC0 Negotiation Pending (VC0NP):
0 = The VC negotiation is complete.
1 = The VC resource is still in the process of negotiation (initialization
or disabling).
This bit indicates the status of the process of Flow Control initialization.
It is set by default on Reset, as well as whenever the corresponding
Virtual Channel is Disabled or the Link is in the DL_Down state. It is
cleared when the link successfully exits the FC_INIT2 state.
Before using a Virtual Channel, software must check whether the VC
Negotiation Pending fields for that Virtual Channel are cleared in both
Components on a Link.
0
Datasheet
RO
0b
Reserved
209
PCI Express* Registers (D1:F0)
6.1.54
RCLDECH—Root Complex Link Declaration Enhanced
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/1/0/MMR
140–143h
00010005h
RO
32 bits
This capability declares links from this element (PEG) to other elements of the root
complex component to which it belongs. See PCI Express specification for
link/topology declaration requirements.
6.1.55
Bit
Access &
Default
31:20
RO
000h
19:16
RO
1h
15:0
RO
0005h
Description
Pointer to Next Capability (PNC): This is the last capability in the
PCI Express extended capabilities list
Link Declaration Capability Version (LDCV): Hardwired to 1 to
indicate compliances with the 1.1 version of the PCI Express
specification.
Extended Capability ID (ECID): Value of 0005h identifies this linked
list item (capability structure) as being for PCI Express Link
Declaration Capability.
ESD—Element Self Description
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/1/0/MMR
144–147h
02000100h
RO, RWO
32 bits
This register provides information about the root complex element containing this Link
Declaration Capability.
210
Bit
Access &
Default
Description
31:24
RO
02h
Port Number (PN): This field specifies the port number associated
with this element with respect to the component that contains this
element. This port number value is utilized by the Express port of the
component to provide arbitration to this Root Complex Element.
23:16
RWO
00h
Component ID (CID): This field identifies the physical component
that contains this Root Complex Element.
15:8
RO
01h
Number of Link Entries (NLE): This field indicates the number of
link entries following the Element Self Description. This field reports 1
(to Express port only as we don't report any peer-to-peer capabilities
in our topology).
7:4
RO
0h
Reserved
3:0
RO
0h
Element Type (ET): This field indicates the type of the Root Complex
Element. Value of 0h represents a root port.
Datasheet
PCI Express* Registers (D1:F0)
6.1.56
LE1D—Link Entry 1 Description
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/1/0/MMR
150–153h
00000000h
RO, RWO
32 bits
This register provides the first part of a Link Entry which declares an internal link to
another Root Complex Element.
Bit
Access &
Default
Description
31:24
RO
00h
Target Port Number (TPN): This field specifies the port number
associated with the element targeted by this link entry (Express Port).
The target port number is with respect to the component that contains
this element as specified by the target component ID.
23:16
RWO
00h
Target Component ID (TCID): This field identifies the physical or
logical component that is targeted by this link entry.
15:2
RO
0000h
1
RO
0b
0
RWO
0b
Reserved
Link Type (LTYP): This field indicates that the link points to
memory-mapped space (for RCRB). The link address specifies the 64bit base address of the target RCRB.
Link Valid (LV):
0 = Link Entry is not valid and will be ignored.
1 = Link Entry specifies a valid link.
6.1.57
LE1A—Link Entry 1 Address
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/1/0/MMR
158–15Fh
0000000000000000h
RO, RWO
64 bits
This register provides the second part of a Link Entry which declares an internal link to
another Root Complex Element.
Datasheet
Bit
Access &
Default
63:32
RO
00000000
h
31:12
RWO
00000h
11:0
RO
000h
Description
Reserved
Link Address (LA): This field contains the memory-mapped base
address of the RCRB that is the target element (Express Port) for this
link entry.
Reserved
211
PCI Express* Registers (D1:F0)
6.1.58
PEGSSTS—PCI Express*-G Sequence Status
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/1/0/MMR
218–21Fh
0000000000000FFFh
RO
64 bits
This register provides PCI Express status reporting that is required by the PCI Express
specification.
Bit
Access &
Default
63:60
RO
0h
59:48
RO
000h
47:44
RO
0h
43:32
RO
000h
31:28
RO
0h
27:16
RO
000h
15:12
RO
0h
11:0
RO
FFFh
Description
Reserved
Next Transmit Sequence Number (NTSN): This field indicates the
value of the NXT_TRANS_SEQ counter. This counter represents the
transmit Sequence number to be applied to the next TLP to be
transmitted onto the Link for the first time.
Reserved
Next Packet Sequence Number (NPSN): This field indicates the
packet sequence number to be applied to the next TLP to be
transmitted or re-transmitted onto the Link.
Reserved
Next Receive Sequence Number (NRSN): This field is the
sequence number associated with the TLP that is expected to be
received next.
Reserved
Last Acknowledged Sequence Number (LASN): This field is the
sequence number associated with the last acknowledged TLP.
§
212
Datasheet
PCI Express* Registers (D1:F0)
Datasheet
213
Direct Memory Interface (DMI) Registers
7
Direct Memory Interface (DMI)
Registers
This Root Complex Register Block (RCRB) controls the GMCH-ICH9 serial interconnect.
The base address of this space is programmed in DMIBAR in D0:F0 configuration
space. Table 7-1 provides an address map of the DMI registers listed by address offset
in ascending order. Section 7.1 provides register bit descriptions.
Table 7-1. DMI Register Address Map
214
Address
Offset
Register
Symbol
00–03h
DMIVCECH
04–07h
Register Name
Default
Value
Access
DMI Virtual Channel Enhanced
Capability
04010002h
RO
DMIPVCCAP1
DMI Port VC Capability Register 1
00000001h
RWO,
RO
08–0Bh
DMIPVCCAP2
DMI Port VC Capability Register 2
00000000h
RO
0C–0Dh
DMIPVCCTL
0000h
RO, RW
10–13h
DMIVC0RCAP
DMI VC0 Resource Capability
00000001h
RO
14–17h
DMIVC0RCTL0
DMI VC0 Resource Control
800000FFh
RO, RW
1A–1Bh
DMIVC0RSTS
DMI VC0 Resource Status
0002h
RO
1C–1Fh
DMIVC1RCAP
DMI VC1 Resource Capability
00008001h
RO
20–23h
DMIVC1RCTL1
DMI VC1 Resource Control
01000000h
RW, RO
26–27h
DMIVC1RSTS
DMI VC1 Resource Status
0002h
RO
84–87h
DMILCAP
DMI Link Capabilities
00012C41h
RO,
RWO
88–89h
DMILCTL
DMI Link Control
0000h
RW, RO
8A–8Bh
DMILSTS
DMI Link Status
0001h
RO
DMI Port VC Control
Datasheet
Direct Memory Interface (DMI) Registers
7.1
Direct Memory Interface (DMI) Configuration
Register Details
7.1.1
DMIVCECH—DMI Virtual Channel Enhanced Capability
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/DMIBAR
00–03h
04010002h
RO
32 bits
This register indicates DMI Virtual Channel capabilities.
Datasheet
Bit
Access &
Default
Description
31:20
RO
040h
Pointer to Next Capability (PNC): This field contains the offset to
the next PCI Express capability structure in the linked list of
capabilities (Link Declaration Capability).
19:16
RO
1h
PCI Express* Virtual Channel Capability Version (PCI
EXPRESS*VCCV): Hardwired to 1 to indicate compliances with the
1.1 version of the PCI Express specification.
15:0
RO
0002h
Extended Capability ID (ECID): Value of 0002h identifies this linked
list item (capability structure) as being for PCI Express Virtual Channel
registers.
215
Direct Memory Interface (DMI) Registers
7.1.2
DMIPVCCAP1—DMI Port VC Capability Register 1
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/DMIBAR
04–07h
00000001h
RWO, RO
32 bits
This register describes the configuration of PCI Express Virtual Channels associated
with this port.
Bit
Access &
Default
31:7
RO
0000000h
6:4
RO
000b
Description
Reserved
Low Priority Extended VC Count (LPEVCC): This field indicates the
number of (extended) Virtual Channels in addition to the default VC
belonging to the low-priority VC (LPVC) group that has the lowest
priority with respect to other VC resources in a strict-priority VC
Arbitration.
The value of 0 in this field implies strict VC arbitration.
3
RO
0b
2:0
RWO
001b
Reserved
Extended VC Count (EVCC): This field indicates the number of
(extended) Virtual Channels in addition to the default VC supported by
the device.
The Private Virtual Channel is not included in this count.
7.1.3
DMIPVCCAP2—DMI Port VC Capability Register 2
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/DMIBAR
08–0Bh
00000000h
RO
32 bits
This register describes the configuration of PCI Express Virtual Channels associated
with this port.
216
Bit
Access &
Default
31:0
RO
00000000h
Description
Reserved
Datasheet
Direct Memory Interface (DMI) Registers
7.1.4
DMIPVCCTL—DMI Port VC Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/DMIBAR
0C–0Dh
0000h
RO, RW
16 bits
Bit
Access &
Default
Description
15:4
RO
000h
Reserved
3:1
RW
000b
VC Arbitration Select (VCAS): This field will be programmed by
software to the only possible value as indicated in the VC Arbitration
Capability field.
See the PCI express specification for more details.
0
7.1.5
RO
0b
Reserved
DMIVC0RCAP—DMI VC0 Resource Capability
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Bit
Access &
Default
31:16
RO
00000h
15
RO
0b
0/0/0/DMIBAR
10–13h
00000001h
RO
32 bits
Description
Reserved
Reject Snoop Transactions (REJSNPT):
0 = Transactions with or without the No Snoop bit set within the TLP
header are allowed on this VC.
1 = Any transaction without the No Snoop bit set within the TLP
header will be rejected as an Unsupported Request.
Datasheet
14:8
RO
00h
Reserved
7:0
RO
01h
Port Arbitration Capability (PAC): Having only bit 0 set indicates
that the only supported arbitration scheme for this VC is nonconfigurable hardware-fixed.
217
Direct Memory Interface (DMI) Registers
7.1.6
DMIVC0RCTL0—DMI VC0 Resource Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/DMIBAR
14–17h
800000FFh
RO, RW
32 bits
This register controls the resources associated with PCI Express Virtual Channel 0.
Bit
Access &
Default
Description
31
RO
1b
Virtual Channel 0 Enable (VC0E): For VC0, this is hardwired to 1
and read only as VC0 can never be disabled.
30:27
RO
0h
Reserved
26:24
RO
000b
23:20
RO
0h
19:17
RW
000b
Virtual Channel 0 ID (VC0ID): Assigns a VC ID to the VC resource.
For VC0, this is hardwired to 0 and read only.
Reserved
Port Arbitration Select (PAS): This field configures the VC resource
to provide a particular Port Arbitration service. Valid value for this field
is a number corresponding to one of the asserted bits in the Port
Arbitration Capability field of the VC resource. Because only bit 0 of
that field is asserted.
This field will always be programmed to '1'.
16:8
RO
000h
7:1
RW
7Fh
Reserved
Traffic Class / Virtual Channel 0 Map (TCVC0M): This field
indicates the TCs (Traffic Classes) that are mapped to the VC resource.
Bit locations within this field correspond to TC values.
For example, when bit 7 is set in this field, TC7 is mapped to this VC
resource. When more than one bit in this field is set, it indicates that
multiple TCs are mapped to the VC resource. In order to remove one
or more TCs from the TC/VC Map of an enabled VC, software must
ensure that no new or outstanding transactions with the TC labels are
targeted at the given Link.
0
218
RO
1b
Traffic Class 0 / Virtual Channel 0 Map (TC0VC0M): Traffic Class
0 is always routed to VC0.
Datasheet
Direct Memory Interface (DMI) Registers
7.1.7
DMIVC0RSTS—DMI VC0 Resource Status
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/DMIBAR
1A–1Bh
0002h
RO
16 bits
This register reports the Virtual Channel specific status.
Bit
Access &
Default
15:2
RO
0000h
1
RO
1b
Description
Reserved.
Virtual Channel 0 Negotiation Pending (VC0NP): This bit
indicates the status of the process of Flow Control initialization. It is
set by default on Reset, as well as whenever the corresponding Virtual
Channel is Disabled or the Link is in the DL_Down state.
It is cleared when the link successfully exits the FC_INIT2 state.
0 = The VC negotiation is complete.
1 = The VC resource is still in the process of negotiation (initialization
or disabling).
BIOS Requirement: Before using a Virtual Channel, software must
check whether the VC Negotiation Pending fields for that Virtual
Channel are cleared in both Components on a Link.
0
7.1.8
RO
0b
Reserved
DMIVC1RCAP—DMI VC1 Resource Capability
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Bit
Access &
Default
31:16
RO
00000h
15
RO
1b
0/0/0/DMIBAR
1C–1Fh
00008001h
RO
32 bits
Description
Reserved
Reject Snoop Transactions (REJSNPT):
0 = Transactions with or without the No Snoop bit set within the TLP
header are allowed on this VC.
1 = Any transaction without the No Snoop bit set within the TLP
header will be rejected as an Unsupported Request.
Datasheet
14:8
RO
00h
Reserved
7:0
RO
01h
Port Arbitration Capability (PAC): Having only bit 0 set indicates
that the only supported arbitration scheme for this VC is nonconfigurable hardware-fixed.
219
Direct Memory Interface (DMI) Registers
7.1.9
DMIVC1RCTL1—DMI VC1 Resource Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/DMIBAR
20–23h
01000000h
RW, RO
32 bits
This register controls the resources associated with PCI Express Virtual Channel 1.
Bit
Access &
Default
31
RW
0b
Description
Virtual Channel 1 Enable (VC1E):
0 = Virtual Channel is disabled.
1 = Virtual Channel is enabled.
30:27
RO
0h
Reserved
26:24
RW
001b
23:20
RO
0h
19:17
RW
000b
Port Arbitration Select (PAS): This field configures the VC resource
to provide a particular Port Arbitration service. Valid value for this field
is a number corresponding to one of the asserted bits in the Port
Arbitration Capability field of the VC resource.
16:8
RO
000h
Reserved
7:1
RW
00h
Virtual Channel 1 ID (VC1ID): This field assigns a VC ID to the VC
resource. Assigned value must be non-zero. This field can not be
modified when the VC is already enabled.
Reserved
Traffic Class / Virtual Channel 1 Map (TCVC1M): This field
indicates the TCs (Traffic Classes) that are mapped to the VC resource.
Bit locations within this field correspond to TC values.
For example, when bit 7 is set in this field, TC7 is mapped to this VC
resource. When more than one bit in this field is set, it indicates that
multiple TCs are mapped to the VC resource. In order to remove one
or more TCs from the TC/VC Map of an enabled VC, software must
ensure that no new or outstanding transactions with the TC labels are
targeted at the given Link.
0
220
RO
0b
Traffic Class 0 / Virtual Channel 1 Map (TC0VC1M): Traffic Class
0 is always routed to VC0.
Datasheet
Direct Memory Interface (DMI) Registers
7.1.10
DMIVC1RSTS—DMI VC1 Resource Status
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/DMIBAR
26–27h
0002h
RO
16 bits
This register reports the Virtual Channel specific status.
Bit
Access &
Default
15:2
RO
0000h
1
RO
1b
Description
Reserved
Virtual Channel 1 Negotiation Pending (VC1NP):
0 = The VC negotiation is complete.
1 = The VC resource is still in the process of negotiation (initialization
or disabling).
0
7.1.11
RO
0b
Reserved
DMILCAP—DMI Link Capabilities
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/DMIBAR
84–87h
00012C41h
RO, RWO
32 bits
This register indicates DMI specific capabilities.
Bit
Access &
Default
31:18
RO
0000h
17:15
RWO
010b
14:12
RWO
010b
Description
Reserved
L1 Exit Latency (L1SELAT): This field indicates the length of time
this Port requires to complete the transition from L1 to L0.
010b = 2 us to less than 4 us.
L0s Exit Latency (L0SELAT): This field indicates the length of time
this Port requires to complete the transition from L0s to L0.
010 = 128 ns to less than 256 ns
Datasheet
11:10
RO
11b
Active State Link PM Support (ASLPMS): L0s & L1 entry
supported.
9:4
RO
04h
Max Link Width (MLW): This field indicates the maximum number
of lanes supported for this link.
3:0
RO
1h
Max Link Speed (MLS): Hardwired to indicate 2.5 Gb/s.
221
Direct Memory Interface (DMI) Registers
7.1.12
DMILCTL—DMI Link Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/DMIBAR
88–89h
0000h
RW, RO
16 bits
This register allows control of DMI.
Bit
Access &
Default
15:8
RO
00h
7
RW
0b
Description
Reserved
Extended Synch (EXTSYNC):
0 = Standard Fast Training Sequence (FTS).
1 = Forces the transmission of additional ordered sets when exiting
the L0s state and when in the Recovery state.
6:3
RO
0h
Reserved
2
RW
0b
Far-End Digital Loopback (FEDLB):
1:0
RW
00b
Active State Power Management Support (ASPMS): This field
controls the level of active state power management supported on the
given link.
00 = Disabled
01 = L0s Entry Supported
10 = Reserved
11 = L0s and L1 Entry Supported
222
Datasheet
Direct Memory Interface (DMI) Registers
7.1.13
DMILSTS—DMI Link Status
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/DMIBAR
8A–8Bh
0001h
RO
16 bits
This register indicates DMI status.
Bit
Access &
Default
Description
15:10
RO
00h
Reserved and Zero for future R/WC/S implementations. Software must
use 0 for writes to these bits.
9:4
RO
00h
Negotiated Width (NWID): This field indicates negotiated link
width. This field is valid only when the link is in the L0, L0s, or L1
states (after link width negotiation is successfully completed).
04h = X4
All other encodings are reserved.
3:0
RO
1h
Negotiated Speed (NSPD): This field indicates negotiated link
speed.
1h = 2.5 Gb/s
All other encodings are reserved.
§
Datasheet
223
Integrated Graphics Device Registers (D2:F0,F1)
8
Integrated Graphics Device
Registers (D2:F0,F1)
The Integrated Graphics Device (IGD) registers are located in Device 2 (D0), Function
0 (F0) and Function 1 (F1). This chapter provides the descriptions for these registers.
Section 8.1 provides the register descriptions for Device 2, Function 0. Section 8.2
provides the register descriptions for Device 2, Function 1.
8.1
Integrated Graphics Register Details (D2:F0)
Device 2, Function 0 contains registers for the internal graphics functions. Table 8-1
lists the PCI configuration registers in order of ascending offset address.
Function 0 can be VGA compatible or not, this is selected through bit 1 of GGC register
(Device 0, offset 52h).
Note: The following sections describe Device 2 PCI configuration registers only.
Table 8-1. Integrated Graphics Device Register Address Map (D2:F0)
224
Address
Offset
Register
Symbol
00–01h
VID2
02–03h
DID
04–05h
Register Name
Default
Value
Access
Vendor Identification
8086h
RO
Device Identification
29C2h
RO
PCICMD2
PCI Command
0000h
RO, RW
06–07h
PCISTS2
PCI Status
0090h
RO
08h
RID2
00h
RO
09–0Bh
CC
Class Code
030000h
RO
0Ch
CLS
Cache Line Size
00h
RO
0Dh
MLT2
Master Latency Timer
00h
RO
0Eh
HDR2
Header Type
80h
RO
18–1Fh
GMADR
Graphics Memory Range Address
000000000
000000Ah
RW/L,
RO, RW
20–23h
IOBAR
IO Base Address
00000001h
RO, RW
2C–2Dh
SVID2
Subsystem Vendor Identification
0000h
RWO
2E–2Fh
SID2
Subsystem Identification
0000h
RWO
30–33h
ROMADR
00000000h
RO
Revision Identification
Video BIOS ROM Base Address
Datasheet
Integrated Graphics Device Registers (D2:F0,F1)
8.1.1
Address
Offset
Register
Symbol
34h
CAPPOINT
3Eh
Register Name
Default
Value
Access
Capabilities Pointer
90h
RO
MINGNT
Minimum Grant
00h
RO
3Fh
MAXLAT
Maximum Latency
00h
RO
44h
MCAPPTR
Mirror of Dev 0 Capabilities Pointer
E0h
RO
48–51h
CAPID0
Mirror of Dev0 Capability Identifier
000000000
000010900
09h
RO
52–53h
MGGC
GMCH Graphics Control Register
0030h
RO
54–57h
DEVEN
Device Enable
000003DBh
RO
58–5Bh
SSRW
Software Scratch Read Write
00000000h
RW
5C–5Fh
BSM
Base of Stolen Memory
07800000h
RO
60–61h
HSRW
Hardware Scratch Read Write
0000h
RW
90–11h
MSI_CAPID
Message Signaled Interrupts
Capability ID
D005h
R)
C0h
GDRST
00h
RO, RW/L
D0–D1h
PMCAPID
Power Management Capabilities ID
0001h
RWO, RO
D2–D3h
PMCAP
Power Management Capabilities
0022h
RO
D4–D5h
PMCS
Power Management Control/Status
0000h
RO, RW
E0–E1h
SWSMI
Software SMI
0000h
RW
E4–E7h
ASLE
System Display Event Register
00000000h
RW
FC–FFh
ASLS
ASL Storage
00000000h
RW
Graphics Debug Reset
VID2—Vendor Identification
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/2/0/PCI
00–01h
8086h
RO
16 bits
This register combined with the Device Identification register uniquely identifies any
PCI device.
Datasheet
Bit
Access &
Default
Description
15:0
RO
8086h
Vendor Identification Number (VID): PCI standard identification
for Intel.
225
Integrated Graphics Device Registers (D2:F0,F1)
8.1.2
DID—Device Identification
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/2/0/PCI
02–03h
2982h
RO
16 bits
This register combined with the Vendor Identification register uniquely identifies any
PCI device.
8.1.3
Bit
Access &
Default
15:0
RO
2982h
Description
Device Identification Number (DID): This is a 16 bit value
assigned to the GMCH Graphic device.
PCICMD2—PCI Command
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/2/0/PCI
04–05h
0000h
RO, RW
16 bits
This 16-bit register provides basic control over the IGD's ability to respond to PCI
cycles. The PCICMD Register in the IGD disables the IGD PCI compliant master
accesses to main memory.
Bit
Access &
Default
Description
15:11
RO
00h
Reserved
10
RW
0b
Interrupt Disable (INTDIS): This bit disables the device from
asserting INTx#.
0 = Enable the assertion of this device's INTx# signal.
1 = Disable the assertion of this device's INTx# signal. DO_INTx
messages will not be sent to DMI.
226
9
RO
0b
Fast Back-to-Back (FB2B): Not Implemented. Hardwired to 0.
8
RO
0b
SERR Enable (SERRE): Not Implemented. Hardwired to 0.
7
RO
0b
Address/Data Stepping Enable (ADSTEP): Not Implemented.
Hardwired to 0.
6
RO
0b
Parity Error Enable (PERRE): Not Implemented. Hardwired to 0.
Since the IGD belongs to the category of devices that does not corrupt
programs or data in system memory or hard drives, the IGD ignores
any parity error that it detects and continues with normal operation.
Datasheet
Integrated Graphics Device Registers (D2:F0,F1)
Bit
Access &
Default
Description
5
RO
0b
Video Palette Snooping (VPS): This bit is hardwired to 0 to disable
snooping.
4
RO
0b
Memory Write and Invalidate Enable (MWIE): Hardwired to 0.
The IGD does not support memory write and invalidate commands.
3
RO
0b
Special Cycle Enable (SCE): This bit is hardwired to 0. The IGD
ignores Special cycles.
2
RW
0b
Bus Master Enable (BME): This bit controls the IGD's response to
bus master accesses.
0 = Disable IGD bus mastering.
1 = Enable the IGD to function as a PCI compliant master.
1
RW
0b
Memory Access Enable (MAE): This bit controls the IGD's response
to memory space accesses.
0 = Disable.
1 = Enable.
0
RW
0b
I/O Access Enable (IOAE): This bit controls the IGD's response to
I/O space accesses.
0 = Disable.
1 = Enable.
Datasheet
227
Integrated Graphics Device Registers (D2:F0,F1)
8.1.4
PCISTS2—PCI Status
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/2/0/PCI
06–07h
0090h
RO, RWC
16 bits
PCISTS is a 16-bit status register that reports the occurrence of a PCI compliant
master abort and PCI compliant target abort. PCISTS also indicates the DEVSEL#
timing that has been set by the IGD.
Bit
Access &
Default
Description
15
RO
0b
Detected Parity Error (DPE): Since the IGD does not detect parity,
this bit is always hardwired to 0.
14
RO
0b
Signaled System Error (SSE): The IGD never asserts SERR#,
therefore this bit is hardwired to 0.
13
RO
0b
Received Master Abort Status (RMAS): The IGD never gets a
Master Abort, therefore this bit is hardwired to 0.
12
RO
0b
Received Target Abort Status (RTAS): The IGD never gets a
Target Abort, therefore this bit is hardwired to 0.
11
RO
0b
Signaled Target Abort Status (STAS): Hardwired to 0. The IGD
does not use target abort semantics.
10:9
RO
00b
DEVSEL Timing (DEVT): N/A. These bits are hardwired to "00".
8
RO
0b
Master Data Parity Error Detected (DPD): Since Parity Error
Response is hardwired to disabled (and the IGD does not do any
parity detection), this bit is hardwired to 0.
7
RO
1b
Fast Back-to-Back (FB2B): Hardwired to 1. The IGD accepts fast
back-to-back when the transactions are not to the same agent.
6
RO
0b
User Defined Format (UDF): Hardwired to 0.
5
RO
0b
66 MHz PCI Capable (66C): N/A - Hardwired to 0.
4
RO
1b
Capability List (CLIST): This bit is set to 1 to indicate that the
register at 34h provides an offset into the function's PCI
Configuration Space containing a pointer to the location of the first
item in the list.
3
RWC
0b
Interrupt Status (INTSTS): This bit reflects the state of the
interrupt in the device. Only when the Interrupt Disable bit in the
command register is a 0 and this Interrupt Status bit is a 1, will the
devices INTx# signal be asserted.
Setting the Interrupt Disable bit to a 1 has no effect on the state of
this bit. This bit is set by Hardware, and Software must write a '1' to
clear it.
2:0
228
RO
000b
Reserved
Datasheet
Integrated Graphics Device Registers (D2:F0,F1)
8.1.5
RID2—Revision Identification
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/2/0/PCI
08h
00h
RO
8 bits
This register contains the revision number for Device 2 Functions 0 and 1.
8.1.6
Bit
Access &
Default
7:0
RO
00h
Description
Revision Identification Number (RID): This is an 8-bit value that
indicates the revision identification number for the GMCH Device 2.
Refer to the Intel® G35 Express Chipset Specification Update for the
value of the Revision ID register.
CC—Class Code
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/2/0/PCI
09–0Bh
030000h
RO
24 bits
This register contains the device programming interface information related to the
Sub-Class Code and Base Class Code definition for the IGD. This register also contains
the Base Class Code and the function sub-class in relation to the Base Class Code.
Bit
Access &
Default
Description
23:16
RO
03h
Base Class Code (BCC): This is an 8-bit value that indicates the
base class code for the GMCH. This code has the value 03h, indicating
a Display Controller.
15:8
RO
00h
Sub-Class Code (SUBCC): Value will be determined based on
Device 0 GGC register, GMS and IVD fields.
00h = VGA compatible
80h = Non VGA (GMS = "0000" or IVD = "1")
7:0
Datasheet
RO
00h
Programming Interface (PI):
00h = Hardwired as a Display controller.
229
Integrated Graphics Device Registers (D2:F0,F1)
8.1.7
CLS—Cache Line Size
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/2/0/PCI
0Ch
00h
RO
8 bits
The IGD does not support this register as a PCI slave.
8.1.8
Bit
Access &
Default
7:0
RO
00h
Description
Cache Line Size (CLS): This field is hardwired to 0s. The IGD as a
PCI compliant master does not use the Memory Write and Invalidate
command and, in general, does not perform operations based on
cache line size.
MLT2—Master Latency Timer
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/2/0/PCI
0Dh
00h
RO
8 bits
The IGD does not support the programmability of the master latency timer because it
does not perform bursts.
230
Bit
Access &
Default
7:0
RO
00h
Description
Master Latency Timer Count Value (MLTCV): Hardwired to 0s.
Datasheet
Integrated Graphics Device Registers (D2:F0,F1)
8.1.9
HDR2—Header Type
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/2/0/PCI
0Eh
80h
RO
8 bits
This register contains the Header Type of the IGD.
8.1.10
Bit
Access &
Default
Description
7
RO
1b
Multi Function Status (MFUNC): Indicates if the device is a MultiFunction Device. The Value of this register is determined by Device 0,
offset 54h, DEVEN[4]. If Device 0 DEVEN[4] is set, the MFUNC bit is
also set.
6:0
RO
00h
Header Code (H): This is a 7-bit value that indicates the Header
Code for the IGD. This code has the value 00h, indicating a type 0
configuration space format.
GMADR—Graphics Memory Range Address
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/2/0/PCI
18–1Fh
00000008h
RW, RO, RW/L
64 bits
IGD graphics memory base address is specified in this register.
Bit
Access &
Default
Description
63:36
RO
35:29
RW
000b
Memory Base Address (MBA): Set by the OS, these bits correspond
to address signals 35:29.
28
RW/L
0b
512 MB Address Mask (512ADMSK): This Bit is either part of the
Memory Base Address (R/W) or part of the Address Mask (RO),
depending on the value of MSAC[1:0]. See MSAC (D2:F0, offset 62h)
for details.
27
RW/L
0b
256 MB Address Mask (256ADMSK): This bit is either part of the
Memory Base Address (R/W) or part of the Address Mask (RO),
depending on the value of MSAC[1:0]. See MSAC (D2:F0, offset 62h)
for details.
26:4
RO
000000h
3
RO
1b
Prefetchable Memory (PREFMEM): Hardwired to 1 to enable
prefetching.
2:1
RO
00b
Memory Type (MEMTYP):
Reserved
Address Mask (ADM): Hardwired to 0s to indicate at least 128 MB
address range.
0 = 32-bit address.
1 = 64-bit address
0
Datasheet
RO
0b
Memory/IO Space (MIOS): Hardwired to 0 to indicate memory
space.
231
Integrated Graphics Device Registers (D2:F0,F1)
8.1.11
IOBAR—I/O Base Address
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/2/0/PCI
20–23h
00000001h
RO, RW
32 bits
This register provides the Base offset of the I/O registers within Device 2. Bits 15:3
are programmable allowing the I/O Base to be located anywhere in 16 bit I/O Address
Space. Bits 2:1 are fixed and return zero; bit 0 is hardwired to a one indicating that 8
bytes of I/O space are decoded. Access to the 8Bs of I/O space is allowed in PM state
D0 when IO Enable (PCICMD bit 0) set. Access is disallowed in PM states D1–D3 or if
I/O Enable is clear or if Device 2 is turned off or if Internal graphics is disabled thru
the fuse or fuse override mechanisms.
Note that access to this IO BAR is independent of VGA functionality within Device 2.
Also note that this mechanism is available only through function 0 of Device 2 and is
not duplicated in function 1.
If accesses to this IO bar is allowed then the GMCH claims all 8, 16 or 32 bit I/O
cycles from the processor that falls within the 8B claimed.
8.1.12
Bit
Access &
Default
31:16
RO
0000h
Reserved
15:3
RW
0000h
IO Base Address (IOBASE): Set by the OS, these bits correspond
to address signals 15:3.
2:1
RO
00b
Memory Type (MEMTYPE): Hardwired to 0s to indicate 32-bit
address.
0
RO
1b
Memory/IO Space (MIOS): Hardwired to 1 to indicate I/O space.
SVID2—Subsystem Vendor Identification
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
232
Description
0/2/0/PCI
2C–2Dh
0000h
RWO
16 bits
Bit
Access &
Default
Description
15:0
RWO
0000h
Subsystem Vendor ID (SUBVID): This value is used to identify the
vendor of the subsystem. This register should be programmed by BIOS
during boot-up. Once written, this register becomes Read Only. This
register can only be cleared by a Reset.
Datasheet
Integrated Graphics Device Registers (D2:F0,F1)
8.1.13
SID2—Subsystem Identification
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
8.1.14
0/2/0/PCI
2E–2Fh
0000h
RWO
16 bits
Bit
Access &
Default
Description
15:0
RWO
0000h
Subsystem Identification (SUBID): This value is used to identify a
particular subsystem. This field should be programmed by BIOS during
boot-up. Once written, this register becomes Read Only. This register
can only be cleared by a Reset.
ROMADR—Video BIOS ROM Base Address
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/2/0/PCI
30–33h
00000000h
RO
32 bits
The IGD does not use a separate BIOS ROM, therefore this register is hardwired to 0s.
Datasheet
Bit
Access &
Default
Description
31:18
RO
0000h
17:11
RO
00h
10:1
RO
000h
Reserved. Hardwired to 0s.
0
RO
0b
ROM BIOS Enable (RBE):
ROM Base Address (RBA): Hardwired to 0s.
Address Mask (ADMSK): Hardwired to 0s to indicate 256 KB address
range.
0 = ROM not accessible.
233
Integrated Graphics Device Registers (D2:F0,F1)
8.1.15
CAPPOINT—Capabilities Pointer
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/2/0/PCI
34h
90h
RO
8 bits
Bit
Access &
Default
Description
7:0
RO
90h
Capabilities Pointer Value (CPV): This field contains an offset into
the function's PCI Configuration Space for the first item in the New
Capabilities Linked List, the MSI Capabilities ID registers at address
90h or the Power Management capability at D0h.
This value is determined by the configuration in CAPL[0].
8.1.16
INTRLINE—Interrupt Line
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
8.1.17
Bit
Access &
Default
7:0
RW
00h
0/2/0/PCI
3Ch
00h
RW
8 bits
Description
Interrupt Connection (INTCON): This field is used to
communicate interrupt line routing information. POST software
writes the routing information into this register as it initializes and
configures the system. The value in this register indicates to which
input of the system interrupt controller the device's interrupt pin is
connected.
INTRPIN—Interrupt Pin
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Bit
Access &
Default
7:0
RO
01h
0/2/0/PCI
3Dh
01h
RO
8 bits
Description
Interrupt Pin (INTPIN): As a single function device, the IGD
specifies INTA# as its interrupt pin.
01h = INTA#.
234
Datasheet
Integrated Graphics Device Registers (D2:F0,F1)
8.1.18
MINGNT—Minimum Grant
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
8.1.19
Bit
Access &
Default
7:0
RO
00h
Description
Minimum Grant Value (MGV): The IGD does not burst as a PCI
compliant master.
MAXLAT—Maximum Latency
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Datasheet
0/2/0/PCI
3Eh
00h
RO
8 bits
Bit
Access &
Default
7:0
RO
00h
0/2/0/PCI
3Fh
00h
RO
8 bits
Description
Maximum Latency Value (MLV): The IGD has no specific
requirements for how often it needs to access the PCI bus.
235
Integrated Graphics Device Registers (D2:F0,F1)
8.1.20
MCAPPTR—Mirror of Dev 0 Capabilities Pointer
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/2/0/PCI
44h
E0h
RO
8 bits
The CAPPTR provides the offset that is the pointer to the location of the first device
capability in the capability list.
8.1.21
Bit
Access &
Default
7:0
RO
E0h
Description
Mirror of CAPPTR (MCAPPTR): Pointer to the offset of the first
capability ID register block. In this case the first capability is the
product-specific Capability Identifier (CAPID0).
CAPID0—Mirror of Dev0 Capability Identifier
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
236
0/2/0/PCI
48–51h
00000000000001090009h
RO
80 bits
Bit
Access &
Default
Description
79:26
RO
00000000
00000h
27:24
RO
1h
CAPID Version (CAPIDV): This field has the value 0001b to identify
the first revision of the CAPID register definition.
23:16
RO
09h
CAPID Length (CAPIDL): This field has the value 09h to indicate the
structure length (9 bytes).
15:8
RO
00h
Next Capability Pointer (NCP): This field is hardwired to 00h
indicating the end of the capabilities linked list.
7:0
RO
09h
Capability Identifier (CAP_ID): This field has the value 1001b to
identify the CAP_ID assigned by the PCI SIG for vendor dependent
capability pointers.
Reserved
Datasheet
Integrated Graphics Device Registers (D2:F0,F1)
8.1.22
MGGC— Mirror of Dev0 GMCH Graphics Control Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Bit
Access &
Default
15:7
RO
0s
6:4
RO
011b
0/2/0/PCI
52–53h
0030h
RO
16 bits
Description
Reserved
Graphics Mode Select (GMS): This field is used to select the
amount of Main Memory that is pre-allocated to support the Internal
Graphics device in VGA (non-linear) and Native (linear) modes. The
BIOS ensures that memory is pre-allocated only when Internal
graphics is enabled.
000 = No memory pre-allocated. Device 2 (IGD) does not claim VGA
cycles (Mem and IO), and the Sub-Class Code field within
Device 2 function 0 Class Code register is 80.
001 = DVMT (UMA) mode, 1 MB of memory pre-allocated for frame
buffer.
010 = Reserved
011 = DVMT (UMA) mode, 8 MB of memory pre-allocated for frame
buffer.
100 = Reserved
101 = Reserved
110 = Reserved
111 = Reserved
Note: This register is locked and becomes Read Only when the
D_LCK bit in the
SMRAM register is set.
3:2
RO
00b
Reserved
1
RO
0b
IGD VGA Disable (IVD):
0 = Enable. Device 2 (IGD) claims VGA memory and I/O cycles, the
Sub-Class Code within Device 2 Class Code register is 00.
1 = Disable. Device 2 (IGD) does not claim VGA cycles (Memory and
I/O), and the Sub- Class Code field within Device 2, Function 0
Class Code register is 80h.
0
Datasheet
RO
0b
Reserved
237
Integrated Graphics Device Registers (D2:F0,F1)
8.1.23
DEVEN—Mirror of Dev0 Device Enable
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/2/0/PCI
54–57h
000003DBh
RO
32 bits
This register allows for enabling/disabling of PCI devices and functions that are within
the GMCH. The table below the bit definitions describes the behavior of all
combinations of transactions to devices controlled by this register.
Bit
Access &
Default
Description
31:10
RO
0s
Reserved
9
RO
1b
ME Function 3 (D3F3EN):
0 = Bus 0, Device 3, Function 3 is disabled and hidden
1 = Bus 0, Device 3, Function 3 is enabled and visible. If Device 3,
Function 0 is disabled and hidden, then Device 3, Function 3 is also
disabled and hidden independent of the state of this bit.
8
RO
1b
ME Function 2 (D3F2EN):
0 = Bus 0, Device 3, Function 2 is disabled and hidden
1 = Bus 0, Device 3, Function 2 is enabled and visible. If Device 3,
Function 0 is disabled and hidden, then Device 3, Function 2 is also
disabled and hidden independent of the state of this bit.
7
RO
1b
Reserved
6
RO
1b
ME Function 0 (D3F0EN):
0 = Bus 0, Device 3, Function 0 is disabled and hidden
1 = Bus 0, Device 3, Function 0 is enabled and visible. If this GMCH
does not have ME capability, then Device 3, Function 0 is disabled
and hidden independent of the state of this bit.
5
RO
0b
Reserved
4
RO
1b
Internal Graphics Engine Function 1 (D2F1EN):
0 = Bus 0, Device 2, Function 1 is disabled and hidden
1 = Bus 0, Device 2, Function 1 is enabled and visible
If Device 2, Function 0 is disabled and hidden, then Device 2, Function
1 is also disabled and hidden independent of the state of this bit.
3
RO
1b
Internal Graphics Engine Function 0 (D2F0EN):
0 = Bus 0, Device 2, Function 0 is disabled and hidden
1 = Bus 0, Device 2, Function 0 is enabled and visible
238
Datasheet
Integrated Graphics Device Registers (D2:F0,F1)
Bit
Access &
Default
Description
2
RO
0b
Reserved
1
RO
1b
PCI Express Port (D1EN):
0 = Bus 0, Device 1, Function 0 is disabled and hidden.
1 = Bus 0, Device 1, Function 0 is enabled and visible.
0
8.1.24
RO
1b
Host Bridge (D0EN): Bus 0, Device 0, Function 0 may not be
disabled and is therefore hardwired to 1.
SSRW—Software Scratch Read Write
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
8.1.25
Bit
Access &
Default
31:0
RW
00000000h
0/2/0/PCI
58–5Bh
00000000h
RW
32 bits
Description
Reserved
BSM—Base of Stolen Memory
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/2/0/PCI
5C–5Fh
07800000h
RO
32 bits
Graphics Stolen Memory and TSEG are within DRAM space defined under TOLUD.
From the top of low used DRAM, GMCH claims 1 to 64 MBs of DRAM for internal
graphics if enabled.
The base of stolen memory will always be below 4 GB. This is required to prevent
aliasing between stolen range and the reclaim region.
Datasheet
Bit
Access &
Default
31:20
RO
078h
19:0
RO
00000h
Description
Base of Stolen Memory (BSM): This register contains bits 31:20 of
the base address of stolen DRAM memory. The host interface
determines the base of Graphics Stolen memory by subtracting the
graphics stolen memory size from TOLUD. See Device 0 TOLUD for
more explanation.
Reserved
239
Integrated Graphics Device Registers (D2:F0,F1)
8.1.26
HSRW—Hardware Scratch Read Write
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
8.1.27
Bit
Access &
Default
15:0
RW
0000h
0/2/0/PCI
60–61h
0000h
RW
16 bits
Description
Reserved
MSI_CAPID— Message Signaled Interrupts Capability ID
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/2/0/PCI
90–91h
D005h
RO;
16 bits
When a device supports MSI, it can generate an interrupt request to the processor by
writing a predefined data item (a message) to a predefined memory address. The
reporting of the existence of this capability can be disabled by setting MSICH (CAPL[0]
@ 7Fh). In that case walking this linked list will skip this capability and instead go
directly to the PCI PM capability.
240
Bit
Access &
Default
Description
15:8
RO
D0h
Pointer to Next Capability (POINTNEXT): This contains a pointer
to the next item in the capabilities list which is the Power Management
capability.
7:0
RO
05h
Capability ID (CAPID): Value of 05h identifies this linked list item
(capability structure) as being for MSI registers.
Datasheet
Integrated Graphics Device Registers (D2:F0,F1)
8.1.28
MC—Message Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/2/0/PCI
92–93h
0000h
RO, RW
16 bits
System software can modify bits in this register, but the device is prohibited from
doing so. If the device writes the same message multiple times, only one of those
messages is ensured to be serviced. If all of them must be serviced, the device must
not generate the same message again until the driver services the earlier one.
Bit
Access &
Default
Description
15:8
RO
00h
Reserved
7
RO
0b
64 Bit Capable (64BCAP): Hardwired to 0 to indicate that the
function does not implement the upper 32 bits of the Message address
register and is incapable of generating a 64-bit memory address.
This may need to change in future implementations when addressable
system memory exceeds the 32b / 4 GB limit.
6:4
RW
000b
Multiple Message Enable (MME): System software programs this
field to indicate the actual number of messages allocated to this
device. This number will be equal to or less than the number actually
requested.
The encoding is the same as for the MMC field (Bits 3:1).
3:1
RO
000b
Multiple Message Capable (MMC): System Software reads this field
to determine the number of messages being requested by this device.
000 = 1
All other encodings are reserved.
0
Datasheet
RW
0b
MSI Enable (MSIEN): This bit controls the ability of this device to
generate MSIs.
241
Integrated Graphics Device Registers (D2:F0,F1)
8.1.29
MA—Message Address
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Bit
Access &
Default
Description
31:2
RW
00000000
h
Message Address (MESSADD): Used by system software to assign
an MSI address to the device.
RO
00b
Force DWord Align (FDWORD): Hardwired to 0 so that addresses
assigned by system software are always aligned on a DWord address
boundary.
1:0
8.1.30
0/2/0/PCI
94–97h
00000000h
RW, RO
32 bits
The device handles an MSI by writing the padded contents of the MD
register to this address.
MD—Message Data
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Bit
Access &
Default
15:0
RW
0000h
0/2/0/PCI
98–99h
0000h
RW
16 bits
Description
Message Data (MESSDATA): Base message data pattern assigned
by system software and used to handle an MSI from the device.
When the device must generate an interrupt request, it writes a 32-bit
value to the memory address specified in the MA register. The upper
16 bits are always set to 0. The lower 16 bits are supplied by this
register.
242
Datasheet
Integrated Graphics Device Registers (D2:F0,F1)
8.1.31
GDRST—Graphics Debug Reset
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/2/0/PCI
C0h
00h
RO, RW
8 bits
Bit
Access &
Default
Description
7:2
RO
0h
Reserved
1
RO
0b
Graphics Reset Status (GRS):
0 = Graphics subsystem not in Reset.
1 = Graphics Subsystem in Reset as a result of Graphics Reset.
This bit gets is set to a 1 when Graphics debug reset bit is set to a 1
and the Graphics hardware has completed the debug reset sequence
and all Graphics assets are in reset. This bit is cleared when Graphics
Reset bit is set to a 0.
0
RW
0b
Graphics Reset Enable (GR):
1 = Assert display and render domain reset
0 = De-assert display and render domain reset
Render and Display clock domain resets should be asserted for at least
20 us. Once this bit is set to a 1, all graphics core MMIO registers are
returned to power on default state. All Ring buffer pointers are reset,
command stream fetches are dropped and ongoing render pipeline
processing is halted, state machines and State Variables returned to
power on default state, Display and overlay engines are halted
(garbage on screen). VGA memory is not available, Store DWORDs
and interrupts are not ensured to be completed. Device 2 I/O registers
are not available.
Device 2 Configuration registers continue to be available while
Graphics debug reset is asserted.
Datasheet
243
Integrated Graphics Device Registers (D2:F0,F1)
8.1.32
PMCAPID—Power Management Capabilities ID
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Bit
Access &
Default
15:8
RWO
00h
Next Capability Pointer (NEXT_PTR): This contains a pointer to next
RO
01h
Capability Identifier (CAP_ID): SIG defines this ID is 01h for
power management.
7:0
8.1.33
0/2/0/PCI
D0–D1h
0001h
RWO, RO
16 bits
Description
item in capabilities list. This is the final capability in the list and must
be set to 00h.
PMCAP—Power Management Capabilities
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/2/0/PCI
D2–D3h
0022h
RO
16 bits
This register is a Mirror of Function 0 with the same read/write attributes. The
hardware implements a single physical register common to both functions 0 and 1.
244
Bit
Access &
Default
Description
15:11
RO
00h
PME Support (PMES): This field indicates the power states in which
the IGD may assert PME#. Hardwired to 0 to indicate that the IGD
does not assert the PME# signal.
10
RO
0b
D2 Support (D2): The D2 power management state is not supported.
This bit is hardwired to 0.
9
RO
0b
D1 Support (D1): Hardwired to 0 to indicate that the D1 power
management state is not supported.
8:6
RO
000b
5
RO
1b
Device Specific Initialization (DSI): Hardwired to 1 to indicate that
special initialization of the IGD is required before generic class device
driver is to use it.
4
RO
0b
Reserved
3
RO
0b
PME Clock (PMECLK): Hardwired to 0 to indicate IGD does not
support PME# generation.
2:0
RO
010b
Reserved
Version (VER): Hardwired to 010b to indicate that there are 4 bytes
of power management registers implemented and that this device
complies with revision 1.1 of the PCI Power Management Interface
Specification.
Datasheet
Integrated Graphics Device Registers (D2:F0,F1)
8.1.34
PMCS—Power Management Control/Status
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/2/0/PCI
D4–D5h
0000h
RO, RW
16 bits
Bit
Access &
Default
Description
15
RO
0b
PME Status (PMESTS): This bit is 0 to indicate that IGD does not
support PME# generation from D3 (cold).
14:13
RO
00b
Data Scale (DSCALE): The IGD does not support data register. This
bit always returns 00 when read, write operations have no effect.
12:9
RO
0h
Data Select (DSEL): The IGD does not support data register. This bit
always returns 0h when read, write operations have no effect.
8
RO
0b
PME Enable (PME_EN): This bit is 0 to indicate that PME# assertion
from D3 (cold) is disabled.
7:2
RO
00h
Reserved
1:0
RW
00b
Power State (PWRSTAT): This field indicates the current power
state of the IGD and can be used to set the IGD into a new power
state. If software attempts to write an unsupported state to this field,
write operation must complete normally on the bus, but the data is
discarded and no state change occurs. On a transition from D3 to D0
the graphics controller is optionally reset to initial values.
00 = D0 (Default)
01 = D1 (Not Supported)
10 = D2 (Not Supported)
11 = D3
Datasheet
245
Integrated Graphics Device Registers (D2:F0,F1)
8.1.35
SWSMI—Software SMI
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/2/0/PCI
E0–E1h
0000h
RW
16 bits
As long as there is the potential that DVO port legacy drivers exist which expect this
register at this address, D2, F0 address E0h–E1h must be reserved for this register.
246
Bit
Access &
Default
Description
15:8
RW
00h
Software Scratch Bits (SWSB):
7:1
RW
00h
Software Flag (SWF): Used to indicate caller and SMI function
desired, as well as return result.
0
RW
0b
GMCH Software SMI Event (GSSMIE): When Set this bit will
trigger an SMI. Software must write a "0" to clear this bit.
Datasheet
Integrated Graphics Device Registers (D2:F0,F1)
8.2
IGD Configuration Register Details (D2:F1)
The Integrated Graphics Device registers are located in Device 2 (D2), Function 0 (F0)
and Function 1 (F1). This section provides the descriptions for the D2:F1 registers.
Table 8-2 provides an address map of the D2:F1registers listed in ascending order by
address offset. Detailed bit descriptions follow the table.
Table 8-2. Integrated Graphics Device Register Address Map (D2:F1)
Datasheet
Address
Offset
Register
Symbol
00–01h
VID2
02–03h
DID2
04–05h
Register Name
Default
Value
Access
Vendor Identification
8086h
RO
Device Identification
29C3h
RO
PCICMD2
PCI Command
0000h
RO, RW
06–07h
PCISTS2
PCI Status
0090h
RO
08h
RID2
00h
RO
09–0Bh
CC
Class Code Register
038000h
RO
0Ch
CLS
Cache Line Size
00h
RO
0Dh
MLT2
Master Latency Timer
00h
RO
0Eh
HDR2
Header Type
80h
RO
10–13h
MMADR
Memory Mapped Range Address
00000000h
RW, RO
2C–2Dh
SVID2
Subsystem Vendor Identification
0000h
RO
2E–2Fh
SID2
Subsystem Identification
0000h
RO
30–33h
ROMADR
00000000h
RO
34h
CAPPOINT
Capabilities Pointer
D0h
RO
3Eh
MINGNT
Minimum Grant
00h
RO
3Fh
MAXLAT
Maximum Latency
00h
RO
44h
MCAPPTR
Mirror of Dev 0 Capabilities Pointer
E0h
RO
48–51h
CAPID0
00000000000
001090009h
RO
52–53h
MGGC
Mirror of Dev 0 GMCH Graphics
Control Register
0030h
RO
54–57h
DEVEN
Device Enable
000003DBh
RO
58–5Bh
SSRW
Mirror of Fun 0 Software Scratch
Read Write
00000000h
RO
5C–5Fh
BSM
Mirror of Func0 Base of Stolen
Memory
07800000h
RO
60–61h
HSRW
Mirror of Dev2 Func0 Hardware
Scratch Read Write
0000h
RO
Revision Identification
Video BIOS ROM Base Address
Capability Identifier
247
Integrated Graphics Device Registers (D2:F0,F1)
248
Address
Offset
Register
Symbol
62h
MSAC
C0h
GDRST
C1–C3h
MI_GFX_CG_
DIS
C4–C7h
RSVD
C8h
Register Name
Default
Value
Access
Mirror of Dev2 Func0 Multi Size
Aperture Control
02h
RO
Mirror of Dev2 Func0 Graphics
Reset
00h
RO
000000h
RO
Reserved
00000000h
RO
RSVD
Reserved
00h
RO
CA–CBh
RSVD
Reserved
0000h
RO
CC–CDh
GCDGMBUS
Mirror of Dev2 Func0 Graphics
Clock Frequency Register for
GMBUS unit
0000h
RO
D0–D1h
PMCAPID
Mirror of Fun 0 Power
Management Capabilities ID
0001h
RO
D2–D3h
PMCAP
Mirror of Fun 0 Power
Management Capabilities
0022h
RO
D4–D5h
PMCS
Power Management Control/Status
0000h
RO, RW
D8–DBh
RSVD
Reserved
00000000h
RO
E0–E1h
SWSMI
Mirror of Func0 Software SMI
0000h
RO
E4–E7h
ASLE
Mirror of Dev2 Func0 System
Display Event Register
00000000h
RO
F0–F3h
GCFGC
Mirror of Dev2 Func0 Graphics
Clock Frequency and Gating
Control
00000000h
RO/P,
RO
F4–F7h
RSVD
Mirror of Fun 0 Reserved for LBBLegacy Backlight Brightness
00000000h
RO
FC–FFh
ASLS
ASL Storage
00000000h
RW
Mirror of Fun 0 MI GFX Unit Level
Clock Ungating
Datasheet
Integrated Graphics Device Registers (D2:F0,F1)
8.2.1
VID2—Vendor Identification
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/2/1/PCI
00–01h
8086h
RO
16 bits
This register, combined with the Device Identification register, uniquely identifies any
PCI device.
8.2.2
Bit
Access &
Default
15:0
RO
8086h
Description
Vendor Identification Number (VID): PCI standard identification
for Intel.
DID2—Device Identification
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/2/1/PCI
02–03h
29C3h
RO
16 bits
This register is unique in Function 1 (the Function 0 DID is separate). This difference
in Device ID is necessary for allowing distinct Plug and Play enumeration of function 1
when both function 0 and function 1 have the same class code.
Datasheet
Bit
Access &
Default
15:0
RO
2983h
Description
Device Identification Number (DID): This is a 16 bit value
assigned to the GMCH Graphic device Function 1.
249
Integrated Graphics Device Registers (D2:F0,F1)
8.2.3
PCICMD2—PCI Command
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/2/1/PCI
04–05h
0000h
RO, RW
16 bits
This 16-bit register provides basic control over the IGD's ability to respond to PCI
cycles. The PCICMD Register in the IGD disables the IGD PCI compliant master
accesses to main memory.
Bit
Access &
Default
Description
15:10
RO
0s
Reserved
9
RO
0b
Fast Back-to-Back (FB2B): Not Implemented. Hardwired to 0.
8
RO
0b
SERR Enable (SERRE): Not Implemented. Hardwired to 0.
7
RO
0b
Address/Data Stepping Enable (ADSTEP): Not Implemented.
Hardwired to 0.
6
RO
0b
Parity Error Enable (PERRE): Not Implemented. Hardwired to 0.
Since the IGD belongs to the category of devices that does not corrupt
programs or data in system memory or hard drives, the IGD ignores
any parity error that it detects and continues with normal operation.
5
RO
0b
VGA Palette Snoop Enable (VGASNOOP): This bit is hardwired to 0
to disable snooping.
4
RO
0b
Memory Write and Invalidate Enable (MWIE): Hardwired to 0.
The IGD does not support memory write and invalidate commands.
3
RO
0b
Special Cycle Enable (SCE): This bit is hardwired to 0. The IGD
ignores Special cycles.
2
RW
0b
Bus Master Enable (BME):
0 = Disable IGD bus mastering.
1 = Enable the IGD to function as a PCI compliant master.
1
RW
0b
Memory Access Enable (MAE): This bit controls the IGD's response
to memory space accesses.
0 = Disable.
1 = Enable.
0
RW
0b
I/O Access Enable (IOAE): This bit controls the IGD's response to
I/O space accesses.
0 = Disable.
1 = Enable.
250
Datasheet
Integrated Graphics Device Registers (D2:F0,F1)
8.2.4
PCISTS2—PCI Status
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/2/1/PCI
06–07h
0090h
RO
16 bits
PCISTS is a 16-bit status register that reports the occurrence of a PCI compliant
master abort and PCI compliant target abort. PCISTS also indicates the DEVSEL#
timing that has been set by the IGD.
Datasheet
Bit
Access &
Default
Description
15
RO
0b
Detected Parity Error (DPE): Since the IGD does not detect parity,
this bit is always hardwired to 0.
14
RO
0b
Signaled System Error (SSE): The IGD never asserts SERR#,
therefore this bit is hardwired to 0.
13
RO
0b
Received Master Abort Status (RMAS): The IGD never gets a
Master Abort, therefore this bit is hardwired to 0.
12
RO
0b
Received Target Abort Status (RTAS): The IGD never gets a
Target Abort, therefore this bit is hardwired to 0.
11
RO
0b
Signaled Target Abort Status (STAS): Hardwired to 0. The IGD
does not use target abort semantics.
10:9
RO
00b
DEVSEL Timing (DEVT): N/A. These bits are hardwired to 00.
8
RO
0b
Master Data Parity Error Detected (DPD): Since Parity Error
Response is hardwired to disabled (and the IGD does not do any
parity detection), this bit is hardwired to 0.
7
RO
1b
Fast Back-to-Back (FB2B): Hardwired to 1. The IGD accepts fast
back-to-back when the transactions are not to the same agent.
6
RO
0b
User Defined Format (UDF): Hardwired to 0.
5
RO
0b
66 MHz PCI Capable (66C): N/A - Hardwired to 0.
4
RO
1b
Capability List (CLIST): This bit is set to 1 to indicate that the
register at 34h provides an offset into the function's PCI Configuration
Space containing a pointer to the location of the first item in the list.
3
RO
0b
Interrupt Status (INTSTS): Hardwired to 0.
2:0
RO
000b
Reserved
251
Integrated Graphics Device Registers (D2:F0,F1)
8.2.5
RID2—Revision Identification
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/2/1/PCI
08h
00h
RO
8 bits
This register contains the revision number for Device 2, Functions 0 and 1.
8.2.6
Bit
Access &
Default
7:0
RO
00h
Description
Revision Identification Number (RID): This is an 8-bit value that
indicates the revision identification number for the GMCH Device 2.
Refer to the Intel® G35 Express Chipset Specification Update for the
value of the Revision ID register.
CC—Class Code Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/2/1/PCI
09–0Bh
038000h
RO
24 bits
This register contains the device programming interface information related to the
Sub-Class Code and Base Class Code definition for the IGD. This register also contains
the Base Class Code and the function sub-class in relation to the Base Class Code.
Bit
Access &
Default
Description
23:16
RO
03h
Base Class Code (BCC): This is an 8-bit value that indicates the
base class code for the GMCH. This code has the value 03h, indicating
a Display Controller.
15:8
RO
80h
Sub-Class Code (SUBCC):
RO
00h
Programming Interface (PI):
7:0
252
80h = Non VGA
00h = Hardwired as a Display controller.
Datasheet
Integrated Graphics Device Registers (D2:F0,F1)
8.2.7
CLS—Cache Line Size
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/2/1/PCI
0Ch
00h
RO
8 bits
The IGD does not support this register as a PCI slave.
8.2.8
Bit
Access &
Default
7:0
RO
00h
Description
Cache Line Size (CLS): This field is hardwired to 0s. The IGD as a
PCI compliant master does not use the Memory Write and Invalidate
command and, in general, does not perform operations based on
cache line size.
MLT2—Master Latency Timer
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/2/1/PCI
Dh
00h
RO
8 bits
The IGD does not support the programmability of the master latency timer because it
does not perform bursts.
Datasheet
Bit
Access &
Default
7:0
RO
00h
Description
Master Latency Timer Count Value (MLTCV): Hardwired to 0s.
253
Integrated Graphics Device Registers (D2:F0,F1)
8.2.9
HDR2—Header Type
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/2/1/PCI
0Eh
80h
RO
8 bits
This register contains the Header Type of the IGD.
8.2.10
Bit
Access &
Default
Description
7
RO
1b
Multi Function Status (MFUNC): Indicates if the device is a MultiFunction Device. The Value of this register is determined by Device 0,
offset 54h, DEVEN[4]. If Device 0 DEVEN[4] is set, the MFUNC bit is
also set.
6:0
RO
00h
Header Code (H): This is a 7-bit value that indicates the Header Code
for the IGD. This code has the value 00h, indicating a type 0
configuration space format.
MMADR—Memory Mapped Range Address
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/2/1/PCI
10–13h
00000000h
RW, RO
64 bits
This register requests allocation for the IGD registers and instruction ports. The
allocation is for 512 KB and the base address is defined by bits 31:19.
254
Bit
Access &
Default
Description
63:36
RO
0s
35:20
RW
0000h
Memory Base Address (MBA): Set by the OS, these bits correspond
to address signals 35:19.
18:4
RO
0000h
Address Mask (ADMSK): Hardwired to 0s to indicate 512 KB address
range.
3
RO
0b
Prefetchable Memory (PREFMEM): Hardwired to 0 to prevent
prefetching.
2:1
RO
00b
Memory Type (MEMTYP): Hardwired to 0s to indicate 32-bit
address.
0
RO
0b
Memory / IO Space (MIOS): Hardwired to 0 to indicate memory
space.
Datasheet
Integrated Graphics Device Registers (D2:F0,F1)
8.2.11
SVID2—Subsystem Vendor Identification
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
8.2.12
Bit
Access &
Default
Description
15:0
RO
0000h
Subsystem Vendor ID (SUBVID): This value is used to identify the
vendor of the subsystem. This register should be programmed by
BIOS during boot-up. Once written, this register becomes Read Only.
This register can only be cleared by a Reset.
SID2—Subsystem Identification
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Datasheet
0/2/1/PCI
2C–2Dh
0000h
RO
16 bits
0/2/1/PCI
2E–2Fh
0000h
RO
16 bits
Bit
Access &
Default
Description
15:0
RO
0000h
Subsystem Identification (SUBID): This value is used to identify a
particular subsystem. This field should be programmed by BIOS
during boot-up. Once written, this register becomes Read Only. This
register can only be cleared by a Reset.
255
Integrated Graphics Device Registers (D2:F0,F1)
8.2.13
ROMADR—Video BIOS ROM Base Address
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/2/1/PCI
30–33h
00000000h
RO
32 bits
The IGD does not use a separate BIOS ROM, therefore this register is hardwired to 0s.
8.2.14
Bit
Access &
Default
Description
31:18
RO
0000h
17:11
RO
00h
10:1
RO
000h
Reserved. Hardwired to 0s.
0
RO
0b
ROM BIOS Enable (RBE):
ROM Base Address (RBA): Hardwired to 0s.
Address Mask (ADMSK): Hardwired to 0s to indicate 256 KB address
range.
0 =
ROM not accessible.
CAPPOINT—Capabilities Pointer
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Bit
Access &
Default
7:0
RO
D0h
0/2/1/PCI
34h
D0h
RO
8 bits
Description
Capabilities Pointer Value (CPV): This field contains an offset into
the function's PCI Configuration Space for the first item in the New
Capabilities Linked List, the MSI Capabilities ID registers at address
90h or the Power Management capability at D0h.
This value is determined by the configuration in CAPL[0].
256
Datasheet
Integrated Graphics Device Registers (D2:F0,F1)
8.2.15
MINGNT—Minimum Grant
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
8.2.16
Bit
Access &
Default
7:0
RO
00h
Description
Minimum Grant Value (MGV): The IGD does not burst as a PCI
compliant master.
MAXLAT—Maximum Latency
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
8.2.17
0/2/1/PCI
3Eh
00h
RO
8 bits
Bit
Access &
Default
7:0
RO
00h
0/2/1/PCI
3Fh
00h
RO
8 bits
Description
Maximum Latency Value (MLV): The IGD has no specific
requirements for how often it needs to access the PCI bus.
MCAPPTR—Mirror of Dev 0 Capabilities Pointer
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/2/1/PCI
44h
E0h
RO;
8 bits
The CAPPTR provides the offset that is the pointer to the location of the first device
capability in the capability list.
Datasheet
Bit
Access &
Default
7:0
RO
Description
Mirror of CAPPTR (MCAPPTR): Pointer to the offset of the first
capability ID register block. In this case the first capability is the
product-specific Capability Identifier (CAPID0).
257
Integrated Graphics Device Registers (D2:F0,F1)
8.2.18
CAPID0—Capability Identifier
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
258
0/2/1/PCI
48–51h
00000000000001090009h
RO
80 bits
Bit
Access &
Default
Description
79:26
RO
00000000
00000h
27:24
RO
1h
CAPID Version (CAPIDV): This field has the value 0001b to identify
the first revision of the CAPID register definition.
23:16
RO
09h
CAPID Length (CAPIDL): This field has the value 09h to indicate the
structure length (9 bytes).
15:8
RO
00h
Next Capability Pointer (NCP): This field is hardwired to 00h
indicating the end of the capabilities linked list.
7:0
RO
09h
Capability Identifier (CAP_ID): This field has the value 1001b to
identify the CAP_ID assigned by the PCI SIG for vendor dependent
capability pointers.
Reserved
Datasheet
Integrated Graphics Device Registers (D2:F0,F1)
8.2.19
MGGC—Mirror of Dev 0 GMCH Graphics Control Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Bit
Access &
Default
15:7
RO
00h
6:4
RO
011b
0/2/1/PCI
52–53h
0030h
RO
16 bits
Description
Reserved
Graphics Mode Select (GMS). This field is used to select the amount
of Main Memory that is pre-allocated to support the Internal Graphics
device in VGA (non-linear) and Native (linear) modes. The BIOS
ensures that memory is pre-allocated only when Internal graphics is
enabled.
000 = No memory pre-allocated. Device 2 (IGD) does not claim VGA
cycles (Mem and IO), and the Sub-Class Code field within
Device 2 function 0 Class Code register is 80.
001 = DVMT (UMA) mode, 1 MB of memory pre-allocated for frame
buffer.
010 = Reserved
011 = DVMT (UMA) mode, 8 MB of memory pre-allocated for frame
buffer.
100 = Reserved
101 = Reserved
110 = Reserved
111 = Reserved
Note: This register is locked and becomes Read Only when the D_LCK
bit in the
SMRAM register is set.
3:2
RO
00b
Reserved
1
RO
0b
IGD VGA Disable (IVD):
0 = Enable. Device 2 (IGD) claims VGA memory and I/O cycles, the
Sub-Class Code within Device 2 Class Code register is 00.
1 = Disable. Device 2 (IGD) does not claim VGA cycles (Memory and
I/O), and the Sub- Class Code field within Device 2, function 0
Class Code register is 80h.
0
Datasheet
RO
0b
Reserved
259
Integrated Graphics Device Registers (D2:F0,F1)
8.2.20
DEVEN—Device Enable
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/2/1/PCI
54–57h
000003DBh
RO
32 bits
This register allows for enabling/disabling of PCI devices and functions that are within
the GMCH. The table below the bit definitions describes the behavior of all
combinations of transactions to devices controlled by this register.
Bit
Access &
Default
31:10
RO
00000h
9
RO
1b
Description
Reserved
ME Function 3 (D3F3EN):
0 = Bus 0, Device 3, Function 3 is disabled and hidden
1 = Bus 0, Device 3, Function 3 is enabled and visible If Device 3,
Function 0 is disabled and hidden, then Device 3, Function 3 is
also disabled and hidden independent of the state of this bit.
8
RO
1b
ME Function 2 (D3F2EN):
0 = Bus0, Device 3, Function 2 is disabled and hidden
1 = Bus 0, Device 3, Function 2 is enabled and visible If Device 3,
Function 0 is disabled and hidden, then Device 3, Function 2 is
also disabled and hidden independent of the state of this bit.
7
RO
1b
Reserved
6
RO
1b
ME Function 0 (D3F0EN):
0 = Bus 0, Device 3, Function 0 is disabled and hidden
1 = Bus 0, Device 3, Function 0 is enabled and visible. If this GMCH
does not have ME capability (CAPID0[??] = 1), then Device 3,
Function 0 is disabled and hidden independent of the state of this
bit.
5
RO
0b
Reserved
4
RO
1b
Internal Graphics Engine Function 1 (D2F1EN):
0 = Bus 0, Device 2, Function 1 is disabled and hidden
1 = Bus 0, Device 2, Function 1 is enabled and visible
If Device 2, Function 0 is disabled and hidden, then Device 2,
Function 1 is also disabled and hidden independent of the state of this
bit.
260
Datasheet
Integrated Graphics Device Registers (D2:F0,F1)
Bit
Access &
Default
3
RO
1b
Description
Internal Graphics Engine Function 0 (D2F0EN):
0 = Bus 0, Device 2, Function 0 is disabled and hidden
1 = Bus 0, Device 2, Function 0 is enabled and visible
2
RO
0b
Reserved
1
RO
1b
PCI Express Port (D1EN):
0 = Bus 0, Device 1, Function 0 is disabled and hidden.
1 = Bus 0, Device 1, Function 0 is enabled and visible.
0
8.2.21
RO
1b
Host Bridge (D0EN): Bus 0 Device 0 Function 0 may not be
disabled and is therefore hardwired to 1.
SSRW—Mirror of Func0 Software Scratch Read Write
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Datasheet
Bit
Access &
Default
31:0
RO
00000000h
0/2/1/PCI
58–5Bh
00000000h
RO
32 bits
Description
Reserved
261
Integrated Graphics Device Registers (D2:F0,F1)
8.2.22
BSM—Mirror of Func0 Base of Stolen Memory
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/2/1/PCI
5C–5Fh
07800000h
RO
32 bits
Graphics Stolen Memory and TSEG are within DRAM space defined under TOLUD.
From the top of low used DRAM, GMCH claims 1 to 64 MBs of DRAM for internal
graphics if enabled.
The base of stolen memory will always be below 4 GB. This is required to prevent
aliasing between stolen range and the reclaim region.
8.2.23
Bit
Access &
Default
Description
31:20
RO
078h
Base of Stolen Memory (BSM): This register contains bits 31:20 of
the base address of stolen DRAM memory. The host interface
determines the base of Graphics Stolen memory by subtracting the
graphics stolen memory size from TOLUD. See Device 0 TOLUD for
more explanation.
19:0
RO
00000h
Reserved
HSRW—Mirror of Dev2 Func0 Hardware Scratch Read
Write
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
262
Bit
Access &
Default
15:0
RO
0000h
0/2/1/PCI
60–61h
0000h
RO
16 bits
Description
Reserved
Datasheet
Integrated Graphics Device Registers (D2:F0,F1)
8.2.24
GDRST—Mirror of Dev2 Func0 Graphics Reset
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/2/1/PCI
C0h
00h
RO
8 bits
This register is a mirror of the Graphics Reset Register in Device 2.
Bit
Access &
Default
7:2
RO
0h
1
Description
Reserved
Graphics Reset Status (GRS):
RO
0b
0 = Graphics subsystem not in Reset.
1 = Graphics Subsystem in Reset as a result of Graphics Reset.
0
Graphics Reset (GDR):
RO
0b
0 = De-assert display and render domain reset
1 = Assert display and render domain reset
8.2.25
PMCAPID—Mirror of Fun 0 Power Management
Capabilities ID
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/2/1/PCI
D0–D1h
0001h
RO
16 bits
This register is a mirror of function 0 with the same R/W attributes. The hardware
implements a single physical register common to both functions 0 and 1.
Datasheet
Bit
Access &
Default
Description
15:8
RO
00h
Next Capability Pointer (NEXT_PTR): This contains a pointer to
next item in capabilities list. This is the final capability in the list and
must be set to 00h.
7:0
RO
01h
Capability Identifier (CAP_ID): SIG defines this ID is 01h for power
management.
263
Integrated Graphics Device Registers (D2:F0,F1)
8.2.26
PMCAP—Mirror of Fun 0 Power Management Capabilities
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/2/1/PCI
D2–D3h
0022h
RO
16 bits
This register is a Mirror of Function 0 with the same read/write attributes. The
hardware implements a single physical register common to both functions 0 and 1.
264
Bit
Access &
Default
Description
15:11
RO
00h
PME Support (PMES): This field indicates the power states in which
the IGD may assert PME#. Hardwired to 0 to indicate that the IGD
does not assert the PME# signal.
10
RO
0b
D2 Support (D2): The D2 power management state is not
supported. This bit is hardwired to 0.
9
RO
0b
D1 Support (D1): Hardwired to 0 to indicate that the D1 power
management state is not supported.
8:6
RO
000b
5
RO
1b
Device Specific Initialization (DSI): Hardwired to 1 to indicate
that special initialization of the IGD is required before generic class
device driver is to use it.
4
RO
0b
Reserved
3
RO
0b
PME Clock (PMECLK): Hardwired to 0 to indicate IGD does not
support PME# generation.
2:0
RO
010b
Reserved
Version (VER): Hardwired to 010b to indicate that there are 4 bytes
of power management registers implemented and that this device
complies with revision 1.1 of the PCI Power Management Interface
Specification.
Datasheet
Integrated Graphics Device Registers (D2:F0,F1)
8.2.27
PMCS—Power Management Control/Status
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/2/1/PCI
D4–D5h
0000h
RO, RW
16 bits
Bit
Access &
Default
Description
15
RO
0b
PME Status (PMESTS): This bit is 0 to indicate that IGD does not
support PME# generation from D3 (cold).
14:13
RO
00b
Data Scale (DSCALE): The IGD does not support data register. This
bit always returns 0 when read, write operations have no effect.
12:9
RO
0h
Data Select (DATASEL): The IGD does not support data register.
This bit always returns 0 when read, write operations have no effect.
8
RO
0b
PME Enable (PME_EN): This bit is 0 to indicate that PME# assertion
from D3 (cold) is disabled.
7:2
RO
00h
Reserved
1:0
RW
00b
Power State (PWRSTAT): This field indicates the current power
state of the IGD and can be used to set the IGD into a new power
state. If software attempts to write an unsupported state to this field,
write operation must complete normally on the bus, but the data is
discarded and no state change occurs. On a transition from D3 to D0
the graphics controller is optionally reset to initial values.
00 = D0 (Default)
01 = D1 (Not Supported)
10 = D2 (Not Supported)
11 = D3
Datasheet
265
Integrated Graphics Device Registers (D2:F0,F1)
8.2.28
SWSMI—Mirror of Func0 Software SMI
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/2/1/PCI
E0–E1h
0000h
RO
16 bits
As long as there is the potential that DVO port legacy drivers exist which expect this
register at this address, D2:F0 address E0h–E1h must be reserved for this register.
Bit
Access &
Default
Description
15:8
RO
00h
Software Scratch Bits (SWSB):
7:1
RO
00h
Software Flag (SWF): This field is used to indicate caller and SMI
function desired, as well as return result.
0
RO
0b
GMCH Software SMI Event (GSSMIE): When Set, this bit will
trigger an SMI. Software must write a 0 to clear this bit.
§
266
Datasheet
Integrated Graphics Device Registers (D2:F0,F1)
Datasheet
267
Manageability Engine (ME) Registers (D3:F0)
9
Manageability Engine (ME)
Registers (D3:F0)
This chapter contains the Manageability Engine registers for Device 3 (D3), Function 0
(0).
9.1
Host Embedded Controller Interface (HECI1)
Configuration Register Details (D3:F0)
Table 9-1. HECI1 Register Address Map (D3:F0)
Address
Offset
268
Symbol
Register Name
Default
Value
Access
00–03h
ID
Identifiers
29848086h
RO
04–05h
CMD
Command
0000h
RO, R/W
06–07h
STS
Device Status
0010h
RO
08h
RID
Revision ID
See register
description
RO
09–0Bh
CC
Class Code
000000h
RO
0Ch
CLS
Cache Line Size
00h
RO
0Dh
MLT
Master Latency Timer
00h
RO
0Eh
HTYPE
Header Type
80h
RO
10–17h
HECI_MBA
R
HECI MMIO Base Address
0000000000
000004h
RO, R/W
2C–2Fh
SS
Sub System Identifiers
00000000h
R/WO
34h
CAP
Capabilities Pointer
50h
RO
3C–3Dh
INTR
Interrupt Information
0100h
RO, R/W
3Eh
MGNT
Minimum Grant
00h
RO
3Fh
MLAT
Maximum Latency
00h
RO
40–43h
HFS
Host Firmware Status
00000000h
RO
50–51h
PID
PCI Power Management Capability
ID
8C01h
RO
52–53h
PC
PCI Power Management Capabilities
C803h
RO
54–55h
PMCS
PCI Power Management Control And
Status
0008h
R/WC,
RO, R/W
8C–8Dh
MID
Message Signaled Interrupt
Identifiers
0005h
RO
8E–8Fh
MC
Message Signaled Interrupt Message
Control
0080h
RO, R/W
Datasheet
Manageability Engine (ME) Registers (D3:F0)
Address
Offset
9.1.1
Symbol
Register Name
Access
90–93h
MA
Message Signaled Interrupt Message
Address
00000000h
R/W, RO
94–97h
MUA
Message Signaled Interrupt Upper
Address (Optional)
00000000h
R/W
98–99h
MD
Message Signaled Interrupt Message
Data
0000h
R/W
A0h
HIDM
HECI Interrupt Delivery Mode
00h
R/W
ID—Identifiers
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
9.1.2
Default
Value
0/3/0/PCI
0–3h
29848086h
RO
32 bits
Bit
Access &
Default
Description
31:16
RO
2984h
Device ID (DID): This register indicates what device number
assigned for the ME subsystem.
15:0
RO
8086h
Vendor ID (VID): This field indicates Intel is the vendor, assigned
by the PCI SIG.
CMD—Command
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Bit
Access &
Default
15:11
RO
00000b
10
R/W
0b
0/3/0/PCI
4–5h
0000h
RO, R/W
16 bits
Description
Reserved
Interrupt Disable (ID): This bit disables this device from
generating PCI line based interrupts. This bit does not have any
effect on MSI operation.
0 = Enable
1 = Disable
Datasheet
9
RO
0b
Fast Back-to-Back Enable (FBE): Not implemented, hardwired to
0.
8
RO
0b
SERR# Enable (SEE): Not implemented, hardwired to 0.
269
Manageability Engine (ME) Registers (D3:F0)
Bit
Access &
Default
Description
7
RO
0b
Wait Cycle Enable (WCC): Not implemented, hardwired to 0.
6
RO
0b
Parity Error Response Enable (PEE): Not implemented, hardwired
to 0.
5
RO
0b
VGA Palette Snooping Enable (VGA): Not implemented,
hardwired to 0.
4
RO
0b
Memory Write and Invalidate Enable (MWIE): Not implemented,
hardwired to 0.
3
RO
0b
Special Cycle Enable (SCE): Not implemented, hardwired to 0.
2
R/W
0b
Bus Master Enable (BME): This bit controls the HECI host
controller's ability to act as a system memory master for data
transfers.
0 = Disable. HECI is blocked from generating MSI to the host
processor.
1 = Enable
When this bit is cleared, HECI bus master activity stops and any
active DMA engines return to an idle condition. This bit is made
visible to firmware through the H_PCI_CSR register, and changes to
this bit may be configured by the H_PCI_CSR register to generate an
ME MSI.
Note that this bit does not block HECI accesses to ME-UMA (i.e.,
writes or reads to the host and ME circular buffers through the read
window and write window registers still cause ME backbone
transactions to ME-UMA).
1
R/W
0b
Memory Space Enable (MSE): This bit controls access to the HECI
host controller’s memory mapped register space.
0 = Disable
1 = Enable
0
270
RO
0b
I/O Space Enable (IOSE): Not implemented, hardwired to 0.
Datasheet
Manageability Engine (ME) Registers (D3:F0)
9.1.3
STS—Device Status
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Bit
Datasheet
0/3/0/PCI
6–7h
0010h
RO
16 bits
Access &
Default
Description
15
RO
0b
Detected Parity Error (DPE): Not implemented, hardwired to 0.
14
RO
0b
Signaled System Error (SSE): Not implemented, hardwired to 0.
13
RO
0b
Received Master-Abort (RMA): Not implemented, hardwired to 0.
12
RO
0b
Received Target Abort (RTA): Not implemented, hardwired to 0.
11
RO
0b
Signaled Target-Abort (STA): Not implemented, hardwired to 0.
10:9
RO
00b
DEVSEL# Timing (DEVT): These bits are hardwired to 00.
8
RO
0b
Master Data Parity Error Detected (DPD): Not implemented,
hardwired to 0.
7
RO
0b
Fast Back-to-Back Capable (FBC): Not implemented, hardwired to
0.
6
RO
0b
Reserved
5
RO
0b
66 MHz Capable (C66): Not implemented, hardwired to 0.
4
RO
1b
Capabilities List (CL): Indicates the presence of a capabilities list,
hardwired to 1.
3
RO
0b
Interrupt Status (IS): Indicates the interrupt status of the device
(1 = asserted).
2:0
RO
000b
Reserved
271
Manageability Engine (ME) Registers (D3:F0)
9.1.4
RID—Revision ID
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
9.1.5
Bit
Access &
Default
7:0
RO
see
description
0/3/0/PCI
8h
see description below
RO
8 bits
Description
Revision ID (RID): This field indicates stepping of the HECI host
controller. Refer to the Intel® G35 Express Chipset Specification
Update for the value of the Revision ID register.
CC—Class Code
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
9.1.6
Bit
Access &
Default
23:16
RO
00h
Base Class Code (BCC): This field indicates the base class code of
the HECI host controller device.
15:8
RO
00h
Sub Class Code (SCC): This field indicates the sub class code of the
HECI host controller device.
7:0
RO
00h
Programming Interface (PI): This field indicates the programming
interface of the HECI host controller device.
Description
CLS—Cache Line Size
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
272
0/3/0/PCI
9–Bh
000000h
RO
24 bits
Bit
Access &
Default
7:0
RO
00h
0/3/0/PCI
Ch
00h
RO
8 bits
Description
Cache Line Size (CLS): Not implemented, hardwired to 0.
Datasheet
Manageability Engine (ME) Registers (D3:F0)
9.1.7
MLT—Master Latency Timer
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
9.1.8
Bit
Access &
Default
7:0
RO
00h
Description
Master Latency Timer (MLT): Not implemented, hardwired to 0.
HTYPE—Header Type
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Datasheet
0/3/0/PCI
Dh
00h
RO
8 bits
Bit
Access &
Default
7
RO
1b
6:0
RO
0000000b
0/3/0/PCI
Eh
80h
RO
8 bits
Description
Multi-Function Device (MFD): This bit indicates the HECI host
controller is part of a multi-function device.
Header Layout (HL): This field indicates that the HECI host
controller uses a target device layout.
273
Manageability Engine (ME) Registers (D3:F0)
9.1.9
HECI_MBAR—HECI MMIO Base Address
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/0/PCI
10–17h
0000000000000004h
RO, R/W
64 bits
This register allocates space for the HECI memory-mapped registers defined in Section
Error! Reference source not found..
9.1.10
Bit
Access &
Default
63:4
R/W
00000000
0000000h
3
RO
0b
Prefetchable (PF): This bit indicates that this range is not prefetchable
2:1
RO
10b
Type (TP): This field indicates that this range can be mapped
anywhere in 64-bit address space. Note that the (G)MCH only uses
bits 35:4 of the base address field as the (G)MCH only decodes FSB
address bits 35:4.
0
RO
0b
Resource Type Indicator (RTE): This bit indicates a request for
register memory space.
Base Address (BA): This field provides the base address of register
memory space.
SS—Sub System Identifiers
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
274
Description
0/3/0/PCI
2C–2Fh
00000000h
R/WO
32 bits
Bit
Access &
Default
Description
31:16
R/WO
0000h
Subsystem ID (SSID): This field indicates the sub-system
identifier. This field should be programmed by BIOS during boot-up.
Once written, this register becomes Read Only. This field can only be
cleared by PLTRST#.
15:0
R/WO
0000h
Subsystem Vendor ID (SSVID): This field indicates the subsystem vendor identifier. This field should be programmed by BIOS
during boot-up. Once written, this register becomes Read Only. This
field can only be cleared by PLTRST#.
Datasheet
Manageability Engine (ME) Registers (D3:F0)
9.1.11
CAP—Capabilities Pointer
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
9.1.12
0/3/0/PCI
34h
50h
RO
8 bits
Bit
Access &
Default
Description
7:0
RO
50h
Capability Pointer (CP): This field indicates the first capability
pointer offset. It points to the PCI power management capability offset.
INTR—Interrupt Information
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Bit
Access &
Default
15:8
RO
01h
0/3/0/PCI
3C–3Dh
0100h
RO, R/W
16 bits
Description
Interrupt Pin (IPIN): This field indicates the interrupt pin the HECI
host controller uses. The value of 01h selects INTA# interrupt pin.
Note: As HECI is an internal device in the GMCH, the INTA# pin is
implemented as an INTA# message to the ICH8.
7:0
9.1.13
R/W
00h
MGNT—Minimum Grant
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Datasheet
Interrupt Line (ILINE): Software written value to indicate which
interrupt line (vector) the interrupt is connected to. No hardware
action is taken on this register.
Bit
Access &
Default
7:0
RO
00h
0/3/0/PCI
3Eh
00h
RO
8 bits
Description
Grant (GNT): Not implemented, hardwired to 0.
275
Manageability Engine (ME) Registers (D3:F0)
9.1.14
MLAT—Maximum Latency
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
9.1.15
Bit
Access &
Default
7:0
RO
00h
Latency (LAT): Not implemented, hardwired to 0.
0/3/0/PCI
40–43h
00000000h
RO
32 bits
Bit
Access &
Default
Description
31:0
RO
00000000h
Firmware Status Host Access (FS_HA): This field indicates current
status of the firmware for the HECI controller.
PID—PCI Power Management Capability ID
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
276
Description
HFS—Host Firmware Status
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
9.1.16
0/3/0/PCI
3Fh
00h
RO
8 bits
0/3/0/PCI
50–51h
8C01h
RO
16 bits
Bit
Access &
Default
Description
15:8
RO
8Ch
Next Capability (NEXT): This field indicates the location of the next
capability item in the list. This is the Message Signaled Interrupts
capability.
7:0
RO
01h
Cap ID (CID): This field indicates that this pointer is a PCI power
management.
Datasheet
Manageability Engine (ME) Registers (D3:F0)
9.1.17
PC—PCI Power Management Capabilities
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Bit
Access &
Default
15:11
RO
11001b
0/3/0/PCI
52–53h
C803h
RO
16 bits
Description
PME_Support (PSUP): This field indicates the states that can
generate PME#.
HECI can assert PME# from any D-state except D1 or D2 which are
not supported by HECI.
Datasheet
10
RO
0b
D2_Support (D2S): The D2 state is not supported for the HECI host
controller.
9
RO
0b
D1_Support (D1S): The D1 state is not supported for the HECI host
controller.
8:6
RO
000b
5
RO
0b
Device Specific Initialization (DSI): This bit indicates whether
device-specific initialization is required.
4
RO
0b
Reserved
3
RO
0b
PME Clock (PMEC): This bit indicates that PCI clock is not required
to generate PME#.
2:0
RO
011b
Version (VS): This bit indicates support for Revision 1.2 of the PCI
Power Management Specification.
Aux_Current (AUXC): Reports the maximum Suspend well current
required when in the D3COLD state.
277
Manageability Engine (ME) Registers (D3:F0)
9.1.18
PMCS—PCI Power Management Control And Status
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Bit
Access &
Default
15
R/WC
0b
0/3/0/PCI
54–55h
0008h
R/WC, RO, R/W
16 bits
Description
PME Status (PMES): The PME Status bit in HECI space can be set to
1 by FW performing a write into AUX register to set PMES.
This bit is cleared by host processor writing a 1 to it.
FW cannot clear this bit.
Host processor writes with value 0 have no effect on this bit.
This bit is reset to 0 by MRST#
14:9
RO
000000b
8
R/W
0b
Reserved
PME Enable (PMEE): This read/write bit is controlled by host SW. It
does not directly have an effect on PME events. This bit is reset to 0 by
MRST#.
0 = Disable
1 = Enable
7:4
RO
0000b
3
RO
1b
Reserved
No_Soft_Reset (NSR): This bit indicates that when the HECI host
controller is transitioning from D3hot to D0 due to power state
command; it does not perform an internal reset.
0 = No soft reset
1 = Soft reset
2
RO
0b
1:0
R/W
00b
Reserved
Power State (PS): This field is used both to determine the current
power state of the HECI host controller and to set a new power state.
The values are:
00 = D0 state
11 = D3HOT state
278
Datasheet
Manageability Engine (ME) Registers (D3:F0)
9.1.19
MID—Message Signaled Interrupt Identifiers
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
9.1.20
0/3/0/PCI
8C–8Dh
0005h
RO
16 bits
Bit
Access &
Default
Description
15:8
RO
00h
Next Pointer (NEXT): This field indicates the next item in the list. This
can be other capability pointers (such as PCI-Express) or it can be the
last item in the list.
7:0
RO
05h
Capability ID (CID): Capabilities ID indicates MSI.
MC—Message Signaled Interrupt Message Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/0/PCI
8E–8Fh
0080h
RO, R/W
16 bits
Bit
Access &
Default
Description
15:8
RO
00h
Reserved
7
RO
1b
64 Bit Address Capable (C64): This bit indicates whether capable of
generating 64-bit messages.
6:4
RO
000b
Multiple Message Enable (MME): Not implemented, hardwired to 0.
3:1
RO
000b
Multiple Message Capable (MMC): Not implemented, hardwired to
0.
0
R/W
0b
MSI Enable (MSIE): If set, MSI is enabled and traditional interrupt
pins are not used to generate interrupts.
0 = Disable
1 = Enable
Datasheet
279
Manageability Engine (ME) Registers (D3:F0)
9.1.21
MA—Message Signaled Interrupt Message Address
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
9.1.22
Bit
Access &
Default
31:2
R/W
00000000h
1:0
RO
00b
Description
Address (ADDR): This field indicates the lower 32 bits of the system
specified message address; always DW aligned.
Reserved
MD—Message Signaled Interrupt Message Data
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
280
0/3/0/PCI
90–93h
00000000h
R/W, RO
32 bits
Bit
Access &
Default
15:0
R/W
0000h
0/3/0/PCI
98–99h
0000h
R/W
16 bits
Description
Data (Data): This 16-bit field is programmed by system software if
MSI is enabled. Its content is driven onto the FSB during the data
phase of the MSI memory write transaction.
Datasheet
Manageability Engine (ME) Registers (D3:F0)
9.1.23
HIDM—HECI Interrupt Delivery Mode
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
BIOS Optimal Default
0/3/0/PCI
A0h
00h
R/W
8 bits
00h
This register is used to select interrupt delivery mechanism for HECI to Host processor
interrupts.
Bit
Access &
Default
7:2
RO
0h
1:0
R/W
00b
Description
Reserved
HECI Interrupt Delivery Mode (HIDM): These bits control what
type of interrupt the HECI will send.:
00
01
10
11
Datasheet
=
=
=
=
Generate Legacy or MSI interrupt
Generate SCI
Generate SMI
Reserved
281
Functional Description
10
Functional Description
This chapter provides a functional description of the major interfaces and capabilities
of the GMCH.
10.1
Host Interface
The GMCH supports the Core® 2 Duo processor subset of the Enhanced Mode
Scaleable Bus. The cache line size is 64 bytes. Source synchronous transfer is used for
the address and data signals. The address signals are double pumped, and a new
address can be generated every other bus clock. At 200/266/333MHz bus clock, the
address signals run at 400/533/667 MT/s. The data is quad pumped, and an entire
64B cache line can be transferred in two bus clocks. At 200/266/333 MHz bus clock,
the data signals run at 800/1066/1333 MT/s for a maximum bandwidth of
6.4/8.5/10.7 GB/s.
10.1.1
FSB IOQ Depth
The Scalable Bus supports up to 12 simultaneous outstanding transactions.
10.1.2
FSB OOQ Depth
The GMCH supports only one outstanding deferred transaction on the FSB.
10.1.3
FSB GTL+ Termination
The GMCH integrates GTL+ termination resistors on die. Also, approximately
2.8 pF(fast) – 3.3 pF(slow) per pad of on die capacitance will be implemented to
provide better FSB electrical performance.
282
Datasheet
Functional Description
10.1.4
FSB Dynamic Bus Inversion
The GMCH supports Dynamic Bus Inversion (DBI) when driving and when receiving
data from the processor. DBI limits the number of data signals that are driven to a low
voltage on each quad pumped data phase. This decreases the worst-case power
consumption of the GMCH. HDINV[3:0]# indicate if the corresponding 16 bits of data
are inverted on the bus for each quad pumped data phase:
HDINV[3:0]#
Data Bits
HDINV0#
HD[15:0]#
HDINV1#
HD[31:16]#
HDINV2#
HD[47:32]#
HDINV3#
HD[63:48]#
Whenever the processor or the GMCH drives data, each 16-bit segment is analyzed. If
more than 8 of the 16 signals would normally be driven low on the bus, the
corresponding HDINV# signal will be asserted, and the data will be inverted prior to
being driven on the bus. Whenever the processor or the GMCH receives data, it
monitors HDINV[3:0]# to determine if the corresponding data segment should be
inverted.
10.1.5
APIC Cluster Mode Support
APIC Cluster mode support is required for backwards compatibility with existing
software, including various operating systems. As one example, beginning with
Microsoft Windows 2000, there is a mode (boot.ini) that allows an end user to enable
the use of cluster addressing support of the APIC.
•
⎯
⎯
⎯
Datasheet
The GMCH supports three types of interrupt re-direction:
Physical
Flat-Logical
Clustered-Logical
283
Functional Description
10.2
System Memory Controller
This section describes the GMCH memory controller interface.
10.2.1
Memory Organization Modes
The system memory controller supports two styles of memory organization
(Interleaved and Asymmetric). Rules for populating DIMM slots are included in this
section.
Table 10-1. Sample System Memory Organization with Interleaved Channels
Channel A
population
Cumulative
top address
in Channel A
Channel B
population
Cumulative
top address
in Channel B
Rank 3
0 MB
2560 MB
0 MB
2560 MB
Rank 2
256 MB
2560 MB
256 MB
2560 MB
Rank 1
512 MB
2048 MB
512 MB
2048 MB
Rank 0
512 MB
1024 MB
512 MB
1024 MB
Table 10-2. Sample System Memory Organization with Asymmetric Channels
Channel A
population
Cumulative
top address
in Channel A
Channel B
population
Cumulative
top address
in Channel B
Rank 3
0 MB
1280 MB
0 MB
2560 MB
Rank 2
256 MB
1280 MB
256 MB
2560 MB
Rank 1
512 MB
1024 MB
512 MB
2304 MB
Rank 0
512 MB
512 MB
512 MB
1792 MB
Interleaved Mode
This mode provides maximum performance on real applications. Addresses are pingponged between the channels, and the switch happens after each cache line (64 byte
boundary). If two consecutive cache lines are requested, both may be retrieved
simultaneously, since they are guaranteed to be on opposite channels. The drawbacks
of Interleaved Mode are that the system designer must populate both channels of
memory such that they have equal capacity, but the technology and device width may
vary from one channel to the other.
Asymmetric Mode
This mode trades performance for system design flexibility. Unlike the previous mode,
addresses start in channel A and stay there until the end of the highest rank in
channel A, then addresses continue from the bottom of channel B to the top. Real
world applications are unlikely to make requests that alternate between addresses
that sit on opposite channels with this memory organization, so in most cases,
bandwidth will be limited to that of a single channel. The system designer is free to
284
Datasheet
Functional Description
populate or not to populate any rank on either channel, including either degenerate
single channel case.
Flex Mode
This mode provides the best performance flexibility. The lowest DRAM memory is
mapped to two channel operation and the top most , if any, DRAM memory is mapped
to single channel operation. The drawbacks of Flex mode are that the system designer
must populate both channels of memory to get the benefits of flex mode, and there
will be multiple zones of Dual/single channel operation across the entire of DRAM
memory.
Figure 10-1. System Memory Styles
Datasheet
285
Functional Description
10.2.2
DRAM Technologies and Organization
"Single sided" below is a logical term referring to the number of Chip Selects attached
to the DIMM. A physical DIMM may have the components on both sides of the
substrate, but be logically indistinguishable from a single sided DIMM with all devices
on one side if all components on the DIMM are attached to the same chip select
signal.
x8
means that each component has 8 data lines.
x16
means that each component has 16 data lines.
All standard 256-Mb, 512-Mb, and 1-Gb technologies and addressing are supported for
x16 and x8 devices.
For DDR2
533 (PC2 4300)
Non-ECC
Version A = Single sided x8
Version B = Double sided x8
Version C = Single sided x16
667 (PC2 5300)
Non-ECC
Version C = Single sided x16
Version D = Single sided x8
Version E = Double sided x8
800 (PC2 6400)
Non-ECC
Version C = Single sided x16
Version D = Single sided x8
Version E = Double sided x8
No support for DIMMs with different technologies or capacities on opposite sides of the
same DIMM. If one side of a DIMM is populated, the other side is either identical or
empty.
Supported components include:
For DDR2 at 533 (PC2 4300) and 667 (PC2 5300)
256-Mb technology
32-M cells x8 data bits/cell
1-K columns
4 banks
8-K rows
Each component has a 1-KB page.
One DIMM has 8 components resulting in an 8-KB page.
The capacity of one rank is 256 MB.
16-M cells x16 data bits/cell
512 columns
4 banks
8-K rows
Each component has a 1-KB page.
One DIMM has 4 components resulting in a 4-KB page.
The capacity of one rank is 128 MB.
286
Datasheet
Functional Description
512-Mb technology
64-M cells x8 data bits/cell
1K columns
4 banks
16K rows
Each component has a 1-KB page.
One DIMM has 8 components resulting
The capacity of one rank is 512 MB.
32-M cells x16 data bits/cell
1-K columns
4 banks
8-K rows
Each component has a 2-KB page.
One DIMM has 4 components resulting
The capacity of one rank is 256 MB.
1-Gb technology
128-M cells x8 data bits/cell
1-K columns
8 banks
16-K rows
Each component has a 1-KB page.
One DIMM has 8 components resulting
The capacity of one rank is 1 GB.
64-M cells x16 data bits/cell
1-K columns
8 banks
8-K rows
Each component has a 2-KB page.
One DIMM has 4 components resulting
The capacity of one rank is 512MB.
in an 8-KB page.
in an 8-KB page.
in an 8-KB page.
in an 8-KB page.
The DRAM sub-system supports single or dual channels, 64b wide per channel. A
maximum of 4 ranks can be populated (2 Double Sided DIMMs) per channel. Mixed
mode DDR DS-DIMMs (x8 and x16 on the same DIMM) are not supported (not
validated).
By using 1Gb technology, the largest memory capacity is 8 GB (16K rows * 1K
columns * 1 cell/(row * column) * 8 b/cell * 8 banks/device * 8 devices/rank * 4
ranks/channel * 2 channel *1M/(K*K) * 1G/1024M * 1B/8b = 8 GB). Utilizing 8GB of
memory is only possible in Interleaved mode with all ranks populated at maximum
capacity.
By using 256Mb technology, the smallest memory capacity is 128 MB (8K rows * 512
columns * 1 cell/(row * column) * 16b/cell * 4 banks/device * 4 devices/rank * 1
rank * 1M/1024K * 1B/8b = 128 MB).
Datasheet
287
Functional Description
10.2.2.1
10.2.2.2
Rules for Populating DIMM Slots
•
In all modes, the frequency of System Memory will be the lowest frequency of all
of the DIMMs in the system, as determined through the SPD registers on the
DIMMs.
•
In Single Channel mode, any DIMM slot within the channel may be populated in
any order. Either channel may be used. To save power, do not populate the
unused channel.
•
In Dual Channel Asymmetric mode, any DIMM slot may be populated in any order.
•
In Dual Channel Interleaved mode, any DIMM slot may be populated in any order,
but the total memory in each channel must be the same.
•
In Flex memory mode, any DIMM slot may be populated in any order per channel,
but each channel must have at least 1 DIMM. The matching amount of memory
per channel will be run in Dual channel interleaved mode and the remaining
unmatched memory will run in Asymmetric mode.
System Memory Supported Configurations
The GMCH supports the 256Mbit, 512Mbit, and 1Gbit technology-based DIMMs shown
in Table 10-3.
Table 10-3. DDR2 DIMM Supported Configurations
10.2.3
Technology
Configuration
# of Row
Address
Bits
# of
Column
Address
Bits
# of Bank
Address
Bits
Page
Size
Rank
Size
256Mbit
16M X 16
13
9
2
4K
128 MB
256Mbit
32M X 8
13
10
2
8K
256 MB
512Mbit
32M X 16
13
10
2
8K
256 MB
512Mbit
64M X 8
14
10
2
8K
512 MB
1Gbit
64M X 16
13
10
3
8K
512 MB
1Gbit
128M X 8
14
10
3
8K
1 GB
Main Memory DRAM Address Translation and Decoding
The following tables specify the host interface to memory interface address multiplex
for the GMCH. Refer to the details of the various DIMM configurations as described in
Table 10-3.
288
Datasheet
Functional Description
Table 10-4. DRAM Address Translation (Single Channel/Dual Asymmetric Mode)
Datasheet
Technology (Mb)
Row bits
Column bits
bank bits
width (b)
Rows
Columns
Banks
Page Size (KB)
Devices per rank
Rank Size (MB)
Depth (M)
Addr bits [n:0]
available in DDR2
Host Address bit
32
256
13
10
2
8
8192
1024
4
8
8
256
32
27
yes
256
13
9
2
16
8192
512
4
4
4
128
16
26
yes
512
512
1024
14
13
14
10
10
10
2
2
3
8
16
8
16384
8192
16384
1024
1024
1024
4
4
8
8
8
8
8
4
8
512
256
1024
64
32
128
28
27
29
yes
yes
yes
Memory Address bit
-
1024
13
10
3
16
8192
1024
8
8
4
512
64
28
yes
-
-
31
-
-
-
-
-
-
30
-
-
-
-
-
-
29
-
-
-
-
r 13
-
28
-
-
r 13
-
r 11
r 11
27
r 12
-
r 12
r 12
r 12
r 12
26
r 10
r 10
r 10
r 10
r 10
r 10
25
r9
r9
r9
r9
r9
r9
24
r8
r8
r8
r8
r8
r8
23
r7
r7
r7
r7
r7
r7
22
r6
r6
r6
r6
r6
r6
21
r5
r5
r5
r5
r5
r5
20
r4
r4
r4
r4
r4
r4
19
r3
r3
r3
r3
r3
r3
18
r2
r2
r2
r2
r2
r2
17
r1
r1
r1
r1
r1
r1
16
r0
r0
r0
r0
r0
r0
15
r 11
r 11
r 11
r 11
b0
b0
14
b1
r 12
b1
b1
b1
b1
13
b0
b0
b0
b0
b2
b2
12
c9
b1
c9
c9
c9
c9
11
c8
c8
c8
c8
c8
c8
-
10
c7
c7
c7
c7
c7
c7
9
c6
c6
c6
c6
c6
c6
8
c5
c5
c5
c5
c5
c5
7
c4
c4
c4
c4
c4
c4
6
c3
c3
c3
c3
c3
c3
5
c2
c2
c2
c2
c2
c2
4
c1
c1
c1
c1
c1
c1
3
c0
c0
c0
c0
c0
c0
289
Functional Description
Table 10-5. DRAM Address Translation (Dual Channel Symmetric Mode)
290
Technology (Mb)
Row bits
Column bits
bank bits
width (b)
Rows
Columns
Banks
Page Size (KB)
Devices per rank
Rank Size (MB)
Depth (M)
Addr bits [n:0]
available in DDR2
Host Address bit
256
13
10
2
8
8192
1024
4
8
8
256
32
27
yes
256
13
9
2
16
8192
512
4
4
4
128
16
26
yes
512
512
1024
14
13
14
10
10
10
2
2
3
8
16
8
16384
8192
16384
1024
1024
1024
4
4
8
8
8
8
8
4
8
512
256
1024
64
32
128
28
27
29
yes
yes
yes
Memory Address bit
1024
13
10
3
16
8192
1024
8
8
4
512
64
28
yes
32
-
-
-
-
-
-
31
-
-
-
-
-
-
30
-
-
-
-
r 13
-
29
-
-
r 13
-
r 11
r 11
28
r 12
-
r 12
r 12
r 12
r 12
27
r 10
r 10
r 10
r 10
r 10
r 10
26
r9
r9
r9
r9
r9
r9
25
r8
r8
r8
r8
r8
r8
24
r7
r7
r7
r7
r7
r7
23
r6
r6
r6
r6
r6
r6
22
r5
r5
r5
r5
r5
r5
21
r4
r4
r4
r4
r4
r4
20
r3
r3
r3
r3
r3
r3
19
r2
r2
r2
r2
r2
r2
18
r1
r1
r1
r1
r1
r1
17
r0
r0
r0
r0
r0
r0
16
r 11
r 11
r 11
r 11
b0
b0
15
b1
r 12
b1
b1
b1
b1
14
b0
b0
b0
b0
b2
b2
13
c9
b1
c9
c9
c9
c9
12
c8
c8
c8
c8
c8
c8
11
c7
c7
c7
c7
c7
c7
10
c6
c6
c6
c6
c6
c6
9
c5
c5
c5
c5
c5
c5
8
c4
c4
c4
c4
c4
c4
7
c3
c3
c3
c3
c3
c3
6
h
h
h
h
h
h
5
c2
c2
c2
c2
c2
c2
4
c1
c1
c1
c1
c1
c1
3
c0
c0
c0
c0
c0
c0
Datasheet
Functional Description
10.2.4
DRAM Clock Generation
The GMCH generates three differential clock pairs for every supported DIMM. A total of
6 clock pairs are driven directly by the GMCH to 2 DIMMs per channel.
10.2.5
Suspend to RAM and Resume
When entering the Suspend to RAM (STR) state, the SDRAM controller will flush
pending cycles and then enter all SDRAM rows into self refresh. In STR, the CKE
signals remain LOW so the SDRAM devices will perform self-refresh.
10.2.6
DDR2 On-Die Termination
On-die termination (ODT) is a feature that allows a DRAM to turn on/off internal
termination resistance for each DQ, DM, DQS, and DQS# signal for x8 and x16
configurations via the ODT control signals. The ODT feature is designed to improve
signal integrity of the memory channel by allowing the termination resistance for the
DQ, DM, DQS, and DQS# signals to be located inside the DRAM devices themselves
instead of on the motherboard. The GMCH drives out the required ODT signals, based
on memory configuration and which rank is being written to or read from, to the
DRAM devices on a targeted DIMM rank to enable or disable their termination
resistance.
10.3
PCI Express*
See the Section 1.3.4 for list of PCI Express features, and the PCI Express
specification for further details.
This GMCH is part of a PCI Express root complex. This means it connects a host
processor/memory subsystem to a PCI Express hierarchy. The control registers for
this functionality are located in device 1 configuration space and two Root Complex
Register Blocks (RCRBs). The DMI RCRB contains registers for control of the Intel
ICH8 attach ports.
10.3.1
PCI Express* Architecture
The PCI Express architecture is specified in layers. Compatibility with the PCI
addressing model (a load-store architecture with a flat address space) is maintained to
ensure that all existing applications and drivers operate unchanged. The PCI Express
configuration uses standard mechanisms as defined in the PCI Plug-and-Play
specification. The initial speed of 1.25 GHz (250 MHz internally) results in
2.5 Gb/s/direction which provides a 250 MB/s communications channel in each
direction (500 MB/s total) that is close to twice the data rate of classic PCI per lane.
Transaction Layer
The upper layer of the PCI Express architecture is the Transaction Layer. The
Transaction Layer’s primary responsibility is the assembly and disassembly of
Transaction Layer Packets (TLPs). TLPs are used to communicate transactions, such as
read and write, as well as certain types of events. The Transaction Layer also
manages flow control of TLPs.
Datasheet
291
Functional Description
Data Link Layer
The middle layer in the PCI Express stack, the Data Link Layer, serves as an
intermediate stage between the Transaction Layer and the Physical Layer.
Responsibilities of Data Link Layer include link management, error detection, and
error correction.
Physical Layer
The Physical Layer includes all circuitry for interface operation, including driver and
input buffers, parallel-to-serial and serial-to-parallel conversion, PLL(s), and
impedance matching circuitry.
10.3.2
Intel® Serial Digital Video Output (SDVO)
The SDVO description is located here because it is multiplexed onto the PCI Express
x16 port pins. The Intel® SDVO Port is the second generation of digital video output
from compliant Intel® GMCHs. The electrical interface is based on the PCI Express
interface, though the protocol and timings are completely unique. Whereas PCI
Express runs at a fixed frequency, the frequency of the SDVO interface is dependant
upon the active display resolution and timing. The port can be dynamically configured
in several modes to support display configurations.
Essentially, an SDVO port will transmit display data in a high-speed, serial format
across differential AC coupled signals. An SDVO port consists of a sideband differential
clock pair and a number of differential data pairs.
10.3.2.1
Intel® SDVO Capabilities
SDVO ports can support a variety of display types including LVDS, DVI, Analog CRT,
TV-Out and external CE type devices. The GMCH utilizes an external SDVO device to
translate from SDVO protocol and timings to the desired display format and timings.
The Internal Graphics Controller can have one or two SDVO ports multiplexed on the
x16 PCI Express interface. When an external x16 PCI Express graphics accelerator is
not in use, an ADD2 card may be plugged into the x16 connector or if a x16 slot is not
present, the SDVO(s) may be located ‘down’ on the motherboard to access the
multiplexed SDVO ports and provide a variety of digital display options.
The ADD2/Media Expansion card is designed to fit in a x16 PCI Express connector. The
ADD2/Media Expansion card can support one or two devices. If a single channel SDVO
device is utilized, it should be attached to the channel B SDVO pins. The ADD2 card
can support two separate SDVO devices when the interface is in Dual Independent or
Dual Simultaneous Standard modes. The Media Expansion card adds Video in
capabilities.
The SDVO port defines a two-wire point-to-point communication path between the
SDVO device and GMCH. The SDVO Control Clock and Data provide similar
functionality to I2C. However unlike I2C, this interface is intended to be point-to-point
(from the GMCH to the SDVO device) and will require the SDVO device to act as a
switch and direct traffic from the SDVO Control bus to the appropriate receiver.
Additionally, this Control bus will be able to run at faster speeds (up to 1 MHz) than a
traditional I2C interface would.
292
Datasheet
Functional Description
Figure 10-2. SDVO Conceptual Block Diagram
Analog RGB
Monitor
Control Clock
Control Data
TV Clock In
Stall
PCI
Express*
Logic
GMCH
SDVO Port C
Internal
Graphics
SDVO Port B
PCI Express x16 Port Pins
Interrupt
ClockC
RedC / AlphaB
GreenC
3rd Party
SDVO
External
Device(s)
Digital
Display
Device(s)
or TV
BlueC
ClockB
RedB
GreenB
BlueB
SDVO_BlkDia
Intel® SDVO Modes
10.3.2.2
The port can be dynamically configured in several modes:
•
Standard – This mode provides baseline SDVO functionality. It supports Pixel
Rates between 25 MP/s and 270 MP/s. It uses three data pairs to transfer RGB
data.
•
Extended – Adds Alpha support to data stream. This mode supports Pixel Rates
between 25 MP/s and 270 MP/s. The mode uses four data channels and is only
supported on SDVOB. Leverages channel C (SDVOC) Red pair as the Alpha pair for
channel B (SDVOB).
•
Dual Standard – This mode uses Standard data streams across both SDVOB and
SDVOC. Both channels can only run in Standard mode (3 data pairs) and each
channel supports Pixel Rates between 25 MP/s and 270 MP/s.
Dual Independent Standard - In Dual Independent Standard mode, each
SDVO channel sees a different pixel stream. The data stream across SDVOB will
not be the same as the data stream across SDVOC.
Dual Simultaneous Standard - In Dual Simultaneous Standard mode, both
SDVO channels sees the same pixel stream. The data stream across SDVOB will
be the same as the data stream across SDVOC. The display timings are identical,
but the transfer timings may not be (i.e., SDVOB clocks and data may not be
perfectly aligned with SDVOC clock and data as seen at the SDVO device(s)).
Since this mode uses just a single data stream, it uses a single pixel pipeline
within the GMCH.
⎯
⎯
Datasheet
293
Functional Description
10.3.2.3
PCI Express* and Internal Graphics Simultaneous
Operation
10.3.2.3.1 Standard PCI Express* Cards and Internal Graphics
BIOS control of simultaneous operation is needed to ensure the PCI Express is
configured appropriately.
10.3.2.3.2 MEDIA EXPANSION Cards (Concurrent SDVO and PCI Express*)
SDVO lane reversal is supported on the GMCH. This functionality allows current SDVO
ADD2 cards to work in current ATX and BTX systems instead of requiring a separate
card. The GMCH will allow SDVO and PCI Express to operate concurrently on the PCI
Express Port. The card that plugs into the x16 connector in this case is called an Media
Expansion card. It uses 4 or 8 lanes for SDVO and up to 8 lanes of standard PCI
Express.
For the GMCH, the only supported PCI Express width when SDVO is present is x1.
This concurrency is supported in reversed and non-reversed configurations.
Mirroring/Reversing is always about the axis.
Table 10-6. Concurrent sDVO / PCI Express* Configuration Strap Controls
Configuration
#
Description
1
PCI Express* not reversed
2
PCI Express* Reversed
3
sDVO (ADD2) not reversed
4
sDVO (ADD2) Reversed
5
sDVO & PCI Express*
(MEDIA EXPANSION) not
reversed
6
sDVO & PCI Express*
(MEDIA EXPANSION)
Reversed
Slot
Reversed
Strap
sDVO
Present
Strap
sDVO/PCI
Express*
Concurrent
Strap
—
—
—
Yes
—
—
—
Yes
—
Yes
Yes
—
Yes
Yes
Yes
Yes
Yes
NOTES:
1.
The Configuration #s refer to the following figures (no intentional relation to validation
Configurations).
2.
Configurations 4, 5, and 6 (required addition of sDVO/PCI Express* Concurrent Strap).
294
Datasheet
Functional Description
Figure 10-3. Concurrent sDVO / PCI Express* Non-Reversed Configurations
0
0
Not Reversed
x1
PCIe
Card
15
3
x16
PCIe
Card
5
0
x4
sDVO
(ADD2)
Card
x8
sDVO
(ADD2)
Card
15
15
0
15
PCIe Lane 0
PCIe
PCIe Lane N
MEC Card
sDVO Lane 7
sDVO
sDVO Lane 0
0
PCI Express x16 Connector
0
1
PCI Express x16 Connector
GMCH
PEG
Pins
PCI Express x16 Connector
GMCH
PEG
Signals
Video In
Video Out
15
SDVO-Conc-PCIe_Non-Reversed_Config
Figure 10-4. Concurrent sDVO / PCI Express* Reversed Configurations
0
15
x8
sDVO
(ADD2)
Card
x4
sDVO
(ADD2)
Card
0
0
sDVO Lane 0
sDVO
sDVO Lane 7
MEC Card
PCIe Lane N
PCIe
PCIe Lane 0
15
PCI Express x16 Connector
x16
PCIe
Card
15
6
15
x1
PCIe
Card
0
4
PCI Express x16 Connector
0
Reversed
15
2
PCI Express x16 Connector
GMCH GMCH
PEG
PEG
Signals Pins
Video Out
Video In
0
SDVO-Conc-PCIe_Reversed_Config
Datasheet
295
Functional Description
10.4
Integrated Graphics Controller
The GMCH provides a highly integrated graphics accelerator and chipset which allows
for a flexible Integrated System Graphics solution. High bandwidth access to data is
provided through the graphics and system memory ports. The GMCH can access
graphics data located in system memory at up to 12.6GB/s (depending on memory
configuration). The GMCH can drive an integrated DAC, and/or two SDVO ports
(multiplexed with PCI Express) capable of driving an ADD2/Media Expansion card.
External SDVO devices are capable of driving a variety of TV-Out, TMDS, and LVDS
transmitters.
10.4.1
Integrated Graphics Device Overview
With the evolution of PC graphics from fixed function parallelizable pipelines to
generalized programmable parallel engines, the GMCH’s Internal Graphics Device
delivers a highly programmable graphics device capable of rendering 3D, 2D, and
video content.
Graphics workloads like 3D, imaging, and video encode/decode are all good examples
of parallel applications. The programmable graphics architecture in G35 allows for the
ability for the driver to program the graphics device to operate on parallel workloads
in a parallel manor.
10.4.1.1
3D Graphics
The GMCH’s graphics engine supports acceleration for all DX9.0c/DX10 and OGL2.0
required features with additional features. Some of the key features supported are:
•
Vertex Shader Model 4.0 (HW)
•
Hardware Pixel Shader 4.0 (HW)
•
32-bit and 16-bit Full Precision Floating Point Operations
•
Up to 8 Multiple Render Targets (MRTs)
•
Occlusion Query
•
128-bit Floating Point Texture Formats
•
Bilinear, Trilinear, and Anisotropic MipMap Filtering
•
Shadow Maps and Double Sided Stencils
The 3D performance of any graphics device is affected by several key factors: memory
bandwidth, and numbers of pixels per clock. The GMCH graphics addresses all of these
potential bottlenecks by sharing the two channels of memory bandwidth that allows
for up to 12.6 GB/s, and the ability to operate on 4 pixels per clock.
296
Datasheet
Functional Description
10.4.1.2
Video Playback
10.4.1.2.1 Deinterlacing Support
For display on a progressive computer monitor, interlaced data that has been
formatted for display on interlaced monitors (TV) needs to be de-interlaced. The
simple approaches to de-interlacing create unwanted display artifacts. More advanced
de-interlacing techniques have been developed to provide a high-quality, effective
solution. The Motion Adaptive Deinterlacing supported in the GMCH greatly reduces
the feathering artifacts typical with Weave deinterlacing and the jaggies typically
associated to Bob deinterlacing. Clear, sharp text is another benefit on Intel’s Motion
Adaptive Deinterlacing technique.
10.5
Display Interfaces
The GMCH has three display ports, one analog and two digital. Each port can transmit
data according to one or more protocols. The digital ports are connected to an
external device that converts one protocol to another. Examples of this are TV
encoders, external DACs, LVDS transmitters, and TMDS transmitters. Each display
port has control signals that may be used to control, configure and/or determine the
capabilities of an external device.
The GMCH has one dedicated display port, the analog port. SDVO ports B and C are
multiplexed with the PCI Express graphics interface and are not available if an
external PCI Express graphics device is in use. When a system utilizes a PCI Express
graphics connector, SDVO ports B and C can be utilized via an ADD2/Media Expansion
(Advanced Digital Display 2) card. Ports B and C can also operate in dual-channel
mode, where the data bus is connected to both display ports, allowing a single device
to take data at twice the pixel rate.
•
The GMCH’s analog port uses an integrated 400 MHz RAMDAC that can directly
drive a standard progressive scan analog monitor up to a resolution of 2048x1536
pixels with 32-bit color at 75 Hz.
•
The GMCH’s SDVO ports are each capable of driving a 270-MP pixel rate. Each
port is capable of driving a digital display up to 1600x1200 @ 60 Hz. When in
dual-channel mode, the GMCH can drive a flat panel up to 2048x1536 @ 75 Hz or
dCRT/HDTV up to 1920x1080 @ 85 Hz.
The GMCH is compliant with DVI Specification 1.0. When combined with a DVI
compliant external device and connector, the GMCH has a high speed interface to a
digital display (e.g., flat panel or digital CRT).
Datasheet
297
Functional Description
Table 10-7. Display Port Characteristics
SIGNALS
Interface Protocol
Analog
Digital Port B
Digital Port C
RGB DAC
DVO 1.0
DVO 1.0
HSYNC
Yes Enable/Polarity
VSYNC
Yes Enable/Polarity
BLANK
No
Yes(1)
Yes(1)
STALL
No
Yes
Yes
Field
No
Yes
Yes
Display_Enable
No
—
No
Image Aspect Ratio
Programmable and typically 1.33:1 or 1.78:1
Pixel Aspect Ratio
Square(1)
—
—
Voltage
RGB 0.7 V p-p
PCI Express*
PCI Express
Clock
NA
Max Rate
400 Mpixel
Format
Analog RGB
RGB 8:8:8 YUV 4:4:4
Control Bus
DDC1/DDC2B
DDC2B
External Device
No
TMDS/LVDS Transmitter /TV Encoder
Connector
VGA/DVI-I
DVI/CVBS/SVideo/Component/SCART/HDMI
Differential
270 Mpixel
270 Mpixel
NOTES:
1.
Single signal software selectable between display enable and Blank#
298
Datasheet
Functional Description
10.5.1
Analog Display Port Characteristics
The analog display port provides a RGB signal output along with a HSYNC and VSYNC
signal. There is an associated DDC signal pair that is implemented using GPIO pins
dedicated to the analog port. The intended target device is for a CRT based monitor
with a VGA connector. Display devices such as LCD panels with analog inputs may
work satisfactory but no functionality has been added to the signals to enhance that
capability.
Table 10-8. Analog Port Characteristics
Signal
Port Characteristic
Support
Voltage Range
0.7 V p-p only
Monitor Sense
Analog Compare
Analog Copy Protection
No
Sync on Green
No
Voltage
2.5 V
Enable/Disable
Port control
HSYNC
Polarity adjust
VGA or port control
VSYNC
Composite Sync Support
No
Special Flat Panel Sync
No
Stereo Sync
No
Voltage
Externally buffered to 5 V
Control
Through GPIO interface
RGB
DDC
10.5.1.1
Integrated RAMDAC
The display function contains a RAM-based Digital-to-Analog Converter (RAMDAC) that
transforms the digital data from the graphics and video subsystems to analog data for
the CRT monitor. GMCH’s integrated 400 MHz RAMDAC supports resolutions up to
2048 x 1536 @ 75 Hz. Three 8-bit DACs provide the R, G, and B signals to the
monitor.
10.5.1.2
Sync Signals
HSYNC and VSYNC signals are digital and conform to TTL signal levels at the
connector. Since these levels cannot be generated internal to the device, external
level shifting buffers are required. These signals can be polarity adjusted and
individually disabled in one of the two possible states. The sync signals should power
up disabled in the high state. No composite sync or special flat panel sync support will
be included.
Datasheet
299
Functional Description
10.5.1.3
VESA/VGA Mode
VESA/VGA mode provides compatibility for pre-existing software that set the display
mode using the VGA CRTC registers. Timings are generated based on the VGA register
values and the timing generator registers are not used.
10.5.1.4
DDC (Display Data Channel)
DDC is a standard defined by VESA. Its purpose is to allow communication between
the host system and display. Both configuration and control information can be
exchanged allowing plug- and-play systems to be realized. Support for DDC 1 and 2 is
implemented. The GMCH uses the DDC_CLK and DDC_DATA signals to communicate
with the analog monitor. The GMCH generates these signals at 2.5 V. External pull-up
resistors and level shifting circuitry should be implemented on the board.
The GMCH implements a hardware GMBus controller that can be used to control these
signals allowing for transactions speeds up to 400 kHz.
10.5.2
Digital Display Interface
The GMCH has several options for driving digital displays. The GMCH contains two
SDVO ports that are multiplexed on the PCI Express* Graphics interface. When an
external PCI Express* Graphics accelerator is not present, the GMCH can use the
multiplexed SDVO ports to provide extra digital display options. These additional
digital display capabilities may be provided through an ADD2 card, which is designed
to plug in to a PCI Express connector.
10.5.2.1
Multiplexed Digital Display Channels – Intel® SDVOB and
Intel® SDVOC
The GMCH has the capability to support digital display devices through two SDVO
ports multiplexed with the PCI Express* Graphics signals. When an external graphics
accelerator is used via the PCI Express* Graphics port, these SDVO ports are not
available.
The shared SDVO ports each support a pixel clock up to 270 MHz and can support a
variety of transmission devices.
SDVOCTRLDATA is an open-drain signal that will act as a strap during reset to tell the
GMCH whether the interface is a PCI Express interface or an SDVO interface. When
implementing SDVO, either via ADD2 cards or with a down device, a pull-up is placed
on this line to signal to the GMCH to run in SDVO mode and for proper GMBus
operation.
10.5.2.1.1 ADD2/MEDIA EXPANSION Card
When an Intel G35 Express Chipset platform uses a PCI Express* graphics connector,
the multiplexed SDVO ports may be used via an ADD2/Media Expansion card. The
ADD2/Media Expansion card will be designed to fit a standard PCI Express (x16)
connector. Refer to the latest ADD2/Media Expansion EDS and ADD2/Media Expansion
card design kits for more details on ADD2/Media Expansion.
300
Datasheet
Functional Description
10.5.2.1.2 TMDS Capabilities
The GMCH is compliant with DVI Specification 1.0. When combined with a DVI
compliant external device and connector, the GMCH has a high speed interface to a
digital display (e.g., flat panel or digital CRT). When combining the two multiplexed
SDVO ports, the GMCH can drive a flat panel up to 2048x1536 or a dCRT/HDTV up to
1920x1080. Flat Panel is a fixed resolution display. The GMCH supports panel fitting in
the transmitter, receiver or an external device, but has no native panel fitting
capabilities. The GMCH will however, provide unscaled mode where the display is
centered on the panel.
10.5.2.1.3 LVDS Capabilities
The GMCH may use the multiplexed SDVO ports to drive an LVDS transmitter. Flat
Panel is a fixed resolution display. The GMCH supports panel fitting in the transmitter,
receiver or an external device, as well as using a built in 3x3 panel scalar for a single
SDVO port.
10.5.2.1.4 TV-Out Capabilities
Although traditional TVs are not digital displays, the GMCH uses a digital display
channel to communicate with a TV-Out transmitter. For that reason, the GMCH
considers a TV-Output to be a digital display. The GMCH supports NTSC/PAL/SECAM
standard definition formats. The GMCH generates the proper timing for the external
encoder. The external encoder is responsible for generation of the proper format
signal. Since the multiplexed SDVO interface is a NTSC/PAL/SECAM display on the TVout port can be configured to be the boot device. It is necessary to ensure that
appropriate BIOS support is provided. If EasyLink is supported in the GMCH, then this
mechanism could be used to interrogate the display device.
The TV-out interface on GMCH is addressable as a master device. This allows an
external TV encoder device to drive a pixel clock signal on SDVO_TVClk[+/-] that the
GMCH uses as a reference frequency. The frequency of this clock is dependent on the
output resolution required.
Flicker Filter and Overscan Compensation
The overscan compensation scaling and the flicker filter is done in the external TV
encoder chip. Care must be taken to allow for support of TV sets with high
performance de-interlacers and progressive scan displays connected to by way of a
non-interlaced signal. Timing will be generated with pixel granularity to allow more
overscan ratios to be supported.
Direct YUV from Overlay
When source material is in the YUV format and is destined for a device that can take
YUV format data in, it is desired to send the data without converting it to RGB. This
avoids the truncation errors associated with multiple color conversion steps. The
common situation will be that the overlay source data is in the YUV format and will
bypass the conversion to RBG as it is sent to the TV port directly.
Datasheet
301
Functional Description
Sync Lock Support
Sync lock to the TV will be done using the external encoders PLL combined with the
display phase detector mechanism. The availability of this feature will be determined
which external encoder is in use.
Analog Content Protection
Analog content protection will be provided through the external encoder using
Macrovision 7.01. DVD software must verify the presence of a Macrovision TV encoder
before playback continues. Simple attempts to disable the Macrovision operation must
be detected.
Connectors
Target TV connectors support includes the CVBS, S-Video, Component, and SCART
connectors. The external TV encoder in use will determine the method of support.
10.5.2.1.5 Control Bus
Communication to SDVO registers and if used, ADD2 PROMs and monitor DDCs, are
accomplished by using the SDVOCTRLDATA and SDVOCTRLCLK signals through the
SDVO device. These signals run up to 1 MHz and connect directly to the SDVO device.
The SDVO device is then responsible for routing the DDC and PROM data streams to
the appropriate location. Consult SDVO device data sheets for level shifting
requirements of these signals.
Intel® SDVO Modes
The port can be dynamically configured in several modes:
•
Standard – Baseline SDVO functionality. This mode supports Pixel Rates between
25 and 270 MP/s. The mode uses three data pairs to transfer RGB data.
•
Extended – Adds Alpha support to data stream. This mode supports Pixel Rates
between 25 MP/s and 270 MP/s. The mode uses four data channels and is only
supported on SDVOB. Leverages channel C (SDVOC) Red pair as the Alpha pair for
channel B (SDVOB).
•
Dual Standard – This mode uses Standard data streams across both SDVOB and
SDVOC. Both channels can only run in Standard mode (3 data pairs) and each
channel supports Pixel Rates between 25 270 MP/s and 270 MP/s.
⎯
Dual Independent Standard - In Dual Independent Standard mode, each
SDVO channel will see a different pixel stream. The data stream across SDVOB
will not be the same as the data stream across SDVOC.
⎯
Dual Simultaneous Standard - In Dual Simultaneous Standard mode, both
SDVO channels will see the same pixel stream. The data stream across SDVOB will
be the same as the data stream across SDVOC. The display timings are identical,
but the transfer timings may not be (i.e., SDVOB clocks and data may not be
perfectly aligned with SDVOC clock and data as seen at the SDVO device(s)).
Since this mode uses just a single data stream, it uses a single pixel pipeline
within the GMCH.
302
Datasheet
Functional Description
10.5.3
Multiple Display Configurations
Microsoft Windows* 2000, Windows* XP, and Windows Vista* operating systems have
enabled support for multi-monitor display. Since the GMCH has several display ports
available for its two pipes, it can support up to two different images on different
display devices. Timings and resolutions for these two images may be different. The
GMCH supports Intel® Dual Display Clone, Intel® Dual Display Twin, Intel® Dual
Display Zoom, and Extended Desktop.
Intel Dual Display Clone uses both display pipes to drive the same content, at the
same resolution and color depth to two different displays. This configuration allows for
different refresh rates on each display.
Intel Dual Display Twin utilizes one of the display pipes to drive the same content, at
the same resolution, color depth, and refresh rates to two different displays.
Intel Dual Display Zoom uses both display pipes to drive different content, at
potentially different resolutions, refresh rates, and color depths to two different
displays. This configuration results in a portion of the primary display to be zoomed in
on and displayed on the secondary display.
Extended Desktop uses both display pipes to drive different content, at potentially
different resolutions, refresh rates, and color depths to two different displays. This
configuration allows for a larger Windows Desktop by using both displays as a work
surface.
Note: The GMCH is also incapable of operating in parallel with an external PCI Express
graphics device. The GMCH can, however, work in conjunction with a PCI graphics
adapter.
10.6
Power Management
Power Management Feature List:
Datasheet
•
ACPI 1.0b support
•
ACPI S0, S1D, S3 (both Cold and Chipset Hot), S4, S5, C0, and C1 states
•
Enhanced power management state transitions for increasing time processor
spends in low power states
•
Internal Graphics Display Device Control D0, D1, D2, D3
•
Graphics Adapter States: D0, D3
•
PCI Express Link States: L0, L0s, L1, L2/L3 Ready, L3
303
Functional Description
10.7
Thermal Sensor
There are several registers that need to be configured to support the GMCH thermal
sensor functionality and SMI# generation. Customers must enable the Catastrophic
Trip Point at 115 °C as protection for the GMCH. If the Catastrophic Trip Point is
crossed, then the GMCH will instantly turn off all clocks inside the device. Customers
may optionally enable the Hot Trip Point between 85 °C and 105 °C to generate SMI#.
Customers will be required to then write their own SMI# handler in BIOS that will
speed up the GMCH (or system) fan to cool the part.
10.7.1
PCI Device 0, Function 0
The SMICMD register requires that a bit be set to generate an SMI# when the Hot trip
point is crossed. The ERRSTS register can be inspected for the SMI alert.
10.7.2
Address
Offset
Symbol
C8–C9h
ERRSTS
CC–CDh
SMICMD
Register Name
Default
Value
Access
Error Status
0000h
RO, RWC/S
SMI Command
0000h
RO, RW
MCHBAR Thermal Sensor Registers
The Digital Thermometer Configuration Registers reside in the MCHBAR configuration
space.
304
Address
Offset
Symbol
CD8h
TSC1
CD9h
TSC2
CDAh
TSS
CDC–CDFh
TSTTP
CE2h
TCO
CE4h
Register Name
Default
Value
Access
Thermal Sensor Control 1
00h
RW/L, RW,
RS/WC
Thermal Sensor Control 2
00h
RW/L, RO
Thermal Sensor Status
00h
RO
00000000h
RO, RW,
RW/L
Thermal Calibration Offset
00h
RW/L/K,
RW/L
THERM1
Hardware Protection
00h
RW/L, RO,
RW/L/K
CE6h
THERM3
TCO Fuses
00h
RS/WC, RO
CEA–CEBh
TIS
0000h
RO, RWC
CF1h
TSMICMD
00h
RO, RW
Thermal Sensor Temperature Trip
Point
Thermal Interrupt Status
Thermal SMI Command
Datasheet
Functional Description
10.7.3
Programming Sequence
Note: The following sequence must be followed in BIOS to properly set up the Hot
Trip Point and SMI# assertion.
1.
In Thermal Sensor Control 1 Register (TSC1), set thermal sensor enable bit (TSE)
and the hysteresis value (DHA) by writing 99h to MCHBAR CD8h.
2.
Program the Hot Trip Point Register (TSTTP[HTPS]) by writing the appropriate
value to MCHBAR CDCh bits [15:8].
3.
Program the Catastrophic Trip Point Setting Register (TSTTP[CTPS]) by writing
2Ch to MCHBAR CDCh bits [7:0].
4.
In Thermal Sensor Control 2 Register (TSC2), program the Thermometer Mode
Enable and Rate (TE) by writing 04h to MCHBAR CD9h bits [3:0].
5.
In the Hardware Protection Register (THERM1), program the Halt on Catastrophic
bit (HOC) by writing 08h to MCHBAR CE4h bits [7:0].
6.
Lock the Hardware Protection by writing a 1 to the Lock bit (HTL) at MCHBAR
CE4h bit [0].
7.
In Thermal SMI Command Register (TSMICMD), set the SMI# on Hot bit by
writing a 02h to MCHBAR CF1h.
8.
Program the SMI Command register (SMICMD[TSTSMI]) by writing a 1 to bit 11 to
PCI CCh.
9.
Program the TCO Register (TCO[TSLB]) to lock down the other register settings by
writing a 1 to bit 7 of MCHBAR CE2h.
If the temperature rises above the Hot Trip point:
The TIS[Hot Thermal Sensor Interrupt Event] is set when SMI# interrupt is generated.
Clear this bit of the TIS register to allow subsequent interrupts of this type to get
registered.
Clear the global thermal sensor event bit in the Error Status Register, bit 11.
In thermal sensor status register (TSS), the Hot trip indicator (HTI) bit is set if this
condition is still valid by the time the software gets to read the register.
10.7.4
Trip Point Temperature Programming
The Catastrophic and Hot trip points are programmed in the TSTTP - Thermal Sensor
Temperature Trip Point Register. Bits 7:0 are for the Catastrophic trip point (CTPS),
and bits 15:8 are for the Hot trip point (HTPS).
Note: Based on Intel silicon test and calculations, the Catastrophic trip point must
be fixed at 115 °C. The Hot trip point is recommended to be between 85 °C
and 105 °C. Programming the Hot Trip Point above this range is not
recommended.
To program both trip point settings, the following polynomial equation should be used.
Programmed temp = (0.0016*value^2)–(1.10707*value)+161.05
Datasheet
305
Functional Description
In this case the “value” is a decimal number between 0 and 128. For the Catastrophic
Trip Point, a decimal value of 44 (0x2C) should be used to hit 115 °C.
(0.0016*44^2)-(1.10707*44)+161.05 = 115.4 deg C
The CTPS should then be programmed with 0x2C. The Hot Trip Point is also
programmed in the same manner.
306
Datasheet
Functional Description
10.8
Clocking
The GMCH has a total of 5 PLLs providing many times that many internal clocks. The
PLLs are:
Datasheet
•
Host PLL – Generates the main core clocks in the host clock domain. This PLL can
also be used to generate memory and internal graphics core clocks. The PLL uses
the Host clock (H_CLKIN) as a reference.
•
Memory I/O PLL - Optionally generates low jitter clocks for memory I/O interface,
as opposed to from Host PLL. The PLL uses the Host FSB differential clock
(HPL_CLKINP/HPL_CLKINN) as a reference. Low jitter clock source from Memory
I/O PLL is required for DDR667 and higher frequencies.
•
PCI Express PLL – Generates all PCI Express related clocks, including the Direct
Media , that connect to the ICH. This PLL uses the 100 MHz clock (G_CLKIN) as a
reference.
•
Display PLL A – Generates the internal clocks for Display A. This PLL uses
D_REFCLKIN as a reference.
•
Display PLL B – Generates the internal clocks for Display B. This PLL uses
D_REFCLKIN as a reference.
•
CK505 is the Clocking chip required for the Intel G35 Express Chipset platform
307
Functional Description
Figure 10-5. Intel® G35 Express Chipset System Clock Diagram
CK505
56-Pin SSOP
CPU Diff Pair
CPU
C1
CPU Diff Pair
C2
Memory
CPU Diff Pair
XDP
C3/S7
x16 PCI Express
PCI Express DIff Pair
PCI Express GFX
S6
PCI Express DIff Pair
PCI Express Slot
S5
G35
GMCH
PCI Express DIff Pair
PCI Express DIff Pair
DMI
LAN (Nineveh)
S4
PCI Express DIff Pair
PCI Express Slot
S3
PCI Express DIff Pair
S2
SATA Diff Pair
S1
D1
U1
R1
DOT 96MHz Diff Pair
USB 48MHz
REF 14MHz
REF 14MHz
SIO LPC
PCI 33MHz
Intel® ICH8
P1
P2
P3
PCI 33MHz
PCI Down Device
PCI 33MHz
TPM LPC
PCI 33MHz
OSC
Intel High
Definition Audio
24MHz
Signal Name
P4
P5
P6
PCI 33MHz
PCI 33MHz
PCI 33MHz
NC
NC
PCI Slot
32.768kHz
Reference
BCLK, ITPCLK, HCLK
C1-C3
SATACLK, ICHCLK, MCHCLK,
LANCLK, PCIECLK
S1-S7
DOTCLK
D1
USBCLK
U1
PCICLK
P1-P6
REFCLK
R1
§
308
Datasheet
Functional Description
Datasheet
309
Electrical Characteristics
11
Electrical Characteristics
This chapter provides the DC characteristics of the GMCH.
11.1
Absolute Minimum and Maximum Ratings
Table 11-1 specifies the GMCH absolute maximum and minimum ratings. Within
functional operation limits, functionality and long-term reliability can be expected.
At conditions outside functional operation condition limits, but within absolute
maximum and minimum ratings, neither functionality nor long-term reliability can be
expected. If a device is returned to conditions within functional operation limits after
having been subjected to conditions outside these limits, but within the absolute
maximum and minimum ratings, the device may be functional, but with its lifetime
degraded depending on exposure to conditions exceeding the functional operation
condition limits.
At conditions exceeding absolute maximum and minimum ratings, neither functionality
nor long-term reliability can be expected. Moreover, if a device is subjected to these
conditions for any length of time its reliability will be severely degraded or not
function when returned to conditions within the functional operating condition limits.
Although the MCH contains protective circuitry to resist damage from static electric
discharge, precautions should always be taken to avoid high static voltages or electric
fields.
Table 11-1. Absolute Minimum and Maximum Ratings
Symbol
Tstorage
Parameter
Min
Max
Unit
Notes
Storage Temperature
-55
150
°C
1
1.25 V Core Supply Voltage with respect to
VSS
-0.3
1.375
V
MCH Core
VCC
Host Interface (800/1066/1333 MHz)
VTT
System Bus Input Voltage with respect to VSS
-0.3
1.32
V
VCCA_HPLL
1.25 V Host PLL Analog Supply Voltage with
respect to VSS
-0.3
1.375
V
System Memory Interface (DDR2 667/800 MHz)
310
VCCSM
1.8 V DDR2 System Memory Supply
Voltage with respect to VSS
-0.3
4.0
V
VCC_SMCLK
1.8 V DDR2 Clock System Memory Supply
Voltage with respect to VSS
-0.3
4.0
V
Datasheet
Electrical Characteristics
Symbol
VCCA_MPLL
Parameter
1.25 V System Memory PLL Analog Supply
Voltage with respect to VSS
Min
Max
Unit
-0.3
1.375
V
Notes
PCI Express* / Intel® sDVO / DMI Interface
VCC_EXP
1.25 V PCI Express* and DMI Supply
Voltage with respect to VSS
-0.3
1.375
V
VCCA_EXP
3.3 V PCI Express* Analog Supply Voltage
with respect to VSS
-0.3
3.63
V
VCCA_EXPPLL
1.25 V PCI Express* PLL Analog Supply
Voltage with respect to VSS
-0.3
1.375
V
R, G, B / CRT DAC Display Interface (8 bit)
VCCA_DAC
3.3 V Display DAC Analog Supply Voltage with
respect to VSS
-0.3
3.63
V
VCCD_CRT
1.5 V Display DAC Digital Supply Voltage
with respect to VSS
-0.3
1.98
V
VCCDQ_CRT
1.5 V Display DAC Quiet Digital Supply
Voltage with respect to VSS
-0.3
1.98
V
VCCA_DPLLA
1.25 V Display PLL A Analog Supply
Voltage with respect to VSS
-0.3
1.375
V
VCCA_DPLLB
1.25 V Display PLL B Analog Supply
Voltage with respect to VSS
-0.3
1.375
V
1.25 V Supply Voltage with respect to VSS
-0.3
1.375
V
3.3 V CMOS Supply Voltage with respect to VSS
-0.3
3.63
V
Controller Link Interface
VCC_CL
CMOS Interface
VCC3_3
NOTE:
1. Possible damage to the GMCH may occur if the GMCH temperature exceeds 150 °C. Intel
does not ensure functionality for parts that have exceeded temperatures above 150 °C due
to specification violation.
11.1.1
Current Consumption
Table 11-2 shows the current consumption for the MCH in the Advanced Configuration
and Power Interface (ACPI) S0 state. Icc max values are determined on a perinterface basis, at the highest frequencies for each interface. Sustained current values
or Max current values cannot occur simultaneously on all interfaces. Sustained Values
are measured sustained RMS maximum current consumption and includes leakage
estimates. The measurements are made with fast silicon at 96 °C Tcase temperature,
at the Max voltage listed in Table 11-4. The Max values are maximum theoretical presilicon calculated values. In some cases, the Sustained measured values have
exceeded the Max theoretical values.
Datasheet
311
Electrical Characteristics
Table 11-2. Current Consumption in S0
Symbol
IVCC
Parameter
1.25 V Core Supply Current
VCC
(Using Integrated Graphics)
(int. graphics)
1.25 V Core Supply Current
VCC
(Using External Graphics)
IVCCSM
IVCC_SMCLK
IVCC_EXP
(ext. graphics)
DDR2 System Memory Interface (1.8 V)
Supply Current
1.25 V PCI Express* / Intel® SDVO and
DMI Supply Current
VCC_EXP
1.25 V PCI Express* / Intel® SDVO and
DMI Supply Current
IVTT
15.5
18.9
7.20
Unit
A
1,2
9.30
3.70
A
1, 2, 3
250
mA
1.76
2.47
A
2
VCC_CL
2.64
3.80
A
2
VTT
0.95
0.98
A
1
(int. graphics)
VCC_EXP
1.25 V Controller Supply Current
®
IVCCA_EXP
3.3 V PCI Express* / Intel SDVO and DMI
Analog Supply Current
VCCA_EXP
0.36
0.36
mA
IVCCA_DAC
3.3 V Display DAC Analog Supply Current
VCCA_DAC
70
65.8
mA
VCC3_3
21
15.8
mA
30
mA
0.03
mA
3.3 V CMOS Supply Current
IVCCD_CRT
1.5 V Display Digital Supply Current
IVCCDQ_CRT
1.5 V Display Quiet Digital Supply Current
IVCCA_EXPPLL
1.25 V PCI Express* / Intel® SDVO and DMI
PLL Analog Supply Current
VCCD_CRT
100
VCCDQ_CRT
VCCA_EXPPLL
70
71.6
mA
VCCA_HPLL
20
67.9
mA
IVCCA_HPLL
1.25 V Host PLL Supply Current
IVCCA_DPLLA
1.25 V Display PLL A and PLL B Supply
Current
VCCA_DPLLA
30
90.6
mA
IVCCA_DPLLB
1.25 V Display PLL A and PLL B Supply
Current
VCCA_DPLLB
40
90.6
mA
IVCCA_MPLL
1.25 V System Memory PLL Analog Supply
Current
VCCA_MPLL
90
225
mA
1.
2.
3.
Notes
(ext. graphics)
System Bus Supply Current
IVCC3_3
312
Max
2.26
VCC_SMCLK
(Using Integrated Graphics)
Sustained
VCCSM
DDR2 System Memory Clock Interface
(1.8 V) Supply Current
(Using External Graphics)
IVCC_CL
Signal
Names
NOTES:
Measurements are for current coming through chipset’s supply pins.
Rail includes DLLs (and FSB sense amps on VCC).
Sustained Measurements are combined because one voltage regulator on the platform supplies
both rails on the GMCH.
Datasheet
3
Electrical Characteristics
11.2
Signal Groups
The signal description includes the type of buffer used for the particular signal.
PCI Express*
/ Intel® sDVO
DMI
Datasheet
PCI Express interface signals. These signals are compatible with PCI Express
1.1 Signaling Environment AC Specifications and are AC coupled. The buffers
are not 3.3 V tolerant. Differential voltage spec = (|D+ - D-|) * 2 =
1.2 Vmax. Single-ended maximum = 1.25 V. Single-ended minimum = 0 V.
Direct Media Interface signals. These signals are compatible with PCI
Express 1.0 Signaling Environment AC Specifications, but are DC coupled.
The buffers are not 3.3 V tolerant. Differential voltage spec = (|D+ - D-|) *
2 = 1.2 Vmax. Single-ended maximum = 1.25 V. Single-ended minimum =
0 V.
GTL+
Open Drain GTL+ interface signal. Refer to the GTL+ I/O Specification for
complete details.
HCSL
Host Clock Signal Level buffers. Current mode differential pair. Differential
typical swing = (|D+ – D-|) * 2 = 1.4 V. Single ended input tolerant from 0.35V to 1.2V. Typical crossing voltage 0.35 V.
SSTL-1.8
Stub Series Termination Logic. These are 1.8 V output capable buffers. 1.8 V
tolerant.
SSTL-1.5
Stub Series Termination Logic. These are 1.5 V output capable buffers. 1.5 V
tolerant.
CMOS
CMOS buffers
Analog
Analog reference or output. May be used as a threshold voltage or for buffer
compensation.
313
Electrical Characteristics
Table 11-3. Signal Groups
Signal Type
Signals
Notes
Host Interface Signal Groups
GTL+ Input/Outputs
HADS#, HBNR#, HBREQ0#, HDBSY#, HDRDY#, HDINV[3:0]#,
HA[35:3]#, HADSTB[1:0]#, HD[63:0]#, HDSTBP[3:0]#,
HDSTBN[3:0]#, HHIT#, HHITM#, HREQ[4:0]#, HLOCK#
GTL+ Common Clock Outputs
HBPRI#, HCPURST#, HDEFER#, HTRDY#, HRS[2:0]#
Analog Host I/F Ref and Comp.
Signals
HDVREF, HACCVREF, HSWING, HRCOMP, HSCOMP, HSCOMP#
GTL+ Input
BSEL[2:0]
®
PCI Express* Graphics and Intel sDVO Interface Signal Groups
PCI Express* / Intel® sDVO Input
PCI Express* Interface: EXP_RXN[15:0], EXP_RXP[15:0],
1
®
Intel sDVO Interface: SDVO_TVCLKIN+, SDVO_TVCLKIN-,
SDVOB_INT+, SDVOB_INT-, SDVO_STALL+, SDVO_STALL-,
SDVOC_INT+, SDVOC_INTPCI Express* / Intel® sDVO Output
PCI Express* Interface: EXP_TXN[15:0], EXP_TXP[15:0]
1
®
Intel sDVO Interface:
SDVOB_RED+, SDVOB_RED-, SDVOB_GREEN+,
SDVOB_GREEN-, SDVOB_BLUE+, SDVOB_BLUE-,
SDVOB_CLK+, SDVOB_CLK-, SDVOC_RED+/SDVOB_ALPHA+,
SDVOC_RED-/SDVOB_ALPHA-, SDVOC_GREEN+,
SDVOC_GREEN-, SDVOC_BLUE+, SDVOC_BLUE-,
SDVOC_CLK+, SDVOC_CLKCMOS I/O OD
SDVO_CTRLCLK, SDVO_CTRLDATA
®
Analog PCI Express* / Intel sDVO
Interface Compensation Signals
EXP_COMPO, EXP_COMPI
Direct Media Interface Signal Groups
DMI Input
DMI_RXN[3:0], DMI_RXP[3:0]
DMI Output
DMI_TXN[3:0], DMI_TXP[3:0]
System Memory Interface Signal Groups
SSTL-1.8 / SSTL-1.5 Input/Output
SDQ_A[63:0], SDQ_B[63:0], SDQS_A[7:0], SDQS_A[7:0]#,
SDQS_B[7:0], SDQS_B[7:0]#
SSTL-1.8 / SSTL-1.5 Output
SDM_A[7:0], SDM_B[7:0], SMA_A[14:0], SMA_B[14:0],
SBS_A[2:0], SBS_B[2:0], SRAS_A#, SRAS_B#, SCAS_A#,
SCAS_B#, SWE_A#, SWE_B#, SODT_A[3:0], SODT_B[3:0],
SCKE_A[3:0], SCKE_B[3:0], SCS_A[3:0]#, SCS_B[3:0]#,
SCLK_A[5:0], SCLK_A[5:0]#, SCLK_B[5:0], SCLK_B[5:0]#
CMOS Input
N/A
Reference and Comp. Voltages
SRCOMP[3:0], SMVREF, SRCOMP_VOL, SRCOMP_VOH
314
Datasheet
Electrical Characteristics
Signal Type
Signals
Notes
Controller Link Signal Groups
CMOS I/O OD
CL_DATA, CL_CLK
CMOS Input
CL_RST#, CL_PWROK
Analog Controller Link Reference
Voltage
CL_VREF
R, G, B / CRT DAC Display Signal Groups
Analog Current Outputs
RED, RED#, GREEN, GREEN#, BLUE, BLUE#
Analog/Ref DAC Miscellaneous
REFSET
CMOS I/O OD
DDC_CLK, DDC_DATA
HVCMOS Output
HSYNC, VSYNC
2
Clocks
HCSL
HCLKN, HCLKP, DREFCLKP, DREFCLKN, GCLKP, GCLKN
Reset, and Miscellaneous Signal Groups
CMOS Input
EXP_EN, EXP_SLR, RSTIN#, PWROK
CMOS Output
ICH_SYNC#
Miscellaneous
TEST[2:0]
I/O Buffer Supply Voltages
System Bus Input Supply Voltage
®
VTT
1.25 V PCI Express* / Intel sDVO
Supply Voltages
VCC_EXP
3.3 V PCI Express* / Intel® sDVO
Analog Supply Voltage
VCCA_EXP
1.8 V DDR2 Supply Voltage
VCCSM
1.8 V DDR2 Clock Supply Voltage
VCC_SMCLK
1.25 V GMCH Core Supply Voltage
VCC
1.25 V Controller Supply Voltage
VCC_CL
3.3 V CMOS Supply Voltage
VCC3_3
3.3 V R, G, B / CRT DAC Display
Analog Supply Voltage
VCCA_DAC
1.5 V DAC Digital Supply Voltages
VCCD_CRT, VCCDQ_CRT
PLL Analog Supply Voltages
VCCA_HPLL, VCCA_EXPPLL, VCCA_DPLLA, VCCA_DPLLB,
VCCA_MPLL
NOTES:
1.
See Section 2.10 for Intel® sDVO and PCI Express* Pin Mapping
2.
Current Mode Reference pin. DC Specification not required.
Datasheet
315
Electrical Characteristics
11.3
Buffer Supply and DC Characteristics
11.3.1
I/O Buffer Supply Voltages
The I/O buffer supply voltage is measured at the GMCH package pins. The tolerances
shown in Table 11-4 are inclusive of all noise from DC up to 20 MHz. In the lab, the
voltage rails should be measured with a bandwidth limited oscilloscope with a roll off
of 3 dB/decade above 20 MHz under all operating conditions.
Table 11-4 indicates which supplies are connected directly to a voltage regulator or to
a filtered voltage rail. For voltages that are connected to a filter, they should me
measured at the input of the filter.
If the recommended platform decoupling guidelines cannot be met, the system
designer will have to make tradeoffs between the voltage regulator output DC
tolerance and the decoupling performance of the capacitor network to stay within the
voltage tolerances listed in Table 11-4.
Table 11-4. I/O Buffer Supply Voltage
Symbol
Parameter
Min
Nom
Max
Unit Notes
VCCSM
DDR2 I/O Supply Voltage
1.7
1.8
1.9
V
5
VCC_SMCLK
DDR2 Clock Supply Voltage
1.7
1.8
1.9
V
2
VCC_EXP
SDVO, PCI Express* Supply Voltage
1.188
1.25
1.313
V
VCCA_EXP
SDVO, PCI Express* Analog Supply Voltage
3.135
3.3
3.465
V
1.2 V System Bus Input Supply Voltage
1.14
1.2
1.26
V
1.1 V System Bus Input Supply Voltage
1.045
1.1
1.155
V
MCH Core Supply Voltage
1.188
1.25
1.313
V
VCC_CL
Controller Supply Voltage
1.188
1.25
1.313
V
VCC3_3
CMOS Supply Voltage
3.135
3.3
3.465
V
VCCA_DAC
Display DAC Analog Supply Voltage
3.135
3.3
3.465
V
3
VCCD_CRT
Display Digital Supply Voltage
1.425
1.5
1.575
V
1
VCCDQ_CRT
Display Quiet Digital Supply Voltage
1.425
1.5
1.575
V
1
VCCA_HPLL,
VCCA_EXPPLL,
VCCA_DPLLA,
VCCA_DPLLB,
VCCA_MPLL
Various PLLs’ Analog Supply Voltages
1.188
1.25
1.313
V
2,7
VTT
VCC
1.
2.
3.
4.
316
2
4
NOTES:
The VCCD_CRT and VCCDQ_CRT can also operate at a nominal 1.8 V ±5% input voltage. Only
the 1.5 V nominal voltage setting will be validated internally.
These rails are filtered from other voltage rails on the platform and should be measured at the
input of the filter.
VCCA_DAC voltage tolerance should only be measured when the DAC is turned ON and at a
stable resolution setting. Any noise on the DAC during power on or display resolution changes do
not impact the circuit.
GMCH supports both VTT = 1.2 V nominal and VTT = 1.1 V nominal depending on the identified
processor.
Datasheet
Electrical Characteristics
11.3.2
General DC Characteristics
Platform Reference Voltages at the top of Table 11-5 are specified at DC only. VREF
measurements should be made with respect to the supply voltage.
Table 11-5. DC Characteristics
Symbol
Parameter
Min
Nom
Max
Unit
0.666 x
VTT_FSB
–2%
0.666 x
VTT_FSB
0.666 x
VTT_FSB
+2%
V
Notes
Reference Voltages
FSB_DVREF
FSB_ACCVREF
Host Data, Address, and
Common Clock Signal
Reference Voltages
FSB_SWING
Host Compensation Reference
Voltage
0.25 x VTT_FSB
–2%
0.25 x
VTT_FSB
0.25 x
VTT_FSB
+2%
V
CL_VREF
Controller Link Reference
Voltage
0.270 x VCC_CL
0.279 x
VCC_CL
0.287 x
VCC_CL
V
SMVREF
DDR2 Reference Voltage
0.49 x
VCC_DDR
0.50 x
VCC_DDR
0.51 x
VCC_DDR
V
Host Interface
VIL_H
Host GTL+ Input Low Voltage
-0.10
0
(0.666 x
VTT_FSB) – 0.1
V
VIH_H
Host GTL+ Input High Voltage
(0.666 x
VTT_FSB) + 0.1
VTT_FSB
VTT_FSB + 0.1
V
VOL_H
Host GTL+ Output Low Voltage
—
—
(0.25 x
VTT_FSB) +
0.1
V
VOH_H
Host GTL+ Output High Voltage
VTT_FSB – 0.1
—
VTT_FSB
V
IOL_H
Host GTL+ Output Low Current
—
—
VTT_FSBmax *
(1–0.25) /
Rttmin
mA
Rttmin =
47.5 Ω
ILEAK_H
Host GTL+ Input Leakage
Current
—
—
45
μA
VOL<
Vpad<
Vtt_FSB
CPAD
Host GTL+ Input Capacitance
2.0
—
2.5
pF
CPCKG
Host GTL+ Input Capacitance
(common clock)
0.90
—
2.5
pF
DDR2 System Memory Interface
VIL(DC)
DDR2 Input Low Voltage
—
—
SMVREF –
0.125
V
VIH(DC)
DDR2 Input High Voltage
SMVREF +
0.125
—
—
V
VIL(AC)
DDR2 Input Low Voltage
—
—
SMVREF – 0.25
V
VIH(AC)
DDR2 Input High Voltage
SMVREF + 0.25
—
—
V
Datasheet
317
Electrical Characteristics
Symbol
Parameter
Min
Nom
Max
Unit
Notes
VOL
DDR2 Output Low Voltage
—
—
0.2 * VCCSM
V
1
VOH
DDR2 Output High Voltage
0.8 * VCCSM
—
—
V
1
ILeak
Input Leakage Current
—
—
±20
µA
4
ILeak
Input Leakage Current
—
—
±550
µA
5
CI/O
DQ/DQS/DQSB DDR2
Input/Output Pin Capacitance
1.0
—
4.0
pF
1.25V PCI Express* Interface 1.1 (includes PCI Express* and Intel® sDVO)
VTX-DIFF P-P
Differential Peak to Peak
Output Voltage
0.800
—
1.2
V
VTX_CM-ACp
AC Peak Common Mode Output
Voltage
—
—
20
mV
ZTX-DIFF-DC
DC Differential TX Impedance
80
100
120
Ω
VRX-DIFF p-p
Differential Peak to Peak Input
Voltage
0.175
—
1.2
V
VRX_CM-ACp
AC Peak Common Mode Input
Voltage
—
—
150
mV
2
3
Input Clocks
VIL
Input Low Voltage
-0.150
0
—
V
VIH
Input High Voltage
0.660
0.710
0.850
V
VCROSS(ABS)
Absolute Crossing Voltage
0.300
—
0.550
V
ΔVCROSS(REL)
Range of Crossing Points
—
—
0.140
V
CIN
Input Capacitance
1
—
3
pF
0.75
V
6,7,8
SDVO_CTRLDATA, SDVO_CTRLCLK
VIL
Input Low Voltage
—
—
VIH
Input High Voltage
1.75
—
ILEAK
Input Leakage Current
—
—
± 10
μA
CIN
Input Capacitance
—
—
10.0
pF
IOL
Output Low Current (CMOS
Outputs)
—
—
7.8
mA
@ 50%
swing
IOH
Output High Current (CMOS
Outputs)
-1
—
—
mA
@ 50%
swing
VOL
Output Low Voltage (CMOS
Outputs)
—
—
0.4
V
VOH
Output High Voltage (CMOS
Outputs)
2.25
—
—
V
318
V
Datasheet
Electrical Characteristics
Symbol
Parameter
Min
Nom
Max
Unit
Notes
CRT_DDC_DATA, CRT_DDC_CLK
VIL
Input Low Voltage
—
—
0.9
V
VIH
Input High Voltage
2.1
—
—
V
ILEAK
Input Leakage Current
—
—
± 10
μA
CIN
Input Capacitance
—
10.0
pF
IOL
Output Low Current (CMOS
Outputs)
—
—
27.0
mA
@ 50%
swing
IOH
Output High Current (CMOS
Outputs)
-1
—
—
mA
@ 50%
swing
VOL
Output Low Voltage (CMOS
Outputs)
—
—
0.4
V
VOH
Output High Voltage (CMOS
Outputs)
2.7
—
—
V
0.277
V
CL_DATA, CL_CLK
VIL
Input Low Voltage
—
—
VIH
Input High Voltage
0.427
—
ILEAK
Input Leakage Current
—
—
± 20
μA
CIN
Input Capacitance
—
—
1.5
pF
IOL
Output Low Current (CMOS
Outputs)
—
—
1.0
mA
@VOL_HI
max
IOH
Output High Current (CMOS
Outputs)
6.0
—
—
mA
@VOH_HI
min
VOL
Output Low Voltage (CMOS
Outputs)
—
—
0.06
V
VOH
Output High Voltage (CMOS
Outputs)
0.6
—
—
V
V
PWROK, CL_PWROK, RSTIN#
VIL
Input Low Voltage
—
—
0.3
V
VIH
Input High Voltage
2.7
—
—
V
ILEAK
Input Leakage Current
—
—
±1
mA
CIN
Input Capacitance
—
—
6.0
pF
VIL
Input Low Voltage
—
—
0.13
V
VIH
Input High Voltage
1.17
—
—
V
ILEAK
Input Leakage Current
—
—
±20
μA
CIN
Input Capacitance
—
—
5.0
pF
CL_RST#
Datasheet
319
Electrical Characteristics
Symbol
Parameter
Min
Nom
Max
Unit
Notes
ICH_SYNCB
IOL
Output Low Current (CMOS
Outputs)
—
—
2.0
mA
@VOL_HI
max
IOH
Output High Current (CMOS
Outputs)
-2.0
—
—
mA
@VOH_HI
min
VOL
Output Low Voltage (CMOS
Outputs)
—
—
0.33
V
VOH
Output High Voltage (CMOS
Outputs)
2.97
—
—
V
EXP_SLR, EXP_EN
VIL
Input Low Voltage
-0.10
0
(0.63 x VTT)
– 0.1
V
VIH
Input High Voltage
(0.63 x
VTT)+0.1
VTT
VTT +0.1
V
ILEAK
Input Leakage Current
—
—
20
μA
CIN
Input Capacitance
2
—
2.5
pF
VOL<
Vpad<
Vtt
HSYNC, VSYNC
IOL
Output Low Current (CMOS
Outputs)
—
—
35.0
mA
@VOL_HI
max
IOH
Output High Current (CMOS
Outputs)
-1.0
—
—
mA
@VOH_HI
min
VOL
Output Low Voltage (CMOS
Outputs)
—
—
0.5
V
VOH
Output High Voltage (CMOS
Outputs)
2.4
—
—
V
1.
2.
3.
4.
5.
6.
7.
8.
320
NOTES:
Determined with 2x GMCH Buffer Strength Settings into a 50 Ω to 0.5xVCC_DDR test load.
Specified at the measurement point into a timing and voltage compliance test load as shown in
Transmitter compliance eye diagram of PCI Express* specification and measured over any 250
consecutive TX Uls.
Specified at the measurement point over any 250 consecutive Uls. The test load shown in
Receiver compliance eye diagram of PCI Express* spec should be used as the RX device when
taking measurements.
Applies to pin to VCC or VSS leakage current for the DDR_A_DQ_63:0 and DDR_B_DQ_63:0
signals.
Applies to pin to pin leakage current between DDR_A_DQS_7:0, DDR_A_DQSB_7:0,
DDR_B_DQS_7:0, and DDR_B_DQSB_7:0 signals.
Crossing voltage defined as instantaneous voltage when rising edge of BCLK0 equals falling edge
of BCLK1.
VHavg is the statistical average of the VH measured by the oscilloscope.
The crossing point must meet the absolute and relative crossing point specifications
simultaneously. Refer to the appropriate processor datasheet for further information.
Datasheet
Electrical Characteristics
11.3.3
R, G, B / CRT DAC Display DC Characteristics
Table 11-6. R, G, B / CRT DAC Display DC Characteristics: Functional Operating Range
(VCCA_DAC = 3.3 V ± 5%)
Parameter
Min
Typ
Max
Units
Notes
8
—
—
Bits
1
0.66
5
0.700
0.77
V
1, 2, 4 (white video level
voltage)
Min Luminance
—
0.000
—
V
1, 3, 4 (black video level
voltage)
LSB Current
—
73.2
—
μA
4,5
Integral Linearity (INL)
-1.0
—
+1.0
LSB
1,6
Differential Linearity
(DNL)
-1.0
—
+1.0
LSB
1,6
—
—
6
%
7
DAC Resolution
Max Luminance (fullscale)
Video channel-channel
voltage amplitude
mismatch
Monotonicity
1.
2.
3.
4.
5.
6.
7.
Datasheet
Ensured
—
NOTES:
Measured at each R, G, B termination according to the VESA Test Procedure – Evaluation of
Analog Display Graphics Subsystems Proposal (Version 1, Draft 4, December 1, 2000).
Max steady-state amplitude
Min steady-state amplitude
Defined for a double 75 Ω termination.
Set by external reference resistor value.
INL and DNL measured and calculated according to VESA Video Signal Standards.
Max full-scale voltage difference among R, G, B outputs (percentage of steady-state full-scale
voltage).
321
Ballout and Package Information
12
Ballout and Package
Information
This chapter contains the ballout and package information for the 82G35 GMCH.
12.1
Ballout
Figure 12-1, Figure 12-2, and Figure 12-3 show the ballout from a top view of the
package. Table 12-1 provides a ballout list arranged alphabetically by ball number.
Note: Notes for Figure 12-1, Figure 12-2, and Figure 12-3, and Table 12-1.
322
1.
Balls that are listed as RSVD are reserved.
2.
Some balls marked as reserved (RSVD) are used in XOR testing. See Chapter 13
for details.
3.
Balls that are listed as NC are No Connects.
Datasheet
Ballout and Package Information
Figure 12-1. GMCH Ballout Diagram (Top View Left – Columns 43–30)
43
42
41
BC
TEST0
NC
VSS
BB
NC
VCC_
SMCLK
VCC_
SMCLK
BA
VCC_
SMCLK
VCC_
SMCLK
AY
AW
VSS
AV
AU
SDM_A4
VCC_
SMCLK
VSS
RSVD
VSS
SDQ_A32
SDQ_A37
VSS
40
39
38
VCCSM
SRCOMP2
VCCSM
SCS_A3#
SRCOMP3
SODT_A3
SODT_A1
SMA_A13
VSS
SDQS_B4
SDQ_A36
37
36
35
VSS
34
VCCSM
SDQ_A38
AP
VSS
AN
AM
SDM_A5
AL
AK
VSS
AJ
AH
SDQ_A49
AG
AF
VSS
AE
AD
SDQ_A57
AC
AB
VSS
AA
Y
HHITM#
W
V
VSS
U
T
HDEFER#
SWE_A#
SRAS_A#
SCS_A1#
SCS_A2#
SBS_A0
P
VSS
N
M
HDSTBN0#
L
K
VSS
J
HREQ3#
SODT_B1
BA
VCCSM
SCS_B3#
AY
SBS_A1
SCLK_B0#
AW
SDQ_B33
VSS
VSS
SCLK_A2
SCLK_B2
SCLK_B0
AV
SDQ_A33
SDQS_B4#
VSS
SDM_B4
SDQ_B36
SCLK_A5#
VSS
SCLK_A0
AU
SCLK_A5
SCLK_B2#
VSS
AT
SDQS_A4#
SDQ_B44
VSS
SDQ_B39
SDQ_B37
VSS
VSS
SCLK_A0#
AR
VSS
SDQ_B35
SDQ_B38
SCLK_B5
SDQ_A35
VSS
SDQ_A41
SDQ_B41
SDM_B5
VSS
SDQ_B40
SDQ_B45
VSS
SDQ_A46
SDQS_A5
SDQS_A5#
SDQ_A47
SDQ_B43
SDQ_B46
VSS
SDQS_B5
SDQS_B5#
VSS
SDQ_A42
SDQ_A43
SDQ_A52
SDQ_A53
SCLK_B5# SCLK_A3#
SDQ_B34
RSVD
SDQ_B47
AP
VSS
AN
RSVD
AM
RSVD
AL
VCC_CL
SDQ_A48
VSS
SDQ_B49
SDQ_B52
VSS
SDQ_B53
SDQ_B42
VSS
RSVD
VCC_CL
VCC_CL
VSS
AK
AJ
AH
SDQS_A6
SDQS_A6#
SDQ_A55
SDQ_A54
SDQ_A60
SDQ_A61
VSS
SDQS_A7
SDQS_A7#
SDQ_A63
SDQ_A58
HBREQ0#
HRS1#
VSS
SDM_A6
SDM_B6
SDQ_B48
VSS
SDQS_B6#
SDQS_B6
VSS
SDQ_B54
RSVD
VCC_CL
VCC_CL
SDQ_A50
SDQ_B61
VSS
VSS
SDQ_B50
SDQ_B55
SDQ_B51
RSVD
VCC_CL
VCC_CL
SDQ_A51
AG
AF
AE
SDQ_A56
VSS
SDM_B7
VSS
SDQ_B56
VSS
SDQ_B60
VSS
VCC_CL
VCC_CL
VCC_CL
SDM_A7
SDQ_A62
VSS
SDQS_B7#
SDQS_B7
VSS
SDQ_B62
SDQ_B57
VCC_CL
VCC_CL
VCC_CL
AD
AC
AB
SDQ_A59
HTRDY#
SM_
SLEWIN1
HA34#
VSS
HA33#
HA35#
VSS
SDQ_B59
HA32#
VSS
VSS
SDQ_B58
HA29#
SDQ_B63
VCC_CL
VCC_CL
VCC_CL
VSS
VCC_CL_
PLL
VCC_CL
VCC_CL
HADS#
AA
Y
HBNR#
HDRDY#
HA30#
HLOCK#
VSS
HA31#
VSS
HA22#
HA28#
VSS
HA27#
VSS
RSVD
VCC_CL
V
HHIT#
HRS0#
HDBSY#
HRS2#
VSS
HA17#
HA24#
VSS
HADSTB1#
HA25#
HCLKN
RSVD
RSVD
U
HD2#
HD0#
HA21#
HA23#
HA19#
VSS
HA26#
HA14#
VSS
HCLKP
VSS
RSVD
R
VSS
P
HD3#
HA18#
HA16#
HA12#
VSS
HA15#
HA10#
VSS
HA9#
VSS
N
HDINV0#
HD5#
HA11#
VSS
HA13#
VSS
HADSTB0#
VSS
HD34#
M
HDSTBP0#
HA4#
HREQ2#
HA6#
HA7#
HREQ1#
W
VSS
T
HA20#
HD1#
HD7
HD6#
VSS
HD10#
HD8#
HA8#
HD12#
HA3#
HD11#
VSS
HA5#
HD13#
HD20#
HD50#
HD52#
HD17#
C
VSS
HD16#
B
NC
NC
HD51#
A
TEST2
NC
VSS
43
42
41
Datasheet
SMA_A0
SMA_A10
SDQ_A44
VSS
D
BB
SCLK_A2#
SDQ_A39
HD14#
E
SCS_B1#
SCS_A0#
SDQ_A40
HD15#
F
BC
SODT_B3
SCAS_A#
HD9#
VSS
HREQ4#
VSS
VSS
H
G
VCCSM
30
VCCSM
SODT_A0
SDQ_A34
VSS
31
SDQ_B32
SDQ_A45
HD4
R
SDQS_A4
32
VSS
SODT_A2
AT
AR
33
VCCSM
HBPRI#
HREQ0#
HDINV1#
VSS
HD32#
J
HDSTBN1#
HD30#
VSS
H
G
HD19#
HDSTBP1#
HD25#
VSS
HD37#
VSS
VSS
HD27#
HD33#
HD39#
F
HD22#
HD28#
HDINV3#
VSS
HD35#
E
HD57#
HD54#
HD59#
HD63#
HDSTBN3#
HD23#
HD56#
HD55#
HD24#
HDSTBP3#
VSS
39
L
K
VSS
HD53#
40
VSS
HD36#
HD18#
HD21#
VSS
VSS
HD29#
VSS
HD49#
HD60#
HD48#
HD61#
HD31#
HD58#
HD26#
38
37
VSS
36
35
34
VSS
VSS
VTT
C
VSS
VTT
B
VTT
A
HD62#
33
32
D
HCPURST#
31
30
323
Ballout and Package Information
Figure 12-2. GMCH Ballout Diagram (Top View Middle– Columns 29–15)
29
28
27
VSS
BC
BB
SODT_B2
BA
SODT_B0
VCCSM
26
25
VCCSM
SCS_B0#
VCCSM
SMA_A1
SWE_B#
SMA_A2
SMA_A3
AY
SMA_B13
SCS_B2#
AW
SCAS_B#
SCLK_B4# SRAS_B#
AV
SCLK_B4
VSS
AU
SCLK_B3
AT
24
23
VSS
SMA_A4
VCCSM
22
21
VCCSM
20
19
SCKE_A0
SMA_A8
SMA_A11
SBS_A2
SMA_A5
SMA_A9
SMA_A14
VCCSM
18
17
VCCSM
RSVD
VCCSM
SMA_B0
SCKE_A3
SBS_B1
SBS_B0
16
15
SMA_B3
VCCSM
BC
SMA_B6
BB
SMA_B2
SMA_B5
BA
SMA_A6
SMA_A7
SCKE_A2
SCKE_A1
SMA_B1
SMA_B8
AY
VCCSM
SDQ_B29
SMA_A12
VCCSM
SMA_B10
SDQ_B23
SMA_B4
AW
VCCSM
SDQ_B24
VSS
VSS
SDQ_A31
VCCSM
VSS
SDQ_B22
AV
SCLK_B1
SDQS_
B3#
VSS
SDQ_B28
SDQ_A26
VSS
SDQS_A3
#
SDQ_B18
SDQ_B16
AU
VSS
SCLK_B1#
SDQ_B26
SDQS_B3
SDQ_B25
SDQ_A27
SDQS_A3
SDQ_A24
SDQ_B19
VSS
AT
AR
SCLK_B3#
VSS
VSS
SDQ_B30
VSS
VSS
VSS
SDQ_A25
VSS
SDQS_B2#
AR
AP
SCLK_A3
SCLK_A1
SDQ_B27
VSS
SDM_B3
SM_
SLEWIN0
SDQ_A30
VSS
SDQ_A28
SDQS_B2
AP
AN
VSS
SCLK_A1#
SDQ_B31
VSS
VSS
RSVD
VSS
SDM_A3
SDQ_A29
VSS
AN
AM
VSS
SCLK_A4#
SCLK_A4
VSS
VSS
RSVD
VSS
RSTIN#
PWROK
CL_
PWROK
AM
AL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
AL
AK
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
AK
AJ
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
AH
AJ
AH
AG
VCC_CL
VCC_CL
VCC_CL
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
AF
VCC_CL
VCC_CL
VCC
VCC
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
AE
VCC_CL
VCC
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VCC
VCC
AC
VCC_CL
VCC
VCC
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VCC
VCC
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VCC
AD
AC
AB
AA
VCC_CL
VCC
VCC
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VCC
Y
VCC_CL
VCC
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VCC
VCC
W
AF
AE
AD
AB
AG
AA
Y
W
V
VCC_CL
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
U
VCC_CL
VCC_CL
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
T
V
U
T
R
RSVD
VTT
VTT
VTT
VTT
VSS
VCC
VCC
VCC
VCC
R
P
VTT
VTT
VTT
VTT
VTT
VSS
VCC
VSS
VSS
VCC
P
N
VTT
VSS
VTT
VTT
VTT
VSS
NC
RSVD
RSVD
RSVD
N
M
VTT
VSS
HD47#
VTT
VTT
VSS
RSVD
RSVD
VSS
VSS
M
L
VSS
HD42#
HD45#
VTT
VTT
VSS
VSS
RSVD
RSVD
RSVD
L
K
HD38#
HD43#
VSS
VTT
VTT
VSS
ALLZTEST
VSS
RSVD
EXP_RXP1
K
J
HD40#
VSS
HD46#
VTT
VTT
VSS
BSEL1
BSEL2
EXP_EN
EXP_RXN1
J
H
VSS
HDSTBN2
#
HD44#
VTT
VTT
VSS
VSS
RSVD
VSS
VSS
H
G
HDINV2#
HDSTBP2#
VTT
VTT
VTT
VSS
BSEL0
RSVD
SDVO_
CTRLDAT
A
EXP_RXN0
G
F
HD41#
VSS
VTT
VTT
VTT
VSS
XORTEST
VSS
RSVD
EXP_RXP0
F
E
VTT
VTT
VTT
VSS
VTT
VSS
VSS
EXP_SLR
SDVO_
CTRLCLK
VSS
E
HDVREF
HRCOMP
VSS
BLUE#
GREEN
RED#
VCCA_
DAC
VSS
RED
VCC3_3
D
VTT
C
VTT
B
VTT
VTT
VTT
29
28
VCCA_
HPLL
VTT
VSS
HSCOMP
VTT
VSS
HSWING HACCVREF
VTT
A
324
VTT
HSCOMP
#
VSS
27
26
VSS
VCCA_
MPLL
25
24
VCCA_
DPLLB
VCCD_
CRT
VSS
VCCDQ_
CRT
VCCA_
DPLLA
23
22
BLUE
GREEN#
REFSET
21
20
VSS
18
VCCA_DA
C
VSYNC
D
HSYNC
C
VCCA_
EXPPLL
B
VCCA_EX
P
VSS
19
VSS
17
16
A
15
Datasheet
Ballout and Package Information
Figure 12-3. GMCH Ballout Diagram (Top View Right – Columns 14–0)
14
BC
VCCSM
BB
SMA_B9
BA
SMA_B7
13
12
11
SBS_B2
SMA_B11
10
9
8
VSS
7
6
SDQ_A17
VCCSM
SCKE_B2
SDQ_A23
SDQS_A2
SCKE_B3
SDQ_A22
SDQS_A2#
SMA_B14
SCKE_B0
SDQ_A19
SDM_B2
SCKE_B1
AV
SDQ_B17
SDQ_B14
AU
SDQ_B20
AT
VSS
AR
AP
5
4
VSS
VSS
SDQ_A20
SDQ_A10
SDQ_A15
SDQ_A21
SDQ_A14
SDQS_A1#
SDM_A2
SDQ_A16
SDQ_A11
SDQ_A18
SDM_B1
SDQ_B3
VSS
VSS
VSS
SDQS_B0
SDQ_B15
SDQ_B9
SDQ_B13
SDQ_B7
VSS
VSS
SDQ_B8
SDQ_B11
SDQS_B1
SDQ_B12
SDQ_B10
SDQS_B1#
AN
VSS
VSS
AM
SDQ_B21
AL
VCC_CL
AY
A
SMA_B12
VSS
SDQ_B2
3
2
1
VSS
NC
TEST1
BC
SDQS_A1
RSVD
NC
BB
SDM_A1
VSS
SDQ_A9
SDQ_A8
SDQ_A13
SDQ_A12
SDQ_A2
SDQ_A3
BA
AY
VSS
W
A
W
VCC_CL
SDQ_A7
SDQS_B0#
SDQS_A0
VSS
VSS
VSS
SDM_B0
SDQ_B6
SDQ_B1
SDQ_B0
VSS
SDQ_A0
SDQ_B5
SDQ_B4
SDQ_A1
VSS
VSS
SMRCOMPV
OH
VSS
SMRCOMP
VOL
VSS
SVREF
CL_VREF
VSS
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
SDQS_A0#
SDM_A0
SDQ_A4
SDQ_A5
SRCOMP1
SRCOMP0
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC
VCC
VCC
VSS
VCC_CL
AJ
VCC_CL
VCC_CL
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
AG
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
AF
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC
AH
AE
AD
VCC
CL_CLK
CL_DATA
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
AC
VCC
VCC
EXP_
COMPI
EXP_
COMPO
VSS
DMI_TXN2
DMI_TXP2
VSS
VCC
VSS
VCC_EXP
AA
VCC
VCC
CL_RST#
RSVD
RSVD
RSVD
VSS
DMI_RXP
2
DMI_RXN2
VSS
DMI_RXN3
Y
VCC
VCC
RSVD
VCC
VSS
DMI_RXN1
DMI_RXP1
VSS
VCC
VSS
DMI_TXN1
AB
DMI_TXP1
W
V
VCC
VCC
VCC
VSS
VCC
VCC
VSS
U
VCC
VCC
RSVD
RSVD
VCC
VCC
VSS
VSS
VCC
DMI_TXP0 DMI_TXN0
VSS
EXP_
RXN15
EXP_RXP1
5
VSS
EXP_
RXN14
VSS
VSS
EXP_
TXN15
VCC
VCC_EXP
DMI_RXP3
VSS
VCC
DMI_TXN3
DMI_TXP3
VSS
P
VCC
EXP_RXN1
EXP_RXP13
3
RSVD
RSVD
VSS
N
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VSS
EXP_
TXN12
M
DDC_CLK
VSS
VSS
EXP_RXN10
EXP_RXP1
0
VSS
EXP_
RXN12
EXP_RXP1
2
EXP_RXP1
1
VSS
EXP_
RXN11
L
DDC_DATA
VCC
K
VSS
VSS
J
ICH_SYNC
#
EXP_RXP3
EXP_RXP4
H
VSS
EXP_RXN3
EXP_RXN4
G
VSS
VSS
F
RSVD
E
D
EXP_RXN9
VSS
VCC
VCC
VSS
EXP_TXP9
VSS
VSS
VSS
EXP_RXP8
EXP_RXN8
EXP_TXN8
EXP_RXP2
VCC
VCC
VSS
EXP_RXN2
VSS
VSS
DREFCLKN
EXP_TXN0
EXP_TXP0
EXP_TXN2
VSS
EXP_TXP2
VCC
GCLKP
EXP_TXP1
VSS
EXP_TXP3
DREFCLKP
VCC
VSS
GCLKN
A
RSVD
Datasheet
EXP_RXP9
VSS
C
14
VSS
VSS
B
VSS
13
12
VSS
VCC
EXP_TXP14
EXP_TXN14
VSS
VSS
VSS
VCC
EXP_TXP11
EXP_TXN11
VSS
EXP_TXP10
EXP_TXN9
VSS
VCC
VCC
AM
AL
VCC_CL
AK
AJ
VCC
AH
AG
VSS
AF
AE
VCC_EXP
AD
AC
VSS
AB
AA
VSS
Y
W
DMI_RXN0
V
U
VSS
EXP_TXP13
EXP_TXP12
AP
AN
T
R
EXP_TXN13
P
N
VSS
M
L
EXP_TXN10
K
J
H
EXP_RXP5 EXP_RXN6
EXP_
RXN5
10
EXP_RXP6
EXP_TXN
3
8
7
VCC
VSS
VSS
VSS
EXP_TXN5
EXP_TXP5
EXP_TXN6
VSS
9
EXP_TXP8
EXP_TXP4 EXP_TXN4
EXP_TXN1
11
AU
AR
VSS
DMI_RXP0
EXP_TXP15
EXP_RXP1
4
T
VCC
SDQ_A6
AT
AK
R
AV
VSS
6
5
VCC
VSS
EXP_TXP7
VSS
EXP_TXN7
VSS
EXP_RXN7
EXP_RXP7
EXP_TXP6
VSS
VSS
3
E
D
VSS
NC
C
B
VSS
4
G
F
A
2
1
325
Ballout and Package Information
Table 12-1. GMCH
Ballout Sorted by
Signal Name
Signal Name
326
Table 12-1. GMCH
Ballout Sorted by
Signal Name
Ball
Signal Name
Table 12-1. GMCH
Ballout Sorted by
Signal Name
Ball
Signal Name
Ball
ALLZTEST
K20
EXP_RXN3
H12
EXP_TXN7
E2
BLUE
B20
EXP_RXN4
H11
EXP_TXN8
G4
BLUE#
D20
EXP_RXN5
E7
EXP_TXN9
K3
BSEL0
G20
EXP_RXN6
F6
EXP_TXN10
K1
BSEL1
J20
EXP_RXN7
D2
EXP_TXN11
M2
BSEL2
J18
EXP_RXN8
G5
EXP_TXN12
N4
CL_CLK
AD13
EXP_RXN9
L8
EXP_TXN13
P1
CL_DATA
AD12
EXP_RXN10
M9
EXP_TXN14
T2
CL_PWROK
AM15
EXP_RXN11
L4
EXP_TXN15
U4
CL_RST#
AA12
EXP_RXN12
M6
EXP_TXP0
D11
CL_VREF
AM5
EXP_RXN13
R10
EXP_TXP1
B11
DDC_CLK
M13
EXP_RXN14
R4
EXP_TXP2
C10
DDC_DATA
L13
EXP_RXN15
R7
EXP_TXP3
B9
DMI_RXN0
V1
EXP_RXP0
F15
EXP_TXP4
D7
DMI_RXN1
Y9
EXP_RXP1
K15
EXP_TXP5
B5
DMI_RXN2
AA6
EXP_RXP2
F12
EXP_TXP6
B3
DMI_RXN3
AA4
EXP_RXP3
J12
EXP_TXP7
F2
DMI_RXP0
W2
EXP_RXP4
J11
EXP_TXP8
F4
DMI_RXP1
Y8
EXP_RXP5
F7
EXP_TXP9
J4
DMI_RXP2
AA7
EXP_RXP6
E5
EXP_TXP10
L2
DMI_RXP3
AB3
EXP_RXP7
C2
EXP_TXP11
N2
DMI_TXN0
V6
EXP_RXP8
G6
EXP_TXP12
P3
DMI_TXN1
Y4
EXP_RXP9
L9
EXP_TXP13
R2
DMI_TXN2
AC9
EXP_RXP10
M8
EXP_TXP14
U2
DMI_TXN3
AA2
EXP_RXP11
M4
EXP_TXP15
V3
DMI_TXP0
V7
EXP_RXP12
M5
GCLKN
B13
DMI_TXP1
W4
EXP_RXP13
R9
GCLKP
B12
DMI_TXP2
AC8
EXP_RXP14
T4
GREEN
C19
DMI_TXP3
Y2
EXP_RXP15
R6
GREEN#
D19
DREFCLKN
D13
EXP_SLR
E18
HA3#
J42
DREFCLKP
C14
EXP_TXN0
D12
HA4#
L39
EXP_COMPI
AC12
EXP_TXN1
A10
HA5#
J40
EXP_COMPO
AC11
EXP_TXN2
D9
HA6#
L37
EXP_EN
J17
EXP_TXN3
B7
HA7#
L36
EXP_RXN0
G15
EXP_TXN4
D6
HA8#
K42
EXP_RXN1
J15
EXP_TXN5
B6
HA9#
N32
EXP_RXN2
E12
EXP_TXN6
B4
HA10#
N34
Datasheet
Ballout and Package Information
Table 12-1. GMCH
Ballout Sorted by
Signal Name
Table 12-1. GMCH
Ballout Sorted by
Signal Name
Signal Name
Datasheet
Ball
Signal Name
Table 12-1. GMCH
Ballout Sorted by
Signal Name
Ball
Signal Name
Ball
HA11#
M38
HD3#
N40
HD41#
F29
HA12#
N37
HD4#
R42
HD42#
L27
HA13#
M36
HD5#
M39
HD43#
K27
HA14#
R34
HD6#
N41
HD44#
H26
HA15#
N35
HD7#
N42
HD45#
L26
HA16#
N38
HD8#
L41
HD46#
J26
HA17#
U37
HD9#
J39
HD47#
M26
HA18#
N39
HD10#
L42
HD48#
C33
HA19#
R37
HD11#
J41
HD49#
C35
HA20#
P42
HD12#
K41
HD50#
E41
HA21#
R39
HD13#
G40
HD51#
B41
HA22#
V36
HD14#
F41
HD52#
D42
HA23#
R38
HD15#
F42
HD53#
C40
HA24#
U36
HD16#
C42
HD54#
D35
HA25#
U33
HD17#
D41
HD55#
B40
HA26#
R35
HD18#
F38
HD56#
C38
HA27#
V33
HD19#
G37
HD57#
D37
HA28#
V35
HD20#
E42
HD58#
B33
HA29#
Y34
HD21#
E39
HD59#
D33
HA30#
V42
HD22#
E37
HD60#
C34
HA31#
V38
HD23#
C39
HD61#
B35
HA32#
Y36
HD24#
B39
HD62#
A32
HA33#
Y38
HD25#
G33
HD63#
D32
HA34#
Y39
HD26#
A37
HDBSY#
U40
HA35#
AA37
HD27#
F33
HDEFER#
T43
HACCVREF
B24
HD28#
E35
HDINV0#
M40
HADS#
W40
HD29#
K32
HDINV1#
J33
HADSTB0#
M34
HD30#
H32
HDINV2#
G29
HADSTB1#
U34
HD31#
B34
HDINV3#
E33
HBNR#
W42
HD32#
J31
HDRDY#
W41
HBPRI#
G39
HD33#
F32
HDSTBN0#
M43
HBREQ0#
AA42
HD34#
M31
HDSTBN1#
H33
HCLKN
U32
HD35#
E31
HDSTBN2#
H27
HCLKP
R32
HD36#
K31
HDSTBN3#
D38
HCPURST#
C31
HD37#
G31
HDSTBP0#
L40
HD0#
R40
HD38#
K29
HDSTBP1#
G35
HD1#
P41
HD39#
F31
HDSTBP2#
G27
HD2#
R41
HD40#
J29
HDSTBP3#
B38
327
Ballout and Package Information
Table 12-1. GMCH
Ballout Sorted by
Signal Name
Table 12-1. GMCH
Ballout Sorted by
Signal Name
Signal Name
Signal Name
Ball
HDVREF
D24
RESERVED
H18
HHIT#
U42
RESERVED
K17
HHITM#
Y43
RESERVED
G18
HLOCK#
V41
RESERVED
M18
HRCOMP
D23
RESERVED
L18
HREQ0#
F40
RESERVED
L15
HREQ1#
L35
RESERVED
M20
HREQ2#
L38
RESERVED
N15
HREQ3#
G43
RESERVED
N18
HREQ4#
J37
RESERVED
N17
HRS0#
U41
RESERVED
L17
HRS1#
AA41
RESERVED
Y12
HRS2#
U39
RESERVED
AA9
HSCOMP
C25
RESERVED
AA10
HSCOMP#
D25
RESERVED
HSWING
B25
HSYNC
HTRDY#
ICH_SYNC#
Signal Name
Ball
SBS_A1
AW3
2
SBS_A2
BB21
SBS_B0
AY19
SBS_B1
BA18
SBS_B2
BC12
SCAS_A#
AY35
SCAS_B#
AW2
9
SCKE_A0
BC20
SCKE_A1
AY20
SCKE_A2
AY21
SCKE_A3
BA19
SCKE_B0
AY12
AA11
SCKE_B1
AW1
2
RESERVED
R29
SCKE_B2
BB11
C15
RESERVED
R30
SCKE_B3
BA11
Y40
RESERVED
U30
SCLK_A0
AU31
J13
RESERVED
U31
SCLK_A0#
AR31
NC
BC42
RESERVED
R13
SCLK_A1
AP27
NC
BC2
RESERVED
R12
SCLK_A1#
AN27
NC
BB43
RESERVED
U11
SCLK_A2
AV33
NC
BB1
RESERVED
U12
NC
B43
RESERVED
AA39
SCLK_A2#
AW3
3
NC
B42
RESERVED
AP21
SCLK_A3
AP29
AP31
RESERVED
AW4
2
SCLK_A3#
SCLK_A4
AM26
RESERVED
BB2
SCLK_A4#
AM27
RESERVED
AF32
SCLK_A5
AT33
RESERVED
AG32
SCLK_A5#
AU33
RESERVED
BB19
SCLK_B0
AV31
RESERVED
AM21
RESERVED
AM31
SCLK_B0#
AW3
1
RESERVED
AN32
SCLK_B1
AU27
RESERVED
AN21
SCLK_B1#
AT27
RSTIN#
AM18
SCLK_B2
AV32
SBS_A0
BA33
SCLK_B2#
AT32
SCLK_B3
AU29
NC
NC
NC
328
Ball
Table 12-1. GMCH
Ballout Sorted by
Signal Name
B2
N20
A42
PWROK
AM17
RED
B18
RED#
C18
REFSET
A20
RESERVED
AJ32
RESERVED
V31
RESERVED
AL31
RESERVED
A14
RESERVED
F13
RESERVED
F17
Datasheet
Ballout and Package Information
Table 12-1. GMCH
Ballout Sorted by
Signal Name
Table 12-1. GMCH
Ballout Sorted by
Signal Name
Signal Name
Datasheet
Ball
Signal Name
Table 12-1. GMCH
Ballout Sorted by
Signal Name
Ball
Signal Name
Ball
SCLK_B3#
AR29
SDQ_A07
AV4
SDQ_A44
AN40
SCLK_B4
AV29
SDQ_A08
AY2
SDQ_A45
AN42
AW2
7
SDQ_A09
AY3
SDQ_A46
AL42
SCLK_B4#
SDQ_A10
BB5
SDQ_A47
AL39
SCLK_B5
AN33
SDQ_A11
AY6
SDQ_A48
AJ40
SCLK_B5#
AP32
SDQ_A12
AW2
SDQ_A49
AH43
SCS_A0#
AW3
5
SDQ_A13
AW3
SDQ_A50
AF39
SCS_A1#
BA35
SDQ_A14
BA5
SDQ_A51
AE40
SCS_A2#
BA34
SDQ_A15
BB4
SDQ_A52
AJ42
SCS_A3#
BB38
SDQ_A16
AY7
SDQ_A53
AJ41
SCS_B0#
BB27
SDQ_A17
BC7
SDQ_A54
AF41
SCS_B1#
BB30
AW1
1
SDQ_A55
AF42
SDQ_A18
SCS_B2#
AY27
SDQ_A56
AD40
SDQ_A19
AY11
SCS_B3#
AY31
SDQ_A57
AD43
SDQ_A20
BB6
SDM_A0
AR2
SDQ_A58
AB41
SDQ_A21
BA6
SDM_A1
BA2
SDQ_A59
AA40
SDQ_A22
BA10
SDM_A2
AY9
SDQ_A60
AE42
SDQ_A23
BB10
SDM_A3
AN18
SDQ_A61
AE41
SDQ_A24
AT18
SDM_A4
AU43
SDQ_A62
AC39
SDQ_A25
AR18
SDM_A5
AM43
SDQ_A26
AU21
SDM_A6
AG40
SDM_A7
AC40
SDM_B0
AR7
SDM_B1
AW9
SDM_B2
AW1
3
SDM_B3
AP23
SDM_B4
AU37
SDM_B5
AM37
SDM_B6
AG39
SDM_B7
AD38
SDQ_A0
AR5
SDQ_A1
AR4
SDQ_A02
AV3
SDQ_A03
AV2
SDQ_A04
AP3
SDQ_A05
AP2
SDQ_A06
AU1
SDQ_A27
AT21
SDQ_A28
AP17
SDQ_A29
AN17
SDQ_A30
AP20
SDQ_A31
AV20
SDQ_A32
AV42
SDQ_A33
AU40
SDQ_A34
AP42
SDQ_A35
AN39
SDQ_A36
AV40
SDQ_A37
AV41
SDQ_A38
AR42
SDQ_A39
AP41
SDQ_A40
AN41
SDQ_A41
AM39
SDQ_A42
AK42
SDQ_A43
AK41
SDQ_A63
AB42
SDQ_B0
AN7
SDQ_B1
AN8
SDQ_B2
AW5
SDQ_B3
AW7
SDQ_B4
AN5
SDQ_B5
AN6
SDQ_B6
AN9
SDQ_B7
AU7
SDQ_B8
AT11
SDQ_B9
AU11
SDQ_B10
AP13
SDQ_B11
AR13
SDQ_B12
AR11
SDQ_B13
AU9
SDQ_B14
AV12
SDQ_B15
AU12
SDQ_B16
AU15
SDQ_B17
AV13
329
Ballout and Package Information
Table 12-1. GMCH
Ballout Sorted by
Signal Name
Table 12-1. GMCH
Ballout Sorted by
Signal Name
Signal Name
330
Ball
Signal Name
Table 12-1. GMCH
Ballout Sorted by
Signal Name
Ball
Signal Name
Ball
SDQ_B18
AU17
SDQ_B54
AG33
SDQS_B5#
AL34
SDQ_B19
AT17
SDQ_B55
AF34
SDQS_B6
AG35
SDQ_B20
AU13
SDQ_B56
AD36
SDQS_B6#
AG36
SDQ_B21
AM13
SDQ_B57
AC33
SDQS_B7
AC36
SDQ_B22
AV15
SDQ_B58
AA34
SDQS_B7#
AC37
AW1
7
SDQ_B59
AA36
SDVO_CTRLCLK
E17
SDQ_B23
SDQ_B60
AD34
SDQ_B24
AV24
SDQ_B61
AF38
SDVO_CTRLDAT
A
G17
SDQ_B25
AT23
SDQ_B62
AC34
SMA_A0
BA31
SDQ_B26
AT26
SMA_A1
BB25
SDQ_B27
AP26
SMA_A2
BA26
SDQ_B28
AU23
SMA_A3
BA25
AW2
3
SMA_A4
AY25
SDQ_B29
SMA_A5
BA23
SDQ_B30
AR24
SMA_A6
AY24
SDQ_B31
AN26
SMA_A7
AY23
SDQ_B32
AW3
7
SMA_A8
BB23
SDQ_B33
AV38
SDQS_A3#
AU18
SMA_A9
BA22
SDQ_B34
AN36
SDQS_A4
AR41
SDQ_B35
AN37
SDQS_A4#
AR40
SDQ_B36
AU35
SDQS_A5
AL41
SDQ_B37
AR35
SDQS_A5#
AL40
SDQ_B38
AN35
SDQS_A6
AG42
SDQ_B39
AR37
SDQS_A6#
AG41
SDQ_B40
AM35
SDQS_A7
AC42
SDQ_B41
AM38
SDQS_A7#
AC41
SDQ_B42
AJ34
SDQS_B0
AV6
SDQ_B43
AL38
SDQS_B0#
AU5
SDQ_B44
AR39
SDQS_B1
SDQ_B45
AM34
SDQ_B46
SDQ_B47
SDQ_B63
AA33
SDQS_A0
AU4
SDQS_A0#
AR3
SDQS_A1
BB3
SDQS_A1#
BA4
SDQS_A2
BB9
SDQS_A2#
BA9
SDQS_A3
AT20
SMA_A10
AY33
SMA_A11
BB22
SMA_A12
AW2
1
SMA_A13
AY38
SMA_A14
BA21
SMA_B0
BB17
SMA_B1
AY17
SMA_B2
BA17
SMA_B3
BC16
AR12
SMA_B4
AW1
5
SDQS_B1#
AP12
SMA_B5
BA15
AL37
SDQS_B2
AP15
SMA_B6
BB15
AL32
SDQS_B2#
AR15
SMA_B7
BA14
SDQ_B48
AG38
SDQS_B3
AT24
SMA_B8
AY15
SDQ_B49
AJ38
SDQS_B3#
AU26
SMA_B9
BB14
SDQ_B50
AF35
SDQS_B4
AW3
9
SMA_B10
AW1
8
SDQS_B4#
AU39
SMA_B11
BB13
SDQS_B5
AL35
SMA_B12
BA13
SDQ_B51
AF33
SDQ_B52
AJ37
SDQ_B53
AJ35
Datasheet
Ballout and Package Information
Table 12-1. GMCH
Ballout Sorted by
Signal Name
Table 12-1. GMCH
Ballout Sorted by
Signal Name
Signal Name
Datasheet
Ball
Signal Name
Table 12-1. GMCH
Ballout Sorted by
Signal Name
Ball
Signal Name
Ball
SMA_B13
AY29
VCC
AF26
VCC
Y18
SMA_B14
AY13
VCC
AF25
VCC
Y17
SMRCOMPVOH
AM10
VCC
AF24
VCC
Y15
SMRCOMPVOL
AM8
VCC
AF22
VCC
Y14
SODT_A0
AY37
VCC
AF20
VCC
W27
SODT_A1
BA38
VCC
AF18
VCC
W26
SODT_A2
BB35
VCC
AF17
VCC
W25
SODT_A3
BA39
VCC
AF15
VCC
W23
SODT_B0
BA29
VCC
AF14
VCC
W21
SODT_B1
BA30
VCC
AE27
VCC
W19
SODT_B2
BB29
VCC
AE26
VCC
W18
SODT_B3
BB31
VCC
AE25
VCC
W17
SRAS_A#
BB33
VCC
AE23
VCC
V27
AW2
6
VCC
AE21
VCC
V26
SRAS_B#
VCC
AE19
VCC
V25
SRCOMP0
AN2
VCC
AE17
VCC
V24
SRCOMP1
AN3
VCC
AD27
VCC
V23
SRCOMP2
BB40
VCC
AD26
VCC
V22
SRCOMP3
BA40
VCC
AD18
VCC
V21
SVREF
AM6
VCC
AD17
VCC
V20
SWE_A#
BB34
VCC
AD15
VCC
V19
SWE_B#
BA27
VCC
AD14
VCC
V18
TEST0
BC43
VCC
AC27
VCC
V17
TEST1
BC1
VCC
AC26
VCC
V15
TEST2
A43
VCC
AC17
VCC
V14
VCC
P20
VCC
AC15
VCC
U26
VCC
AC14
VCC
U25
VCC
AB27
VCC
U24
VCC
AB26
VCC
U23
VCC
AB18
VCC
U22
VCC
AB17
VCC
U21
VCC
AA27
VCC
U20
VCC
AA26
VCC
U19
VCC
AA17
VCC
U18
VCC
AA15
VCC
U17
VCC
AA14
VCC
U15
VCC
Y27
VCC
U14
VCC
Y26
VCC
R20
VCC
Y11
VCC
AG25
VCC
AG24
VCC
AG23
VCC
AG22
VCC
AG21
VCC
AG20
VCC
AG19
VCC
AG18
VCC
AG17
VCC
AG15
VCC
AG14
331
Ballout and Package Information
Table 12-1. GMCH
Ballout Sorted by
Signal Name
Table 12-1. GMCH
Ballout Sorted by
Signal Name
Signal Name
332
Ball
Signal Name
Table 12-1. GMCH
Ballout Sorted by
Signal Name
Ball
Signal Name
Ball
VCC
R18
VCC
AC25
VCC
J2
VCC
R17
VCC
AC23
VCC
G2
VCC
R15
VCC
AC21
VCC
F11
VCC
R14
VCC
AC19
VCC
F9
VCC
P15
VCC
AC13
VCC
D4
VCC
P14
VCC
AC6
VCC
C13
VCC
AJ12
VCC
AB24
VCC
C9
VCC
AJ11
VCC
AB22
VCC
L12
VCC
AJ10
VCC
AB20
VCC_CL
AJ26
VCC
AJ9
VCC
AA25
VCC_CL
AJ24
VCC
AJ8
VCC
AA23
VCC_CL
AJ23
VCC
AJ7
VCC
AA21
VCC_CL
AJ21
VCC
AJ6
VCC
AA19
VCC_CL
AJ20
VCC
AJ5
VCC
AA13
VCC_CL
AJ18
VCC
AJ4
VCC
AA3
VCC_CL
AJ17
VCC
AJ3
VCC
Y24
VCC_CL
AJ15
VCC
AJ2
VCC
Y22
VCC_CL
AJ14
VCC
AH4
VCC
Y20
VCC_CL
AA30
VCC
AH2
VCC
Y13
VCC_CL
AA29
VCC
AH1
VCC
Y6
VCC_CL
Y30
VCC
AG13
VCC
V13
VCC_CL
Y29
VCC
AG12
VCC
V12
VCC_CL
V30
VCC
AG11
VCC
V10
VCC_CL
V29
VCC
AG10
VCC
V9
VCC_CL
U29
VCC
AG9
VCC
U13
VCC_CL
U27
VCC
AG8
VCC
U10
VCC_CL
AL12
VCC
AG7
VCC
U9
VCC_CL
AL11
VCC
AG6
VCC
U6
VCC_CL
AL10
VCC
AG5
VCC
U3
VCC_CL
AL9
VCC
AG4
VCC
N12
VCC_CL
AL8
VCC
AG3
VCC
N11
VCC_CL
AL7
VCC
AG2
VCC
N9
VCC_CL
AL6
VCC
AF13
VCC
N8
VCC_CL
AL5
VCC
AF12
VCC
N6
VCC_CL
AL4
VCC
AF11
VCC
N3
VCC_CL
AL3
VCC
AD24
VCC
L6
VCC_CL
AL2
VCC
AD22
VCC
J6
VCC_CL
AK26
VCC
AD20
VCC
J3
VCC_CL
AK24
Datasheet
Ballout and Package Information
Table 12-1. GMCH
Ballout Sorted by
Signal Name
Table 12-1. GMCH
Ballout Sorted by
Signal Name
Signal Name
Datasheet
Ball
Signal Name
Table 12-1. GMCH
Ballout Sorted by
Signal Name
Ball
Signal Name
Ball
VCC_CL
AK23
VCC_CL
AK27
VCCA_EXP
A16
VCC_CL
AK21
VCC_CL
AJ31
VCCA_EXPPLL
B15
VCC_CL
AK20
VCC_CL
AG31
VCCA_HPLL
C23
VCC_CL
AK18
VCC_CL
AF31
VCCA_MPLL
A24
VCC_CL
AK17
VCC_CL
AD32
VCCD_CRT
C21
VCC_CL
AK15
VCC_CL
AC32
VCCDQ_CRT
B21
VCC_CL
AK3
VCC_CL
AA32
VCCSM
BC39
VCC_CL
AK2
VCC_CL
AL29
VCCSM
BC34
VCC_CL
AK1
VCC_CL
AL27
VCCSM
BC30
VCC_CL
AJ13
VCC_CL
AL13
VCCSM
BC26
VCC_CL
AD31
VCC_CL
AK14
VCCSM
BC22
VCC_CL
AC31
VCC_CL_PLL
Y32
VCCSM
BC18
VCC_CL
AA31
VCC_EXP
AD11
VCCSM
BC14
VCC_CL
Y31
VCC_EXP
AD10
VCCSM
BB39
VCC_CL
AJ30
VCC_EXP
AD9
VCCSM
BB37
VCC_CL
AJ29
VCC_EXP
AD8
VCCSM
BB32
VCC_CL
AJ27
VCC_EXP
AD7
VCCSM
BB28
VCC_CL
AG30
VCC_EXP
AD6
VCCSM
BB26
VCC_CL
AG29
VCC_EXP
AD5
VCCSM
BB24
VCC_CL
AG27
VCC_EXP
AD4
VCCSM
BB20
VCC_CL
AG26
VCC_EXP
AD2
VCCSM
BB18
VCC_CL
AF30
VCC_EXP
AD1
VCCSM
BB16
VCC_CL
AF29
VCC_EXP
AC4
VCCSM
BB12
VCC_CL
AF27
VCC_EXP
AC3
VCCSM
AY32
VCC_CL
AD30
VCC_EXP
AC2
VCC_CL
AD29
VCC_EXP
AE4
VCCSM
AW2
4
VCC_CL
AC30
VCC_EXP
AE3
VCC_CL
AC29
VCC_EXP
AE2
VCCSM
AW2
0
VCC_CL
AL26
VCC_SMCLK
BB42
VCCSM
AV26
VCC_CL
AL24
VCC_SMCLK
BA43
VCCSM
AV18
VCC_CL
AL23
VCC_SMCLK
BB41
VSS
D16
VCC_CL
AL21
VCC_SMCLK
BA42
VSS
BC41
VCC_CL
AL20
VCC_SMCLK
AY42
VSS
BC3
VCC_CL
AL18
VCC3_3
B17
VSS
BA1
VCC_CL
AL17
VCCA_DAC
C17
VCC_CL
AL15
VCCA_DAC
B16
VCC_CL
AK30
VCCA_DPLLA
A22
VCC_CL
AK29
VCCA_DPLLB
C22
VSS
AY40
VSS
AF23
VSS
AF21
VSS
AF19
333
Ballout and Package Information
Table 12-1. GMCH
Ballout Sorted by
Signal Name
Table 12-1. GMCH
Ballout Sorted by
Signal Name
Signal Name
334
Ball
Signal Name
Table 12-1. GMCH
Ballout Sorted by
Signal Name
Ball
Signal Name
Ball
VSS
AE24
VSS
AV7
VSS
AN4
VSS
AE22
VSS
AU42
VSS
AM42
VSS
AE20
VSS
AU38
VSS
AM40
VSS
AE18
VSS
AU32
VSS
AM36
VSS
AC18
VSS
AU24
VSS
AM33
VSS
AA18
VSS
AU20
VSS
AM29
VSS
W24
VSS
AU6
VSS
AM24
VSS
W22
VSS
AU2
VSS
AM23
VSS
W20
VSS
AT31
VSS
AM20
VSS
R21
VSS
AT29
VSS
AM11
VSS
E1
VSS
AT15
VSS
AM9
VSS
C43
VSS
AT13
VSS
AM7
VSS
C1
VSS
AT12
VSS
AM4
VSS
A41
VSS
AR38
VSS
AM2
VSS
A5
VSS
AR33
VSS
AM1
VSS
A3
VSS
AR32
VSS
AL36
VSS
BC37
VSS
AR27
VSS
AL33
VSS
BC32
VSS
AR26
VSS
AK43
VSS
BC28
VSS
AR23
VSS
AJ39
VSS
BC24
VSS
AR21
VSS
AJ36
VSS
BC10
VSS
AR20
VSS
AJ33
VSS
BC5
VSS
AR17
VSS
AH42
VSS
BB7
VSS
AR9
VSS
AG37
VSS
AY41
VSS
AR6
VSS
AG34
VSS
AY4
VSS
AP43
VSS
AF43
VSS
AP24
VSS
AF37
VSS
AW4
3
VSS
AP18
VSS
AF36
VSS
AW4
1
VSS
AP1
VSS
AF10
VSS
AW1
VSS
AN38
VSS
AF9
VSS
AV37
VSS
AN31
VSS
AF8
VSS
AV35
VSS
AN29
VSS
AF7
VSS
AV27
VSS
AN24
VSS
AF6
VSS
AV23
VSS
AN23
VSS
AF5
VSS
AV21
VSS
AN20
VSS
AF3
VSS
AV17
VSS
AN15
VSS
AF2
VSS
AV11
VSS
AN13
VSS
AF1
VSS
AV9
VSS
AN12
VSS
AD42
VSS
AN11
VSS
AD39
Datasheet
Ballout and Package Information
Table 12-1. GMCH
Ballout Sorted by
Signal Name
Table 12-1. GMCH
Ballout Sorted by
Signal Name
Signal Name
Datasheet
Ball
Signal Name
Table 12-1. GMCH
Ballout Sorted by
Signal Name
Ball
Signal Name
Ball
VSS
AD37
VSS
Y7
VSS
N13
VSS
AD35
VSS
Y5
VSS
N10
VSS
AD33
VSS
Y1
VSS
N7
VSS
AD25
VSS
W3
VSS
N5
VSS
AD23
VSS
V43
VSS
M42
VSS
AD21
VSS
V39
VSS
M37
VSS
AD19
VSS
V37
VSS
M35
VSS
AC38
VSS
V34
VSS
M33
VSS
AC35
VSS
V32
VSS
M27
VSS
AC24
VSS
V11
VSS
M21
VSS
AC22
VSS
V8
VSS
M17
VSS
AC20
VSS
V5
VSS
M15
VSS
AC10
VSS
V2
VSS
M10
VSS
AC7
VSS
U38
VSS
M7
VSS
AC5
VSS
U35
VSS
M1
VSS
AB43
VSS
U8
VSS
L33
VSS
AB25
VSS
U7
VSS
L32
VSS
AB23
VSS
U5
VSS
L31
VSS
AB21
VSS
T42
VSS
L29
VSS
AB19
VSS
T1
VSS
L21
VSS
AB2
VSS
R36
VSS
L20
VSS
AB1
VSS
R33
VSS
L11
VSS
AA38
VSS
R31
VSS
L7
VSS
AA35
VSS
R11
VSS
L5
VSS
AA24
VSS
R8
VSS
L3
VSS
AA22
VSS
R5
VSS
K43
VSS
AA20
VSS
R3
VSS
K26
VSS
AA8
VSS
P43
VSS
K21
VSS
AA5
VSS
P30
VSS
K18
VSS
Y42
VSS
P21
VSS
K13
VSS
Y37
VSS
P18
VSS
K12
VSS
Y35
VSS
P17
VSS
K2
VSS
Y33
VSS
P2
VSS
J38
VSS
Y25
VSS
N36
VSS
J35
VSS
Y23
VSS
N33
VSS
J32
VSS
Y21
VSS
N31
VSS
J27
VSS
Y19
VSS
N27
VSS
J21
VSS
Y10
VSS
N21
VSS
J9
335
Ballout and Package Information
Table 12-1. GMCH
Ballout Sorted by
Signal Name
Table 12-1. GMCH
Ballout Sorted by
Signal Name
Signal Name
336
Ball
Signal Name
Table 12-1. GMCH
Ballout Sorted by
Signal Name
Ball
Signal Name
Ball
VSS
J7
VSS
D21
VTT
N23
VSS
J5
VSS
D17
VTT
M29
VSS
H31
VSS
D3
VTT
M24
VSS
H29
VSS
C26
VTT
M23
VSS
H21
VSS
C11
VTT
L24
VSS
H20
VSS
C6
VTT
L23
VSS
H17
VSS
C5
VTT
K24
VSS
H15
VSS
C4
VTT
K23
VSS
H13
VSS
B37
VTT
J24
VSS
G42
VSS
B32
VTT
J23
VSS
G38
VSS
B31
VTT
H24
VSS
G32
VSS
B26
VTT
H23
VSS
G21
VSS
B23
VTT
G26
VSS
G13
VSS
B22
VTT
G24
VSS
G12
VSS
B19
VTT
G23
VSS
G11
VSS
B14
VTT
F26
VSS
G9
VSS
B10
VTT
F24
VSS
G7
VSS
A39
VTT
F23
VSS
G1
VSS
A34
VTT
E29
VSS
F37
VSS
A26
VTT
E27
VSS
F35
VSS
A18
VTT
E26
VSS
F27
VSS
A12
VTT
E23
VSS
F21
VSS
A7
VTT
D29
VSS
F18
VSS
M11
VTT
D28
VSS
F3
VSYNC
D15
VTT
D27
VSS
E43
VTT
R27
VTT
C30
VSS
E32
VTT
R26
VTT
C29
VSS
E24
VTT
R24
VTT
C27
VSS
E21
VTT
R23
VTT
B30
VSS
E20
VTT
P29
VTT
B29
VSS
E15
VTT
P27
VTT
B28
VSS
E13
VTT
P26
VTT
B27
VSS
E11
VTT
P24
VTT
A30
VSS
E9
VTT
P23
VTT
A28
VSS
E3
VTT
N29
XORTEST
F20
VSS
D40
VTT
N26
VSS
D31
VTT
N24
Datasheet
12.2
Package
The GMCH package measures 34 mm × 34 mm. The 1226 balls are located in a nongrid pattern. Figure 12-4 shows the GMCH package dimensions. Refer to the Intel®
G35 Express Chipset Thermal and Mechanical Design Guidelines for further
information.
Document Number: 317607-001
Ballout and Package Information
Figure 12-4. GMCH Package Drawing
338
Datasheet
Testability
13
Testability
In the GMCH, testability for Automated Test Equipment (ATE) board level testing has
been implemented as an XOR chain. An XOR-tree is a chain of XOR gates each with
one input pin connected to it which allows for pad to ball to trace connection testing.
The XOR testing methodology is to boot the part using straps to enter XOR mode (A
description of the boot process follows). Once in XOR mode, all of the pins of an XOR
chain are driven to logic 1. This action will force the output of that XOR chain to either
a 1 if the number of the pins making up the chain is even and a 0 if the number of the
pins making up the chain is odd.
Once a valid output is detected on the XOR chain output, a walking 0 pattern is moved
from one end of the chain to the other. Every time the walking 0 is applied to a pin on
the chain, the output will toggle. If the output does not toggle, there is a disconnect
somewhere between die, package, and board and the system can be considered a
failure.
Datasheet
339
Testability
13.1
XOR Test Mode Initialization
Figure 13-1. XOR Test Mode Initialization Cycles
The above figure shows the wave forms to be able to boot the part into XOR mode.
The straps that need to be controlled during this boot process are BSEL[2:0],
SDVO_CTRLDATA, EXP_EM, EXP_SLR, and XORTEST.
On G35 platforms, all strap values must be driven before PWROK asserts. BSEL0 must
be a 1. BSEL[2:1] need to be defined values, but logic value in any order will do.
XORTEST must be driven to 0.
If sDVO is present in the design, SDVO_CTRLDATA must be pulled to logic 1.
Depending on if Static Lane Reversal is used and if the sDVO/PCIe Coexistence is
selected, EXP_SLR and EXP_EN must be pulled in a valid manner.
Because of the different functionalities of the sDVO/PCIe interface, not all of the pins
will be used in all implementations. Due to the need to minimize test points and
unnecessary routing, the XOR Chain 14 is dynamic depending on the values of
SDVO_CTRLDATA, EXP_SLR, and EXP_EN. Please see the below table for what parts of
XOR Chain 14 become valid XOR inputs depending on the use of SDVO_CTRLDATA,
EXP_SLR, and EXP_EN.
340
Datasheet
Testability
Table 137-1. XOR Chain 14 Functionality
SDVO_CTRLDATA
0
0
1
1
EXP_SLR
XOR Chain 14
0
EXP_RXP[15:0]
EXP_RXN[15:0]
EXP_TXP[15:0]
EXP_TXN[15:0]
1
EXP_RXP[15:0]
EXP_RXN[15:0]
EXP_TXP[15:0]
EXP_TXN[15:0]
1
0
0
EXP_RXP[15:8]
EXP_RXN[15:8]
EXP_TXP[15:8]
EXP_TXN[15:8]
1
0
1
EXP_RXP[7:0]
EXP_RXN[7:0]
EXP_TXP[7:0]
EXP_TXN[7:0]
0
EXP_RXP[15:0]
EXP_RXN[15:0]
EXP_TXP[15:0]
EXP_TXN[15:0]
1
EXP_RXP[15:0]
EXP_RXN[15:0]
EXP_TXP[15:0]
EXP_TXN[15:0]
1
1
Datasheet
EXP_EN
1
1
341
Testability
13.2
XOR Chain Definition
The GMCH chipset has 15 XOR chains. The XOR chain outputs are driven out on the
following output pins. During fullwidth testing, XOR chain outputs will be visible on
both pins.
Table 13-1. XOR Chain Outputs
342
XOR Chain
Output Pins
Coordinate Location
xor_out0
ALLZTEST
K20
xor_out1
XORTEST
F20
xor_out2
ICH_SYNC#
J13
xor_out3
RSV
F17
xor_out4
RSV
AA9
xor_out5
RSV
AA10
xor_out6
BSEL1
J20
xor_out7
BSEL2
J18
xor_out8
RSV
AA11
xor_out9
RSV
Y12
xor_out10
EXP_SLR
E18
xor_out11
EXP_EN
J17
xor_out12
MTYPE
G18
xor_out13
RSV
K17
xor_out14
BSEL0
G20
Datasheet
Testability
13.3
XOR Chains
Table 13-2 through Table Table 13-7 show the XOR chains. Section 0Table 13-17
has a pin exclusion list.
Table 13-2. XOR Chain 0
Datasheet
Table 13-2. XOR Chain 0
Pin
Count
Ball
#
Signal Name
Pin
Count
Ball
#
Signal Name
1
C35
HD49
34
F31
HD39
2
D42
HD52
35
F29
HD41
3
B35
HD61
36
J26
HD46
4
B33
HD58
37
E31
HD35
5
D37
HD57
38
H26
HD44
6
A32
HD62
39
K27
HD43
7
C33
HD48
40
J31
HD32
8
D32
HD63
41
F32
HD33
9
B40
HD55
42
L26
HD45
10
D35
HD54
43
J29
HD40
11
C38
HD56
44
K31
HD36
12
C34
HD60
45
M31
HD34
13
B41
HD51
46
K29
HD38
14
E41
HD50
47
G31
HD37
15
D33
HD59
48
M26
HD47
16
C40
HD53
49
J41
HD11
17
B34
HD31
50
F42
HD15
18
C42
HD16
51
G40
HD13
19
E39
HD21
52
L42
HD10
20
E35
HD28
53
F41
HD14
21
D41
HD17
54
N42
HD7
22
C39
HD23
55
K41
HD12
23
F33
HD27
56
N41
HD6
24
E37
HD22
57
J39
HD9
25
G33
HD25
58
M39
HD5
26
F38
HD18
59
N40
HD3
27
B39
HD24
60
L41
HD8
28
G37
HD19
61
P41
HD1
29
K32
HD29
62
R40
HD0
30
H32
HD30
63
R41
HD2
31
E42
HD20
64
R42
HD4
32
A37
HD26
33
L27
HD42
343
Testability
Table 13-3. XOR Chain 1
Pin
Count
Ball #
Signal Name
1
G43
HREQ4#
2
F40
HREQ0#
3
J42
HA3#
4
L36
HA7#
5
L37
HA6#
6
L35
HREQ1#
7
N32
HA9#
8
N35
9
M36
10
HA13#
HA5#
11
M34
12
M38
HA11#
13
N37
HA12#
14
G43
HADSTB0#
HREQ3#
15
K42
HA8#
16
N38
HA16#
17
L39
HA4#
18
L38
19
N34
HA10#
20
R34
HA14#
21
R39
HA21#
22
N39
HA18#
23
V38
HA31#
24
Y36
HA32#
25
R42
26
27
HREQ2#
38
Y39
HA34#
39
V33
HA27#
40
Y34
HA29#
Table 13-4. XOR Chain 2
Pin
Count
Ball #
Signal Name
1
H33
HDSTBN1#
2
G35
HDSTBP1#
3
AA41
HRS1#
4
U42
HHIT#
5
Y40
HTRDY#
6
Y43
HHITM#
7
H27
HDSTBN2#
8
G27
HDSTBP2#
9
M43
HDSTBN0#
10
L40
HDSTBP0#
11
W42
HBNR#
12
G39
HBPRI#
13
V41
HLOCK#
14
C31
HCPURST#
Table 13-5. XOR Chain 3
Pin
Count
Ball #
Signal Name
HA20#
1
D38
HDSTBN3#
V35
HA28#
2
B38
HDSTBP3#
R38
HA23#
3
E33
HDINV3#
J33
HDINV1#
T43
HDEFER#
28
U33
HA25#
4
29
R37
HA19#
5
30
R35
HA26#
6
U41
HRS0#
HADSTB1#
7
W41
HDRDY#
HA33#
8
U40
HDBSY#
HA30#
9
U39
HRS2#
HA24#
10
G29
HDINV2#
HA22#
11
M40
HDINV0#
HA17#
12
W40
HADS#
HA35#
13
F40
HBREQ0#
31
U34
32
Y38
33
V42
34
U36
35
V36
36
U37
37
344
J40
HA15#
Table 13-3. XOR Chain 1
AA37
Datasheet
Testability
Table 13-6. XOR Chain 4
Datasheet
Table 13-7. XOR Chain 5
Pin
Count
Ball #
Signal Name
1
AC41
SDQS_A7#
2
AC40
SDM_A7
3
AG41
SDQS_A6#
SODT_A0
4
AG40
AW35
SDM_A6
SCS_A0#
5
AL40
5
BA31
SDQS_A5#
SMA_A0
6
AM43
6
AY33
SDM_A5
SMA_A10
7
AR40
7
AY25
SDQS_A4#
SMA_A4
8
AU43
8
BB25
SDM_A4
SMA_A1
9
AY38
9
BA26
SMA_A13
SMA_A2
10
AY35
10
BA25
SCAS_A#
SMA_A3
11
BB33
11
AV33
SRAS_A#
SCLK_A2
12
BA33
12
AW33
SBS_A0
SCLK_A2#
13
BB34
13
AU31
SWE_A#
SCLK_A0
14
AW32
14
AR31
SBS_A1
SCLK_A0#
15
BB22
15
AN27
SMA_A11
SCLK_A1#
16
BA21
16
AP27
SMA_A14
SCLK_A1
17
BB21
17
BA23
SBS_A2
SMA_A5
18
AW21
18
BA22
SMA_A12
SMA_A9
19
AD12
19
BB23
CL_DATA
SMA_A8
20
AD13
20
AY24
CL_CLK
SMA_A6
21
BC20
SCKE_A0
22
AY23
SMA_A7
23
AY20
SCKE_A1
24
AU18
SDQS_A3#
25
AN18
26
Pin
Count
Ball #
Signal Name
1
BA38
SODT_A1
2
BA35
SCS_A1#
3
AY37
4
Table 13-8. XOR Chain 6
Pin
Count
Ball #
Signal Name
SDM_A3
1
AC42
SDQS_A7
BA9
SDQS_A2#
2
AD43
SDQ_A57
27
AY9
SDM_A2
3
AB42
SDQ_A63
28
BA4
SDQS_A1#
4
AE41
SDQ_A61
29
BA2
SDM_A1
5
AE42
SDQ_A60
30
AR3
SDQS_A0#
6
AD40
SDQ_A56
31
AR2
SDM_A0
7
AC39
SDQ_A62
8
AB41
SDQ_A58
9
AA40
SDQ_A59
10
AG42
SDQS_A6
11
AF41
SDQ_A54
12
AE40
SDQ_A51
345
Testability
Table 13-8. XOR Chain 6
346
Table 13-8. XOR Chain 6
Pin
Count
Ball #
Signal Name
Pin
Count
Ball #
Signal Name
13
AJ42
SDQ_A52
50
BB10
SDQ_A23
14
AJ41
SDQ_A53
51
AW11
SDQ_A18
15
AF39
SDQ_A50
52
BA6
SDQ_A21
16
AJ40
SDQ_A48
53
BB6
SDQ_A20
17
AF42
SDQ_A55
54
AY7
SDQ_A16
18
AH43
SDQ_A49
55
BB3
SDQS_A1
19
AL41
SDQS_A5
56
BA5
SDQ_A14
20
AN40
SDQ_A44
57
AW2
SDQ_A12
21
AK41
SDQ_A43
58
BB5
SDQ_A10
22
AM39
SDQ_A41
59
BB4
SDQ_A15
23
AL39
SDQ_A47
60
AY6
SDQ_A11
24
AN41
SDQ_A40
61
AY3
SDQ_A9
25
AL42
SDQ_A46
62
AY2
SDQ_A8
26
AN42
SDQ_A45
63
AW3
SDQ_A13
27
AK42
SDQ_A42
64
AU4
SDQS_A0
28
AR41
SDQS_A4
65
AV4
SDQ_A7
29
AV42
SDQ_A32
66
AP2
SDQ_A5
30
AP42
SDQ_A34
67
AP3
SDQ_A4
31
AR42
SDQ_A38
68
AR4
SDQ_A1
32
AV41
SDQ_A37
69
AR5
SDQ_A0
33
AU40
SDQ_A33
70
AU1
SDQ_A6
34
AN39
SDQ_A35
71
AV2
SDQ_A3
35
AP41
SDQ_A39
72
AV3
SDQ_A2
36
AV40
SDQ_A36
37
AT20
SDQS_A3
38
AV20
SDQ_A31
39
AU21
SDQ_A26
40
AT18
SDQ_A24
41
AR18
SDQ_A25
42
AT21
SDQ_A27
43
AN17
SDQ_A29
44
AP20
SDQ_A30
45
AP17
SDQ_A28
46
BB9
SDQS_A2
47
AY11
SDQ_A19
48
BA10
SDQ_A22
49
BC7
SDQ_A17
Datasheet
Testability
Table 13-9. XOR Chain 7
Table 13-10. XOR Chain 8
Pin
Count
Ball #
Signal Name
Pin
Count
Ball #
Signal Name
1
BA39
SODT_A3
21
AY15
SMA_B8
2
BB38
SCS_A3#
22
BB15
SMA_B6
3
BB35
SODT_A2
23
BA14
SMA_B7
4
BA34
SCS_A2#
24
AW12
SCKE_B1
5
AP29
SCLK_A3
25
AY12
SCKE_B0
6
AP31
SCLK_A3#
26
AR15
SDQS_B2#
7
AU33
SCLK_A5#
27
AW13
SDM_B2
8
AT33
SCLK_A5
28
AP12
SDQS_B1#
9
AM26
SCLK_A4
29
AW9
SDM_B1
10
AM27
SCLK_A4#
30
AU5
SDQS_B0#
11
AY21
SCKE_A2
31
AR7
SDM_B0
12
BA19
SCKE_A3
Table 13-11. XOR Chain 9
Table 13-10. XOR Chain 8
Datasheet
Pin
Count
Ball #
Signal Name
Signal Name
1
AC37
SDQS_B7#
BB30
SCS_B1#
2
AD38
SDM_B7
2
BA30
SODT_B1
3
AG36
SDQS_B6#
3
BA29
SODT_B0
4
AG39
SDM_B6
4
BB27
SCS_B0#
5
AL34
SDQS_B5#
5
AV32
SCLK_B2
6
AM37
SDM_B5
6
AT32
SCLK_B2#
7
AU39
SDQS_B4#
7
AV31
SCLK_B0
8
AU37
SDM_B4
8
AW31
SCLK_B0#
9
AY29
SMA_B13
9
AU27
SCLK_B1
10
AW29
SCAS_B#
10
AT27
SCLK_B1#
11
BA27
SWE_B#
11
AW18
SMA_B10
12
AW26
SRAS_B#
12
BB17
SMA_B0
13
BA18
SBS_B1
13
AU26
SDQS_B3#
14
AY19
SBS_B0
14
AP23
SDM_B3
15
BB13
SMA_B11
15
BC16
SMA_B3
16
BC12
SBS_B2
16
BA15
SMA_B5
17
BA13
SMA_B12
17
AY17
SMA_B1
18
AY13
SMA_B14
18
BA17
SMA_B2
19
AW15
SMA_B4
20
BB14
SMA_B9
Pin
Count
Ball #
1
347
Testability
348
Table 13-12. XOR Chain 10
Table 13-12. XOR Chain 10
Pin
Count
Ball #
Signal Name
Pin
Count
Ball #
Signal Name
1
AC36
SDQS_B7
38
AP26
SDQ_B27
2
AF38
SDQ_B61
39
AW23
SDQ_B29
3
AD36
SDQ_B56
40
AR24
SDQ_B30
4
AA36
SDQ_B59
41
AV24
SDQ_B24
5
AA33
SDQ_B63
42
AT23
SDQ_B25
6
AD34
SDQ_B60
43
AT26
SDQ_B26
7
AC34
SDQ_B62
44
AN26
SDQ_B31
8
AC33
SDQ_B57
45
AU23
SDQ_B28
9
AA34
SDQ_B58
46
AP15
SDQS_B2
10
AG35
SDQS_B6
47
AU17
SDQ_B18
11
AJ37
SDQ_B52
48
AW17
SDQ_B23
12
AJ38
SDQ_B49
49
AV15
SDQ_B22
13
AG38
SDQ_B48
50
AT17
SDQ_B19
14
AF34
SDQ_B55
51
AU15
SDQ_B16
15
AF33
SDQ_B51
52
AM13
SDQ_B21
16
AG33
SDQ_B54
53
AV13
SDQ_B17
17
AF35
SDQ_B50
54
AU13
SDQ_B20
18
AJ35
SDQ_B53
55
AR12
SDQS_B1
19
AL35
SDQS_B5
56
AP13
SDQ_B10
20
AL38
SDQ_B43
57
AU12
SDQ_B15
21
AL32
SDQ_B47
58
AV12
SDQ_B14
22
AR39
SDQ_B44
59
AR13
SDQ_B11
23
AJ34
SDQ_B42
60
AU11
SDQ_B9
24
AM38
SDQ_B41
61
AT11
SDQ_B8
25
AM35
SDQ_B40
62
AU9
SDQ_B13
26
AL37
SDQ_B46
63
AR11
SDQ_B12
27
AM34
SDQ_B45
64
AV6
SDQS_B0
28
AW39
SDQS_B4
65
AN6
SDQ_B5
29
AN37
SDQ_B35
66
AN8
SDQ_B1
30
AR37
SDQ_B39
67
AU7
SDQ_B7
31
AW37
SDQ_B32
68
AN9
SDQ_B6
32
AN36
SDQ_B34
69
AN7
SDQ_B0
33
AV38
SDQ_B33
70
AW5
SDQ_B2
34
AR35
SDQ_B37
71
AW7
SDQ_B3
35
AN35
SDQ_B38
72
AN5
SDQ_B4
36
AU35
SDQ_B36
37
AT24
SDQS_B3
Datasheet
Testability
Table 13-13. XOR Chain 11
Pin
Count
Ball #
Signal Name
Pin
Count
Ball #
Signal Name
1
AY31
SCS_B3#
13
V6
DMI_TXN0
2
BB31
SODT_B3
14
V7
DMI_TXP0
3
AY27
SCS_B2#
15
V1
DMI_RXN0
4
BB29
SODT_B2
16
W2
DMI_RXP0
5
AV29
SCLK_B4
6
AP32
SCLK_B5#
7
AN33
SCLK_B5
8
AW27
SCLK_B4#
9
AR29
SCLK_B3#
10
ZU29
11
BA11
12
BB11
Table 13-16. XOR Chain 14
Pin
Count
Ball #
Signal Name
SCLK_B3
1
U4
EXP_TXN15
SCKE_B3
2
V3
EXP_TXP15
SCKE_B2
3
R7
EXP_RXN15
4
R6
EXP_RXP15
5
T2
EXP_TXN14
6
U2
EXP_TXP14
7
R4
EXP_RXN14
8
T4
EXP_RXP14
9
P1
EXP_TXN13
10
R2
EXP_TXP13
EXP_RXN13
Table 13-14. XOR Chain 12
Pin
Count
Ball #
Signal Name
1
G17
SDVO_CTRLDATA
2
E17
3
L13
DDC_DATA
11
R10
4
M13
DDC_CLK
12
R9
EXP_RXP13
13
N4
EXP_TXN12
14
P3
EXP_TXP12
15
M6
EXP_RXN12
16
M5
EXP_RXP12
EXP_TXN11
SDVO_CTRLCLK
Table 13-15. XOR Chain 13
Datasheet
Table 13-15. XOR Chain 13
Pin
Count
Ball #
Signal Name
1
AA2
17
M2
DMI_TXN3
2
Y2
18
N2
EXP_TXP11
DMI_TXP3
L4
3
AA4
19
EXP_RXN11
DMI_RXN3
AB3
20
M4
4
EXP_RXP11
DMI_RXP3
5
AC9
21
K1
EXP_TXN10
DMI_TXN2
L2
6
AC8
22
EXP_TXP10
DMI_TXP2
7
AA6
23
M9
EXP_RXN10
DMI_RXN2
8
AA7
24
M8
EXP_RXP10
DMI_RXP2
K3
9
Y4
25
EXP_TXN9
DMI_TXN1
W4
26
J4
10
EXP_TXP9
DMI_TXP1
11
Y9
27
L8
EXP_RXN9
DMI_RXN1
L9
12
Y8
28
EXP_RXP9
DMI_RXP1
349
Testability
Table 13-16. XOR Chain 14
350
Table 13-16. XOR Chain 14
Pin
Count
Ball #
Signal Name
Pin
Count
Ball #
Signal Name
29
G4
EXP_TXN8
47
H11
EXP_RXN4
30
F4
EXP_TXP8
48
J11
EXP_RXP4
31
G5
49
B7
EXP_TXN3
32
G6
EXP_RXP8
50
B9
EXP_TXP3
33
E2
EXP_TXN7
51
H12
EXP_RXN3
34
F2
EXP_TXP7
52
J12
EXP_RXP3
35
D2
EXP_RXN7
53
D9
EXP_TXN2
36
C2
EXP_RXP7
54
C10
EXP_TXP2
37
B4
55
E12
EXP_RXN2
38
B3
EXP_TXP6
56
F12
EXP_RXP2
39
F6
EXP_RXN6
57
A10
EXP_TXN1
40
E5
58
B11
EXP_TXP1
41
B6
EXP_TXN5
59
J15
EXP_RXN1
42
B5
EXP_TXP5
60
K15
EXP_RXP1
43
E7
EXP_RXN5
61
D12
EXP_TXN0
44
F7
EXP_RXP5
62
D11
EXP_TXP0
45
D6
EXP_TXN4
63
G15
EXP_RXN0
46
D7
EXP_TXP4
64
F15
EXP_RXP0
EXP_RXN8
EXP_TXN6
EXP_RXP6
Datasheet
Testability
13.4
PADs Excluded from XOR Mode(s)
A large number of pads do not support XOR testing. The majority of the pads that fall
into this category are analog related pins (see Table 13-17).
Table 13-17. XOR Pad Exclusion List
PCI Express*
FSB
SM
Miscellaneous
GCLKN
HCLKN
SRCOMP[3 :0]
RED
GCLKP
HCLKP
SVREF
RED#
EXP_COMPO
HRCOMP
SMRCOMPVOL
GREEN
EXP_COMPI
HSCOMP
SMRCOMPVOH
GREEN#
HSCOMP#
BLUE
HSWING
BLUE#
HDVREF
DREFCLKN
HACCVREF
DREFCLKP
REFSET
HSYNC
VSYNC
DREFCLKN
DREFCLKP
TEST[2 :0]
CL_DATA
CL_CLK
CL_VREF
§
Datasheet
351