S72WS-P based MCP/PoP Products 1.8 Volt-only x16 Flash Memory and SDRAM on Split Bus Simultaneous Read/Write, Burst Mode NOR Flash NAND Flash or NAND Interface ORNAND™ Flash on Bus 1 Mobile SDRAM on Bus 2 S72WS-P based MCP/PoP Products Cover Sheet Data Sheet (Advance Information) Notice to Readers: This document states the current technical specifications regarding the Spansion product(s) described herein. Each product described herein may be designated as Advance Information, Preliminary, or Full Production. See Notice On Data Sheet Designations for definitions. Publication Number S72WS-P_00 Revision A Amendment 4 Issue Date May 29, 2006 Da ta Sh eet ( A dvan ce In fo r mat io n) Notice On Data Sheet Designations Spansion LLC issues data sheets with Advance Information or Preliminary designations to advise readers of product information or intended specifications throughout the product life cycle, including development, qualification, initial production, and full production. In all cases, however, readers are encouraged to verify that they have the latest information before finalizing their design. The following descriptions of Spansion data sheet designations are presented here to highlight their presence and definitions. Advance Information The Advance Information designation indicates that Spansion LLC is developing one or more specific products, but has not committed any design to production. Information presented in a document with this designation is likely to change, and in some cases, development on the product may discontinue. Spansion LLC therefore places the following conditions upon Advance Information content: “This document contains information on one or more products under development at Spansion LLC. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed product without notice.” Preliminary The Preliminary designation indicates that the product development has progressed such that a commitment to production has taken place. This designation covers several aspects of the product life cycle, including product qualification, initial production, and the subsequent phases in the manufacturing process that occur before full production is achieved. Changes to the technical specifications presented in a Preliminary document should be expected while keeping these aspects of production under consideration. Spansion places the following conditions upon Preliminary content: “This document states the current technical specifications regarding the Spansion product(s) described herein. The Preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. Due to the phases of the manufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications.” Combination Some data sheets contain a combination of products with different designations (Advance Information, Preliminary, or Full Production). This type of document distinguishes these products and their designations wherever necessary, typically on the first page, the ordering information page, and pages with the DC Characteristics table and the AC Erase and Program table (in the table notes). The disclaimer on the first page refers the reader to the notice on this page. Full Production (No Designation on Document) When a product has been in production for a period of time such that no changes or only nominal changes are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include those affecting the number of ordering part numbers available, such as the addition or deletion of a speed option, temperature range, package type, or VIO range. Changes may also include those needed to clarify a description or to correct a typographical error or incorrect specification. Spansion LLC applies the following conditions to documents in this category: “This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion LLC deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid combinations offered may occur.” Questions regarding these document designations may be directed to your local AMD or Fujitsu sales office. ii S72WS-P based MCP/PoP Products S72WS-P_00_A4 May 29, 2006 S72WS-P based MCP/PoP Products 1.8 Volt-only x16 Flash Memory and SDRAM on Split Bus Simultaneous Read/Write, Burst Mode NOR Flash NAND Flash or NAND Interface ORNAND™ Flash on Bus 1 Mobile SDRAM on Bus 2 Data Sheet (Advance Information) Features Power supply voltage of 1.7 to 1.95V Package: Flash access time: 80 ns for NOR Flash, 25 ns for ORNAND Flash 9.0 x 12.0 mm MCP Flash burst frequencies: 66 MHz, 80 MHz, 108 MHz 15.0 x 15.0 mm Package-on-Package (PoP) Mobile SDRAM burst frequency: 104 MHz (SDR), 133 MHz (DDR) Operating Temperature 11.0 x 13.0 mm MCP –25°C to +85°C (wireless) The S72WS series is a product line of stacked packages and consists of: One or two NOR flash memory die One NAND Interface ORNAND die Separate bus for one or more Mobile SDRAM die The products covered by this document are listed in the table below. NOR Flash Density 512Mb Device 256Mb S72WS256PD0 (MCP) X S72WS256PD0 (POP) X S72WS512PE0 (MCP) X S72WS512PEF (POP) X S72WS512PEF (POP) X 128Mb ORNAND™ Flash Density 1024Mb 512Mb NAND Flash Density 512Mb DRAM Density 512Mb 256Mb 128Mb X (DDR) X (DDR) X (SDR) X X (SDR) X X (SDR) S72WS512PFF (MCP) X X X (DDR) S72WS512PFF (POP) X X X (DDR) S72WS512PFF (MCP) X X X (DDR) S72WS512PFF (POP) X X X (DDR) S72WS512PFG (MCP) X X X (DDR) S72WS512PFG (POP) X X X (DDR) Note: For a full list of OPNs, please contact the local sales representative or refer to the Ordering Information valid combinations tables. For detailed specifications, please refer to the individual data sheets. Document Publication Identification Number (PID) S29WS-P S29WS-P_00 S30MS-P S30MS-P_00 128 Mb Mobile DDR-DRAM Type 5 SDRAM_07 256 Mb Mobile SDR-DRAM Type 2 SDRAM_05 512 Mb Mobile DDR-DRAM Type 1 SDRAM_09 512 Mb Mobile SDR-DRAM Type 4 SDRAM_06 512 Mb NAND Type 1 NAND_01 512 Mb Mobile DDR-DRAM Type 5 DRAM_04 Publication Number S72WS-P_00 Revision A Amendment 4 Issue Date May 29, 2006 This document contains information on one or more products under development at Spansion LLC. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed product without notice. Da ta 1. 1.1 Sh eet ( A dvan ce In fo r mat io n) Product Selector Guide NOR Flash + DRAM Products Device NOR Flash Density NOR Flash Speed DRAM Density DRAM Speed DRAM Supplier PoP 15 x 15 mm S72WS256PD0KFKLG 256 Mb 66 MHz 128 Mb 133 MHz (DDR) Type 5 MCP 9 x 12 mm S72WS256PD0HF6LG S72WS512PE0HF61R 1.2 Package 512 Mb 80 MHz 256 Mb 104 MHz (SDR) MCP 9 x 12 mm Type 2 NOR Flash + ORNAND Flash + DRAM Products Device-Model# NOR Flash Density NOR Flash Speed ORNAND Flash Density ORNAND Bus Width ECC Required S72WS512PEFKFKHH DRAM Density DRAM Speed 256 Mb S72WS512PFFKFKGH DRAM Supplier Type 2 PoP 15 x 15 mm 160-ball PoP 15 x 15 mm 160-ball 512Mb S72WS512PFFJF9GH Package 66 MHz x16 MCP 11 x 13 mm 137-ball Yes Type 1 S72WS512PFGJF9GH MCP 11 x 13 mm 137-ball 133 MHz (DDR) 512 Mb 1024 Mb 512 Mb S72WS512PFGKFKGH PoP 15 x 15 mm 160-ball S72WS512PFFJF9LD MCP 11 x 13 mm 137-ball 80 MHz 512 Mb x16 Yes Type 5 PoP 15 x 15 mm 160-ball S72WS512PFFKFKLD 1.3 NOR Flash + NAND Flash + DRAM Products Device-Model# NOR Flash Density NOR Flash Speed NAND Flash Density NAND Bus Width ECC Required S72WS512PEFKFKHJ DRAM Density DRAM Speed 256 Mb S72WS512PFFKFKGJ DRAM Supplier Type 2 Package PoP 15 x 15 mm 160-ball PoP 15 x 15 mm 160-ball 66 MHz Type 1 S72WS512PFFJF9GJ 512Mb 512Mb x16 MCP 11 x 13 mm 137ball 133 MHz (DDR) Yes 512 Mb PoP 15 x 15 mm 160-ball S72WS512PFFKFKLE 80 MHz 2 Type 5 MCP 11 x 13 mm 137-ball S72WS512PFFJF9LE S72WS-P based MCP/PoP Products S72WS-P_00_A4 May 29, 2006 Da t a Sh ee t (A d va nce I nfo r ma ti on ) 2. MCP Block Diagram 2.1 NOR Flash + DRAM Products A0-Amax F-RDY F-CLK F-ADV# A0-Amax CLK ADV# F-CE# CE# F-OE# OE# F-RST# F-ACC F-WP# WP# F-WE# WE# S72WS-P_00_A4 May 29, 2006 WS-P NOR Flash Memory RESET# ACC D-RAS# D-CAS# D-BA0 D-BA1 D-CKE D-WE# D-CE# D-A0 - D-Amax D-VCC D-VCCQ DQ0-DQ15 RDY RAS# CAS# BA0 BA1 CKE WE# CE# A0-Amax VCC VCCQ DDR DRAM MEMORY S72WS-P based MCP/PoP Products F-DQ15 - F-DQ0 VSS VSSQ F-VSS F-VSS Q VCC VCCQ F-VCC F-VCC Q CLK CLK# DQS0 DQS1 LDQM UDQM D-CLK D-CLK# D-D QS0 D-D QS1 D-DM0 D-DM1 DQ15-DQ0 VSS VSSQ D-DQ15 - D-DQ0 D-VSS D-VSSQ 3 Da ta 2.2 Sh eet ( A dvan ce In fo r mat io n) NOR Flash + (OR)NAND Flash + DRAM Products A0-A24 F-RDY F-CLK F-AVD# F-CE# F-OE# F-RST# F-ACC F-WP# F-WE# A0-A24 RDY CLK AVD# CE# OE# RESET# ACC WP# WE# DQ0-DQ15 WS512P NOR Flash Memory DQ0-DQ15 VSS VSSQ F-VSS F-VSSQ VCC VCCQ F-VCC F-VCCQ I/O0-I/O15 N-RY/BY# RB# N-CLE N-CE# N-ALE N-PRE N-RE# N-WP# N-WE# CLE CE# ALE PRE RE# WP# WE# D-RAS# D-CAS# D-BA0 D-BA1 D-CKE D-WE# D-CE# D-A0 - D-A12 D-VCC D-VCCQ RAS# CAS# BA0 BA1 CKE WE# CE# A0-A12 VCC VCCQ MS512P x16 ORNAND Flash Memory 512Mb DDR DRAM MEMORY VSS N-VSS VCC N-VCC CLK CLK# DQS0 DQS1 LDQM UDQM DQ15-DQ0 VSS VSSQ D-CLK D-CLK# D-D QS0 D-D QS1 D-DM0 D-DM1 D-DQ15 - D-DQ0 D-VSS D-VSSQ Note 1. For MCPs, VSS is shared between all Flash (NOR and ORNAND). Also, VSSQ is tied to VSS internally within the MCP. 4 S72WS-P based MCP/PoP Products S72WS-P_00_A4 May 29, 2006 Da t a Sh ee t (A d va nce I nfo r ma ti on ) 3. Connection Diagrams 3.1 256Mb NOR Flash with 128Mb SDR/DDR-DRAM 137-ball Fine-Pitch Ball Grid Array (Top View, Balls Facing Down) A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 D-CKE D-CLK D-CLK# RFU D-VSS D-VCC RFU D-A11 D-VSS D-CE# B1 B2 D-RAS# D-WE# B3 B4 B5 B6 B7 B8 B9 B10 D-A9 D-A8 D-VSSQ D-VCCQ D-A7 D-A6 RFU D-CAS# C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 D-A10 AVD# VSS CLK RFU RFU RFU RFU RFU RFU D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D-A0 F-WP# A7 D-DM0 F-ACC WE# A8 A11 RFU D-A5 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 D-VCCQ A3 A6 D-DM1 F-RST# RFU A19 A12 A15 D-VCCQ F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 D-VSSQ A2 A5 A18 F-RDY A20 A9 A13 A21 D-VSSQ G1 G2 G3 G4 G6 G7 G8 G9 G10 D-DQ0 A1 A4 A17 A23 A10 A14 A22 D-DQ15 H1 H2 H3 H4 H7 H8 H9 H10 D-DQ1 A0 VSS DQ1 DQ6 RFU A16 D-DQ14 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 OE# DQ9 DQ3 DQ4 DQ13 DQ15 RFU D-DQ13 D-DQ2 F1-CE# K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 D-DQ3 RFU DQ0 DQ10 F-VCC RFU DQ12 DQ7 VSS D-DQ12 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 D-DQ4 RFU DQ8 DQ2 DQ11 RFU DQ5 DQ14 RFU D-DQ11 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 D-DQ5 RFU RFU VSS F-VCC RFU RFU F-VCCQ RFU D-DQ10 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 RFU D-BA0 D-DQ6 D-DQ7 D-VSSQ D-VCCQ D-DQ8 D-DQ9 D-BA1 RFU P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 D-A1 D-A2 D-VSS D-VCC D-A3 D-A4 RFU D-DQS1 D-DQS0 D-VSS Legend NOR Flash only DRAM only Reserved for Future Use DDR DRAM only Note: DDR-only signals are RFUs in the case of the SDR DRAM-based solutions. S72WS-P_00_A4 May 29, 2006 S72WS-P based MCP/PoP Products 5 Da ta 3.2 Sh eet ( A dvan ce In fo r mat io n) 512Mb NOR Flash with 512-Mb (OR)NAND on Bus 1 and 512-Mb DRAM on Bus 2 137-ball Fine-Pitch Ball Grid Array (Top View, Balls Facing Down) A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 D-CKE D-CLK D-CLK# RFU D-VSS D-VCC D-A12 D-A11 D-VSS D-CE# B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 D-RAS# D-WE# D-A9 D-A8 D-VSSQ D-VCCQ D-A7 D-A6 RFU D-CAS# Legend C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 D-A10 F-AVD# VSS F-CLK RFU F-VCC N-PRE N-ALE N-CLE RFU D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D-A0 F-WP# A7 D-DM0 F-ACC F-WE# A8 A11 N-CE# D-A5 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 D-VCCQ A3 A6 D-DM1 F-RST# DNU A19 A12 A15 D-VCCQ Reserved for Future Use Do Not Use F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 D-VSSQ A2 A5 A18 F-RDY A20 A9 A13 A21 D-VSSQ G1 G2 G3 G4 G6 G7 G8 G9 G10 D-DQ0 A1 A4 A17 A23 A10 A14 A22 D-DQ15 H1 H2 H3 H4 H7 H8 H9 H10 D-DQ1 A0 VSS DQ1 DQ6 A24 A16 D-DQ14 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 D-DQ2 F1-CE# F-OE# DQ9 DQ3 DQ4 DQ13 DQ15 DNU D-DQ13 NOR Flash Only ORNAND Flash Only 6 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 D-DQ3 DNU DQ0 DQ10 F-VCC N-VCC DQ12 DQ7 VSS D-DQ12 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 D-DQ4 N-VCC DQ8 DQ2 DQ11 RFU DQ5 DQ14 N-WP# D-DQ11 DRAM Only All Flash Shared M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 D-DQ5 RFU RFU VSS F-VCC RFU DNU F-VCCQ DNU D-DQ10 N5 N6 N1 N2 N3 N4 N-WE# D-BA0 D-DQ6 D-DQ7 D-VSSQ D-VCCQ N7 N8 N9 N10 D-DQ8 D-DQ9 D-BA1 N-RE# P9 P9 P10 P1 P2 P3 P4 P5 P6 P7 P8 D-DQS0 D-VSS D-A1 D-A2 D-VSS D-VCC D-A3 D-A4 S72WS-P based MCP/PoP Products N-RY/BY# D-DQS1 S72WS-P_00_A4 May 29, 2006 Da t a 3.2.0.1 Sh ee t (A d va nce I nfo r ma ti on ) Special Handling Instructions For FBGA Package Special handling is required for Flash Memory products in FBGA packages. Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150×C for prolonged periods of time. 3.2.1 Package-on-Package Connection Diagram 160-ball Fine Pitch Ball Grid Array (Top View, Balls Facing Down) 19 20 21 22 F-A23 RFU RFU N-V SS NC F-A22 F-A24 N-V CC F-V CCQ F-V SSQ N-RY/ BY# F-RST# RFU D-DQ1 D-DQ0 F1-CE# F2-CE# E D-V SSQ D-V DDQ N1-CE# RFU F D-DQ3 D-DQ2 N-RE# N-WP# G D-DQ5 D-DQ4 F-WE# F-WP# H D-V SSQ D-V DDQ D-WE# F-OE# J D-DQ7 D-DQ6 D-V DD D-V SS K D-DM0 D-DQS0 D-A0 D-A1 L D-DM1 D-DQS1 D-A2 D-A3 M D-V SSQ D-V DDQ D-A4 D-A5 N D-DQ9 D-DQ8 D-A6 D-A7 P D-V SS D-V DD D-BA0 D-BA1 R D-DQ11 D-DQ10 D1-CS# RFU T D-DQ13 D-DQ12 D-RAS# D-CAS# U D-V SSQ D-V DDQ D-A8 D-A9 V D-DQ15 D-DQ14 D-A10 D-A11 W D-CKE D-CLK D-A12 RFU Y RFU D-CLK# F-ACC D-V SS AA RFU F-V SS F-V CC F-DQ0/ N-ADQ0 F-V CCQ F-DQ2/ N-ADQ2 F-DQ4/ N-ADQ4 F-V CCQ F-DQ6/ N-ADQ6 RFU F-CLK N-V CC RFU F-DQ8/ N-ADQ8 F-V CCQ F-DQ10/ N-ADQ10 F-DQ12/ N-ADQ12 F-V CCQ F-DQ14/ N-ADQ14 F-ADV# D-V DD RFU AB NC D-V DD N-PRE F-DQ1/ N-ADQ1 F-V SSQ F-DQ3/ N-ADQ3 F-DQ5/ N-ADQ5 F-V SSQ F-DQ7/ N-ADQ7 RFU RFU N-V SS RFU F-DQ9/ N-ADQ9 F-V SSQ F-DQ11/ N-ADQ11 F-DQ13/ N-ADQ13 F-V SSQ F-DQ15/ N-ADQ15 F-WAIT F-V CCQ NC 1 2 3 4 5 6 7 8 9 NC D-V SS F-A1 F-V SS F-A3 F-A5 F-A7 F-A9 F-V SSQ D-V SS D-V DD F-A0 F-V CC F-A2 F-A4 F-A6 F-A8 F-V CCQ C N-WE# D A B 10 11 12 13 14 15 16 17 N-CLE F-A11 F-A13 F-A15 F-A17 F-V SSQ F-A19 F-A21 N-ALE F-A10 F-A12 F-A14 F-A16 F-V CCQ F-A18 F-A20 18 Legend NOR Flash Only Reserved for Future Use DDR DRAM Only 3.2.2 ORNAND Flash Only Flash Shared Only No Connect Look-ahead Ballout for Future Designs Please refer to the Design-in Scalable Wireless Solutions with Spansion Products application note (publication number: Design_Scalable_Wireless_A0_E). Contact your local Spansion sales representative for more details. S72WS-P_00_A4 May 29, 2006 S72WS-P based MCP/PoP Products 7 Da ta 3.3 8 ( A dvan ce In fo r mat io n) NOR Flash and DRAM Input/Output Descriptions Amax-A0 3.3.1 Sh eet = NOR Flash Address inputs DQ15-DQ0 = Flash Data input/output, shared between NOR and ORNAND Flash. DQ0-DQ7 shared for x8 ORNAND F-CE# = NOR Flash Chip-enable input #1. Asynchronous relative to CLK for Burst Mode. F-OE# = NOR Flash Output Enable input. Asynchronous relative to CLK for Burst mode. F-WE# = NOR Flash Write Enable input. F-VCC = NOR Flash device power supply (1.7 V - 1.95V). F-VCCQ = Input/Output Buffer power supply. VSS = Ground RFU = Reserved for Future Use F-RDY = Flash ready output. Indicates the status of the Burst read. VOL = data valid. F-CLK = NOR Flash Clock. The first rising edge of CLK in conjunction with AVD# low latches the address input and activates burst mode operation. After the initial word is output, subsequent rising edges of CLK increment the internal address counter. CLK should remain low during asynchronous access. F-AVD# = NOR Flash Address Valid input. Indicates to device that the valid address is present on the address inputs. VIL = for asynchronous mode, indicates valid address; for burst mode, causes starting address to be latched on rising edge of CLK. VIH= device ignores address inputs F-RST# = NOR Flash hardware reset input. VIL= device resets and returns to reading array data F-WP# = NOR Flash hardware write protect input. VIL = disables program and erase functions in the four outermost sectors. F-ACC = NOR Flash accelerated input. At VHH, accelerates programming; automatically places device in unlock bypass mode. At VIL, disables all program and erase functions. Should be at VIH for all other conditions. D-Amax-D-A0 = SDRAM Address inputs D-DQ15-D-DQ0 = SDRAM Data input/output D-CLK = SDRAM System Clock D-CE# = SDRAM Chip Select SDRAM Clock Enable D-CKE = D-BA1-BA0 = SDRAM Bank Select D-RAS# = SDRAM Row Address Strobe D-CAS# = SDRAM Column Address Strobe D-DM1-D-DM0 = SDRAM Data Input/Output Mask D-WE# = SDRAM Write Enable input D-VSS = SDRAM Ground D-CLK# = DDR SDRAM Clock - in addition to D-CLK, this signal is available for DDRAMs that need CLK# for normal operations D-VSSQ = SDRAM Input/Output Buffer ground D-VCCQ = SDRAM Input/Output Buffer power supply D-VCC = SDRAM device power supply D-DQS0 - DDQS1 = DDR SDRAM Data Strobe pins. DQS provides the read data strobes (as output) and the write data strobes (as input). Each DQS pin corresponds to eight DQ pins, respectively. ORNAND Signal Descriptions N-PRE = N-ALE = ORNAND Power-On Read Enable. Tie to VSS on customer board if not used ORNAND Address Latch Enable N-CLE N-CE# = = ORNAND Command Latch Enable ORNAND Chip-enablE N-WP# N-WE# = = ORNAND Write-protect ORNAND Write-enable N-RE# N-RY/BY# = = ORNAND Read-enable ORNAND Ready-Busy N-I/O0-N-I/O15 N-VCC = = ORNAND I/O Signals (I/O0-I/O7 for x8 bus width) ORNAND Power Supply S72WS-P based MCP/PoP Products S72WS-P_00_A4 May 29, 2006 Da t a Sh ee t (A d va nce I nfo r ma ti on ) 4. Ordering Information The order number is formed by a valid combinations of the following: S72WS 512 P D0 HF 0 L G 0 PACKING TYPE 0 = Tray 2 = 7” Tape and Reel 3 = 13” Tape and Reel MODEL NUMBER 2 G = 66MHz/133MHz Speed, No Data Flash H = 66MHz/133MHz Speed, Spansion MS-P as Data Flash J = 66MHz/133MHz Speed, NAND Type 1 as Data Flash R = 80MHz/104MHz Speed, No Data Flash D = 80MHz/133MHz Speed, Spansion MS-P as Data Flash E = 80MHz/133MHz Speed, NAND Type 1 as Data Flash MODEL NUMBER 1 L = x16 DDR DRAM Type 5 G = x16 DDR DRAM Type 1 H = x16 DDR DRAM Type 2 1 = x16 SDR DRAM Type 2 PACKAGE DESCRIPTOR Depends on Character 12. For a more detailed description see Table 4.1. PACKAGE TYPE & MATERIAL SET HF = 1.2mm MCP FBGA, Pb-free KF = 1.2mm POP FBGA, Pb-free JF = 1.4mm MCP FBGA, Pb-free DRAM & ORNAND FLASH DENSITY D0 = 128 Mb DRAM, No Data Flash EF = 256Mb DRAM, 512Mb NAND Flash FF = 512Mb DRAM, 512Mb NAND Flash E0 = 256Mb DRAM, No Data Flash PROCESS TECHNOLOGY P = 90 nm, MirrorBitTM Technology CODE FLASH DENSITY 256 = 256Mb 512 = 512Mb PRODUCT FAMILY S72WS Stacked Products (MCP/PoP) 1.8 V NOR Flash and ORNAND Flash on Bus 1 with Mobile DRAM on Bus 2 Table 4.1 Character Position Descriptions (Sheet 1 of 2) Character 14 Description Character 12 Character 13 Package Area Package Ball Count 0 7x9 mm 56 1 7x9 mm 80 2 8x11.6 mm 64 3 8x11.6 mm 84 4 9x12 mm 84 5 9x12 mm 115 6 9x12 mm 137 7 11x13 mm 84 8 11x13 mm 115 9 11x13 mm 137 H, J, or G S72WS-P_00_A4 May 29, 2006 Raw Ball Size 0.35 mm S72WS-P based MCP/PoP Products 9 Da ta Sh eet ( A dvan ce In fo r mat io n) Table 4.1 Character Position Descriptions (Sheet 2 of 2) Character 14 Description Character 12 Character 13 Package Area Package Ball Count Raw Ball Size A 11x11 mm 112 0.45 mm B 11x11 mm 112 0.50 mm D 12x12 mm 128 0.45 mm F 12x12 mm 128 0.50 mm G 14x14 mm 152 0.45 mm H 14x14 mm 152 0.50 mm J 15x15 mm 160 0.45 mm K 4.1 K 15x15 mm 160 0.50 mm L 17x17 mm 192 0.45 mm M 17x17 mm 192 0.50 mm Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. S72WS-P Valid Combinations Base Ordering Number Package & Material Set Package Descriptor KF K HF 6 S72WS512PE0 HF 6 80 MHz Type 2 104 MHz 9x12 mm (MCP) S72WS512PEF KF K 66 MHz Type 2 133 MHz 15x15 mm (PoP) HF 6 66 MHz Type 1 66 MHz Type 1 80 MHz Type 5 Packing Type 66 MHz JF KF DRAM Supplier DRAM Speed Type 5 133 MHz 0, 2, 3 (Note 1) 66 MHz Type 1 80 MHz Type 5 15x15 mm (PoP) 133 MHz KF K (Note 2) 11x13 mm (MCP) 15x15 mm (PoP) K 9 Package Markings 9x12 mm (MCP) 9 JF Package Type 15x15 mm (PoP) S72WS256PD0 S72WS512PFF NOR Flash Speed 11x13 mm (MCP) S72WS512PFG 66 MHz Type 1 133 MHz 15x15 mm (PoP) Notes: 1. Packing Type 0 is standard. Specify other options as required. 2. BGA package marking omits leading S and packing type designator from ordering part number. 10 S72WS-P based MCP/PoP Products S72WS-P_00_A4 May 29, 2006 Da t a Sh ee t (A d va nce I nfo r ma ti on ) 5. Physical Dimensions 5.1 TLD137—137-ball Fine-Pitch Ball Grid Array (FBGA) 12 x 9 mm Package D1 A D eD 0.15 C (2X) 10 9 SE 7 8 7 6 E E1 5 4 eE 3 2 1 P N M L K J INDEX MARK PIN A1 CORNER B 10 TOP VIEW H G F E D C B A 7 SD 0.15 C PIN A1 CORNER (2X) BOTTOM VIEW 0.20 C A A2 A1 C 137X 0.08 C SIDE VIEW 6 b 0.15 M C A B 0.08 M C NOTES: PACKAGE TLD 137 JEDEC N/A DxE 12.00 mm x 9.00 mm PACKAGE SYMBOL MIN NOM MAX A --- --- 1.20 A1 0.17 --- --- A2 0.81 --- 0.97 NOTE PROFILE BODY SIZE E 9.00 BSC. BODY SIZE D1 10.40 BSC. MATRIX FOOTPRINT E1 7.20 BSC. MATRIX FOOTPRINT MD 14 MATRIX SIZE D DIRECTION ME 10 MATRIX SIZE E DIRECTION 137 0.35 0.40 2. ALL DIMENSIONS ARE IN MILLIMETERS. 3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010. 4. e REPRESENTS THE SOLDER BALL GRID PITCH. 5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. BODY THICKNESS 12.00 BSC. n DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. BALL HEIGHT D φb 1. n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. 6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. 7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. BALL COUNT 0.45 WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. BALL DIAMETER eE 0.80 BSC. BALL PITCH eD 0.80 BSC BALL PITCH SD / SE 0.40 BSC. SOLDER BALL PLACEMENT G5,H5,H6 DEPOPULATED SOLDER BALLS WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. 9. N/A 10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. 3393\ 16-038.22a S72WS-P_00_A4 May 29, 2006 S72WS-P based MCP/PoP Products 11 Da ta 5.2 Sh eet ( A dvan ce In fo r mat io n) FVD137—137-ball Fine-Pitch Ball Grid Array (FBGA) 13 x 11 mm Package A D D1 eD 0.15 C (2X) 10 9 8 7 6 E eE SE 7 E1 5 4 3 2 1 P PIN A1 CORNER 9 B INDEX MARK L K J H G F E D C B A PIN A1 CORNER 7 SD 0.15 C TOP VIEW N M (2X) BOTTOM VIEW 0.20 C A A2 A1 137X C SIDE VIEW 6 0.08 C b 0.15 M C A B 0.08 M C NOTES: PACKAGE FVD 137 JEDEC N/A DxE 13.00 mm x 11.00 mm PACKAGE SYMBOL NOTE MIN NOM MAX A --- --- 1.40 A1 0.10 --- --- A2 1.09 --- 1.24 e REPRESENTS THE SOLDER BALL GRID PITCH. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. BODY THICKNESS BODY SIZE BODY SIZE D1 10.40 BSC. MATRIX FOOTPRINT E1 7.20 BSC. MD 14 MATRIX SIZE D DIRECTION ME 10 MATRIX SIZE E DIRECTION eE MATRIX FOOTPRINT 137 BALL POSITION DESIGNATION PER JEP95, SECTION 4.3, SPP-010. 5. 11.00 BSC. 0.40 ALL DIMENSIONS ARE IN MILLIMETERS. 3. 4. E 0.35 2. PROFILE 13.00 BSC. n DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. BALL HEIGHT D Øb 1. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. 6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. 7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. BALL COUNT 0.45 WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. BALL DIAMETER 0.80 BSC. BALL PITCH eD 0.80 BSC BALL PITCH SD SE 0.40 BSC. SOLDER BALL PLACEMENT G5,H5,H6 DEPOPULATED SOLDER BALLS WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. 9 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. 3522 \ 16-038.21 \ 09.29.05 12 S72WS-P based MCP/PoP Products S72WS-P_00_A4 May 29, 2006 Da t a 5.3 Sh ee t (A d va nce I nfo r ma ti on ) BWB160—160-ball Fine-Pitch Ball Grid Array (FBGA) 15 x 15 mm Package A D PIN A1 CORNER D1 9 INDEX MARK PIN A1 CORNER eD A B C D E F G H J K L M N P R T U V W Y AA AB E eE 0.10 C 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 (2X) B TOP VIEW SD 2 SE 7 E1 1 7 0.10 C BOTTOM VIEW (2X) 0.20 C A A2 A1 C 0.10 C SIDE VIEW 6 b 160X 0.15 0.08 M C A B M C NOTES: PACKAGE BWB 160 JEDEC N/A DxE 15.00 mm x 15.00 mm PACKAGE SYMBOL MIN NOM MAX A --- --- 1.30 A1 0.40 --- --- A2 0.74 --- 0.84 D 15.00 BSC. NOTE PROFILE BODY SIZE 13.65 BSC. MATRIX FOOTPRINT E1 13.65 BSC. MATRIX FOOTPRINT MD 22 MATRIX SIZE D DIRECTION ME 22 MATRIX SIZE E DIRECTION n 160 BALL COUNT N 160 MAXIMUM NUMBER OF BALLS 2 eE 0.50 4. e REPRESENTS THE SOLDER BALL GRID PITCH. 5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. 6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. 7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 NUMBER OF LAND PARAMETERS 0.55 BALL DIAMETER 0.65 BSC. 8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. 9 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. BALL PITCH eD 0.65 BSC. BALL PITCH SD / SE 0.325 BSC. SOLDER BALL PLACEMENT ? BALL POSITION DESIGNATION PER JEP95, SECTION 4.3, SPP-010. BODY SIZE 15.00 BSC. 0.45 ALL DIMENSIONS ARE IN MILLIMETERS. 3. BALL HEIGHT E R DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. 2. BODY THICKNESS D1 Øb 1. C3~C20,D3~D20,E3~E20,F3~F20 G3~G20,H3~H20,J3~J20,K3~K20 L3~L20,M3~M20,N3~N20,P3~P20 R3~R20,T3~T20,U3~U20,V3~V20 W3~W20,Y3~Y20 DEPOPULATED SOLDER BALLS 10. OUTLINE AND DIMENSIONS PER CUSTOMER REQUIREMENT. 3523 \ 16-038.46 \ 02.23.06 S72WS-P_00_A4 May 29, 2006 S72WS-P based MCP/PoP Products 13 Da ta 5.4 Sh eet ( A dvan ce In fo r mat io n) BTA160—160-ball Fine-Pitch Ball Grid Array (FBGA) 15 x 15 mm Package A D PIN A1 CORNER D1 9 INDEX MARK PIN A1 CORNER eD A B C D E F G H J K L M N P R T U V W Y AA AB E eE 0.10 C 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 (2X) B TOP VIEW SD 2 SE 7 E1 1 7 0.10 C BOTTOM VIEW (2X) 0.20 C A A2 A1 C 160X 0.10 C SIDE VIEW 6 b 0.15 M 0.08 M C A B C NOTES: PACKAGE BTA 160 JEDEC N/A DxE 15.00 mm x 15.00 mm PACKAGE NOTE SYMBOL MIN NOM MAX A --- --- 1.30 A1 0.40 --- --- A2 0.74 --- 0.84 PROFILE BODY SIZE E 15.00 BSC. BODY SIZE D1 13.65 BSC. MATRIX FOOTPRINT E1 13.65 BSC. MATRIX FOOTPRINT MD 22 MATRIX SIZE D DIRECTION ME 22 MATRIX SIZE E DIRECTION n 160 BALL COUNT N 160 MAXIMUM NUMBER OF BALLS eE 2 0.45 0.50 2. ALL DIMENSIONS ARE IN MILLIMETERS. 3. BALL POSITION DESIGNATION PER JEP95, SECTION 4.3, SPP-010. 4. e REPRESENTS THE SOLDER BALL GRID PITCH. 5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. BODY THICKNESS 15.00 BSC. R DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. BALL HEIGHT D Øb 1. n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. 6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. 7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 NUMBER OF LAND PARAMETERS 0.55 BALL DIAMETER 0.65 BSC. BALL PITCH eD 0.65 BSC. BALL PITCH SD SE 0.325 BSC. SOLDER BALL PLACEMENT C3~C20,D3~D20,E3~E20,F3~F20 G3~G20,H3~H20,J3~J20,K3~K20 L3~L20,M3~M20,N3~N20,P3~P20 R3~R20,T3~T20,U3~U20,V3~V20 W3~W20,Y3~Y20 DEPOPULATED SOLDER BALLS 8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. 9 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. 10. OUTLINE AND DIMENSIONS PER CUSTOMER REQUIREMENT. 3550 \ 16-038.55 \ 02.23.06 14 S72WS-P based MCP/PoP Products S72WS-P_00_A4 May 29, 2006 Da t a 6. Sh ee t (A d va nce I nfo r ma ti on ) Revision History 6.1 Revision A1 (February 23, 2006) Initial release. 6.2 Revision A2 (March 29, 2006) Modified Block Diagram for Section 2.1 and Section 2.2 2. Updated PoP Connection Diagram in Section 3.2.2 3. Updated Section 3.3 to append F-RDY and N-RY/BY# as separate signals 6.3 Revision A3 (April 11, 2006) Added a note to the NOR Flash + (OR)NAND Flash + DRAM Products block diagram Updated pin M8 on the 256Mb NOR Flash with 128Mb SDR/DDR-DRAM connection diagram 6.4 Revision A4 (May 29, 2006) Added OPNs for products based on DRAM Type 5 Updated Product Selector Guide Updated Ordering Information Updated Valid Combinations Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products. Trademarks and Notice The contents of this document are subject to change without notice. This document may contain information on a Spansion product under development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any damages of any kind arising out of the use of the information in this document. Copyright © 2006 Spansion LLC. All Rights Reserved. Spansion, the Spansion logo, MirrorBit, ORNAND, HD-SIM, and combinations thereof are trademarks of Spansion LLC. Other names are for informational purposes only and may be trademarks of their respective owners. S72WS-P_00_A4 May 29, 2006 S72WS-P based MCP/PoP Products 15