SUMMIT S93662/S93663 MICROELECTRONICS, Inc. Precision Supply-Voltage Monitor and Reset Controller FEATURES • Precision Monitor & RESET Controller — RESET and RESET Outputs — Guaranteed RESET Assertion to VCC = 1V — 200ms Reset Pulse Width — Internal 1.26V Reference with ±1% Accuracy — ZERO External Components Required • Memory — 4K-bit Microwire Memory — S93662 – Internally Ties ORG Low – 100% Compatible With all 8-bit Implementations – Sixteen Byte Page Write Capability — S93663 – Internally Ties ORG High – 100% Compatible With all 16-bit Implementations – Eight Word Page Write Capability OVERVIEW The S93662 and S93663 are precision power supervisory circuits providing both active high and active low reset outputs. Both devices have 4k-bits of E2PROM memory that is accessible via the industry standard microwire bus. The S93662 is configured with an internal ORG pin tied low providing a 8-bit byte organization and the S93663 is configured with an internal ORG pin tied high providing a 16-bit word organization. Both the S93662 and S93663 have page write capability. The devices are designed for a minimum 100,000 program/erase cycles and have data retention in excess of 100 years. BLOCK DIAGRAM VCC 8 RESET PULSE GENERATOR 5kHz OSCILLATOR + VTRIP 2 DI 3 MODE DECODE ADDRESS DECODER RESET WRITE CONTROL E2PROM MEMORY ARRAY DATA I/O DO 7 1.26V 1 SK RESET# RESET CONTROL – CS 6 4 5 2012 T BD 2.0 GND SUMMIT MICROELECTRONICS, Inc. • 300 Orchard City Drive, Suite 131 © SUMMIT MICROELECTRONICS, Inc. 2000 2012 2.0 4/18/00 • Campbell, CA 95008 1 • Telephone 408-378-6461 • Fax 408-378-6586 • www.summitmicro.com Characteristics subject to change without notice S93662/S93663 PIN CONFIGURATION ing VTRIP. The reset outputs will be valid so long as VCC is ≥1.0V. During power-down, the reset outputs will begin driving active when VCC falls below VTRIP. 8-Pin PDIP or 8-Pin SOIC CS SK DI DO 1 2 3 4 8 7 6 5 The reset pins are I/Os; therefore, the S93662/663 can act as a stabilization circuit for an externally applied reset. The inputs are edge triggered; that is, the RESET input will initiate a reset time-out after detecting a low to high transition and the RESET# input will initiate a reset time-out after detecting a high to low transition. Refer to the applications Information section for more details on device operation as a debounce/reset extender circuit. VCC RESET RESET# GND It should be noted the reset outputs are open drain. When used as outputs driving a circuit they need to be either tied high (RESET#) or tied to ground (RESET) through the use of pull-up or pull-down resistors. Refer to the applications aid section for help in determining the value of resistor to be used. Internally these pins are weakly pulled up (RESET#) and pulled down (RESET): therefore, if the signals are not being used the pins may be left unconnected. 2012 T PCon 2.0 PIN FUNCTIONS Pin Name Function CS Chip Select SK Clock Input DI Serial Data Input DO Serial Data Output VCC +2.7 to 6.0V Power Supply GND Ground RESET/RESET# RESET I/O GENERAL OPERATION The S93662/663 is a 4096-bit nonvolatile memory intended for use with industry standard microprocessors. The S93663 is organized as X16, seven 11-bit instructions control the reading, writing and erase operations of the device. The S93662 is organized as X8, seven 12bit instructions control the reading, writing and erase operations of the device. The device operates on a single 3V or 5V supply and will generate on chip, the high voltage required during any write operation. DEVICE OPERATION Instructions, addresses, and write data are clocked into the DI pin on the rising edge of the clock (SK). The DO pin is normally in a high impedance state except when reading data from the device, or when checking the ready/busy status after a write operation. APPLICATIONS The S93662/663 is ideal for applications requiring low voltage and low power consumption. This device provides microcontroller RESET control and can be manually resettable. The ready/busy status can be determined after the start of a write operation by selecting the device (CS high) and polling the DO pin; DO low indicates that the write operation is not completed, while DO high indicates that the device is ready for the next instruction. See the Applications Aid section for detailed use of the ready busy status. RESET CONTROLLER DESCRIPTION The S93662/663 provides a precision reset controller that ensures correct system operation during brownout and power-up/-down conditions. It is configured with two open drain reset outputs; pin 7 is an active high output and pin 6 is an active low output. The format for all instructions is: one start bit; two op code bits and either eight (x16) or nine (x8) address or instruction bits. During power-up, the reset outputs remain active until VCC reaches the VTRIP threshold. The outputs will continue to be driven for approximately 200ms after reach- 2012 2.0 4/18/00 2 S93662/S93663 Read Upon receiving a READ command and an address (clocked into the DI pin), the DO pin of the S93662/663 will come out of the high impedance state and, will first output an initial dummy zero bit, then begin shifting out the data addressed (MSB first). The output data bits will toggle on the rising edge of the SK clock and are stable after the specified time delay (tPD0 or tPD1). Erase Upon receiving an ERASE command and address, the CS (Chip Select) pin must be deselected for a minimum of 250ns (tCSMIN). The falling edge of CS will start the auto erase cycle of the selected memory location. The ready/busy status of the S93662/663 can be determined by selecting the device and polling the DO pin. Once cleared, the content of a cleared location returns to a logical “1” state. Write After receiving a WRITE command, address and the data, the CS (Chip Select) pin must be deselected for a minimum of 250ns (tCSMIN). The falling edge of CS will start automatic erase and write cycle to the memory location specified in the instruction. The ready/busy status of the S93662/663 can be determined by selecting the device and polling the DO pin. Erase/Write Enable and Disable The S93662/663 powers up in the write disable state. Any writing after power-up or after an EWDS (write disable) instruction must first be preceded by the EWEN (write enable) instruction. Once the write instruction is enabled, it will remain enabled until power to the device is removed, or the EWDS instruction is sent. The EWDS instruction can be used to disable all S93662/663 write and clear instructions, and will prevent any accidental t SKLOW tSKHI t CSH SK t DIS t DIH VALID DI VALID t CSS CS t DIS t PD0,t PD1 DO tCSMIN DATA V ALID 2012 ILL 3 1.0 Figure 1. Sychronous Data Timing SK tCS CS STANDBY AN DI DO 1 1 AN–1 A0 0 HIGH-Z tPD0 tHZ HIGH-Z 0 DN DN–1 D1 D0 2012 ILL4 1.0 Figure 2. Read Instruction Timing 3 2012 2.0 4/18/00 S93662/S93663 writing or clearing of the device. Data can be read normally from the device regardless of the write enable/ disable status. Write All Upon receiving a WRAL command and data, the CS (Chip Select) pin must be deselected for a minimum of 250ns (tCSMIN). The falling edge of CS will start the self clocking data write to all memory locations in the device. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/ busy status of the S93662/663 can be determined by selecting the device and polling the DO pin. It is not necessary for all memory locations to be cleared before the WRAL command is executed. Erase All Upon receiving an ERAL command, the CS (Chip Select) pin must be deselected for a minimum of 250ns (tCSMIN). The falling edge of CS will start the self clocking clear cycle of all memory locations in the device. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the S93662/663 can be determined by selecting the device and polling the DO pin. Once cleared, the contents of all memory bits return to a logical “1” state. address. Internally the address pointer is incremented after receiving each group of sixteen clocks; however, once the address counter reaches xxxx x111 it will roll over to xxxx x000 with the next clock. After the last bit is clocked in no internal write operation will occur until CS is brought low. Page Write 93662 - Assume WEN has been issued. The host will then take CS high, and begin clocking in the start bit, write command and 9-bit byte address immediately followed by the first byte of data to be written. The host can then continue clocking in 8-bit bytes of data with each byte to be written to the next higher address. Internally the address pointer is incremented after receiving each group of eight clocks; however, once the address counter reaches x xxxx 1111 it will roll over to x xxxx 0000 with the next clock. After the last bit is clocked in no internal write operation will occur until CS is brought low. Continuous Read This begins just like a standard read with the host issuing a read instruction and clocking out the data byte [word]. If the host then keeps CS high and continues generating clocks on SK, the S93662/663 will output data from the next higher address location. The S93662/663 will continue incrementing the address and outputting data so long as CS stays high. If the highest address is reached, the address counter will roll over to address 0000. . CS going low will reset the instruction register and any subsequent read must be initiated in the normal manner of issuing the command and address. 93663 - Assume WEN has been issued. The host will then take CS high, and begin clocking in the start bit, write command and 8-bit byte address immediately followed by the first 16-bit word of data to be written. The host can then continue clocking in 16-bit words of data with each word to be written to the next higher 2012 2.0 4/18/00 4 S93662/S93663 SK tCS CS AN DI STANDBY STATUS VERIFY 1 0 AN-1 A0 DN D0 1 tSV BUSY HIGH-Z DO tHZ READY HIGH-Z tEW 2012 ILL 5 1.0 Figure 3. Write Instruction Timing SK STATUS VERIFY CS AN DI 1 1 tCS A0 AN-1 STANDBY 1 tSV tHZ HIGH-Z DO BUSY READY HIGH-Z tEW 2012 ILL6 1.0 Figure 4. Erase Instruction Timing SK STANDBY CS DI 1 0 0 * * ENABLE=1 DISABLE=00 1 2012 ILL 7 1.0 Figure 5. EWEN/EWDS Instruction Timing 5 2012 2.0 4/18/00 S93662/S93663 SK CS STANDBY STATUS VERIFY t CS DI 1 0 0 0 1 t SV t HZ HIGH-Z DO BUSY READY HIGH-Z t EW 2012 ILL 8 1.0 Figure 6. ERAL Instruction Timing SK CS STATUS VERIFY STANDBY t CS DI 1 0 0 0 DN 1 DO t SV t HZ DO BUSY READY HIGH-Z t EW 2012 ILL 10 1.0 Figure 7. WRAL Instruction Timing INSTRUCTION SET Instruction Start Bit Opcode Address x8 x16 Data x8 Comments READ 1 10 A8–A0 A7–A0 ERASE 1 11 A8–A0 A7–A0 WRITE 1 01 A8–A0 A7–A0 EWEN 1 00 11xxx xxxx 11xxx xxx Write Enable EWDS 1 00 00xxx xxxx 00xxx xxx Write Disable ERAL 1 00 10xxx xxxx 10xxx xxx Clear All Addresses WRAL 1 00 01xxx xxxx 01xxx xxx x16 Read Address AN–A0 Clear Address AN–A0 D7–D0 D7–D0 D15–D0 D15–D0 Write Address AN–A0 Write All Addresses 2012 PGM T5 1.1 2012 2.0 4/18/00 6 S93662/S93663 ABSOLUTE MAXIMUM RATINGS* Temperature Under Bias .................................................................................................................................... –55°C to +125°C Storage Temperature ......................................................................................................................................... –65°C to +150°C Voltage on any Pin with Respect to Ground(1) ............................................................................................ –2.0V to +VCC +2.0V VCC with Respect to Ground .................................................................................................................................. –2.0V to +7.0V Package Power Dissipation Capability (Ta = 25°C) ............................................................................................................. 1.0W Lead Soldering Temperature (10 seconds) ........................................................................................................................ 300°C Output Short Circuit Current(2) ........................................................................................................................................... 100mA *COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. RECOMMENDED OPERATING CONDITIONS Temperature Commercial Min 0°C Max +70°C Industrial -40°C +85°C 2012 PGM T7 1.0 RELIABILITY CHARACTERISTICS Symbol Parameter Min. Max. Units Reference Test Method 100,000 Cycles/Byte MIL-STD-883, Test Method 1033 NEND(3) Endurance TDR(3) Data Retention 100 Years MIL-STD-883, Test Method 1008 VZAP(3) ESD Susceptibility 2000 Volts MIL-STD-883, Test Method 3015 ILTH(3)(4) Latch-Up 100 mA JEDEC Standard 17 2012 PGM T2 1.1 D.C. OPERATING CHARACTERISTICS (over recommended operating conditions unless otherwise specified) Limits Symbol Parameter Min. Typ. Max. Units Test Conditions ICC Power Supply Current (Operating) 3 mA DI = 0.0V, fSK = 1MHz VCC = 5.0V, CS = 5.0V, Output Open ISB Power Supply Current (Standby) 50 µA CS = 0V Reset Outputs Open ILI Input Leakage Current 2 µA VIN = 0V to VCC ILO Output Leakage Current (Including ORG pin) 10 µA VOUT = 0V to VCC, CS = 0V VIL1 VIH1 Input Low Voltage Input High Voltage -0.1 2 0.8 VCC+1 V V 4.5V-VCC<5.5V VIL2 VIH2 Input Low Voltage Input High Voltage 0 VCC × 0.7 VCC × 0.2 VCC+1 V V 1.8V-VCC<2.7V VOL1 VOH1 Output Low Voltage Output High Voltage 0.4 2.4 V V 4.5V-VCC<5.5V IOL = 2.1mA IOH = -400µA VOL2 VOH2 Output Low Voltage Output High Voltage 0.2 VCC-0.2 V V 1.8V-VCC<2.7V IOL = 1mA IOH = -100µA 2012 PGM T3 1.1 Note: (1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20ns. (2) Output shorted for no more than one second. No more than one output shorted at a time. (3) This parameter is tested initially and after a design or process change that affects the parameter. (4) Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to VCC +1V. 7 2012 2.0 4/18/00 S93662/S93663 PIN CAPACITANCE Symbol (1) COUT CIN(1) Test Max. Units Conditions OUTPUT CAPACITANCE (DO) 5 pF VOUT=OV INPUT CAPACITANCE (CS, SK, DI, ORG) 5 pF VIN=OV Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. 2012 PGM T4 1.0 A.C. CHARACTERISTICS (over recommended operating conditions unless otherwise specified) Limits VCC=2.7V-4.5V VCC=4.5V-5.5V Max. Min. Test SYMBOL PARAMETER Min. tCSS CS Setup Time 100 50 ns tCSH CS Hold Time 0 0 ns VIL = 0.45V tDIS DI Setup Time 200 100 ns VIH = 2.4V tDIH DI Hold Time 200 100 ns CL = 100pF tPD1 Output Delay to 1 0.5 0.25 µs VOL = 0.8V tPD0 Output Delay to 0 0.5 0.25 µs tHZ(1) Output Delay to High-Z 200 100 ns VOH = 2.0v CL = 100pF tEW Program/Erase Pulse Width 10 10 ms tCSMIN Minimum CS Low Time 0.5 0.25 µs tSKHI Minimum SK High Time 0.5 0.25 µs tSKLOW Minimum SK Low Time 0.5 0.25 µs tSV Output Delay to Status Valid SKMAX Maximum Clock Frequency 0.5 DC 500 DC Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. 2012 2.0 4/18/00 8 Max. UNITS Conditions 0.25 µs 1000 KHZ CL = 100pF 2012 PGM T6 1.0 S93662/S93663 RESET CIRCUIT AC and DC ELECTRICAL CHARACTERISTICS 2.7 Symbol Parameter 5 Volt-A 5 Volt-B Min Max Min Max Min Max Unit VTRIP Reset Trip Point 2.55 2.7 4.25 4.5 4.50 4.75 V tPURST Power-Up Reset Timeout 130 270 130 270 130 270 ms tRPD VTRIP to RESET Output Delay 5 µs VRVALID RESET# Output Valid tGLITCH Glitch Reject Pulse Width 30 30 30 ns VOLRS RESET# Output Low Voltage IOL=1mA 0.4 0.4 0.4 V VOHRS RESET Output High IOH 5 1 5 1 VCC-.75 VCC-.75 1 V VCC-.75 V 2012 PGM T1 1.1 tGLITCH VTRIP VRVALID VCC tRPD tPURST tPURST RESET# tRPD RESET 2012 T fig08 2.0 Figure 8. RESET Timing Diagram 9 2012 2.0 4/18/00 S93662/S93663 8 Pin SOIC (Type S) Package JEDEC (150 mil body width) .050 (1.27) TYP. .050 (1.270) TYP. 8 Places .157 (4.00) .150 (3.80) .275 (6.99) TYP. .030 (.762) TYP. 8 Places 1 .196 (5.00) .189 (4.80) FOOTPRINT .061 (1.75) .053 (1.35) .020 (.50) x45° .010 (.25) .0098 (.25) .004 (.127) .05 (1.27) TYP. .0192 (.49) .0138 (.35) .035 (.90) .016 (.40) .244 (6.20) .228 (5.80) 8pn JEDEC SOIC ILL.2 8 Pin PDIP (Type P) Package .375 (9.525) .250 (6.350) PIN 1 INDICATOR .300 (7.620) .070 (1.778) .0375 (0.952) .015 (.381) Min. 5°-7°TYP. (4 PLCS) 0°-15° SEATING PLANE .130 (3.302) .060 ± .005 (1.524) ± .127 TYP. .100 (2.54) TYP. .130 (3.302) .018 (.457) TYP. 2012 2.0 4/18/00 10 .350 (8.89) .009 ± .002 (.229 ± .051) 8pn PDIP/P ILL.3 S93662/S93663 Frequently the reset controller will be deployed on a PC board that provides a peripheral function to a system. Examples might be modem or network cards in a PC or a PCMCIA card in a laptop. In instances like this the peripheral card may have a requirement for a clean reset function to insure proper operation. The system may or may not provide a reset pulse of sufficient duration to clear the peripheral or to protect data stored in a nonvolatile memory. The I/O capability of the RESET pins can provide a solution. The system’s reset signal to the peripheral can be fed into the S93662/663 and it in turn can clean up the signal and provide a known entity to the peripheral’s circuits. The figure below shows the basic timing characteristics under the assumption the reset input is shorter in duration than tPURST. The same reset output affect can be attained by using the active high reset input. RESET# Input RESET# Output RESET Output t PURST 2012 T fig09 2.0 When planning your resistor pull-up and pull-down values, use the following chart to help determine min. resistances. Worst Case RESET Sink/Source Capabilities at Various VCC Levels Parameter RESET# Output Symbol VOL Voltage RESET# Output VOL Voltage RESET Output Voltage VOH Condition Min Typ Max Units VCC = 1.0V, IOL=100µA 0.3 V VCC = 1.2V, IOL=100µA 0.3 V VCC = 3.0V, IOL=500µA 0.3 V VCC = 3.6V, IOL=500µA 0.3 V VCC = 4.5V, IOL=750µA 0.3 V VCC = 1.0V, IOL=100µA 0.4 V VCC = 1.2V, IOL=150µA 0.4 V VCC = 3.0V, IOL=750µA 0.4 V VCC = 3.6V, IOL=1mA 0.4 V VCC = 4.5V, IOL=1mA 0.4 V VCC = 1.0V, IOH=400µA VCC-0.75 V VCC = 1.2V, IOH=800µA VCC-0.75 V VCC = 3.0V, IOH=800µA VCC-0.5 V VCC = 3.6V, IOH=800µA VCC-0.5 V VCC = 4.5V, IOH=800µA VCC-0.5 V 2012 PGM T5 1.0 11 2012 2.0 4/18/00 S93662/S93663 Ready/Busy Status During the internal write operation the S93662/663 memory array is inaccessible. After starting the write operation (taking CS low) the host can implement a 10ms time-out routine or alternatively it can employ a polling routine that tests the state of the DO pin. After starting the write, testing for the status is easily accomplished by taking CS high and testing the state of DO. If it is low the device is still busy with the internal write. If it is high the write operation has completed. For the polling routine the host has the option of toggling CS for each test of DO, or it can place CS high and then intermittently test DO. SK is not required for any of these operations. Once the device is ready, it will continue to drive DO high whenever the S93662/663 is selected. The ready state of DO can be cleared by clocking in a start bit; this start bit can either be the beginning of a new command sequence or it can be a dummy start bit with CS returning low before the host issues a new command. SK CS STATUS VERIFY t CS DI t SV t HZ DO BUSY HIGH-Z READY HIGH-Z t EW STATUS CLEARED 2012 ILL 13 1.0 2012 2.0 4/18/00 12 S93662/S93663 ORDERING INFORMATION S93662 A P T Tape & Reel Option Blank = Tube T = Tape & Reel Base Part Number S93662 = 8-bit configuration S93663 = 16-bit configuration Package P = 8 lead PDIP S = 8 lead 150mil SOIC Operating Voltage Range A = 4.5V to 5.5V VTRIP min. @ 4.25V B = 4.5V to 5.5V VTRIP min. @ 4.50V 2.7 = 2.7V to 5.5V VTRIP min. @ 2.55V 2012 Tree 2.0 13 2012 2.0 4/18/00 S93662/S93663 NOTICE SUMMIT Microelectronics, Inc. reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. SUMMIT Microelectronics, Inc. assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained herein reflect representative operating parameters, and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked, SUMMIT Microelectronics, Inc. shall not be liable for any damages arising as a result of any error or omission. SUMMIT Microelectronics, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless SUMMIT Microelectronics, Inc. receives written assurances, to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; and (c) potential liability of SUMMIT Microelectronics, Inc. is adequately protected under the circumstances. © Copyright 2000 SUMMIT Microelectronics, Inc. 2012 2.0 4/18/00 14