SCA1000-D01
PRODUCT SPECIFICATION FOR
XY-DUAL AXIS ACCELEROMETER
SCA1000 – D01
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Rev.C
SCA1000-D01
Table of Contents
1
2
General description ...................................................................................................... 3
1.1
Block diagram ...................................................................................................... 3
1.2
SCA1000 family Accelerometer Features ............................................................ 3
Electrical specifications ................................................................................................ 4
2.1
3
4
2.1.1
Recommended connection when SPI interface is used .................................... 5
2.1.2
Recommended connection when analog output is used .................................. 5
2.1.3
Recommended EMC protection circuitry .......................................................... 6
2.2
Absolute maximum ratings .................................................................................. 6
2.3
Electrical Specification of the SCA1000 – D01 .................................................... 7
2.3.1
Analog Output................................................................................................... 7
2.3.2
Digital Output .................................................................................................... 9
SPI Interface ............................................................................................................... 10
3.1
DC characteristics of SPI interface .................................................................... 12
3.2
AC characteristics of SPI interface .................................................................... 13
3.3
SPI Commands ................................................................................................. 14
Mechanical specification (Reference only) ................................................................. 16
4.1
5
Electrical Connection ........................................................................................... 4
Dimensions (Reference only) ............................................................................ 16
Mounting..................................................................................................................... 17
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1
General description
The SCA1000 accelerometer consists of two silicon bulk micro machined sensing element
chips and a signal conditioning ASIC. The chips are mounted on a pre-molded package and
wire bonded to appropriate contacts. The sensing elements and ASIC are protected with
silicone gel and lid. The sensor has 12 SMD legs (Gull-wing type).
Block diagram
1.1
ax
SC
SC
sensing element
filter1
SC
gain
SC
SC
sample and hold
SC
filter2
pfilter
X_Ext_C
DAC
C/V
DAC
fail_det SC
S/H
X_OUT
CSB
SCK
MOSI
MISO
ST_X/Test_in
ST_Y
BG
interface+control logic+EEPROM
ADC
agnd por
DAC
OSC
clk gen
HV pump
VDD
VSS
ay
SC
SC
sensing element
filter1
SC
gain
SC
SC
filter2
sample and hold
SC
pfilter
Y_Ext_C
C/V
DAC
DAC
fail_det SC
S/H
Y_OUT
Figure 1.
Block diagram of the SCA1000
1.2 SCA1000 family Accelerometer Features
•
•
•
•
•
Single +5V supply
Two ratiometric analog outputs in relation to supply voltage (Vdd = 4.75....5.25V)
• Wide load driving capability
Serial Peripheral Interface (SPI) compatible
• Provides digital output for both channels
• Supports testing and programming
Non-volatile programming features
• Factory programmable filter settings ( 400Hz, 1 kHz, WB, Ext_C )
• Offset and sensitivity calibration
• Linear temperature compensation
Enhanced failure detection features
• True self test by deflecting the sensing elements’ proof mass by electrostatic
force. Deflection voltage is adjustable with two memory bits for both channels.
The self-test is channel specific, and separately activated for both channels by
digital on-off commands via dedicated pins or via SPI bus.
• Continuous sensing element interconnection failure check
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2
Electrical specifications
2.1 Electrical Connection
The following is a typical requirement for electrical interface to the SCA1000. If special over
voltage or reverse polarity protection is needed, please contact VTI Technologies for
application information.
If self test (Pins 9 and 10) is not used, it should be left floating / grounded
SCK 1
12 VDD
NC
Ext_C_1
2
No.
1
2
3
4
5
6
7
8
9
10
11
12
Node
SCK
NC
MISO
MOSI
Out_2
VSS
CSB
NC
ST_2
ST_1 / Test_in
Out_1
VDD
Figure 2.
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11 OUT_1
MISO 3
10 ST_1/Test_in
MOSI 4
9
ST_2
OUT_2 5
8
NC
Ext_C_2
VSS 6
7
CSB
I/O
Input
NC
Output
Input
Output
Power
Input
NC
Input
Input
Output
Power
Description
Serial clock
NC
Master in slave out; data output
Master out slave in; data input
Y axis Output (Ch 2)
Negative supply voltage (VSS)
Chip select (active low)
NC
Self test input for Y axis (Ch 2)
Self test input for X axis (Ch 1 ) / Analog test input
X axis output (Ch 1)
Positive supply voltage (VDD)
Pin layout and description of the SCA1000
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Rev.C
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2.1.1 Recommended connection when SPI interface is used
Vdd (+5V)
SCK
Serial Clock
NC
Data Out
MISO
Data In
MOSI
12 VDD
1
11 OUT_1
X
2
3
10 ST_1
4
9
Y
OUT_2 5
8
VSS 6
7
Min 100n
F
ST_2
NC
CSB
Chip select
Recommended SPI-Output connection on PCB
2.1.2 Recommended connection when analog output is used
When SCA1020 is used in Analog mode and the PCB is designed correctly the SCA610 / 620 and
SCA1020 are interchangeable. If the PCB layout is designed for SCA1020, then SCA610 / 620 can
be used for single axis applications. Pins 1, 2, 3, 4 and 8 can be connected to GND (pins 2 and 8
can be connected also to Vdd) but for the best EMC performance these pins should be left floating.
CSB pin can be pulled up but it is recommended to left floating. The output of SCA610 / 620
corresponds to the output of channel 1 in the SCA1020
Vdd (+5V)
SCK 1
12 VDD
Min 100nF
NC 2
MISO
Z
3
MOSI 4
Out 2 (Y)
OUT_2 5
VSS 6
11 OUT_1
Out 1 (Z)
10 ST_1/Test_i
n
Self-Test 1
9
Y
8
7
ST_2
Self-Test 2
NC
CSB
Recommended Analog output connection on PCB
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SCA610 or SCA620 connected
to the SCA1020 lay-out
5/18
Rev.C
SCA1000-D01
2.1.3 Recommended EMC protection circuitry
The purpose of the following recommendation is to give generic EMC protection guidelines for the
SCA1020. EMC susceptibility is highly dependent on the PCB layout and therefore the component
values given here can be different depending on the actual PCB layout. With the following circuitry
and properly designed PCB the part will pass 200V/m EMC susceptibility tests.
Please note that only channel 1 output protection circuitry is presented. Similar kind of circuit must
be also at the channel 2 output.
Vdd (+5V)
SCK 1
Vdd (+5V)
12 VDD
Min 100nF
NC
2
11 OUT_1
Z
68pF
10 ohm
Out 1 (Z)
68pF
MISO
10 ST_1/Test_i
n
3
GND
MOSI 4
Out 2 (Y)
OUT_2 5
Self-Test 1
ST_2
9
Y
NC
8
VSS 6
7
Self-Test 2
CSB
Recommended EMC protection circuitry
2.2 Absolute maximum ratings
Supply voltage (VDD)
Voltage at input / output pins
ESD
HBM (Human Body Model)
CDM (Charged Device Model)
Storage temperature
Operating temperature
Mechanical shock
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-0.3 V to +5.5V (continuous)
-0.3V to 7V (5 seconds during 1 minutes cycle)
-0.3V to (VDD + 0.3V)
±2kV
±500V
-55°C to +125°C
-40°C to +125°C
Drop from 1 meter on a concrete surface.
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Rev.C
SCA1000-D01
2.3 Electrical Specification of the SCA1000 – D01
2.3.1 Analog Output
Vdd = 5.00V and ambient temperature (23°C±5°C) unless otherwise specified. .
KPC
(16
Parameter
(1
<CC>
X axis (Out_1) Measuring range
(1
Y axis (Out_2) Measuring range
Supply voltage Vdd
Current consumption
Operating temperature
Condition
Min.
Nominal
Nominal
-1.7
-1.7
4.75
<SC>
X axis (Out_1) Offset Error (output at 0g)
<SC>
X axis (Out_1) Sensitivity error
(5,
13
Vout to Vdd or Vss
Vout to Vdd or Vss
10k from Vout to Vdd
10k from Vout to Vss
@ room temperature
@ room temperature
0
4.75
-40...+105°C
-40…+125°C
(6, 13
-40...+105°C
-40...+125°C
(3, 13
<CC>
<CC>
Y axis (Out_2) Offset (output at 0g)
(4, 13
Y axis (Out_2) Sensitivity
<SC>
Y axis (Out_2) Offset Error (output at 0g)
<SC>
Y axis (Out_2) Sensitivity error
(5,
(6, 13
Typical non-linearity
(8
X axis (Out_1) Frequency response -3dB
(8
Y axis (Out_2) Frequency response -3dB
(9
Ratiometric error
(10
Cross-axis sensitivity
(11
Output noise
Start-up delay
Self test input pull down current
(14
T1: T st-on
T3: T recov.
T4: T stab.
= T2+T3
(14
T5: T r
(14
V2
(14, 15
V3
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(14
(14
(14
5.0
g
(2
g
V
mA
10
-40...+105°C
-40…+125°C
-40...+105°C
-40...+125°C
Range = -1g...+1g
Vdd = 4.75...5.25V
@ room temperature
From DC...4kHz
Reset and parity check
Vdd = 5V
Self test ON period.
Controlled externally by
user
Saturation delay. Time
when element beam
remains still out from
linear operating range.
Recovery time when
element is back in linear
operating range
Stabilisation time, when
self test is released.
Rise time during self test,
when Vout reach V2
Vout during self test
Stabilised output voltage
after self test is released.
Doc. Nr. 8225700
20
0.25
5.00
-80
-100
Vdd/2
0.24 x
Vdd
-
+80
+100
-4
±3
-
+4
-80
-100
Vdd/2
0.24 x
Vdd
-
+80
+100
-4
±3
-
+4
-20
20
20
-2
50
50
-
10
10
21
@ room temperature
@ room temperature
13
T2: Tsat.del.
Units
+1.7
+1.7
5.25
5.0
+125
-40
<CC>
<CC>
<SC>
Max.
Vdd = 5 V; No load
Resistive output load (Analog Output)
Capacitive load (Analog Output)
Min. output voltage; Vdd = 5V
Max. output voltage; Vdd = 5V
(3, 13
X axis (Out_1) Offset (output at 0g)
(4, 13
X axis (Out_1) Sensitivity
(7
Typ
4.75
0.95*
V1
(2
°C
kOhm
nF
V
V
V
V/g
mg
%
V
V/g
mg
%
+20
80
80
2
3.5
5
10
30
100
mg
Hz
Hz
%
%
mVrms
ms
20
ms
50
ms
70
ms
10
ms
µA
ms
V
V1
1.05 *
V1
7/18
Rev.C
SCA1000-D01
Note 1.
The measuring range is limited only by the sensitivity, offset and supply voltage rails of the device
Note 2.
1g = 9.82m/S2
Note 3.
Offset specified as Voffset = Vout(0g) [ V ]. See note 13.
Note 4.
Sensitivity specified as Vsens = {Vout(+1g) - Vout(-1g)}/2
Note 5.
Offset error specified as Offset Error = {Vout(0g) - Vdd/2} / Vsens [ g ]
Vsens = Nominal sensitivity
Vdd/2 = Nominal offset
See note 13.
Note 6.
Sensitivity error specified as Sensitivity Error = { [Vout(+1g) - Vout(-1g)] / 2 - Vsens} / Vsens x 100% [% ]
Vsens = Nominal sensitivity
See note 13.
Note 7.
From straight line through -1g and +1g.
Note 8.
The frequency response is determined by the sensing element’s internal gas damping. The output has true DC
(0Hz) response.
Note 9.
The ratiometric error is specified as.
[ V/g ]. See note 13
Vout (@ Vx ) × 5.00V
Vx
RE = 100% × 1 −
Vout
(@
5
V
)
Note 10. The cross-axis sensitivity determines how much acceleration, perpendicular to the measuring axis, couples to the
output. The total cross-axis sensitivity is the geometric sum of the sensitivities of the two axes that are
perpendicular to the measuring axis.
Note 11. In addition, supply voltage noise couples to the output due to the ratiometric nature of the accelerometer.
Note 12. The self-test will increase the output voltage. The output will go to Vdd rail. The purpose of the self-test is to check
out the total functionality of the sensor. It is not meant for calibration or auto zeroing.
Note 13. Measuring positions
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Note 14. Self-test waveforms:
5V
ST pin
voltage
0V
5V
V1
Vout
V2
T1
0V
T5
V3
T2
T3
T4
Time [ ms ]
Note 15. V1=
V3=
Initial output Voltage before self-test activation
Output voltage after self-test has been removed and after stabilization time. Please note that the error
band specified for V3 is to guarantee that the output is within 5% of the initial value after the specified
stabilization time.
After longer time V1=V3.
Note 16 CC=
SC=
Critical Characteristics. Must be 100% monitored during production
Significant Characteristic. The process capability (Cpk) must be better than 1.33, which allows sample
based testing. If process is not capable the part will be 100% tested
2.3.2 Digital Output
Vdd = 5.00V and ambient temperature unless otherwise specified.
Parameter
Condition
Output load
SPI clock frequency
Internal A/D conversion time
Data transfer time
@500kHz
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Min.
Typ
Max.
Units
1
500
150
38
nF
kHz
µs
µs
9/18
Rev.C
SCA1000-D01
3
SPI Interface
Serial peripheral interface (SPI) is a 4-wire synchronous serial interface. Data communication
is enabled with low active Slave Select or Chip Select wire (CSB). Data is transmitted with 3wire interface consisting of serial data input (MOSI), serial data output (MISO) and serial
clock (SCK). Every SPI system consists of one master and one or more slaves, where the
master is defined as the microcomputer that provides the SPI clock, and the slave is any
integrated circuit that receives the SPI clock from the master.
MASTER
MICROCONTROLLER
DATA OUT (MOSI)
DATA IN (MISO)
SERIAL CLOCK (SCK)
SS0
SLAVE
SI
SO
SCK
CS
SS1
SS2
SS3
SI
SO
SCK
CS
SI
SO
SCK
CS
SI
SO
SCK
CS
Figure 4.
Typical SPI connection
The SPI interface of this ASIC is designed to support almost any micro controller that uses
software implemented SPI. However it is not designed to support any particular hardware
implemented SPI found in many commercial micro controllers. Serial peripheral interface in
this product is used in testing and calibration purposes as well as in the final application. In
normal use some testing and calibration commands are disabled and have not been
documented here. This ASIC operates always as a slave device in the master-slave
operation mode. The data transfer between the master (µP test machine etc.) and ASIC is
performed serially with four wire system.
MOSI
MISO
SCK
CSB
master out slave in
master in slave out
serial clock
chip select (low active)
µP → ASIC
ASIC → µP
µP → ASIC
µP → ASIC
Each transmission starts with a falling edge on CSB and ends with the rising edge. During
the transmission, commands and data are controlled by SCK and CSB according to the
following rules:
•
•
•
commands and data are shifted MSB first LSB last
each output data/status-bits are shifted out on the falling edge of SCK (MISO line)
each bit is sampled on the rising edge of SCK (MOSI line)
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•
•
•
•
•
•
•
after the device is selected with CSB going low, an 8-bit command is received. The
command defines the operations to be performed
the rising edge of CSB ends all data transfer and resets internal counter and
command register
if an invalid command is received, no data will be shifted into chip and the MISO
will remain in high impedance state until the falling edge of CSB. This will
reinitialize the serial communication.
to be able to perform any other command than those listed in Table 1. SPI
commands, the lock register content has to be set correctly. If other command is
feed without correct lock register content, no data will be shifted into chip and the
MISO will remain in high impedance state until the falling edge of CSB.
data transfer to MOSI continues right after the command is received in all cases
where data is to be written to ASIC’s internal registers
data transfer out from MISO starts with a falling edge of SCK right after the last bit
of SPI command is sampled in on the rising edge of SCK
maximum data transfer speed exceeds 500 kHz clock rate
SPI command can be an individual command or a combination of command and data. In
the case of combined command and data, the input data follows uninterruptedly the SPI
command and the output data is shifted out parallel with the input data.
CSB
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
2
1
0
2
1
0
SCK
D A TA IN
COM MAND
MOSI
7
6
5
7
6
5
Figure 5.
3
D A TA O U T
H IG H IM PED A N C E
M ISO
4
4
3
One command and data transmission over the SPI
After power up the circuit starts up in measure mode. This is the operation mode that is
used in the final application.
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3.1 DC characteristics of SPI interface
Supply voltage is 5 V unless otherwise noted. Current flowing into the circuit have positive values.
Parameter
Conditions
Input terminal CSB
Pull up current
VIN = 0 V
Input high voltage
Input low voltage
Hysteresis
Input capacitance
Input terminal MOSI, SCK
Pull down current
VIN = 5 V
Input high voltage
Input low voltage
Hysteresis
Input capacitance
Output terminal MISO
Output high voltage
I > -1mA
Output low voltage
I < 1 mA
Tristate leakage
0 < VMISO < Vdd
Table 1.
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Symbol
Min
Typ
Max
IPU
VIH
VIL
VHYST
CIN
13
4
-0.3
22
35
Vdd+0.3
1
µA
V
V
V
pF
IPD
VIH
VIL
VHYST
CIN
9
4
-0.3
29
Vdd+0.3
1
µA
V
V
V
pF
VOH
VOL
ILEAK
0.23*Vdd
2
17
0.23*Vdd
2
Vdd-0.5
5
0.5
100
Unit
V
V
pA
DC characteristics of SPI interface
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3.2 AC characteristics of SPI interface
Parameter
Terminal CSB, SCK
Time from CSB (10%) to
SCK (90%)1
Time from SCK (10%) to
CSB (90%)1
Terminal SCK
SCK low time
Conditions
Terminal MOSI, SCK
Time from changing MOSI
(10%, 90%) to SCK (90%)1.
Data setup time
Time from SCK (90%) to
changing MOSI (10%,90%)1.
Data hold time
Terminal MISO, CSB
Time from CSB (10%) to
stable MISO (10%, 90%)1.
Time from CSB (90%) to
high impedance state of
MISO1.
Terminal MISO, SCK
Time from SCK (10%) to
stable MISO (10%, 90%)1.
Terminal CSB
Time between SPI cycles,
CSB at high level (90%)
1 not production tested
TLS1
Min
TLS1
120
ns
TLS2
120
ns
TCL
1
µs
TCH
1
µs
TSET
30
ns
THOL
30
ns
Load capacitance at
MISO < 15 pF
Load capacitance at
MISO < 15 pF
TVAL1
10
100
ns
TLZ
10
100
ns
Load capacitance at
MISO < 15 pF
TVAL2
100
ns
Load capacitance at
MISO < 2 nF
Load capacitance at
MISO < 2 nF
SCK high time
Table 2.
Symbol
TLH
Typ
15
Max
Unit
µs
AC characteristics of SPI interface
TCH
TCL
TLS2
TLH
CSB
SCK
THOL
MOSI
TSET
MSB in
DATA in
TVAL1
MISO
MSB out
Figure 6.
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LSB in
TVAL2
TLZ
DATA out
LSB out
SPI bus timing diagram
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3.3 SPI Commands
This SPI interface utilizes an 8-bit instruction (or command) register. The list of commands
available to end-user is presented in Table 3.
Command
name
MEAS
RWTR
RDSR
RLOAD
STX
STY
RDAX
RDAY
Table 3.
Command
format
00000000
00001000
00001010
00001011
00001110
00001111
00010000
00010001
Description:
Measure mode (normal operation mode after power on)
Read and write temperature data register
Read status register
Reload NV data to memory output register
Activate Self test for X-channel
Activate Self test for Y-channel
Read X-channel acceleration through SPI
Read Y-channel acceleration through SPI
SPI commands
Measure mode (MEAS): Standard operation mode after power-up. During normal
operation, MEAS command is exit command from Self-Test.
Read and write temperature data register (RWTR): Temperature data register can be
read during normal operation without affecting the circuit operation. Temperature data
register is loaded in every 150 µs, and the load operation is disabled whenever the CSB
signal is low, hence CSB has to stay high at least 150 µs prior the RWTR command in order
to guarantee correct data. The data transfer is as presented in Figure 5 and data is
transferred MSB first. In normal operation, it doesn’t matter what data is written to
temperature data register during RWTR command and hence all zeros is recommended.
Read status register (RDSR): Read status register command provides access to the
status register. Status register format is shown in Table 4. Bold values in Definition column
are the expected values during normal operation.
Bit
Bit 3
(PERR)
Bit 2
(TEST)
Bit 1
(LOCK)
Bit 0
(PD)
Table 4.
Definition
Bit 3 = 0 Parity check hasn’t detected errors
Bit 3 = 1 Parity error detected
Bit 2 = 0 Analog test mode isn’t active
Bit 2 = 1 Analog test mode is active
Bit 1 = 0 Lock register is open
Bit 1 = 1 Lock register is locked
Bit 0 = 0 circuit is not in power down mode
Bit 0 = 1 circuit is in power down mode
Status register bit definitions
Reload NV data to memory output register (RLOAD): Reads NV data from EEPROM to
the memory output register.
Self test for X-channel (STX): STX command activates the circuit’s self test function for
the X-channel. Internal charge pump is activated and high voltage is applied to the XMurata Electronics Oy
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channel acceleration sensor element electrode. This causes electrostatic force, which
deflects the beam of the sensing element and simulates the acceleration to the positive
direction. X-channel self-test is de-activated by giving MEAS command.
Self test for Y-channel (STY): STY command activates the circuit’s self test function for
the Y-channel. Internal charge pump is activated and high voltage is applied to the Ychannel acceleration sensor element electrode. This causes electrostatic force, which
deflects the beam of the sensing element and simulates the acceleration to the positive
direction. Y-channel self-test is de-activated by giving MEAS command.
Read X-channel acceleration (RDAX): RDAX command provides access to AD
converted X-channel acceleration signal stored in acceleration data register X. During
normal operation acceleration data register X is loaded in every 150 µs, and the load
operation is disabled whenever the CSB signal is low, hence CSB has to stay high at least
150 µs prior the RDAX command in order to guarantee correct data. Data output is an 11bit digital word, which is feed out MSB first and LSB last. (See Figure 7).
CSB
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
5
4
3
16
17
18
1
0
SCK
COMM AND
M OSI
DATA OUT
H IG H IM P E D A N C E
M IS O
Figure 7.
10
9
8
7
6
2
RDAX command and data transmission over the SPI
Read Y-channel acceleration (RDAY): RDAY command provides access to AD
converted Y-channel acceleration signal which is stored in acceleration data register Y.
During normal operation acceleration data register Y is loaded in every 150 µs and the
load operation is disabled whenever the CSB signal is low, hence CSB has to stay high at
least 150 µs prior the RDAY command in order to guarantee correct data. Data output is
an 11-bit digital word, which is feed out MSB first and LSB last
Detailed information on all SPI commands is presented in document IC008 Dual Axis
Acceleration Sensor ASIC, Digital Specification.
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4
Mechanical specification (Reference only)
Lead frame material:
Plating:
Solderability:
<CC> Co-planarity error
Copper
Nickel followed by Gold
JEDEC standard: JESD22-B102-C
0.1mm max.
4.1 Dimensions (Reference only)
Figure 8.
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Mechanical dimensions of the SCA1000
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5
Mounting
The SCA1000 is suitable for Sn-Pb eutectic and Pb- free soldering process and mounting with
normal SMD pick-and-place equipment.
Recommended SCA1000 body temperature profile during reflow soldering:
Profile feature
Average ramp-up rate
Sn-Pb Eutectic Assembly
Pb-free Assembly
3°C/second max.
3°C/second max.
(TL to TP)
Preheat
-
Temperature min (Tsmin)
100°C
150°C
-
Temperature max (Tsmax)
150°C
200°C
-
Time (min to max) (ts)
60-120 seconds
Tsmax to TL
-
60-180 seconds
3°C/second max
Ramp up rate
Time maintained above:
-
Temperature (TL)
-
Time (tL)
Peak temperature (TP)
Time within 5°C of actual Peak Temperature (TP)
Ramp-down rate
Time 25° to Peak temperature
Figure 9.
183°C
217°C
60-150 seconds
60-150 seconds
240 +0/-5°C
250 +0/-5°C
10-30 seconds
20-40 seconds
6°C/second max
6°C/second max
6 minutes max
8 minutes max
Recommended SCA1000 body temperature profile during reflow soldering.
Ref. IPC/JEDEC J-STD-020B.
Note.
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Preheating time and temperatures according to solder paste manufacturer.
Component body temperature during the soldering should be measured from the
body of the component.
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The Moisture Sensitivity Level of the part is 3 according to the IPC/JEDEC J-STD-020B.
The part should be delivered in a dry pack. The manufacturing floor time (out of bag) in the
customer’s end is 168 hours.
Maximum soldering temperature is 250°C/40sec.
Figure 10.
Recommended PCB lay-out
Notes:
• It is important that the part is parallel to the PCB plane and that there is no angular
alignment error from intended measuring direction during assembly process.
• 1° mounting alignment error will increase the cross-axis sensitivity by 1.7%
• 1° mounting alignment error will change the output by 17mg
• To achieve the highest accuracy and to minimize resonance, it is recommended to glue
the accelerometer to the PCB before soldering
• Wave soldering is not recommended.
• A supply voltage by-pass capacitor (>100nF) must be used and located as close as
possible to the Vdd and GND pins.
• Note: When the accelerometer is oriented in such a way that the arrow points toward the
earth, the output will decrease. Please also note that you can rotate the part around the
measuring axis for optimum mounting location.
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