SD6830 Semiconductor 4BIT MICROCONTROLLER 1. Description SD6830 is a remote control transmitter, consists of the optimized 4-bit CPU with ROM and RAM. It contains power-on reset, watchdog timer and carrier frequency generator. The SD6830 provide a various carrier frequency for encoding output of key matrix and has built-in transistor to drive infrared LED. The SD6830 is supported with a software development tool, which allows code development in a PC environment. It allows the user to simulate the SD6830 on an instruction level. 2. Features • Number of basic instructions ------------------------------------- 45 • Instruction cycle time (one word instruction) At Fsys=480KHz ---------------------------------------- 16.67uS At Fsys=455kHz ---------------------------------------- 17.58uS • Memory size ROM --------------------------------------------------- 1024 x 8 Bits RAM ------------------------------------------------------ 32 x 4 Bits • Input ports (D0 ~ D3, E0 ~ E3 : with pull-up resistor) • Output ports (C, G, K, F0 ~ F7) • Carrier frequency generator Fsys/12 (1/2 duty), Fsys/12 (1/3 duty), Fsys/12 (1/4 duty), Fsys/8 (1/2 duty), Fsys/8 (1/4 duty), Fsys/11 (4/11 duty), No carrier • Watchdog Timer • Built-in power on reset • Single power supply ------------------------------------------------ 1.8V ~ 3.6V • Power dissipation (stop mode , VDD = 3V) ----------------------- Less than 3uW • Package ------------------------------------------------------------- 20/24 DIP, 20/24 SOP • Low-power system applications such as an infrared remote controller • MASK OPTION 1. Divide ratio of the oscillator frequency 2. Whether connected infrared LED driver or not * Descriptions of this spec sheet assume that the SD6830 include driver for infrared LED. 3. Ordering Information Type NO. Marking Package Code SD6830P-option SD6830P-option DIP20 SD6830-option SD6830-option SOP20 SD6830P-option SD6830P-option DIP24 SD6830-option SD6830-option SOP24 KSI-W002-000 1 SD6830 4. Block Diagram VSS 1 OSCIN 2 OSCOUT 3 OSC 3 Z Watchdog Timer 24 VDD 23 C/REM Test Control 22 TEST Port K 21 K 20 F0 19 F1 18 F2 17 F3 16 F4 15 F5 14 F6 13 F7 Port C Carrier Frequency Generator H Reset Control 4 RAM 4 4 L 3 G 4 Port G 4 4 B A 4 D0 5 D1 6 D2 7 4 Port D 4 ALU 4 CY STACK D3 8 10 PC E0 10 Port F ROM 9 E1 10 E2 11 E3 12 Port E 8 4 SF 4 4 Instruction Decoder OSC Start/Stop Control Key Input Detector Figure 4-1 Block Diagram of the SD6830 KSI-W002-000 2 SD6830 5. PIN Assignment and Description 5.1 PIN Assignment for 24PINS( DIP24, SOP24) VSS 1 24 VDD OSCIN 2 23 C/REM OSCOUT 3 22 TEST G 4 21 K D0 5 20 F0 D1 6 19 F1 D2 7 18 F2 D3 8 17 F3 E0 9 16 F4 E1 10 15 F5 E2 11 14 F6 E3 12 13 F7 DMC6830 SD 6830 SD6830 OUTLINE 24 PIN Figure 5-1. Pin Assignment of 24 Pins 5.2 PIN Description for 24 PINS Symbol Pin No. I /O Functions VDD 24 - Power Supply VSS 1 - Ground TEST 22 INPUT Input for test ( Normally connected to VSS ) OSCin 2 INPUT Input for oscillating OSCout 3 OUTPUT Output for oscillating C/REM 23 OUTPUT 1-Bit output for remote transmission B D0 - D3 5 ~ 8 INPUT 4-Bit input for key sense ( with pull-up resistor ) A E0 - E3 9 ~ 12 INPUT 4-Bit input for key sense ( with pull-up resistor ) A F0 - F7 20 ~ 13 OUTPUT 1-Bit individual output for key scan C G 4 OUTPUT 1-Bit output D K 21 OUTPUT 1-Bit output D KSI-W002-000 I/O Type 3 SD6830 5.3 PIN Assignment for 20PINS( DIP20, SOP20) VSS 1 20 OSCIN 2 19 C/REM OSCOUT 3 18 TEST D0 4 17 K D1 5 16 F0 D2 6 15 F1 D3 7 14 F2 E0 8 13 F3 E1 9 12 F4 F6 10 11 F5 SD 6830 SD6830 DMC6830 VDD OUTLINE 20 PIN Figure 5-3. Pin Assignment of 20Pin 5.4 PIN Description for 20 PINS Symbol Pin No. I /O Functions VDD 20 - Power Supply VSS 1 - Ground TEST 18 INPUT Input for test ( Normally connected to VSS ) OSCin 2 INPUT Input for oscillating OSCout 3 OUTPUT Output for oscillating C/REM 19 OUTPUT 1-Bit output for remote transmission B D0 - D3 4~7 INPUT 4-Bit input for key scan ( with pull-up resistor ) A E0 – E1 8 ~ 9 INPUT 2-Bit input for key scan ( with pull-up resistor ) A F0 – F6 16 ~ 10 OUTPUT 1-Bit individual output for key scan C K 17 OUTPUT 1-Bit output D KSI-W002-000 I/O Type 4 SD6830 5.5 I/O CIRCUIT SCHEMATICS TYPE A TYPE B VDD VDD 30ΚΩ ∼ 150ΚΩ PIN DATA PIN CARRIER CLOCK DATA PIN VSS VSS TYPE C TYPE D VDD VDD PIN PIN DATA DATA STOP VSS VSS Note :: IfIfSTOP STOP mode is specified, theCTYPE output"L" becomes state Band the becomes TYPE Bfloating output becomes floating NOTE mode is specified, the TYPE output C becomes state and“L” the TYPE output state, thethe TYPE D output maintains previous state. state, TYPE D output maintains previous state Figure 5-5. I/O Circuit Schematics KSI-W002-000 5 SD6830 6. Basic Function Block 6.1 Program Counter (PC) Program counter is used to indicate the address of the next instruction to be executed. The 10-bit program counter consists of two registers, PCH(4-bit) and PCL (6-bit). This is a polynomial counter. 6.2 Program Memory (ROM) Program memory is used to store user-specified program. This consists of a 1024 x 8-bit. It is organized in 16 pages and each page is 64 bytes long. For page-in addressing, all instructions excluding JMPL and CALL can be executed by page. In order to execute jump or call in page, JMP or CAL is suitable. For page-to-page addressing, JMPL or CALL must be used. PROGRAM COUNTER PCH (4-BIT) Figure PCL (6-BIT) 6-1. Program Memory Map PAGE 0 000h 0 1 2 3 PAGE 15 60 61 62 63 0 1 2 3 60 61 62 63 RESET ADDRESS PROGRAM MEMORY KSI-W002-000 6 SD6830 6.3 Data Memory (RAM) Data memory is used to store various type of processing data. This consists of a 32-nibble, which is organized into two files of 16 nibbles each. RAM addressing is indirectly implemented by a two registers; H, L. It’s upper 1-bit register (H) selects one of two files and its lower 4-bit register (L) selects one of 16 nibbles in the selected file. REG H (1-bit) REG L ( 4-bit ) FILE 0 F0 FILE 1 F1 0 1 2 3 0 F2 1 2 3 4 Lower 3-bit PORT F F3 F4 F5 12 13 14 15 12 F6 13 14 15 F7 DATA MEMORY Figure 6-2. Data Memory Map 6.4 Stack Register (SK) Stack register is used to store return address and provide a particularly mechanism for transferring control between programs. Two level hardware push/pop stacks are manipulated by CAL, CALL, and RET instructions. CAL/CALL instructions push the current program counter value, incremented by “1”, into stack level 1. Stack level 1 is automatically pushed to level 2. If more than two subsequent CAL/CALL are executed, only the most recent two return addresses are stored. RET instruction load the contents of stack level 1 into the program counter while stack level 2 gets copied into level 1. If more than two subsequent RET are executed, the stack will be filled with the address previously stored in level 2. KSI-W002-000 7 SD6830 6.5 Arithmetic and Logic Unit (ALU) This unit is used to perform arithmetic and logical operations such as addition, comparison, and bit manipulation. 6.6 Carry Flag (CY) The carry flag contains the carry generated by the arithmetic and logical unit immediately after an operation. The set carry (SETB CY) and clear carry (CLRB CY) instructions allow direct access for setting and clearing this flag. 6.7 Skip Flag (SF) The skip flag is a 1-bit register, which enables programs to conditionally skip an instruction. All instructions are executed when this flag is , the program executes NOP instruction and resets SF to “0”. Then program execution proceeds. The following instructions affect the skip flag Instructions Set conditions of SF Arithmetic ADD n INC L If carry occurs (L) = 0 Compare IF0 @HL.b IF0 CY IFEQU @HL IFEQU n M[HL].b = 0 (CY) = 0 (A) = M[HL].b (A) = n Data Transfer STA @HL+ XCH @HL+ (L) = 0 (L) = 0 The instructions, which doesn t affect the skip flag but have a skip condition, are as follows. Instructions Data Transfer LDA n LDL n Bit Manipulate SETB H CLRB H Skip conditions If it is continuous, skip next same instruction. If it is continuous, skip next same instruction. If SETB H or CLRB H are continuous, skip next SETB H or CLRB H instruction. KSI-W002-000 8 SD6830 6.8 Registers Register A Register A, called the accumulator, plays a central role, is used to store an input or an output operand (result) in the execution of most instructions. It consists of 4-bit. Register B Register B is used to store a temporary data in CPU. It consists of 4-bit. Register H Register H is used to indicate an address of the data memory in conjunction with register L. It consists of 1-bit, which is related with the bit 0 of accumulator Register L Register L is used to indicate an address of the data memory in conjunction with register H, Also lower 3-bit can be used to indicate the bit position of the port F. It consists of 4-bit Register Z Register Z is used to select a carrier frequency. The carrier frequency must be selected before Port C data write operation. It consists of 3-bit. Register Z Carrier frequency Bit 2 Bit 1 Bit 0 0 0 0 F SYS/12, 1/2 duty 0 0 1 F SYS/12, 1/3 duty 0 1 0 F SYS/12, 1/4 duty 0 1 1 F SYS/8, 1/2 duty 1 0 0 F SYS/8, 1/4 duty 1 0 1 F SYS/11, 4/11 duty 1 1 0 No carrier 1 1 1 No carrier KSI-W002-000 9 SD6830 6.9 I /O Ports Port C/REM Port C/REM is a 1-bit output port, which is related with the bit 3 of accumulator, with CMOS N-channel open drain, which have large current sink capability, for I.R.LED drive. This output can be configured as carrier frequency by programming the register Z and port C data. This pin is put into the high-impedance state in stop mode. Port D Port D is a 4-bit input port with pull-up resistor. Forcing any input pins to “L” state, system reset occurs and it starts to operate from the reset address. Port E Port E is a 4-bit input port with pull-up resistor. Forcing any input pins to reset occurs and it starts to operate from the reset address. Port F Port F is an 8-bit output port with N-channel open drain. Each output which specified by the lower 3-bit of register L can be set and reset individually. All F pins are put into the low state in stop mode. Port G Port G is a 1-bit output port with N-channel open drain. When stop mode is specified, this pin still remains in the previous state. Set this pin to appropriate state before entering stop mode for visible LED or key scan application. Port K Port K is a 1-bit output port with N-channel open drain. When stop mode is specified, this pin still remains in the previous state. Set this pin to appropriate state before entering stop mode for visible LED or key scan application. KSI-W002-000 10 SD6830 6.10 Carrier frequency generator One of seven carrier frequencies can be selected and transmitted through the C/REM pin by programming the register Z and port C. Fosc/8 (1/2 duty ) Fosc/8 (1/4 duty ) Fosc/11 (4/11 duty ) Vdd ( No carrier ) MUX VSS / 3 Register Z output Fsys (Fsys/12, 1/2 duty) (Fsys/12, 1/3 duty) (Fsys/12, 1/4 duty) (Fsys/8, 1/2 duty) (Fsys/8, 1/4 duty) Figure 6-3 PORT C/REM and Carrier Output KSI-W002-000 11 SD6830 6.11 Watchdog timer (WDT) The watchdog timer provides the means to return to a reset condition when a system malfunction occurs and the program enters an infinite loop caused by noise or any abnormal state. Also this timer have a function of oscillation stabilization timer. This is a 13-bit counter, counts the clock which is divided twelve (FSYS/12). In the stop mode the oscillation circuit stops but when a key input is detected (Port D, Port E) oscillation starts. When 12288 clock cycles have been counted, the program will be executed from reset address (000H). If the port C data register’s value does not change from “L” to “H” before the timer counts 98304 clock cycles, a device reset condition is generated. The oscillator stabilization time : 12/FSYS * 2 10 = 1/FSYS * 12288 = 27mS (@455KHz) The time-out period : 12/FSYS * 213 = 1/FSYS * 98304 = 216mS (@455KHz) Watchdog Timer (13-bit) Fsys/12 CLK OPSTART Operating Start OVERFLOW To Reset Logic RESET Power-on Reset Active Stop Mode Active PORT C Data : Low to High Transition Normal mode Stop mode Normal mode OSCOUT 27mS(Min.) PC WDT counting value 98304 Watchdog Timer Overflow PORT C Data Low to High PORT C Data Low to High STOP Instruction 12288 0 Time Figure 6-4. Function of Watchdog Timer KSI-W002-000 12 SD6830 6.12 Power-on reset The SD6830 incorporates an on-chip power-on reset circuitry which provides internal chip reset for most power-up situations. The power-on reset circuit and the watchdog timer are closely related. On power-up the power-on reset circuit is active and watchdog timer is reset. After the reset time, which is in proportion to the rate of rise of VDD, watchdog timer begins counting. After the oscillator stabilization time, which is typically 27mS in FSYS=455KHz, program execution proceeds from reset address (000H). DMC6830 SD6830 VDD VDD PIN VDD 7pF 1.8V Internal Internal /POR /POR 0.3VDD 2Mohm 0 VSS RESET TIME Figure 6-5. Built-in Power-on Reset 6.13 Stop mode The SD6830 support the stop mode to reduce power consumption. This mode is entered when the STOP instruction is executed during key inputs are not active. Activating any key inputs (Port D, Port E) the device is awakened from stop mode and restarts to operate from reset address. When the device is released from stop mode, following module set to appropriate value in reset routine: PORT G and PORT K. In stop mode, the oscillator is stopped and the each port state is as follows. Port C/REM become inactive state. ( for including I.R.LED driver, after the reset release) Port G and Port K retain previous state. KSI-W002-000 13 SD6830 DMC6830 SD6830 VDD Key input ( PORT D or PORT E ) 4 4 PORT D PORT E STOP STOP instruction RESET internal /POR Internal /STOP STOP instruction Stop mode Normal mode Stop mode OSCOUT WDT overflow 27mS(Min.) Figure 6-6. Rest structure and Release Timing for STOP Mode to Normal Mode 6.14 OSC Divide Option The OSC divide option provides a maximum 1MHz system clock (FSYS). FOSC which is generated in oscillation circuit is divided eight or non-divide to produce F SYS. This dividing ratio will be selected by mask option. F OSC : Oscillator clock, FSYS : System clock (FOSC or FOSC /8) MASK OPTION OSC IN DIVIDE-8 OSC F OSC F SYS OSC OUT Figure 6-7 OSC Divide Option 7. Electrical Specifications 7.1 Absolute maximum ratings Symbols Parameters VDD Supply Voltage VI Input Voltage VO Output Voltage T OPR Operating temperature T STG Storage Temperature Conditions Ratings Units -0.3 ~ 6.0 V -0.3 ~ VDD + 0.3 V -0.3 ~ VDD + 0.3 V - -20 ~ 85 ℃ - -40 ~ 125 ℃ Ta=25℃ KSI-W002-000 14 SD6830 7.2 Recommended operating conditions (VDD = 3V ± 10%, Ta=-20 ~ 70℃, unless otherwise noted) Symbols Parameters Min. VDD Supply Voltage 1.8 VIH1 "H" input Voltage, all input pins except OSCIN 0.7VDD VIH2 "H" input Voltage, OSCIN VIL1 VIL2 F OSC Max. Units 3.6 V VDD VDD -V VDD-0.3 VDD VDD V "L" input Voltage, all input pins except OSCIN 0 0 0.3 VDD V "L" input Voltage, OSCIN 0 0 0.3 V Oscillating frequency Typ. Non-divide option 250 1000 KHz Divide-8 option 2 6 MHz 7.3 Electrical characteristics (VDD = 3V ± 10%, Ta= 25℃ , unless otherwise noted) Symbols Parameters 3.0 3.6 V 3.9MHz≤F OSC≤6.0MHz 2.2 3.0 3.6 V "H" output current VO = 2.0V, Port C -6 -9 -14 mA "L" output current VO = 0.4V, Port C 1.5 3 4.5 mA VO = 0.4V, Port C 180 210 240 mA VO = 0.4V, Port F 0.5 1.0 2.0 mA VO = 0.4V, Port G/K 1.5 3.0 4.5 mA VI = VDD, Port D/E - - 3 ㎂ VI = VDD, OSCIN - 3 10 ㎂ -0.6 -3 -10 ㎂ - - 1 ㎂ 30 70 150 KΩ 0.5 1.0 mA 1.0 ㎂ 250 1000 KHz 250 1000 KHz 2 6 MHz IOH IOL0 IOL1 "L" output current IOL3 ILIH2 Typ. Max. Units 1.8 Supply Voltage ILIH1 Min. 250KHz≤F OSC≤3.9MHz VDD IOL2 Test Conditions "H" input leakage current ILIL "L" input leakage current VI = VSS, OSCIN ILOH "H"output leakage current VO = VDD, Port C/F/G/K RPULL-UP Pull-up resistance of input Port VI = 0V, VD D =3V IDD Supply current at normal mode IDDS Supply current at stop mode F SYS Clock frequency F OSC Oscillator frequency Non-divide option Divide-8 option KSI-W002-000 15 SD6830 Packing Outlines and Dimensions 24 SOP-300 0.4160(10.566) 0.3980(10.109) BASE PLANE SEATING PLANE 0.0118(0.300) 0.0040(0.102) 0.2980(7.569) 0.2920(7.417) 0.0500 BSC (1.270) 0.0350(0.889) 0.0160(0.406) 0 ˚~ 8 ˚ 45˚ 0.0160(0.406) 0.0100(0.254) 0.6100(15.494) 0.6040(15.342) 0.0200(0.508) 0.0138(0.351) 0.0125(0.318) 0.0091(0.231) 0.1040(2.642) 0.0940(2.388) UNIT : INCH (MM) 20 SOP-300 0.4160(10.566) 0.3980(10.109) BASE PLANE SEATING PLANE 0.0118(0.300) 0.0040(0.102) 0.2980(7.569) 0.2920(7.417) KSI-W002-000 0.0350(0.889) 0.0160(0.406) 0˚ ~8˚ 0.0160(0.406) 0.0100(0.254) 45˚ 0.5080(12.903) 0.5020(12.751) 0.0200(0.508) 0.0138(0.351) 0.0125(0.318) 0.0091(0.231) 0.0500 BSC (1.270) 8. 0.1040(2.642) 0.0940(2.388) UNIT : INCH (MM) 16 0.145(3.683) 0.135(3.429) KSI-W002-000 0.014(0.356) 0.008(0.200) 0.180(4.572) 0.155(3.937) 3。 ~ 11。 0.100 BSC (2.540) 0.014(0.356) 0.008(0.200) 0.021(0.533) 0.015(0.381) 0.300 BSC (7.620) 0.270(6.858) 0.250(6.350) 0.065(1.650) 0.050(1.270) 0.140(3.556) 0.120(3.048) 3。 ~ 11。 0.090(2.286) 0.070(1.778) 0.145(3.683) 0.135(3.429) 0.300 BSC (7.620) 0.270(6.858) 0.250(6.350) 0.035(0.889) 0.020(0.508) 0.065(1.650) 0.021(0.533) 0.100 BSC 0.050(1.270) 0.015(0.381) (2.540) 1.265(32.131) 1.245(31.623) 0.035(0.889) 0.020(0.508) 0.079(2.007) 0.059(1.499) 1.043(26.492) 1.023(25.984) 2-EJECTION MARK (OPTION 1) SD6830 24 DIP-300 UNIT : INCH (MM) 20 DIP-300 0.140(3.556) 0.120(3.048) 0.180(4.572) 0.155(3.937) UNIT : INCH (MM) 17 SD6830 9. Instructions 9.1 Symbol Description SYMBOL DESCRIPTIONS A , B , L 4 Bit Register H 1-Bit Register Z 3-Bit Register PCH The Higher 4-Bit of the Program Counter PCL The Lower 6-Bit of the Program Counter PC 10-Bit Program Counter ( Consisting of the PCH and PCL ) SK 10-Bit Stack Register CY 1-Bit Carry Flag SF 1-Bit Skip Flag C, G, K 1-Bit Port D, E 4-Bit Port F 8-Bit Port ← Direction of Data Flow M[(HL)] or @HL The Contents of Data Memory Addressed by Reg HL M[(HL)].b or @HL.b The Specified Bit’s Content of Data Memory Addressed by Reg HL @HL+ As a result of execution, increment L by one addr Address n immediate data KSI-W002-000 18 SD6830 9.2 Opcode Map 0001b 0010b 0011b 0100b 0101b 0110b 0111b 1000b~ 1100b~ 1011b 1111b 0h 1h 2h 3h 4h 5h 6h 7h 8h~Bh Ch~Fh ADD n LDA n MSB 0000b LSB 0000b 0h NOP ADDC @HL XCH @HL+ 0001b 1h STOP LDA H XCH @HL LDA E INC L RRC LDA @HL 0010b 2h 0011b 3h STA H 0100b 4h LDA D CLRB H 0101b 5h LDA B SETB H IF0 @HL.b 6h 0111b 7h 1000b 8h CLRB CY STA @HL+ 1001b 9h SETB CY STA @HL NOT Ah CLRB F 1011b Bh SETB F 1100b Ch STA C 1101b Dh LDZ n JMPL addr LDA L 0110b 1010b CALL addr IF0 CY CLRB G RET SETB G 1110b Eh IFEQU n STA B CLRB K 1111b Fh IFEQU @HL STA L SETB K LDL n JMP addr CAL addr CLRB @HL.b SETB @HL.b KSI-W002-000 19 SD6830 9.3 Instruction Descriptions ADD n Binary code : 0110xxxx Syntax : [<label>] ADD n Operation : (A) ← (A) + n, n=0~15 ( n must be decimal number ) Flags : CY: Unaffected. SF: Set to one if carry occurs, cleared otherwise. Words/Cycles : 1/1 Description : Adds an immediate data to the accumulator and stores the result in the accumulate. Example : ADD 8 ; Add 8 to A. JMP 035 ; Jump to 035 if 0≤A≤7 JMP 05F ; Jump to 05F if 8≤A≤15 ADDC @HL Binary code 00010000 Syntax : [<label>] ADDC @HL Operation : (A) ← (A) + M[(HL)] + (CY), (CY) ← Carry Flags : CY: Set on carry-out of (A) + M[(HL)] + (CY) SF: Unaffected Words/Cycles : 1/1 Description : Adds the contents of the accumulator, the contents of data memory addressed by registers H and L, and the carry bit. It stores the result in the accumulator and the carry flag. Example : CLRB LDA CY 5 ; Clear CY to zero ; Load 5 to A CLRB H ; Clear H to zero LDL 6 ; Load 6 to L ADDC @HL ; Add the content of A, M[(06)], and the content of CY CAL addr Binary code : 11xxxxxx Syntax : [<label>] CAL addr Operation : (SK1) ← (SK0), (SK0) ← (PC) + 1, (PCL) ← addr, addr = 000 ~ 03F ( addr must be hexadecimal number ) Flags : CY: Unaffected SF: Unaffected Words/Cycles : 1/1 Description : Calls a subroutine located at the indicated address and pushes the current contents of the program counter to the top of stack. The indicated address must be within the current page. Example : CAL 100 : Call subroutine located at the 100. The 100 must be logical address and within the current page. KSI-W002-000 20 SD6830 CALL addr Binary code : 010100xx Syntax Operation : xxxxxxxx [<label>] CALL addr : (SK1) ← (SK0), (SK0) ← (PC) + 1, (PC) ← addr, addr = 000 ~ 3FF ( addr must be hexadecimal number ) Flags : CY: Unaffected SF: Unaffected Words/Cycles : 2/2 Description : Calls a subroutine located at the indicated address and pushes the current contents of the program counter to the top of stack. The indicated address can be anywhere in the full 1Kbyte memory space. Example : CALL 2FF ; Call subroutine located at the 2FF. The 2FF must be logical address. CLRB @HL.b Binary code : 010110xx Syntax : [<label>] CLRB @HL.b Operation : M[(HL)].b ← 0 Flags : CY: Unaffected SF: Unaffected Words/Cycles : 1/1 Description : Clears the specified bit of data memory addressed by registers H and L to zero. Example : CLRB H LDL ; Clear H to 0 10 CLRB @HL.0 ; Load 10 to L. The 10 must be decimal number. ; Clear the bit 0 of M[(0A)] to 0. CLRB CY Binary code : 00001000 Syntax : [<label>] CLRB CY Operation : (CY) ← 0 Flags : CY: Set to zero SF: Unaffected Words/Cycles: 1/1 Description : Clears the carry flag to zero. Example : CLRB CY ; Clear CY to zero KSI-W002-000 21 SD6830 CLRB F Binary code : 00001010 Syntax : [<label>] CLRB F Operation : F.(L) ← 0 Flags : CY: Unaffected Words/Cycles : 1/1 Description : Clears the specified bit of port F addressed by the lower 3-bit of register SF: Unaffected L to zero. Example : CLRB : Clears the bit 5 of F to zero F LDL 13 ; Load 13 to L CLRB G Binary code : 00101100 Syntax : [<label>] CLRB G Operation : Flags : CY: Unaffected G.(L) ← 0 SF: Unaffected 1/1 Words/Cycles : Description : Clears the port G to zero. Example : CLRB G ; Clear G to zero Binary code : 00100100 Syntax : [<label>] CLRB H Operation : (H) ← 0 Flags : CY: Unaffected CLRB H SF: Unaffected 1/1 Words/Cycles : Description : Clears the contents of register H to zero. Skip this instruction if it or SETB H was used just before. Example : IFEQU 1 CLRB H ; Clear H to zero and skip continuous SETB H/CLRB H, if (A)≠1 SETB H ; Sets H to one and skip continuous SETB H/CLRB H, if (A)=1 KSI-W002-000 22 SD6830 CLRB K Binary code : 00101110 Syntax : [<label>] CLRB K Operation : (K) ← 0 Flags : CY: Unaffected SF: Unaffected 1/1 Words/Cycles : Description : Clears the port K to zero. Example : CLRB K ; Clear K to zero. IF0 @HL.b Binary code : 000001xx Syntax : Operation : M[(HL)b] = 0 Flags : CY: Unaffected [<label>] IF0 @HL.b SF: Set to one if equal, cleared otherwise Words/Cycles 1/1 : Description : Compares the specified bit of data memory addressed by registers H and L with zero. Example : SETB H LDL 4 ; Set H to one ; Load 4 to L IF0 @HL.3 ; Compare the bit 3 of M[(14)] with zero JMP 020 ; Jump to 020 if not equal JMP 030 ; Jump to 030 if equal IF0 CY Binary code : 00011100 Syntax : [<label>] IF0 CY Operation : (CY) = 0 Flags : CY : Unaffected SF : Set to one if equal, cleared otherwise Words/Cycles Description Example : : : 1/1 Compares the carry flag with zero. IF0 CY ; Compare the content of CY to zero JMP 030 ; Jump to 030 if not equal JMP 040 ; Jump to 040 if equal KSI-W002-000 23 SD6830 IFEQU @HL Binary code : 00001111 Syntax : [<label>] IFEQU @HL Operation : (A) = M[(HL)] Flags : CY : Unaffected SF : Set to one if equal, cleared otherwise Words/Cycles Description : : 1/1 Compares the contents of accumulator with the contents of data memory Example : addressed by registers H and L. LDA 14 ; Load 14 to A, and 14 must be decimal number SETB H ; Sets H to one LDL 4 ; Loads 4 to L IFEQU @HL ; Compares 14 with M[(14)] JMP 050 ; Jump to 050 if not equal JMP 060 ; Jump to 060 if equal IFEQU n Binary code : 00001110 0111xxxx Syntax : [<label>] IFEQU n Operation : (A) = n, n = 0 ~15 ( n must be decimal number ) Flags : CY: Unaffected SF: Set to one if equal, cleared otherwise Words/Cycles : Description : Compares the contents of accumulator with an immediate data. Example : 2/2 IFEQU 15 ; Compare the contents of accumulator with 15 JMP 070 ; Jump to 070 if not equal JMP 080 ; Jump to 080 if equal INC L Binary code : 00100010 Syntax : [<label>] INC L Operation : (L) ← (L) + 1 Flags : CY : Unaffect SF:As a result of execution, set to one if the contents of register L are zero, cleared otherwise. Words/Cycles : 1/1 Description : The contents of register L are incremented by one. Example : LDL 14 ; Load 14 to L INC L ; The contents of L are incremented by one INC L ; The contents of L are incremented by one JMP 090 ; It is skipped because the contents of L is JMP 0A0 ; Jump to 0A0 KSI-W002-000 24 SD6830 JMP addr Binary code : 10xxxxxx Syntax : [<label>] JMP addr Operation : (PCL) ← addr, addr = 00 ~ 3F ( addr must be hexadecimal number ) Flags : CY : Unaffected SF : Unaffected Words/Cycles : 1/1 Description : Jumps unconditionally to the indicated address. The indicated address must be within the current page. Example : JMP 2EF ; Jump unconditionally to the 2EF. The 2EF address must be within the current page. JMPL addr Binary code : 010101xx xxxxxxxx Syntax : [<label>] JMPL addr Operation : (PC) ← addr, addr = 000 ~ 3FF (addr must be hexadecimal number. ) Flags : CY : Unaffected SF : Unaffected Words/Cycles : 2/2 Description : Jumps unconditionally to the indicated address. The indicated address can be anywhere in the full 1K-byte memory space. Example : JMPL 100 ; Jump unconditionally to 100 LDA @HL Binary code : 00100011 Syntax : [<label>] LDA @HL Operation : (A) ← M[(HL)] Flags : CY : Unaffected SF : Unaffected Words/Cycles : 1/1 Description : Loads the contents of memory addressed by registers H and L into the accumulator. Example : SETB LDL LDA H 0 ; Set H to 1 ; Load 0 to L @HL ; Load M[(10)] into A KSI-W002-000 25 SD6830 LDA n Binary code : 0111xxxx Syntax : [<label>] LDA n Operation : (A) ← n, n=0~15 ( n must be decimal number. ) Flags : CY : Unaffected SF : Unaffected Words/Cycles : 1/1 Description : Loads an immediate data into the accumulator. Skip this instruction if it was used just before. Example : STA B LDA 15 LDA 4 ; It is skipped because this instruction was used just before LDA 7 ; It is skipped because this instruction was used just before JMP 0B0 ; Load 15 into A. ; Jump to 0B0 LDA B Binary code : 00010101 Syntax : [<label>] LDA B Operation : (A) ← (B) Flags : CY : Unaffected SF : Unaffected Words/Cycles : 1/1 Description : Loads the contents of register B into the accumulator. Example : LDA B ; Load the contents of B into A LDA D Binary code : 00010100 Syntax : [<label>] LDA D Operation : (A) ← (D) Flags : CY : Unaffected SF : Unaffected Words/Cycles : 1/1 Description : Loads the contents of port D into the accumulator. Example : LDA D ; Load the contents of D into A KSI-W002-000 26 SD6830 LDA E Binary code : 00010010 Syntax : [<label>] LDA E Operation : (A) ← (E) Flags : CY : Unaffected SF : Unaffected Words/Cycles : Description : Loads the contents of port E into the accumulator Example 1/1. : LDA E ; Load the contents of E into A LDA H Binary code : 00010001 Syntax : [<label>] LDA H Operation : (A) ← (H) Flags : CY : Unaffected SF : Unaffected Words/Cycles : 1/1 Description : Loads the contents of register H into the bit 0 of accumulator. Example : LDA H ; Load the content of H into the bit 0 of A LDA L Binary code : 00010110 Syntax : [<label>] LDA L Operation : (A) ← (L) Flags : CY : Unaffected SF : Unaffected Words/Cycles : 1/1 Description : Loads the contents of register L into the accumulator. Example : LDA L ; Load the contents of L into A KSI-W002-000 27 SD6830 LDL n Binary code : 0100xxxx Syntax : [<label>] LDL n Operation : (A) ← n, n = 0 ~ 15 ( n must be decimal number ) Flags : CY : Unaffected SF : Unaffected Words/Cycles : 1/1 Description : Loads an immediate data to the register L. Skip this instruction if it was used just before. Example : LDA 3 LDL 8 ; LDL 4 ; It is skipped because this instruction was used just before JMP 0C0 Load 8 to L ; Jump to 0C0 LDZ n Binary code : 00110xxx Syntax : [<label>] LDZ n Operation : (A) ← n, n = 0 ~ 7 ( n must be decimal number ) Flags : CY : Unaffected SF : Unaffected Words/Cycles : 1/1 Description : Load an immediate data into the register Z. Example : LDZ 0 ; Load 0 into Z. The 0 must be decimal number NOP Binary code : 00000000 Syntax : [<label>] NOP Operation : (PC) ← (PC) + 1 Flags : CY : Unaffected SF : Unaffected Words/Cycles : 1/1 Description : No operation. Example : NOP ; No operation KSI-W002-000 28 SD6830 NOT Binary code : 00010111 Syntax : [<label>] NOT Operation : (A) ← /(A) Flags : CY : Unaffected SF : Unaffected Words/Cycles : 1/1 Description The contents of accumulator are 1 Example : : LDA 7 NOT ; 1’s complement 7, then leaves 8 in A RET Binary code : 00011101 Syntax : [<label>] RET Operation : (PC) ← (SK0), (SK0) ← (SK1) Flags : CY: Unaffected SF: Unaffected Words/Cycles : 1/1 Description : Returns from the subroutine to main routine. Example : RET ; Returns from the subroutine to main routine RRC Binary code : 00010011 Syntax : [<label>] RRC Operation : (A.b) ← (A.b+1) (A.3) ← (CY) (CY) ← (A.0) Flags : CY : Set to bit 0 of the accumulator SF : Unaffected Words/Cycles : 1/1 Description : Shifts the contents of accumulator 1-bit to the right through the carry. The carry bit content shifts into the bit 3 of accumulator, and the bit 0 of accumulator is shifted into the carry bit. Example : SETB CY ; Set CY to one. LDA RRC 5 ; Load 5 to A ; CY becomes zero, and the contents of A is 11 KSI-W002-000 29 SD6830 SETB @HL.b Binary code : 010111xx Syntax : [<label>] SETB @HL.b Operation : M[(HL)].b ← 1 Flags : CY : Unaffected SF : Unaffected Words/Cycles : 1/1 Description : Sets the specified bit of memory addressed by registers H and L to one. Example : CLRB H ; Clear H to zero LDL ; 5 SETB @HL.2 Load 5 to L ; Set the bit 2 of M[(05)] to one SETB CY Binary code : 00001001 Syntax : [<label>] SETB CY Operation : (CY) ← 1 Flags : CY : Set to one SF : Unaffected Words/Cycles : 1/1 Description : Sets the contents of carry flag to one. Example : SETB Binary code : 00001011 Syntax : [<label>] SETB F Operation : F.(L) ← 1 Flags : CY : Unaffected CY ; Sets the content of CY to one SETB F SF : Unaffected Words/Cycles : 1/1 Description : Sets the specified bit of the port F addressed by register L to one. Example : LDL 4 ; Loads 4 to L SETB F ; Sets the bit 4 of F to one KSI-W002-000 30 SD6830 SETB G Binary code : 00101101 Syntax : [<label>] SETB G Operation : (G) ← 1 Flags : CY : Unaffected SF : Unaffected Words/Cycles : 1/1 Description : Sets the port G to one. Example : SETB G Binary code : 00100101 Syntax : [<label>] SETB H Operation : (H) ← 1 Flags : CY : Unaffected ; Sets the port G to one SETB H SF : Unaffected Words/Cycles : 1/1 Description : Sets the contents of register H to one. Skip this instruction if it or SETB H was used just before. Example : IFEQU 1 SETB H ; Sets H to one and skip continuous CLRB H/SETB H, if (A)≠1 CLRB H ; Clear H to zero and skip continuous CLRB H/SETB H, if (A)=1 SETB K Binary code : 00101111 Syntax : [<label>] SETB K Operation : (K) ← 1 Flags : CY : Unaffected SF : Unaffected Words/Cycles : 1/1 Description : Sets the port K to one. Example : SETB K ; Sets the port K to one KSI-W002-000 31 SD6830 STA @HL Binary code : 00101001 Syntax : [<label>] STA @HL Operation : M[(HL)] ← (A) Flags : CY : Unaffected SF : Unaffected Words/Cycles : 1/1 Description : Stores the contents of accumulator in memory addressed by registers H and L. Example : LDL 0 ; Load 0 to L SETB H ; STA Set H to one @HL ; Stores the contents of A in M[(10)] STA @HL+ Binary code : 00101000 Syntax : [<label>] STA @HL+ Operation : M[(HL)] ← (A), (L) ← (L) + 1 Flags : CY : Unaffected SF : Unaffected Words/Cycles : 1/1 Description : Stores the contents of accumulator in memory addressed by registers H and L. And then the contents of register L are incremented by one. Example : LDL 15 SETB ; Load 15 to L H ; Set H to one STA @HL+ ; Stores the contents of A in M[(1F)]. L becomes JMP 035 ; JMP 045 ; Jump to 045 It is skipped because L is “0” STA B Binary code : 00011110 Syntax : [<label>] STA B Operation : (B) ← (A) Flags : CY : Unaffected SF : Unaffected Words/Cycles : 1/1 Description : Stores the contents of accumulator in the register B. Example : STA B ; Stores the contents of A in B KSI-W002-000 32 SD6830 STA C Binary code : 00001100 Syntax : [<label>] STA C Operation : (C) ← (A)3 Flags : CY : Unaffected SF : Unaffected Words/Cycles : 1/1 Description : Stores the bit 3 of accumulator in the port C. Example : STA Binary code : 00000011 Syntax : [<label>] STA H Operation : (H) ← (A)0 Flags : CY : Unaffected C ; Stores the bit 3 of A in C STA H SF : Unaffected Words/Cycles : 1/1 Description : Stores the bit 0 of accumulator in the register H. Example : STA Binary code : 00011111 Syntax : [<label>] STA L Operation : (L) ← (A) Flags : CY : Unaffected H ; Store the bit 0 of A in H STA L SF : Unaffected Words/Cycles : 1/1 Description : Stores the contents of accumulator in the register L. Example : STA L ; Stores the contents of A in L KSI-W002-000 33 SD6830 STOP Binary code : 00000001 Syntax : [<label>] STOP Operation : Stop the oscillation of the oscillator, and reset PORT F to zero Flags : CY : Unaffected Words/Cycles : 1/1 Description : Stops the oscillation of the oscillator. Example : STOP Binary code : 00100001 Syntax : [<label>] XCH @HL Operation : (A) ↔ M[(H,L)] Flags : CY : Unaffected SF : Unaffected Words/Cycles : 1/1 Description : Exchanges the accumulator with the contents of the data memory SF : Unaffected XCH @HL addressed by registers H and L without going through an intermediate location. Example : LDL 3 SETB XCH H ; Load 3 to L ; Set H to one @HL ; Exchanges the contents of A with M[(13)] without going through an intermediate location XCH @HL+ Binary code : 00100000 Syntax : [<label>] XCH @HL+ Operation : (A) ↔ M[(H,L)], (L) ← (L) + 1 Flags : CY : Unaffected SF: As a result of execution, set to one if the contents of register L are zero, cleared otherwise Words/Cycles : 1/1 Description : Exchanges the accumulator with the contents of the data memory addressed by registers H and L without going through an intermediate location. As a result of execution, the contents of register L are incremented by one. Example : SETB H ; LDL 15 ; Load 15 into L CH @HL+ ; Exchanges A with M[(1F)] without going through an intermediate location. As a result of execution, the contents of L are “0” JMP 055 ; It is skipped because L is “0” JMP 065 ; Jump to 065 KSI-W002-000 34