Evaluation board available. NX2601 DUAL SYNCHRONOUS PWM CONTROLLER WITH NMOS LDO CONTROLLER & 5V BIAS REGULATOR PRELIMINARY DATA SHEET Pb Free Product DESCRIPTION The NX2601 controller IC is a triple controller with a dual channel synchronous Buck controller IC and an LDO controller designed for multiple converters such as PCIe graphic card applications .The two synchronous PWM controllers are 180 degree out of phase which reduces the input ripple current, allowing to reduce the # of input capacitors.Another main feature of the part is that it can operate from single 12V supply while maintaining a regulated 5V supply for the biasing and the internal drivers. Other features of NX2601 are: programmable frequency from 200kHz to 1MHz, independent digital soft start and enable pins for each controller which allows for different power sequencing, Adaptive driver provides optimized efficiency while maintain sufficient deadband, Vcc undervoltage lock out and current limiting using an Rdson of the external MOSFET with HICCUP feature. FEATURES n Two channel PWM with out of phase operation n Individual digital soft start for two PWM output and LDO controller n Bus voltage operation from 2V to 25V n Hiccup Current limit by sensing Rdson of MOSFET n Adjustable frequency up to 1Mhz per channel n Adaptive deadband time n Three enable pin available allows for independent power sequencing n MLPQ-32L package offers small size n Pb-free and RoHS compliant APPLICATIONS n n n PCI Graphic Card on board converters Vddq Supply in mother board applications On board DC to DC such as 12V to 3.3V, 2.5V or 1.8V FPGA and Set Top Box Applications n 11 REG FB R13 1.65k 47pF C16 10 2N3904 5k M5 VOUT3 +2.5V/2A R18 1.5k R15 C18 0 150pF R16 C19 5k 150uF R17 2.35k R19 1.25k 2N3904 ON R26 10k 7 6.8k LDRV1 ENLDO 2 R28 10k M1 L2 0.78uH R1 10.5k R2 1.5k 22 M2 21 18 C7 2 x (2R5TPD680M6,680uF,6mohm) R3 10.4k C6 2.7nF R5 5k 8.2nF C5 R4 20.8k 220pF C8 1uF +5V D2 17 C11 0.1uF 16 C9 180uF M3 LDRV2 R6 6k M4 19 20 R24 62k PGND2 C21 1nF Fb2 12 13 Comp2 GND VOUT2 +1.8V/10A 15 OCP2 14 VP 31 VREF VIN1 +12V VOUT1 +1.2V@15A 26 C22 PVCC2 C3 100uF C2 180uF C4 0.1uF 25 Fb1 29 28 SW2 R7 820 C14 3 x (4TPE150M,150uF,18mohm) R8 8.7k C13 3.3nF R10 5k 4 Rev. 2.3 12/01/06 L1 1uH L4 1.5uH ENSW2 30 Device NX2601CMTR +5V Comp1 HDRV2 2N3904 6 RT PATENT PENDING PGND1 BST2 R21 1.25k OFF R27 10k ON C1 1uF 24 OCP1 27 LDO FB 1 ENSW1 VIN1 HDRV1 SW1 C25 1uF R20 23 8 LDO OUT 3 OFF R25 10k BST1 AUXVCC 1uF PVCC1 D1 REG OUT 9 C24 5 VCC NX2601 VIN1 C20 150uF C15 1uF R12 5k C17 68uF VIN2 +3.3V TYPICAL APPLICATION R11 10 +5V C23 C12 R9 6.97k 10nF 220pF Figure1 - Typical application of 2601 ORDERING INFORMATION Temperature 0 to 70oC Package MLPQ-32L Frequency 200kHz to 1MHz Pb-Free Yes 1 NX2601 ABSOLUTE MAXIMUM RATINGS Vcc,PVcc & BST to SW voltage ......................... 6.5V BST Voltage ...................................................... 35V SW ................................................................... -5V(Note1) to 35V AUXVCC .......................................................... 35V All other pins .................................................... GND to Vcc+0.3V Storage Temperature Range ............................... -65oC to 150oC Operating Junction Temperature Range ............... -40oC to 125oC CAUTION: Stresses above those listed in "ABSOLUTE MAXIMUM RATINGS", may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. PACKAGE INFORMATION HDRV1 SW1 COMP1 OCP1 FB1 VP NC VREF 32-LEAD 5x5 PLASTIC MLPQ 32 31 30 29 28 27 26 25 ENSW1 1 24 BST1 ENSW2 2 23 PVCC1 ENLDO 3 22 LDRV1 GND 4 VCC 5 21 PGnd1 NX2601 20 PGnd2 RT 6 19 LDRV2 LDO FB 7 18 PVCC2 θJA ≈ 35o C / W 17 BST2 LDO OUT 8 SW2 HDRV2 OCP2 COMP2 FB2 REG FB AUXVCC REG OUT 9 10 11 12 13 14 15 16 ELECTRICAL SPECIFICATIONS Unless otherwise specified, these specifications apply over Vcc = 5V, VBST-VSW =5V, ENSW1=HIGH, ENSW2=HIGH, ENLDO=HIGH, and T A = 0 to 70oC. Typical values refer to T A = 25oC. Low duty cycle pulse testing is used which keeps junction and case temperatures equal to the ambient temperature. PARAMETER SYM TEST CONDITION MIN TYP MAX UNITS Reference Voltage VREF 4.5 < Vcc < 5.5 FB Voltage 0.800 V FB Voltage Line Regulation 0.4 % Vcc Supply Voltage VCC Vcc Voltage Range 5.5 5.0 4.5 V ICC_STA Outputs not switching Vcc Static Supply Current 2.0 mA ICC_DYN Freq=600kHz, Vcc Dynamic Supply 8 mA CLOAD = 3300pF Current 4. VBST VBST Voltage Range 5.5 5.0 4.5 V IBST_STA Outputs not switching VBST Static Supply Current 2.0 mA IBST_DYN Freq = 600KHz, VBST Dynamic Supply TBD mA CLOAD = 3300pF Current Rev. 2.3 12/01/06 2 NX2601 PARAMETER Under Voltage Lockout UVLO Threshold - Vcc UVLO Hysteresis - Vcc UVLO Threshold - VAUXVcc UVLO Hysteresis - VAUXVcc Error Amplifiers Open Loop Gain Input Bias Current Input Offset Voltage Oscillator Frequency SYM VCC_UVLO VCC__HYST VAUX_UVLO VAUX_HYST FS Ramp Amplitude VRAMP EN & SS Soft Start Time TSS Enable Threshold Voltage Enable Hysterises LDO Controller LDO FB Voltage FB Pin Bias Current LDO_out Output Voltage High LDO_out Output Voltage Low Open Loop Gain 5V AUX REG REG FB Voltage FB Pin Bias Current REG_out Output Voltage High REG_out Output Voltage Low Open Loop Gain High Side driver (CL=3300pF) Output Impedance, Sourcing Current Output Impedance , Sinking Current Rise Time Fall Time Deadband Time Rev. 2.3 12/01/06 TEST CONDITION MIN Supply Ramping Up Supply Ramping Down Supply Ramping Up Supply Ramping Down Rt=30k,measured at the output drive Fs=600KHz Enable ramp up LDOOUT=LDOFB AUXVCC=24V,LDO FB=0.7V IO_SOURCE=1.4mA AUXVCC=24V,LDO FB=0.9V IO_SINK=1.4mA GBNT(Note2) -0.2 22 Rsource_H -0.2 22 MAX UNITS 4 0.2 7 0.7 V V V V 65 0.3 0 dB uA mV 600 KHz 1 V 3.41 1.25 100 mS V mV 0.8 0 23.5 V µA V 0.2 V dB 50 REGOUT=REGFB AUXVCC=24V,REG FB=1.1V IO_SOURCE=1.4mA AUXVCC=24V,REG FB=1.4V IO_SINK=1.4mA GBNT(Note2) TYP 1.25 0 23.5 V µA V 0.2 V dB 50 0.85 ohm 0.65 25 20 30 ohm ns ns ns R sink_H THDRV_RISE 10% to 90% THDRV_FALL 90% to 10% TDEAD_LH LDRV going Low to HDRV going High, 10% to 10% 3 NX2601 PARAMETER Low Side driver (CL=3300pF) Output Impedance, Sourcing Current Output Impedance , Sinking Current Rise Time Fall Time Deadband Time SYM TEST CONDITION MIN TYP MAX UNITS Rsource_L 0.85 ohm 0.5 25 20 20 ohm ns ns ns R sink_L TLDRV_RISE 10% to 90% TLDRV_FALL 90% to 10% TDEAD_HL SW going Low to LDRV going High, 10% to 10% Note 1: 500ns transient. This pin can withstand -2V DC. Note 2: This parameter is guaranteed by design but not tested in production(GBNT). Rev. 2.3 12/01/06 4 NX2601 PIN DESCRIPTIONS PIN # PIN SYMBOL 1 ENSW1 2 ENSW2 3 ENLDO 4 GND Analog ground. 5 VCC IC's supply voltage. This pin biases the internal logic circuits. A high freq 1uF ceramic capacitor is placed as close as possible to and connected to this pin and ground pin. 6 RT 7 LDO FB 8 LDO OUT 9 AUXVCC 10 REGOUT RER 11 REGFB 12 FB2 29 FB1 13 COMP2 28 COMP1 Rev. 2.3 12/01/06 PIN DESCRIPTION A resistor divider is connected from the respective switcher BUS voltages to these pins that holds off the controllers soft start until this threshold is reached. An external low cost MOSFET or NPN transisitor can be connected to this pin for external enable control. A resistor divider is connected from the LDO bus voltage to this pin that holds off the LDO soft start until this threshold is reached. An external low cost MOSFET can be connected to this pin for external enable control. Oscillator's frequency can be set by using an external resistor from this pin to GND. This frequency is the master clock frequency which is internally divided by two to set each controller frequency. LDO controller feedback input. If the LDOFB pin is pulled below 0.5*Vref, an internal comparator after certain delay and pulls down LDOOUT pin and initiates the HICCUP circuitry. During the startup this latch is not activated, allowing the LDOFB pin to come up and follow the Soft started Vref voltage. LDO controller output. This pin is controlling the gate of an external NCH MOSFET. The maximum rating of this pin is 16V. This pin is the supply voltage for the LDO controller as well as the 5V regulator controller that regulates the voltage at Vcc derived from the BUS voltage. The maximum voltage applied to this pin is 30V. The output of the 5V regulator controller that drives a low current low cost external BIPOLAR transistor or an external MOSFET to regulate the voltage at Vcc pin derived from BUS voltage. This eliminates an otherwise external regulator needed in applications where 5V is not available. Feedback pin of the 5V regulator controller. A resistor divider is connected from the output of the 5V regulator to this pin to complete the loop. This pin is the error amplifiers inverting input. These pins are connected via resistor dividers to the output of the switching regulators to set the output DC voltage. These pins are the outputs of error amplifiers and are used to compensate the respective voltage control feedback loops. 5 NX2601 PIN DESCRIPTIONS PIN # PIN SYMBOL 14 OCP2 27 OCP1 15 SW2 26 SW1 16 25 HDRV2 HDRV1 17 BST2 24 BST1 18 PVCC2 23 PVCC1 19 22 LDRV2 LDRV1 Low side gate driveroutputs. 20 21 PGND2 PGND1 Powerground pinforlow sidedrivers. 30 VP 31 VREF 32 NC Rev. 2.3 12/01/06 PIN DESCRIPTION This pin is connected to the drain of the external low side MOSFET and is the input of the over current protection(OCP) comparator. An internal current source which equals 1.25V divided by Rt resistor is flown to the external resistor which sets the OCP voltage across the Rdson of the low side MOSFET. Current limit point is this voltage divided by the Rds-on. Once this threshold is reached the Hdrv and Ldrv pins are switched low and an internal hiccup circuit is set that recycles the soft start circuit after 2048 switching cycles. Thesepinsareconnected tosourceofhighside FETsandprovide return path for the high side drivers.Theyare also used to hold the low side driverslow untilthis pin is broughtlow by the action ofhigh side turning off.LDRVs can only go high if SW is below 1V threshold . Highside gate driveroutputs. Thispin suppliesvoltage to highside FET driver.A high freq 1uF ceram iccapacitoris placed as close as possible to and connected to these pins and respected SW pins. Supplyvoltage forthe low side fetdrivers.A high frequency1uF ceram iccapm ust be connected from this pin to the PGND1 and PGND2 pin as close as possible to the pins. Thispin isthe firsterroram plifiernon-inverting input.Thispin shouldbeconnected eithertoanexternalreferencevoltage (tracking application)orto the internalreferencevoltageprovidedbythisdevice. Referencevoltage available.A 100pFcapacitorcan be connected from thispin to GND.This pin is held low untilinternalVccUVLO and the ENSW 1 pin are good, allowing itto softstart. 6 NX2601 BLOCK DIAGRAM AUXVCC Bias REGFB 9.6/9.2 UVLO POR_LDO REGOUT VCC Bias Generator 1.25V 4/3.8 0.8V UVLO POR_SW BST1 Vref ENSW1 DRVH1 1.25/1.15 two phase OSC RT VP Digital start Up SW1 set1 Control Logic ramp1 PVCC1 S R Q POR_SW DRVL1 FB1 PGND1 COMP1 OCP1 Channel 1 PWM Controller OCP comparator BST2 ENSW2 Channel 2 PWM controller (exclude oscillator) FB2 COMP2 DrvH2 SW2 PVCC2 DrvL2 PGND2 OCP2 ENLDO 1.25/1.15 POR_LDO GND Rev. 2.3 12/01/06 LDO control logic digital start up 0.4 LDOOUT FBLDO 7 NX2601 R19 10 VIN1 VIN3 +3.3V VOUT3 +2.5V/2A 11 REG FB R15 1.65k C7 47pF C8 33uF C10 1uF R16 5k C17 68uF R13 5k 10 Q2 9 C5 150uF M5 C4 150uF R10 150pF R11 5k R6 2.35k 7 3 REG OUT AUXVCC HDRV1 VIN1 ENLDO ENSW1 PGND1 C11 0.1uF 25 2 VIN2 PVCC2 HDRV2 ENSW2 R3 1.25k SW2 Q4 R22 10.5k C24 1uF C23 180uF VIN1 +12V C21 39uF L1 0.78uH R23 20k 22 Q5 21 18 5k 8.2nF R24 C17 C12 470pF R26 1.5k C19 2.7nF C13,C14 680uF,6mohm VOUT1 +1.2V@15A R27 10.4k R25 20.8k 220pF C18 C42 1uF +5V 17 LDRV2 R2 62k PGND2 VP Q6 15 R32 3k L4 1uH Q7 20 R33 5k 31 VREF GND C32 C38 1uF C36 180uF L3 1.5uH R34 20k 19 Fb2 12 13 Comp2 R1 1k C31 0.1uF 16 OCP2 14 6 RT 30 L2 1uH 26 Fb1 29 28 Comp1 BST2 R9 C2 100pF +5V VIN2 +5V D2 R4 1.25k C1 100pF C41 1uF 24 OCP1 27 LDO FB R5 1.25k 1 2.7k BST1 LDRV1 R8 6.8k 23 D1 SW1 R7 1.5k PVCC1 8 LDO OUT C3 0 5 VCC NX2601 +5V C34 470pF R28 330 C33 39uF VOUT2 +1.8V@10A C26,27,28 150uF,18mohm R29 3.5k C25 8.2nF C37 10nF R35 2.7k 220pF 4 Simplified Demo board schematic Rev. 2.3 12/01/06 8 NX2601 TP3 Q3 J6 R 19 J7 1 OP 1 SW 1 SW 2 0 0 TP4 1u TP7 C9 R 1 6 6 T P B 68M U 1 L2 Vcc1 4.99k VCC R 13 24 R 20 0 C7 M T D 3055E R 1 2 8 OCP1 AUX_VCC LDO_OUT 0 C3 150pf 32 NC R 10 0 R 11 7 C4 R6 4 T P E 150M 2.35k .1u L D O _ IN R7 3 LD O _O U T PGND1 Fb1 Comp1 1 14 5 15 R9 6 16 L D O _ IN 17 TP6 R2 C1 SW2 2 18 9 19 S W 1 _ IN 10 EN_SW2 OCP2 20 S W 2 _ IN C 35 C 33 OP 16S V P A 39M A A 16S V P A 180M 4 0 Q6 IR F 7822 SW2 15 14 R 32 C 30 6 0 Rt 4 Vp PGND2 Fb2 20 1u 3.5k 100p C 32 Vref 220p Comp2 13 S W 2 _ IN J5 R 29 12 1k 31 op 470p IR F 7822 R1 C2 C 26 C 27 C 28 C 29 C 34 Q7 1 2 DO5010P-222HC PVC C C 42 30 SW2_OUT 20k R 31 19 Ldrv 2 18 PVCC2 J3 L3 R 34 3k op 100p 1k R 30 16 C 31 62k 17 8 C 36 C 38 1u PVC C R 33 C 37 10n R 35 2.7k 1 R 28 C 25 330 8.2nF 4.99k C 40 .1u PACKAGE:MLPQ32L 4 7 L4 DO1603C-102 D2 Hdrv 2 1.25k R 36 S W 2 _ IN 20.8k Vcc2 EN_SW1 AGND S W 2 _ IN 13 TP5 4.99k R3 4 2.7n .1u 2.7k J8 3 1.5k .1u 5 4 3 2 S W 2 _ IN 12 C 19 4T P E 150M R8 1.25k 2 R 26 C 39 R 25 8.2n R 24 28 R4 L D O _ IN C 18 220p BST2 6.8k L D O _ IN 10.4k 29 J4 1 D 1N 5819 S W 1 _ IN 11 R 27 1u C 17 1.25k 1 470p 4T P E 150M 1 2 C 12 C 41 21 EN_LDO R5 IR F 3706 PVC C 1.5k J9 0 1 2 C 13 C 14 C 15 C 16 20k R 21 4T P E 150M C6 LDO_FB C 20 R 23 1 2 3 2 3 4 5 4.99k Q5 10.5k 8 7 6 5 1 op 22 Ldrv 1 23 PVCC1 SW1_OUT DO5010P-781HC R 22 27 J2 L1 O p Q1 REG_OUT IR F 3706 8 7 6 5 9 N X 2601_M L P Q 10 C5 4TP E 150M SW1 SW1 26 5 4 3 2 25 2R 5T P D 680M 6 Hdrv 1 47p TP2 C 21 16S V P A 39M A A Q4 .1u R 15 LD O _O U T C 22 16S V P A 180M OP D 1N 5819 C 11 1.65k J1 1u PVC C R 14 0 C 23 C 24 D1 BST1 2R 5T P D 680M 6 4.99k L D O _ IN REG_Fb 1 2 3 TP1 11 S W 1 _ IN DO1603C-102 O P Q2 C 8 2N3904 16TQ C 33M C 10 PVC C 2 3 4 5 R 18 5 S W 1 _ IN R 17 2 3 4 5 10 Size Document Number Date: T h u rsday, M a rc h 2 4 , 2 0 0 5Sheet S W 2 _ IN Rev A NX2601-02EVL BRD SCHEMATIC 1 of 1 Figure 2 - Demo board schematic based on ORCAD Rev. 2.3 12/01/06 9 NX2601 Bill of Materials Item number Quantity 1 2 3 4 5 6 7 8 9 10 11 Rev. 2.3 12/01/06 2 1 5 5 1 1 1 5 2 2 9 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 2 1 1 2 2 1 1 2 5 3 1 1 2 1 1 1 2 2 1 1 3 1 2 1 2 8 38 39 40 41 42 43 44 45 46 47 48 49 5 1 1 1 2 1 1 1 1 1 1 7 50 1 C2,C1 C3 C4,C5,C26,C27,C28 C6,C11,C31,C39,C40 C7 C8 C9 C10,C24,C38,C41,C42 C12,C34 C14,C13 Q3,R14,C15,C16,C20,C22, C29,C30,C35 C17,C32 C18 C19 C21,C33 C36,C23 C25 C37 D1,D2 J1,J4,J5,J6,J7 J2,J3,J9 J8 L1 L2,L4 L3 Q1 Q2 Q4,Q5 Q7,Q6 R1 R2 R3,R4,R5 R6 R7,R26 R8 R35,R9 R10,R12,R17,R18,R20,R21, R30,R31 R11,R13,R16,R24,R33 R15 R19 R22 R34,R23 R25 R27 R28 R29 R32 R36 TP1,TP2,TP3,TP4,TP5,TP6, TP7 U1 Value 100p 150pf 4TPE150M .1u 47p 16TQC33M 6TPB68M 1u 470p 2R5TPD680M6 OP 220p 8.2n 2.7n 16SVPA39MAA 16SVPA180M 8.2nF 10n D1N5819 SCOPE TP CON2 CON20B DO5010P-781HC DO1603C-102 DO5010P-222HC MTD3055E 2N3904 IRF3706 IRF7822 1k 62k 1.25k 2.35k 1.5k 6.8k 2.7k 0 Manufacture SANYO SANYO SANYO SANYO SANYO SANYO Tektronics Coilcraft International Rectifier International Rectifier 4.99k 1.65k 10 10.5k 20k 20.8k 10.4k 330 3.5k 3k 10k TP NX2601_MLPQ NEXSEM INC. 10 NX2601 Demoboard waveforms Figure 3 - Start up waveform of VCC by internal regulator. Ch1(AUXVCC), Ch3( VCC&PVCC) Figure 6 - Output ripple for power output CH1 and CH2 Figure 4 - Soft start for Channel 1 1.2V and chanel 2 1.8V output Figure 7-Transient response for first channel 1.2V output Figure 5 - Soft start for Channel 1 1.2V and LDO output Figure 8 -Transient reponse for Channel 1. (zoomed) Rev. 2.3 12/01/06 11 NX2601 Demo Board Waveforms (Cont') Figure 9 - Ch2 1.8V output transient 0 to 9A. Figure 12 - Ch1 is short. All channels go into hiccup. Figure 10 - Ch2 1.8V transient (zoomed) Figure 13 - Ch2 is in short. All channels are in hiccup. Figure 11 - Transient response for 2.5V LDO output Rev. 2.3 12/01/06 Figure 14 - LDO in short. All channels go into hiccup. 12 NX2601 APPLICATION INFORMATION Symbol Used In Application Information: VIN - Input voltage VOUT - Output voltage IOUT - Output current = DVRIPPLE - Output voltage ripple FS ∆IRIPPLE = VIN -VOUT VOUT 1 × × L OUT VIN FS 12V-1.2V 1.2V 1 × × = 4.6A 0.78uH 12V 300kHz ...(2) Output Capacitor Selection - Switching frequency Output capacitor is basically decided by the DIRIPPLE - Inductor current ripple amount of the output voltage ripple allowed during steady state(DC) load condition as well as specification for the Design Example load transient. The optimum design may require a couple Power stage design requirements: VOUT=1.2V of iterations to satisfy both condition. Based on DC Load Condition The amount of voltage ripple during the DC load IOUT =15A condition is determined by equation(3). VIN=12V DVRIPPLE<=20mV ∆VRIPPLE = ESR × ∆IRIPPLE + DVTRAN<=100mV @ 15A step FS=300kHz ∆IRIPPLE 8 × FS × COUT ...(3) Where ESR is the output capacitors' equivalent series resistance,COUT is the value of output capacitors. Output Inductor Selection Typically when large value capacitors are selected The selection of inductor value is based on induc- such as Aluminum Electrolytic,POSCAP and OSCON tor ripple current, power rating, working frequency and types are used, the amount of the output voltage ripple efficiency. Larger inductor value normally means smaller is dominated by the first term in equation(3) and the ripple current. However if the inductance is chosen too second term can be neglected. large, it brings slow response and higher cost. Usually For this example, POSCAP are chosen as output the ripple current ranges from 20% to 40% of the output capacitors, the ESR and inductor current typically de- current. This is a design freedom which can be decided termines the output voltage ripple. by design engineer according to various application requirements. The inductor value can be calculated by using ESR desire = the following equations: ∆VRIPPLE 20mV = = 4.3m Ω ∆IRIPPLE 4.6A ...(4) If low ESR is required, for most applications, mul- V -V V 1 L OUT = IN OUT × OUT × ∆IRIPPLE VIN FS IRIPPLE =k × IOUTPUT tiple capacitors in parallel are better than a big capaci...(1) where k is between 0.2 to 0.4. Select k=0.3, then 12V-1.2V 1.2V 1 × × 0.3 × 15A 12V 300kHz L OUT =0.8uH L OUT = Choose LOUT=0.78uH, then coilcraft inductor DO5010P-781HC is a good choice. Current Ripple is calculated as tor. For example, for 20mV output ripple, POSCAP 2R5TPD680M6 with 6mΩ are chosen. N = E S R E × ∆ IR I P P L E ∆ VR IPPLE ...(5) Number of Capacitor is calculated as N= 6m Ω × 4.6A 20mV N =1.38 The number of capacitor has to be round up to a integer. Choose N =2. Rev. 2.3 12/01/06 13 NX2601 If ceramic capacitors are chosen as output capacitors, both terms in equation (3) need to be evaluated to determine the overall ripple. Usually when this type of capacitors are selected, the amount of capacitance per single unit is not sufficient to meet the transient specification, which results in parallel configuration of multiple capacitors. Based On Transient Requirement Typically, the output voltage droop during transient is specified as ∆V droop < ∆V tran @step load DISTEP During the transient, the voltage droop during the transient is composed of two sections. One section is dependent on the ESR of capacitor, the other section is a function of the inductor, output capacitance as well as tiple capacitor in parallel. The number of capacitors can be calculated by the following N= where τ is the a function of capacitor, etc. 0 if L ≤ L crit τ = L × ∆Istep − ESR × COUT V OUT if L ≥ L crit ...(7) where L crit = ESR × COUT × VOUT ESR E × C E × VOUT = ...(8) ∆Istep ∆Istep where ESRE and CE represents ESR and capacitance of each capacitor if multiple capacitors are used in parallel. The above equation shows that if the selected output inductor is smaller than the critical inductance, the voltage droop or overshoot is only dependent on the ESR ...(9) if L ≥ L crit ...(10) sient is 100mV for 15A load step. If the POSCAP 2R5TPD680M6 (680uF, 6mohm ESR) is used, the crticial inductance is given as L crit = ESR E × C E × VOUT = ∆I step 6mΩ × 680µF × 1.2V = 0.33µH 15A enough, the overshoot can be estimated as the following ...(6) VOUT × τ2 2 × L × C E × ∆Vtran For example, assume voltage droop during tran- sient load, if assuming the bandwidth of system is high VOUT × τ2 2 × L × COUT + 0 if L ≤ L crit τ = L × ∆Istep − ESR E × CE V OUT when load from high load to light load with a DISTEP tran- ∆Vovershoot = ESR × ∆Istep + ∆Vtran where input, output voltage. For example, for the overshoot equation. ESR E × ∆Istep The selected inductor is 0.78uH which is bigger than critical inductance. In that case, the output voltage transient not only dependent on the ESR, but also capacitance. number of capacitors is τ= = L × ∆Istep VOUT − ESR E × CE 0.78µH × 15A − 6mΩ× 680µF = 5.67us 1.2V N= ESR E × ∆Istep ∆Vtran + VOUT × τ2 2 × L × CE × ∆Vtran 6mΩ × 15A + 100mV 1.2V × (5.67us) 2 2 × 0.78µH × 680µF × 100mV = 1.3 = of output capacitor. For low frequency capacitor such The number of capacitors has to satisfied both ripple as electrolytic capacitor, the product of ESR and ca- and transient requirement. Overall, we can choose N=2. pacitance is high and L ≤ L crit is true. In that case, the It should be considered that the proposed equa- transient spec is likely to dependent on the ESR of ca- tion is based on ideal case, in reality, the droop or over- pacitor. shoot is typically more than the calculation. The equa- For most cases, the output capacitors are mul- tion gives a good start. For more margin, more capacitors have to choose after the test. Typically, for high Rev. 2.3 12/01/06 14 NX2601 frequency capacitor such as high quality POSCAP es- where FZ1,FZ2,FP1 and FP2 are poles and zeros in pecially ceramic capacitor, 20% up 100% (for ceramic) the compensator. Their locations are shown in figure 15. more capacitors have to be chosen since the ESR of The transfer function of type III compensator is capacitors is so low that the PCB parasitics can affect given by: the results tremendously. More capacitors have to be (1+ sR4 × C2 ) × [1+ s(R2 + R3 ) × C3 ] Ve 1 = × VOUT sR2 × (C2 + C1) (1+ sR × C2 × C1 ) × 1+ sR × C ( 4 3 3) C2 + C1 selected to compensate these parasitic parameters. Compensator Design Due to the double pole generated by LC filter of the power stage, the power system has 180o phase shift , and therefore, is unstable by itself. In order to achieve accurate output voltage and fast transient response, Zin Zf C1 Vout compensator is employed to provide highest possible bandwidth and enough phase margin.Ideally,the Bode R3 R2 plot of the closed loop system has crossover frequency between1/10 and 1/5 of the switching frequency, phase C3 C2 R4 Fb margin greater than 50o and the gain crossing 0db with - Ve 20db/decade. Power stage output capacitors usually R1 decide the compensator type. If electrolytic capacitors Vref are chosen as output capacitors, type II compensator can be used to compensate the system, because the zero caused by output capacitor ESR is lower than crossover frequency. Otherwise type III compensator should A. Type III compensator design For low ESR output capacitors, typically such as Sanyo OSCON and POSCAP, the frequency of ESR zero Gain(db) be chosen. power stage FLC 40dB/decade caused by output capacitors is higher than the crossover frequency. In this case, it is necessary to compensate the system with type III compensator. The following figures and equations show how to realize the type III loop gain FESR compensator by voltage mode amplifier. 1 FZ1 = 2 × π × R 4 × C2 20dB/decade ...(11) compensator FZ2 = 1 2 × π × (R 2 + R3 ) × C3 ...(12) FP1 = 1 2 × π × R3 × C3 ...(13) FP2 = 1 2 × π × R4 × C1 × C2 C1 + C2 ...(14) FZ1 FZ2 FO FP1 FP2 Figure 15 - Type III compensator and its bode plot Rev. 2.3 12/01/06 15 NX2601 The crossover frequency usually is selected as F LC <F O <F ESR, and F O <=1/10~1/5F s for type III 1 2 × π × FZ1 × R 4 C2 = compensator . 1.Calculate the location of LC double pole FLC and ESR zero FESR . FLC = 1 2 × π × L OUT × COUT 1 = 2 × π × 0.78uH × 1320uF = 4.89kHz FESR = 1 2 × π × 0.75 × 4.89kHz × 5k Ω = 8.8nF = Choose C2=8.2nF 6. Calculate C 1 by equation (14) with pole F p2 at half the swithing frequency. 1 2 × π × ESR × COUT 1 2 × π × 3m Ω × 1360uF = 39kHz 1 2 × π × R 4 × FP 2 C1 = 1 2 × π × 5k Ω × 150kHz = 212pF = = Choose C1=220pF 7. Calculate R 3 by equation (13). 2.Set R2 equal to10.4kΩ. R1 = R2 × VREF 10.4kΩ × 0.8V = = 20.8k Ω VOUT -VREF 1.2V-0.8V Choose R1= 20.8kΩ. 3. Set zero FZ2 = FLC and Fp1 =FESR . 4. Calculate R4 and C3 with the crossover frequency smaller than 1/10~ 1/5 of the swithing frequency. Set FO=25kHz. 1 1 1 C3 = ×( ) 2 × π × R2 Fz2 Fp1 1 1 1 = ×( ) 2 × π × 10.4kΩ 4.89kHz 39kHz =2.8nF Choose C3=2.7nF. V 2 × π × FO × L R4 = OSC × × Cout Vin C3 1V 2 × π × 25kHz × 0.8uH × × 1360uF 12V 2.7nF =5.3kΩ = Choose R4=5k 5. Calculate C2 with zero Fz1 at 75% of the LC double pole by equation (11). Rev. 2.3 12/01/06 R3 = 1 2 × π × FP1 × C3 1 2 × π × 39kHz × 2.7nF = 1.5k Ω Choose R3= 1.5kΩ. = B. Type II compensator design If the electrolytic capacitors are chosen as power stage output capacitors, usually the Type II compensator can be used to compensate the system. Type II compensator can be realized by simple RC circuit as shown in figure 16.R3 and C1 introduce a zero to cancel the double pole effect. C2 introduces a pole to suppress the switching noise. The following equations show the compensator pole zero location and constant gain. Gain= R3 R2 ... (15) Fz = 1 2 × π × R3 × C1 ... (16) Fp = 1 2 × π × R3 × C2 ... (17) 16 NX2601 FLC = C2 Vout C1 R3 1 2 × π × L OUT × COUT 1 = R2 2 × π × 1.5uH × 4500uF = 1.94kHz Fb Ve R1 Vref FESR = 1 2 × π × ESR × COUT 1 2 × π × 6.33m Ω × 4500uF = 5.6kHz = Gain(db) power stage 2.Set crossover frequency FO=20kHz>>FESR. 3. Set R2 equal to10kΩ. Based on output voltage, 40dB/decade using equation 18, the final selection of R 1 is 20kΩ. 4.Calculate R3 value by the following equation. loop gain R3= 20dB/decade VOSC 2 × π × FO × L × × R2 V in ESR 1V 2 × π × 20kHz × 1.5uH × × 10kΩ 12V 6.33m Ω =24.8kΩ = Choose R 3 =24.8kΩ. compensator Gain 5. Calculate C1 by setting compensator zero FZ at 75% of the LC double pole. FZ FLC FESR FO FP 1 2 × π × R3 × Fz C1= 1 2 × π × 24.8kΩ × 0.75 × 1.94kHz =4.4nF = Figure 16 - Type II compensator and its bode plot For type II compensator, FO has to satisfy FLC<FESR<<FO<=1/10~1/5Fs. The following parameters are used as an ex- Choose C1=4.7nF. 6. Calculate C 2 by setting compensator pole Fp at half the swithing frequency. ample for type II compensator design, three 1500uF with 19mohm Sanyo electrolytic CAP 6MV1500WGL are used as output capacitors. Coilcraft DO5010P152HC 1.5uH is used as output inductor. The other power stage information is that: VIN=12V, VOUT=1.2V, IOUT =15A, FS=200kHz. 1.Calculate the location of LC double pole F LC C2= 1 π × R 3 × Fs 1 π × 2 4 .8k Ω × 2 0 0 k H z =64pF = Choose C2=68pF and ESR zero FESR. Rev. 2.3 12/01/06 17 NX2601 Output Voltage Calculation Output voltage is set by reference voltage and pacitors supply current to the MOSFETs. Usually 1uF ceramic capacitor is chosen to decouple the high fre- external voltage divider. The reference voltage is fixed quency noise. The bulk input capacitors are decided by at 0.8V. The divider consists of two ratioed resistors voltage rating and RMS current rating. The RMS current so that the output voltage applied at the Fb pin is 0.8V in the input capacitor can be calculated when the output voltage is at the desired value. The following equation and picture show the relationship between VOUT , VREF and voltage divider.. R 1= R 2 × VR E F V O U T -V R E F ...(18) where R2 is part of the compensator, and the value of R1 value can be set by voltage divider. Choose R2=10kΩ, to set the output voltage at 1.8V, the result of R1 is 8kΩ. IRMS = IOUT × D × 1- D D= VOUT VIN ...(19) VIN = 12V, VOUT=1.2V, IOUT=15A, using equation (19), the result of input RMS current is 4.5A. For higher efficiency, low ESR capacitors are recommended. Two Sanyo OS-CON SVPA180M 16V 180uF 29m O with 3.4A RMS rating are chosen as input bulk capacitors. Vout Power MOSFETs Selection R2 Fb The NX2601 requires two N-Channel power MOSFETs. The selection of MOSFETs is based on R1 maximum drain source voltage, gate source voltage, Vref maximum current rating, MOSFET on resistance and power dissipation. The main consideration is the power Voltage divider loss contribution of MOSFETs to the overall converter efficiency. In this design example, two IRFR3706 are Figure 17 - Voltage divider In general, the minimum output load impedance including the resistor divider should be less than 5kΩ to prevent overcharge the output voltage by leakage current (e.g. Error Amplifier feedback pin bias current). A minimum load for 5kΩ less (<1/16w for most of application) is recommended to put at the output. For example, in this application, Vout=1.6V The power loss is 1/16W less RLOAD = 1.6V × 1.6V /(1/16W) = 40Ω Select minimum load is 1kΩ should be good enough. Input Capacitor Selection Input capacitors are usually a mix of high frequency ceramic capacitors and bulk capacitors. Ceramic ca- used. They have the following parameters: VDS=30V, ID =75A,RDSON =9mΩ,QGATE =23nC. There are three factors causing the MOSFET power loss:conduction loss, switching loss and gate driver loss. Gate driver loss is the loss generated by discharging the gate capacitor and is dissipated in driver circuits. It is proportional to frequency and is defined as: Pgate = (QHGATE × VHGS + QLGATE × VLGS ) × FS ...(20) where QHGATE is the high side MOSFETs gate charge,QLGATE is the low side MOSFETs gate charge,VHGS is the high side gate source voltage, and VLGS is the low side gate source voltage. According to equation (3), PGATE =0.07W. This power dissipation should not exceed maximum power dissipation of the driver device. Conduction loss is simply defined as: pacitors bypass the high frequency noise, and bulk ca- Rev. 2.3 12/01/06 18 NX2601 The start up of NX2601 can be programmed through PHCON =IOUT 2 × D × RDS(ON) × K resistor divider at Enable pin. For example, for channel PLCON =IOUT 2 × (1 − D) × RDS(ON) × K ...(21) PTOTAL =PHCON + PLCON 1, if the input bus voltage is 12V and we want NX2601 starts when Vbus is above 8V. We can select where the RDS(ON) will increases as MOSFET junc- R2=1.24k tion temperature increases, K is RDS(ON) temperature (8V − 1.25V) × R 2 = 6.8k Ω 1.25V dependency. As a result, RDS(ON) should be selected for R1 = the worst case, in which K equals to 1.4 at 125oC The NX2601 can be turned off by pulling down the according to IRFR3706 datasheet. Using equation (4), ENable pin by extra signal MOSFET as shown in the the result of PTOTAL is 0.54W. Conduction loss should above Figure. When Enable pin (ENSW1) is below 1.15V, not exceed package rating or overall system thermal the digital soft start is reset to zero. In addition, all the budget. high side is off and output voltage is turned off. Switching loss is mainly caused by crossover conduction at the switching transition. The total switching loss can be approximated. Frequency Selection The frequency can be set by external Rt resistor. 1 × VIN × IOUT × TSW × FS ...(22) 2 where IOUT is output current, T SW is the sum of T R and TF which can be found in mosfet datasheet, and F S is switching frequency. The result of PSW is 1.5W. Swithing loss PSW is frequency dependent. PSW = The relationship between frequency and RT pin is shown as follows. Frequency(kHz) vs. RT amplifier starts to increase, the feedback network will 0 Soft Start and Enable NX2601 has two switching controller and one LDO controller. Each of them has individual digital soft start. Each channel has one enable pin for start up. When the Power Ready (POR) signal is high and the voltage at enable pin is above 1.25V, the internal digital counter Frequency(khz) starts to operate and the voltage at positive input of Error 900 800 700 600 500 400 300 200 100 20 force the output voltage follows the reference and starts the output slowly. After 2048 cycles, the soft start is 30 40 50 60 70 Rt(kohm) complete and the output voltage is regulated to the desired voltage decided by the feedback resistor divider Figure 19 - Frequency versus Rt resistor + Vbus For example, for 300kHz operation, Rt is about POR OFF R1 ENSW1 ON R2 1.25/1.15 Digital start up 10k Figure 18 - Enable and Shut down the NX2601 with Enable pin. Rev. 2.3 12/01/06 62kohm. Over Current Limit Protection Over current limit for step down converter is achieved by sensing current through the low side 19 NX2601 MOSFET. Inside NX2601, the current through Rt pin is important is that MOSFET has to be selected right pack- mirrored and injecting to the pin OCP. Since the current age to handle the thermal capability. For LDO, maxi- through Rt pin is decided as mum power dissipation is given as 1 .2 5 R t IR T = This current is very accurate and does not change with silicon process and temperature, the over current PLOSS = (VLDOIN − VLDOOUT ) × I LOAD = (3.3V − 2.5V) × 2A = 1.6W Select IR MOSFET IRFR3706 with 9mΩ RDSON is sufficient. limit tripping point can be set more accurate than traditional current source. This scheme is the property of LDO Compensation Nexsem. When synchronous FET is on, the voltage at node SW is given as VSW =-IL × RDSON The voltage at pin OCP is given as IOCP × ROCP +VSW The diagram of LDO controller including VCC regulator is shown in above figure 20. For low frequency capacitor such as electrolytic, POSCAP, OSCON, etc, The compensation parameter can be calculated as follows. When the voltage is below zero, the over current CC = occurs. The over current limit can be set by the following g × ESR 1 × m 2 × π × FO × R f1 1+gm × ESR where FO is the desired loop gain. equation ISET = IRT × ROCP /RDSON For example, For 20A current limit and 9mohm Rdson for IRFR3706, the OCP set resistor is calculated as I RT = + LDO input Vref Rf1 1.25V = 20uA 62k ESR Rf2 Rc R OCP = ISET 20A × R DSON = × 9mohm = 9kohm I RT 20uA Rload Cc Co Select OCP set resistor R=10.5k. For NX2601, if one channel goes to hiccup current limit, the other channels include LDO will go to hiccup too. Figure 20 - NX2601 LDO controller. Typically, F O has to be higher than zero caused by LDO Selection Guide NX2601 offers a LDO controller. The selection of ESR. FO is typically around several tens kHz to a few MOSFET to meet LDO is more straight forward. The hundred kHz. For this example, we select Fo=100kHz. selection is that the Rdson of MOSFET should meet gm is the forward trans-conductance of MOSFET. For IRFR3706, gm=53. the dropout requirement. For example. VLDOIN =3.3V Select Rf1=5kohm. VLDOOUT =2.5V Output capacitor is Sanyo POSCAP 4TPE150MI ILoad =2A The maximum Rdson of MOSFET should be R RDSON = (VLDOIN − VLDOOUT ) × I LOAD with 150uF, ESR=18mohm. CC = 1 53 × 18mΩ × =155pF 2 × π × 100kHz × 5kΩ 1+53 × 18mΩ = (3.3V − 2.5V) / 2A = 0.4Ω Most of MOSFETs can meet the requirement. More Rev. 2.3 12/01/06 Choose CC=150pF. 20 NX2601 For electrolytic or POSCAP, RC is typically selected to be zero. Rf2 is determined by the desired output voltage R f 2 = R f 1 × VREF /(VLDOOUT − VREF ) = 5kΩ × 0.8V /(2.5V − 0.8) = 2.35kΩ Choose Rf2=2.34kΩ. Current Limit for LDO Current limit of LDO is achieved by sensing the as to the load as possible and plane connection is required. 4. Drain of the low-side MOSFET and source of the high-side MOSFET need to be connected thru a plane ans as close as possible. A snubber nedds to be placed as close to this junction as possible. 5. Source of the lower MOSFET needs to be connected to the GND plane with multiple vias. One is not enough. This is very important. The same applies to the output capacitors and input capacitors. LDO feedback voltage. When LDO_FB pin is below 0.4V, 6. Hdrv and Ldrv pins should be as close to the IC goes into hiccup mode. The IC will turn off all the MOSFET gate as possible. The gate traces should be channel (Channel 1 and Channel 2 ) for 2096 cycles and wide and short. A place for gate drv resistors is needed start to restart system again. to fine tune noise if needed. 7. Vcc capacitor, BST capacitor or any other by- Layout Considerations The layout is very important when designing high frequency switching converters. Layout will affect noise pickup and can cause a good design to perform with less than expected results. There are two sets of components considered in the layout which are power components and small signal components. Power components usually consist of input capacitors, high-side MOSFET, low-side MOSFET, inductor and output capacitors. A noisy environment is generated by the power components due to the switching power. Small signal components are connected to sensitive pins or nodes. A multilayer layout which includes power plane, ground plane and signal plane is recommended . Layout guidelines: 1. First put all the power components in the top layer connected by wide, copper filled areas. The input passing capacitor needs to be placed first around the IC and as close as possible. The capacitor on comp to GND or comp back to FB needs to be place as close to the pin as well as resistor divider. 8. The output sense line which is sensing output back to the resistor divider should not go through high frequency signals. 9. All GNDs need to go directly thru via to GND plane. 10. The feedback part of the system should be kept away from the inductor and other noise sources, and be placed close to the IC. 11. In multilayer PCB, separate power ground and analog ground. These two grounds must be connected together on the PC board layout at a single point. The goal is to localize the high current path to a separate loop that does not interfere with the more sensitive analog control function. capacitor, inductor, output capacitor and the MOSFETs should be close to each other as possible. This helps to reduce the EMI radiated by the power loop due to the high switching currents through them. 2. Low ESR capacitor which can handle input RMS ripple current and a high frequency decoupling ceramic cap which usually is 1uF need to be practically touching the drain pin of the upper MOSFET, a plane connection is a must. 3. The output capacitors should be placed as close Rev. 2.3 12/01/06 21 NX2601 TYPICAL APPLICATIONS R11 10 +5V 11 REG FB R13 1.65k 47pF C16 10 2N3904 C24 C20 150uF VOUT3 +2.5V/2A M5 R15 C19 150uF 9 1uF C18 0 150pF R16 5k R17 2.35k R18 OFF R25 10k ON R26 10k PVCC1 BST1 REG OUT AUXVCC HDRV1 SW1 7 LDRV1 R19 1.25k R20 PGND1 6.8k PVCC2 HDRV2 OFF ON R27 10k 6.8k 2N3904 R28 10k VIN1 +12V C4 0.1uF 25 M1 C3 100uF L2 1.5uH VOUT1 +1.2V@15A 26 R1 10.5k C7 3 x (1500uF,19mohm) R3 10k 22 M2 21 28 C5 R5 R4 20.8k 18 C8 1uF 68pF +5V 17 C11 0.1uF 16 C9 180uF M3 L4 1.5uH ENSW2 SW2 R23 1.25k LDRV2 6 RT PGND2 VP 31 VREF R6 3k C14 2 x (1500uF,19mohm) M4 19 20 Fb2 12 13 30 R10 C12 25k 4.7nF Comp2 GND 4 VOUT2 +1.6V/10A 15 OCP2 14 R24 100k C21 1nF C2 180uF 24.8k 4.7nF C22 BST2 2 L1 1uH D2 R21 1.25k R22 +5V Fb1 29 Comp1 1 ENSW1 VIN1 C1 1uF 24 OCP1 27 LDO FB ENLDO 23 D1 8 LDO OUT 3 1.5k C25 1uF 2N3904 5 VCC NX2601 VIN1 VIN2 +3.3V C15 1uF R12 5k C17 68uF C23 R8 10k R9 10k 68pF Figure 21 - NX2601 application with electrolytic capacitors as output capacitors Rev. 2.3 12/01/06 22 NX2601 TYPICAL APPLICATIONS(cont') R11 10 +5V 11 REG FB R13 1.65k 10k VIN1 C16 33pF 10 2N3904 9 VIN2 +3.3V C24 C20 10uF VOUT3 +2.5V/2A M5 1uF R15 2.5k R16 5k C19 47uF C18 100pF OFF R25 10k 1.5k C25 1uF 2N3904 R26 10k 5 VCC PVCC1 BST1 REG OUT AUXVCC HDRV1 SW1 7 LDO FB LDRV1 ENLDO R19 1.25k PGND1 ON R27 10k 6.8k 2N3904 R28 10k PVCC2 BST2 M1 L2 0.68uH 26 R1 10.5k R2 440 22 M2 21 C6 1.2nF 28 18 C5 R5 C8 1uF VOUT1 +1.2V@10A R3 11k R4 22k 3.9nF C22 C7 6 x 47uF 100pF +5V 17 C11 0.1uF 16 C9 39uF M3 L4 2.2uH ENSW2 SW2 R23 1.25k 15 OCP2 14 LDRV2 6 RT R24 30k PGND2 VP 31 VREF R6 3k M4 19 20 Fb2 12 13 30 C21 1nF C4 0.1uF 25 5k HDRV2 OFF VIN1 +12V C3 100uF C2 180uF D2 R21 1.25k 2 L1 1uH Fb1 29 Comp1 1 ENSW1 R22 +5V 24 OCP1 27 R20 6.8k C1 1uF 8 LDO OUT 3 VIN1 23 D1 R17 2.35k R18 ON C15 1uF R12 5k R29 NX2601 C17 2.2uF C6 1.2nF R10 C12 Comp2 GND 4 R7 440 5k C23 3.9nF C14 2 x47uF VOUT2 +1.8V/5A R8 11k R9 8.9k 100pF Figure 22 - NX2601 application with ceramic capacitors as output capacitors Rev. 2.3 12/01/06 23 NX2601 MLPQ 32 PIN 5 x 5 PACKAGE OUTLINE DIMENSIONS D D2 D/2 E/2 D2/2 E2/2 E E2 e L R 2 1 Exposed Pad N N-1 TOP VIEW B A BTM VIEW SEATING PLANE A1 A3 SIDE VIEW SYMBOL NAME A A1 A3 B D D2 E E2 e L R ND NE MIN 0.80 0.00 0.18 3.30 3.30 0.30 0.09 32 PIN 5 x 5 NOM 0.90 0.02 0.20REF 0.25 5.00BSC 3.45 5.00BSC 3.45 0.50BSC 0.40 --6 6 MAX 1.00 0.05 0.30 3.55 3.55 0.50 --- NOTE: ALL DIMENSIONS ARE DISPLAYED IN MILLIMETERS. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY. Rev. 2.3 12/01/06 24 NX2601 MLPQ 32 PIN 5 x 5 TAPE AND REEL INFORMATION NOTE: 1. R7 = 7 INCH LOCK REEL, R13 = 13 INCH LOCK REEL. 2. ALL DIMENSIONS ARE DISPLAYED IN MILLIMETERS. Rev. 2.3 12/01/06 25