SAMSUNG S3P9428

S3C9424/C9428/P9428
1
PRODUCT OVERVIEW
PRODUCT OVERVIEW
SAM87RI PRODUCT FAMILY
Samsung’s SAM87Ri family of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide
range of integrated peripherals, and various mask-programmable ROM sizes.
A address/data bus architecture and a large number of bit-configurable I/O ports provide a flexible programming
environment for applications with varied memory and I/O requirements. Timer/counters with selectable operating
modes are included to support real-time operations.
S3C9424/C9428/P9428 MICROCONTROLLER
The S3C9424/C9428/P9428 single-chip 8-bit microcontroller is fabricated using an advanced CMOS process. It is
built around the powerful SAM87Ri CPU core. The S3C9424/C9428/P9428 is a versatile microcontroller, with its
A/D converter, SIO, IIC and a zero-crossing detection capability it can be used in a wide range of general
purpose applications.
Stop and Idle power-down modes were implemented to reduce power consumption. To increase on-chip register
space, the size of the internal register file was logically expanded. The S3C9424/C9428/P9428 have 4K-byte or
8K-byte of program memory on-chip (ROM) and 208-bytes of general purpose register area RAM.
Using the SAM87Ri design approach, the following peripherals were integrated with the SAM87Ri core:
•
Four configurable I/O ports (24 pins)
•
Nine interrupt sources with one vector and one interrupt level
•
Two 8-bit timer/counter with various operating modes
•
Analog to digital converter with 12 input channels and 10-bit resolution
•
One synchronous SIO module
•
One IIC module
•
Two 12-bit PWM output
The S3C9424/C9428/P9428 microcontroller is ideal for use in a wide range of electronic applications requiring
simple timer/counter, PWM, ADC, SIO, IIC, ZCD and capture functions. S3C9424/C9428/P9428 is available in a
28/32-pin SOP and a 30-pin SDIP package.
OTP
The S3P9428 is an OTP (One Time Programmable) version of the S3C9424/C9428 microcontroller. The
S3P9428 has on-chip 8-K-byte one-time-programmable EPROM instead of masked ROM. The S3P9428 is fully
compatible with the S3C9424/C9428, in function, in D.C. electrical characteristics and in pin configuration.
1-1
PRODUCT OVERVIEW
S3C9424/C9428/P9428
FEATURES
CPU
Timer/Counters
•
•
One 8-bit basic timer for watchdog function
•
One 8-bit timer/counter with three operating
mode
•
One 8-bit timer/counter
SAM87RI CPU core
Memory
•
208-byte general purpose register area (RAM)
•
4K/8K byte internal program memory (ROM)
PWM module
Instruction Set
•
12-bit PWM 2-ch (Max: 250KHz)
•
41 instructions
•
6-bit base + 6-bit extension frame
•
The SAM87RI core provides all the SAM87 core
instruction except the word-oriented instruction,
multiplication, division, and some one-byte
instruction
•
One 8-bit timer/counter
Instruction Execution Time
•
A/D Converter
•
12 analog input pins
•
10-bit conversion resolution
375 ns at 16 MHz fosc(minimum)
Buzzer Frequency Range
Interrupts
•
9 interrupt sources and 1 vector
•
One interrupt level
•
Oscillator Freqeuncy
•
1-MHz to 16-MHz external crystal oscillator
Maximum 16-MHz CPU clock
•
RC: 4MHz(typ)
General I/O
•
Four I/O ports (total 24pins)
•
Bit programmable ports
Serial I/O
•
One synchronous serial I/O module
•
Selectable transmit and receive rates
Multi-Master IIC-Bus
•
Serial peripheral interface
Zero-Crossing Detection Circuit
•
Zero crossing detection circuit that generates a
digital signal in synchronism with an AC signal
input
Built-in reset Circuit (LVD)
•
1-2
Low voltage detector for safe reset
200 Hz to 20 kHz signal can be generated
Operating Temperature Range
•
– 40°C to + 85°C
Operating Voltage Range
•
3.0 V to 5.5 V (LVD)
•
1.8 V to 5.5 V (No LVD)
OTP Interface Protocol Spec
•
Serial OTP
Package Types
•
S3C9424/C9428
32-pin SOP-450 (3V LVD)
30-pin SDIP-400 (3V LVD)
28-pin SOP-375
S3C9424/C9428/P9428
PRODUCT OVERVIEW
BLOCK DIAGRAM
Basic
Timer
XIN
XOUT
T0 (CAP)
T0(PWM)
P0.0-P0.7
SCK,SO, SI, AD8-AD11
P1.0-P1.3
T0, BUZ, INT0, INT1
Port 0
Port 1
OSC
Timer 0
Port I/O and Interrupt
Control
Timer 1
Port 2
P2.0-P2.7
AD0-AD7
Port 3
P3.0-P3.3
ADC
P1.1/BUZ
BUZ
IIC
P2.7/SCLK
P2.6/SDAT
P0.7/PWM0
P1.3/PWM1
PWM
SIO
P0.0/SCK
P0.1/SO
P0.2/SI
SAM87RI CPU
4K/8K ROM
208-Byte
Register File
ZCD
ZCD
AD0-AD11
Figure 1-1. Block Diagram
1-3
PRODUCT OVERVIEW
S3C9424/C9428/P9428
PIN ASSIGNMENTS
VSS
XIN
XOUT
TEST
P0.1/SO
P0.0/SCK
RESET
P3.0
P3.2
P2.0/AD0
P2.1/AD1
P2.2/AD2
P2.3/AD3
P2.4/AD4
P2.5/AD5
AVSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
S3C9424/C9428
32-SOP
(Top View)
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VDD
P0.2/SI
P0.3/CLO
P0.4/AD8
P0.5/AD9
P0.6/AD10
P0.7/AD11/PWM0
P3.1
P3.3
P1.0/T0/ZCD
P1.1/BUZ
P1.2/INT0
P1.3/INT1/PWM1
P2.7/AD7/SCLK
P2.6/AD6/SDAT
AVREF
Figure 1-2. Pin Assignment Diagram (32-Pin SOP Package)
1-4
S3C9424/C9428/P9428
PRODUCT OVERVIEW
PIN ASSIGNMENTS (Continued)
VSS
XIN
XOUT
TEST
P0.1/SO
P0.0/SCK
RESET
P3.0
P2.0/AD0
P2.1/AD1
P2.2/AD2
P2.3/AD3
P2.4/AD4
P2.5/AD5
AVSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
S3C9424/C9428
30-SDIP
(Top View)
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
VDD
P0.2/SI
P0.3/CLO
P0.4/AD8
P0.5/AD9
P0.6/AD10
P0.7/AD11/PWM0
P3.1
P1.0/T0/ZCD
P1.1/BUZ
P1.2/INT0
P1.3/INT1/PWM1
P2.7/AD7/SCLK
P2.6/AD6/SDAT
AVREF
Figure 1-3. Pin Assignment Diagram (30-Pin SDIP Package)
VSS
XIN
XOUT
TEST
P0.1/SO
P0.0/SCK
RESET
P2.0/AD0
P2.1/AD1
P2.2/AD2
P2.3/AD3
P2.4/AD4
P2.5/AD5
AVSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
S3C9424/C9428
28-SOP
(Top View)
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDD
P0.2/SI
P0.3/CLO
P0.4/AD8
P0.5/AD9
P0.6/AD10
P0.7/AD11/PWM0
P1.0/T0/ZCD
P1.1/BUZ
P1.2/INT0
P1.3/INT1/PWM1
P2.7/AD7/SCLK
P2.6/AD6/SDAT
AVREF
Figure 1-4. Pin Assignment Diagram (28-Pin SOP Package)
1-5
PRODUCT OVERVIEW
S3C9424/C9428/P9428
PIN DESCRIPTIONS
Table 1-1. S3C9424/C9428/P9428 Pin Descriptions
Pin
Names
P0.0-P0.7
P1.0-P1.3
Pin
Type
I/O
I/O
Pin Description
Bit-programmable I/O port for Schmitt trigger input or pushpull, open-drain output. Pull-up resistors are assignable by
software.
Pin
Type
Share
Pins
E
SCK,SO,SI
, CLO,
AD8-AD11
E-1
Bit-programmable I/O port for Schmitt trigger input or pushpull output.
Pull-up resistors are assignable by software. Port 1 pins can
also be used as alternative functions.
D
T0/ZCD
BUZ
INT0
INT1
P2.0-P2.7
I/O
Bit-programmable I/O port for Schmitt trigger input or pushpull, open drain output. Pull up resistors are assignable by
software. Port 2 can also be used as external interrupt, A/D
input.
E-1
AD0-AD7
P3.0-P3.3
O
Push-pull or open-drain output port.
Pull-up resistors are assignable by software.
E-2
–
XIN, XOUT
–
Crystal/ceramic, or RC oscillator signal for system clock.
–
–
RESET
I
System RESET signal input pin.
B
–
TEST
I
Test signal input pin (for factory use only: must be connected
to VSS)
–
–
AVREF, AVSS
–
A/D converter reference voltage input and ground
–
–
VDD, VSS
–
Voltage input pin and ground
–
–
SCK
I/O
Serial interface clock input or output
E
P0.0
SO
O
Serial data output
E
P0.1
SI
I
Serial data output
E
P0.2
CLO
O
System clock output port
E
P0.3
SCLK
SDAT
I/O
IIC CLOCK
IIC DATA
E-1
P2.7
P2.6
BUZ
O
200 Hz-20 kHz frequency output for buzzer sound.
D
P1.1
ZCD
I
Zero crossing detector input
D
P1.0
Timer 0 capture input or 10-bit PWM output
D
P1.0
D
P1.2
P1.3
T0
I/O
INT0
INT1
I
External interrupt input
PWM0
PWM1
O
12-bit PWM output
E-1
D
P0.7
P1.3
AD0-AD11
I
A/D converter input
E-1
P2.0-P2.7
P0.4-P0.7
1-6
S3C9424/C9428/P9428
PRODUCT OVERVIEW
PIN CIRCUITS
VDD
VDD
P-Channel
P-Channel
Data
In
Out
N-Channel
Figure 1-5. Pin Circuit Type A
N-Channel
Output
DIsable
Figure 1-7. Pin Circuit Type C
Last Developing: 99.02.02
VDD
Pull-up
Resistor
VDD
Pull-Up
Resistor
In
Resistor
Enable
Data
Output
DIsable
P-Channel
Circuit
Type C
I/O
Data
Figure 1-6. Pin Circuit Type B
Figure 1-8. Pin Circuit Type D
1-7
PRODUCT OVERVIEW
S3C9424/C9428/P9428
VDD
PNE
VDD
PNE
47K
VDD
Pull-up
Enable
I/O
P-CH
Data
Pull-up
Enable
Data
N-CH
Output
Disable
VDD
Pull-up
Resistor
Out
Output
Disable
Input
Figure 1-11. Pin Circuit Type E-2
Figure 1-9. Pin Circuit Type E
VDD
PNE
VDD
Pull-up
Resistor
P-CH
Data
N-CH
Output
Disable
Input
Analog Input
Figure 1-10. Pin Circuit Type E-1
1-8
Pull-up
Enable
I/O
S3C9424/C9428/P9428
16
ELECTRICAL DATA
ELECTRICAL DATA
OVERVIEW
In this section, the following S3C9424/C9428/P9428 electrical characteristics are presented in tables and graphs:
— Absolute maximum ratings
— D.C. electrical characteristics
— A.C. electrical characteristics
— Operating Voltage Range
— Schmitt trigger input characteristics
— Oscillator characteristics
— Oscillation stabilization time
— Data retention supply voltage in Stop mode
— Stop mode release timing when initiated by a RESET
— Power-on RESET circuit characteristics
— A/D converter electrical characteristics
— Zero-crossing detector
— Zero Crossing Waveform Diagram
16-1
ELECTRICAL DATA
S3C9424/C9428/P9428
Table 16-1. Absolute Maximum Ratings
(TA = 25°C)
Parameter
Supply voltage
Symbol
Conditions
Rating
Unit
VDD
–
– 0.3 to + 6.5
V
Input voltage
VI
All input ports
– 0.3 to VDD + 0.3
V
Output voltage
VO
All output ports
– 0.3 to VDD + 0.3
V
Output current
I OH
One I/O pin active
– 25
mA
All I/O pins active
– 80
One I/O pin active
+ 30
Total pin current for ports 1, 2, 3
+ 100
Total pin current for ports 0
+ 200
high
Output current
I OL
low
mA
Operating
temperature
TA
–
– 40 to + 85
°C
Storage
temperature
TSTG
–
– 65 to + 150
°C
16-2
S3C9424/C9428/P9428
ELECTRICAL DATA
Table 16-2. D.C. Electrical Characteristics(30SDIP, 32SOP)
(TA = – 40°C to + 85°C, VDD = 3.0 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
0.8 VDD
–
VDD
V
–
0.2 VDD
V
VIH1
Ports 0, 1, 2 and
VIH3
XIN and XOUT
VIL1
Ports 0, 1, 2 and
VIL2
XIN and XOUT
Output high
voltage
VOH
IOH = – 10 mA
ports 0-3
VDD= 4.5 to 5.5 V
VDD – 1.5
VDD –
0.4
–
V
Output low
voltage
VOL
IOL = 25 mA
port 0-3
VDD= 4.5 to 5.5 V
–
0.4
2.0
V
Input high
leakage current
ILIH1
All input pins except VIN = VDD
ILIH2
–
–
1
µA
ILIH2
XIN, XOUT
ILIL1
All input pins except VIN = 0 V
ILIL2 and RESET
ILIL2
XIN, XOUT
VIN = 0 V
Output high
leakage current
ILOH
All output pins
VOUT = VDD
–
–
2
µA
Output low
leakage current
ILOL
All output pins
VOUT = 0 V
–
–
–2
µA
Pull-up resistor
RP
VIN = 0 V Port 0-2
VDD = 5 V
30
47
70
KΩ
RESET
VDD = 5 V
100
200
350
–
11
20
1.5
4
3
8
0.5
2
65
100
45
80
Input high
voltage
Input low
voltage
Input low
leakage current
Supply current
IDD1
IDD2
IDD3
RESET
RESET
VDD= 3.0 to 5.5 V
VDD – 0.1
VDD= 3.0 to 5.5 V
–
0.1
VIN = VDD
RUN mode 16-MHz VDD = 4.5 to 5.5 V
CPU clock
4-MHz CPU clock
VDD = 3 V
Idle mode 16-MHz
CPU clock
VDD = 4.5 to 5.5 V
4-MHz CPU clock
VDD = 3.3 V
Stop mode
VDD = 4.5 to 5.5 V
VDD = 3.3 V
20
–
–
–1
µA
– 20
–
–
mA
µA
NOTE: D.C. electrical values for Supply current (IDD1 to IDD3) do not include current drawn through internal pull-up
resisters, output port drive current, ZCD and ADC.
16-3
ELECTRICAL DATA
S3C9424/C9428/P9428
Table 16-3. D.C. Electrical Characteristics (28SOP)
(TA = – 40°C to + 85°C, VDD = 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
0.8 VDD
–
VDD
V
–
0.2 VDD
V
VIH1
Ports 0, 1, 2 and
VIH3
XIN and XOUT
VIL1
Ports 0, 1, 2 and
VIL2
XIN and XOUT
Output high
voltage
VOH
IOH = – 10 mA
ports 0-3
VDD= 4.5 to 5.5 V
VDD – 1.0
VDD –
0.4
–
V
Output low
voltage
VOL
IOL = 25 mA
port 0-3
VDD= 4.5 to 5.5 V
–
0.4
2.0
V
Input high
leakage current
ILIH1
All input pins except VIN = VDD
ILIH2
–
–
1
µA
ILIH2
XIN, XOUT
ILIL1
All input pins except VIN = 0 V
ILIL2 and RESET
ILIL2
XIN, XOUT
VIN = 0 V
Output high
leakage current
ILOH
All output pins
VOUT = VDD
–
–
2
µA
Output low
leakage current
ILOL
All output pins
VOUT = 0 V
–
–
–2
µA
Pull-up resistor
RP
VIN = 0 V Port 0-2
VDD = 5 V
30
47
70
KΩ
RESET
VDD = 5 V
100
200
350
–
11
20
1
3
3
9
0.3
1.0
0.1
5
Input high
voltage
Input low
voltage
Input low
leakage current
Supply current
IDD1
IDD2
IDD3
RESET
RESET
VDD= 1.8 to 5.5 V
VDD – 0.1
VDD= 1.8 to 5.5 V
–
0.1
VIN = VDD
RUN mode 16-MHz VDD = 4.5 to 5.5 V
CPU clock
3-MHz CPU clock
VDD = 1.8 to 2.2 V
Idle mode 16-MHz
CPU clock
VDD = 4.5 to 5.5 V
3-MHz CPU clock
VDD = 1.8 to 2.2 V
Stop mode
VDD = 4.5 to 5.5 V
20
–
–
–1
– 20
–
–
VDD = 3 V
VDD = 1.8 to 2.2 V
NOTE: D.C. electrical values for Supply current (IDD1 to IDD3) do not include current drawn through internal pull-up
resisters, output port drive current, ZCD and ADC.
16-4
µA
mA
µA
S3C9424/C9428/P9428
ELECTRICAL DATA
Table 16-4. A.C. Electrical Characteristics
(TA = –40°C to + 85°C, VDD = 1.8 V to 5.5 V)
Parameter
Interrupt input
high, low width
RESET input
low width
Symbol
tINTH,
tINTL
tRSL
–
Conditions
Min
Typ
Max
Unit
Port 1v(INT0, INT1)
VDD = 5V ± 10%
–
200
–
ns
Input
VDD = 5V ± 10%
–
1
–
us
1/tCPU
tINTL
tINTH
tRSL
0.8 VDD
0.2 VDD
NOTE:
The unit tcpu means one CPU clock period.
Figure 16-1. Input Timing Measurement Points
16-5
ELECTRICAL DATA
S3C9424/C9428/P9428
CPU Clock
16MHz
8MHz
4MHz
3MHz
2MHz
1MHz
1 1.8 2 2.7 3
4 4.5 5 5.5 6
7
Supply Voltage (V)
Figure 16-2. Operating Voltage Range (KS86C4204/C4208)
VOUT
VDD
A = 0.2 VDD
B = 0.4 VDD
C = 0.6 VDD
D = 0.8 VDD
VSS
A
B
0.3 VDD
C
D
VIN
0.7 VDD
Figure 16-3. Schimtt Trigger Input Characteristic Diagram
16-6
S3C9424/C9428/P9428
ELECTRICAL DATA
Table 16-5. Oscillator Characteristics (30SDIP, 32SOP)
(TA = – 40°C to + 85°C)
Oscillator
Main crystal or
ceramic
Clock Circuit
XIN
XOUT
C1
External clock
(Main system)
RC oscillator
Test Condition
Min
Typ
Max
Unit
VDD = 4.5 to 5.5 V
VDD = 3.0 to 4.5 V
1
1
–
–
16
8
MHz
VDD = 4.5 to 5.5 V
VDD = 3.0 to 4.5 V
1
1
–
–
16
8
VDD = 4.75 to 5.25 V
–
4
–
Min
Typ
Max
Unit
1
1
1
–
–
–
16
8
3
MHz
VDD = 4.5 to 5.5 V
VDD = 2.7 to 4.5 V
VDD = 1.8 to 2.7 V
1
1
1
–
–
–
16
8
3
VDD = 4.75 to 5.25 V
–
4
–
C2
XIN
XIN
XOUT
XOUT
Tolerance: 10%
R
Table 16-6. Oscillation Stabilization Time (28SOP)
(TA = – 40°C to + 85°C)
Oscillator
Main crystal or
ceramic
Clock Circuit
XIN
XOUT
C1
External clock
(Main system)
RC oscillator
Test Condition
VDD = 4.5 to 5.5 V
VDD = 2.7 to 4.5 V
VDD = 1.8 to 2.7 V
C2
XIN
XOUT
XIN
XOUT
R
Tolerance: 10%
16-7
ELECTRICAL DATA
S3C9424/C9428/P9428
Table 16-7. Oscillation Stabilization Time
(TA = – 40°C to + 85°C, VDD = 1.8 V to 5.5 V)
Oscillator
Test Condition
Min
Typ
Max
Unit
ms
Main crystal
fosc > 1.0 MHz
–
–
20
Main ceramic
Oscillation stabilization occurs when VDD is equal
to the minimum oscillator voltage range.
–
–
10
External clock
(main system)
XIN input high and low width (tXH, tXL)
25
–
500
ns
Oscillator
stabilization
tWAIT when released by a reset (1)
–
216/fosc
–
ms
wait time
tWAIT when released by an interrupt (2)
–
–
–
NOTES:
1. fosc is the oscillator frequency.
2.
The duration of the oscillator stabilization wait time, tWAIT, when it is released by an interrupt is determined by the
setting in the basic timer control register, BTCON.
16-8
S3C9424/C9428/P9428
ELECTRICAL DATA
Table 16-8. Data Retention Supply Voltage in Stop Mode
(TA = – 40°C to + 85°C, VDD = 1.8 V to 5.5V)
Parameter
Symbol
Conditions
Data retention
supply voltage
VDDDR
Stop mode
Data retention
supply current
IDDDR
Stop mode; VDDDR = 1.8 V
Min
Typ
Max
Unit
1.8
–
5.5
V
–
0.1
5
µA
NOTE: Supply current does not include current drawn through internal pull-up resistors or external output current loads.
Internal RESET
Operation
~
~
Stop Mode
Oscillation
Stabilization Time
Normal
Operating
Mode
Data Retention Mode
~
~
VDD
Execution Of
Stop Instrction
RESET
VDDDR
0.8 VDD
0.2 VDD
tWAIT
NOTE:
tWAIT is the same as 4096 x 16 x 1/fosc
Figure 16-4. Stop Mode Release Timing When Initiated by a RESET
16-9
ELECTRICAL DATA
S3C9424/C9428/P9428
Table 16-9. Power-on RESET Circuit Characteristics
(TA = – 40 °C to + 85 °C, VDD = 3.0 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Power-on reset
voltage high
VDDH
3.0
–
5.5
V
Power-on reset
voltage low
VDDL
0
2.6
3.0
V
Power supply
voltage rise time
tr
10
(1)
us
Power supply
voltage off time
toff
0.5
Power-on reset circuit
cunsumption current (2)
IDDPR
s
VDD = 5 V ± 10%
65
100
VDD = 3.3 V
45
80
NOTES:
1. 216/fx (= 6.55 ms at fx = 10 MHz)
2. Current consumed when power-on reset circuit is provided internally.
VDD
VDDH
VDDL
toff
Figure16-5. Power-on RESET Timing
16-10
tr
µA
S3C9424/C9428/P9428
ELECTRICAL DATA
Table 16-10. A/D Converter Electrical Characteristics
(TA = – 40°C to + 85°C, VDD = 1.8/3.0 V to 5.5 V, VSS = 0 V)
Parameter
Symbol
Test Conditions
VDD = 5.12 V
Total accuracy
Min
Typ
Max
Unit
–
–
±3
LSB
LSB
CPU clock = 10 MHz
AVREF = 5.12 V
AVSS = 0 V
Integral linearity error
ILE
“
–
–
±2
Differential linearity error
DLE
“
–
–
±1
Offset error of top
EOT
“
–
±1
±3
Offset error of bottom
EOB
“
–
±1
±2
tCON
fosc = 10 MHz
20
–
–
µs
Analog input voltage
VIAN
–
AVSS
–
AVREF
V
Analog input impedance
RAN
–
2
–
–
MΩ
ADC reference voltage
AVREF
–
2.5
–
VDD
V
ADC reference ground
AVSS
–
VSS
–
VSS +
0.3
V
Analog input current
IADIN
AVREF = VDD = 5 V
–
–
10
µA
ADC block
IADC
AVREF = VDD = 5 V
–
1
3
mA
0.5
1.5
100
500
Conversion
time(1)
current (2)
AVREF = VDD = 3 V
AVREF = VDD = 5 V
Power down mode
–
nA
NOTES:
1. ‘Conversion time’ is the time required from the moment a conversion operation starts until it ends.
2. IADC is operating current during A/D conversion.
Digital Output
11 1111 1111
11 1111 1110
11 1111 1101
.
.
.
.
.
.
.
00 0000 0010
00 0000 0001
00 0000 0000
AVSS VEOB
Analog Input
V2
V(K-1)
V(K)
VEOT AVREF
Figure 16-6. Definition of DLE and ILE
16-11
ELECTRICAL DATA
S3C9424/C9428/P9428
Table 16-11. Zero Crossing Detector
(TA = – 40°C to + 85°C, VDD = 4.5 V to 5.5 V, VSS = 0 V)
Parameter
Zero-crossing
detection input
voltage
Symbol
VZC
Zero-crossing
detection accuracy
VAZC
Zero-crossing
detection input
frequency
Test Conditions
AC connection
c = 0.1 µF
f ZC = 60 Hz
Min
1.0
Typ
–
Max
3.0
Unit
Vp-p
–
–
± 150
mV
40
–
200
Hz
(sine wave)
VDD = 5 V
f OSC = 10 MHz
–
f ZC
1/fzc
AC input
VAZC
ZCINT
Figure 16-7. Zero Crossing Waveform Diagram
16-12
VAZ(P-P)
S3C9424/C9428/P9428
17
MECHANICAL DATA
MECHANICAL DATA
OVERVIEW
The S3C9424/C9428 is available in a 30-pin SDIP package (Samsung: 30-SDIP-400) and a 32-pin SOP package
(32-SOP-450A) and a 28-pin SOP package (28-SOP-375). Package dimensions are shown in Figures 17-1, 17-2,
and 17-3
#16
10.16
8.94 ±
0.2
5
30-SDIP-400
+0
- 0 .1
.05
0-15
0.2
#30
(1.30)
NOTE:
1.12 ±
0.1
5.08 MAX
27.48 ± 0.2
0.1
3.30 ± 0.3
0.2
27.88MAX
0.56 ±
3.81 ±
#15
0.51 MIN
#1
1.778
Dimensions are in millimeters.
Figure 17-1. 30-Pin SDIP Package Dimensions
17-1
S3C9424/C9428/P9428
0-8
MECHANICAL DATA
2.00 ± 0.2
#16
19.90 ± 0.2
(0.43)
0.40 ± 0.1
1.27
0.05 MIN
#1
NOTE: Dimensions are in millimeters
Figure 17-2. 32-SOP-450A Package Dimensions
17-2
0.20
+ 0.1
- 0.05
0.78 ± 0.2
32-SOP-450A
11.43
8.34 ± 0.2
#17
2.40 MAX
12.00 ± 0.3
#32
MECHANICAL DATA
8
S3C9424/C9428/P9428
#1
#14
17.62 ± 0.2
(0.56)
0.41 ± 0.1
1.27
+ 0.10
- 0.05
0.05 MIN
2.15 ± 0.1
18.02 MAX
0.15
0.60 ± 0.2
28-SOP-375
9.53
7.70 ± 0.2
#15
2.50 MAX
10.45 ± 0.3
#28
NOTE: Dimensions are in millimeters
Figure 17-3. 28-SOP-375 Package Dimensions
17-3
S3C9424/C9428/P9428
18
S3P9428 OTP
S3P9428 OTP
OVERVIEW
The S3P9428 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the
S3C9424/C9428 microcontroller. It has an on-chip OTP ROM instead of masked ROM. The EPROM is accessed
by serial data format.
The S3P9428 is fully compatible with the S3C9424/C9428, both in function and in pin configuration. Because of
its simple programming requirements, the S3P9428 is ideal for use as an evaluation chip for the
S3C9424/C9428.
VSS
XIN
XOUT
TEST/VPP
P0.1/SO
P0.0/SCK
RESET
P3.0
P2.0/AD0
P2.1/AD1
P2.2/AD2
P2.3/AD3
P2.4/AD4
P2.5/AD5
AVSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
NOTE:
S3P9428
30-SDIP
(Top View)
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
VDD
P0.2/SI/SCL
P0.3/CLO/SDA
P0.4/AD8
P0.5/AD9
P0.6/AD10
P0.7/AD11/PWM0
P3.1
P1.0/T0/ZCD
P1.1/BUZ
P1.2/INT0
P1.3/INT1/PWM1
P2.7/AD7/SCLK
P2.6/AD6/SDAT
AVREF
The bolds indicate an OTP pin name.
Figure 18-1. Pin Assignment Diagram (30-Pin SDIP Package)
18-1
S3P9428 OTP
S3C9424/C9428/P9428
VSS
XIN
XOUT
TEST/VPP
P0.1/SO
P0.0/SCK
RESET
P3.0
P3.2
P2.0/AD0
P2.1/AD1
P2.2/AD2
P2.3/AD3
P2.4/AD4
P2.5/AD5
AVSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
NOTE:
S3P9428
32-SOP
(Top View)
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VDD
P0.2/SI/SCL
P0.3/CLO/SDA
P0.4/AD8
P0.5/AD9
P0.6/AD10
P0.7/AD11/PWM0
P3.1
P3.3
P1.0/T0/ZCD
P1.1/BUZ
P1.2/INT0
P1.3/INT1/PWM1
P2.7/AD7/SCLK
P2.6/AD6/SDAT
AVREF
The bolds indicate an OTP pin name.
Figure 18-2. Pin Assignment Diagram (32-Pin SOP Package)
VSS
XIN
XOUT
TEST/VPP
P0.1/SO
P0.0/SCK
RESET
P2.0/AD0
P2.1/AD1
P2.2/AD2
P2.3/AD3
P2.4/AD4
P2.5/AD5
AVSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
NOTE:
S3P9428
28-SOP
(Top View)
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDD
P0.2/SI/SCL
P0.3/CLO/SDA
P0.4/AD8
P0.5/AD9
P0.6/AD10
P0.7/AD11/PWM0
P1.0/T0/ZCD
P1.1/BUZ
P1.2/INT0
P1.3/INT1/PWM1
P2.7/AD7/SCLK
P2.6/AD6/SDAT
AVREF
The bolds indicate an OTP pin name.
Figure 18-3. Pin Assignment Diagram (28-Pin SOP Package)
18-2
S3C9424/C9428/P9428
S3P9428 OTP
Table 18-1. Descriptions of Pins Used to Read/Write the EPROM
Main Chip
During Programming
Pin Name
Pin Name
Pin No.
I/O
Function
P0.3
SDAT
S3P9428
- 30 SDIP: 28
- 32 SOP: 30
I/O
P0.2
SCLK
S3P9428
- 30 SDIP: 29
- 32 SOP: 31
I
Serial clock pin (input only pin)
TEST
VPP (TEST)
4
I
Power supply pin for EPROM cell writing
(indicates that OTP enters into the writing mode).
When 12.5 V is applied, OTP is in writing mode
and when 5 V is applied, OTP is in reading
mode. (Option)
RESET
RESET
7
I
Chip Initialization
VDD/VSS
VDD/VSS
I
Logic power supply pin.
S3P9428
- 30 SDIP: 30/1
- 32 SOP: 32/1
Serial data pin (output when reading, Input
when writing) Input and push-pull output
port can be assigned
Table 18-2. Comparison of S3P9428 and S3C9424/C9428 Features
Characteristic
S3P9428
S3C9424/C9428
8-Kbyte EPROM
4/8-Kbyte mask ROM
Operating Voltage (VDD)
3.0 V to 5.5 V (28 SOP: 1.8 V to 5.5)
3.0 V to 5.5 V (28 SOP: 1.8 V to 5.5)
OTP Programming Mode
VDD = 5 V, VPP (TEST) = 12.5 V
Program Memory
Pin Configuration
30 SDIP/32 SOP/28SOP
EPROM Programmability
User Program 1 time
Programmed at the factory
OPERATING MODE CHARACTERISTICS
When 12.5 V is supplied to the VPP (TEST) pin of the S3P9428, the EPROM programming mode is entered. The
operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in
Table 18-3 below.
Table 18-3. Operating Mode Selection Criteria
VDD
Vpp (TEST)
REG/MEM
MEM
ADDRESS(A15-A0)
R/W
MODE
5V
5V
0
0000H
1
EPROM read
12.5 V
0
0000H
0
EPROM program
12.5 V
0
0000H
1
EPROM verify
12.5 V
1
0E3FH
0
EPROM read protection
NOTE: "0" means Low level; "1" means High level.
18-3