SDC-630/632/634* A/ST
10-, 12-, OR 14-BIT SYNCHRO-TO-DIGITAL/
RESOLVER-TO-DIGITAL CONVERTER
LOWER COST! PIN-FOR-PIN REPLACEMENT FOR
SDC-630/632/634 SERIES. FOR ALL NEW DESIGNS!
FEATURES
DESCRIPTION
APPLICATIONS
The SDC-630/632/634 A/ST series
are low cost, low profile synchro-todigital (S/D) and resolver-to-digital
(R/D) tracking converters with standard pin configurations. They use a
unique control transformer algorithm
that provides inherently higher accuracy and jitter-free output. Utilizing a
type II servo loop, these converters
have no velocity lag up to the specified tracking rate, and output data is
always fresh and continuously available. Each unit is fully trimmed and
requires no adjustment or field calibration.
These converters may be used wherever analog angle data from a synchro or resolver must be rapidly and
accurately converted to digital form
for transmission, storage or analysis.
Because these units are extremely
rugged and stable, and meet the
requirements on MIL-STD-202E, they
are suitable for the most severe
industrial, commercial and military
applications. Military ground support
and avionics uses include ordnance
control, radar tracking systems, navigation and collision avoidance systems.
• Low Cost Pin-for-Pin
Replacement
for SDC-630/632/634 Series
• Industry Standard Low Profile
Modular Converters
• Accuracy:
10 Bit: 21 Minutes
12 Bit: 8.5 Minutes
14 Bit: 4 Minutes, 0.9 LSB or
2.6 Minutes (High Accuracy)
• Options (Consult Factory):
Velocity Input
BIT: Built-In-Test
16-Bit Resolution
INPUT OPTIONS
RESISTOR (ST)
DIVIDER
SYNCHRO INPUT OPTION (A)
S1
S2
S3
SCOTT-T
TRANSFORMER
SIN θ
COS θ
RH
RL
RESOLVER INPUT OPTION (A)
S1
S2
S3
S4
RESOLVER
ISOLATION
TRANSFORMER
S2
S3
S2
S3
S4
DEMODULATOR
SIN (θ − φ)
SIN (θ − φ) COS ω t
ERROR
PROCESSOR
AND
VOLTAGE
CONTROLLED
OSCILLATOR
COS θ
SIN θ
INPUT
OPTION
SOLID STATE
SCOTT-T
BUFFER
SIN θ
COS θ
RESOLVER INPUT OPTION (ST)
S1
REF
SIN θ
SYNCHRO INPUT OPTION (ST)
S1
REFERENCE (A)
ISOLATION
TRANSFORMER
SOLID STATE
RESOLVER
BUFFER
COS θ
SOLID STATE
CONTROL
TRANSFORMER
(CT)
UP-DOWN COUNTER
(CONTAINS ANGLE φ )
BIT 1
SIN θ
COS θ
BIT 10,
12 OR 14
FIGURE 1. SDC-630/632/634 A/ST BLOCK DIAGRAM
* Patented
© 1993, 1999 Data Device Corporation
BIT 1
(MSB)
BIT 10, 12, OR 14
(LSB)
VEL
VELOCITY
(OPTIONAL)
INH
INHIBIT
CB
CONVERTER
BUSY
TABLE 1. SDC-630/632/634 A/ST SPECIFICATIONS
SDC-630
ACCURACY
Standard Units
High Accuracy Option
SIGNAL AND
REFERENCE INPUT
PARAMETER
VALUE
PARAMETER
RESOLUTION
SDC-632
10 bits
SDC-630 12 bits
±21 min
–
±8.5 min
–
Signal
Frequency
Range
REFERENCE INPUT
Options H, I
Options M, L
POWER SUPPLIES
SDC-634
Nominal Voltage
Range
Maximum Voltage
Without Damage
Current (All)
14 bits
±5.3 min
±2.6 min
Signal Input
Impedance
(L-L Balanced, Resistive)
A*
Synchro Input
90V L-L, 400 Hz
(Option H)
90V L-L, 60 Hz
(Option I)
11.8V L-L, 400 Hz
(Option L)
Resolver Input
90V L-L, 400 Hz
(Option H)
26V L-L, 60 Hz
(Option M)
11.8V L-L, 400 Hz
(Option L)
TABLE 1. SDC-630/632/634 A/ST SPECIFICATIONS (CONTD)
123 k
47-1000 Hz
148 kΩ min
123 k
350-1000 Hz
19 kΩ min
52 k
350-1000 Hz 148 kΩ min
--
350-1000 Hz
42 kΩ min
--
350-1000 Hz
19 kΩ min
70 k
Reference
Voltage
Range
PHYSICAL
CHARACTERISTICS
Size (Encapsulated
Module)
Outputs
Type
10, 12, 14, (For 16
Consult Factory)
Parallel Data Bits
Converter Busy (CB)
Drive Capability
Built-In-Test (BIT)
(Special Order,
Consult Factory)
VELOCITY OUTPUT
(SPECIAL ORDER)
Polarity
Std. Voltage Range
(Full Scale)
-55°C to +105°C
0°C to +70°C
-55°C to +125°C
3.125 x 2.625 x 0.43 inches
(7.94 x 6.67 x 1.07 cm).
4 oz.
(113 gm.)
NOTE: These specifications apply over temperature range, power
supply range, reference frequency and amplitude range, ±10%
signal amplitude variation, and up to 10% harmonic distortion in
reference input.
270 k
60 k
POWER SUPPLIES
The main power supplies can vary over the specified ranges with
no change in converter specifications, except for a proportional
change in maximum tracking rates.
* Transformer Isolated. Other voltages and frequencies available on
special order.
DIGITAL
INPUT/OUTPUTS
Logic Type
Inhibit Input (INH)
-15 V Supply + 5 V Supply
+11 to +16.5 V -11 to -16.5 V +4.5 to +5.5
V
+18 V
-18 V
20 mA
25 mA
+7
10 mA
Weight
Reference Input Impedance
(Resistive)
40-150 Vrms 300 kΩ min
10- 50 Vrms
80 kΩ min
+15 V Supply
TEMPERATURE
RANGES
Operating
-1 Option
-3 Option
Storage
ST
350-1000 Hz 148 kΩ min
VALUE
When testing or evaluating the converters, it is advisable to limit
the current in each of the supplies. Set each current limit 50%
greater than the maximum current listed for that supply as listed
in TABLE 1.
TTL/CMOS Compatible
Logic “0” inhibits
Does not interrupt converter tracking.
TTL/CMOS
TIMING
Natural Binary Angle; Positive logic
0.5 to 1.5 µsec positive pulse.
Data changes on leading edge.
FIGURE 2 shows the converter timing waveforms. Whenever an
input angle change occurs, the converter changes the digital
angle in 1 LSB steps, and generates a Converter Busy (CB)
pulse. The CB is a positive pulse 0.5 to 1.5 µsec long.
1 Std. TTL load
CONVERTER "1"
BUSY (CB) "0"
Positive Output for increasing angle
INHIBIT "1"
(INH) "0"
±4 Min (Other ranges available; Consult
Factory)
DATA
VALID
For other Velocity
Characteristics
Consult Factory
6.1 µs MIN
DEPENDS ON dθ
dt
0.5-1.5 µs
.5 µs
DATA
VALID
FIGURE 2. SDC-630/632/634* A/ST TIMING DIAGRAM
2
TABLE 2. SDC-630/632/634 A/ST DYNAMIC CHARACTERISTICS
Bandwidth (non F carrier)
60 HZ
400 HZ
UNITS
Carrier Frequency Range
Bandwidth (Closed Loop)
Ka
A1
A2
A
B
47 - 1,000
15
1,100
0.1
7,600
33
16.3
360 - 1,000 (ST to 5,000)
100
48,000
1
48,000
220
110
Hz
Hz
1/s
1/s
1/s
1/s
1/s
RESOLUTION
Tracking Rate (rps)
Typical
Minimum
Acceleration (1 LSB lag)
Settling Time (179° step, max)
10
12
14
16
10
12
14
16
UNITS
28.5
24
370
500
7.1
6
93
600
1.8
1.5
23
900
0.45
0.37
5.8
2,200
192
160
17,000
90
48
40
4,220
100
12
10
1,050
140
3
2.5
260
320
rps
rps
°/s2
msec
The ABSOLUTE value of the resistor is not critical.
Data changes on the leading edge of the CB pulse, and data can
be transferred 0.5 µsec after the leading edge.
In the case of the RESOLVER version (RDC), the equation is:
The simplest method of interfacing with a computer is to transfer
data at a fixed time interval after the Inhibit is applied. The converter will ignore an Inhibit during the “busy” interval until that
interval is over. Timing is as follows: (a) apply the Inhibit, (b) wait
0.5 µsec, (c) transfer the data, (d) release the Inhibit. The Inhibit
line has no effect on converter tracking.
RSIG = 2.2k (New L-L Voltage – Standard Unit L-L Voltage)
The calculated resistors are connected in series with S1 and S2
respectively. Note only two resistors are required. The required
resistance matching and its effect on accuracy, is the same as for
a synchro input, see FIGURE 3. The Reference Voltage is treated in the same manner, but the value is not critical.
SIGNAL INPUTS
RREF = 2.8k (New Reference – Standard Reference)
To prevent damage to the inputs, the maximum steady-state voltage should not exceed the specified input voltage by more than
30%.
For this use a 10% tolerance resistor is adequate.
ACCOMMODATING NON-STANDARD INPUT
VOLTAGES (A ONLY)
The signal and reference input levels can be resistively scaled to
accommodate non-standard voltages, see FIGURE 3. Select a
converter that is the next lower standard voltage, and the voltage
is then scaled up by using resistors in series with the synchro
and/or reference inputs.
R SIG
NONSTANDARD
LINE-TO-LINE
LEVEL
For a synchro input (SDC), a resistor RSIG is added in series
with S1, S2 and S3 which is determined as follows:
RSIG = 1.1k (New L-L Voltage – Standard Unit L-L Voltage)
That is, 1.1k for each volt above the design voltage level of the
standard unit.
NONSTANDARD
REFERENCE
LEVEL
Example: An SDC-634A-L (11.8 V) is to be used at 50 V L-L.
{
{
S1
R SIG
S2
R SIG
S3
R REF
SDC-630A
RSIG = 1.1k (50 – 11.8) = 42.2k
The closest available high grade resistor with a low temperature
coefficient of resistance should be used, and the three resistors
should be as closely matched to each other as possible. In general, a 0.1% difference will introduce 1.7 arc minutes of additional error due to the effect on SIN/COS ratio relationship.
FIGURE 3. SDC-630/632/634 A/ST NON-STANDARD
INPUT LEVEL SCALING
3
ORDERING INFORMATION
XXX-XXX-X-X-X-X-X
Reliability Grade:
R = Enhanced Reliability
Accuracy:
a = High Accuracy Version,
±2.6 Minutes (SDC-634 Only)
Temperature Range:
1 = -55°C to +105°C
3 = 0°C to + 70°C
Signal Input Voltage and Frequency:
H = 90 VL-L, 400 Hz (Synchro or
Resolver)
I = 90 VL-L, 60 Hz (Synchro Only)
L = 11.8 VL-L, 400 Hz (Synchro or
Resolver)
Transformer Type:
A = Internal Transformer
ST = Solid State
Resolution:
636 = 16 bits, Consult Factory
634 = 14 bits
632 = 12 bits
630 = 10 bits
Input Type:
SDC = Synchro
RDC = Resolver
Dimensions are in inches (mm).
2.625 +- 0.015
(66.68)
0.040 +- 0.002
(1.02)
VEL
14 LSB
13
S4
S3
12
11
3.125 +- 0.015
(79.38)
0.26 + 0.01
-
(6.604)
10
9
8
7
6
5
4
3
Dia (Typ)
+
S2
SDC-630A/ST S1
or
CB
SDC-632A/ST INH
or
+15V
SDC-634A/ST GND
0.430
(10.92)
(Max)
-15V
+5V
RL
RH
2
1 MSB
0.20 +- 0.01
(5.08) (Typ)
2.2 +- 0.01
(55.88)
0.21 +- 0.01
(5.334)
0.25
(6.35)
(Tol Noncum)
(Min)
BOTTOM VIEW
SIDE VIEW
Note: VEL is not present on the standard product.
For VEL output contact factory.
Note: For versions with Velocity or Built-In-Test, Please
Consult Factory.
FIGURE 4. SDC-630/632/634 A/ST
MECHANICAL OUTLINE
The information in this data sheet is believed to be accurate; however, no responsibility is assumed by Data Device Corporation for its
use, and no license or rights are granted by implication or otherwise in connection therewith.
Specifications are subject to change without notice.
105 Wilbur Place, Bohemia, New York 11716-2482
For Technical Support - 1-800-DDC-5757 ext. 7389 or 7413
Headquarters - Tel: (631) 567-5600 ext. 7389 or 7413, Fax: (631) 567-7358
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Asia/Pacific - Tel: +81-(0)3-3814-7688, Fax: +81-(0)3-3814-7689
World Wide Web - http://www.ddc-web.com
ILC DATA DEVICE CORPORATION
REGISTERED TO ISO 9001
FILE NO. A5976
D-08/99-500
PRINTED IN THE U.S.A.
4