Si51210 TWO O UTPUTS F ACTORY P ROGRAMMABLE C L O C K G ENERATOR Features Generates up to 2 CMOS clock 2.5 to 3.3 V voltage supply range outputs from 3 to 200 MHz 0.25% to 1.0% spread spectrum (center spread) Accepts crystal or reference clock input Low cycle-cycle jitter 3 to 166 MHz reference clock input Programmable output rise and 8 to 48 MHz crystal input fall times Programmable FSEL, SSEL, Ultra small 6-pin TDFN package SSON, PD, and OE input (1.2 mm x 1.4 mm) functions Low power dissipation Applications Crystal/XO replacement EMI reduction Portable devices Ordering Information: See page 9. Digital still camera IP phone Smart meter Pin Assignments Description The factory programmable Si51210 is industry’s lowest power, smallest footprint and frequency flexible programmable clock generator targeting low power, low cost and high volume consumer and embedded applications. The device operates from a single crystal or an external clock source and generates 1 to 2 outputs up to 200 MHz. They are factory programmed to provide customized output frequencies, control inputs and ac parameter tuning like output drive strength that are optimized for customer board condition and application requirements. VDD 1 XIN/CLKIN 2 XOUT 3 6 Si51210 5 4 VSS SSCLK2/REFCLK_D FSEL/SSEL/SSON/ PD/OE1 SSCLK1/REFCLK FSEL/SSEL/SSON/ OE2 Patents pending Functional Block Diagram PLL with Modulation Control XIN/ 2 CLKIN XOUT 3 VDD 1 VSS 6 V-REG To Core To Pin 4 and Pin 5 Preliminary Rev. 0.7 1/12 Programmable Configuration Register Buffers, Dividers, and Switch Matrix 4 SSCLK1/ REFCLK/ 0E2/FSEL/ SSEL/SS0N 5 SSCLK2/ REFCLK_D 0E1/FSEL/ SSEL/SS0N/PD Copyright © 2012 by Silicon Laboratories Si51210 This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Si51210 2 Preliminary Rev. 0.7 Si51210 TABLE O F C ONTENTS Section Page 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 2.1. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 2.2. Comments and Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 3.1. Input Frequency Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 3.2. Output Frequency Range and Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 3.3. Programmable Modulation Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 3.4. Programmable Spread Percent (%) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 3.5. SSON or Frequency Select (FSEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 3.6. Power Down (PD) or Output Enable (OE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 4. Pin Descriptions: 6-Pin TDFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 5. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 6. Package Outline (6-pin TDFN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Preliminary Rev. 0.7 3 Si51210 1. Electrical Specifications Table 1. DC Electrical Specifications (VDD = 2.5 V ±5%, or VDD = 3.3 V ± 10%, TA = 0 to 70 oC) Parameter Operating Voltage Symbol Test Condition Min Typ Max Unit VDD VDD=3.3 V ± 10% 2.97 3.3 3.63 V VDD=2.5 V ± 5% 2.375 2.5 2.625 V Output High Voltage VOH IOH=–4 mA VDD – 0.5 — — V Output Low Voltage VOL IOL=4 mA — — 0.3 V Input High Voltage VIH CMOS Level 0.7 VDD — — V Input Low Voltage VIL CMOS Level 0 — 0.3 VDD V Operating Supply Current IDD FIN=12 MHz, SSCLK1 =12 MHz, SSCLK2 =24 MHz, CL=0, VDD=3.3 V — 4.5 — mA Nominal Output Impedance ZO — 30 — RPUP/RPD Pin 5 — 150k — Input Pin Capacitance CIN Input pin capacitance — 3 5 pF Load Capacitance CL Clock outputs < 166 MHz — — 15 pF Clock outputs > 166 MHz — — 10 pF Internal Pull-up/Pull-down Resistor 4 Preliminary Rev. 0.7 Si51210 Table 2. AC Electrical Specifications (VDD = 2.5 V ±5%, or VDD = 3.3 V ± 10%, TA = 0 to 70 oC) Parameter Symbol Condition Min Typ Max Unit Input Frequency Range FIN1 Crystal input 8 — 48 MHz Input Frequency Range FIN2 Reference clock Input 3 — 166 MHz Output Frequency Range FOUT SSCLK1/2, CL=15 pF 3 — 200 MHz Frequency Accuracy FACC Configuration dependent — 0 — ppm DCOUT Measured at VDD/2 45 50 55 % Input Duty Cycle DCIN CLKIN, CLKOUT through PLL 30 50 70 % Output Rise Time tr CL=15 pF, 20 to 80% — 1 3.0 ns Output Fall Time tf CL=15 pF, 20 to 80% — 1 3.0 ns PJ1 SSCLK1/2, two clocks running, VDD=3.3 V, CL=15 pF — 150* — ps CCJ1 SSCLK1/2, two clocks running, VDD=3.3 V, CL=15 pF — 100* — ps Power-up Time tPU Time from 0.9 VDD to valid frequencies at all clock outputs — 1.2 5.0 ms Output Enable Time tOE Time from OE raising edge to active at output SSCLK (asynchronous) — 15 — ns Output Disable Time tOD Time from OE falling edge to active at output SSCLK (asynchronous) — 15 — ns Output Duty Cycle Period Jitter Cycle-to-Cycle Jitter *Note: Jitter performance depends on configuration and programming parameters. Table 3. Absolute Maximum Conditions Parameter Symbol Condition Min Typ Max Unit –0.5 — 4.2 V Main Supply Voltage VDD Input Voltage VIN Relative to VSS –0.5 — VDD+0.5 V Temperature, TS Non-functional –65 — 150 °C Temperature, Operating Ambient TA Functional, C-Grade 0 — 70 °C ESD Protection (Human Body Model) ESDHBM JEDEC (JESD 22-A114) –4000 — 4000 V ESD Protection (Charge Device Model) ESDCDM JEDEC (JESD 22-C101) –1500 — 1500 V ESD Protection (Machine Model) ESDMM JEDEC (JESD 22-A115) –200 — 200 V MSL JEDEC (J-STD-020) Moisture Sensitivity Level 1 Note: While using multiple power supplies, the Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is not required. Preliminary Rev. 0.7 5 Si51210 2. Design Considerations 2.1. Typical Application Schematic VDD 10µF 0.1µF VDD CL1 XIN XOUT VSS SSCLK3 VDD Si51210 XIN XOUT FSEL 5K CL2 5K 2.2. Comments and Recommendations Decoupling Capacitor: A decoupling capacitor of 0.1 μF must be used between VDD and VSS on pin 1. Place the capacitor on the component side of the PCB as close to the VDD pin as possible. The PCB trace to the VDD pin and to the GND via should be kept as short as possible. Do not use vias between the decoupling capacitor and the VDD pin. In addition, a 10 µF capacitor should be placed between VDD and VSS. Series Termination Resistor: A series termination resistor is recommended if the distance between the outputs (SSCLK or REFCLK pins) and the load is over 1 ½ inches. The nominal impedance of the SSCLK output is about 30 Ω. Use a 20 Ω resistor in series with the output to terminate a 50 Ω trace impedance and place a 20 Ω resistor as close to the SSCLK output as possible. Crystal and Crystal Load: Only use a parallel resonant fundamental AT cut crystal. Do not use higher overtone crystals. To meet the crystal initial accuracy specification (in ppm) make sure that external crystal load capacitor is matched to crystal load specification. To determine the value of CL1 and CL2, use the following formula: C1 = C2 = 2CL – (Cpin + Cp) Where: CL is load capacitance stated by crystal manufacturer Cpin is the Si51210 pin capacitance (4 pF). Cp is the parasitic capacitance of the PCB traces. Example: If a crystal with CL = 12 pF specification is used and Cp = 1 pF (parasitic PCB capacitance on PCB), 19 or 20 pF external capacitors from pins XIN (pin 2) and XOUT (Pin 3) to VSS are required. Users must verify Cp value. 6 Preliminary Rev. 0.7 Si51210 3. Functional Description 3.1. Input Frequency Range The input frequency range is from 8.0 to 48.0 MHz for crystals and ceramic resonators. If an external clock is used, the input frequency range is from 8.0 to 166.0 MHz. 3.2. Output Frequency Range and Outputs Up to two outputs can be programmed as SSCLK or REFCLK. SSCLK output can be synthesized to any value from 3 to 200 MHz with spread based on valid input frequency. The spread at SSCLK pins can be stopped by the SSON input control pin. If SSON pin is high (VDD), the frequency at SSCLK pin is synthesized to the nominal value of the input frequency and there is no spread. REFCLK is the buffered output of the oscillator and is the same frequency as the input frequency without spread. However, REFCLK_D output is divided by output dividers from 2 to 32. By using only low cost, fundamental mode crystals, the Si51210 can synthesize output frequency up to 200 MHz, eliminating the need for higher order crystals (Xtals) and crystal oscillators (XOs). This reduces the cost while improving the system clock accuracy, performance, and reliability 3.3. Programmable Modulation Frequency The spread spectrum clock (SSC) modulation default value is 31.5 kHz. The higher values of up to 62 kHz can also be programmed. Less than 30 kHz modulation frequency is not recommended to stay out of the range audio frequency bandwidth since this frequency could be detected as a noise by the audio receivers within the vicinity. 3.4. Programmable Spread Percent (%) The spread percent (%) value is programmable from ±0.25% to ±1% (center spread) for all SSCLK frequencies. It is possible to program smaller or larger non-standard values of spread percentage. Contact Silicon Labs if these non-standard spread percent values are required in the application. 3.5. SSON or Frequency Select (FSEL) The Si51210 pin 4 and 5 can be programmed as either SSON to enable or disable the programmed spread percent value or as frequency select (FSEL). If SSON is used, when this pin is pulled high (VDD), the spread is stopped and the frequency is the nominal value without spread. If low (GND), the frequency is the nominal value with the spread. If FSEL function is used, the output pin can be programmed for different set of frequencies as selected by FSEL. SSCLK value can be any frequency from 3 to 200 MHz, but the spread % is the same percent value. REFCLK is the same frequency as the input reference clock and the REFCLK_D is input clock divided by 2 to 32 without spread. The set of frequencies in Table 4 is given as an example, using a 48 MHz crystal. Table 4. Example Frequencies FSEL (Pin 4) SSCLK1 (Pin 5) 0 66 MHz, ±1% 1 33 MHz, ±1% 3.6. Power Down (PD) or Output Enable (OE) The Si51210 pin 5 can be programmed as PD input. Pin 4 and pin 5 can be programmed as OE input. PD turns off both PLL and output buffers whereas OE only disables the output buffers to Hi-Z. Preliminary Rev. 0.7 7 Si51210 4. Pin Descriptions: 6-Pin TDFN VDD 1 XIN/CLKIN 2 XOUT 3 6 Si51210 5 4 VSS SSCLK2/REFCLK_D FSEL/SSEL/ SSON/PD/OE1 SSCLK1/REFCLK FSEL/SSEL/ SSON/OE2 Table 5. Si51210 6-Pin Descriptions 8 Pin # Name Type Description 1 VDD 2 XIN/CLKIN I External crystal and clock input. 3 XOUT O Crystal output. Leave this pin unconnected (floating) if an external clock input is used. 4 SSCLK1/REFCLK/ FSEL/SSEL/SSON/ OE2 I/O Programmable SSCLK1 or REFCLK output or MultiFunction control input. The frequency at this pin is synthesized by internal PLL if programmed as SSCLK1 with or without spread. If programmed as REFCLK, output clock is buffered output of crystal or reference clock input. If programmed as MultiFunction control input, it can be OE, FSEL, SSEL and SSON. 5 SSCLK2/REFCLK_D/ OE1/FSEL/SSEL/ SSON/PD I/O Programmable SSCLK2 or REFCLK_D output or MultiFunction control input. The frequency at this pin is synthesized by internal PLL if programmed as SSCLK2 with or without spread. If programmed as REFCLK_D, output clock is buffered output of crystal or reference clock input divided by 2 to 32. If programmed as MultiFunction control input, it can be OE, PD, FSEL, SSEL and SSON. 6 VSS GND PWR 2.5 to 3.3 V power supply. Ground. Preliminary Rev. 0.7 Si51210 5. Ordering Information Part Number Package Type Temperature Si51210-AxxxFM 6-pin TDFN Commercial, 0 to 70 C Si51210-AxxxFMR 6-pin TDFN—Tape and Reel Commercial, 0 to 70 C Si 51210 SiSi512xx 51210 programmable Clock Generator Product Family FMR AXXX Operating Temp Range : F = 0 to + 70° C M = TDFN, ROHS6 , Pb - free R = Tape & Reel ( blank) = Tubes A = Product Revision A 2nd Option Code= XXX A three character code will be assigned for each unique configuration . Device starts operation upon powerup . Preliminary Rev. 0.7 9 Si51210 1.20±0.05 1.40±0.05 0.75±0.05 0.00-0.05 0.20±0.05 PIN 1 AREA 0.20± 0.025 NOTE 10 0.40± 0.05 6. Package Outline: 6-pin TDFN Preliminary Rev. 0.7 0.40±0.05 4 6 3 1 Pin 1 Corner Si51210 NOTES: Preliminary Rev. 0.7 11 Si51210 CONTACT INFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Please visit the Silicon Labs Technical Support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. 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Other products or brand names mentioned herein are trademarks or registered trademarks of their respective holders. 12 Preliminary Rev. 0.7