SN54/74LS256 DUAL 4-BIT ADDRESSABLE LATCH The SN54/74LS256 is a Dual 4-Bit Addressable Latch with common control inputs; these include two Address inputs (A0, A1), an active LOW Enable input (E) and an active LOW Clear input (CL). Each latch has a Data input (D) and four outputs (Q0 – Q3). When the Enable (E) is HIGH and the Clear input (CL) is LOW, all outputs (Q0 – Q3) are LOW. Dual 4-channel demultiplexing occurs when the (CL) and E are both LOW. When CL is HIGH and E is LOW, the selected output (Q0 – Q3), determined by the Address inputs, follows D. When the E goes HIGH, the contents of the latch are stored. When operating in the addressable latch mode (E = LOW, CL = HIGH), changing more than one bit of the Address (A0, A1) could impose a transient wrong address. Therefore, this should be done only while in the memory mode (E= CL = HIGH). • • • • • • DUAL 4-BIT ADDRESSABLE LATCH LOW POWER SCHOTTKY J SUFFIX CERAMIC CASE 620-09 Serial-to-Parallel Capability Output From Each Storage Bit Available Random (Addressable) Data Entry Easily Expandable Active Low Common Clear Input Clamp Diodes Limit High Speed Termination Effects 16 1 N SUFFIX PLASTIC CASE 648-08 16 1 CONNECTION DIAGRAM DIP (TOP VIEW) 16 1 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. PIN NAMES A0, A1 Da, Db E CL Q0a – Q3a, Q0b – Q3b D SUFFIX SOIC CASE 751B-03 ORDERING INFORMATION SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC LOADING (Note a) Address Inputs Data Inputs Enable Input (Active LOW) Clear Input (Active LOW) Parallel Latch Outputs (Note b) HIGH LOW 0.5 U.L. 0.5 U.L. 1.0 U.L. 0.5 U.L. 0.25 U.L. 0.25 U.L. 0.5 U.L. 0.25 U.L. 10 U.L. LOGIC SYMBOL 5 (2.5) U.L. NOTES: a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW. b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) Temperature Ranges. 5-421 FAST AND LS TTL DATA SN54/74LS256 LOGIC DIAGRAM TRUTH TABLE CL E D A0 A1 Q0 Q1 Q2 Q3 L H X X X L L L L Clear L L L L L L L L L L L L L L L L L H L H L H L H L L H H L L H H L L L L H H H H L H L L L L L L L L L H L L L L L L L L L H L L L L L L L L L H Demultiplex H H X X X QN–1 QN–1 QN–1 QN–1 Memory H H H H H H H H L L L L L L L L L H L H L H L H L L H H L L H H L L L L H H H H L H QN–1 QN–1 L H QN–1 QN–1 QN–1 QN–1 QN–1 QN–1 QN–1 QN–1 L H QN–1 QN–1 QN–1 QN–1 QN–1 QN–1 QN–1 QN–1 L H Addressable Latch QN–1 QN–1 QN–1 QN–1 QN–1 QN–1 H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial MODE SELECTION E CL L H L H H H L L MODE Addressable Latch Memory Dual 4-Channel Demultiplexer Clear FAST AND LS TTL DATA 5-422 MODE SN54/74LS256 GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC Supply Voltage 54 74 4.5 4.75 5.0 5.0 5.5 5.25 V TA Operating Ambient Temperature Range 54 74 – 55 0 25 25 125 70 °C IOH Output Current — High 54, 74 – 0.4 mA IOL Output Current — Low 54 74 4.0 8.0 mA DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH Input HIGH Voltage VIL Input LOW Voltage VIK Input Clamp Diode Voltage VOH Output HIGH Voltage VOL Output LOW Voltage IIH Min Parameter Typ Max 2.0 54 0.7 74 0.8 – 0.65 54, 74 2.4 – 1.5 3.5 Short Circuit Current (Note 1) ICC Power Supply Current Guaranteed Input HIGH Voltage for All Inputs V Guaranteed Input LOW Voltage for All Inputs V VCC = MIN, IIN = – 18 mA V VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table VCC = VCC MIN, VIN = VIL or VIH per Truth Table 0.4 V IOL = 4.0 mA 74 0.35 0.5 V IOL = 8.0 mA 20 40 µA VCC = MAX, VIN = 2.7 V mA VCC = MAX, VIN = 7.0 V – 0.4 – 0.8 mA VCC = MAX, VIN = 0.4 V – 100 mA VCC = MAX 30 mA VCC = MAX 0.1 0.2 IOS V 0.25 Others E Input Input LOW Current Others E Input Test Conditions 54, 74 Input HIGH Current Others E Input IIL Unit – 20 Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. AC CHARACTERISTICS (TA = 25°C) Limits Symbol Parameter Min Typ Max Unit Test Conditions tPLH tPHL Turn-Off Delay, Enable to Output Turn-On Delay, Enable to Output 20 16 27 24 ns ns Figure 1 tPLH tPHL Turn-Off Delay, Data to Output Turn-On Delay, Data to Output 20 13 30 20 ns ns Figure 2 tPLH tPHL Turn-Off Delay, Address to Output Turn-On Delay, Address to Output 20 14 30 24 ns ns Figure 3 tPHL Turn-On Delay, Clear to Output 12 23 ns Figure 5 FAST AND LS TTL DATA 5-423 VCC = 5.0 V, CL = 15 pF SN54/74LS256 AC SET-UP REQUIREMENTS (TA = 25°C) Limits Symbol Parameter Min Typ Max Unit Test Conditions ts Data Setup Time 20 ns ts Address Setup Time 0 ns th Data Hold Time 0 ns Figure 4 th Address Hold Time 15 ns Figure 6 tW Enable Pulse Width 15 ns Figure 1 Figures 4 & 6 VCC = 5.0 V AC WAVEFORMS Figure 2. Turn-on and Turn-off Delays, Data to Output Figure 1. Turn-on and Turn-off Delays, Enable To Output and Enable Pulse Width Figure 4. Setup and Hold Time, Data to Enable Figure 3. Turn-on and Turn-off Delays, Address to Output Figure 5. Turn-on Delay, Clear to Output Figure 6. Setup Time, Address to Enable (See Notes 1 and 2) NOTES: 1. The Address to Enable Setup Time is the time before the HIGH-to-LOW Enable transition that the Address must be stable so that the correct latch is addressed and the other latches are not affected. 2. The shaded areas indicate when the inputs are permitted to change for predictable output performance. FAST AND LS TTL DATA 5-424 Case 751B-03 D Suffix 16-Pin Plastic SO-16 -A- "! ! " " ! " # 1 %# ) ! !" $ !" 8 C -T- D M K " ! #! J F ! Case 648-08 N Suffix 16-Pin Plastic R X 45° G " ! ) #! P ! " " 9 -B- ! 16 & ! ! ° ° ° ° ( ( ( ( "! ! " " ! ! ' " " ! ' ! " # & -A- 16 9 1 8 ! ! $ ! B # ) " ! " # ) !" $ !" ) F L C S -T- K H G M J D " Case 620-09 J Suffix 16-Pin Ceramic Dual In-Line -A- ! ! ! ! ° ° ° ° "! ! " 16 " ) " L K M N J G D " $ " $ ! " " ! ! FAST AND LS TTL DATA 5-425 & # ) !" $ !" ) -T $ " " C F & 8 E ! ! ! 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Literature Distribution Centers: USA: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. EUROPE: Motorola Ltd.; European Literature Centre; 88 Tanners Drive, Blakelands, Milton Keynes, MK14 5BP, England. JAPAN: Nippon Motorola Ltd.; 4-32-1, Nishi-Gotanda, Shinagawa-ku, Tokyo 141, Japan. ASIA PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. ◊ FAST AND LS TTL DATA 5-426