MC54/74F256 DUAL 4-BIT ADDRESSABLE LATCH The MC54/74F256 dual addressable latch has four distinct modes of operation which are selectable by controlling the Clear and Enable inputs (see Function Table). In the addressable latch mode, data at the Data (D) inputs is written into the addressed latches. The addressed latches will follow the Data input with all unaddressed latches remaining in their previous states. In the memory mode, all latches remain in their previous states and are unaffected by the Data or Address inputs. To eliminate the possibility of entering erroneous data in the latches, the enable should be held HIGH (inactive) while the address lines are changing. In the dual 1-of-4 decoding or demultiplexing mode (MR = E = LOW), addressed outputs will follow the level of the D inputs with all other outputs LOW. In the clear mode, all outputs are LOW and uneffected by the Address and Data inputs. • Combines Dual Demultiplexer and 8-Bit Latch • Serial-to-Parallel Capability • Output from Each Storage Bit Available • Random (Addressable) Data Entry • Easily Expandable • Common Clear Input • Useful as Dual 1-of-4 Active HIGH Decoder DUAL 4-BIT ADDRESSABLE LATCH FAST SCHOTTKY TTL J SUFFIX CERAMIC CASE 620-09 16 1 CONNECTION DIAGRAM N SUFFIX PLASTIC CASE 648-08 16 VCC MR E Db Q3b Q2b Q1b Q0b 16 15 14 13 12 11 10 9 1 D SUFFIX SOIC CASE 751B-03 16 1 1 A0 2 A1 3 Da 4 Q0a 5 Q1a ORDERING INFORMATION 8 7 Q3a GND 6 Q2a MC54FXXXJ MC74FXXXN MC74FXXXD FUNCTION TABLE Inputs Operating Mode Ceramic Plastic SOIC Outputs MR E D A0 A1 Q0 Q1 Q2 Q3 Master Reset L H X X X L L L L Demultiplex (Active HIGH Decoder when D = H) L L L L L L L L d d d d L H L H L L H H Q=d L L L L Q=d L L L L Q=d L L L L Q=d Store (Do Nothing) H H X X X q0 q1 q2 q3 Addressable Latch H H H H L L L L d d d d L H L H L L H H Q=d q0 q0 q0 q1 Q=d q1 q1 q2 q2 Q=d q2 q3 q3 q3 Q=d H = HIGH Voltage Level Steady State L = LOW Voltage Level Steady State X = Immaterial d = HIGH or LOW Data one setup time prior to the LOW-to-HIGH Enable transition. q = Lower case letters indicate the state of the referenced output established during the last cycle in which it was addressed or cleared. FAST AND LS TTL DATA 4-123 LOGIC SYMBOL 3 13 Da Db 1 A0 E 14 2 A1 MR Q0a Q1a Q2a Q3a Q0b Q1b Q2b Q3b 15 4 5 6 7 9 10 11 12 MC54/74F256 LOGIC DIAGRAM E Da Q0a A0 A1 Q1a Q2a MR Q3a Db Q0b Q1b Q2b Q3b Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. GUARANTEED OPERATING RANGES Symbol VCC Parameter Supply Voltage Min Typ Max Unit 54, 74 4.5 54 –55 5.0 5.5 V 25 125 74 0 25 70 °C TA Operating Ambient Temperature Range IOH Output Current — High 54, 74 –1.0 mA IOL Output Current — Low 54, 74 20 mA FAST AND LS TTL DATA 4-124 MC54/74F256 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol Parameter VIH Input HIGH Voltage VIL Input LOW Voltage VIK Input Clamp Diode Voltage VOH Output HIGH Voltage VOL Output LOW Voltage IIH Input HIGH Current IIL Input LOW Current IOS Output Short Circuit Current (Note 2) ICC Power Supply Current Total, Output HIGH Total, Output LOW Min Typ Max 2.0 Unit Test Conditions V Guaranteed Input HIGH Voltage 0.8 V Guaranteed Input LOW Voltage –1.2 V VCC = MIN, IIN = –18 mA 54, 74 2.5 V IOL = –1.0 mA VCC = MIN 74 2.7 V IOL = –1.0 mA VCC = 4.75 V 0.5 V IOL = 20 mA VCC = MIN 20 µA VCC = MAX, VIN = 2.7 V – 60 0.1 mA VCC = MAX, VIN = 7.0 V – 0.6 mA VCC = MAX, VIN = 0.5 V –150 mA VCC = MAX, VOUT = 0 V 42 mA VCC = MAX 60 mA VCC = MAX NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable device type. 2. Not more than one output should be shorted at a time, nor for more than 1 second. FAST AND LS TTL DATA 4-125 MC54/74F256 AC CHARACTERISTICS Symbol Parameter 54/74F 54F 74F TA = +25°C VCC = +5.0 V CL = 50 pF TA = –55 to +125°C VCC = 5.0 V ±10% CL = 50 pF TA = 0 to 70°C VCC = 5.0 V ± 5% CL = 50 pF Min Max Min Max Min Max Unit tPLH tPHL Propagation Delay E to Qn 4.0 3.0 10.5 7.0 4.0 3.0 13 8.5 4.0 3.0 12 7.5 ns tPLH tPHL Propagation Delay Dn to Qn 3.5 3.0 9.0 7.0 3.5 2.5 11.5 8.5 3.5 2.5 10 7.5 ns tPLH tPHL Propagation Delay An to Qn 3.5 4.0 14 9.5 3.5 4.0 15.5 11 3.5 4.0 14.5 10 ns tPHL Propagation Delay MR to Qn 5.0 9.0 4.5 11.5 4.5 10 ns AC OPERATING REQUIREMENTS Symbol Parameter 54/74F 54F 74F TA = +25°C VCC = +5.0 V TA = –55 to +125°C VCC = 5.0 V ±10% TA = 0 to 70°C VCC = 5.0 V ± 5% Min Max Min Max Min Unit Max ts(H) ts(L) Setup Time, HIGH or LOW Dn to E 4.0 4.0 5.0 5.0 4.0 4.0 ns th(H) th(L) Hold Time, HIGH or LOW Dn to E 2.0 2.0 2.0 2.0 2.0 2.0 ns ts(H) ts(L) Setup Time, HIGH or LOW A to E(a) 4.0 4.0 4.0 4.0 4.0 4.0 ns th(H) th(L) Hold Time HIGH or LOW A to E(b) 0 0 0 0 0 0 ns tW E Pulse Width 4.0 4.0 4.0 ns tW MR Pulse Width 4.0 4.0 4.0 ns NOTES: 1. The Address to Enable setup time is the time before the HIGH-to-LOW Enable transition that the Address must be stable so that the correct latch is 1. addressed and the other latches are not affected. 2. The Address to Enable hold time is the time after the LOW-to-HIGH Enable transition that the Address must be stable so that the correct latch is addressed 1. and the other latches are not affected. FAST AND LS TTL DATA 4-126