TI SN74AHC05N

SN54AHC05, SN74AHC05
HEX INVERTERS
WITH OPEN-DRAIN OUTPUTS
SCLS357F – MAY 1997 – REVISED JANUARY 2000
D
D
D
D
EPIC  (Enhanced-Performance Implanted
CMOS) Process
Operating Range 2-V to 5.5-V VCC
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
Package Options Include Plastic
Small-Outline (D), Shrink Small-Outline
(DB), Thin Very Small-Outline (DGV), Thin
Shrink Small-Outline (PW), and Ceramic
Flat (W) Packages, Ceramic Chip Carriers
(FK), and Standard Plastic (N) and Ceramic
(J) DIPs
SN54AHC05 . . . J OR W PACKAGE
SN74AHC05 . . . D, DB, DGV, N, OR PW PACKAGE
(TOP VIEW)
1A
1Y
2A
2Y
3A
3Y
GND
1
14
2
13
3
12
4
11
5
10
6
9
7
8
VCC
6A
6Y
5A
5Y
4A
4Y
SN54AHC05 . . . FK PACKAGE
(TOP VIEW)
1Y
1A
NC
VCC
6A
D
2A
NC
2Y
NC
3A
description
The ’AHC05 devices contain six independent
inverters. These devices perform the Boolean
function Y = A.
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
6Y
NC
5A
NC
5Y
3Y
GND
NC
4Y
4A
The open-drain outputs require pullup resistors to
perform correctly. They can be connected to other
open-drain outputs to implement active-low
wired-OR or active-high wired-AND functions.
4
NC – No internal connection
The SN54AHC05 is characterized for operation
over the full military temperature range of –55°C
to 125°C. The SN74AHC05 is characterized for
operation from –40°C to 85°C.
FUNCTION TABLE
(each inverter)
INPUT
A
OUTPUT
Y
H
L
L
H
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright  2000, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN54AHC05, SN74AHC05
HEX INVERTERS
WITH OPEN-DRAIN OUTPUTS
SCLS357F – MAY 1997 – REVISED JANUARY 2000
logic symbol†
1A
2A
3A
4A
5A
6A
1
2
1
3
4
5
6
9
8
11
10
13
12
1Y
2Y
3Y
4Y
5Y
6Y
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, DB, DGV, J, N, PW, and W packages.
logic diagram, each inverter (positive logic)
A
Y
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
2
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SN54AHC05, SN74AHC05
HEX INVERTERS
WITH OPEN-DRAIN OUTPUTS
SCLS357F – MAY 1997 – REVISED JANUARY 2000
recommended operating conditions (see Note 3)
SN54AHC05
VCC
Supply voltage
VIH
VCC = 2 V
VCC = 3 V
High-level input voltage
Low-level input voltage
VI
VO
5.5
2
5.5
UNIT
V
1.5
2.1
3.85
V
0.5
0.9
0.9
1.65
1.65
V
0
5.5
0
5.5
V
0
VCC
50
0
VCC
50
mA
VCC = 5 V ± 0.5 V
VCC = 3.3 V ± 0.3 V
Input transition rise or fall rate
MAX
2.1
VCC = 2 V
VCC = 3.3 V ± 0.3 V
Low-level output current
MIN
3.85
VCC = 3 V
VCC = 5.5 V
Output voltage
∆t/∆v
2
SN74AHC05
0.5
Input voltage
IOL
MAX
1.5
VCC = 5.5 V
VCC = 2 V
VIL
MIN
VCC = 5 V ± 0.5 V
4
4
8
8
100
100
20
20
V
mA
ns/V
TA
Operating free-air temperature
–55
125
–40
85
°C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
IOL = 50 mA
VOL
IOL = 4 mA
II
ICC
IOL = 8 mA
VI = VCC or GND
VI = VCC or GND,
VI = VCC or GND
IO = 0
MIN
TA = 25°C
TYP
MAX
SN54AHC05
MIN
MAX
SN74AHC05
MIN
MAX
2V
0.1
0.1
0.1
3V
0.1
0.1
0.1
4.5 V
0.1
0.1
0.1
UNIT
V
3V
0.36
0.5
0.44
4.5 V
0.36
0.5
0.44
0 V to 5.5 V
±0.1
±1*
±1
mA
2
20
20
mA
10
pF
5.5 V
Ci
5V
2.5
10
* On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V.
switching characteristics over recommended operating free-air temperature range,
VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
tPLZ
tPZL
A
Y
CL = 15 pF
tPLZ
tPZL
A
Y
CL = 50 pF
MIN
TA = 25°C
TYP
MAX
SN54AHC05
SN74AHC05
MIN
MAX
MIN
MAX
2.9**
7.1**
1**
8.5**
1
8.5
4**
7.1**
1**
8.5**
1
8.5
4.7
10.6
1
12
1
12
5.8
10.6
1
12
1
12
UNIT
ns
ns
** On products compliant to MIL-PRF-38535, this parameter is not production tested.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
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SN54AHC05, SN74AHC05
HEX INVERTERS
WITH OPEN-DRAIN OUTPUTS
SCLS357F – MAY 1997 – REVISED JANUARY 2000
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
tPLZ
tPZL
A
Y
CL = 15 pF
tPLZ
tPZL
A
Y
CL = 50 pF
MIN
TA = 25°C
TYP
MAX
SN54AHC05
SN74AHC05
MIN
MAX
MIN
MAX
2.2*
5.5*
1*
6.5*
1
6.5
2.9*
5.5*
1*
6.5*
1
6.5
3.4
7.5
1
8.5
1
8.5
4.2
7.5
1
8.5
1
8.5
UNIT
ns
ns
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Power dissipation capacitance
No load,
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
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f = 1 MHz
TYP
3
UNIT
pF
SN54AHC05, SN74AHC05
HEX INVERTERS
WITH OPEN-DRAIN OUTPUTS
SCLS357F – MAY 1997 – REVISED JANUARY 2000
PARAMETER MEASUREMENT INFORMATION
RL = 1 kΩ
From Output
Under Test
Test
Point
From Output
Under Test
S1
VCC
Open
TEST
GND
CL
(see Note A)
CL
(see Note A)
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
Open
VCC
GND
VCC
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
VCC
50% VCC
Timing Input
tw
tsu
VCC
Input
50% VCC
50% VCC
0V
th
VCC
50% VCC
Data Input
50% VCC
0V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VCC
50% VCC
Input
50% VCC
0V
tPLH
In-Phase
Output
tPHL
50% VCC
tPHL
Out-of-Phase
Output
VOH
50% VCC
VOL
Output
Waveform 1
S1 at VCC
(see Note B)
VOH
50% VCC
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
50% VCC
50% VCC
0V
tPZL
tPLZ
≈VCC
50% VCC
tPZH
tPLH
50% VCC
VCC
Output
Control
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.3 V
VOL
tPHZ
50% VCC
VOH – 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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Copyright  2000, Texas Instruments Incorporated