SN54LV14, SN74LV14 HEX SCHMITT-TRIGGER INVERTERS SCLS187C – FEBRUARY 1993 – REVISED FEBRUARY 1998 D D D D D EPIC (Enhanced-Performance Implanted CMOS) 2-µ Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC, TA = 25°C Typical VOHV (Output VOH Undershoot) > 2 V at VCC, TA = 25°C ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 250 mA JESD 17 Package Options Include Plastic Small-Outline (D), Shrink Small-Outline (DB), Thin Shrink Small-Outline (PW), Ceramic Flat (W) Packages, Chip Carriers (FK), and (J) 300-mil DIPs SN54LV14 . . . J OR W PACKAGE SN74LV14 . . . D, DB, OR PW PACKAGE (TOP VIEW) 1A 1Y 2A 2Y 3A 3Y GND 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 6A 6Y 5A 5Y 4A 4Y SN54LV14 . . . FK PACKAGE (TOP VIEW) 1Y 1A NC VCC 6A D 2A NC 2Y NC 3A description These hex Schmitt-trigger inverters are designed for 2.7-V to 5.5-V VCC operation. 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 6Y NC 5A NC 5Y 3Y GND NC 4Y 4A The ’LV14 devices contain six independent inverters. These devices perform the Boolean function Y = A. 4 NC – No internal connection The SN54LV14 is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74LV14 is characterized for operation from –40°C to 85°C. FUNCTION TABLE (each inverter) INPUT A OUTPUT Y H L L H Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments Incorporated. Copyright 1998, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54LV14, SN74LV14 HEX SCHMITT-TRIGGER INVERTERS SCLS187C – FEBRUARY 1993 – REVISED FEBRUARY 1998 logic symbol† 1A 2A 3A 4A 5A 6A logic diagram (positive logic) 1 2 3 4 5 6 9 8 11 10 13 12 1Y A Y 2Y 3Y 4Y 5Y 6Y † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, DB, J, PW, and W packages. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Package thermal impedance, θJA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/W DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C ‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stressratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. This value is limited to 7 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51. recommended operating conditions (see Note 4) VCC Supply voltage SN54LV14 SN74LV14 MIN MAX MIN MAX 2.7 5.5 2.7 5.5 VIH High level input voltage High-level VCC = 2.7 V to 3.6 V VCC = 4.5 V to 5.5 V 2.4 2.4 3.55 3.55 VIL Low level input voltage Low-level VCC = 2.7 V to 3.6 V VCC = 4.5 V to 5.5 V VI VO Input voltage 0 Output voltage 0 IOH High level output current High-level VCC = 2.7 V to 3.6 V VCC = 4.5 V to 5.5 V IOL Low level output current Low-level VCC = 2.7 V to 3.6 V VCC = 4.5 V to 5.5 V 0.4 0.4 1.25 0 0 V V 1.25 VCC VCC UNIT VCC VCC –6 –6 –12 –12 6 6 12 12 V V V mA mA TA Operating free-air temperature –55 125 –40 85 °C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54LV14, SN74LV14 HEX SCHMITT-TRIGGER INVERTERS SCLS187C – FEBRUARY 1993 – REVISED FEBRUARY 1998 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VT+ Positive-going threshold VT– Negative-going threshold ∆VT Hysteresis (VT+ – VT– T ) VOH VOL SN54LV14 VCC MIN TYP SN74LV14 MAX MIN TYP 2.7 V 1 2 1 2 3V 1.2 2.2 1.2 2.2 3.6 V 1.5 2.4 1.5 2.4 4.5 V 1.7 3.2 1.7 3.2 5.5 V 2.1 3.9 2.1 3.9 2.7 V 0.4 1.4 0.4 1.4 3V 0.6 1.5 0.6 1.5 3.6 V 0.8 1.8 0.8 1.8 4.5 V 0.9 2.25 0.9 2.25 5.5 V 1.1 2.75 1.1 2.75 2.7 V 0.3 1.1 0.3 1.1 3V 0.4 1.2 0.4 1.2 3.6 V 0.4 1.2 0.4 1.2 4.5 V 0.4 1.4 0.4 1.4 1.5 0.5 1.5 5.5 V 0.5 IOH = –100 µA IOH = –6 mA 2.7 V to 5.5 V VCC – 0.2 2.4 VCC – 0.2 2.4 IOH = –12 mA IOL = 100 µA 4.5 V 3.6 3.6 3V 2.7 V to 5.5 V IOL = 6 mA IOL = 12 mA II VI = VCC or GND ICC VI = VCC or GND, GND nICC One input at VCC – 0.6 V, Other inputs at VCC or GND Ci VI = VCC or GND IO = 0 MAX UNIT V V V V 0.2 0.2 3V 0.4 0.4 4.5 V 0.55 0.55 3.6 V ±1 ±1 5.5 V ±1 ±1 3.6 V 20 20 5.5 V 20 20 3 V to 3.6 V 500 500 3.3 V 2.5 2.5 5V 3 3 V µA µA µA pF switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) SN54LV14 PARAMETER FROM (INPUT) TO (OUTPUT) tpd A Y VCC = 5 V ± 0.5 V MIN TYP MAX 8 18 VCC = 3.3 V ± 0.3 V MIN TYP MAX 12 22 VCC = 2.7 V MIN MAX 25 UNIT ns PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54LV14, SN74LV14 HEX SCHMITT-TRIGGER INVERTERS SCLS187C – FEBRUARY 1993 – REVISED FEBRUARY 1998 switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) SN74LV14 PARAMETER FROM (INPUT) TO (OUTPUT) tpd A Y VCC = 5 V ± 0.5 V MIN TYP MAX 8 VCC = 3.3 V ± 0.3 V MIN TYP MAX 18 12 VCC = 2.7 V MIN MAX 22 25 UNIT ns operating characteristics, TA = 25°C PARAMETER Cpd 4 TEST CONDITIONS Power dissipation dissi ation ca capacitance acitance per er inverter POST OFFICE BOX 655303 CL = 50 pF F, • DALLAS, TEXAS 75265 VCC 3.3 V TYP 5V 24 UNIT 22 f = 10 MHz pF F SN54LV14, SN74LV14 HEX SCHMITT-TRIGGER INVERTERS SCLS187C – FEBRUARY 1993 – REVISED FEBRUARY 1998 PARAMETER MEASUREMENT INFORMATION S1 1 kΩ From Output Under Test Vz Open GND CL = 50 pF (see Note A) TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Vz GND 1 kΩ WAVEFORM CONDITION Vm Vi Vz LOAD CIRCUIT VCC = 4.5 V to 5.5 V 0.5 × VCC VCC 2 × VCC VCC = 2.7 V to 3.6 V 1.5 V 2.7 V 6V Vi Vm Timing Input 0V tw tsu Vi Input Vm th Vi Vm Vm Data Input Vm 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Vi Vm Input 0V VOH Vm Output Vm VOL Output VOH Vm 0V Vm VOL tPLZ Output Waveform 1 S1 at Vz (see Note B) tPLH tPHL Vm Vm tPZL tPHL tPLH Vi Output Control Vm Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Vm tPZH 0.5 × Vz VOL + 0.3 V VOL tPHZ Vm VOH – 0.3 V VOH [0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 1. 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